From b87b7a99c5d706f5ff756744778e1725640ae334 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 29 Sep 2021 20:21:46 -0700 Subject: [PATCH] [Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators --- openfpga/src/base/openfpga_build_fabric.cpp | 1 + openfpga/src/base/openfpga_context.h | 8 ++++++++ openfpga/src/fabric/build_device_module.cpp | 2 ++ openfpga/src/fabric/build_device_module.h | 1 + openfpga/src/fabric/build_top_module.cpp | 3 ++- openfpga/src/fabric/build_top_module.h | 2 ++ openfpga/src/fabric/build_top_module_memory.cpp | 6 +++++- openfpga/src/fabric/build_top_module_memory.h | 2 ++ openfpga/src/fabric/build_top_module_memory_bank.cpp | 11 +++++------ openfpga/src/fabric/build_top_module_memory_bank.h | 3 +++ .../src/fabric/memory_bank_shift_register_banks.h | 1 + 11 files changed, 32 insertions(+), 8 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric.cpp b/openfpga/src/base/openfpga_build_fabric.cpp index 146520624..1caac7342 100644 --- a/openfpga/src/base/openfpga_build_fabric.cpp +++ b/openfpga/src/base/openfpga_build_fabric.cpp @@ -103,6 +103,7 @@ int build_fabric(OpenfpgaContext& openfpga_ctx, curr_status = build_device_module_graph(openfpga_ctx.mutable_module_graph(), openfpga_ctx.mutable_decoder_lib(), + openfpga_ctx.mutable_blwl_shift_register_banks(), const_cast(openfpga_ctx), g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view), diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index c85bf8607..dbb611fe6 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -23,6 +23,7 @@ #include "device_rr_gsb.h" #include "io_location_map.h" #include "fabric_global_port_info.h" +#include "memory_bank_shift_register_banks.h" /******************************************************************** * This file includes the declaration of the date structure @@ -65,6 +66,7 @@ class OpenfpgaContext : public Context { const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; } const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; } const openfpga::DecoderLibrary& decoder_lib() const { return decoder_lib_; } + const std::array& blwl_shift_register_banks() { return blwl_sr_banks_; } const openfpga::TileDirect& tile_direct() const { return tile_direct_; } const openfpga::ModuleManager& module_graph() const { return module_graph_; } const openfpga::FlowManager& flow_manager() const { return flow_manager_; } @@ -87,6 +89,7 @@ class OpenfpgaContext : public Context { openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; } openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; } openfpga::DecoderLibrary& mutable_decoder_lib() { return decoder_lib_; } + std::array& mutable_blwl_shift_register_banks() { return blwl_sr_banks_; } openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; } openfpga::ModuleManager& mutable_module_graph() { return module_graph_; } openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; } @@ -132,6 +135,11 @@ class OpenfpgaContext : public Context { /* Inner/inter-column/row tile direct connections */ openfpga::TileDirect tile_direct_; + /* Library of shift register banks that control BLs and WLs + * @note Only used when memory bank is used as configuration protocol + */ + std::array blwl_sr_banks_; + /* Fabric module graph */ openfpga::ModuleManager module_graph_; openfpga::IoLocationMap io_location_map_; diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 4b39a5cee..3541616fc 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -31,6 +31,7 @@ namespace openfpga { *******************************************************************/ int build_device_module_graph(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx, const bool& frame_view, @@ -112,6 +113,7 @@ int build_device_module_graph(ModuleManager& module_manager, /* Build FPGA fabric top-level module */ status = build_top_module(module_manager, decoder_lib, + blwl_sr_banks, openfpga_ctx.arch().circuit_lib, openfpga_ctx.vpr_device_annotation(), vpr_device_ctx.grid, diff --git a/openfpga/src/fabric/build_device_module.h b/openfpga/src/fabric/build_device_module.h index 5d3215bb4..1cde17ba7 100644 --- a/openfpga/src/fabric/build_device_module.h +++ b/openfpga/src/fabric/build_device_module.h @@ -17,6 +17,7 @@ namespace openfpga { int build_device_module_graph(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx, const bool& frame_view, diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 4fc4c396f..c5b3aee45 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -283,6 +283,7 @@ vtr::Matrix add_top_module_connection_block_instances(ModuleManager& mod *******************************************************************/ int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, @@ -414,7 +415,7 @@ int build_top_module(ModuleManager& module_manager, * This is a one-shot addition that covers all the memory modules in this pb module! */ if (0 < module_manager.configurable_children(top_module).size()) { - add_top_module_nets_memory_config_bus(module_manager, decoder_lib, + add_top_module_nets_memory_config_bus(module_manager, decoder_lib, blwl_sr_banks, top_module, circuit_lib, config_protocol, circuit_lib.design_tech_type(sram_model), diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index d7e90a09f..3ddaea09a 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -19,6 +19,7 @@ #include "config_protocol.h" #include "module_manager.h" #include "fabric_key.h" +#include "memory_bank_shift_register_banks.h" /******************************************************************** * Function declaration @@ -29,6 +30,7 @@ namespace openfpga { int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 42debe24f..e48167970 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -1735,6 +1735,7 @@ void add_top_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_mana static void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const ModuleId& parent_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, @@ -1754,7 +1755,8 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module, num_config_bits); break; case CONFIG_MEM_QL_MEMORY_BANK: - add_top_module_nets_cmos_ql_memory_bank_config_bus(module_manager, decoder_lib, parent_module, circuit_lib, config_protocol, num_config_bits); + add_top_module_nets_cmos_ql_memory_bank_config_bus(module_manager, decoder_lib, blwl_sr_banks, + parent_module, circuit_lib, config_protocol, num_config_bits); break; case CONFIG_MEM_FRAME_BASED: add_top_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module, num_config_bits); @@ -1800,6 +1802,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager, *******************************************************************/ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const ModuleId& parent_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, @@ -1811,6 +1814,7 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, switch (mem_tech) { case CIRCUIT_MODEL_DESIGN_CMOS: add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib, + blwl_sr_banks, parent_module, circuit_lib, config_protocol, diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index 7b6f9aa10..4819a56f6 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -18,6 +18,7 @@ #include "device_rr_gsb.h" #include "fabric_key.h" #include "config_protocol.h" +#include "memory_bank_shift_register_banks.h" #include "build_top_module_memory_utils.h" /******************************************************************** @@ -64,6 +65,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager, void add_top_module_nets_memory_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const ModuleId& parent_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp index db82870ad..dd2bdf29b 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.cpp +++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp @@ -1272,6 +1272,7 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan **********************************************************************/ static void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(ModuleManager& module_manager, + MemoryBankShiftRegisterBanks& sr_banks, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) { @@ -1298,8 +1299,6 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module sr_size); } - /* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/ - MemoryBankShiftRegisterBanks sr_banks; /* Instanciate the shift register chains in the top-level module */ sr_banks.resize_regions(module_manager.regions(top_module).size()); for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { @@ -1360,6 +1359,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module **********************************************************************/ static void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(ModuleManager& module_manager, + MemoryBankShiftRegisterBanks& sr_banks, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol) { @@ -1385,8 +1385,6 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module sr_size); } - /* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/ - MemoryBankShiftRegisterBanks sr_banks; /* Instanciate the shift register chains in the top-level module */ sr_banks.resize_regions(module_manager.regions(top_module).size()); for (const ConfigRegionId& config_region : module_manager.regions(top_module)) { @@ -1458,6 +1456,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module ********************************************************************/ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, @@ -1475,7 +1474,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma break; } case BLWL_PROTOCOL_SHIFT_REGISTER: { - add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(module_manager, top_module, circuit_lib, config_protocol); + add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(module_manager, blwl_sr_banks[0], top_module, circuit_lib, config_protocol); break; } default: { @@ -1494,7 +1493,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma break; } case BLWL_PROTOCOL_SHIFT_REGISTER: { - add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(module_manager, top_module, circuit_lib, config_protocol); + add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(module_manager, blwl_sr_banks[1], top_module, circuit_lib, config_protocol); break; } default: { diff --git a/openfpga/src/fabric/build_top_module_memory_bank.h b/openfpga/src/fabric/build_top_module_memory_bank.h index 3d6acc255..d3a3d2f77 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.h +++ b/openfpga/src/fabric/build_top_module_memory_bank.h @@ -7,12 +7,14 @@ #include #include +#include #include "vtr_vector.h" #include "vtr_ndmatrix.h" #include "module_manager.h" #include "config_protocol.h" #include "circuit_library.h" #include "decoder_library.h" +#include "memory_bank_shift_register_banks.h" #include "build_top_module_memory_utils.h" /******************************************************************** @@ -24,6 +26,7 @@ namespace openfpga { void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + std::array& blwl_sr_banks, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, diff --git a/openfpga/src/fabric/memory_bank_shift_register_banks.h b/openfpga/src/fabric/memory_bank_shift_register_banks.h index 83d7c517d..262508bad 100644 --- a/openfpga/src/fabric/memory_bank_shift_register_banks.h +++ b/openfpga/src/fabric/memory_bank_shift_register_banks.h @@ -59,6 +59,7 @@ class MemoryBankShiftRegisterBanks { bool valid_region_id(const ConfigRegionId& region) const; private: /* Internal data */ + /* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/ vtr::vector, std::vector>>> sr_instance_info_; };