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[Lib] Remove unused data storage from repack design constraints

This commit is contained in:
tangxifan 2021-01-16 21:14:52 -07:00
parent fa67517349
commit b86adabe69
5 changed files with 4 additions and 43 deletions
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8
libopenfpga/librepackdc/dc_example/repack_design_constraint_example.xml
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@ -1,7 +1,7 @@
<repack_pin_constraints> <repack_pin_constraints>
<pin_constraint tile="clb" x="1" y="1" pin="clk[0]" net="clk0"/> <pin_constraint tile="clb" pin="clk[0]" net="clk0"/>
<pin_constraint tile="clb" x="2" y="2" pin="clk[1]" net="clk1"/> <pin_constraint tile="clb" pin="clk[1]" net="clk1"/>
<pin_constraint tile="clb" x="-1" y="1" pin="clk[2]" net="OPEN"/> <pin_constraint tile="clb" pin="clk[2]" net="OPEN"/>
<pin_constraint tile="clb" x="1" y="-1" pin="clk[3]" net="OPEN"/> <pin_constraint tile="clb" pin="clk[3]" net="OPEN"/>
</repack_pin_constraints> </repack_pin_constraints>

5
libopenfpga/librepackdc/src/read_xml_repack_design_constraints.cpp
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@ -41,11 +41,6 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint,
repack_design_constraints.set_tile(design_constraint_id, repack_design_constraints.set_tile(design_constraint_id,
get_attribute(xml_pin_constraint, "tile", loc_data).as_string()); get_attribute(xml_pin_constraint, "tile", loc_data).as_string());
repack_design_constraints.set_tile_coordinate(design_constraint_id,
vtr::Point<size_t>(get_attribute(xml_pin_constraint, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1),
get_attribute(xml_pin_constraint, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1)));
openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string()); openfpga::PortParser port_parser(get_attribute(xml_pin_constraint, "pin", loc_data).as_string());
repack_design_constraints.set_pin(design_constraint_id, repack_design_constraints.set_pin(design_constraint_id,

19
libopenfpga/librepackdc/src/repack_design_constraints.cpp
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@ -38,13 +38,6 @@ std::string RepackDesignConstraints::tile(const RepackDesignConstraintId& repack
return repack_design_constraint_tiles_[repack_design_constraint_id]; return repack_design_constraint_tiles_[repack_design_constraint_id];
} }
vtr::Point<size_t> RepackDesignConstraints::tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const {
/* validate the design_constraint_id */
VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id));
return vtr::Point<size_t>(repack_design_constraint_tiles_x_[repack_design_constraint_id],
repack_design_constraint_tiles_y_[repack_design_constraint_id]);
}
openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const { openfpga::BasicPort RepackDesignConstraints::pin(const RepackDesignConstraintId& repack_design_constraint_id) const {
/* validate the design_constraint_id */ /* validate the design_constraint_id */
VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id)); VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id));
@ -68,8 +61,6 @@ void RepackDesignConstraints::reserve_design_constraints(const size_t& num_desig
repack_design_constraint_ids_.reserve(num_design_constraints); repack_design_constraint_ids_.reserve(num_design_constraints);
repack_design_constraint_types_.reserve(num_design_constraints); repack_design_constraint_types_.reserve(num_design_constraints);
repack_design_constraint_tiles_.reserve(num_design_constraints); repack_design_constraint_tiles_.reserve(num_design_constraints);
repack_design_constraint_tiles_x_.reserve(num_design_constraints);
repack_design_constraint_tiles_y_.reserve(num_design_constraints);
repack_design_constraint_pins_.reserve(num_design_constraints); repack_design_constraint_pins_.reserve(num_design_constraints);
repack_design_constraint_nets_.reserve(num_design_constraints); repack_design_constraint_nets_.reserve(num_design_constraints);
} }
@ -81,8 +72,6 @@ RepackDesignConstraintId RepackDesignConstraints::create_design_constraint(const
repack_design_constraint_ids_.push_back(repack_design_constraint_id); repack_design_constraint_ids_.push_back(repack_design_constraint_id);
repack_design_constraint_types_.push_back(repack_design_constraint_type); repack_design_constraint_types_.push_back(repack_design_constraint_type);
repack_design_constraint_tiles_.emplace_back(); repack_design_constraint_tiles_.emplace_back();
repack_design_constraint_tiles_x_.push_back(size_t(-1));
repack_design_constraint_tiles_y_.push_back(size_t(-1));
repack_design_constraint_pins_.emplace_back(); repack_design_constraint_pins_.emplace_back();
repack_design_constraint_nets_.emplace_back(); repack_design_constraint_nets_.emplace_back();
@ -96,14 +85,6 @@ void RepackDesignConstraints::set_tile(const RepackDesignConstraintId& repack_de
repack_design_constraint_tiles_[repack_design_constraint_id] = tile; repack_design_constraint_tiles_[repack_design_constraint_id] = tile;
} }
void RepackDesignConstraints::set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id,
const vtr::Point<size_t>& tile_coordinate) {
/* validate the design_constraint_id */
VTR_ASSERT(valid_design_constraint_id(repack_design_constraint_id));
repack_design_constraint_tiles_x_[repack_design_constraint_id] = tile_coordinate.x();
repack_design_constraint_tiles_y_[repack_design_constraint_id] = tile_coordinate.y();
}
void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id, void RepackDesignConstraints::set_pin(const RepackDesignConstraintId& repack_design_constraint_id,
const openfpga::BasicPort& pin) { const openfpga::BasicPort& pin) {
/* validate the design_constraint_id */ /* validate the design_constraint_id */

13
libopenfpga/librepackdc/src/repack_design_constraints.h
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@ -52,9 +52,6 @@ class RepackDesignConstraints {
/* Get the tile name to be constrained */ /* Get the tile name to be constrained */
std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const; std::string tile(const RepackDesignConstraintId& repack_design_constraint_id) const;
/* Get the tile coordinate to be constrained */
vtr::Point<size_t> tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id) const;
/* Get the pin to be constrained */ /* Get the pin to be constrained */
openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const; openfpga::BasicPort pin(const RepackDesignConstraintId& repack_design_constraint_id) const;
@ -76,10 +73,6 @@ class RepackDesignConstraints {
void set_tile(const RepackDesignConstraintId& repack_design_constraint_id, void set_tile(const RepackDesignConstraintId& repack_design_constraint_id,
const std::string& tile); const std::string& tile);
/* Set the tile coordinate to be constrained */
void set_tile_coordinate(const RepackDesignConstraintId& repack_design_constraint_id,
const vtr::Point<size_t>& tile_coordinate);
/* Set the pin to be constrained */ /* Set the pin to be constrained */
void set_pin(const RepackDesignConstraintId& repack_design_constraint_id, void set_pin(const RepackDesignConstraintId& repack_design_constraint_id,
const openfpga::BasicPort& pin); const openfpga::BasicPort& pin);
@ -100,12 +93,6 @@ class RepackDesignConstraints {
/* Tiles to constraint */ /* Tiles to constraint */
vtr::vector<RepackDesignConstraintId, std::string> repack_design_constraint_tiles_; vtr::vector<RepackDesignConstraintId, std::string> repack_design_constraint_tiles_;
/* Coordinates of tiles to constraint
* Avoid using an object but a flatten way to be memory efficient
*/
vtr::vector<RepackDesignConstraintId, size_t> repack_design_constraint_tiles_x_;
vtr::vector<RepackDesignConstraintId, size_t> repack_design_constraint_tiles_y_;
/* Pins to constraint */ /* Pins to constraint */
vtr::vector<RepackDesignConstraintId, openfpga::BasicPort> repack_design_constraint_pins_; vtr::vector<RepackDesignConstraintId, openfpga::BasicPort> repack_design_constraint_pins_;

2
libopenfpga/librepackdc/src/write_xml_repack_design_constraints.cpp
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@ -43,8 +43,6 @@ int write_xml_pin_constraint(std::fstream& fp,
} }
write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str()); write_xml_attribute(fp, "tile", repack_design_constraints.tile(design_constraint).c_str());
write_xml_attribute(fp, "x", repack_design_constraints.tile_coordinate(design_constraint).x());
write_xml_attribute(fp, "y", repack_design_constraints.tile_coordinate(design_constraint).y());
write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str()); write_xml_attribute(fp, "pin", generate_xml_port_name(repack_design_constraints.pin(design_constraint)).c_str());
write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str()); write_xml_attribute(fp, "net", repack_design_constraints.net(design_constraint).c_str());