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OpenFPGA
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Fixed parameter ys_rewrite_params name bug

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ganeshgore 2021-03-08 10:34:39 -07:00 committed by GitHub
parent 52de55e7eb
commit b860722893
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1 changed files with 1 additions and 1 deletions
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openfpga_flow/scripts/run_fpga_flow.py
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@ -711,7 +711,7 @@ def run_rewrite_verilog():
ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1]
tmpl = Template(open(args.ys_rewrite_tmpl, encoding='utf-8').read())
with open("yosys_rewrite.ys", 'w') as archfile:
archfile.write(tmpl.safe_substitute(ys_params))
archfile.write(tmpl.safe_substitute(ys_rewrite_params))
run_command("Run yosys", "yosys_rewrite_output.log",
[cad_tools["yosys_path"], 'yosys_rewrite.ys'])