From b8559249dc33028fce9dac39ce7f3e8e2c94424e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 25 Nov 2020 22:23:27 -0700 Subject: [PATCH] [Test] Bug fix in task configuration file --- .../lut_design/frac_native_lut4/config/task.conf | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf index 6249f1f48..51f41156e 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_native_lut4/config/task.conf @@ -28,9 +28,9 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40n bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif [SYNTHESIS_PARAM] -bench2_top = and2_or2 -bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act -bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v +bench0_top = and2_or2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=