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fix a bug for supporting default circuit_model of LUTs and FFs

This commit is contained in:
tangxifan 2019-01-10 15:10:05 -07:00
parent 9c8444da43
commit b8187bbca5
2 changed files with 33 additions and 5 deletions
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26
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_setup.c
View File

@ -168,7 +168,33 @@ void match_pb_types_spice_model_rec(t_pb_type* cur_pb_type,
/* Map pb_type ports to SPICE model ports*/ /* Map pb_type ports to SPICE model ports*/
map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model); map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model);
return; return;
} else {
/* Find default spice model if this is a primitive block */
if (LUT_CLASS == cur_pb_type->class_type) {
cur_pb_type->spice_model = get_default_spice_model(SPICE_MODEL_LUT, num_spice_model, spice_models);
/* Complete the name */
cur_pb_type->spice_model_name = my_strdup(cur_pb_type->spice_model->name);
if (NULL == cur_pb_type->spice_model) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name);
exit(1);
} }
/* Map pb_type ports to SPICE model ports*/
map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model);
return;
} else if (LATCH_CLASS == cur_pb_type->class_type) {
cur_pb_type->spice_model = get_default_spice_model(SPICE_MODEL_FF, num_spice_model, spice_models);
/* Complete the name */
cur_pb_type->spice_model_name = my_strdup(cur_pb_type->spice_model->name);
if (NULL == cur_pb_type->spice_model) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,LINE[%d]) Fail to find a defined SPICE model called %s, in pb_type(%s)!\n",__FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name);
exit(1);
}
/* Map pb_type ports to SPICE model ports*/
map_pb_type_port_to_spice_model_ports(cur_pb_type,cur_pb_type->spice_model);
return;
}
}
/* Traversal the hierarchy*/ /* Traversal the hierarchy*/
for (imode = 0; imode < cur_pb_type->num_modes; imode++) { for (imode = 0; imode < cur_pb_type->num_modes; imode++) {
/* Task 1: Find the interconnections and match the spice_model */ /* Task 1: Find the interconnections and match the spice_model */

8
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c
View File

@ -5900,9 +5900,9 @@ int get_pb_graph_node_wired_lut_logical_block_index(t_pb_graph_node* cur_pb_grap
} }
} }
/* Make sure we only have 1 used input pin */ /* Make sure we only have 1 used input pin */
//if (1 != num_used_lut_input_pins) { if (1 != num_used_lut_input_pins) {
assert (0 < num_used_lut_input_pins); assert (-1 < num_used_lut_input_pins);
//} }
/* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); */ /* vpr_printf(TIO_MESSAGE_INFO, "Wired LUT output vpack_net_num is %d\n", lut_output_vpack_net_num); */
@ -6986,7 +6986,9 @@ void stats_mux_spice_model_pb_type_rec(t_llist** muxes_head,
continue; continue;
} }
interc_spice_model = cur_pb_type->modes[imode].interconnect[jinterc].spice_model; interc_spice_model = cur_pb_type->modes[imode].interconnect[jinterc].spice_model;
if (NULL == interc_spice_model) {
assert(NULL != interc_spice_model); assert(NULL != interc_spice_model);
}
check_and_add_mux_to_linked_list(muxes_head, check_and_add_mux_to_linked_list(muxes_head,
cur_pb_type->modes[imode].interconnect[jinterc].fan_in, cur_pb_type->modes[imode].interconnect[jinterc].fan_in,
interc_spice_model); interc_spice_model);