Merge pull request #792 from lnis-uofu/io_indexing
Now I/O indexing follows a natural way (clockwise) throughout the fabric.
This commit is contained in:
tangxifan
GitHub
commit
b7b82804ff
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@ -51,7 +51,6 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager,
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size_t grid_instance = module_manager.num_instance(top_module, grid_module);
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/* Add the module to top_module */
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module_manager.add_child_module(top_module, grid_module, false);
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module_manager.add_io_child(top_module, grid_module, grid_instance, vtr::Point<int>(grid_coord.x(), grid_coord.y()));
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/* Set an unique name to the instance
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* Note: it is your risk to gurantee the name is unique!
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*/
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@ -276,6 +275,118 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
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return cb_instance_ids;
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}
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/********************************************************************
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* Add the I/O children to the top-level module, which impacts the I/O indexing
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* This is the default function to build the I/O sequence/indexing
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* The I/O children is added in a maze shape
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* The function supports I/Os in the center of grids, starting from the bottom-left corner and ending at the center
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*
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* +----------------------+
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* |+--------------------+|
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* ||+------------------+||
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* |||+----------------+|||
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* ||||+-------------->||||
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* ||||+---------------+|||
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* |||+-----------------+||
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* ||+-------------------+|
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* |+---------------------+
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* ^
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* io[0]
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*******************************************************************/
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static
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void add_top_module_io_children(ModuleManager& module_manager,
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const ModuleId& top_module,
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const DeviceGrid& grids,
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const vtr::Matrix<size_t>& grid_instance_ids) {
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/* Create the coordinate range for the perimeter I/Os of FPGA fabric */
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std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates = generate_perimeter_grid_coordinates( grids);
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for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
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for (const vtr::Point<size_t>& io_coord : io_coordinates[io_side]) {
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/* Bypass EMPTY grid */
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if (true == is_empty_type(grids[io_coord.x()][io_coord.y()].type)) {
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continue;
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}
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/* Skip width, height > 1 tiles (mostly heterogeneous blocks) */
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if ( (0 < grids[io_coord.x()][io_coord.y()].width_offset)
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|| (0 < grids[io_coord.x()][io_coord.y()].height_offset)) {
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continue;
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}
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/* Find the module name for this type of grid */
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t_physical_tile_type_ptr grid_type = grids[io_coord.x()][io_coord.y()].type;
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), io_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Add a I/O children to top_module*/
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module_manager.add_io_child(top_module, grid_module, grid_instance_ids[io_coord.x()][io_coord.y()], vtr::Point<int>(io_coord.x(), io_coord.y()));
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}
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}
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/* Walk through the center grids */
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size_t xmin = 1;
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size_t xmax = grids.width() - 2;
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size_t ymin = 1;
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size_t ymax = grids.height() - 2;
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std::vector<vtr::Point<size_t>> coords;
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while (xmin < xmax && ymin < ymax) {
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for (size_t iy = ymin; iy < ymax + 1; iy++) {
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coords.push_back(vtr::Point<size_t>(xmin, iy));
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}
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for (size_t ix = xmin + 1; ix < xmax + 1; ix++) {
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coords.push_back(vtr::Point<size_t>(ix, ymax));
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}
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for (size_t iy = ymax - 1; iy > ymin; iy--) {
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coords.push_back(vtr::Point<size_t>(xmax, iy));
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}
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for (size_t ix = xmax; ix > xmin; ix--) {
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coords.push_back(vtr::Point<size_t>(ix, ymin));
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}
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xmin++;
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ymin++;
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xmax--;
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ymax--;
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}
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/* If height is odd, add the missing horizental line */
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if ((grids.height() - 2) % 2 == 1) {
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if (ymin == ymax) {
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for (size_t ix = xmin; ix < xmax + 1; ix++) {
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coords.push_back(vtr::Point<size_t>(ix, ymin));
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}
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}
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}
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/* If width is odd, add the missing vertical line */
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if ((grids.width() - 2) % 2 == 1) {
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if (xmin == xmax) {
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for (size_t iy = ymin; iy < ymax + 1; iy++) {
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coords.push_back(vtr::Point<size_t>(xmin, iy));
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}
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}
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}
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/* Now walk through the coordinates */
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for (vtr::Point<size_t> coord : coords) {
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/* Bypass EMPTY grid */
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if (true == is_empty_type(grids[coord.x()][coord.y()].type)) {
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continue;
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}
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/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
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if ( (0 < grids[coord.x()][coord.y()].width_offset)
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|| (0 < grids[coord.x()][coord.y()].height_offset)) {
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continue;
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}
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/* Find the module name for this type of grid */
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t_physical_tile_type_ptr grid_type = grids[coord.x()][coord.y()].type;
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_module_name = generate_grid_block_module_name(grid_module_name_prefix, std::string(grid_type->name), is_io_type(grid_type), NUM_SIDES);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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/* Add a I/O children to top_module*/
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module_manager.add_io_child(top_module, grid_module, grid_instance_ids[coord.x()][coord.y()], vtr::Point<int>(coord.x(), coord.y()));
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}
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}
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/********************************************************************
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* Print the top-level module for the FPGA fabric in Verilog format
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* This function will
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@ -328,6 +439,9 @@ int build_top_module(ModuleManager& module_manager,
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cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy);
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cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy);
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/* Update I/O children list */
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add_top_module_io_children(module_manager, top_module, grids, grid_instance_ids);
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/* Add nets when we need a complete fabric modeling,
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* which is required by downstream functions
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*/
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@ -129,6 +129,9 @@ echo -e "Testing K4N5 with pattern based local routing";
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run-task basic_tests/k4_series/k4n5_pattern_local_routing $@
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echo -e "Testing K4N4 with custom I/O location syntax";
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run-task basic_tests/k4_series/k4n4_custom_io_loc $@
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run-task basic_tests/k4_series/k4n4_custom_io_loc_center $@
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run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@
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run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@
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echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs";
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run-task basic_tests/k4_series/k4n4_rstOnLut $@
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@ -0,0 +1,109 @@
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"""
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=========================================
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Represetes IO Sequence in OpenFPGA Engine
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=========================================
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This example demonstrates the ``OpenFPGA_Arch`` class which parses the
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`VPR` and `OpenFPGA` Architecture file and provides logical information.
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.. image:: ../../../examples/OpenFPGA_basic/_sample_io_sequence.svg
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:width: 60%
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:align: center
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Author: Ganesh Gore
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"""
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import math
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import svgwrite
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from svgwrite.container import Group
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def draw_connections(width, height, connections):
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"""
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Draw connection sequence
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"""
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dwg = svgwrite.Drawing()
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DRAW_WIDTH = (width + 2) * SCALE
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DRAW_HEIGHT = (height + 2) * SCALE
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# set user coordinate space
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dwg.viewbox(width=DRAW_WIDTH, height=DRAW_HEIGHT, miny=-1 * DRAW_HEIGHT)
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dwg_main = Group(id="Main", transform="scale(1,-1)")
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dwg.add(dwg_main)
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for w in range(1, width + 2):
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dwg_main.add(
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dwg.line(
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(w * SCALE, SCALE), (w * SCALE, (height + 1) * SCALE), stroke="red"
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)
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)
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for h in range(1, height + 2):
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dwg_main.add(
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dwg.line((SCALE, h * SCALE), ((width + 1) * SCALE, h * SCALE), stroke="red")
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)
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path = "M "
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for point in connections:
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path += " %d %d " % ((point[0] + 0.5) * SCALE, (point[1] + 0.5) * SCALE)
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dwg_main.add(dwg.path(path, stroke="blue", fill="none", stroke_width="2px"))
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dwg.saveas("_sample_io_sequence.svg", pretty=True)
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SCALE = 20
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FPGA_WIDTH = 40
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FPGA_HEIGHT = 15
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W = max(FPGA_WIDTH, FPGA_HEIGHT)
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W2 = math.floor(W / 2) + 1
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connections = []
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xmin, xmax = 1, FPGA_WIDTH
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ymin, ymax = 1, FPGA_HEIGHT
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while (xmin < xmax) and (ymin < ymax):
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print(xmin, ymin, end=" -> ")
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print(xmax, ymax)
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x = xmin
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for y in range(ymin, ymax + 1):
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connections.append((x, y))
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y = ymax
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for x in range(xmin, xmax + 1):
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connections.append((x, y))
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x = xmax
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for y in range(ymin, ymax + 1)[::-1]:
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connections.append((x, y))
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y = ymin
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for x in range(xmin, xmax + 1)[::-1][:-1]:
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connections.append((x, y))
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xmin += 1
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ymin += 1
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xmax -= 1
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ymax -= 1
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if FPGA_HEIGHT % 2 == 1: # if height is odd
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if ymin == ymax: # if touching vertically
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y = ymin
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for x in range(xmin, xmax + 1):
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connections.append((x, y))
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if FPGA_WIDTH % 2 == 1: # if width is odd
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if xmin == xmax: # if touching horizontally
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x = xmin
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for y in range(ymin, ymax + 1):
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connections.append((x, y))
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# print(connections)
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if connections:
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draw_connections(FPGA_WIDTH, FPGA_HEIGHT, connections)
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else:
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# Dummy draw
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draw_connections(FPGA_WIDTH, FPGA_HEIGHT, [(1, 1)])
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@ -0,0 +1,37 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=--device 4x4_io_center
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openfpga_fast_configuration=
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_customIoLoc_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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@ -0,0 +1,37 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=--device 4x3_io_center
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openfpga_fast_configuration=
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_customIoLoc_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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@ -0,0 +1,37 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=--device 3x4_io_center
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openfpga_fast_configuration=
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_customIoLoc_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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@ -132,6 +132,48 @@
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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<fixed_layout name="4x4_io_center" width="6" height="6">
|
||||
<!--Perimeter of 'clb' blocks, I/Os are placed in the center-->
|
||||
<row type="clb" starty="H-2" priority="90"/>
|
||||
<row type="clb" starty="1" priority="91"/>
|
||||
<col type="clb" startx="W-2" priority="93"/>
|
||||
<col type="clb" startx="1" priority="93"/>
|
||||
<row type="EMPTY" starty="H-1" priority="101"/>
|
||||
<row type="EMPTY" starty="0" priority="102"/>
|
||||
<col type="EMPTY" startx="0" priority="103"/>
|
||||
<col type="EMPTY" startx="W-1" priority="104"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="io_top" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="4x3_io_center" width="6" height="5">
|
||||
<!--Perimeter of 'clb' blocks, I/Os are placed in the center-->
|
||||
<row type="clb" starty="H-2" priority="90"/>
|
||||
<row type="clb" starty="1" priority="91"/>
|
||||
<col type="clb" startx="W-2" priority="93"/>
|
||||
<col type="clb" startx="1" priority="93"/>
|
||||
<row type="EMPTY" starty="H-1" priority="101"/>
|
||||
<row type="EMPTY" starty="0" priority="102"/>
|
||||
<col type="EMPTY" startx="0" priority="103"/>
|
||||
<col type="EMPTY" startx="W-1" priority="104"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="io_top" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="3x4_io_center" width="5" height="6">
|
||||
<!--Perimeter of 'clb' blocks, I/Os are placed in the center-->
|
||||
<row type="clb" starty="H-2" priority="90"/>
|
||||
<row type="clb" starty="1" priority="91"/>
|
||||
<col type="clb" startx="W-2" priority="93"/>
|
||||
<col type="clb" startx="1" priority="93"/>
|
||||
<row type="EMPTY" starty="H-1" priority="101"/>
|
||||
<row type="EMPTY" starty="0" priority="102"/>
|
||||
<col type="EMPTY" startx="0" priority="103"/>
|
||||
<col type="EMPTY" startx="W-1" priority="104"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="io_top" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="48x48" width="50" height="50">
|
||||
<!--Perimeter of 'EMPTY' blocks, I/Os are placed on the inner ring -->
|
||||
<row type="io_top" starty="H-2" priority="90"/>
|
||||
|
|
|
|||
Loading…
Reference in New Issue