From b7b0a2a5d8fbe2407fc1a22d4cd18b7bfa7f73a7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 1 Feb 2022 12:19:26 -0800 Subject: [PATCH] [Doc] Update doc about the new option --- .../openfpga_commands/fpga_verilog_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index f58b29523..4308786e7 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -94,6 +94,10 @@ write_full_testbench Do not print time stamp in Verilog netlists + .. option:: --use_relative_path + + Force to use relative path in netlists when including other netlists. By default, this is off, which means that netlists use absolute paths when including other netlists + .. option:: --verbose Show verbose log