diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rst_gen/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rst_gen/config/task.conf
index 8954d8cf3..13eb8f773 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rst_gen/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rst_gen/config/task.conf
@@ -13,7 +13,7 @@ power_analysis = false
 spice_output=false
 verilog_output=true
 timeout_each_job = 3*60
-fpga_flow=vpr_blif
+fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga
@@ -26,7 +26,8 @@ openfpga_vpr_device_layout=2x2
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
 
 [SYNTHESIS_PARAM]
 # Yosys script parameters
@@ -37,10 +38,13 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench0_top = two_dff_inv_rst
-bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v
 bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
 bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
 
+bench1_top = rst_on_lut
+bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
+bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=