From 57a24570f5b2c6e1628d37303c070a27e606127d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 16:01:31 -0700 Subject: [PATCH 1/8] [Tool] Move icarus and signal initialization options to testbench generator --- openfpga/src/base/openfpga_verilog.cpp | 8 +++---- .../src/base/openfpga_verilog_command.cpp | 12 +++++----- .../fpga_verilog/fabric_verilog_options.cpp | 18 -------------- .../src/fpga_verilog/fabric_verilog_options.h | 6 ----- openfpga/src/fpga_verilog/verilog_api.cpp | 2 +- .../verilog_auxiliary_netlists.cpp | 24 +++++++++---------- .../verilog_testbench_options.cpp | 18 ++++++++++++++ .../fpga_verilog/verilog_testbench_options.h | 6 +++++ 8 files changed, 47 insertions(+), 47 deletions(-) diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index efa77aaf7..c9a360489 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -26,8 +26,6 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); CommandOptionId opt_include_timing = cmd.option("include_timing"); - CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); - CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template"); CommandOptionId opt_verbose = cmd.option("verbose"); @@ -38,8 +36,6 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing)); - options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); - options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); @@ -73,6 +69,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench"); CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); + CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -88,6 +86,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench)); options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); + options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); + options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); fpga_verilog_testbench(openfpga_ctx.module_graph(), diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 116d2842c..8eb8d83df 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -33,12 +33,6 @@ ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell Date: Sun, 22 Nov 2020 16:12:28 -0700 Subject: [PATCH 2/8] [Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes --- .../configuration_chain_example_script.openfpga | 4 ++-- .../custom_fabric_netlist_example_script.openfpga | 4 ++-- .../duplicated_grid_pin_example_script.openfpga | 4 ++-- openfpga_flow/OpenFPGAShellScripts/example_script.openfpga | 4 ++-- .../fast_configuration_example_script.openfpga | 4 ++-- .../OpenFPGAShellScripts/fix_device_example_script.openfpga | 4 ++-- .../fix_device_route_chan_width_example_script.openfpga | 4 ++-- .../flatten_routing_example_script.openfpga | 4 ++-- .../full_testbench_example_script.openfpga | 4 ++-- .../generate_fabric_example_script.openfpga | 2 +- .../generate_fabric_key_example_script.openfpga | 2 +- .../generate_secure_fabric_example_script.openfpga | 4 ++-- .../generate_secure_fabric_from_key_example_script.openfpga | 4 ++-- .../generate_testbench_example_script.openfpga | 2 +- .../global_tile_clock_example_script.openfpga | 4 ++-- .../implicit_verilog_example_script.openfpga | 4 ++-- .../load_external_arch_bitstream_example_script.openfpga | 4 ++-- .../sdc_time_unit_example_script.openfpga | 4 ++-- 18 files changed, 33 insertions(+), 33 deletions(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga index d9391c4c1..67c1419bd 100644 --- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga index 577ed9ce4..3bc847bdf 100644 --- a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_t # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index f507fc49c..227e1fdda 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga index a9f20d9d8..18b7c97f2 100644 --- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga index 43e62f7a4..0699d4ea6 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping --fast_configuration +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping --fast_configuration # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga index 3d5418466..ef37d9242 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga index 5bac56d00..c03f2b175 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index 4889f8414..1e60f70e1 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga index a9f20d9d8..18b7c97f2 100644 --- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index 38ebc9d28..fcbf6e144 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -26,7 +26,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga index d7f025434..a836b02bc 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga @@ -26,7 +26,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga index 7993838cd..b7a856dfd 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga @@ -50,7 +50,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga index 9d9b0aa7d..8d8d07d32 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga @@ -50,7 +50,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga index 8cfb063d1..b88e5370a 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga @@ -51,7 +51,7 @@ write_fabric_bitstream --file fabric_bitstream --format xml # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga index 597014117..1be7eb731 100644 --- a/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga @@ -49,7 +49,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -57,7 +57,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index 7dbab86a5..ded4e1fbc 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --include_timing --include_signal_init --suppo # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga index 8276a9119..976087ded 100644 --- a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga @@ -50,7 +50,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga index fc8d333f5..6887cd8a4 100644 --- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga @@ -44,7 +44,7 @@ build_fabric_bitstream --verbose # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -52,7 +52,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here From 655da9f3d0b31f2d827eb1e57f56b29a0755ba47 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 16:37:19 -0700 Subject: [PATCH 3/8] [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention --- ...onfiguration_chain_example_script.openfpga | 0 ...tom_fabric_netlist_example_script.openfpga | 0 ...uplicated_grid_pin_example_script.openfpga | 0 .../example_script.openfpga | 0 ...fast_configuration_example_script.openfpga | 0 .../fix_device_example_script.openfpga | 0 ...e_route_chan_width_example_script.openfpga | 0 .../flatten_routing_example_script.openfpga | 0 .../full_testbench_example_script.openfpga | 0 ...generate_bitstream_example_script.openfpga | 0 ...tstream_fix_device_example_script.openfpga | 0 .../generate_fabric_example_script.openfpga | 0 ...enerate_fabric_key_example_script.openfpga | 0 ...rate_secure_fabric_example_script.openfpga | 0 ...re_fabric_from_key_example_script.openfpga | 0 .../generate_spice_example_script.openfpga | 0 ...generate_testbench_example_script.openfpga | 0 .../global_tile_clock_example_script.openfpga | 0 .../implicit_verilog_example_script.openfpga | 0 .../iverilog_example_script.openfpga | 71 ++++++++++++++++++ ...nal_arch_bitstream_example_script.openfpga | 0 .../mcnc_example_script.openfpga | 0 .../openfpga_shell_scripts/rename_scripts.sh | 4 + .../sdc_time_unit_example_script.openfpga | 0 .../skywater_tapeout_example_script.openfpga | 74 +++++++++++++++++++ .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../generate_random_key/config/task.conf | 2 +- .../generate_vanilla_key/config/task.conf | 2 +- .../load_external_key/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../fixed_device_support/config/task.conf | 2 +- .../config/task.conf | 2 +- .../configuration_chain/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../configuration_frame/config/task.conf | 2 +- .../configuration_frame_ccff/config/task.conf | 2 +- .../configuration_frame_scff/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../fast_configuration_chain/config/task.conf | 2 +- .../config/task.conf | 2 +- .../fast_configuration_frame/config/task.conf | 2 +- .../config/task.conf | 2 +- .../fast_memory_bank/config/task.conf | 2 +- .../fast_memory_bank_use_set/config/task.conf | 2 +- .../flatten_memory/config/task.conf | 2 +- .../memory_bank/config/task.conf | 2 +- .../memory_bank_use_reset/config/task.conf | 2 +- .../memory_bank_use_resetb/config/task.conf | 2 +- .../memory_bank_use_set/config/task.conf | 2 +- .../config/task.conf | 2 +- .../memory_bank_use_setb/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../multi_region_memory_bank/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../smart_fast_memory_bank/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../generate_fabric/config/task.conf | 2 +- .../generate_testbench/config/task.conf | 2 +- .../global_tile_clock/config/task.conf | 2 +- .../k4_series/k4n4_L124/config/task.conf | 2 +- .../k4_series/k4n4_adder/config/task.conf | 2 +- .../k4_series/k4n4_bram/config/task.conf | 2 +- .../k4_series/k4n4_frac_lut/config/task.conf | 2 +- .../k4_series/k4n4_frac_mult/config/task.conf | 2 +- .../k4n4_no_local_routing/config/task.conf | 2 +- .../config/task.conf | 2 +- .../configuration_chain/config/task.conf | 2 +- .../configuration_frame/config/task.conf | 2 +- .../flatten_memory/config/task.conf | 2 +- .../memory_bank/config/task.conf | 2 +- .../bottom_right_custom_pins/config/task.conf | 2 +- .../top_left_custom_pins/config/task.conf | 2 +- .../top_right_custom_pins/config/task.conf | 2 +- .../benchmark_sweep/counter/config/task.conf | 2 +- .../benchmark_sweep/fsm/config/task.conf | 2 +- .../benchmark_sweep/sapone/config/task.conf | 2 +- .../compilation_verification/config/task.conf | 2 +- .../device_48x48/config/task.conf | 2 +- .../device_96x96/config/task.conf | 2 +- .../device_auto/config/task.conf | 2 +- .../config/task.conf | 2 +- .../fpga_sdc/sdc_time_unit/config/task.conf | 2 +- .../generate_spice/config/task.conf | 2 +- .../behavioral_verilog/config/task.conf | 2 +- .../bram/dpram16k/config/task.conf | 2 +- .../bram/wide_dpram16k/config/task.conf | 2 +- .../depopulate_crossbar/config/task.conf | 2 +- .../duplicated_grid_pin/config/task.conf | 2 +- .../fabric_chain/adder_chain/config/task.conf | 2 +- .../register_chain/config/task.conf | 2 +- .../fabric_chain/scan_chain/config/task.conf | 2 +- .../flatten_routing/config/task.conf | 2 +- .../config/task.conf | 2 +- .../fpga_verilog/hard_adder/config/task.conf | 2 +- .../implicit_verilog/config/task.conf | 2 +- .../fpga_verilog/io/aib/config/task.conf | 2 +- .../io/embedded_io/config/task.conf | 2 +- .../io/multi_io_capacity/config/task.conf | 2 +- .../io/reduced_io/config/task.conf | 2 +- .../fpga_verilog/io/soc_io/config/task.conf | 2 +- .../lut_design/frac_lut4/config/task.conf | 2 +- .../frac_lut4_and_switch/config/task.conf | 2 +- .../lut_design/frac_lut6/config/task.conf | 2 +- .../intermediate_buffer/config/task.conf | 2 +- .../lut_design/single_mode/config/task.conf | 2 +- .../const_input_gnd/config/task.conf | 2 +- .../mux_design/debuf_mux/config/task.conf | 2 +- .../inbuf_only_mux/config/task.conf | 2 +- .../mux_design/local_encoder/config/task.conf | 2 +- .../no_const_input/config/task.conf | 2 +- .../outbuf_only_mux/config/task.conf | 2 +- .../mux_design/stdcell_mux2/config/task.conf | 2 +- .../tree_structure/config/task.conf | 2 +- .../power_gated_inverter/config/task.conf | 2 +- .../fpga_verilog/spypad/config/task.conf | 2 +- .../thru_narrow_tile/config/task.conf | 2 +- .../thru_wide_tile/config/task.conf | 2 +- .../fpga_verilog/untileable/config/task.conf | 2 +- .../tasks/mcnc_big20/config/task.conf | 2 +- 133 files changed, 257 insertions(+), 108 deletions(-) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/configuration_chain_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/custom_fabric_netlist_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/duplicated_grid_pin_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/fast_configuration_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/fix_device_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/fix_device_route_chan_width_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/flatten_routing_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/full_testbench_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_bitstream_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_bitstream_fix_device_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_fabric_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_fabric_key_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_secure_fabric_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_secure_fabric_from_key_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_spice_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/generate_testbench_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/global_tile_clock_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/implicit_verilog_example_script.openfpga (100%) create mode 100644 openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/load_external_arch_bitstream_example_script.openfpga (100%) rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/mcnc_example_script.openfpga (100%) create mode 100644 openfpga_flow/openfpga_shell_scripts/rename_scripts.sh rename openfpga_flow/{OpenFPGAShellScripts => openfpga_shell_scripts}/sdc_time_unit_example_script.openfpga (100%) create mode 100644 openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga new file mode 100644 index 000000000..e161d8e2f --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga @@ -0,0 +1,71 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh new file mode 100644 index 000000000..6b568e5d8 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh @@ -0,0 +1,4 @@ +foreach i (*.openfpga) + sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i + sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +end diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga similarity index 100% rename from openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga rename to openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga new file mode 100644 index 000000000..e9195e9e7 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf index cd23bc3f7..e7f02d189 100644 --- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_fabric_netlist_file=./FABRIC_NETLIST/fabric_netlists.v diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf index a89cf8eaa..2cba7a963 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf index 5e78d1462..069541110 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf index c5abfbf78..8d1184a38 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_key_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf index d15e02442..787e469d0 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf index 41768fc75..9a12bc1d8 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf index bfaecd8a1..5ce93941b 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_sample_key.xml diff --git a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf index 364962203..3fea70cef 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf index 7b107698e..78daaf0c9 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf index f2786dee3..7ae2d1334 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf index b96d8f648..9d7ea2d8d 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf index 379ae0404..4efa817a1 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf index 6c7ae7c75..37a1eb75b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf index 288a3564a..94acf3ed8 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf index 4a8222d91..d3290d175 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf index ded20701d..aaee4c7c9 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf index 399be683b..37d68988c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf index 2be6528e4..2a8cded3f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf index b5e82f32b..40b3c6f9b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf index 24751ed47..d6f4a1812 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf index 1f2a9bd45..86edcefec 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf index 548e37cb8..e91cbd103 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf index 793854774..63baba79e 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf index 04e7fef1b..6f4200ffe 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf index d3879a68f..51f2344fe 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf index 0ab4871ca..14425886d 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf index 4b5763f69..2ee58fbf2 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index 05e3f475b..5510c7a8c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf index 44494baf6..1ceeb3384 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf index 74cba9434..adaf26a25 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf index 5da25a81e..960cc0358 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf index cb9ddbee7..88f00dd83 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf index 87ef8b32b..2db9c982f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf index cf4341928..1b27c683c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf index 855e3156e..1e15dba22 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf index 55af9d7cc..6f166e5fc 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf index 6aa293777..eff60d97e 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf index d1e73545c..85771410c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf index a78899a35..41c819a8c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf index fb8de2067..4fac7ac49 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf index 1cdffa78f..d4a77cd79 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf index 26e5b6239..f7e99fd89 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf index 2e2c32b55..ed7db9ae5 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf index b4b6a7759..4f9b28e27 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf index 342c3ae94..66d4da4fb 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf index 9c3fd2442..5d06846c5 100644 --- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf index f8c81bb1b..42d3c5733 100644 --- a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index 6267eda37..fd95b7ca9 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf index c59ceb467..1bde7ed3d 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf index e1beaf610..398dbb170 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index 6ed4e217e..ff0985799 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf index fa6394642..ab37fc5c0 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf index d338a3409..99127bef3 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf index c076b156c..aafcef4d2 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf index 2a94ee552..97333b186 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf index fd40bb331..5407cced6 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf index 8a82fbb57..ed14464f6 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf index 513ac66d4..f076601d4 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf index a8cfe8b50..456a65ff6 100644 --- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/bottom_right_custom_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/bottom_right_custom_pins/config/task.conf index d2549d58e..797e27e28 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/bottom_right_custom_pins/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/bottom_right_custom_pins/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/top_left_custom_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/top_left_custom_pins/config/task.conf index e4b05060d..741697876 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/top_left_custom_pins/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/top_left_custom_pins/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/top_right_custom_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/top_right_custom_pins/config/task.conf index fafdb3ceb..2b4f2ea35 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/top_right_custom_pins/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/top_right_custom_pins/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 30e2367f7..9d5a92747 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf index 7fa78a379..4ecd92e5c 100644 --- a/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/fsm/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf index 3da4d6263..89a6da9d3 100644 --- a/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/sapone/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/iverilog_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/compilation_verification/config/task.conf b/openfpga_flow/tasks/compilation_verification/config/task.conf index a8ae907f9..84645e9a0 100644 --- a/openfpga_flow/tasks/compilation_verification/config/task.conf +++ b/openfpga_flow/tasks/compilation_verification/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf index 911239184..22f2f94a4 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf @@ -17,7 +17,7 @@ timeout_each_job = 3*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_route_chan_width=50 diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf index 97dcc465b..45903d9e6 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf @@ -17,7 +17,7 @@ timeout_each_job = 6*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_route_chan_width=100 diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf index eba6485e2..86f0c8053 100644 --- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf index f88536f37..11cf542e3 100644 --- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf index 102363652..88e4314d6 100644 --- a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf b/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf index aa4a6cb82..e9d852a6f 100644 --- a/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf +++ b/openfpga_flow/tasks/fpga_spice/generate_spice/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_spice_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf index 0e1a11deb..822c2fde1 100644 --- a/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf index b693eab56..b7d8715ec 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 diff --git a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf index bf748e819..d8dc5d26d 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf index b6b8fa9c9..cb1737e18 100644 --- a/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf index 650132a45..44836f03f 100644 --- a/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf index 71813d734..0b6e85df9 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf index aa92c76ae..307034e96 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf index d042a6923..c90e6588a 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf index 6a4c3aad5..8d63328e2 100644 --- a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf index f8717b5fd..8f41b34e6 100644 --- a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf index 0b3ecf486..0764beeb3 100644 --- a/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= diff --git a/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf index e56a04fca..d2eba0433 100644 --- a/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf index 3dc99925d..a25c10ce5 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x4 diff --git a/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf index a899588b2..2c6789133 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf index 645339aee..1a53f8912 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 diff --git a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf index 04d01af53..a04fd61fc 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 diff --git a/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf index 2ef732970..1480385a0 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf index 805502d33..7791c2a69 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf index 2ff8d23d1..cde143549 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_and_switch/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf index 1809feae5..3e5b932ab 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf index 35584d351..8acff380a 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf index 7753da7cb..3c2aa65cc 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf index 4d743f8a9..f1b77e97f 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/const_input_gnd/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_const_input_gnd_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf index c076c6071..62ec6547a 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf index ed3766047..68e822fe5 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf index 6ed171b79..661ca08c3 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf index f463f0823..1eaecad4e 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/no_const_input/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_no_const_input_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf index da765eacd..e8607aaaa 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf index b6decc57b..160a16355 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf index 0508a2181..11bd58730 100644 --- a/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf index fe450ce38..1e919ff29 100644 --- a/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf index 63d24e471..eeadd3d3f 100644 --- a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf index 7099ff2bc..1652b5d5e 100644 --- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf index 711c7c7c5..393e0bbbc 100644 --- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf index 44182f645..eebcf13c9 100644 --- a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 diff --git a/openfpga_flow/tasks/mcnc_big20/config/task.conf b/openfpga_flow/tasks/mcnc_big20/config/task.conf index 72cb951d0..1198d8fc5 100644 --- a/openfpga_flow/tasks/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/mcnc_big20/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml From 3b2a4c5387a57c8a2f919e3a9a0867a627f8fe97 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 20:25:03 -0700 Subject: [PATCH 4/8] [Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists --- openfpga/src/fpga_verilog/verilog_api.cpp | 1 + .../fpga_verilog/verilog_essential_gates.cpp | 6 - .../verilog_preconfig_top_module.cpp | 7 + .../fpga_verilog/verilog_submodule_utils.cpp | 37 ----- .../fpga_verilog/verilog_submodule_utils.h | 4 - .../fpga_verilog/verilog_testbench_utils.cpp | 136 ++++++++++++++++++ .../fpga_verilog/verilog_testbench_utils.h | 7 + .../fpga_verilog/verilog_top_testbench.cpp | 8 ++ .../src/fpga_verilog/verilog_top_testbench.h | 2 + 9 files changed, 161 insertions(+), 47 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index e012c32e6..623f141f1 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -202,6 +202,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, + circuit_lib, config_protocol, fabric_global_port_info, atom_ctx, place_ctx, io_location_map, diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index 3fbcb5d45..9b4a356f4 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -195,9 +195,6 @@ void print_verilog_invbuf_module(const ModuleManager& module_manager, /* Print timing info */ print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - /* Put an end to the Verilog module */ print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); } @@ -271,9 +268,6 @@ void print_verilog_passgate_module(const ModuleManager& module_manager, /* Print timing info */ print_verilog_submodule_timing(fp, circuit_lib, circuit_model); - /* Print signal initialization */ - print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model); - /* Put an end to the Verilog module */ print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); } diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 033fcc346..667463d53 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -470,6 +470,13 @@ namespace openfpga circuit_lib, sram_model, bitstream_manager); + /* Add signal initialization */ + print_verilog_testbench_signal_initialization(fp, + std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), + circuit_lib, + module_manager, + top_module); + /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp index faf965068..37009c930 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp @@ -88,43 +88,6 @@ void print_verilog_submodule_timing(std::fstream& fp, } -void print_verilog_submodule_signal_init(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model) { - /* Ensure a valid file handler*/ - VTR_ASSERT(true == valid_file_stream(fp)); - - fp << std::endl; - fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl; - print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); - fp << "\tinitial begin" << std::endl; - fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl; - - /* Only for formal verification: deposite a zero signal values */ - /* Initialize each input port */ - for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - fp << "\t\t$deposit("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); - fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); - fp << ");" << std::endl; - } - fp << "\t`else" << std::endl; - - /* Regular case: deposite initial signal values: a random value */ - for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - fp << "\t\t$deposit("; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); - fp << ", $random);" << std::endl; - } - - fp << "\t`endif\n" << std::endl; - fp << "\tend" << std::endl; - print_verilog_comment(fp, std::string("------ END driver initialization -----")); - fp << "`endif" << std::endl; -} - /********************************************************************* * Register all the user-defined modules in the module manager * Walk through the circuit library and add user-defined circuit models diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.h b/openfpga/src/fpga_verilog/verilog_submodule_utils.h index 3f0e1dadd..51347de35 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.h +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.h @@ -20,10 +20,6 @@ void print_verilog_submodule_timing(std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model); -void print_verilog_submodule_signal_init(std::fstream& fp, - const CircuitLibrary& circuit_lib, - const CircuitModelId& circuit_model); - void add_user_defined_verilog_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 6f08a1c85..d8d09bb38 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -16,6 +16,8 @@ #include "openfpga_port.h" #include "openfpga_digest.h" +#include "openfpga_naming.h" + #include "verilog_port_types.h" #include "module_manager_utils.h" @@ -732,4 +734,138 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Print signal initialization which + * deposit initial values for the input ports of primitive circuit models + * This function recusively walk through from the parent_module + * until reaching a primitive module that matches the circuit_model name + * The hierarchy walkthrough collects the full paths for the primitive modules + * in the graph of modules + *******************************************************************/ +static +void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fstream& fp, + const std::string& hie_path, + const CircuitLibrary& circuit_lib, + const CircuitModelId& circuit_model, + const ModuleManager& module_manager, + const ModuleId& parent_module, + const ModuleId& primitive_module) { + /* Validate the file stream */ + valid_file_stream(fp); + + /* Return if the current module has no children */ + if (0 == module_manager.child_modules(parent_module).size()) { + return; + } + + /* Go through child modules */ + for (const ModuleId& child_module : module_manager.child_modules(parent_module)) { + /* If the child module is not the primitive module, + * we recursively visit the child module + */ + for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) { + std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); + /* Use default instanec name if not assigned */ + if (true == instance_name.empty()) { + instance_name = generate_instance_name(module_manager.module_name(child_module), child_instance); + } + + std::string child_hie_path = hie_path + "." + instance_name; + + if (child_module != primitive_module) { + rec_print_verilog_testbench_primitive_module_signal_initialization(fp, + child_hie_path, + circuit_lib, circuit_model, + module_manager, child_module, + primitive_module); + } else { + /* If the child module is the primitive module, + * we output the signal initialization codes for the input ports + */ + VTR_ASSERT_SAFE(child_module == primitive_module); + + print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); + fp << "\tinitial begin" << std::endl; + fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl; + + for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { + /* Only for formal verification: deposite a zero signal values */ + /* Initialize each input port */ + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + fp << "\t\t$deposit("; + fp << child_hie_path << "."; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); + fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); + fp << ");" << std::endl; + } + fp << "\t`else" << std::endl; + + /* Regular case: deposite initial signal values: a random value */ + for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) { + BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); + fp << "\t\t$deposit("; + fp << child_hie_path << "."; + fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info); + fp << ", $random);" << std::endl; + } + + fp << "\t`endif\n" << std::endl; + fp << "\tend" << std::endl; + print_verilog_comment(fp, std::string("------ END driver initialization -----")); + } + } + } +} + +/******************************************************************** + * Print signal initialization for Verilog testbenches + * which aim to deposit initial values for the input ports of primitive circuit models: + * - Passgate + * - Logic gates (ONLY for MUX2) + *******************************************************************/ +void print_verilog_testbench_signal_initialization(std::fstream& fp, + const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleId& top_module) { + /* Validate the file stream */ + valid_file_stream(fp); + + /* Collect circuit models that need signal initialization */ + std::vector signal_init_circuit_models; + + for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) { + signal_init_circuit_models.push_back(model); + } + + for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_GATE)) { + if (CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(model)) { + signal_init_circuit_models.push_back(model); + } + } + + /* If there is no circuit model in the list, return directly */ + if (signal_init_circuit_models.empty()) { + return; + } + + /* Add signal initialization Verilog codes */ + fp << std::endl; + fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl; + for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) { + /* Find the module id corresponding to the circuit model from module graph */ + ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model)); + VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); + + /* Find all the instances created by the circuit model across the fabric*/ + rec_print_verilog_testbench_primitive_module_signal_initialization(fp, + top_instance_name, + circuit_lib, signal_init_circuit_model, + module_manager, top_module, + primitive_module); + } + + fp << "`endif" << std::endl; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 9ba67f298..9a6fbeb17 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -8,6 +8,7 @@ #include #include #include "module_manager.h" +#include "circuit_library.h" #include "vpr_context.h" #include "io_location_map.h" #include "vpr_netlist_annotation.h" @@ -94,6 +95,12 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const std::string& check_flag_port_postfix, const std::string& autocheck_preprocessing_flag); +void print_verilog_testbench_signal_initialization(std::fstream& fp, + const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, + const ModuleManager& module_manager, + const ModuleId& top_module); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index dbcb737e0..21e8de9d6 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -1769,6 +1769,7 @@ void print_verilog_top_testbench_check(std::fstream& fp, void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx, @@ -1916,6 +1917,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, module_manager, top_module, bitstream_manager, fabric_bitstream); + /* Add signal initialization */ + print_verilog_testbench_signal_initialization(fp, + std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME), + circuit_lib, + module_manager, + top_module); + /* Add stimuli for reset, set, clock and iopad signals */ print_verilog_testbench_random_stimuli(fp, atom_ctx, netlist_annotation, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index 6aeb5578b..1a657c526 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -9,6 +9,7 @@ #include "module_manager.h" #include "bitstream_manager.h" #include "fabric_bitstream.h" +#include "circuit_library.h" #include "config_protocol.h" #include "vpr_context.h" #include "io_location_map.h" @@ -26,6 +27,7 @@ namespace openfpga { void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx, From fd0e6814eab68183d2b09a569cc7f39774172d5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 20:33:15 -0700 Subject: [PATCH 5/8] [Doc] Update documentation about the pre-processing flags --- docs/source/manual/fpga_verilog/fabric_netlist.rst | 12 ------------ docs/source/manual/fpga_verilog/testbench.rst | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/docs/source/manual/fpga_verilog/fabric_netlist.rst b/docs/source/manual/fpga_verilog/fabric_netlist.rst index 46c8a934b..f09575a84 100644 --- a/docs/source/manual/fpga_verilog/fabric_netlist.rst +++ b/docs/source/manual/fpga_verilog/fabric_netlist.rst @@ -48,18 +48,6 @@ Top-level Netlists .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command. - - .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command. - - .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. - -__ iverilog_website_ - -.. _iverilog_website: http://iverilog.icarus.com/ - Logic Blocks ~~~~~~~~~~~~ This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks. diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index db3ed8835..d6cd518fe 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -80,6 +80,20 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! + - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command. + + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. + + - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command. + + .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. + +__ iverilog_website_ + +.. _iverilog_website: http://iverilog.icarus.com/ + + + .. option:: _autocheck_top_tb.v This is the netlist for full testbench. From 5eb04e6fff42d2c59b67d2f53a6afb438eaead80 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 20:53:32 -0700 Subject: [PATCH 6/8] [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals --- openfpga_flow/openfpga_cell_library/verilog/mux2.v | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index b539b7a69..66d204a99 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -7,10 +7,12 @@ //----------------------------------------------------- module MUX2( - input A, // Data input 0 - input B, // Data input 1 - input S0, // Select port - output Y // Data output + // iVerilog is buggy on the 'input A' declaration when deposit initial + // values + input [0:0] A, // Data input 0 + input [0:0] B, // Data input 1 + input [0:0] S0, // Select port + output [0:0] Y // Data output ); assign Y = S0 ? B : A; From 617f7e3062566356e247bc9b337822512505d75b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 21:13:22 -0700 Subject: [PATCH 7/8] [Flow] disable signal initialization for behavioral verilog generation --- .../tasks/fpga_verilog/behavioral_verilog/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf index 822c2fde1..6e45342b7 100644 --- a/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml From fd80cacaa3b6d84522d9e9df4fdc80a74e61b17e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 22 Nov 2020 21:14:10 -0700 Subject: [PATCH 8/8] [Flow] Add example script for behaviorial verilog generation --- ...behavioral_verilog_example_script.openfpga | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga new file mode 100644 index 000000000..0da27426f --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --support_icarus_simulator --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory