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[Engine] Register QL memory bank as a legal protocol

This commit is contained in:
tangxifan 2021-09-09 15:06:51 -07:00
parent 81a2ad58df
commit b787c4e100
14 changed files with 34 additions and 4 deletions
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1
openfpga/src/base/openfpga_naming.cpp
View File

@ -703,6 +703,7 @@ std::string generate_sram_port_name(const e_config_protocol_type& sram_orgz_type
}
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* Two types of ports are available:
* (1) Bit Lines (BLs) of a SRAM cell, enabled by port type of BL

2
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -279,7 +279,7 @@ void build_primitive_block_module(ModuleManager& module_manager,
size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, sram_orgz_type);
if (0 < num_shared_config_bits) {
/* Check: this SRAM organization type must be memory-bank ! */
VTR_ASSERT( CONFIG_MEM_MEMORY_BANK == sram_orgz_type );
VTR_ASSERT( CONFIG_MEM_MEMORY_BANK == sram_orgz_type || CONFIG_MEM_QL_MEMORY_BANK == sram_orgz_type );
/* Generate a list of ports */
add_reserved_sram_ports_to_module_manager(module_manager, primitive_module,
num_shared_config_bits);

1
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -786,6 +786,7 @@ void build_memory_module(ModuleManager& module_manager,
const size_t& num_mems) {
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
build_memory_flatten_module(module_manager, circuit_lib,
module_name, sram_model, num_mems);

4
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -265,7 +265,8 @@ void build_top_module_configurable_regions(ModuleManager& module_manager,
/* Exclude decoders from the list */
size_t num_configurable_children = module_manager.configurable_children(top_module).size();
if (CONFIG_MEM_MEMORY_BANK == config_protocol.type()) {
if (CONFIG_MEM_MEMORY_BANK == config_protocol.type()
|| CONFIG_MEM_QL_MEMORY_BANK == config_protocol.type()) {
num_configurable_children -= 2;
} else if (CONFIG_MEM_FRAME_BASED == config_protocol.type()) {
num_configurable_children -= 1;
@ -752,6 +753,7 @@ size_t generate_top_module_sram_port_size(const ConfigProtocol& config_protocol,
case CONFIG_MEM_STANDALONE:
break;
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_FRAME_BASED:
/* CCFF head/tail, data input could be multi-bit ports */

3
openfpga/src/fpga_bitstream/build_device_bitstream.cpp
View File

@ -96,7 +96,8 @@ size_t rec_estimate_device_bitstream_num_bits(const ModuleManager& module_manage
/* Memory configuration protocol will have 2 decoders
* at the top-level
*/
if (CONFIG_MEM_MEMORY_BANK == config_protocol_type) {
if (CONFIG_MEM_MEMORY_BANK == config_protocol_type
|| CONFIG_MEM_QL_MEMORY_BANK == config_protocol_type) {
VTR_ASSERT(2 <= curr_region_num_config_child);
curr_region_num_config_child -= 2;
}

1
openfpga/src/fpga_bitstream/fast_configuration.cpp
View File

@ -87,6 +87,7 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type&
}
break;
}
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_FRAME_BASED: {
/* Count how many logic '1' and logic '0' bits we can skip */

1
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -306,6 +306,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
bitstream_manager,
fabric_bitstream);
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
status = write_memory_bank_fabric_bitstream_to_text_file(fp,
apply_fast_configuration,

1
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
View File

@ -103,6 +103,7 @@ int write_fabric_config_bit_to_xml_file(std::fstream& fp,
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_SCAN_CHAIN:
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* Bit line address */
write_tab_to_file(fp, xml_hierarchy_depth + 1);

3
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -217,6 +217,7 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
case CONFIG_MEM_SCAN_CHAIN:
print_verilog_top_testbench_config_chain_port(fp, module_manager, top_module);
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module);
break;
@ -835,6 +836,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
100. * ((float)num_config_clock_cycles / (float)(1 + regional_bitstream_max_size) - 1.));
}
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* For fast configuration, we will skip all the zero data points */
num_config_clock_cycles = 1 + build_memory_bank_fabric_bitstream_by_address(fabric_bitstream).size();
@ -1093,6 +1095,7 @@ void print_verilog_top_testbench_configuration_protocol_stimulus(std::fstream& f
break;
case CONFIG_MEM_SCAN_CHAIN:
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_FRAME_BASED: {
ModulePortId en_port_id = module_manager.find_module_port(top_module,

3
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -1010,6 +1010,7 @@ void print_verilog_local_sram_wires(std::fstream& fp,
print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false);
break;
}
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* Generate the name of local wire for the SRAM output and inverted output */
std::vector<BasicPort> sram_ports;
@ -1100,6 +1101,7 @@ void print_verilog_local_config_bus(std::fstream& fp,
*/
break;
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* Two configuration buses should be outputted
* One for the regular SRAM ports of a routing multiplexer
@ -1173,6 +1175,7 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp,
*/
break;
}
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* This is currently most used in ReRAM FPGAs */
/* Print configuration bus to group reserved BL/WLs */

3
openfpga/src/utils/circuit_library_utils.cpp
View File

@ -94,6 +94,7 @@ size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_li
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_SCAN_CHAIN:
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* Find BL/WL ports */
std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, CIRCUIT_MODEL_PORT_BLB);
@ -175,6 +176,7 @@ size_t find_circuit_num_config_bits(const e_config_protocol_type& config_protoco
switch (config_protocol_type) {
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
break;
}
@ -293,6 +295,7 @@ bool check_configurable_memory_circuit_model(const e_config_protocol_type& confi
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_FRAME_BASED:
num_err = check_sram_circuit_model_ports(circuit_lib,
config_mem_circuit_model,

7
openfpga/src/utils/memory_utils.cpp
View File

@ -74,6 +74,7 @@ std::map<std::string, BasicPort> generate_cmos_mem_module_port2port_map(const Ba
port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
break;
}
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* TODO: */
break;
@ -131,6 +132,7 @@ std::map<std::string, BasicPort> generate_rram_mem_module_port2port_map(const Ba
port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
break;
}
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */
break;
@ -189,6 +191,7 @@ void update_cmos_mem_module_config_bus(const e_config_protocol_type& sram_orgz_t
*/
VTR_ASSERT(true == config_bus.rotate(1));
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* In this case, a memory module has a number of BL/WL and BLB/WLB (possibly).
* LSB and MSB of configuration bus will be shifted by the number of BL/WL/BLB/WLB.
@ -219,6 +222,7 @@ void update_rram_mem_module_config_bus(const e_config_protocol_type& sram_orgz_t
*/
VTR_ASSERT(true == config_bus.rotate(1));
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* In this case, a memory module contains unique BL/WL or BLB/WLB,
* which are not shared with other modules
@ -275,6 +279,7 @@ bool check_mem_config_bus(const e_config_protocol_type& sram_orgz_type,
*/
return (local_expected_msb == config_bus.get_msb());
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* TODO: comment on why
*/
@ -319,6 +324,7 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
break;
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
std::vector<e_circuit_model_port_type> ports_to_search;
ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
@ -373,6 +379,7 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
/* CCFF head/tail are single-bit ports */
sram_port_size = 1;
break;
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
break;
case CONFIG_MEM_FRAME_BASED:

3
openfpga/src/utils/module_manager_utils.cpp
View File

@ -313,6 +313,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
/* Add ports to the module manager */
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
for (const std::string& sram_port_name : sram_port_names) {
/* Add generated ports to the ModuleManager */
@ -1288,6 +1289,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
break;
}
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
sram_orgz_type, CIRCUIT_MODEL_PORT_BL);
@ -1742,6 +1744,7 @@ size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_mana
switch (sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK: {
/* For scan-chain, standalone and memory bank configuration protocol
* The number of configuration bits is the sum of configuration bits

5
openfpga/src/utils/mux_utils.cpp
View File

@ -257,6 +257,7 @@ size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib,
size_t num_config_bits = 0;
switch (sram_orgz_type) {
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_STANDALONE:
@ -298,6 +299,7 @@ size_t find_rram_mux_num_config_bits(const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type) {
size_t num_config_bits = 0;
switch (sram_orgz_type) {
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
/* In memory bank, by intensively share the Bit/Word Lines,
* we only need 1 additional BL and WL for each MUX level.
@ -365,6 +367,7 @@ size_t find_cmos_mux_num_shared_config_bits(const e_config_protocol_type& sram_o
size_t num_shared_config_bits = 0;
switch (sram_orgz_type) {
case CONFIG_MEM_QL_MEMORY_BANK:
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_STANDALONE:
@ -388,7 +391,7 @@ size_t find_rram_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type) {
size_t num_shared_config_bits = 0;
switch (sram_orgz_type) {
case CONFIG_MEM_MEMORY_BANK: {
case CONFIG_MEM_QL_MEMORY_BANK: {
/* In memory bank, the number of shared configuration bits is
* the sum of largest branch size at each level
*/