[test] reworking the testcase to validate clock network with internal drivers

openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v

@@ -0,0 +1,21 @@
+/////////////////////////////////////////
+//  Functionality: A locally generated clock signal which is to test clock network with internal drivers
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module clk_cond(clk_i, clk_cond_i, d_i, q_o);
+
+input wire clk_cond_i;
+input wire clk_i;
+input wire d_i;
+output reg q_o;
+
+wire int_clk;
+assign int_clk = clk_cond_i & clk_i;
+
+always @(posedge int_clk) begin
+  q_o <= d_i;
+end
+
+endmodule

openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga

@@ -0,0 +1,76 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+  --clock_modeling ideal \
+  --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \
+  --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \
+  --read_vpr_constraints ${OPENFPGA_VPR_CONSTRAINT_FILE}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Read OpenFPGA clock architecture
+read_openfpga_clock_arch -f ${OPENFPGA_CLOCK_ARCH_FILE}
+
+# Append clock network to vpr's routing resource graph
+append_clock_rr_graph
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Route clock based on clock network definition
+route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS_FILE} #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --include_signal_init --bitstream fabric_bitstream.bit  --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_PORT_MAPPING} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/clk_arch_1clk_1rst_2layer_int_driver.xml

@@ -1,5 +1,5 @@
 <clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
-  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:1]"> 
     <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"> 
         <internal_driver tile_pin="clb.O[0:7]"/>
@@ -21,6 +21,7 @@
     <taps>
       <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
       <all from_pin="op_clk[0:0]" to_pin="clb[0:0].I[0:11]"/>
+      <all from_pin="op_clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
     </taps>
   </clock_network>  
   <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_clk_cond.xml

@@ -2,7 +2,8 @@
   <!-- For a given .blif file, we want to assign 
        - the reset signal to the op_reset[0] port of the FPGA fabric
     -->
-  <set_io pin="op_reset[0]" net="rst_i"/>
+  <set_io pin="op_reset[0]" net="OPEN"/>
   <set_io pin="op_clk[0]" net="clk_i"/>
+  <set_io pin="op_clk[1]" net="int_clk"/>
 </pin_constraints>
 

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf

@@ -16,7 +16,7 @@ timeout_each_job = 3*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
@@ -25,12 +25,13 @@ openfpga_vpr_route_chan_width=32
 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
 openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
 openfpga_route_clock_options=
+openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v
 
 [SYNTHESIS_PARAM]
 # Yosys script parameters
@@ -40,8 +41,9 @@ bench_read_verilog_options_common = -nolatches
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
-bench0_top = clk_gate
-bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_gate.xml
+bench0_top = clk_cond
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml
+bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/vpr_constraint_clk_cond.xml

@@ -0,0 +1,12 @@
+<vpr_constraints tool_name="vpr">
+  <partition_list>
+    <partition name="q_o_part">
+      <add_atom name_pattern="q_o"/>
+      <add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
+    </partition>
+    <partition name="int_clk_part">
+      <add_atom name_pattern="int_clk*"/>
+      <add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
+    </partition>
+  </partition_list>
+</vpr_constraints>