From b6eace8facb3878b36f0329d73b27b64c574cc61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 27 Feb 2023 13:10:54 -0800 Subject: [PATCH] [core] now switch id is linked in clock network --- .../src/base/clock_network.cpp | 9 +++++ .../src/base/clock_network.h | 2 + .../src/utils/clock_network_utils.cpp | 39 +++++++++++++++++++ .../src/utils/clock_network_utils.h | 4 +- .../src/annotation/append_clock_rr_graph.cpp | 30 ++++++++++++-- .../src/base/openfpga_read_arch_template.h | 2 +- 6 files changed, 80 insertions(+), 6 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index dcd6e828f..40397a7c9 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -155,6 +155,10 @@ std::string ClockNetwork::default_switch_name() const { return default_switch_name_; } +RRSwitchId ClockNetwork::default_switch() const { + return default_switch_id_; +} + std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const { VTR_ASSERT(valid_tree_id(tree_id)); return tree_names_[tree_id]; @@ -267,6 +271,11 @@ void ClockNetwork::set_default_segment(const RRSegmentId& seg_id) { default_segment_id_ = seg_id; } +void ClockNetwork::set_default_switch(const RRSwitchId& switch_id) { + default_switch_id_ = switch_id; +} + + void ClockNetwork::set_default_segment_name(const std::string& name) { default_segment_name_ = name; } diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 60250af86..1a093cdf0 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -72,6 +72,7 @@ class ClockNetwork { * information from RRGraph */ RRSegmentId default_segment() const; std::string default_segment_name() const; + RRSwitchId default_switch() const; std::string default_switch_name() const; std::string tree_name(const ClockTreeId& tree_id) const; size_t tree_width(const ClockTreeId& tree_id) const; @@ -116,6 +117,7 @@ class ClockNetwork { /* Reserve a number of trees to be memory efficent */ void reserve_trees(const size_t& num_trees); void set_default_segment(const RRSegmentId& seg_id); + void set_default_switch(const RRSwitchId& switch_id); void set_default_segment_name(const std::string& name); void set_default_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp index b58daf418..ffda09026 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp @@ -10,6 +10,7 @@ namespace openfpga { // Begin namespace openfpga * Link all the segments that are defined in a routing resource graph to a given *clock network *******************************************************************/ +static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, const RRGraphView& rr_graph) { /* default segment id */ @@ -26,4 +27,42 @@ int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, return CMD_EXEC_FATAL_ERROR; } +/******************************************************************** + * Link all the switches that are defined in a routing resource graph to a given + *clock network + *******************************************************************/ +static +int link_clock_network_rr_switches(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph) { + /* default switch id */ + std::string default_switch_name = clk_ntwk.default_switch_name(); + for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches(); + ++rr_switch_id) { + if (std::string(rr_graph.rr_switch_inf(RRSwitchId(rr_switch_id)).name) == + default_switch_name) { + clk_ntwk.set_default_switch(RRSwitchId(rr_switch_id)); + return CMD_EXEC_SUCCESS; + } + } + + return CMD_EXEC_FATAL_ERROR; +} + +int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph) { + int status = CMD_EXEC_SUCCESS; + + status = link_clock_network_rr_segments(clk_ntwk, rr_graph); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + status = link_clock_network_rr_switches(clk_ntwk, rr_graph); + if (CMD_EXEC_FATAL_ERROR == status) { + return status; + } + + return status; +} + + } // End of namespace openfpga diff --git a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h index faa348989..0a266c188 100644 --- a/libs/libclkarchopenfpga/src/utils/clock_network_utils.h +++ b/libs/libclkarchopenfpga/src/utils/clock_network_utils.h @@ -13,8 +13,8 @@ namespace openfpga { // Begin namespace openfpga -int link_clock_network_rr_segments(ClockNetwork& clk_ntwk, - const RRGraphView& rr_graph); +int link_clock_network_rr_graph(ClockNetwork& clk_ntwk, + const RRGraphView& rr_graph); } // End of namespace openfpga diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 6eb06c1c1..476ed6a3f 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -164,6 +164,29 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, } } +/******************************************************************** + * Add edges for the clock nodes in a given connection block + * For example + * + * clk0_lvl1_chany[1][2] + * ^ + * | + * clk0_lvl0_chanx[1][1] -->---------+--->---> clk0_lvl0_chanx[2][1] + * | + * v + * clk0_lvl1_chany[1][1] + *******************************************************************/ +static +std::vector find_clock_track2track_node(const vtr::Point& chan_coord, + const ClockTreeId& clk_tree, + const ClockLevelId& clk_lvl, + const ClockTreePinId& clk_pin, + const Direction& direction) { + std::vector des_nodes; + + return des_nodes +} + /******************************************************************** * Add edges for the clock nodes in a given connection block *******************************************************************/ @@ -179,10 +202,10 @@ static void add_rr_graph_block_clock_edges( /* find the driver clock node through lookup */ RRNodeId src_node = clk_rr_lookup.find_node( chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir); - VTR_ASSERT(driver_node); + VTR_ASSERT(src_node); /* TODO: find the fan-out clock node through lookup */ for (RRNodeId des_node : find_clock_track2track_node(chan_coord, itree, ilvl, ipin, node_dir)) { - /* TODO: Create edges */ + /* Create edges */ VTR_ASSERT(des_node); rr_graph_builder.create_edge(src_node, des_node, clk_ntwk.default_switch()); edge_count++; @@ -207,7 +230,8 @@ static void add_rr_graph_block_clock_edges( *clock tree may contain multiple clocks) * - clock nodes can only drive clock nodes (by making a turn, straight *connection is not allowed) which are 1 level lower in the same clock tree with - *the same clock index For example + *the same clock index + * For example * * clk0_lvl1_chany[1][2] * ^ diff --git a/openfpga/src/base/openfpga_read_arch_template.h b/openfpga/src/base/openfpga_read_arch_template.h index c60b91452..65daa4f27 100644 --- a/openfpga/src/base/openfpga_read_arch_template.h +++ b/openfpga/src/base/openfpga_read_arch_template.h @@ -237,7 +237,7 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd, read_xml_clock_network(arch_file_name.c_str()); /* Build internal links */ openfpga_context.mutable_clock_arch().link(); - link_clock_network_rr_segments(openfpga_context.mutable_clock_arch(), + link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(), g_vpr_ctx.device().rr_graph); /* Ensure clean data */ openfpga_context.clock_arch().validate();