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[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed

This commit is contained in:
tangxifan 2023-05-27 12:13:16 -07:00
parent e1feebc96d
commit b6c90eb99a
6 changed files with 48 additions and 31 deletions
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7
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -116,8 +116,9 @@ static void print_verilog_top_random_testbench_benchmark_instance(
print_verilog_testbench_benchmark_instance(
fp, reference_verilog_top_name, std::string(BENCHMARK_INSTANCE_NAME),
std::string(), std::string(), std::string(),
std::string(BENCHMARK_PORT_POSTFIX), std::vector<std::string>(), atom_ctx,
netlist_annotation, pin_constraints, bus_group, explicit_port_mapping);
std::string(BENCHMARK_PORT_POSTFIX), std::vector<std::string>(), false,
atom_ctx, netlist_annotation, pin_constraints, bus_group,
explicit_port_mapping);
print_verilog_comment(
fp, std::string("----- End reference Benchmark Instanication -------"));
@ -147,7 +148,7 @@ static void print_verilog_random_testbench_fpga_instance(
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)),
std::string(FPGA_INSTANCE_NAME), std::string(), std::string(),
std::string(), std::string(FPGA_PORT_POSTFIX), std::vector<std::string>(),
atom_ctx, netlist_annotation, pin_constraints, bus_group,
false, atom_ctx, netlist_annotation, pin_constraints, bus_group,
explicit_port_mapping);
print_verilog_comment(

43
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
View File

@ -46,7 +46,7 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
const PlacementContext& place_ctx, const IoLocationMap& io_location_map,
const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& global_ports,
const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group,
const VprNetlistAnnotation& netlist_annotation,
const std::string& net_name_postfix,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
@ -265,18 +265,19 @@ static void print_verilog_mock_fpga_wrapper_connect_ios(
* this pre-configured FPGA top module
*******************************************************************/
static int print_verilog_mock_fpga_wrapper_connect_global_ports(
std::fstream &fp, const ModuleManager &module_manager,
const ModuleId &top_module, const PinConstraints &pin_constraints,
const FabricGlobalPortInfo &fabric_global_ports,
const std::vector<std::string> &benchmark_clock_port_names) {
std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& top_module, const PinConstraints& pin_constraints,
const FabricGlobalPortInfo& fabric_global_ports,
const std::vector<std::string>& benchmark_clock_port_names) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_comment(
fp,
std::string("----- Begin Connect Global ports to FPGA top-level interface -----"));
std::string(
"----- Begin Connect Global ports to FPGA top-level interface -----"));
for (const FabricGlobalPortId &global_port_id :
for (const FabricGlobalPortId& global_port_id :
fabric_global_ports.global_ports()) {
ModulePortId module_global_port_id =
fabric_global_ports.global_module_port(global_port_id);
@ -292,9 +293,9 @@ static int print_verilog_mock_fpga_wrapper_connect_global_ports(
*/
for (size_t pin_id = 0; pin_id < module_global_port.pins().size();
++pin_id) {
BasicPort module_clock_pin(
module_global_port.get_name(),
module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
BasicPort module_clock_pin(module_global_port.get_name(),
module_global_port.pins()[pin_id],
module_global_port.pins()[pin_id]);
/* If the clock port name is in the pin constraints, we should wire it
* to the constrained pin */
@ -326,6 +327,7 @@ static int print_verilog_mock_fpga_wrapper_connect_global_ports(
}
clock_name_to_connect = benchmark_clock_port_names[pin_id];
}
clock_name_to_connect += std::string(APPINST_PORT_POSTFIX);
BasicPort benchmark_clock_pin(clock_name_to_connect, 1);
print_verilog_wire_connection(fp, benchmark_clock_pin, module_clock_pin,
@ -345,10 +347,13 @@ static int print_verilog_mock_fpga_wrapper_connect_global_ports(
/* If the global port name is in the pin constraints, we should wire it to
* the constrained pin */
std::string constrained_net_name =
pin_constraints.pin_net(module_global_pin) + std::string(APPINST_PORT_POSTFIX);
pin_constraints.pin_net(module_global_pin);
if (constrained_net_name.empty()) {
continue;
}
constrained_net_name += std::string(APPINST_PORT_POSTFIX);
module_global_pin.set_name(
module_global_port.get_name());
module_global_pin.set_name(module_global_port.get_name());
/* - If constrained to a given net in the benchmark, we connect the global
* pin to the net
@ -365,7 +370,8 @@ static int print_verilog_mock_fpga_wrapper_connect_global_ports(
}
print_verilog_comment(
fp, std::string("----- End Connect Global ports to FPGA top-level interface -----"));
fp, std::string(
"----- End Connect Global ports to FPGA top-level interface -----"));
/* Add an empty line as a splitter */
fp << std::endl;
@ -373,7 +379,6 @@ static int print_verilog_mock_fpga_wrapper_connect_global_ports(
return CMD_EXEC_SUCCESS;
}
/********************************************************************
* Top-level function to generate a Verilog module of
* a mock FPGA wrapper which contains an benchmark instance.
@ -444,7 +449,7 @@ int print_verilog_mock_fpga_wrapper(
/* Print local wires */
print_verilog_testbench_shared_input_ports(
fp, module_manager, global_ports, pin_constraints, atom_ctx,
netlist_annotation, benchmark_clock_port_names,
netlist_annotation, benchmark_clock_port_names, true,
std::string(APPINST_PORT_POSTFIX), false);
print_verilog_testbench_shared_benchmark_output_ports(
@ -454,8 +459,8 @@ int print_verilog_mock_fpga_wrapper(
print_verilog_testbench_benchmark_instance(
fp, circuit_name, std::string(APP_INSTANCE_NAME), std::string(),
std::string(), std::string(APPINST_PORT_POSTFIX),
std::string(APPINST_PORT_POSTFIX), benchmark_clock_port_names, atom_ctx,
netlist_annotation, pin_constraints, bus_group,
std::string(APPINST_PORT_POSTFIX), benchmark_clock_port_names, true,
atom_ctx, netlist_annotation, pin_constraints, bus_group,
options.explicit_port_mapping());
/* Connect FPGA top module global ports to constant or benchmark global
@ -470,7 +475,7 @@ int print_verilog_mock_fpga_wrapper(
/* Connect I/Os to benchmark I/Os or constant driver */
print_verilog_mock_fpga_wrapper_connect_ios(
fp, module_manager, top_module, atom_ctx, place_ctx, io_location_map,
pin_constraints, global_ports, netlist_annotation, bus_group, std::string(),
pin_constraints, global_ports, netlist_annotation, std::string(),
std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);

17
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -78,7 +78,8 @@ void print_verilog_testbench_benchmark_instance(
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix, const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names, const AtomContext& atom_ctx,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const bool& use_explicit_port_map) {
@ -183,6 +184,8 @@ void print_verilog_testbench_benchmark_instance(
clock_port_names.end(),
port_names[iport])) {
fp << input_port_postfix;
} else if (include_clock_port_postfix) {
fp << input_port_postfix;
}
pin_counter++;
@ -206,6 +209,8 @@ void print_verilog_testbench_benchmark_instance(
clock_port_names.end(),
port_names[iport])) {
fp << input_port_postfix;
} else if (include_clock_port_postfix) {
fp << input_port_postfix;
}
}
@ -922,7 +927,8 @@ void print_verilog_testbench_shared_input_ports(
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& shared_input_port_postfix, const bool& use_reg_port) {
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
const bool& use_reg_port) {
/* Validate the file stream */
valid_file_stream(fp);
@ -945,7 +951,9 @@ void print_verilog_testbench_shared_input_ports(
if (clock_port_names.end() != std::find(clock_port_names.begin(),
clock_port_names.end(),
block_name)) {
continue;
if (!include_clock_ports) {
continue;
}
}
/* Each logical block assumes a single-width port */
@ -1114,7 +1122,8 @@ void print_verilog_testbench_shared_ports(
const std::string& check_flag_port_postfix, const bool& no_self_checking) {
print_verilog_testbench_shared_input_ports(
fp, module_manager, global_ports, pin_constraints, atom_ctx,
netlist_annotation, clock_port_names, shared_input_port_postfix, true);
netlist_annotation, clock_port_names, false, shared_input_port_postfix,
true);
print_verilog_testbench_shared_fpga_output_ports(
fp, atom_ctx, netlist_annotation, fpga_output_port_postfix);

6
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -38,7 +38,8 @@ void print_verilog_testbench_benchmark_instance(
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix, const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names, const AtomContext& atom_ctx,
const std::vector<std::string>& clock_port_names,
const bool& include_clock_port_postfix, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const bool& use_explicit_port_map);
@ -96,7 +97,8 @@ void print_verilog_testbench_shared_input_ports(
const PinConstraints& pin_constraints, const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const std::string& shared_input_port_postfix, const bool& use_reg_port);
const bool& include_clock_ports, const std::string& shared_input_port_postfix,
const bool& use_reg_port);
void print_verilog_testbench_shared_fpga_output_ports(
std::fstream& fp, const AtomContext& atom_ctx,

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1146,7 +1146,7 @@ static void print_verilog_top_testbench_benchmark_instance(
std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME), std::string(),
std::string(), std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), clock_port_names,
atom_ctx, netlist_annotation, pin_constraints, bus_group,
false, atom_ctx, netlist_annotation, pin_constraints, bus_group,
explicit_port_mapping);
print_verilog_comment(

4
openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
View File

@ -52,8 +52,8 @@ write_mock_fpga_wrapper --file ./SRC ${OPENFPGA_MOCK_WRAPPER_OPTIONS} ${OPENFPGA
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream none --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
write_preconfigured_fabric_wrapper --embed_bitstream none --file ./SRC --explicit_port_mapping ${OPENFPGA_MOCK_WRAPPER_BGF} ${OPENFPGA_MOCK_WRAPPER_PCF}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping ${OPENFPGA_MOCK_WRAPPER_BGF} ${OPENFPGA_MOCK_WRAPPER_PCF}
# Write the SDC files for PnR backend
# - Turn on every options here