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[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;

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tangxifan 2021-05-24 13:03:40 -06:00
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75
docs/source/manual/arch_lang/circuit_model_examples.rst
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@ -963,16 +963,15 @@ This example shows:
.. note:: If the embedded harden logic are driven partially by LUT outputs, users may use the :ref:`file_formats_bitstream_setting` to gaurantee correct bitstream generation for the LUTs.
Flip-Flops
~~~~~~~~~~
Datapath Flip-Flops
~~~~~~~~~~~~~~~~~~~
Template
````````
.. code-block:: xml
<circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<circuit_model type="ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
@ -987,16 +986,14 @@ Template
.. note:: FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. option:: <circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
.. option:: type="ff"
- ``type="ccff|ff"`` Specify the type of a flip-flop. ``ff`` is a regular flip-flop while ``ccff`` denotes a configuration-chain flip-flop
``ff`` is a regular flip-flop to be used in datapath logic, e.g., a configurable logic block.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_dff_example:
D-type Flip-Flop
@ -1029,6 +1026,68 @@ This example shows:
- The flip-flop has ``set`` and ``reset`` functionalities
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
.. _circuit_model_multi_mode_ff_example:
Multi-mode Flip-Flop
````````````````````
:numref:`fig_multi_mode_ff_circuit_model` illustrates an example of a flip-flop which can be operate in different modes.
.. _fig_multi_mode_ff_circuit_model:
.. figure:: ./figures/multi_mode_ff_circuit_model.svg
:scale: 100%
:alt: Multi-mode flip-flop example
An example of a flip-flop which can be operate in different modes
The code describing this FF is:
.. code-block:: xml
<circuit_model type="ff" name="frac_ff" prefix="frac_ff" verilog_netlist="frac_ff.v" spice_netlist="frac_ff.sp">
<port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="Reset" lib_name="RST_OP" size="1" is_global="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clock" lib_name="CLK" size="1" is_global="true"/>
<port type="sram" prefix="MODE" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A multi-mode flip-flop which is defined in a Verilog netlist ``frac_ff.v`` and a SPICE netlist ``frac_ff.sp``
- The flip-flop has a ``reset`` pin which can be either active-low or active-high, depending on the mode selection pin ``MODE``.
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
Configuration Chain Flip-Flop
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Template
````````
.. code-block:: xml
<circuit_model type="ccff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
<port type="input" prefix="<string>" size="<int>"/>
<port type="output" prefix="<string>" size="<int>"/>
<port type="clock" prefix="<string>" size="<int>"/>
</circuit_model>
.. note:: The circuit designs of configurable memory elements are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis.
.. note:: FPGA-Verilog/SPICE currently support only one clock domain for any configuration protocols in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_ccff_example:
Regular Configuration-chain Flip-flop

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docs/source/manual/arch_lang/figures/multi_mode_ff_circuit_model.svg Normal file
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11
docs/source/overview/tech_highlights.rst
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@ -42,15 +42,16 @@ Supported Circuit Designs
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` |
| | Memory | | | - :ref:`circuit_model_sram_blwl_example` |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_ccff_example` |
| | | | - :ref:`circuit_model_ccff_enable_example` |
| | | | - :ref:`circuit_model_ccff_scanable_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| Block RAM | No | Yes | - **Any size** |
| | | | - Single-port |
| | | | - Dual-port |
| | | | - Fracturable |
| Data Memory | No | Yes | - **Any size** |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_multi_mode_ff_example` |
| | | | - Single-port Block RAM |
| | | | - Dual-port Block RAM |
| | | | - Multi-mode Block RAM |
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Arithmetic | No | Yes | - **Any size** |
| | Units | | | - Multiplier |