riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added loading rr node segment indices 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2020-11-23 14:36:12 +01:00
parent a00752938b
commit b6728cf2d9
3 changed files with 20 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vpr/src/device/check_rr_graph_obj.cpp
View File

@ -70,7 +70,7 @@ static bool check_rr_graph_dangling_nodes(const RRGraph& rr_graph) {
if ((0 == rr_graph.node_fan_in(node))
&& (0 == rr_graph.node_fan_out(node))) {
/* Print a warning! */
VTR_LOG_WARN("Node %s is dangling (zero fan-in and zero fan-out)!\n",
VTR_LOG_WARN("Node %d is dangling (zero fan-in and zero fan-out)!\n",
node);
VTR_LOG_WARN("Node details for debugging:\n");
rr_graph.print_node(node);

1
vpr/src/device/rr_graph_obj.cpp
View File

@ -449,6 +449,7 @@ void RRGraph::print_node(const RRNodeId& node) const {
VTR_LOG("Node ptc: %d\n", node_ptc_num(node));
VTR_LOG("Node num in_edges: %d\n", node_in_edges(node).size());
VTR_LOG("Node num out_edges: %d\n", node_out_edges(node).size());
VTR_LOG("Node segment id: %d\n", node_segment(node));
}
/* Check if the segment id of a node is in range */

26
vpr/src/route/rr_graph_reader.cpp
View File

@ -129,6 +129,11 @@ void load_rr_file(const t_graph_type graph_type,
VTR_LOG("Starting build routing resource graph...\n");
/* Add segments */
for (const auto& inf : segment_inf) {
device_ctx.rr_graph.create_segment(inf);
}
next_component = get_first_child(rr_graph, "channels", loc_data);
t_chan_width nodes_per_chan;
process_channels(nodes_per_chan, grid, next_component, loc_data);
@ -163,6 +168,15 @@ void load_rr_file(const t_graph_type graph_type,
//edge subsets. Must be done after RR switches have been allocated
device_ctx.rr_graph.rebuild_node_edges();
//sets the cost index and seg id information
next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
process_seg_id(next_component, loc_data);
/* Essential check for rr_graph, build look-up */
if (false == device_ctx.rr_graph.validate()) {
/* Error out if built-in validator of rr_graph fails */
@ -172,14 +186,6 @@ void load_rr_file(const t_graph_type graph_type,
"Fundamental errors occurred when validating rr_graph object!\n");
}
//sets the cost index and seg id information
next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
process_seg_id(next_component, loc_data);
device_ctx.chan_width = nodes_per_chan;
device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
@ -292,6 +298,10 @@ void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
if (attribute) {
int seg_id = get_attribute(segmentSubnode, "segment_id", loc_data).as_int(0);
device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = seg_id;
// Assign node to a segment
device_ctx.rr_graph.set_node_segment(node, RRSegmentId(seg_id));
} else {
//-1 for non chanx or chany nodes
device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = -1;