add memory ports and nets to intermediate pb_types

vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp

@@ -814,6 +814,31 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
   }
 }
 
+/********************************************************************
+ * Find the size of shared(reserved) configuration ports for module 
+ *******************************************************************/
+size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
+                                          const ModuleId& module_id) {
+  std::vector<std::string> shared_config_port_names;
+  shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB));
+  shared_config_port_names.push_back(generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL));
+  size_t num_shared_config_bits = 0; /* By default it has zero configuration bits*/
+
+  /* Try to find these ports in the module manager */
+  for (const std::string& shared_config_port_name : shared_config_port_names) {
+    ModulePortId module_port_id = module_manager.find_module_port(module_id, shared_config_port_name);
+    /* If the port does not exist, go to the next */
+    if (false == module_manager.valid_module_port_id(module_id, module_port_id)) {
+      continue;
+    }
+    /* The port exist, find the port size and update the num_config_bits if the size is larger */
+    BasicPort module_port = module_manager.module_port(module_id, module_port_id);
+    num_shared_config_bits = std::max((int)num_shared_config_bits, (int)module_port.get_width());
+  }
+
+  return num_shared_config_bits;
+}
+
 /********************************************************************
  * Find the size of configuration ports for module 
  *******************************************************************/
@@ -917,6 +942,49 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
   } 
 }
 
+/********************************************************************
+ * Find the number of shared configuration bits for a module 
+ * by selected the maximum number of shared configuration bits of child modules
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                             const ModuleId& module_id) {
+  size_t num_shared_config_bits = 0;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_module_num_shared_config_bits(module_manager, child));
+  } 
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * Find the number of configuration bits for a module 
+ * by summing up the number of configuration bits of child modules
+ *
+ * Note: This function should be call ONLY after all the sub modules (instances)
+ * have been added to the pb_module!
+ * Otherwise, some global ports of the sub modules may be missed!
+ *******************************************************************/
+size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const CircuitModelId& sram_model,
+                                                      const e_sram_orgz& sram_orgz_type) {
+  size_t num_config_bits = 0;
+
+  /* Iterate over the child modules */
+  for (const ModuleId& child : module_manager.child_modules(module_id)) {
+    num_config_bits += find_module_num_config_bits(module_manager, child, circuit_lib, sram_model, sram_orgz_type);
+  } 
+
+  return num_config_bits;
+}
+
 
 /********************************************************************
  * TODO:

vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h

@@ -76,6 +76,9 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
                                        const e_sram_orgz& sram_orgz_type, 
                                        const e_spice_model_design_tech& mem_tech);
 
+size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
+                                          const ModuleId& module_id);
+
 size_t find_module_num_config_bits(const ModuleManager& module_manager,
                                    const ModuleId& module_id,
                                    const CircuitLibrary& circuit_lib,
@@ -88,4 +91,13 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
 void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, 
                                               const ModuleId& module_id);
 
+size_t find_module_num_shared_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                             const ModuleId& module_id);
+
+size_t find_module_num_config_bits_from_child_modules(ModuleManager& module_manager, 
+                                                      const ModuleId& module_id,
+                                                      const CircuitLibrary& circuit_lib,
+                                                      const CircuitModelId& sram_model,
+                                                      const e_sram_orgz& sram_orgz_type);
+
 #endif

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp

@@ -775,17 +775,33 @@ void print_verilog_physical_blocks_rec(std::fstream& fp,
    */
   add_module_gpio_ports_from_child_modules(module_manager, pb_module);
 
-  /* TODO: Count shared SRAM ports from the sub-modules under this Verilog module
+  /* Count shared SRAM ports from the sub-modules under this Verilog module
    * This is a much easier job after adding sub modules (instances), 
    * we just need to find all the I/O ports from the child modules and build a list of it
    */
+  size_t module_num_shared_config_bits = find_module_num_shared_config_bits_from_child_modules(module_manager, pb_module); 
+  if (0 < module_num_shared_config_bits) {
+    add_reserved_sram_ports_to_module_manager(module_manager, pb_module, module_num_shared_config_bits);
+  }
 
-  /* TODO: Count SRAM ports from the sub-modules under this Verilog module
+  /* Count SRAM ports from the sub-modules under this Verilog module
    * This is a much easier job after adding sub modules (instances), 
    * we just need to find all the I/O ports from the child modules and build a list of it
    */
+  size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type); 
+  printf("Add %lu configuration bits to module %s\n", module_num_config_bits, module_manager.module_name(pb_module).c_str());
+  if (0 < module_num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, pb_module, circuit_lib, sram_model, cur_sram_orgz_info->type, module_num_config_bits);
+  }
 
-  /* TODO: Add module nets to connect memory cells inside */
+  /* Add module nets to connect memory cells inside
+   * This is a one-shot addition that covers all the memory modules in this pb module!
+   */
+  if (false == memory_modules.empty()) {
+    add_module_nets_memory_config_bus(module_manager, pb_module, 
+                                      memory_modules, memory_instances,
+                                      cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model));
+  }
 
   /* Comment lines */
   print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
@@ -857,8 +873,8 @@ void print_verilog_grid(ModuleManager& module_manager,
   /* Print preprocessing flags */
   print_verilog_include_defines_preproc_file(fp, verilog_dir);
 
-  /* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */
+  /* Print Verilog modules for all the pb_types/pb_graph_nodes
-  /* TODO: use a Depth-First Search Algorithm to print the sub-modules 
+   * use a Depth-First Search Algorithm to print the sub-modules 
    * Note: DFS is the right way. Do NOT use BFS.
    * DFS can guarantee that all the sub-modules can be registered properly
    * to its parent in module manager  

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp

@@ -468,7 +468,7 @@ std::vector<BasicPort> combine_verilog_ports(const std::vector<BasicPort>& ports
     /* Identify if the port name can be potentially merged: if the port name is already in the merged port list, it may be merged */
     bool merged = false;
     for (auto& merged_port : merged_ports) {
-      if (0 != port.get_name().compare(merged_port.get_name())) {
+      if (false == port.mergeable(merged_port)) {
         /* Unable to merge, Go to next */
         continue;
       }