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streamline regression tes

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tangxifan 2019-11-01 15:23:38 -06:00
parent 000f93ffd7
commit b54bec1609
1 changed files with 1 additions and 1 deletions
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.travis/script.sh
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@ -23,7 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py single_mode
#python3 openfpga_flow/scripts/run_fpga_task.py s298 #python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures"; echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4 python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
echo -e "Testing compact routing techniques"; echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing python3 openfpga_flow/scripts/run_fpga_task.py compact_routing