From b4c587f10b083b4f430abb63b6624ae7c6d8e221 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Jun 2021 19:58:15 -0600 Subject: [PATCH] [Test] Added the new test cases to regression tests --- .../regression_test_scripts/fpga_verilog_reg_test.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 9c51ef6ea..044821b3e 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -136,3 +136,7 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs echo -e "Testing through channels in tileable routing"; run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs + +echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators"; +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs