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Merge branch 'master' into gg_ci_cd_dev

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Ganesh Gore 2021-10-18 11:17:57 -06:00
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59
.github/ISSUE_TEMPLATE/bug_report.md vendored
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@ -7,26 +7,49 @@ assignees: ''
---
**Describe the bug**
A clear and concise description of what the bug is.
> **Describe the bug**
> A clear and concise description of what the bug is.
<!--- Uncomment relevant options --->
<!-- Which part of OpenFPGA is buggy -->
<!--- [ ] Documentation --->
<!--- [ ] OpenFPGA flow --->
<!--- [ ] FPGA-Verilog --->
<!--- [ ] FPGA-Bitstream --->
<!--- [ ] FPGA-SDC --->
<!--- [ ] FPGA-SPICE --->
<!--- [ ] VPR --->
<!--- [ ] Yosys --->
**To Reproduce**
Steps to reproduce the behavior:
1. Go to '...'
2. Click on '....'
3. Scroll down to '....'
4. See error
> **To Reproduce**
> Steps to reproduce the behavior:
> 1. Clone OpenFPGA repository and checkout commit id: <The problem commit id>
> 2. Execute OpenFPGA task or your own example: <more details>
> 3. See error
**Expected behavior**
A clear and concise description of what you expected to happen.
> **Expected behavior**
> A clear and concise description of what you expected to happen.
**Screenshots**
If applicable, add screenshots to help explain your problem.
> **Screenshots**
> If applicable, add screenshots to help explain your problem.
**Enviornment (please complete the following information):**
- OS: [e.g. CentOs, Ubuntu]
- Compiler [e.g. gcc, clang]
- Version [e.g. Github commit id]
> **Enviornment (please complete the following information):**
<!--- Uncomment relevant options --->
> - OS:
<!--- - [ ] CentOS 7 --->
<!--- - [ ] Ubuntu 18.04 --->
<!--- - [ ] Others. If so, please specify: --->
> - Compiler:
<!--- - [ ] gcc-5 --->
<!--- - [ ] gcc-6 --->
<!--- - [ ] gcc-7 --->
<!--- - [ ] gcc-8 --->
<!--- - [ ] gcc-9 --->
<!--- - [ ] clang-6 --->
<!--- - [ ] clang-8 --->
<!--- - [ ] Others. If so, please specify: --->
> - Version:
<!--- - [ ] Current master --->
<!--- - [ ] Others. If so, please specify Github commit id: --->
**Additional context**
Add any other context about the problem here.
> **Additional context**
> Add any other context about the problem here.

64
.github/PULL_REQUEST_TEMPLATE.md vendored
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@ -1,33 +1,39 @@
---
name: Pull request
about: Push a change to this project
---
> ### Motivate of the pull request
> - [ ] To address an existing issue. If so, please provide a link to the issue: <issue id>
> - [ ] Breaking new feature. If so, please describe details in the description part.
### Motivate of the pull request
- [ ] To address an existing issue. If so, please provide a link to the issue.
- [ ] Breaking new feature. If so, please decribe details in the description part.
> ### Describe the technical details
> #### What is currently done? (Provide issue link if applicable)
> <!-- Please provide a list of limitations if not specified in any issue -->
> <!-- Below is a template, uncomment upon your needs -->
> <!-- Currently, OpenFPGA has the following limitations: -->
> <!-- - [ ] technical details about limitation -->
> <!-- - [ ] more limitations -->
>
> #### What does this pull request change?
> <!-- Please provide a list of highlights of your changes. -->
> <!-- Below is a template, uncomment upon your needs -->
> <!-- This PR improves in the following aspects: -->
> <!-- - [ ] details about the technical highlight -->
> <!-- - [ ] <more technical highlights -->
### Describe the technical details
- What is currently done? (Provide issue link if applicable)
- What does this pull request change?
> ### Which part of the code base require a change
> <!-- In general, modification on existing submodules are not acceptable. You should push changes to upstream. -->
> - [ ] VPR
> - [ ] Tileable routing architecture generator
> - [ ] OpenFPGA libraries
> - [ ] FPGA-Verilog
> - [ ] FPGA-Bitstream
> - [ ] FPGA-SDC
> - [ ] FPGA-SPICE
> - [ ] Flow scripts
> - [ ] Architecture library
> - [ ] Cell library
> - [ ] Documentation
> - [ ] Regression tests
> - [ ] Continous Integration (CI) scripts
### Which part of the code base require a change
**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
- [ ] VPR
- [ ] OpenFPGA libraries
- [ ] FPGA-Verilog
- [ ] FPGA-Bitstream
- [ ] FPGA-SDC
- [ ] FPGA-SPICE
- [ ] Flow scripts
- [ ] Architecture library
- [ ] Cell library
> ### Impact of the pull request
### Checklist of the pull request
- [ ] Require code changes.
- [ ] Require new tests to be added
- [ ] Require an update on documentation
### Impact of the pull request
- [ ] Require a change on Quality of Results (QoR)
- [ ] Break back-compatibility. If so, please list who may be influenced.
> - [ ] Require a change on Quality of Results (QoR)
> - [ ] Break back-compatibility. If so, please list who may be influenced.

64
.github/PULL_REQUEST_TEMPLATE/pull_request_template.md vendored
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@ -1,33 +1,39 @@
---
name: Pull request
about: Push a change to this project
---
> ### Motivate of the pull request
> - [ ] To address an existing issue. If so, please provide a link to the issue: <issue id>
> - [ ] Breaking new feature. If so, please describe details in the description part.
### Motivate of the pull request
- [ ] To address an existing issue. If so, please provide a link to the issue.
- [ ] Breaking new feature. If so, please decribe details in the description part.
> ### Describe the technical details
> #### What is currently done? (Provide issue link if applicable)
> <!-- Please provide a list of limitations if not specified in any issue -->
> <!-- Below is a template, uncomment upon your needs -->
> <!-- Currently, OpenFPGA has the following limitations: -->
> <!-- - [ ] technical details about limitation -->
> <!-- - [ ] more limitations -->
>
> #### What does this pull request change?
> <!-- Please provide a list of highlights of your changes. -->
> <!-- Below is a template, uncomment upon your needs -->
> <!-- This PR improves in the following aspects: -->
> <!-- - [ ] details about the technical highlight -->
> <!-- - [ ] <more technical highlights -->
### Describe the technical details
- What is currently done? (Provide issue link if applicable)
- What does this pull request change?
> ### Which part of the code base require a change
> <!-- In general, modification on existing submodules are not acceptable. You should push changes to upstream. -->
> - [ ] VPR
> - [ ] Tileable routing architecture generator
> - [ ] OpenFPGA libraries
> - [ ] FPGA-Verilog
> - [ ] FPGA-Bitstream
> - [ ] FPGA-SDC
> - [ ] FPGA-SPICE
> - [ ] Flow scripts
> - [ ] Architecture library
> - [ ] Cell library
> - [ ] Documentation
> - [ ] Regression tests
> - [ ] Continous Integration (CI) scripts
### Which part of the code base require a change
**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
- [ ] VPR
- [ ] OpenFPGA libraries
- [ ] FPGA-Verilog
- [ ] FPGA-Bitstream
- [ ] FPGA-SDC
- [ ] FPGA-SPICE
- [ ] Flow scripts
- [ ] Architecture library
- [ ] Cell library
> ### Impact of the pull request
### Checklist of the pull request
- [ ] Require code changes.
- [ ] Require new tests to be added
- [ ] Require an update on documentation
### Impact of the pull request
- [ ] Require a change on Quality of Results (QoR)
- [ ] Break back-compatibility. If so, please list who may be influenced.
> - [ ] Require a change on Quality of Results (QoR)
> - [ ] Break back-compatibility. If so, please list who may be influenced.

6
.github/workflows/build.yml vendored
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@ -210,7 +210,10 @@ jobs:
- name: fpga_bitstream_reg_test
- name: fpga_sdc_reg_test
- name: fpga_spice_reg_test
- name: micro_benchmark_reg_test
- name: quicklogic_reg_test
- name: vtr_benchmark_reg_test
- name: iwls_benchmark_reg_test
steps:
- name: Checkout OpenFPGA repo
uses: actions/checkout@v2
@ -255,7 +258,10 @@ jobs:
- name: fpga_bitstream_reg_test
- name: fpga_sdc_reg_test
- name: fpga_spice_reg_test
- name: micro_benchmark_reg_test
- name: quicklogic_reg_test
- name: vtr_benchmark_reg_test
- name: iwls_benchmark_reg_test
steps:
- name: Checkout OpenFPGA repo
uses: actions/checkout@v2

1
.github/workflows/install_dependencies_build.sh vendored
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@ -37,4 +37,5 @@ apt-get update && apt-get install -y \
texinfo \
time \
valgrind \
wget \
zip

2
.github/workflows/install_dependencies_run.sh vendored
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@ -1,4 +1,4 @@
apt-get install --no-install-recommends -y \
libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \
libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \
iverilog git rsync make curl
iverilog git rsync make curl wget

1
CMakeLists.txt
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@ -91,7 +91,6 @@ else ()
"-D__USE_FIXED_PROTOTYPES__"
"-ansi"
"-Wshadow"
"-Wcast-allign"
"-Wno-write-strings"
"-D_POSIX_SOURCE"
"-Wall" #Most warnings, typically good

8
README.md
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@ -8,14 +8,14 @@ The award-winning OpenFPGA framework is the **first open-source FPGA IP generato
**If this is the first time you learn OpenFPGA, we strongly recommend you to watch the [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo)**
A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/tools/).
We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights.html) before compiling.
A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/tools/).
We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights/#) before compiling.
## Compilation
**A tutorial video about how-to-compile can be found [here](https://youtu.be/F9sMRmDewM0)**
Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/compile).
Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/compile/).
It also includes detailed information about docker image.
---
@ -55,4 +55,4 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl
## Tutorials
You can find some tutorials in the [**./tutorials**](./docs/source/tutorials/) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.
You can find a set of [tutorials](https://openfpga.readthedocs.io/en/master/tutorials/), with which you get familiar with the tool and use OpenFPGA in various purposes.

47
docs/source/faq.rst Normal file
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@ -0,0 +1,47 @@
.. _faq:
Frequently Asked Questions
==========================
Where is the best place to get help with OpenFPGA?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Currently, we have an active github issues page found `here <https://github.com/lnis-uofu/OpenFPGA/issues>`_. Users can see if their
questions have already been answered by searching the open or closed issues, and users are recommended to post questions there first.
Asking questions on the github issues page allows us to answer the question for everyone who may be experiencing similar problems as
well.
What should I do if check-in tests failed when first installing OpenFPGA?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
First, check to make sure all dependencies for OpenFPGA and Python have been installed and are up-to-date on the desired device. To see the full
list of depenencies, please visit
`our github dependencies page <https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh>`_.
This issue has been discussed `in issue 280 <https://github.com/lnis-uofu/OpenFPGA/issues/280>`_.
How to sweep design parameters in a task run of OpenFPGA design flow?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Testing multiple script parameters for a variable is possible by modifying the task.conf file. Doing so will create a job for
each combination of the variables. A solution is discussed `in issue 228 <https://github.com/lnis-uofu/OpenFPGA/issues/228>`_.
How do I setup OpenFPGA to be used by multiple users on a single device?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
OpenFPGA can support multiple users on a shared device using the environment variable ``OPENFPGA_ROOT``. The OpenFPGA script for
running tasks needs ``OPENFPGA_ROOT`` to be the path to the OpenFPGA root directory. Users can then run the script on a task in the
current working directory. A solution is discussed `in issue 209 <https://github.com/lnis-uofu/OpenFPGA/issues/209>`_.
How do I contribute to OpenFPGA?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Users of OpenFPGA that are interested in contributing must complete the following:
- Create a branch. For external collaborators, please fork the repository first and create a branch in the fork.
- Creatre a pull request and fill out our pull request template. It is easy for us to acknowledge and review your pull request.
- Wait or keep debugging until all the CI tests pass.
- Request for a review. You may expect several rounds of review and discussion before the pull request is approved.

1
docs/source/index.rst
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@ -36,6 +36,7 @@ Welcome to OpenFPGA's documentation!
contact
reference
faq
For more information on the VTR see vtr_doc_ or vtr_github_

29
docs/source/manual/arch_lang/annotate_vpr_arch.rst
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@ -136,6 +136,8 @@ When a global port, e.g., ``clk``, is defined in ``tile_annotation`` using the f
Clock port ``clk`` of each ``clb`` tile will be connected to a common clock port of the top module, while local clock network is customizable through VPR's architecture description language. For instance, the local clock network can be a programmable clock network.
.. _annotate_vpr_arch_pb_type_annotation:
Primitive Blocks inside Multi-mode Configurable Logic Blocks
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -221,7 +223,9 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
.. note:: A ``<pb_type name="<string>">`` parent XML node is required for the interconnect-to-circuit bindings whose interconnects are defined under the ``pb_type`` in VPR architecture description.
.. option:: <port name="<string>" physical_mode_port="<string>"
physical_mode_pin_initial_offset="<int>" physical_mode_pin_rotate_offset="<int>"/>
physical_mode_pin_initial_offset="<int>"
physical_mode_pin_rotate_offset="<int>"/>
physical_mode_port_rotate_offset="<int>"/>
Link a port of an operating ``pb_type`` to a port of a physical ``pb_type``
@ -231,7 +235,6 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
.. note:: Users can define multiple ports. For example: ``physical_mode_pin="a[0:1] b[2:2]"``. When multiple ports are used, the ``physical_mode_pin_initial_offset`` and ``physical_mode_pin_rotate_offset`` should also be adapt. For example: ``physical_mode_pin_rotate_offset="1 0"``)
- ``physical_mode_pin_initial_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when part of port of operating mode is mapped to a port in physical ``pb_type``. When ``physical_mode_pin_initial_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
.. note:: A quick example to understand the initial offset
@ -247,7 +250,24 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
.. note:: If not defined, the default value of ``physical_mode_pin_initial_offset`` is set to ``0``.
- ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
- ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset, **each time a pin in the operating mode is binded to a pin in the physical mode**.
.. note:: A quick example to understand the rotate offset
For example, a rotating offset of 9 is used to map
- operating pb_type ``mult_9x9[0].a[0]`` with a full path ``mult[frac].mult_9x9[0]``
- operating pb_type ``mult_9x9[1].a[1]`` with a full path ``mult[frac].mult_9x9[1]``
to
- physical pb_type ``mult_36x36.a[0]`` with a full path ``mult[physical].mult_36x36[0]``
- physical pb_type ``mult_36x36.a[9]`` with a full path ``mult[physical].mult_36x36[0]``
.. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``.
.. warning:: The result of using ``physical_mode_pin_rotate_offset`` is fundementally different than ``physical_mode_port_rotate_offset``!!! Please read the examples carefully and pick the one fitting your needs.
- ``physical_mode_port_rotate_offset="<int>"`` aims to align the port indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_port_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset, **only when all the pins of a port in the operating mode is binded to all the pins of a port in the physical mode**.
.. note:: A quick example to understand the rotate offset
For example, a rotating offset of 9 is used to map
@ -260,7 +280,8 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
- physical pb_type ``mult_36x36.a[0:8]`` with a full path ``mult[physical].mult_36x36[0]``
- physical pb_type ``mult_36x36.a[9:17]`` with a full path ``mult[physical].mult_36x36[0]``
.. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``.
.. note:: If not defined, the default value of ``physical_mode_port_rotate_offset`` is set to ``0``.
.. note::
It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description.

218
docs/source/manual/arch_lang/circuit_model_examples.rst
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@ -284,6 +284,8 @@ This example shows:
SRAMs
~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for SRAM cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
@ -963,16 +965,17 @@ This example shows:
.. note:: If the embedded harden logic are driven partially by LUT outputs, users may use the :ref:`file_formats_bitstream_setting` to gaurantee correct bitstream generation for the LUTs.
Datapath Flip-Flops
~~~~~~~~~~~~~~~~~~~
Flip-Flops
~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for datapath flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
.. code-block:: xml
<circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<circuit_model type="ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
@ -987,16 +990,14 @@ Template
.. note:: FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. option:: <circuit_model type="ccff|ff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
.. option:: type="ff"
- ``type="ccff|ff"`` Specify the type of a flip-flop. ``ff`` is a regular flip-flop while ``ccff`` denotes a configuration-chain flip-flop
``ff`` is a regular flip-flop to be used in datapath logic, e.g., a configurable logic block.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_dff_example:
D-type Flip-Flop
@ -1029,6 +1030,70 @@ This example shows:
- The flip-flop has ``set`` and ``reset`` functionalities
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
.. _circuit_model_multi_mode_ff_example:
Multi-mode Flip-Flop
````````````````````
:numref:`fig_multi_mode_ff_circuit_model` illustrates an example of a flip-flop which can be operate in different modes.
.. _fig_multi_mode_ff_circuit_model:
.. figure:: ./figures/multi_mode_ff_circuit_model.svg
:scale: 150%
:alt: Multi-mode flip-flop example
An example of a flip-flop which can be operate in different modes
The code describing this FF is:
.. code-block:: xml
<circuit_model type="ff" name="frac_ff" prefix="frac_ff" verilog_netlist="frac_ff.v" spice_netlist="frac_ff.sp">
<port type="input" prefix="D" lib_name="D" size="1"/>
<port type="input" prefix="Reset" lib_name="RST_OP" size="1" is_global="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="clock" prefix="clock" lib_name="CLK" size="1" is_global="true"/>
<port type="sram" prefix="MODE" lib_name="MODE" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A multi-mode flip-flop which is defined in a Verilog netlist ``frac_ff.v`` and a SPICE netlist ``frac_ff.sp``
- The flip-flop has a ``reset`` pin which can be either active-low or active-high, depending on the mode selection pin ``MODE``.
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
- The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file
Configuration Chain Flip-Flop
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for configuration chain flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
.. code-block:: xml
<circuit_model type="ccff" name="<string>" prefix="<string>" spice_netlist="<string>" verilog_netlist="<string>"/>
<design_technology type="cmos"/>
<input_buffer exist="<string>" circuit_model_name="<string>"/>
<output_buffer exist="<string>" circuit_model_name="<string>"/>
<port type="input" prefix="<string>" size="<int>"/>
<port type="output" prefix="<string>" size="<int>"/>
<port type="clock" prefix="<string>" size="<int>"/>
</circuit_model>
.. note:: The circuit designs of configurable memory elements are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis.
.. note:: FPGA-Verilog/SPICE currently support only one clock domain for any configuration protocols in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``.
.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic.
.. _circuit_model_ccff_example:
Regular Configuration-chain Flip-flop
@ -1147,6 +1212,8 @@ The code describing this FF is:
Hard Logics
~~~~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for the hard logics. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````
@ -1175,6 +1242,13 @@ Template
Full Adder
``````````
.. figure:: ./figures/full_adder_1bit_circuit_model.svg
:scale: 200%
:alt: An example of a 1-bit full adder
An example of a 1-bit full adder.
The code describing the 1-bit full adder is:
.. code-block:: xml
@ -1189,6 +1263,134 @@ Full Adder
<port type="output" prefix="sumout" size="1"/>
</circuit_model>
This example shows:
- A 1-bit full adder which is defined in a Verilog netlist ``adder.v`` and a SPICE netlist ``adder.sp``
- The adder has three 1-bit inputs, i.e., ``a``, ``b`` and ``cin``, and two 2-bit outputs, i.e., ``cout``, ``sumout``.
.. _circuit_model_single_mode_mult8x8_example:
Multiplier
``````````
.. figure:: ./figures/single_mode_mult8x8_circuit_model.svg
:scale: 200%
:alt: An example of a 8-bit multiplier.
An example of a 8-bit multiplier.
The code describing the multiplier is:
.. code-block:: xml
<circuit_model type="hard_logic" name="mult8x8" prefix="mult8x8" spice_netlist="dsp.sp" verilog_netlist="dsp.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="a" size="8"/>
<port type="input" prefix="b" size="8"/>
<port type="output" prefix="out" size="16"/>
</circuit_model>
This example shows:
- A 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp``
.. _circuit_model_multi_mode_mult8x8_example:
Multi-mode Multiplier
`````````````````````
.. figure:: ./figures/multi_mode_mult8x8_circuit_model.svg
:scale: 200%
:alt: An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
The code describing the multiplier is:
.. code-block:: xml
<circuit_model type="hard_logic" name="frac_mult8x8" prefix="frac_mult8x8" spice_netlist="dsp.sp" verilog_netlist="dsp.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="a" size="8"/>
<port type="input" prefix="b" size="8"/>
<port type="output" prefix="out" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A multi-mode 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp``
- The multi-mode multiplier can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
.. _circuit_model_single_mode_dpram_example:
Dual Port Block RAM
```````````````````
.. figure:: ./figures/single_mode_dpram128x8_memory_circuit_model.svg
:scale: 150%
:alt: An example of a dual port block RAM with 128 addresses and 8-bit data width.
An example of a dual port block RAM with 128 addresses and 8-bit data width.
The code describing this block RAM is:
.. code-block:: xml
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="dpram.sp" verilog_netlist="dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="waddr" size="7"/>
<port type="input" prefix="raddr" size="7"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clock" size="1" is_global="true" default_val="0"/>
</circuit_model>
This example shows:
- A 128x8 dual port RAM which is defined in a Verilog netlist ``dpram.v`` and a SPICE netlist ``dpram.sp``
- The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`).
.. _circuit_model_multi_mode_dpram_example:
Multi-mode Dual Port Block RAM
``````````````````````````````
.. figure:: ./figures/multi_mode_dpram128x8_memory_circuit_model.svg
:scale: 150%
:alt: An example of a multi-mode dual port block RAM with 128 addresses and 8-bit data width.
An example of a dual port block RAM which can operate in two modes: 128x8 and 256x4.
The code describing this block RAM is:
.. code-block:: xml
<circuit_model type="hard_logic" name="frac_dpram_128x8" prefix="frac_dpram_128x8" spice_netlist="frac_dpram.sp" verilog_netlist="frac_dpram.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="inv1x"/>
<output_buffer exist="true" circuit_model_name="inv1x"/>
<port type="input" prefix="waddr" size="8"/>
<port type="input" prefix="raddr" size="8"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clock" size="1" is_global="true" default_val="0"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CCFF" default_value="0"/>
</circuit_model>
This example shows:
- A fracturable dual port RAM which is defined in a Verilog netlist ``frac_dpram.v`` and a SPICE netlist ``frac_dpram.sp``
- The dual port RAM can operate in two modes: (1) 128 addresses with 8-bit data width; (2) 256 addresses with 4-bit data width
- The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`).
- The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`).
Routing Wire Segments
~~~~~~~~~~~~~~~~~~~~~
@ -1255,6 +1457,8 @@ This example shows
I/O pads
~~~~~~~~
.. note:: OpenFPGA does not auto-generate any netlist for I/O cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs.
Template
````````

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.. _file_format_bitstream_distribution_file:
Bitstream Distribution File (.xml)
----------------------------------
The bitstream distribution file aims to show
- The total number of configuration bits under each block
- The number of configuration bits per block
An example of design constraints is shown as follows.
.. code-block:: xml
<block name="fpga_top" number_of_bits="527">
<block name="grid_clb_1__1_" number_of_bits="136">
</block>
<block name="grid_io_top_1__2_" number_of_bits="8">
</block>
<block name="grid_io_right_2__1_" number_of_bits="8">
</block>
<block name="grid_io_bottom_1__0_" number_of_bits="8">
</block>
<block name="grid_io_left_0__1_" number_of_bits="8">
</block>
<block name="sb_0__0_" number_of_bits="58">
</block>
<block name="sb_0__1_" number_of_bits="57">
</block>
<block name="sb_1__0_" number_of_bits="59">
</block>
<block name="sb_1__1_" number_of_bits="56">
</block>
<block name="cbx_1__0_" number_of_bits="33">
</block>
<block name="cbx_1__1_" number_of_bits="33">
</block>
<block name="cby_0__1_" number_of_bits="30">
</block>
<block name="cby_1__1_" number_of_bits="33">
</block>
</block>
.. option:: name="<string>"
The block name represents the instance name which you can find in the fabric netlists
.. option:: number_of_bits="<string>"
The total number of configuration bits in this block

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@ -6,22 +6,68 @@ Bitstream Setting (.xml)
An example of bitstream settings is shown as follows.
This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics.
.. warning:: Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
.. code-block:: xml
<openfpga_bitstream_setting>
<pb_type name="<string>" source="eblif" content=".param LUT"/>
<pb_type name="<string>" source="eblif" content=".param LUT" is_mode_select_bistream="true" bitstream_offset="1"/>
<interconnect name="<string>" default_path="<string>"/>
</openfpga_bitstream_setting>
.. option:: pb_type="<string>"
pb_type-related Settings
^^^^^^^^^^^^^^^^^^^^^^^^
The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, ``pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"``
The following syntax are applicable to the XML definition tagged by ``pb_type`` in bitstream setting files.
.. option:: name="<string>"
The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
.. code-block:: xml
pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"
.. option:: source="<string>"
The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, ``source="eblif"``.
The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example,
.. code-block:: xml
source="eblif"
.. option:: content="<string>"
The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file).
.. warning:: Bitstream is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream.
.. option:: is_mode_select_bitstream="<bool>"
Can be either ``true`` or ``false``. When set ``true``, the bitstream is considered as mode-selection bitstream, which may overwrite ``mode_bits`` definition in ``pb_type_annotation`` of OpenFPGA architecture description. (See details in :ref:`annotate_vpr_arch_pb_type_annotation`)
.. option:: bitstream_offset="<int>"
Specify the offset to be applied when overloading the bitstream to a target. For example, a LUT may have a 16-bit bitstream. When ``offset=1``, bitstream overloading will skip the first bit and start from the second bit of the 16-bit bitstream.
Interconnection-related Settings
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The following syntax are applicable to the XML definition tagged by ``interconnect`` in bitstream setting files.
.. option:: name="<string>"
The ``interconnect`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example,
.. code-block:: xml
pb_type="clb.fle[arithmetic].mux1"
.. option:: default_path="<string>"
The default path denotes an input name that is consistent with VPR's architecture description. For example, in VPR architecture, there is a mux defined as
.. code-block:: xml
<mux name="mux1" input="iopad.inpad ff.Q" output="io.inpad"/>
The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively.

80
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@ -5,7 +5,7 @@ Fabric-dependent Bitstream
.. _file_formats_fabric_bitstream_plain_text:
Plain text (.txt)
Plain text (.bit)
~~~~~~~~~~~~~~~~~
This file format is designed to be directly loaded to an FPGA fabric.
@ -19,31 +19,66 @@ The information depends on the type of configuration procotol.
.. option:: scan_chain
A line consisting of ``0`` | ``1``
Multiple lines consisting of ``0`` | ``1``
For example, a bitstream for 1 configuration regions:
.. code-block:: xml
0
1
0
0
For example, a bitstream for 4 configuration regions:
.. code-block:: xml
0000
1010
0110
0120
.. note:: When there are multiple configuration regions, each line may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
.. option:: memory_bank
Multiple lines will be included, each of which is organized as <address><space><bit>.
Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
The first line represents the Bit-Line address and configuration bit.
The second line represents the Word-Line address and configuration bit.
Multiple lines will be included, each of which is organized as <bl_address><wl_address><bits>.
The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
For example
.. code-block:: verilog
// Bitstream width (LSB -> MSB): <bl_address 5 bits><wl_address 5 bits><data input 1 bits>
The first part represents the Bit-Line address.
The second part represents the Word-Line address.
The third part represents the configuration bit.
For example
.. code-block:: xml
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address><wordline_address><bit_value>
<bitline_address><wordline_address><bit_value>
...
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address><wordline_address><bit_value>
.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
.. option:: frame_based
Multiple lines will be included, each of which is organized as <address><space><bit>.
Multiple lines will be included, each of which is organized as ``<address><data_input_bits>``.
The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
For example
.. code-block:: verilog
// Bitstream width (LSB -> MSB): <address 14 bits><data input 1 bits>
Note that the address may include don't care bit which is denoted as ``x``.
OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
.. note:: OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
For example
.. code-block:: xml
@ -53,6 +88,7 @@ The information depends on the type of configuration procotol.
...
<frame_address><bit_value>
.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
.. _file_formats_fabric_bitstream_xml:
@ -61,7 +97,21 @@ XML (.xml)
This file format is designed to generate testbenches using external tools, e.g., CocoTB.
In principle, the file consist a number of XML node ``<bit>``, each bit contains the following attributes:
In principle, the file consist a number of XML node ``<region>``, each region has a unique id, and contains a number of XML nodes ``<bit>``.
- ``id``: The unique id of a configuration region in the fabric bitstream.
A quick example:
.. code-block:: xml
<region id="0">
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
</bit>
</region>
Each XML node ``<bit>`` contains the following attributes:
- ``id``: The unique id of the configuration bit in the fabric bitstream.

4
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@ -21,3 +21,7 @@ OpenFPGA widely uses XML format for interchangable files
bitstream_setting
fabric_key
io_mapping_file
bitstream_distribution_file

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@ -0,0 +1,33 @@
.. _file_format_io_mapping_file:
I/O Mapping File (.xml)
-----------------------
The I/O mapping file aims to show
- What nets have been mapped to each I/O
- What is the directionality of each mapped I/O
An example of design constraints is shown as follows.
.. code-block:: xml
<io_mapping>
<io name="gfpga_pad_GPIO_PAD[6:6]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[1:1]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[9:9]" net="out_c" dir="output"/>
</io_mapping>
.. option:: name="<string>"
The pin name of the FPGA fabric which has been mapped, which should be a valid pin defined in OpenFPGA architecture description.
.. note:: You should be find the exact pin in the top-level module of FPGA fabric if you output the Verilog netlists.
.. option:: net="<string>"
The net name which is actually mapped to a pin, which should be consistent with net definition in your ``.blif`` file.
.. option:: dir="<string>"
The direction of an I/O, which can be either ``input`` or ``output``.

10
docs/source/manual/file_formats/pin_constraints_file.rst
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@ -10,7 +10,7 @@ An example of design constraints is shown as follows.
.. code-block:: xml
<pin_constraints>
<set_io pin="clk[0]" net="clk0"/>
<set_io pin="clk[0]" net="clk0" default_value="1"/>
<set_io pin="clk[1]" net="clk1"/>
<set_io pin="clk[2]" net="OPEN"/>
<set_io pin="clk[3]" net="OPEN"/>
@ -23,3 +23,11 @@ An example of design constraints is shown as follows.
.. option:: net="<string>"
The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
.. option:: default_value="<string>"
The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli.
.. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration.
.. note:: The default value in pin constraint file has a higher priority than the ``default_value`` syntax in the :ref:`circuit_library`.

5
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@ -3,6 +3,11 @@
Repack Design Constraints (.xml)
--------------------------------
.. warning:: For the best practice, current repack design constraints only support the net remapping between pins in the same port. Pin constraints are **NOT** allowed for two separated ports.
- A legal pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two pins in a clock port ``clk[0:2]`` (e.g., ``clk[0] = clk0`` and ``clk[1] == clk1``).
- An **illegal** pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two clock ports ``clkA[0]`` and ``clkB[0]`` (e.g., ``clkA[0] = clk0`` and ``clkB[0] == clk1``).
An example of design constraints is shown as follows.
.. code-block:: xml

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@ -16,24 +16,32 @@ In this part, we will introduce the hierarchy, dependency and functionality of e
+-----------------+---------+----------------+---------------+
OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented.
Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a).
Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization`.
To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
.. _fig_verilog_testbench_organization:
.. figure:: figures/verilog_testbench_organization.png
.. figure:: figures/full_testbench_block_diagram.svg
:scale: 50%
:alt: Functional Verification using ModelSim
:alt: Verilog testbench principles
Principles of Verilog testbenches organization: (a) block diagram and (b) waveforms.
Principles of Verilog testbenches: (1) using common input stimuli; (2) applying bitstream; (3) checking output vectors.
.. _fig_verilog_full_testbench_waveform:
.. figure:: figures/full_testbench_waveform.svg
:scale: 50%
:alt: Full testbench waveform
Illustration on the waveforms in full testbench
Full Testbench
~~~~~~~~~~~~~~
Full testbench aims at simulating an entire FPGA operating period, consisting of two phases:
- the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_testbench_organization` (b);
- the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_full_testbench_waveform`;
- the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_testbench_organization` (b). Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA.
- the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_full_testbench_waveform`. Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA.
Formal-oriented Testbench
~~~~~~~~~~~~~~~~~~~~~~~~~
@ -50,8 +58,8 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. _fig_verilog_testbench_hierarchy:
.. figure:: ./figures/verilog_testbench_hierarchy.png
:scale: 90%
.. figure:: ./figures/verilog_testbench_hierarchy.svg
:scale: 100%
Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application
@ -65,37 +73,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: Fabric Verilog netlists are included in this file.
.. option:: define_simulation.v
This file includes pre-processing flags required by the testbenches, to smooth HDL simulation.
It will include the folliwng pre-procesing flags:
- ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag.
.. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``.
- ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command.
- ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench.

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@ -69,6 +69,49 @@ write_fabric_bitstream
Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
See file formats in :ref:`file_formats_fabric_bitstream_xml` and :ref:`file_formats_fabric_bitstream_plain_text`.
.. option:: --fast_configuration
Reduce the bitstream size when outputing by skipping dummy configuration bits. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.
.. warning:: Fast configuration is only applicable to plain text file format!
.. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
.. option:: --verbose
Show verbose log
write_io_mapping
~~~~~~~~~~~~~~~~
Output the I/O mapping information to a file
.. option:: --file <string> or -f <string>
Specify the file name where the I/O mapping will be outputted to.
See file formats in :ref:`file_format_io_mapping_file`.
.. option:: --verbose
Show verbose log
report_bitstream_distribution
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Output the bitstream distribution to a file
.. option:: --file <string> or -f <string>
Specify the file name where the bitstream distribution will be outputted to.
See file formats in :ref:`file_format_bitstream_distribution_file`.
.. option:: --depth <int> or -d <int>
Specify the maximum depth of the block which should appear in the block
.. option:: --verbose
Show verbose log

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@ -6,7 +6,7 @@ FPGA-Verilog
write_fabric_verilog
~~~~~~~~~~~~~~~~~~~~
Write the Verilog netlist for FPGA fabric based on module graph
Write the Verilog netlist for FPGA fabric based on module graph. See details in :ref:`fabric_netlists`.
.. option:: --file <string> or -f <string>
@ -24,14 +24,6 @@ write_fabric_verilog
Output timing information to Verilog netlists for primitive modules
.. option:: --include_signal_init
Output signal initialization to Verilog netlists for primitive modules
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulatorcan accept
.. option:: --print_user_defined_template
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
@ -40,22 +32,28 @@ write_fabric_verilog
Show verbose log
write_verilog_testbench
write_full_testbench
~~~~~~~~~~~~~~~~~~~~~~~
Write the Verilog testbench for FPGA fabric
Write the full testbench for FPGA fabric in Verilog format. See details in :ref:`fpga_verilog_testbench`.
.. option:: --file <string> or -f <string>
The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench``
.. option:: --bitstream <string>
The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit``
.. option:: --fabric_netlist_file_path <string>
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
@ -68,22 +66,139 @@ write_verilog_testbench
.. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
.. option:: --print_top_testbench
.. option:: --explicit_port_mapping
Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
Use explicit port mapping when writing the Verilog netlists
.. option:: --print_formal_verification_top_netlist
.. option:: --default_net_type <string>
Generate a top-level module which can be used in formal verification
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --print_preconfig_top_testbench
.. option:: --include_signal_init
Enable pre-configured top-level testbench which is a fast verification skipping programming phase
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. option:: --print_simulation_ini <string>
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts. For example, ``--print_simulation_ini /temp/testbench/sim.ini``
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
Show verbose log
write_preconfigured_fabric_wrapper
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Write the Verilog wrapper for a preconfigured FPGA fabric. See details in :ref:`fpga_verilog_testbench`.
.. option:: --file <string> or -f <string>
The output directory for the netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench``
.. option:: --fabric_netlist_file_path <string>
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
.. option:: --pin_constraints_file <string> or -pcf <string>
Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml``
Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
.. option:: --explicit_port_mapping
Use explicit port mapping when writing the Verilog netlists
.. option:: --default_net_type <string>
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --embed_bitstream <string>
Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``.
.. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
.. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: --include_signal_init
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose
Show verbose log
write_preconfigured_testbench
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Write the Verilog testbench for a preconfigured FPGA fabric. See details in :ref:`fpga_verilog_testbench`.
.. option:: --file <string> or -f <string>
The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench``
.. option:: --fabric_netlist_file_path <string>
Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
.. option:: --reference_benchmark_file_path <string>
Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. note:: If not specified, the testbench will not include any self-checking feature!
.. option:: --pin_constraints_file <string> or -pcf <string>
Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml``
Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`.
.. option:: --explicit_port_mapping
Use explicit port mapping when writing the Verilog netlists
.. option:: --default_net_type <string>
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --verbose
Show verbose log
write_simulation_task_info
~~~~~~~~~~~~~~~~~~~~~~~~~~
Write an interchangeable file in ``.ini`` format to interface HDL simulators, such as iVerilog and Modelsim.
.. option:: --file <string> or -f <string>
Specify the file path to output simulation-related information. For example, ``--file simulation.ini``
.. option:: --hdl_dir <string>
Specify the directory path where HDL netlists are created. For example, ``--hdl_dir ./SRC``
.. option:: --reference_benchmark_file_path <string>
Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v``
.. option:: --testbench_type <string>
Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``.
.. option:: --time_unit <string>
Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``).
.. option:: --verbose
Show verbose log

28
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@ -1,13 +1,13 @@
Why OpenFPGA?
-------------
.. note:: If this is the first time you learn OpenFPGA, we strongly recommend you to watch the `introduction video <https://youtu.be/ocODUGcYGqo>`_
.. note:: If this is your first time learning OpenFPGA, we strongly recommend you to watch the `introduction video <https://youtu.be/ocODUGcYGqo>`_
.. only:: html
.. youtube:: ocODUGcYGqo
OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and assoicated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support.
OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and associated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support.
.. _fig_openfpga_motivation:
@ -15,15 +15,15 @@ OpenFPGA aims to be an open-source framework that enables rapid prototyping of c
:scale: 50%
:alt: OpenFPGA: a fast prototyping framework for customizable FPGAs
Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are permitted to publish under proper licenses]
Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are publishable under the proper licenses]
Using OpenFPGA, the development cycle in both hardware and software can be significantly accelerated. OpenFPGA can automatically generate Verilog netlists describing a full FPGA fabric based on an XML-based description file. Thanks to modern semi-custom design tools, production-ready layout generation can be achieved within 24 hours. To help sign-off, OpenFPGA can auto-generate Verilog testbenches to validate the correctness of FPGA fabric using modern verification tools.
OpenFPGA also provides native bitstream generation support based the same XML-based description file used in Verilog generation. This avoid the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use.
OpenFPGA also provides native bitstream generation support based on the same XML-based description file used in Verilog generation, avoiding the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use.
OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customized primitive circuit designed downto transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers.
OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customize primitive circuits designed down to transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers.
In terms of tool functionality, OpenFPGA consists of the following parts: FPGA-Verilog, FPGA-SDC, FPGA-Bitstream and FPGA-SPICE.
The rest of this section will focus on detailed motivation on each of them, as depicted in :numref:`fig_openfpga_framework`.
The rest of this section will focus on detailed motivation for each of them, as depicted in :numref:`fig_openfpga_framework`.
.. _fig_openfpga_framework:
@ -39,7 +39,7 @@ Fully Customizable Architecture
OpenFPGA supports VPR's architecture description language, which allows
users to define versatile programmable fabrics down to point-to-point
interconnection.
OpenFPGA leverage VPR's architecture description by introducing an XML-based
OpenFPGA leverages VPR's architecture description by introducing an XML-based
architecture annotation, enabling fully customizable FPGA fabric down to
circuit elements.
As illustrated in :ref:`fig_openfpga_arch_lang_coverage`, OpenFPGA's
@ -60,7 +60,9 @@ FPGA-Verilog
~~~~~~~~~~~~
Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern
computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts.
computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors.
OpenFPGA, an opensource framework, aims to rapidly prototype customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts.
FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabling various backend choices, as illustrated in :ref:`fig_fpga_verilog_motivation`.
.. _fig_fpga_verilog_motivation:
@ -98,20 +100,18 @@ The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`.
FPGA-Bitstream
~~~~~~~~~~~~~~
EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs.
Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generators for customized FPGAs. Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow, the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics.
The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`.
FPGA-SPICE
~~~~~~~~~~
The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages of generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model requires updates to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages of generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
It motivates us to develop FPGA-SPICE, an add-on for the current State-of-Art FPGA architecture exploration tools, VPR :cite:`JRose_FPGA_2012`.
FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA architectures supported by VPR. The SPICE netlists and testbenches are generated according to the placement and routing results of VPR. As a result, SPICE simulator can be used to perform precise delay and power analysis. The SPICE simulation results are useful in three aspects: (1) it can provide accurate power analysis; (2) it helps to improve the accuracy of built-in analytical models; and moreover (3) it creates opportunities in developing novel analytical models.
FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA architectures supported by VPR. The SPICE netlists and testbenches are generated according to the placement and routing results of VPR. As a result, SPICE simulator can be used to perform precise delay and power analysis. The SPICE simulation results are useful in three aspects: (1) they provide accurate power analysis; (2) they help to improve the accuracy of built-in analytical models; and moreover (3) they create opportunities in developing novel analytical models.
SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we develop an extension on the VPR architectural description language to model the transistor-level circuit designs.
SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we are developing an extension on the VPR architectural description language to model the transistor-level circuit designs.
The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.

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Technical Highlights
--------------------
The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of February 2021**)
The following lists of technical features were created to help users find their needs for customizing FPGA fabrics.(**as of February 2021**)
Supported Circuit Designs
~~~~~~~~~~~~~~~~~~~~~~~~~
@ -42,19 +42,21 @@ Supported Circuit Designs
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` |
| | Memory | | | - :ref:`circuit_model_sram_blwl_example` |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_ccff_example` |
| | | | - :ref:`circuit_model_ccff_enable_example` |
| | | | - :ref:`circuit_model_ccff_scanable_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| Block RAM | No | Yes | - **Any size** |
| | | | - Single-port |
| | | | - Dual-port |
| | | | - Fracturable |
| Data Memory | No | Yes | - **Any size** |
| | | | - :ref:`circuit_model_dff_example` |
| | | | - :ref:`circuit_model_multi_mode_ff_example` |
| | | | - Single-port Block RAM |
| | | | - :ref:`circuit_model_single_mode_dpram_example` |
| | | | - :ref:`circuit_model_multi_mode_dpram_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| | Arithmetic | No | Yes | - **Any size** |
| | Units | | | - Multiplier |
| | | | - :ref:`circuit_model_full_adder_example` |
| | Units | | | - :ref:`circuit_model_full_adder_example` |
| | | | - :ref:`circuit_model_single_mode_mult8x8_example` |
| | | | - :ref:`circuit_model_multi_mode_mult8x8_example` |
+-----------------+--------------+-----------+-----------------------------------------------------+
| I/O | No | Yes | - :ref:`circuit_model_gpio_example` |
| | | | - Bi-directional buffer |
@ -62,13 +64,13 @@ Supported Circuit Designs
+-----------------+--------------+-----------+-----------------------------------------------------+
* The user defined netlist could come from a standard cell
* The user defined netlist could come from a standard cell. See :ref:`tutorial_standard_cell` for details.
Supported FPGA Architectures
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
We support most FPGA architectures that VPR can support!
The following are most commonly seen architectural features:
The following are the most commonly seen architectural features:
+------------------------+----------------------------------------------+
| Block Type | Architecture features |

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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 3623.61 L 795.082 3623.61 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 3747.54 L 795.082 3747.54 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 1287.27 3871.48 L 720 3871.48 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4110.49 L 795.082 4110.49 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4225.57 L 795.082 4225.57 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4349.51 L 795.082 4349.51 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4473.44 L 795.082 4473.44 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4588.52 L 795.082 4588.52 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4712.46 L 795.082 4712.46 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4827.54 L 795.082 4827.54 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4951.48 L 795.082 4951.48 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 1287.27 5075.41 L 720 5075.41 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5190.49 L 795.082 5190.49 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5314.43 L 795.082 5314.43 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5429.51 L 795.082 5429.51 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5792.46 L 795.082 5792.46 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5916.39 L 795.082 5916.39 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6031.48 L 795.082 6031.48 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6155.41 L 795.082 6155.41 Z "/>
<text xml:space="preserve" transform="matrix(.56422337 0 0 1.7723478 0 0)" font-size="6.024833" font-family="Courier"><tspan y="44.389596" x="890.1263 893.74118 897.3561 900.97097 904.5859">30 ns</tspan></text>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 1287.27 6279.34 L 720 6279.34 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6394.43 L 795.082 6394.43 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6757.38 L 795.082 6757.38 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6881.31 L 795.082 6881.31 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6996.39 L 795.082 6996.39 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 7120.33 L 795.082 7120.33 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 986.953 7191.15 L 986.953 1463.61 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 3747.54 L 795.082 3747.54 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 1287.27 3871.48 L 720 3871.48 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4712.46 L 795.082 4712.46 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4827.54 L 795.082 4827.54 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 4951.48 L 795.082 4951.48 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 1287.27 5075.41 L 720 5075.41 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 5916.39 L 795.082 5916.39 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6031.48 L 795.082 6031.48 Z "/>
<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 6155.41 L 795.082 6155.41 Z "/>
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<path transform="matrix(0,.1,.1,0,0,0)" stroke-width="5" stroke-linecap="square" stroke-miterlimit="10" stroke-linejoin="miter" fill="none" stroke="#cbcbcb" d="M 845.133 7120.33 L 795.082 7120.33 Z "/>
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:maxdepth: 2
quick_start
user_defined_temp_tutorial
open_cell_libraries_tutorial
spypads_tutorial

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.. _tutorial_standard_cell:
Build an FPGA fabric using Standard Cell Libraries
==================================================
Introduction
~~~~~~~~~~~~
**In this tutorial, we will**
- Showcase how to create an architecture description based on standard cells, using OpenFPGA's circuit modeling language
- Use Skywater's Process Design Kit (`PDK`_) cell library to create an OR Gate circuit model for OpenFPGA
- Verify that the standard cell library file was correctly bound into the selected architecture file by looking at auto-generated OpenFPGA files and checking simulation waveforms in GTKWave
Through this example, we will show how to bind standard cell library files with OpenFPGA Architectures.
.. note:: We showcase the methodology by considering the open-source Skywater 130nm PDK so that users can easily reproduce the results.
Create and Verify the OpenFPGA Circuit Model
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. note:: In this tutorial, we focus on binding a 2-input **OR** gate from a standard cell library to a circuit model in OpenFPGA's architecture description file. Note that the approach can be generalized to any circuit model.
For this tutorial, we start with an example where the HDL netlist of an 2-input **OR** gate that is auto-generated by OpenFPGA. After updating the architecture file, the auto-generated HDL netlist created by OpenFPGA will directly instantiate a standard cell from the open-source Skywater 130nm PDK library.
To follow along, go to the root directory of OpenFPGA and enter:
.. code-block:: bash
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
This will run a prebuilt task with OpenFPGA cell libraries. When the task is finished, there will be many auto-generated files to look through. For this tutorial, we are interested in the ``luts.v`` and ``and2_formal.vcd`` files. The **OR2** gate is used as a control circuit in the **lut6** circuit model, and the ``and2_formal.vcd`` file will have the resulting waveforms from the simulation run by the task. To open the ``luts.v`` file, run the following command:
.. code-block:: bash
vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v
.. note:: Users can find full details about netlist organization in our documentation: :ref:`fabric_netlists`
The ``luts.v`` file represents a Look Up Table within the OpenFPGA architecture. The important lines of this file for the tutorial are highlighted below.
These lines show the instantiation of OpenFPGA's **OR2** cell library.
.. code-block:: verilog
:emphasize-lines: 58,59,72,73,74,75,76,77,78,79,80
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Look-Up Tables
// Author: Xifan TANG
// Organization: University of Utah
// Date: Tue Mar 30 15:25:03 2021
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for frac_lut6 -----
module frac_lut6(in,
sram,
sram_inv,
mode,
mode_inv,
lut4_out,
lut5_out,
lut6_out);
//----- INPUT PORTS -----
input [0:5] in;
//----- INPUT PORTS -----
input [0:63] sram;
//----- INPUT PORTS -----
input [0:63] sram_inv;
//----- INPUT PORTS -----
input [0:1] mode;
//----- INPUT PORTS -----
input [0:1] mode_inv;
//----- OUTPUT PORTS -----
output [0:3] lut4_out;
//----- OUTPUT PORTS -----
output [0:1] lut5_out;
//----- OUTPUT PORTS -----
output [0:0] lut6_out;
//----- BEGIN wire-connection ports -----
wire [0:5] in;
wire [0:3] lut4_out;
wire [0:1] lut5_out;
wire [0:0] lut6_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] OR2_0_out;
wire [0:0] OR2_1_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;
wire [0:0] buf4_4_out;
wire [0:0] buf4_5_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
OR2 OR2_0_ (
.a(mode[0:0]),
.b(in[4]),
.out(OR2_0_out));
OR2 OR2_1_ (
.a(mode[1]),
.b(in[5]),
.out(OR2_1_out));
INVTX1 INVTX1_0_ (
.in(in[0:0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
INVTX1 INVTX1_4_ (
.in(OR2_0_out),
.out(INVTX1_4_out));
INVTX1 INVTX1_5_ (
.in(OR2_1_out),
.out(INVTX1_5_out));
buf4 buf4_0_ (
.in(in[0:0]),
.out(buf4_0_out));
buf4 buf4_1_ (
.in(in[1]),
.out(buf4_1_out));
buf4 buf4_2_ (
.in(in[2]),
.out(buf4_2_out));
buf4 buf4_3_ (
.in(in[3]),
.out(buf4_3_out));
buf4 buf4_4_ (
.in(OR2_0_out),
.out(buf4_4_out));
buf4 buf4_5_ (
.in(OR2_1_out),
.out(buf4_5_out));
frac_lut6_mux frac_lut6_mux_0_ (
.in(sram[0:63]),
.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out, buf4_4_out, buf4_5_out}),
.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}),
.lut4_out(lut4_out[0:3]),
.lut5_out(lut5_out[0:1]),
.lut6_out(lut6_out));
endmodule
// ----- END Verilog module for frac_lut6 -----
//----- Default net type -----
`default_nettype none
We will also need to look at the control's simulation waveforms. Viewing the waveforms is done through `GTKWave`_ with the following command:
.. code-block:: bash
gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
The simulation waveforms should look similar to the following :numref:`fig_control_output`:
.. _fig_control_output:
.. figure:: ./figures/Control_Waves2.png
:scale: 75%
Simulation Waveforms with OpenFPGA Circuit Model
.. note:: The waveform inputs do not need to exactly match because the testbench provides input in random intervals.
We have now finished creating the control and viewing the important sections for this tutorial. We can now incorporate Skywater's cell library to create a new circuit model.
Clone Skywater PDK into OpenFPGA
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
We will be using the open-source Skywater PDK to create our circuit model. We start by cloning the Skywater PDK github repository into the OpenFPGA root directory.
Run the following command in the root directory of OpenFPGA:
.. code-block:: bash
git clone https://github.com/google/skywater-pdk.git
Once the repository has been cloned, we need to build the cell libraries by running the following command in the Skywater PDK root directory:
.. code-block:: bash
SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1
This will take some time to complete due to the size of the libraries. Once the libraries are made, creating the circuit model can begin.
Create and Verify the Standard Cell Library Circuit Model
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To create the circuit model, we will modify the ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` OpenFPGA architecture file by removing the circuit model
for OpenFPGA's **OR2** gate, replacing the circuit model with one referencing the Skywater cell library, and modifying the LUT that references the old **OR2**
circuit model to reference our new circuit model. We begin by running the following command in the root directory:
.. code-block:: bash
vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
We continue the circuit model creation process by replacing **LINE67** to **LINE81** with the following:
.. code-block:: xml
<circuit_model type="gate" name="sky130_fd_sc_ls__or2_1" prefix="sky130_fd_sc_ls__or2_1" verilog_netlist="${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2/sky130_fd_sc_ls__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="A" size="1"/>
<port type="input" prefix="B" size="1"/>
<port type="output" prefix="X" size="1"/>
</circuit_model>
.. note:: The name of the circuit model must be consistent with the standard cell!
The most significant differences from the OpenFPGA Circuit Model in this section are:
- Change the ``name`` and ``prefix`` to match the module name from Skywater's cell library
- Include a path to the verilog file using ``verilog_netlist``.
The second change to ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` is at **LINE160**, where we will be replacing the line with the following:
.. code-block:: xml
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="sky130_fd_sc_ls__or2_1"/>
This change replaces the input of the LUT with our new circuit model. Everything is in place to begin verification.
Verification begins by running the following command:
.. code-block:: bash
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
The task may output this error:
.. code-block:: bash
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - iverilog_verification run failed with returncode 1
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>error: Unable to find the root module "and2_top_formal_verification_random_tb" in the Verilog source.
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>1 error(s) during elaboration.
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Current working directory : OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run057/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to run iverilog_verification task
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Exiting . . . . . .
ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH
This error has occurred because IVerilog could not find the path to the Skywater PDK Cell Library we have selected. To fix this, we need to go to the
``iverilog_output.txt`` file found here:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/iverilog_output.txt
Replace all the text within ``iverilog_output.txt`` with the following:
.. code-block:: bash
iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb -I ${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2
We can now manually rerun IVerilog, a tutorial on manually running IVerilog can be found at our :ref:`from_verilog_to_verification` tutorial. From the root
directory, run the following commands:
.. code-block:: bash
cd openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/
source iverilog_output.txt
vvp compiled_and2
With IVerilog complete, we can verify that the cell library has been bound correctly by viewing the ``luts.v`` file and the waveforms with GTKWave.
From the root directory, view the ``luts.v`` file with this command:
.. code-block:: bash
vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v
Scrolling through ``luts.v``, this should be present in the file:
.. code-block:: verilog
:emphasize-lines: 64,65,72,73,74,75,76,77,78,79,80
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Look-Up Tables
// Author: Xifan TANG
// Organization: University of Utah
// Date: Tue Mar 30 20:25:06 2021
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for frac_lut6 -----
module frac_lut6(in,
sram,
sram_inv,
mode,
mode_inv,
lut4_out,
lut5_out,
lut6_out);
//----- INPUT PORTS -----
input [0:5] in;
//----- INPUT PORTS -----
input [0:63] sram;
//----- INPUT PORTS -----
input [0:63] sram_inv;
//----- INPUT PORTS -----
input [0:1] mode;
//----- INPUT PORTS -----
input [0:1] mode_inv;
//----- OUTPUT PORTS -----
output [0:3] lut4_out;
//----- OUTPUT PORTS -----
output [0:1] lut5_out;
//----- OUTPUT PORTS -----
output [0:0] lut6_out;
//----- BEGIN wire-connection ports -----
wire [0:5] in;
wire [0:3] lut4_out;
wire [0:1] lut5_out;
wire [0:0] lut6_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;
wire [0:0] buf4_4_out;
wire [0:0] buf4_5_out;
wire [0:0] sky130_fd_sc_ls__or2_1_0_X;
wire [0:0] sky130_fd_sc_ls__or2_1_1_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_0_ (
.A(mode[0:0]),
.B(in[4]),
.X(sky130_fd_sc_ls__or2_1_0_X));
sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_1_ (
.A(mode[1]),
.B(in[5]),
.X(sky130_fd_sc_ls__or2_1_1_X));
INVTX1 INVTX1_0_ (
.in(in[0:0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
INVTX1 INVTX1_4_ (
.in(sky130_fd_sc_ls__or2_1_0_X),
.out(INVTX1_4_out));
INVTX1 INVTX1_5_ (
.in(sky130_fd_sc_ls__or2_1_1_X),
.out(INVTX1_5_out));
buf4 buf4_0_ (
.in(in[0:0]),
.out(buf4_0_out));
buf4 buf4_1_ (
.in(in[1]),
.out(buf4_1_out));
buf4 buf4_2_ (
.in(in[2]),
.out(buf4_2_out));
buf4 buf4_3_ (
.in(in[3]),
.out(buf4_3_out));
buf4 buf4_4_ (
.in(sky130_fd_sc_ls__or2_1_0_X),
.out(buf4_4_out));
buf4 buf4_5_ (
.in(sky130_fd_sc_ls__or2_1_1_X),
.out(buf4_5_out));
frac_lut6_mux frac_lut6_mux_0_ (
.in(sram[0:63]),
.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out, buf4_4_out, buf4_5_out}),
.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}),
.lut4_out(lut4_out[0:3]),
.lut5_out(lut5_out[0:1]),
.lut6_out(lut6_out));
endmodule
// ----- END Verilog module for frac_lut6 -----
//----- Default net type -----
`default_nettype none
We can check the waveforms as well to see if they are similar with the command:
.. code-block:: bash
gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
The simulation waveforms should look similar to the following :numref:`fig_custom_output`:
.. _fig_custom_output:
.. figure:: ./figures/Custom_Waves2.png
:scale: 75%
Simulation Waveforms with Skywater PDK Circuit Model
We have now verified that the Skywater PDK Cell Library has been instantiated and bound to the OpenFPGA architecture file. If you have any problems, please :ref:`contact` us.
.. _PDK: https://github.com/google/skywater-pdk
.. _GTKWave: https://github.com/gtkwave/gtkwave

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Creating Spypads Using XML Syntax
=================================
Introduction
~~~~~~~~~~~~
**In this tutorial, we will**
- Show the XML syntax for global outputs
- Showcase an example with spypads
- Modify an existing architecture to incorporate spypads
- Verify correctness through GTKWave
Through this tutorial, we will show how to create spypads in OpenFPGA.
Spypads are physical output pins on a FPGA chip through which you can read out internal signals when doing silicon-level debugging. The XML syntax for spypads and other
global signals can be found on our :ref:`circuit_library` documentation page.
To create a spypad, the ``port type`` needs to be set to **output** and ``is_global`` and ``is_io`` need to be set to **true**:
.. code-block:: xml
<port type="output" is_global="true" is_io="true"/>
When the port is syntactically correct, the outputs are independently wired from different instances to separated FPGA outputs and would physically look like :ref:`fig_gpout_ports`
Pre-Built Spypads
~~~~~~~~~~~~~~~~~
An OpenFPGA architecture file that contains spypads and has a task that references it is the `k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml <https://github.com/lnis-uofu/OpenFPGA/blob/tutorials/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml>`_
file. We can view ``k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml`` by entering the following command at the root directory of OpenFPGA:
.. code-block:: bash
emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
In this architecture file, the output ports of a 6-input Look-Up Table (LUT) are defined as spypads using the XML syntax ``is_global`` and ``is_io``. As a result, all of the outputs from the 6-input LUT will be visible in the top-level module. The output ports to the 6-input LUT are declared from **LINE181** to **LINE183** and belong to the ``frac_lut6_spypad`` ``circuit_model`` that begins at **LINE172**.
.. code-block:: xml
<circuit_model type="lut" name="frac_lut6_spypad" prefix="frac_lut6_spypad" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
LINE181 <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3" is_global="true" is_io="true"/>
LINE182 <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1" is_global="true" is_io="true"/>
LINE183 <port type="output" prefix="lut6_out" size="1" lut_output_mask="0" is_global="true" is_io="true"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
</circuit_model>
The spypads are instantiated in the top-level verilog module ``fpga_top.v``. ``fpga_top.v`` is automatically generated when we run our task from the OpenFPGA root
directory. However, we need to modify the task configuration file to run the **full testbench** instead of the **formal testbench** to view the spypads' waveforms in
GTKWave.
.. note:: To read about the differences between the **formal testbench** and the **full testbench**, please visit our page on testbenches: :ref:`testbench`.
To open the task configuration file, run this command from the root directory of OpenFPGA:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
The last line of the task configuration file (**LINE44**) sets the **formal testbench** to be the desired testbench. To use the **full testbench**, comment out **LINE44**.
The file will look like this when finished:
.. code-block:: python
:linenos:
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
# Cannot pass automatically. Need change in .v file to match ports
# When passed, we can replace the and2 benchmark
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif
[SYNTHESIS_PARAM]
bench0_top = and2
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
#bench0_top = test_mode_low
#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act
#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=
Our OpenFPGA task will now run the full testbench. We run the task with the following command from the root directory of OpenFPGA:
.. code-block:: bash
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
.. note:: Python 3.8 or later is required to run this task
We can now see the instantiation of these spypads in ``fpga_top.v`` and ``luts.v``. We will start by viewing ``luts.v`` with the following command:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.verilog
The spypads are coming from the ``frac_lut6_spypad`` circuit model. In ``luts.v``, the ``frac_lut6_spypad`` module is defined around **LINE150** and looks as follows:
.. code-block:: verilog
module frac_lut6_spypad(in,
sram,
sram_inv,
mode,
mode_inv,
lut4_out,
lut5_out,
lut6_out);
//----- INPUT PORTS -----
input [0:5] in;
//----- INPUT PORTS -----
input [0:63] sram;
//----- INPUT PORTS -----
input [0:63] sram_inv;
//----- INPUT PORTS -----
input [0:1] mode;
//----- INPUT PORTS -----
input [0:1] mode_inv;
//----- OUTPUT PORTS -----
output [0:3] lut4_out;
//----- OUTPUT PORTS -----
output [0:1] lut5_out;
//----- OUTPUT PORTS -----
output [0:0] lut6_out;
The ``fpga_top.v`` file has some similarities. We can view the ``fpga_top.v`` file by running the following command:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
If we look at the module definition and ports of ``fpga_top.v`` we should see the following:
.. code-block:: verilog
module fpga_top(pReset,
prog_clk,
TESTEN,
set,
reset,
clk,
gfpga_pad_frac_lut6_spypad_lut4_out,
gfpga_pad_frac_lut6_spypad_lut5_out,
gfpga_pad_frac_lut6_spypad_lut6_out,
gfpga_pad_GPIO_PAD,
ccff_head,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] TESTEN;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- GPOUT PORTS -----
output [0:3] gfpga_pad_frac_lut6_spypad_lut4_out;
//----- GPOUT PORTS -----
output [0:1] gfpga_pad_frac_lut6_spypad_lut5_out;
//----- GPOUT PORTS -----
output [0:0] gfpga_pad_frac_lut6_spypad_lut6_out;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
Using :ref:`fig_gpout_ports` as a guide, we can relate our task like :numref:`fig_gpout_example`
.. _fig_gpout_example:
.. figure:: ./figures/lut6_Example_Spypad.svg
:scale: 100%
An illustrative example of the ``lut6`` spypad sourced from inside a logic element.
We can view testbench waveforms with GTKWave by running the following command from the root directory:
.. code-block:: bash
gtkwave openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
.. note:: Information on GTKWave can be found on our documentation page located here: :ref:`from_verilog_to_verification`
The waveforms will appear similar to :numref:`fig_spypad_waves`
.. _fig_spypad_waves:
.. figure:: ./figures/spypad_waveforms.png
:width: 100%
Waveforms of ``frac_lut6`` spypads
Building Spypads
~~~~~~~~~~~~~~~~
We will modify the `k6_frac_N10_adder_chain_40nm_openfpga.xml <https://github.com/lnis-uofu/OpenFPGA/blob/tutorials/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml>`_ file found in OpenFPGA to expose the **sumout** output from the **ADDF** module. We can start modifying
the file by running the following command:
.. code-block:: bash
emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
Replace **LINE214** with the following:
.. code-block:: xml
<port type="output" prefix="sumout" lib_name="SUM" size="1" is_global=”true” is_io=”true”/>
**sumout** is now a global output. **sumout** will show up in the ``fpga_top.v`` file and will have waveforms in GTKWave if we run the **full testbench**. To run the
**full testbench**, we have to modify the ``hard_adder`` configuration file:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf
Comment out the last line of the file to run the **full testbench**:
.. code-block:: python
#vpr_fpga_verilog_formal_verification_top_netlist=
We now run the task to see our changes:
.. code-block:: bash
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
We can view the global ports in ``fpga_top.v`` by running the following command:
.. code-block:: bash
emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run064/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v
The ``fpga_top.v`` should have the following in its module definition:
.. code-block:: verilog
module fpga_top(pReset,
prog_clk,
set,
reset,
clk,
gfpga_pad_ADDF_sumout,
gfpga_pad_GPIO_PAD,
ccff_head,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- GPOUT PORTS -----
output [0:19] gfpga_pad_ADDF_sumout;
The architecture will now look like :numref:`fig_addf_example`
.. _fig_addf_example:
.. figure:: ./figures/ADDF_Example_Spypad.svg
:scale: 100%
An illustrative example of the sumout spypad sourced from an adder inside a logic element. There are 10 logic elements in a CLB, and we are looking at the 1st logic element.
We can view the waveform by running GTKWave:
.. code-block:: bash
gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd &
The waveform should have some changes to its value. An example of what it may look like is displayed in :numref:`fig_spy_adder`
.. _fig_spy_adder:
.. figure:: ./figures/spyadder_waveform.png
:width: 100%
Waveforms of ``sumout`` spypad
Conclusion
~~~~~~~~~~
In this tutorial, we have shown how to build spypads into OpenFPGA Architectures using XML Syntax. If you have any issues, feel free to :ref:`contact` us.

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.. _tutorial_user_def_temp:
Integrating Custom Verilog Modules with user_defined_template.v
================================================================
.. only:: html
.. youtube:: YTggSZHsTjg
Introduction and Setup
~~~~~~~~~~~~~~~~~~~~~~
**In this tutorial, we will**
- Provide the motivation for generating the user_defined_template.v verilog file
- Go through a generated user_defined_template.v file to demonstrate how to use it
Through this tutorial, we will show how and when to use the :ref:`user_defined_template.v <fabric_netlists>` file.
To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA.
To follow along, go to the root directory of OpenFPGA and enter:
.. code-block:: bash
vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
Go to **LINE187** and replace **LINE187** with:
.. code-block:: XML
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="">
Motivation
~~~~~~~~~~
From the OpenFPGA root directory, run the command:
.. code-block:: bash
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
Running this command should fail and produce the following errors:
.. code-block:: bash
ERROR - iverilog_verification run failed with returncode 21
ERROR - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF
ERROR - -->>21 error(s) during elaboration.
ERROR - Current working directory : /research/ece/lnis/USERS/leaptrot/OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run019/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH
ERROR - Failed to run iverilog_verification task
ERROR - Exiting . . . . . .
This error log can also be found by running the following command from the root directory:
.. code-block:: bash
cat openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/00_and2_MIN_ROUTE_CHAN_WIDTH_out.log
This command failed during the verification step because the path to the module definition for **ADDF** is missing. In our architecture file, user-defined verilog modules are those ``<circuit_model>`` with the key term `verilog_netlist`. The ``user_defined_template.v`` file provides a module template for incorporating Hard IPs without external library into the architecture.
Fixing the Error
~~~~~~~~~~~~~~~~
This error can be resolved by replacing the **LINE187** of ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` with the following:
.. code-block:: XML
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
The above line provides a path to generate the :ref:`user_defined_template.v <fabric_netlists>` file.
Now we can return to the root directory and run this command again:
.. code-block:: bash
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
The task should now complete without any errors.
Fixing the Error with user_defined_template.v
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The :ref:`user_defined_template.v <fabric_netlists>` file can be found starting from the root directory and entering:
.. code-block:: bash
vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v
.. note:: The ``user_defined_template.v`` file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. ``user_defined_template.v`` is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. ``user_defined_template.v`` can be included in simulation only if there are modifications to the ``user_defined_template.v``.
To implement our own **ADDF** module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_template.v`` file with the following:
.. code-block:: Verilog
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Template for user-defined Verilog modules
// Author: Xifan TANG
// Organization: University of Utah
// Date: Fri Mar 19 10:05:32 2021
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- Template Verilog module for ADDF -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for ADDF -----
module ADDF(A,
B,
CI,
SUM,
CO);
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] B;
//----- INPUT PORTS -----
input [0:0] CI;
//----- OUTPUT PORTS -----
output [0:0] SUM;
//----- OUTPUT PORTS -----
output [0:0] CO;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
assign SUM = A ^ B ^ CI;
assign CO = (A & B) | (A & CI) | (B & CI);
// ----- Internal logic should end here -----
endmodule
// ----- END Verilog module for ADDF -----
We can now link this ``user_defined_template.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``.
.. note:: Be sure to select the run where you modified the ``user_defined_template.v``!
From the OpenFPGA root directory, run:
.. code-block:: bash
vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
At **LINE187** in verilog_netlist, put in:
.. code-block:: XML
${OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/**YOUR_RUN_NUMBER**/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v
Finally, rerun this command from the OpenFPGA root directory to ensure it is working:
.. code-block:: bash
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs

17
docs/source/tutorials/getting_started/compile.rst
View File

@ -11,7 +11,7 @@ How to Compile
General Guidelines
~~~~~~~~~~~~~~~~~~
OpenFPGA uses CMake to generate the Makefile scripts
OpenFPGA uses CMake to generate the Makefile scripts.
In general, please follow the steps to compile
.. code-block:: shell
@ -24,13 +24,13 @@ In general, please follow the steps to compile
.. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI
.. note:: recommand to use ``make -j`` to accelerate the compilation
.. note:: Recommend using ``make -j<int>`` to accelerate the compilation, where ``<int>`` denotes the number of cores to be used in compilation.
.. note:: VPR's GUI requires gtk-3, and can be enabled with ``cmake .. -DVPR_USE_EZGL=on``
**Quick Compilation Verification**
To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
To quickly verify the tool is well compiled, users can run the following command from OpenFPGA root repository
.. code-block:: shell
@ -38,7 +38,7 @@ To quickly verify the tool is well compiled, user can run the following command
Dependencies
~~~~~~~~~~~~
Full list of dependencies can be found at install_dependencies_build_
Full list of dependencies can be found at install_dependencies_build_.
In particular, OpenFPGA requires specific versions for the following dependencies:
:cmake:
@ -47,14 +47,19 @@ In particular, OpenFPGA requires specific versions for the following dependencie
:iverilog:
version 10.1+ is required to run Verilog-to-Verification flow
:python dependencies:
python packages are also required:
python3 -m pip install -r requirements.txt
.. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh
Running with the docker image
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Users can skip the traditional installation process by using Dockerized version
of the OpenFPGA tool. OpenFPGA project maintains the docker image/Github package of
Users can skip the traditional installation process by using the Dockerized version
of the OpenFPGA tool. The OpenFPGA project maintains the docker image/Github package of
the latest stable version of OpenFPGA in the following repository
`openfpga-master <https://github.com/orgs/lnis-uofu/packages/container/package/openfpga-master>`_.
This image contains precompiled OpenFPGA binaries with all prerequisites installed.

4
docs/source/tutorials/getting_started/shell_shortcuts.rst
View File

@ -22,13 +22,13 @@ Once the ``openfpga.sh`` script is sourced, you can run any of the following com
.. option:: run-task <task_name> **kwarags
This command runs the specified task listed from the ``list-task`` command or from the existing directory. The command name is relative to the ``TASK_DIRECTORY``. User can provide any additional arguments which are listed `here <_openfpga_task_args>`_ to this command.
This command runs the specified task listed from the ``list-task`` command or from the existing directory. The command name is relative to the ``TASK_DIRECTORY``. Users can provide any additional arguments which are listed `here <_openfpga_task_args>`_ to this command.
.. option:: run-modelsim
This command runs the verification using ModelSim.
The test benches are generated during the OpenFPGA run.
**Note**: user need to have ``VSIM`` install and configured
**Note**: users need to have ``VSIM`` installed and configured
.. option:: run-regression-local

66
libopenfpga/libarchopenfpga/src/bitstream_setting.cpp
View File

@ -16,6 +16,10 @@ BitstreamSetting::bitstream_pb_type_setting_range BitstreamSetting::pb_type_sett
return vtr::make_range(pb_type_setting_ids_.begin(), pb_type_setting_ids_.end());
}
BitstreamSetting::bitstream_interconnect_setting_range BitstreamSetting::interconnect_settings() const {
return vtr::make_range(interconnect_setting_ids_.begin(), interconnect_setting_ids_.end());
}
/************************************************************************
* Constructors
***********************************************************************/
@ -51,6 +55,36 @@ std::string BitstreamSetting::pb_type_bitstream_content(const BitstreamPbTypeSet
return pb_type_bitstream_contents_[pb_type_setting_id];
}
bool BitstreamSetting::is_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id) const {
VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id));
return is_mode_select_bitstreams_[pb_type_setting_id];
}
size_t BitstreamSetting::bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id) const {
VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id));
return bitstream_offsets_[pb_type_setting_id];
}
std::string BitstreamSetting::interconnect_name(const BitstreamInterconnectSettingId& interconnect_setting_id) const {
VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id));
return interconnect_names_[interconnect_setting_id];
}
std::vector<std::string> BitstreamSetting::parent_pb_type_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const {
VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id));
return interconnect_parent_pb_type_names_[interconnect_setting_id];
}
std::vector<std::string> BitstreamSetting::parent_mode_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const {
VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id));
return interconnect_parent_mode_names_[interconnect_setting_id];
}
std::string BitstreamSetting::default_path(const BitstreamInterconnectSettingId& interconnect_setting_id) const {
VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id));
return interconnect_default_paths_[interconnect_setting_id];
}
/************************************************************************
* Public Mutators
***********************************************************************/
@ -66,10 +100,38 @@ BitstreamPbTypeSettingId BitstreamSetting::add_bitstream_pb_type_setting(const s
parent_mode_names_.push_back(parent_mode_names);
pb_type_bitstream_sources_.push_back(bitstream_source);
pb_type_bitstream_contents_.push_back(bitstream_content);
is_mode_select_bitstreams_.push_back(false);
bitstream_offsets_.push_back(0);
return pb_type_setting_id;
}
void BitstreamSetting::set_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id,
const bool& is_mode_select_bitstream) {
VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id));
is_mode_select_bitstreams_[pb_type_setting_id] = is_mode_select_bitstream;
}
void BitstreamSetting::set_bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id,
const size_t& offset) {
VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id));
bitstream_offsets_[pb_type_setting_id] = offset;
}
BitstreamInterconnectSettingId BitstreamSetting::add_bitstream_interconnect_setting(const std::string& interconnect_name,
const std::vector<std::string>& parent_pb_type_names,
const std::vector<std::string>& parent_mode_names,
const std::string& default_path) {
BitstreamInterconnectSettingId interc_setting_id = BitstreamInterconnectSettingId(interconnect_setting_ids_.size());
interconnect_setting_ids_.push_back(interc_setting_id);
interconnect_names_.push_back(interconnect_name);
interconnect_parent_pb_type_names_.push_back(parent_pb_type_names);
interconnect_parent_mode_names_.push_back(parent_mode_names);
interconnect_default_paths_.push_back(default_path);
return interc_setting_id;
}
/************************************************************************
* Public Validators
***********************************************************************/
@ -77,4 +139,8 @@ bool BitstreamSetting::valid_bitstream_pb_type_setting_id(const BitstreamPbTypeS
return ( size_t(pb_type_setting_id) < pb_type_setting_ids_.size() ) && ( pb_type_setting_id == pb_type_setting_ids_[pb_type_setting_id] );
}
bool BitstreamSetting::valid_bitstream_interconnect_setting_id(const BitstreamInterconnectSettingId& interconnect_setting_id) const {
return ( size_t(interconnect_setting_id) < interconnect_setting_ids_.size() ) && ( interconnect_setting_id == interconnect_setting_ids_[interconnect_setting_id] );
}
} /* namespace openfpga ends */

41
libopenfpga/libarchopenfpga/src/bitstream_setting.h
View File

@ -17,6 +17,10 @@ namespace openfpga {
/********************************************************************
* A data structure to describe bitstream settings
*
* This data structure includes following types of settings:
* - Pb type: include definiting hard coded bitstream for pb_types (LUT or configurable pb_type for mode selection)
* - Interconnect: include defining default paths for routing multiplexers in pb_types
*
* Typical usage:
* --------------
* // Create an empty bitstream setting
@ -27,33 +31,70 @@ namespace openfpga {
class BitstreamSetting {
public: /* Types */
typedef vtr::vector<BitstreamPbTypeSettingId, BitstreamPbTypeSettingId>::const_iterator bitstream_pb_type_setting_iterator;
typedef vtr::vector<BitstreamInterconnectSettingId, BitstreamInterconnectSettingId>::const_iterator bitstream_interconnect_setting_iterator;
/* Create range */
typedef vtr::Range<bitstream_pb_type_setting_iterator> bitstream_pb_type_setting_range;
typedef vtr::Range<bitstream_interconnect_setting_iterator> bitstream_interconnect_setting_range;
public: /* Constructors */
BitstreamSetting();
public: /* Accessors: aggregates */
bitstream_pb_type_setting_range pb_type_settings() const;
bitstream_interconnect_setting_range interconnect_settings() const;
public: /* Public Accessors */
std::string pb_type_name(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
std::vector<std::string> parent_pb_type_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
std::vector<std::string> parent_mode_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
std::string pb_type_bitstream_source(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
std::string pb_type_bitstream_content(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
bool is_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
size_t bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
std::string interconnect_name(const BitstreamInterconnectSettingId& interconnect_setting_id) const;
std::vector<std::string> parent_pb_type_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const;
std::vector<std::string> parent_mode_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const;
std::string default_path(const BitstreamInterconnectSettingId& interconnect_setting_id) const;
public: /* Public Mutators */
BitstreamPbTypeSettingId add_bitstream_pb_type_setting(const std::string& pb_type_name,
const std::vector<std::string>& parent_pb_type_names,
const std::vector<std::string>& parent_mode_names,
const std::string& bitstream_source,
const std::string& bitstream_content);
void set_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id,
const bool& is_mode_select_bitstream);
void set_bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id,
const size_t& offset);
BitstreamInterconnectSettingId add_bitstream_interconnect_setting(const std::string& interconnect_name,
const std::vector<std::string>& parent_pb_type_names,
const std::vector<std::string>& parent_mode_names,
const std::string& default_path);
public: /* Public Validators */
bool valid_bitstream_pb_type_setting_id(const BitstreamPbTypeSettingId& pb_type_setting_id) const;
bool valid_bitstream_interconnect_setting_id(const BitstreamInterconnectSettingId& interconnect_setting_id) const;
private: /* Internal data */
/* Pb type -related settings
* - Paths to a pb_type in the pb_graph
* - Bitstream source, data_type, offsets etc.
*/
vtr::vector<BitstreamPbTypeSettingId, BitstreamPbTypeSettingId> pb_type_setting_ids_;
vtr::vector<BitstreamPbTypeSettingId, std::string> pb_type_names_;
vtr::vector<BitstreamPbTypeSettingId, std::vector<std::string>> parent_pb_type_names_;
vtr::vector<BitstreamPbTypeSettingId, std::vector<std::string>> parent_mode_names_;
vtr::vector<BitstreamPbTypeSettingId, std::string> pb_type_bitstream_sources_;
vtr::vector<BitstreamPbTypeSettingId, std::string> pb_type_bitstream_contents_;
/* Indicate if the bitstream is applied to mode selection bits of a pb_type */
vtr::vector<BitstreamPbTypeSettingId, bool> is_mode_select_bitstreams_;
/* The offset that the bitstream is applied to the original bitstream of a pb_type */
vtr::vector<BitstreamPbTypeSettingId, size_t> bitstream_offsets_;
/* Interconnect-related settings:
* - Name of interconnect under a given pb_type
* - The default path to be considered for a given interconnect during bitstream generation
*/
vtr::vector<BitstreamInterconnectSettingId, BitstreamInterconnectSettingId> interconnect_setting_ids_;
vtr::vector<BitstreamInterconnectSettingId, std::string> interconnect_names_;
vtr::vector<BitstreamInterconnectSettingId, std::vector<std::string>> interconnect_parent_pb_type_names_;
vtr::vector<BitstreamInterconnectSettingId, std::vector<std::string>> interconnect_parent_mode_names_;
vtr::vector<BitstreamInterconnectSettingId, std::string> interconnect_default_paths_;
};
} /* namespace openfpga ends */

2
libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h
View File

@ -13,8 +13,10 @@
#include "vtr_strong_id.h"
struct bitstream_pb_type_setting_id_tag;
struct bitstream_interconnect_setting_id_tag;
typedef vtr::StrongId<bitstream_pb_type_setting_id_tag> BitstreamPbTypeSettingId;
typedef vtr::StrongId<bitstream_interconnect_setting_id_tag> BitstreamInterconnectSettingId;
/* Short declaration of class */
class BitstreamSetting;

40
libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
View File

@ -86,11 +86,11 @@ std::vector<std::string> PbTypeAnnotation::port_names() const {
return keys;
}
std::map<BasicPort, std::array<int, 2>> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(port_name);
std::map<BasicPort, std::array<int, 3>> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
std::map<std::string, std::map<BasicPort, std::array<int, 3>>>::const_iterator it = operating_pb_type_ports_.find(port_name);
if (it == operating_pb_type_ports_.end()) {
/* Return an empty port */
return std::map<BasicPort, std::array<int, 2>>();
return std::map<BasicPort, std::array<int, 3>>();
}
return operating_pb_type_ports_.at(port_name);
}
@ -169,25 +169,25 @@ void PbTypeAnnotation::set_physical_pb_type_index_offset(const int& value) {
void PbTypeAnnotation::add_pb_type_port_pair(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port) {
/* Give a warning if the operating_pb_port_name already exist */
std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
std::map<std::string, std::map<BasicPort, std::array<int, 3>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
/* If not exist, initialize and set a default value */
if (it == operating_pb_type_ports_.end()) {
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0};
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0, 0};
/* We can return early */
return;
}
/* If the physical port is not in the list, we create one and set a default value */
if (0 == operating_pb_type_ports_[operating_pb_port_name].count(physical_pb_port)) {
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0};
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0, 0};
}
}
void PbTypeAnnotation::set_physical_pin_initial_offset(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port,
const int& physical_pin_initial_offset) {
std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
std::map<std::string, std::map<BasicPort, std::array<int, 3>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
if (it == operating_pb_type_ports_.end()) {
VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
@ -210,7 +210,7 @@ void PbTypeAnnotation::set_physical_pin_initial_offset(const std::string& operat
void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port,
const int& physical_pin_rotate_offset) {
std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
std::map<std::string, std::map<BasicPort, std::array<int, 3>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
if (it == operating_pb_type_ports_.end()) {
VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
@ -230,6 +230,30 @@ void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operati
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][1] = physical_pin_rotate_offset;
}
void PbTypeAnnotation::set_physical_port_rotate_offset(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port,
const int& physical_port_rotate_offset) {
std::map<std::string, std::map<BasicPort, std::array<int, 3>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
if (it == operating_pb_type_ports_.end()) {
VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
operating_pb_port_name.c_str());
exit(1);
}
if (operating_pb_type_ports_[operating_pb_port_name].end() == operating_pb_type_ports_[operating_pb_port_name].find(physical_pb_port)) {
VTR_LOG_ERROR("The physical pb_type port '%s[%lu:%lu]' definition for operating pb_type port '%s' is not valid!\n",
physical_pb_port.get_name().c_str(),
physical_pb_port.get_lsb(),
physical_pb_port.get_msb(),
operating_pb_port_name.c_str());
exit(1);
}
operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][2] = physical_port_rotate_offset;
}
void PbTypeAnnotation::add_interconnect_circuit_model_pair(const std::string& interc_name,
const std::string& circuit_model_name) {
std::map<std::string, std::string>::const_iterator it = interconnect_circuit_model_names_.find(interc_name);

24
libopenfpga/libarchopenfpga/src/pb_type_annotation.h
View File

@ -49,7 +49,7 @@ class PbTypeAnnotation {
float physical_pb_type_index_factor() const;
int physical_pb_type_index_offset() const;
std::vector<std::string> port_names() const;
std::map<BasicPort, std::array<int, 2>> physical_pb_type_port(const std::string& port_name) const;
std::map<BasicPort, std::array<int, 3>> physical_pb_type_port(const std::string& port_name) const;
std::vector<std::string> interconnect_names() const;
std::string interconnect_circuit_model_name(const std::string& interc_name) const;
public: /* Public mutators */
@ -73,6 +73,9 @@ class PbTypeAnnotation {
void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port,
const int& physical_pin_rotate_offset);
void set_physical_port_rotate_offset(const std::string& operating_pb_port_name,
const BasicPort& physical_pb_port,
const int& physical_port_rotate_offset);
void add_interconnect_circuit_model_pair(const std::string& interc_name,
const std::string& circuit_model_name);
private: /* Internal data */
@ -138,10 +141,10 @@ class PbTypeAnnotation {
int physical_pb_type_index_offset_;
/* Link from the pins under an operating pb_type to pairs of
* its physical pb_type and its pin initial & rotating offset
*
* Note that initial offset is the first element of the std::array
* Note that rotating offset is the second element of the std::array
* its physical pb_type and
* - its pin initial offset: the first element of the std::array
* - pin-level rotating offset: the second element of the std::array
* - port-level rotating offset: the third element of the std::array
*
* The offsets aim to align the pin indices for port of pb_type
* between operating and physical modes, especially when an operating
@ -158,14 +161,21 @@ class PbTypeAnnotation {
* physical pb_type bram[0].dout_a[0] with a full path memory[physical].bram[0]
* physical pb_type bram[0].dout_a[1] with a full path memory[physical].bram[0]
*
* For example, a rotating offset of 9 is used to map
* For example, a pin-level rotating offset of 9 is used to map
* operating pb_type mult_9x9[0].a[0] with a full path mult[frac].mult_9x9[0]
* operating pb_type mult_9x9[0].a[1] with a full path mult[frac].mult_9x9[1]
* to
* physical pb_type mult_36x36.a[0] with a full path mult[physical].mult_36x36[0]
* physical pb_type mult_36x36.a[9] with a full path mult[physical].mult_36x36[0]
*
* For example, a port-level rotating offset of 9 is used to map
* operating pb_type mult_9x9[0].a[0:8] with a full path mult[frac].mult_9x9[0]
* operating pb_type mult_9x9[1].a[0:8] with a full path mult[frac].mult_9x9[1]
* to
* physical pb_type mult_36x36.a[0:8] with a full path mult[physical].mult_36x36[0]
* physical pb_type mult_36x36.a[9:17] with a full path mult[physical].mult_36x36[0]
*/
std::map<std::string, std::map<BasicPort, std::array<int, 2>>> operating_pb_type_ports_;
std::map<std::string, std::map<BasicPort, std::array<int, 3>>> operating_pb_type_ports_;
/* Link between the interconnects under this pb_type and circuit model names */
std::map<std::string, std::string> interconnect_circuit_model_names_;

44
libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp
View File

@ -36,11 +36,38 @@ void read_xml_bitstream_pb_type_setting(pugi::xml_node& xml_pb_type,
openfpga::PbParser operating_pb_parser(name_attr);
/* Add to bitstream setting */
bitstream_setting.add_bitstream_pb_type_setting(operating_pb_parser.leaf(),
BitstreamPbTypeSettingId bitstream_pb_type_id = bitstream_setting.add_bitstream_pb_type_setting(operating_pb_parser.leaf(),
operating_pb_parser.parents(),
operating_pb_parser.modes(),
source_attr,
content_attr);
/* Parse if the bitstream overwritting is applied to mode bits of a pb_type */
const bool& is_mode_select_bitstream = get_attribute(xml_pb_type, "is_mode_select_bitstream", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false);
bitstream_setting.set_mode_select_bitstream(bitstream_pb_type_id, is_mode_select_bitstream);
const int& offset = get_attribute(xml_pb_type, "bitstream_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0);
bitstream_setting.set_bitstream_offset(bitstream_pb_type_id, offset);
}
/********************************************************************
* Parse XML description for a pb_type annotation under a <interconect> XML node
*******************************************************************/
static
void read_xml_bitstream_interconnect_setting(pugi::xml_node& xml_pb_type,
const pugiutil::loc_data& loc_data,
openfpga::BitstreamSetting& bitstream_setting) {
const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string();
const std::string& default_path_attr = get_attribute(xml_pb_type, "default_path", loc_data).as_string();
/* Parse the attributes for operating pb_type */
openfpga::PbParser operating_pb_parser(name_attr);
/* Add to bitstream setting */
bitstream_setting.add_bitstream_interconnect_setting(operating_pb_parser.leaf(),
operating_pb_parser.parents(),
operating_pb_parser.modes(),
default_path_attr);
}
/********************************************************************
@ -53,12 +80,19 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(pugi::xml_node& Node,
/* Iterate over the children under this node,
* each child should be named after <pb_type>
*/
for (pugi::xml_node xml_pb_type : Node.children()) {
for (pugi::xml_node xml_child : Node.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_pb_type.name() != std::string("pb_type")) {
bad_tag(xml_pb_type, loc_data, Node, {"pb_type"});
if ( (xml_child.name() != std::string("pb_type"))
&& (xml_child.name() != std::string("interconnect")) ) {
bad_tag(xml_child, loc_data, Node, {"pb_type | interconnect"});
}
if (xml_child.name() == std::string("pb_type")) {
read_xml_bitstream_pb_type_setting(xml_child, loc_data, bitstream_setting);
} else {
VTR_ASSERT_SAFE(xml_child.name() == std::string("interconnect"));
read_xml_bitstream_interconnect_setting(xml_child, loc_data, bitstream_setting);
}
read_xml_bitstream_pb_type_setting(xml_pb_type, loc_data, bitstream_setting);
}
return bitstream_setting;

25
libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
View File

@ -114,6 +114,31 @@ void read_xml_pb_port_annotation(pugi::xml_node& xml_port,
std::stoi(rotate_offsets[iport]));
}
}
/* We have an optional attribute: physical_mode_port_rotate_offset
* Split based on the number of physical pb_type ports that have been defined
*/
const std::string& physical_port_rotate_offset_attr = get_attribute(xml_port, "physical_mode_port_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
if (false == physical_port_rotate_offset_attr.empty()) {
/* Split the physical mode port attributes with space */
openfpga::StringToken offset_tokenizer(physical_port_rotate_offset_attr);
const std::vector<std::string> rotate_offsets = offset_tokenizer.split();
/* Error out if the offset does not match the port definition */
if (physical_mode_ports.size() != rotate_offsets.size()) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
"Defined %lu physical mode ports but only %lu physical port rotate offset are defined! Expect size matching.\n",
physical_mode_ports.size(), rotate_offsets.size());
}
for (size_t iport = 0; iport < physical_mode_ports.size(); ++iport) {
openfpga::PortParser port_parser(physical_mode_ports[iport]);
pb_type_annotation.set_physical_port_rotate_offset(name_attr,
port_parser.port(),
std::stoi(rotate_offsets[iport]));
}
}
}
/********************************************************************

55
libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp
View File

@ -39,6 +39,31 @@ std::string generate_bitstream_setting_pb_type_hierarchy_name(const openfpga::Bi
return hie_name;
}
/********************************************************************
* Generate the full hierarchy name for an interconnect in bitstream setting
*******************************************************************/
static
std::string generate_bitstream_setting_interconnect_hierarchy_name(const openfpga::BitstreamSetting& bitstream_setting,
const BitstreamInterconnectSettingId& bitstream_interc_setting_id) {
/* Iterate over the parent_pb_type and modes names, they should well match */
VTR_ASSERT_SAFE(bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id).size() == bitstream_setting.parent_mode_names(bitstream_interc_setting_id).size());
std::string hie_name;
for (size_t i = 0 ; i < bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id).size(); ++i) {
hie_name += bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id)[i];
hie_name += std::string("[");
hie_name += bitstream_setting.parent_mode_names(bitstream_interc_setting_id)[i];
hie_name += std::string("]");
hie_name += std::string(".");
}
/* Add the leaf pb_type */
hie_name += bitstream_setting.interconnect_name(bitstream_interc_setting_id);
return hie_name;
}
/********************************************************************
* A writer to output a bitstream pb_type setting to XML format
*******************************************************************/
@ -57,6 +82,29 @@ void write_xml_bitstream_pb_type_setting(std::fstream& fp,
write_xml_attribute(fp, "source", bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str());
write_xml_attribute(fp, "content", bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id).c_str());
write_xml_attribute(fp, "is_mode_select_bitstream", bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id));
write_xml_attribute(fp, "bitstream_offset", bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id));
fp << "/>" << "\n";
}
/********************************************************************
* A writer to output a bitstream interconnect setting to XML format
*******************************************************************/
static
void write_xml_bitstream_interconnect_setting(std::fstream& fp,
const char* fname,
const openfpga::BitstreamSetting& bitstream_setting,
const BitstreamInterconnectSettingId& bitstream_interc_setting_id) {
/* Validate the file stream */
openfpga::check_file_stream(fname, fp);
fp << "\t" << "<pb_type";
/* Generate the full hierarchy name of the pb_type */
write_xml_attribute(fp, "name", generate_bitstream_setting_interconnect_hierarchy_name(bitstream_setting, bitstream_interc_setting_id).c_str());
write_xml_attribute(fp, "default_path", bitstream_setting.default_path(bitstream_interc_setting_id).c_str());
fp << "/>" << "\n";
}
@ -74,11 +122,16 @@ void write_xml_bitstream_setting(std::fstream& fp,
*/
fp << "<openfpga_bitstream_setting>" << "\n";
/* Write clock settings */
/* Write pb_type -related settings */
for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) {
write_xml_bitstream_pb_type_setting(fp, fname, bitstream_setting, bitstream_pb_type_setting_id);
}
/* Write interconnect -related settings */
for (const auto& bitstream_interc_setting_id : bitstream_setting.interconnect_settings()) {
write_xml_bitstream_interconnect_setting(fp, fname, bitstream_setting, bitstream_interc_setting_id);
}
/* Write the root node <openfpga_bitstream_setting> */
fp << "</openfpga_bitstream_setting>" << "\n";
}

9
libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
View File

@ -144,7 +144,14 @@ void write_xml_pb_port_annotation(std::fstream& fp,
physical_mode_pin_rotate_offset_attr += std::to_string(physical_pb_port_pair.second[1]);
}
write_xml_attribute(fp, "physical_mode_pin_rotate_offset", physical_mode_pin_rotate_offset_attr.c_str());
std::string physical_mode_port_rotate_offset_attr;
for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) {
if (false == physical_mode_port_rotate_offset_attr.empty()) {
physical_mode_port_rotate_offset_attr += " ";
}
physical_mode_port_rotate_offset_attr += std::to_string(physical_pb_port_pair.second[2]);
}
write_xml_attribute(fp, "physical_mode_port_rotate_offset", physical_mode_port_rotate_offset_attr.c_str());
fp << "/>" << "\n";
}

22
libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp
View File

@ -71,5 +71,27 @@ size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamMa
return curr_index;
}
/********************************************************************
* Find the total number of configuration bits under a block
* As configuration bits are stored only under the leaf blocks,
* this function will recursively visit all the child blocks
* until reaching a leaf block, where we collect the number of bits
*******************************************************************/
size_t rec_find_bitstream_manager_block_sum_of_bits(const BitstreamManager& bitstream_manager,
const ConfigBlockId& block) {
/* For leaf block, return directly with the number of bits, because it has not child block */
if (0 < bitstream_manager.block_bits(block).size()) {
VTR_ASSERT_SAFE(bitstream_manager.block_children(block).empty());
return bitstream_manager.block_bits(block).size();
}
size_t sum_of_bits = 0;
/* Dive to child blocks if this block has any */
for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) {
sum_of_bits += rec_find_bitstream_manager_block_sum_of_bits(bitstream_manager, child_block);
}
return sum_of_bits;
}
} /* end namespace openfpga */

3
libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h
View File

@ -22,6 +22,9 @@ std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(const BitstreamMana
size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamManager& bitstream_manager,
const ConfigBitId& bit_id);
size_t rec_find_bitstream_manager_block_sum_of_bits(const BitstreamManager& bitstream_manager,
const ConfigBlockId& block);
} /* end namespace openfpga */
#endif

124
libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.cpp Normal file
View File

@ -0,0 +1,124 @@
/********************************************************************
* This file includes functions that report distribution of bitstream by blocks
*******************************************************************/
#include <chrono>
#include <ctime>
#include <fstream>
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_tokenizer.h"
#include "openfpga_version.h"
#include "openfpga_reserved_words.h"
#include "bitstream_manager_utils.h"
#include "report_arch_bitstream_distribution.h"
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* This function write header information for an XML file of bitstream distribution
*******************************************************************/
static
void report_architecture_bitstream_distribution_xml_file_head(std::fstream& fp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!-- " << std::endl;
fp << "\t- Report Architecture Bitstream Distribution" << std::endl;
fp << "\t- Version: " << openfpga::VERSION << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
fp << "--> " << std::endl;
fp << std::endl;
}
/********************************************************************
* Recursively report the bitstream distribution of a block to a file
* This function will use a Depth-First Search in outputting bitstream
* for each block
* For block with child blocks, we visit each child recursively
* The reporting can be stopped at a given maximum hierarchy level
* which is used to limit the length of the report
*******************************************************************/
static
void rec_report_block_bitstream_distribution_to_xml_file(std::fstream& fp,
const BitstreamManager& bitstream_manager,
const ConfigBlockId& block,
const size_t& max_hierarchy_level,
const size_t& hierarchy_level) {
valid_file_stream(fp);
if (hierarchy_level > max_hierarchy_level) {
return;
}
/* Write the bitstream distribution of this block */
write_tab_to_file(fp, hierarchy_level);
fp << "<block";
fp << " name=\"" << bitstream_manager.block_name(block)<< "\"";
fp << " number_of_bits=\"" << rec_find_bitstream_manager_block_sum_of_bits(bitstream_manager, block) << "\"";
fp << ">" << std::endl;
/* Dive to child blocks if this block has any */
for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) {
rec_report_block_bitstream_distribution_to_xml_file(fp, bitstream_manager, child_block,
max_hierarchy_level, hierarchy_level + 1);
}
write_tab_to_file(fp, hierarchy_level);
fp << "</block>" <<std::endl;
}
/********************************************************************
* Report the distribution of bitstream by blocks, e.g., the number of
* configuration bits per SB/CB/CLB
* This function can generate a report to a file
*
* Notes:
* - The output format is a table whose format is compatible with RST files
*******************************************************************/
int report_architecture_bitstream_distribution(const BitstreamManager& bitstream_manager,
const std::string& fname,
const size_t& max_hierarchy_level) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR("Received empty file name to report bitstream!\n\tPlease specify a valid file name.\n");
return 1;
}
std::string timer_message = std::string("Report architecture bitstream distribution into XML file '") + fname + std::string("'");
vtr::ScopedStartFinishTimer timer(timer_message);
/* Create the file stream */
std::fstream fp;
fp.open(fname, std::fstream::out | std::fstream::trunc);
check_file_stream(fname.c_str(), fp);
/* Put down a brief introduction */
report_architecture_bitstream_distribution_xml_file_head(fp);
/* Find the top block, which has not parents */
std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
/* Make sure we have only 1 top block */
VTR_ASSERT(1 == top_block.size());
/* Write bitstream, block by block, in a recursive way */
rec_report_block_bitstream_distribution_to_xml_file(fp, bitstream_manager, top_block[0], max_hierarchy_level, 0);
/* Close file handler */
fp.close();
return 0;
}
} /* end namespace openfpga */

23
libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef REPORT_ARCH_BITSTREAM_DISTRIBUTION_H
#define REPORT_ARCH_BITSTREAM_DISTRIBUTION_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <string>
#include "bitstream_manager.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
int report_architecture_bitstream_distribution(const BitstreamManager& bitstream_manager,
const std::string& fname,
const size_t& max_hierarchy_level = 1);
} /* end namespace openfpga */
#endif

16
libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp
View File

@ -10,17 +10,18 @@
/* Headers from fabric key */
#include "read_xml_arch_bitstream.h"
#include "write_xml_arch_bitstream.h"
#include "report_arch_bitstream_distribution.h"
int main(int argc, const char** argv) {
/* Ensure we have only one or two argument */
VTR_ASSERT((2 == argc) || (3 == argc));
/* Ensure we have only one or two or 3 argument */
VTR_ASSERT((2 == argc) || (3 == argc) || (4 == argc));
/* Parse the bitstream from an XML file */
openfpga::BitstreamManager test_bitstream = openfpga::read_xml_architecture_bitstream(argv[1]);
VTR_LOG("Read the bitstream from an XML file: %s.\n",
argv[1]);
/* Output the circuit library to an XML file
/* Output the bitstream database to an XML file
* This is optional only used when there is a second argument
*/
if (3 <= argc) {
@ -28,6 +29,15 @@ int main(int argc, const char** argv) {
VTR_LOG("Echo the bitstream to an XML file: %s.\n",
argv[2]);
}
/* Output the bitstream distribution to an XML file
* This is optional only used when there is a third argument
*/
if (4 <= argc) {
openfpga::report_architecture_bitstream_distribution(test_bitstream, argv[3]);
VTR_LOG("Echo the bitstream distribution to an XML file: %s.\n",
argv[3]);
}
}

3
libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
View File

@ -59,6 +59,9 @@ constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
} /* end namespace openfpga */
#endif

81
libopenfpga/libpcf/src/pin_constraints.cpp
View File

@ -38,6 +38,58 @@ std::string PinConstraints::net(const PinConstraintId& pin_constraint_id) const
return pin_constraint_nets_[pin_constraint_id];
}
std::string PinConstraints::pin_net(const openfpga::BasicPort& pin) const {
std::string constrained_net_name;
for (const PinConstraintId& pin_constraint : pin_constraints()) {
if (pin == pin_constraint_pins_[pin_constraint]) {
constrained_net_name = net(pin_constraint);
break;
}
}
return constrained_net_name;
}
openfpga::BasicPort PinConstraints::net_pin(const std::string& net) const {
openfpga::BasicPort constrained_pin;
for (const PinConstraintId& pin_constraint : pin_constraints()) {
if (net == pin_constraint_nets_[pin_constraint]) {
constrained_pin = pin(pin_constraint);
break;
}
}
return constrained_pin;
}
PinConstraints::e_logic_level PinConstraints::net_default_value(const std::string& net) const {
PinConstraints::e_logic_level logic_level = PinConstraints::NUM_LOGIC_LEVELS;
for (const PinConstraintId& pin_constraint : pin_constraints()) {
if (net == pin_constraint_nets_[pin_constraint]) {
logic_level = pin_constraint_net_default_values_[pin_constraint];
break;
}
}
return logic_level;
}
std::string PinConstraints::net_default_value_to_string(const PinConstraintId& pin_constraint) const {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
if (PinConstraints::LOGIC_HIGH == pin_constraint_net_default_values_[pin_constraint]) {
return std::string("1");
} else if (PinConstraints::LOGIC_LOW == pin_constraint_net_default_values_[pin_constraint]) {
return std::string("0");
}
return std::string();
}
size_t PinConstraints::net_default_value_to_int(const std::string& net) const {
if (PinConstraints::LOGIC_HIGH == net_default_value(net)) {
return 1;
} else if (PinConstraints::LOGIC_LOW == net_default_value(net)) {
return 0;
}
return -1;
}
bool PinConstraints::empty() const {
return 0 == pin_constraint_ids_.size();
}
@ -49,6 +101,7 @@ void PinConstraints::reserve_pin_constraints(const size_t& num_pin_constraints)
pin_constraint_ids_.reserve(num_pin_constraints);
pin_constraint_pins_.reserve(num_pin_constraints);
pin_constraint_nets_.reserve(num_pin_constraints);
pin_constraint_net_default_values_.reserve(num_pin_constraints);
}
PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin,
@ -59,10 +112,21 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort&
pin_constraint_ids_.push_back(pin_constraint_id);
pin_constraint_pins_.push_back(pin);
pin_constraint_nets_.push_back(net);
pin_constraint_net_default_values_.push_back(PinConstraints::NUM_LOGIC_LEVELS);
return pin_constraint_id;
}
void PinConstraints::set_net_default_value(const PinConstraintId& pin_constraint,
const std::string& default_value) {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
if (default_value == std::string("1")) {
pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_HIGH;
} else if (default_value == std::string("0")) {
pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_LOW;
}
}
/************************************************************************
* Internal invalidators/validators
***********************************************************************/
@ -70,3 +134,20 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort&
bool PinConstraints::valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const {
return ( size_t(pin_constraint_id) < pin_constraint_ids_.size() ) && ( pin_constraint_id == pin_constraint_ids_[pin_constraint_id] );
}
bool PinConstraints::unconstrained_net(const std::string& net) const {
return net.empty();
}
bool PinConstraints::unmapped_net(const std::string& net) const {
return std::string(PIN_CONSTRAINT_OPEN_NET) == net;
}
bool PinConstraints::valid_net_default_value(const PinConstraintId& pin_constraint) const {
VTR_ASSERT(valid_pin_constraint_id(pin_constraint));
return PinConstraints::NUM_LOGIC_LEVELS != pin_constraint_net_default_values_[pin_constraint];
}
bool PinConstraints::valid_net_default_value(const std::string& net) const {
return PinConstraints::NUM_LOGIC_LEVELS != net_default_value(net);
}

65
libopenfpga/libpcf/src/pin_constraints.h
View File

@ -41,6 +41,12 @@ class PinConstraints {
typedef vtr::vector<PinConstraintId, PinConstraintId>::const_iterator pin_constraint_iterator;
/* Create range */
typedef vtr::Range<pin_constraint_iterator> pin_constraint_range;
/* Logic value */
enum e_logic_level {
LOGIC_HIGH,
LOGIC_LOW,
NUM_LOGIC_LEVELS
};
public: /* Constructors */
PinConstraints();
public: /* Accessors: aggregates */
@ -52,11 +58,36 @@ class PinConstraints {
/* Get the net to be constrained */
std::string net(const PinConstraintId& pin_constraint_id) const;
/* Find the net that is constrained on a pin
* TODO: this function will only return the first net found in the constraint list
*/
std::string pin_net(const openfpga::BasicPort& pin) const;
/* Find the pin that a net is constrained to
* If not found, the return port will be an invalid BasicPort
* TODO: this function will only return the first pin found in the constraint list
*/
openfpga::BasicPort net_pin(const std::string& net) const;
/* Find the default value that a net is constrained to
* If not found, return an invalid value
*/
e_logic_level net_default_value(const std::string& net) const;
/* Generate the string of the default value
* If not found, return an empty string
*/
std::string net_default_value_to_string(const PinConstraintId& pin_constraint) const;
/* Generate the integer representation of the default value
* If not found, return -1
*/
size_t net_default_value_to_int(const std::string& net) const;
/* Check if there are any pin constraints */
bool empty() const;
public: /* Public Mutators */
/* Reserve a number of design constraints to be memory efficent */
void reserve_pin_constraints(const size_t& num_pin_constraints);
@ -64,8 +95,37 @@ class PinConstraints {
PinConstraintId create_pin_constraint(const openfpga::BasicPort& pin,
const std::string& net);
/* Set the default value for the net under a given pin constraint */
void set_net_default_value(const PinConstraintId& pin_constraint,
const std::string& default_value);
public: /* Public invalidators/validators */
/* Show if the pin constraint id is a valid for data queries */
bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const;
/* Show if the net has no constraints (free to map to any pin)
* This function is used to identify the net name returned by APIs:
* - pin_net()
* - net()
*/
bool unconstrained_net(const std::string& net) const;
/* Show if the net is defined specifically not to map to any pin
* This function is used to identify the net name returned by APIs:
* - pin_net()
* - net()
*/
bool unmapped_net(const std::string& net) const;
/* Check if default value is a valid one or not
* This is to check if the default value is constrained or not
*/
bool valid_net_default_value(const PinConstraintId& pin_constraint) const;
/* Check if default value is a valid one or not
* This is to check if the default value is constrained or not
*/
bool valid_net_default_value(const std::string& net) const;
private: /* Internal data */
/* Unique ids for each design constraint */
vtr::vector<PinConstraintId, PinConstraintId> pin_constraint_ids_;
@ -75,6 +135,9 @@ class PinConstraints {
/* Nets to constraint */
vtr::vector<PinConstraintId, std::string> pin_constraint_nets_;
/* Default value of the nets to constraint */
vtr::vector<PinConstraintId, e_logic_level> pin_constraint_net_default_values_;
};
#endif

8
libopenfpga/libpcf/src/read_xml_pin_constraints.cpp
View File

@ -41,6 +41,14 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint,
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
"Fail to create pin constraint!\n");
}
/* Set default value if defined */
std::string default_value = get_attribute(xml_pin_constraint, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
pin_constraints.set_net_default_value(pin_constraint_id, default_value);
if (!default_value.empty() && !pin_constraints.valid_net_default_value(pin_constraint_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint),
"Invalid default value for pin constraints. Expect [0|1]!\n");
}
}
/********************************************************************

1
libopenfpga/libpcf/src/write_xml_pin_constraints.cpp
View File

@ -44,6 +44,7 @@ int write_xml_pin_constraint(std::fstream& fp,
write_xml_attribute(fp, "pin", generate_xml_port_name(pin_constraints.pin(pin_constraint)).c_str());
write_xml_attribute(fp, "net", pin_constraints.net(pin_constraint).c_str());
write_xml_attribute(fp, "default_value", pin_constraints.net_default_value_to_string(pin_constraint).c_str());
fp << "/>" << "\n";

22
libopenfpga/librepackdc/src/repack_design_constraints.cpp
View File

@ -50,6 +50,20 @@ std::string RepackDesignConstraints::net(const RepackDesignConstraintId& repack_
return repack_design_constraint_nets_[repack_design_constraint_id];
}
std::string RepackDesignConstraints::find_constrained_pin_net(const std::string& pb_type,
const openfpga::BasicPort& pin) const {
std::string constrained_net_name;
for (const RepackDesignConstraintId& design_constraint : design_constraints()) {
/* If found a constraint, record the net name */
if ( (pb_type == repack_design_constraint_pb_types_[design_constraint])
&& (pin == repack_design_constraint_pins_[design_constraint])) {
constrained_net_name = repack_design_constraint_nets_[design_constraint];
break;
}
}
return constrained_net_name;
}
bool RepackDesignConstraints::empty() const {
return 0 == repack_design_constraint_ids_.size();
}
@ -106,3 +120,11 @@ void RepackDesignConstraints::set_net(const RepackDesignConstraintId& repack_des
bool RepackDesignConstraints::valid_design_constraint_id(const RepackDesignConstraintId& design_constraint_id) const {
return ( size_t(design_constraint_id) < repack_design_constraint_ids_.size() ) && ( design_constraint_id == repack_design_constraint_ids_[design_constraint_id] );
}
bool RepackDesignConstraints::unconstrained_net(const std::string& net) const {
return net.empty();
}
bool RepackDesignConstraints::unmapped_net(const std::string& net) const {
return std::string(REPACK_DESIGN_CONSTRAINT_OPEN_NET) == net;
}

18
libopenfpga/librepackdc/src/repack_design_constraints.h
View File

@ -61,6 +61,10 @@ class RepackDesignConstraints {
/* Get the net to be constrained */
std::string net(const RepackDesignConstraintId& repack_design_constraint_id) const;
/* Find a constrained net */
std::string find_constrained_pin_net(const std::string& pb_type,
const openfpga::BasicPort& pin) const;
/* Check if there are any design constraints */
bool empty() const;
@ -86,6 +90,20 @@ class RepackDesignConstraints {
public: /* Public invalidators/validators */
bool valid_design_constraint_id(const RepackDesignConstraintId& repack_design_constraint_id) const;
/* Show if the net has no constraints (free to map to any pin)
* This function is used to identify the net name returned by APIs:
* - find_constrained_pin_net()
* - net()
*/
bool unconstrained_net(const std::string& net) const;
/* Show if the net is defined specifically not to map to any pin
* This function is used to identify the net name returned by APIs:
* - find_constrained_pin_net()
* - net()
*/
bool unmapped_net(const std::string& net) const;
private: /* Internal data */
/* Unique ids for each design constraint */
vtr::vector<RepackDesignConstraintId, RepackDesignConstraintId> repack_design_constraint_ids_;

2
openfpga.sh
View File

@ -21,7 +21,7 @@ if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi
# inside current OpendFPGA folder
check_execution_path (){
if [[ $1 != *"${OPENFPGA_PATH}"* ]]; then
echo -e "\e[33mCommand is not executed from configured OPNEFPGA directory\e[0m"
echo -e "\e[33mCommand is not executed from configured OPENFPGA directory\e[0m"
fi
}

156
openfpga/src/annotation/annotate_bitstream_setting.cpp
View File

@ -12,6 +12,9 @@
#include "vtr_assert.h"
#include "vtr_log.h"
/* Headers from openfpgautil library */
#include "openfpga_tokenizer.h"
#include "pb_type_utils.h"
#include "annotate_bitstream_setting.h"
@ -23,7 +26,8 @@ namespace openfpga {
* - Find the pb_type and link to the bitstream source
* - Find the pb_type and link to the bitstream content
*******************************************************************/
int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
static
int annotate_bitstream_pb_type_setting(const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
VprBitstreamAnnotation& vpr_bitstream_annotation) {
@ -56,17 +60,30 @@ int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
if (nullptr == target_pb_type) {
continue;
}
/* Found one, build annotation */
if (std::string("eblif") == bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) {
vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF);
} else {
if (std::string("eblif") != bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) {
/* Invalid source, error out! */
VTR_LOG_ERROR("Invalid bitstream source '%s' for pb_type '%s' which is defined in bitstream setting\n",
bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str(),
target_pb_type_names[0].c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* Depending on the bitstream type, annotate through different entrances
* - For regular bitstream, set bitstream content, flags etc.
* - For mode-select bitstream, set mode-select bitstream content, flags etc.
*/
if (false == bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id)) {
vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF);
vpr_bitstream_annotation.set_pb_type_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id));
vpr_bitstream_annotation.set_pb_type_bitstream_offset(target_pb_type, bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id));
} else {
VTR_ASSERT_SAFE(false == bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id));
vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF);
vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id));
vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_offset(target_pb_type, bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id));
}
link_success = true;
}
@ -82,4 +99,135 @@ int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
return CMD_EXEC_SUCCESS;
}
/********************************************************************
* Annotate bitstream setting based on VPR device information
* - Find the interconnect and link to the default path id
*******************************************************************/
static
int annotate_bitstream_interconnect_setting(const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
const VprDeviceAnnotation& vpr_device_annotation,
VprBitstreamAnnotation& vpr_bitstream_annotation) {
for (const auto& bitstream_interc_setting_id : bitstream_setting.interconnect_settings()) {
/* Get the full name of pb_type */
std::vector<std::string> target_pb_type_names;
std::vector<std::string> target_pb_mode_names;
target_pb_type_names = bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id);
target_pb_mode_names = bitstream_setting.parent_mode_names(bitstream_interc_setting_id);
/* Kick out the last mode so that we can use an existing function search the pb_type in graph */
std::string expected_physical_mode_name = target_pb_mode_names.back();
target_pb_mode_names.pop_back();
std::string interconnect_name = bitstream_setting.interconnect_name(bitstream_interc_setting_id);
std::string expected_input_path = bitstream_setting.default_path(bitstream_interc_setting_id);
/* Pb type information are located at the logic_block_types in the device context of VPR
* We iterate over the vectors and find the pb_type matches the parent_pb_type_name
*/
bool link_success = false;
for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) {
/* By pass nullptr for pb_type head */
if (nullptr == lb_type.pb_type) {
continue;
}
/* Check the name of the top-level pb_type, if it does not match, we can bypass */
if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) {
continue;
}
/* Match the name in the top-level, we go further to search the pb_type in the graph */
t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names,
target_pb_mode_names);
if (nullptr == target_pb_type) {
continue;
}
/* Found one, build annotation */
t_mode* physical_mode = vpr_device_annotation.physical_mode(target_pb_type);
VTR_ASSERT(nullptr != physical_mode);
/* Ensure that the annotation is only applicable to physical mode */
if (std::string(physical_mode->name) != expected_physical_mode_name) {
VTR_LOG_ERROR("The physical mode '%s' under pb_type '%s' does not match in the bitstream setting '%s'!\n",
physical_mode->name,
target_pb_type->name,
expected_physical_mode_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* Find the interconnect name under the physical mode of a physical pb_type */
t_interconnect* pb_interc = find_pb_mode_interconnect(physical_mode, interconnect_name.c_str());
if (nullptr == pb_interc) {
VTR_LOG_ERROR("Unable to find interconnect '%s' under physical mode '%s' of pb_type '%s'!\n",
interconnect_name.c_str(),
physical_mode->name,
target_pb_type->name);
return CMD_EXEC_FATAL_ERROR;
}
/* Find the default path and spot the path id from the input string recorded */
StringToken input_string_tokenizer(std::string(pb_interc->input_string));
std::vector<std::string> input_paths = input_string_tokenizer.split(' ');
size_t input_path_id = input_paths.size();
for (size_t ipath = 0; ipath < input_paths.size(); ++ipath) {
if (expected_input_path == input_paths[ipath]) {
input_path_id = ipath;
break;
}
}
/* If the input_path id is invalid, error out! */
if (input_path_id == input_paths.size()) {
VTR_LOG_ERROR("Invalid default path '%s' for interconnect '%s' which inputs are '%s'\n",
expected_input_path.c_str(),
interconnect_name.c_str(),
pb_interc->input_string);
return CMD_EXEC_FATAL_ERROR;
}
vpr_bitstream_annotation.set_interconnect_default_path_id(pb_interc, input_path_id);
link_success = true;
}
/* If fail to link bitstream setting to architecture, error out immediately */
if (false == link_success) {
VTR_LOG_ERROR("Fail to find an interconnect '%s' with default path '%s', which is defined in bitstream setting from VPR architecture description\n",
interconnect_name.c_str(),
expected_input_path.c_str());
return CMD_EXEC_FATAL_ERROR;
}
}
return CMD_EXEC_SUCCESS;
}
/********************************************************************
* Annotate bitstream setting based on VPR device information
* - Fill pb_type -related mapping
* - Fill interconnect -related mapping
*******************************************************************/
int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
const VprDeviceAnnotation& vpr_device_annotation,
VprBitstreamAnnotation& vpr_bitstream_annotation) {
int status = CMD_EXEC_SUCCESS;
status = annotate_bitstream_pb_type_setting(bitstream_setting,
vpr_device_ctx,
vpr_bitstream_annotation);
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
status = annotate_bitstream_interconnect_setting(bitstream_setting,
vpr_device_ctx, vpr_device_annotation,
vpr_bitstream_annotation);
return status;
}
} /* end namespace openfpga */

1
openfpga/src/annotation/annotate_bitstream_setting.h
View File

@ -16,6 +16,7 @@ namespace openfpga {
int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting,
const DeviceContext& vpr_device_ctx,
const VprDeviceAnnotation& vpr_device_annotation,
VprBitstreamAnnotation& vpr_bitstream_annotation);
} /* end namespace openfpga */

26
openfpga/src/annotation/annotate_pb_graph.cpp
View File

@ -333,7 +333,7 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
* by the pin rotate offset value
* The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
*/
int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port);
int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port) + vpr_device_annotation.physical_pb_port_offset(operating_pb_graph_pin->port, candidate_port);
int init_offset = vpr_device_annotation.physical_pb_pin_initial_offset(operating_pb_graph_pin->port, candidate_port);
const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port, candidate_port);
if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
@ -463,6 +463,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
physical_pb_graph_node, vpr_device_annotation,
verbose_output);
}
/* Finish a port, accumulate the port-level offset affiliated to the port */
if (0 == operating_pb_graph_node->num_input_pins[iport]) {
continue;
}
t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->input_pins[iport][0]);
for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port);
}
}
for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) {
@ -471,6 +479,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
physical_pb_graph_node, vpr_device_annotation,
verbose_output);
}
/* Finish a port, accumulate the port-level offset affiliated to the port */
if (0 == operating_pb_graph_node->num_output_pins[iport]) {
continue;
}
t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->output_pins[iport][0]);
for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port);
}
}
for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) {
@ -479,6 +495,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no
physical_pb_graph_node, vpr_device_annotation,
verbose_output);
}
/* Finish a port, accumulate the port-level offset affiliated to the port */
if (0 == operating_pb_graph_node->num_clock_pins[iport]) {
continue;
}
t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->clock_pins[iport][0]);
for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port);
}
}
}

3
openfpga/src/annotation/annotate_pb_types.cpp
View File

@ -211,7 +211,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
* if not found, we assume that the physical port is the same as the operating pb_port
*/
for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
std::map<BasicPort, std::array<int, 2>> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
std::map<BasicPort, std::array<int, 3>> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
/* If not defined in the annotation, set the default pair:
* rotate_offset is 0 by default!
@ -243,6 +243,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, physical_pb_port, expected_physical_pb_port.first);
vpr_device_annotation.add_physical_pb_pin_initial_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[0]);
vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[1]);
vpr_device_annotation.add_physical_pb_port_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[2]);
}
}

48
openfpga/src/annotation/annotate_physical_tiles.cpp Normal file
View File

@ -0,0 +1,48 @@
/********************************************************************
* This file includes functions to build links between pb_types
* in particular to annotate the physical mode and physical pb_type
*******************************************************************/
/* Headers from vtrutil library */
#include "vtr_time.h"
#include "vtr_assert.h"
#include "vtr_log.h"
#include "annotate_physical_tiles.h"
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Build the fast look-up for each physical tile between
* pin index and the physical port information, i.e., port name and port index
*******************************************************************/
void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx,
VprDeviceAnnotation& vpr_device_annotation) {
vtr::ScopedStartFinishTimer timer("Build fast look-up for physical tile pins");
for (const t_physical_tile_type& physical_tile : vpr_device_ctx.physical_tile_types) {
/* Count the number of pins for each sub tile */
int num_pins_per_subtile = 0;
for (const t_physical_tile_port& tile_port : physical_tile.ports) {
num_pins_per_subtile += tile_port.num_pins;
}
/* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */
for (int subtile_index = 0; subtile_index < physical_tile.capacity; ++subtile_index) {
for (const t_physical_tile_port& tile_port : physical_tile.ports) {
for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) {
int absolute_pin_index = subtile_index * num_pins_per_subtile + tile_port.absolute_first_pin_index + pin_index;
BasicPort tile_port_info(tile_port.name, pin_index, pin_index);
vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile,
absolute_pin_index,
tile_port_info);
vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile,
absolute_pin_index,
subtile_index);
}
}
}
}
}
} /* end namespace openfpga */

23
openfpga/src/annotation/annotate_physical_tiles.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef ANNOTATE_PHYSICAL_TILES_H
#define ANNOTATE_PHYSICAL_TILES_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "vpr_context.h"
#include "openfpga_context.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx,
VprDeviceAnnotation& vpr_device_annotation);
} /* end namespace openfpga */
#endif

76
openfpga/src/annotation/vpr_bitstream_annotation.cpp
View File

@ -4,6 +4,7 @@
#include "vtr_log.h"
#include "vtr_assert.h"
#include "vpr_bitstream_annotation.h"
#include "mux_bitstream_constants.h"
/* namespace openfpga begins */
namespace openfpga {
@ -38,6 +39,56 @@ std::string VprBitstreamAnnotation::pb_type_bitstream_content(t_pb_type* pb_type
return std::string();
}
size_t VprBitstreamAnnotation::pb_type_bitstream_offset(t_pb_type* pb_type) const {
auto result = bitstream_offsets_.find(pb_type);
if (result != bitstream_offsets_.end()) {
return result->second;
}
/* Not found, return an zero offset */
return 0;
}
VprBitstreamAnnotation::e_bitstream_source_type VprBitstreamAnnotation::pb_type_mode_select_bitstream_source(t_pb_type* pb_type) const {
auto result = mode_select_bitstream_sources_.find(pb_type);
if (result != mode_select_bitstream_sources_.end()) {
return result->second;
}
/* Not found, return an invalid type*/
return NUM_BITSTREAM_SOURCE_TYPES;
}
std::string VprBitstreamAnnotation::pb_type_mode_select_bitstream_content(t_pb_type* pb_type) const {
auto result = mode_select_bitstream_contents_.find(pb_type);
if (result != mode_select_bitstream_contents_.end()) {
return result->second;
}
/* Not found, return an invalid type */
return std::string();
}
size_t VprBitstreamAnnotation::pb_type_mode_select_bitstream_offset(t_pb_type* pb_type) const {
auto result = mode_select_bitstream_offsets_.find(pb_type);
if (result != mode_select_bitstream_offsets_.end()) {
return result->second;
}
/* Not found, return an zero offset */
return 0;
}
size_t VprBitstreamAnnotation::interconnect_default_path_id(t_interconnect* interconnect) const {
auto result = interconnect_default_path_ids_.find(interconnect);
if (result != interconnect_default_path_ids_.end()) {
return result->second;
}
/* Not found, return an invalid input id */
return DEFAULT_PATH_ID;
}
/************************************************************************
* Public mutators
***********************************************************************/
@ -45,10 +96,35 @@ void VprBitstreamAnnotation::set_pb_type_bitstream_source(t_pb_type* pb_type,
const e_bitstream_source_type& bitstream_source) {
bitstream_sources_[pb_type] = bitstream_source;
}
void VprBitstreamAnnotation::set_pb_type_bitstream_content(t_pb_type* pb_type,
const std::string& bitstream_content) {
bitstream_contents_[pb_type] = bitstream_content;
}
void VprBitstreamAnnotation::set_pb_type_bitstream_offset(t_pb_type* pb_type,
const size_t& offset) {
bitstream_offsets_[pb_type] = offset;
}
void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_source(t_pb_type* pb_type,
const e_bitstream_source_type& bitstream_source) {
mode_select_bitstream_sources_[pb_type] = bitstream_source;
}
void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_content(t_pb_type* pb_type,
const std::string& bitstream_content) {
mode_select_bitstream_contents_[pb_type] = bitstream_content;
}
void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_offset(t_pb_type* pb_type,
const size_t& offset) {
mode_select_bitstream_offsets_[pb_type] = offset;
}
void VprBitstreamAnnotation::set_interconnect_default_path_id(t_interconnect* interconnect,
const size_t& default_path_id) {
interconnect_default_path_ids_[interconnect] = default_path_id;
}
} /* End namespace openfpga*/

34
openfpga/src/annotation/vpr_bitstream_annotation.h
View File

@ -33,16 +33,50 @@ class VprBitstreamAnnotation {
public: /* Public accessors */
e_bitstream_source_type pb_type_bitstream_source(t_pb_type* pb_type) const;
std::string pb_type_bitstream_content(t_pb_type* pb_type) const;
size_t pb_type_bitstream_offset(t_pb_type* pb_type) const;
e_bitstream_source_type pb_type_mode_select_bitstream_source(t_pb_type* pb_type) const;
std::string pb_type_mode_select_bitstream_content(t_pb_type* pb_type) const;
size_t pb_type_mode_select_bitstream_offset(t_pb_type* pb_type) const;
size_t interconnect_default_path_id(t_interconnect* interconnect) const;
public: /* Public mutators */
void set_pb_type_bitstream_source(t_pb_type* pb_type,
const e_bitstream_source_type& bitstream_source);
void set_pb_type_bitstream_content(t_pb_type* pb_type,
const std::string& bitstream_content);
void set_pb_type_bitstream_offset(t_pb_type* pb_type,
const size_t& offset);
void set_pb_type_mode_select_bitstream_source(t_pb_type* pb_type,
const e_bitstream_source_type& bitstream_source);
void set_pb_type_mode_select_bitstream_content(t_pb_type* pb_type,
const std::string& bitstream_content);
void set_pb_type_mode_select_bitstream_offset(t_pb_type* pb_type,
const size_t& offset);
void set_interconnect_default_path_id(t_interconnect* interconnect,
const size_t& default_path_id);
private: /* Internal data */
/* For regular bitstreams */
/* A look up for pb type to find bitstream source type */
std::map<t_pb_type*, e_bitstream_source_type> bitstream_sources_;
/* Binding from pb type to bitstream content */
std::map<t_pb_type*, std::string> bitstream_contents_;
/* Offset to be applied to bitstream */
std::map<t_pb_type*, size_t> bitstream_offsets_;
/* For mode-select bitstreams */
/* A look up for pb type to find bitstream source type */
std::map<t_pb_type*, e_bitstream_source_type> mode_select_bitstream_sources_;
/* Binding from pb type to bitstream content */
std::map<t_pb_type*, std::string> mode_select_bitstream_contents_;
/* Offset to be applied to mode-select bitstream */
std::map<t_pb_type*, size_t> mode_select_bitstream_offsets_;
/* A look up for interconnect to find default path indices
* Note: this is different from the default path in bitstream setting which is the index
* of inputs in the context of the interconnect input string
*/
std::map<t_interconnect*, size_t> interconnect_default_path_ids_;
};
} /* End namespace openfpga*/

104
openfpga/src/annotation/vpr_device_annotation.cpp
View File

@ -220,6 +220,21 @@ int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* operating_pb_port
return physical_pb_pin_rotate_offsets_.at(operating_pb_port).at(physical_pb_port);
}
int VprDeviceAnnotation::physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const {
/* Ensure that the pb_type is in the list */
std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_port_rotate_offsets_.find(operating_pb_port);
if (it == physical_pb_port_rotate_offsets_.end()) {
/* Default value is 0 */
return 0;
}
if (0 == physical_pb_port_rotate_offsets_.at(operating_pb_port).count(physical_pb_port)) {
/* Default value is 0 */
return 0;
}
return physical_pb_port_rotate_offsets_.at(operating_pb_port).at(physical_pb_port);
}
int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const {
/* Ensure that the pb_type is in the list */
@ -235,6 +250,21 @@ int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port,
return physical_pb_pin_offsets_.at(operating_pb_port).at(physical_pb_port);
}
int VprDeviceAnnotation::physical_pb_port_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const {
/* Ensure that the pb_type is in the list */
std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_port_offsets_.find(operating_pb_port);
if (it == physical_pb_port_offsets_.end()) {
/* Default value is 0 */
return 0;
}
if (0 == physical_pb_port_offsets_.at(operating_pb_port).count(physical_pb_port)) {
/* Default value is 0 */
return 0;
}
return physical_pb_port_offsets_.at(operating_pb_port).at(physical_pb_port);
}
t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const {
/* Ensure that the pb_type is in the list */
std::map<const t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
@ -278,6 +308,46 @@ LbRRGraph VprDeviceAnnotation::physical_lb_rr_graph(t_pb_graph_node* pb_graph_he
return physical_lb_rr_graphs_.at(pb_graph_head);
}
BasicPort VprDeviceAnnotation::physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const {
/* Try to find the physical tile in the fast look-up */
auto physical_tile_search_result = physical_tile_pin2port_info_map_.find(physical_tile);
if (physical_tile_search_result == physical_tile_pin2port_info_map_.end()) {
/* Not found. Return an invalid port */
return BasicPort();
}
/* Try to find the physical tile port info with pin index */
auto pin_search_result = physical_tile_search_result->second.find(pin_index);
if (pin_search_result == physical_tile_search_result->second.end()) {
/* Not found. Return an invalid port */
return BasicPort();
}
/* Reach here, we should find a port. Return the port information */
return pin_search_result->second;
}
int VprDeviceAnnotation::physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const {
/* Try to find the physical tile in the fast look-up */
auto physical_tile_search_result = physical_tile_pin_subtile_indices_.find(physical_tile);
if (physical_tile_search_result == physical_tile_pin_subtile_indices_.end()) {
/* Not found. Return an invalid index */
return -1;
}
/* Try to find the physical tile port info with pin index */
auto pin_search_result = physical_tile_search_result->second.find(pin_index);
if (pin_search_result == physical_tile_search_result->second.end()) {
/* Not found. Return an invalid index */
return -1;
}
/* Reach here, we should find a port. Return the port information */
return pin_search_result->second;
}
/************************************************************************
* Public mutators
***********************************************************************/
@ -438,6 +508,28 @@ void VprDeviceAnnotation::add_physical_pb_pin_initial_offset(t_port* operating_p
physical_pb_pin_initial_offsets_[operating_pb_port][physical_pb_port] = offset;
}
void VprDeviceAnnotation::add_physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port,
const int& offset) {
/* Warn any override attempt */
std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_port_rotate_offsets_.find(operating_pb_port);
if ( (it != physical_pb_port_rotate_offsets_.end())
&& (0 < physical_pb_port_rotate_offsets_[operating_pb_port].count(physical_pb_port)) ) {
VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s' port rotate offset '%d'!\n",
operating_pb_port->name, offset);
}
physical_pb_port_rotate_offsets_[operating_pb_port][physical_pb_port] = offset;
/* We initialize the accumulated offset to 0 */
physical_pb_port_offsets_[operating_pb_port][physical_pb_port] = 0;
}
void VprDeviceAnnotation::accumulate_physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port) {
physical_pb_port_offsets_[operating_pb_port][physical_pb_port] += physical_pb_port_rotate_offsets_[operating_pb_port][physical_pb_port];
}
void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port,
const int& offset) {
@ -533,4 +625,16 @@ void VprDeviceAnnotation::add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_hea
physical_lb_rr_graphs_[pb_graph_head] = lb_rr_graph;
}
void VprDeviceAnnotation::add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const BasicPort& port) {
physical_tile_pin2port_info_map_[physical_tile][pin_index] = port;
}
void VprDeviceAnnotation::add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const int& subtile_index) {
physical_tile_pin_subtile_indices_[physical_tile][pin_index] = subtile_index;
}
} /* End namespace openfpga*/

30
openfpga/src/annotation/vpr_device_annotation.h
View File

@ -67,6 +67,9 @@ class VprDeviceAnnotation {
int physical_pb_pin_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const;
int physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const;
/**This function returns an accumulated offset. Note that the
* accumulated offset is NOT the pin rotate offset specified by users
* It is an aggregation of the offset during pin pairing
@ -76,11 +79,17 @@ class VprDeviceAnnotation {
*/
int physical_pb_pin_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const;
int physical_pb_port_offset(t_port* operating_pb_port,
t_port* physical_pb_port) const;
t_pb_graph_pin* physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const;
CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
ArchDirectId direct_annotation(const size_t& direct) const;
LbRRGraph physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const;
BasicPort physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const;
int physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const;
public: /* Public mutators */
void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@ -102,6 +111,11 @@ class VprDeviceAnnotation {
void add_physical_pb_pin_initial_offset(t_port* operating_pb_port,
t_port* physical_pb_port,
const int& offset);
void add_physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port,
const int& offset);
void accumulate_physical_pb_port_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port);
void add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
t_port* physical_pb_port,
const int& offset);
@ -110,6 +124,12 @@ class VprDeviceAnnotation {
void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id);
void add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph);
void add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const BasicPort& port);
void add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const int& subtile_index);
private: /* Internal data */
/* Pair a regular pb_type to its physical pb_type */
std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@ -156,8 +176,11 @@ class VprDeviceAnnotation {
std::map<t_port*, std::vector<t_port*>> physical_pb_ports_;
std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_initial_offsets_;
std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_rotate_offsets_;
std::map<t_port*, std::map<t_port*, int>> physical_pb_port_rotate_offsets_;
/* Accumulated offsets for a physical pb_type port, just for internal usage */
/* Accumulated offsets for a physical pb port, just for internal usage */
std::map<t_port*, std::map<t_port*, int>> physical_pb_port_offsets_;
/* Accumulated offsets for a physical pb_graph_pin, just for internal usage */
std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_offsets_;
/* Pair a pb_port to its LSB and MSB of a physical pb_port
@ -197,6 +220,11 @@ class VprDeviceAnnotation {
/* Logical type routing resource graphs built from physical modes */
std::map<t_pb_graph_node*, LbRRGraph> physical_lb_rr_graphs_;
/* A fast look-up from pin index in physical tile to physical tile port */
std::map<t_physical_tile_type_ptr, std::map<int, BasicPort>> physical_tile_pin2port_info_map_;
/* A fast look-up from pin index in physical tile to sub tile index */
std::map<t_physical_tile_type_ptr, std::map<int, int>> physical_tile_pin_subtile_indices_;
};
} /* End namespace openfpga*/

6
openfpga/src/annotation/write_xml_device_rr_gsb.cpp
View File

@ -60,6 +60,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
<< " side=\"" << gsb_side_manager.to_string()
<< "\" index=\"" << inode
<< "\" node_id=\"" << size_t(cur_rr_node)
<< "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size()
<< "\">"
<< std::endl;
@ -85,6 +86,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_node)]
<< "\" side=\"" << chan_side_manager.to_string()
<< "\" node_id=\"" << size_t(driver_node)
<< "\" index=\"" << driver_node_index
<< "\" segment_id=\"" << size_t(des_segment_id)
<< "\"/>"
@ -116,6 +118,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
<< " side=\"" << gsb_side_manager.to_string()
<< "\" index=\"" << inode
<< "\" node_id=\"" << size_t(cur_rr_node)
<< "\" segment_id=\"" << size_t(src_segment_id)
<< "\" mux_size=\"" << driver_rr_edges.size()
<< "\">"
@ -127,6 +130,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
<< "\" side=\"" << oppo_side.to_string()
<< "\" index=\"" << rr_gsb.get_node_index(rr_graph, cur_rr_node, oppo_side.get_side(), IN_PORT)
<< "\" node_id=\"" << size_t(cur_rr_node)
<< "\" segment_id=\"" << size_t(src_segment_id)
<< "\"/>"
<< std::endl;
@ -144,6 +148,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t\t<driver_node type=\"" << rr_node_typename[OPIN]
<< "\" side=\"" << driver_side.to_string()
<< "\" index=\"" << driver_node_index
<< "\" node_id=\"" << size_t(driver_rr_node)
<< "\" grid_side=\"" << grid_side.to_string()
<<"\"/>"
<< std::endl;
@ -152,6 +157,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_rr_node)]
<< "\" side=\"" << driver_side.to_string()
<< "\" index=\"" << driver_node_index
<< "\" node_id=\"" << size_t(driver_rr_node)
<< "\" segment_id=\"" << size_t(des_segment_id)
<< "\"/>"
<< std::endl;

54
openfpga/src/base/io_map.cpp Normal file
View File

@ -0,0 +1,54 @@
/******************************************************************************
* Memember functions for data structure IoMap
******************************************************************************/
#include "vtr_assert.h"
#include "io_map.h"
/* begin namespace openfpga */
namespace openfpga {
IoMap::io_map_range IoMap::io_map() const {
return vtr::make_range(io_map_ids_.begin(), io_map_ids_.end());
}
BasicPort IoMap::io_port(IoMapId io_map_id) const {
VTR_ASSERT(valid_io_map_id(io_map_id));
return io_ports_[io_map_id];
}
BasicPort IoMap::io_net(IoMapId io_map_id) const {
VTR_ASSERT(valid_io_map_id(io_map_id));
return mapped_nets_[io_map_id];
}
bool IoMap::is_io_output(IoMapId io_map_id) const {
VTR_ASSERT(valid_io_map_id(io_map_id));
return IoMap::IO_MAP_DIR_OUTPUT == io_directionality_[io_map_id];
}
bool IoMap::is_io_input(IoMapId io_map_id) const {
VTR_ASSERT(valid_io_map_id(io_map_id));
return IoMap::IO_MAP_DIR_INPUT == io_directionality_[io_map_id];
}
IoMapId IoMap::create_io_mapping(const BasicPort& port,
const BasicPort& net,
IoMap::e_direction dir) {
/* Create a new id */
IoMapId io_map_id = IoMapId(io_map_ids_.size());
io_map_ids_.push_back(io_map_id);
/* Allocate related attributes */
io_ports_.push_back(port);
mapped_nets_.push_back(net);
io_directionality_.push_back(dir);
return io_map_id;
}
bool IoMap::valid_io_map_id(IoMapId io_map_id) const {
return (size_t(io_map_id) < io_map_ids_.size()) && (io_map_id == io_map_ids_[io_map_id]);
}
} /* end namespace openfpga */

59
openfpga/src/base/io_map.h Normal file
View File

@ -0,0 +1,59 @@
#ifndef IO_MAP_H
#define IO_MAP_H
/********************************************************************
* Include header files required by the data structure definition
*******************************************************************/
#include "vtr_vector.h"
#include "openfpga_port.h"
#include "io_map_fwd.h"
/* Begin namespace openfpga */
namespace openfpga {
/********************************************************************
* This is a data structure storing io mapping information
* - the net-to-I/O mapping
* - each I/O directionality
*******************************************************************/
class IoMap {
public: /* Types and ranges */
enum e_direction {
IO_MAP_DIR_INPUT,
IO_MAP_DIR_OUTPUT,
NUM_IO_MAP_DIR_TYPES
};
typedef vtr::vector<IoMapId, IoMapId>::const_iterator io_map_iterator;
typedef vtr::Range<io_map_iterator> io_map_range;
public: /* Public aggregators */
/* Find all io mapping */
io_map_range io_map() const;
/* Get the port of the io that is mapped */
BasicPort io_port(IoMapId io_map_id) const;
/* Get the net of the io that is mapped to */
BasicPort io_net(IoMapId io_map_id) const;
/* Query on if an io is configured as an input */
bool is_io_input(IoMapId io_map_id) const;
/* Query on if an io is configured as an output */
bool is_io_output(IoMapId io_map_id) const;
public: /* Public mutators */
/* Create a new I/O mapping */
IoMapId create_io_mapping(const BasicPort& port,
const BasicPort& net,
e_direction dir);
public: /* Public validators/invalidators */
bool valid_io_map_id(IoMapId io_map_id) const;
private: /* Internal Data */
vtr::vector<IoMapId, IoMapId> io_map_ids_;
vtr::vector<IoMapId, BasicPort> io_ports_;
vtr::vector<IoMapId, BasicPort> mapped_nets_;
vtr::vector<IoMapId, e_direction> io_directionality_;
};
} /* End namespace openfpga*/
#endif

23
openfpga/src/base/io_map_fwd.h Normal file
View File

@ -0,0 +1,23 @@
/**************************************************
* This file includes only declarations for
* the data structures for IoMap
* Please refer to io_map.h for more details
*************************************************/
#ifndef IO_MAP_FWD_H
#define IO_MAP_FWD_H
#include "vtr_strong_id.h"
/* begin namespace openfpga */
namespace openfpga {
/* Strong Ids */
struct io_map_id_tag;
typedef vtr::StrongId<io_map_id_tag> IoMapId;
class IoMap;
} /* end namespace openfpga */
#endif

92
openfpga/src/base/openfpga_bitstream.cpp
View File

@ -10,15 +10,21 @@
/* Headers from openfpgautil library */
#include "openfpga_digest.h"
#include "openfpga_reserved_words.h"
/* Headers from fpgabitstream library */
#include "read_xml_arch_bitstream.h"
#include "write_xml_arch_bitstream.h"
#include "report_arch_bitstream_distribution.h"
#include "openfpga_naming.h"
#include "build_device_bitstream.h"
#include "write_text_fabric_bitstream.h"
#include "write_xml_fabric_bitstream.h"
#include "build_fabric_bitstream.h"
#include "build_io_mapping_info.h"
#include "write_xml_io_mapping.h"
#include "openfpga_bitstream.h"
/* Include global variables of VPR */
@ -86,6 +92,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_file_format = cmd.option("format");
CommandOptionId opt_fast_config = cmd.option("fast_configuration");
/* Write fabric bitstream if required */
int status = CMD_EXEC_SUCCESS;
@ -114,11 +121,96 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
status = write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(),
openfpga_ctx.fabric_bitstream(),
openfpga_ctx.arch().config_protocol,
openfpga_ctx.fabric_global_port_info(),
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_fast_config),
cmd_context.option_enable(cmd, opt_verbose));
}
return status;
}
/********************************************************************
* A wrapper function to call the write_io_mapping() in FPGA bitstream
*******************************************************************/
int write_io_mapping(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_file = cmd.option("file");
/* Write fabric bitstream if required */
int status = CMD_EXEC_SUCCESS;
VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
/* Create directories */
create_directory(src_dir_path);
/* Create a module as the top-level fabric, and add it to the module manager */
std::string top_module_name = generate_fpga_top_module_name();
ModuleId top_module = openfpga_ctx.module_graph().find_module(top_module_name);
VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
/* VPR added a prefix to the output ports, remove them here */
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
IoMap io_map = build_fpga_io_mapping_info(openfpga_ctx.module_graph(),
top_module,
g_vpr_ctx.atom(),
g_vpr_ctx.placement(),
openfpga_ctx.io_location_map(),
openfpga_ctx.vpr_netlist_annotation(),
std::string(),
std::string(),
prefix_to_remove);
status = write_io_mapping_to_xml_file(io_map,
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_verbose));
return status;
}
/********************************************************************
* A wrapper function to call the report_arch_bitstream_distribution() in FPGA bitstream
*******************************************************************/
int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_file = cmd.option("file");
int status = CMD_EXEC_SUCCESS;
VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file));
/* Create directories */
create_directory(src_dir_path);
/* Default depth requirement, this is to limit the report size by default */
int depth = 1;
CommandOptionId opt_depth = cmd.option("depth");
if (true == cmd_context.option_enable(cmd, opt_depth)) {
depth = std::atoi(cmd_context.option_value(cmd, opt_depth).c_str());
/* Error out if we have negative depth */
if (0 > depth) {
VTR_LOG_ERROR("Invalid depth '%d' which should be 0 or a positive number!\n",
depth);
return CMD_EXEC_FATAL_ERROR;
}
}
status = report_architecture_bitstream_distribution(openfpga_ctx.bitstream_manager(),
cmd_context.option_value(cmd, opt_file),
depth);
return status;
}
} /* end namespace openfpga */

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