diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index b465fdee4..b5ef99630 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -7,26 +7,49 @@ assignees: '' --- -**Describe the bug** -A clear and concise description of what the bug is. +> **Describe the bug** +> A clear and concise description of what the bug is. + + + + + + + + + + -**To Reproduce** -Steps to reproduce the behavior: -1. Go to '...' -2. Click on '....' -3. Scroll down to '....' -4. See error +> **To Reproduce** +> Steps to reproduce the behavior: +> 1. Clone OpenFPGA repository and checkout commit id: +> 2. Execute OpenFPGA task or your own example: +> 3. See error -**Expected behavior** -A clear and concise description of what you expected to happen. +> **Expected behavior** +> A clear and concise description of what you expected to happen. -**Screenshots** -If applicable, add screenshots to help explain your problem. +> **Screenshots** +> If applicable, add screenshots to help explain your problem. -**Enviornment (please complete the following information):** - - OS: [e.g. CentOs, Ubuntu] - - Compiler [e.g. gcc, clang] - - Version [e.g. Github commit id] +> **Enviornment (please complete the following information):** + +> - OS: + + + +> - Compiler: + + + + + + + + +> - Version: + + -**Additional context** -Add any other context about the problem here. +> **Additional context** +> Add any other context about the problem here. diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index d1c458c04..f1b1063fd 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -1,33 +1,39 @@ ---- -name: Pull request -about: Push a change to this project ---- +> ### Motivate of the pull request +> - [ ] To address an existing issue. If so, please provide a link to the issue: +> - [ ] Breaking new feature. If so, please describe details in the description part. -### Motivate of the pull request -- [ ] To address an existing issue. If so, please provide a link to the issue. -- [ ] Breaking new feature. If so, please decribe details in the description part. +> ### Describe the technical details +> #### What is currently done? (Provide issue link if applicable) +> +> +> +> +> +> +> #### What does this pull request change? +> +> +> +> +> -### Describe the technical details -- What is currently done? (Provide issue link if applicable) -- What does this pull request change? +> ### Which part of the code base require a change +> +> - [ ] VPR +> - [ ] Tileable routing architecture generator +> - [ ] OpenFPGA libraries +> - [ ] FPGA-Verilog +> - [ ] FPGA-Bitstream +> - [ ] FPGA-SDC +> - [ ] FPGA-SPICE +> - [ ] Flow scripts +> - [ ] Architecture library +> - [ ] Cell library +> - [ ] Documentation +> - [ ] Regression tests +> - [ ] Continous Integration (CI) scripts -### Which part of the code base require a change -**In general, modification on existing submodules are not acceptable. You should push changes to upstream.** -- [ ] VPR -- [ ] OpenFPGA libraries -- [ ] FPGA-Verilog -- [ ] FPGA-Bitstream -- [ ] FPGA-SDC -- [ ] FPGA-SPICE -- [ ] Flow scripts -- [ ] Architecture library -- [ ] Cell library +> ### Impact of the pull request -### Checklist of the pull request -- [ ] Require code changes. -- [ ] Require new tests to be added -- [ ] Require an update on documentation - -### Impact of the pull request -- [ ] Require a change on Quality of Results (QoR) -- [ ] Break back-compatibility. If so, please list who may be influenced. +> - [ ] Require a change on Quality of Results (QoR) +> - [ ] Break back-compatibility. If so, please list who may be influenced. diff --git a/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md index d1c458c04..f1b1063fd 100644 --- a/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md +++ b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md @@ -1,33 +1,39 @@ ---- -name: Pull request -about: Push a change to this project ---- +> ### Motivate of the pull request +> - [ ] To address an existing issue. If so, please provide a link to the issue: +> - [ ] Breaking new feature. If so, please describe details in the description part. -### Motivate of the pull request -- [ ] To address an existing issue. If so, please provide a link to the issue. -- [ ] Breaking new feature. If so, please decribe details in the description part. +> ### Describe the technical details +> #### What is currently done? (Provide issue link if applicable) +> +> +> +> +> +> +> #### What does this pull request change? +> +> +> +> +> -### Describe the technical details -- What is currently done? (Provide issue link if applicable) -- What does this pull request change? +> ### Which part of the code base require a change +> +> - [ ] VPR +> - [ ] Tileable routing architecture generator +> - [ ] OpenFPGA libraries +> - [ ] FPGA-Verilog +> - [ ] FPGA-Bitstream +> - [ ] FPGA-SDC +> - [ ] FPGA-SPICE +> - [ ] Flow scripts +> - [ ] Architecture library +> - [ ] Cell library +> - [ ] Documentation +> - [ ] Regression tests +> - [ ] Continous Integration (CI) scripts -### Which part of the code base require a change -**In general, modification on existing submodules are not acceptable. You should push changes to upstream.** -- [ ] VPR -- [ ] OpenFPGA libraries -- [ ] FPGA-Verilog -- [ ] FPGA-Bitstream -- [ ] FPGA-SDC -- [ ] FPGA-SPICE -- [ ] Flow scripts -- [ ] Architecture library -- [ ] Cell library +> ### Impact of the pull request -### Checklist of the pull request -- [ ] Require code changes. -- [ ] Require new tests to be added -- [ ] Require an update on documentation - -### Impact of the pull request -- [ ] Require a change on Quality of Results (QoR) -- [ ] Break back-compatibility. If so, please list who may be influenced. +> - [ ] Require a change on Quality of Results (QoR) +> - [ ] Break back-compatibility. If so, please list who may be influenced. diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9b81db480..77ccb1527 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -210,7 +210,10 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: micro_benchmark_reg_test - name: quicklogic_reg_test + - name: vtr_benchmark_reg_test + - name: iwls_benchmark_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 @@ -255,7 +258,10 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: micro_benchmark_reg_test - name: quicklogic_reg_test + - name: vtr_benchmark_reg_test + - name: iwls_benchmark_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 diff --git a/.github/workflows/install_dependencies_build.sh b/.github/workflows/install_dependencies_build.sh index 3f6ef089e..4741cf053 100644 --- a/.github/workflows/install_dependencies_build.sh +++ b/.github/workflows/install_dependencies_build.sh @@ -37,4 +37,5 @@ apt-get update && apt-get install -y \ texinfo \ time \ valgrind \ + wget \ zip diff --git a/.github/workflows/install_dependencies_run.sh b/.github/workflows/install_dependencies_run.sh index 3efb3affb..4c022ee15 100644 --- a/.github/workflows/install_dependencies_run.sh +++ b/.github/workflows/install_dependencies_run.sh @@ -1,4 +1,4 @@ apt-get install --no-install-recommends -y \ libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \ libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \ -iverilog git rsync make curl +iverilog git rsync make curl wget diff --git a/CMakeLists.txt b/CMakeLists.txt index 49b2fa1fb..a6a055ba1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -91,7 +91,6 @@ else () "-D__USE_FIXED_PROTOTYPES__" "-ansi" "-Wshadow" - "-Wcast-allign" "-Wno-write-strings" "-D_POSIX_SOURCE" "-Wall" #Most warnings, typically good diff --git a/README.md b/README.md index e71c1f637..9a9238b94 100644 --- a/README.md +++ b/README.md @@ -8,14 +8,14 @@ The award-winning OpenFPGA framework is the **first open-source FPGA IP generato **If this is the first time you learn OpenFPGA, we strongly recommend you to watch the [introduction video about OpenFPGA](https://youtu.be/ocODUGcYGqo)** -A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/tools/). -We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights.html) before compiling. +A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/tools/). +We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights/#) before compiling. ## Compilation **A tutorial video about how-to-compile can be found [here](https://youtu.be/F9sMRmDewM0)** -Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/compile). +Before start, we strongly recommend you to read the required dependencies at [**compilation guidelines**](https://openfpga.readthedocs.io/en/master/tutorials/getting_started/compile/). It also includes detailed information about docker image. --- @@ -55,4 +55,4 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl ## Tutorials -You can find some tutorials in the [**./tutorials**](./docs/source/tutorials/) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations. +You can find a set of [tutorials](https://openfpga.readthedocs.io/en/master/tutorials/), with which you get familiar with the tool and use OpenFPGA in various purposes. diff --git a/docs/source/faq.rst b/docs/source/faq.rst new file mode 100644 index 000000000..035cbc2a7 --- /dev/null +++ b/docs/source/faq.rst @@ -0,0 +1,47 @@ +.. _faq: + +Frequently Asked Questions +========================== + +Where is the best place to get help with OpenFPGA? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Currently, we have an active github issues page found `here `_. Users can see if their +questions have already been answered by searching the open or closed issues, and users are recommended to post questions there first. +Asking questions on the github issues page allows us to answer the question for everyone who may be experiencing similar problems as +well. + +What should I do if check-in tests failed when first installing OpenFPGA? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +First, check to make sure all dependencies for OpenFPGA and Python have been installed and are up-to-date on the desired device. To see the full +list of depenencies, please visit +`our github dependencies page `_. +This issue has been discussed `in issue 280 `_. + + +How to sweep design parameters in a task run of OpenFPGA design flow? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Testing multiple script parameters for a variable is possible by modifying the task.conf file. Doing so will create a job for +each combination of the variables. A solution is discussed `in issue 228 `_. + + +How do I setup OpenFPGA to be used by multiple users on a single device? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +OpenFPGA can support multiple users on a shared device using the environment variable ``OPENFPGA_ROOT``. The OpenFPGA script for +running tasks needs ``OPENFPGA_ROOT`` to be the path to the OpenFPGA root directory. Users can then run the script on a task in the +current working directory. A solution is discussed `in issue 209 `_. + + +How do I contribute to OpenFPGA? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Users of OpenFPGA that are interested in contributing must complete the following: + + - Create a branch. For external collaborators, please fork the repository first and create a branch in the fork. + - Creatre a pull request and fill out our pull request template. It is easy for us to acknowledge and review your pull request. + - Wait or keep debugging until all the CI tests pass. + - Request for a review. You may expect several rounds of review and discussion before the pull request is approved. + diff --git a/docs/source/index.rst b/docs/source/index.rst index df991919f..be9a43257 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -36,6 +36,7 @@ Welcome to OpenFPGA's documentation! contact reference + faq For more information on the VTR see vtr_doc_ or vtr_github_ diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index ea128cb1c..f4767c938 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -136,6 +136,8 @@ When a global port, e.g., ``clk``, is defined in ``tile_annotation`` using the f Clock port ``clk`` of each ``clb`` tile will be connected to a common clock port of the top module, while local clock network is customizable through VPR's architecture description language. For instance, the local clock network can be a programmable clock network. +.. _annotate_vpr_arch_pb_type_annotation: + Primitive Blocks inside Multi-mode Configurable Logic Blocks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -221,7 +223,9 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de .. note:: A ```` parent XML node is required for the interconnect-to-circuit bindings whose interconnects are defined under the ``pb_type`` in VPR architecture description. .. option:: + physical_mode_pin_initial_offset="" + physical_mode_pin_rotate_offset=""/> + physical_mode_port_rotate_offset=""/> Link a port of an operating ``pb_type`` to a port of a physical ``pb_type`` @@ -231,7 +235,6 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de .. note:: Users can define multiple ports. For example: ``physical_mode_pin="a[0:1] b[2:2]"``. When multiple ports are used, the ``physical_mode_pin_initial_offset`` and ``physical_mode_pin_rotate_offset`` should also be adapt. For example: ``physical_mode_pin_rotate_offset="1 0"``) - - ``physical_mode_pin_initial_offset=""`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when part of port of operating mode is mapped to a port in physical ``pb_type``. When ``physical_mode_pin_initial_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. .. note:: A quick example to understand the initial offset @@ -247,7 +250,24 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de .. note:: If not defined, the default value of ``physical_mode_pin_initial_offset`` is set to ``0``. - - ``physical_mode_pin_rotate_offset=""`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. + - ``physical_mode_pin_rotate_offset=""`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset, **each time a pin in the operating mode is binded to a pin in the physical mode**. + + .. note:: A quick example to understand the rotate offset + For example, a rotating offset of 9 is used to map + + - operating pb_type ``mult_9x9[0].a[0]`` with a full path ``mult[frac].mult_9x9[0]`` + - operating pb_type ``mult_9x9[1].a[1]`` with a full path ``mult[frac].mult_9x9[1]`` + + to + + - physical pb_type ``mult_36x36.a[0]`` with a full path ``mult[physical].mult_36x36[0]`` + - physical pb_type ``mult_36x36.a[9]`` with a full path ``mult[physical].mult_36x36[0]`` + + .. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``. + + .. warning:: The result of using ``physical_mode_pin_rotate_offset`` is fundementally different than ``physical_mode_port_rotate_offset``!!! Please read the examples carefully and pick the one fitting your needs. + + - ``physical_mode_port_rotate_offset=""`` aims to align the port indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_port_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset, **only when all the pins of a port in the operating mode is binded to all the pins of a port in the physical mode**. .. note:: A quick example to understand the rotate offset For example, a rotating offset of 9 is used to map @@ -260,7 +280,8 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de - physical pb_type ``mult_36x36.a[0:8]`` with a full path ``mult[physical].mult_36x36[0]`` - physical pb_type ``mult_36x36.a[9:17]`` with a full path ``mult[physical].mult_36x36[0]`` - .. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``. + .. note:: If not defined, the default value of ``physical_mode_port_rotate_offset`` is set to ``0``. + .. note:: It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description. diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index a7a6dba97..7113be1c0 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -284,6 +284,8 @@ This example shows: SRAMs ~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for SRAM cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -963,16 +965,17 @@ This example shows: .. note:: If the embedded harden logic are driven partially by LUT outputs, users may use the :ref:`file_formats_bitstream_setting` to gaurantee correct bitstream generation for the LUTs. +Datapath Flip-Flops +~~~~~~~~~~~~~~~~~~~ -Flip-Flops -~~~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for datapath flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. Template ```````` .. code-block:: xml - + @@ -987,16 +990,14 @@ Template .. note:: FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1. -.. option:: +.. option:: type="ff" - - ``type="ccff|ff"`` Specify the type of a flip-flop. ``ff`` is a regular flip-flop while ``ccff`` denotes a configuration-chain flip-flop + ``ff`` is a regular flip-flop to be used in datapath logic, e.g., a configurable logic block. .. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``. .. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. -.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic. - .. _circuit_model_dff_example: D-type Flip-Flop @@ -1029,6 +1030,70 @@ This example shows: - The flip-flop has ``set`` and ``reset`` functionalities - The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file +.. _circuit_model_multi_mode_ff_example: + +Multi-mode Flip-Flop +```````````````````` + +:numref:`fig_multi_mode_ff_circuit_model` illustrates an example of a flip-flop which can be operate in different modes. + +.. _fig_multi_mode_ff_circuit_model: + +.. figure:: ./figures/multi_mode_ff_circuit_model.svg + :scale: 150% + :alt: Multi-mode flip-flop example + + An example of a flip-flop which can be operate in different modes + +The code describing this FF is: + +.. code-block:: xml + + + + + + + + + +This example shows: + - A multi-mode flip-flop which is defined in a Verilog netlist ``frac_ff.v`` and a SPICE netlist ``frac_ff.sp`` + - The flip-flop has a ``reset`` pin which can be either active-low or active-high, depending on the mode selection pin ``MODE``. + - The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`). + - The flip-flop port names defined differently in standard cell library and VPR architecture. The ``lib_name`` capture the port name defined in standard cells, while ``prefix`` capture the port name defined in ``pb_type`` of VPR architecture file + +Configuration Chain Flip-Flop +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. note:: OpenFPGA does not auto-generate any netlist for configuration chain flip-flops. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + +Template +```````` + +.. code-block:: xml + + + + + + + + + + +.. note:: The circuit designs of configurable memory elements are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package. + + The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating SPICE testbenches, which may leads to larger errors in power analysis. + +.. note:: FPGA-Verilog/SPICE currently support only one clock domain for any configuration protocols in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1. + +.. note:: A flip-flop should at least have three types of ports, ``input``, ``output`` and ``clock``. + +.. note:: If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. + +.. note:: In a valid FPGA architecture, users should provide at least either a ``ccff`` or ``sram`` circuit model, so that the configurations can loaded to core logic. + .. _circuit_model_ccff_example: Regular Configuration-chain Flip-flop @@ -1147,6 +1212,8 @@ The code describing this FF is: Hard Logics ~~~~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for the hard logics. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` @@ -1175,6 +1242,13 @@ Template Full Adder `````````` +.. figure:: ./figures/full_adder_1bit_circuit_model.svg + :scale: 200% + :alt: An example of a 1-bit full adder + + An example of a 1-bit full adder. + +The code describing the 1-bit full adder is: .. code-block:: xml @@ -1189,6 +1263,134 @@ Full Adder +This example shows: + - A 1-bit full adder which is defined in a Verilog netlist ``adder.v`` and a SPICE netlist ``adder.sp`` + - The adder has three 1-bit inputs, i.e., ``a``, ``b`` and ``cin``, and two 2-bit outputs, i.e., ``cout``, ``sumout``. + +.. _circuit_model_single_mode_mult8x8_example: + +Multiplier +`````````` + +.. figure:: ./figures/single_mode_mult8x8_circuit_model.svg + :scale: 200% + :alt: An example of a 8-bit multiplier. + + An example of a 8-bit multiplier. + +The code describing the multiplier is: + +.. code-block:: xml + + + + + + + + + + +This example shows: + - A 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp`` + +.. _circuit_model_multi_mode_mult8x8_example: + +Multi-mode Multiplier +````````````````````` + +.. figure:: ./figures/multi_mode_mult8x8_circuit_model.svg + :scale: 200% + :alt: An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier + + An example of a 8-bit multiplier which can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier + +The code describing the multiplier is: + +.. code-block:: xml + + + + + + + + + + + +This example shows: + - A multi-mode 8-bit multiplier which is defined in a Verilog netlist ``dsp.v`` and a SPICE netlist ``dsp.sp`` + - The multi-mode multiplier can operating in two modes: (1) dual 4-bit multipliers; and (2) 8-bit multiplier + - The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`). + +.. _circuit_model_single_mode_dpram_example: + +Dual Port Block RAM +``````````````````` + +.. figure:: ./figures/single_mode_dpram128x8_memory_circuit_model.svg + :scale: 150% + :alt: An example of a dual port block RAM with 128 addresses and 8-bit data width. + + An example of a dual port block RAM with 128 addresses and 8-bit data width. + +The code describing this block RAM is: + +.. code-block:: xml + + + + + + + + + + + + + + +This example shows: + - A 128x8 dual port RAM which is defined in a Verilog netlist ``dpram.v`` and a SPICE netlist ``dpram.sp`` + - The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`). + +.. _circuit_model_multi_mode_dpram_example: + +Multi-mode Dual Port Block RAM +`````````````````````````````` + +.. figure:: ./figures/multi_mode_dpram128x8_memory_circuit_model.svg + :scale: 150% + :alt: An example of a multi-mode dual port block RAM with 128 addresses and 8-bit data width. + + An example of a dual port block RAM which can operate in two modes: 128x8 and 256x4. + +The code describing this block RAM is: + +.. code-block:: xml + + + + + + + + + + + + + + + +This example shows: + - A fracturable dual port RAM which is defined in a Verilog netlist ``frac_dpram.v`` and a SPICE netlist ``frac_dpram.sp`` + - The dual port RAM can operate in two modes: (1) 128 addresses with 8-bit data width; (2) 256 addresses with 4-bit data width + - The clock port of the RAM is controlled by a global signal (see details about global signal definition in :ref:`annotate_vpr_arch_physical_tile_annotation`). + - The mode-selection bit will be generated by a configurable memory outside the flip-flop, which will be implemented by a circuit model ``CCFF`` defined by users (see an example in :ref:`circuit_model_ccff_example`). + Routing Wire Segments ~~~~~~~~~~~~~~~~~~~~~ @@ -1255,6 +1457,8 @@ This example shows I/O pads ~~~~~~~~ +.. note:: OpenFPGA does not auto-generate any netlist for I/O cells. Users should define the HDL modeling in external netlists and ensure consistency to physical designs. + Template ```````` diff --git a/docs/source/manual/arch_lang/figures/frac_lut3_example.svg b/docs/source/manual/arch_lang/figures/frac_lut3_example.svg index 78582dd61..dd0025266 100644 --- a/docs/source/manual/arch_lang/figures/frac_lut3_example.svg +++ b/docs/source/manual/arch_lang/figures/frac_lut3_example.svg @@ -1,6 +1,6 @@ - + @@ -48,8 +48,8 @@ - Produced by OmniGraffle 7.18\n2020-11-26 19:26:01 +0000 - + Produced by OmniGraffle 7.18.4\n2021-03-15 17:35:45 +0000 + frac_lut3_example Legend @@ -267,12 +267,12 @@ - + in_buf - + in_inv diff --git a/docs/source/manual/arch_lang/figures/full_adder_1bit_circuit_model.svg b/docs/source/manual/arch_lang/figures/full_adder_1bit_circuit_model.svg new file mode 100644 index 000000000..dc7ff3837 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/full_adder_1bit_circuit_model.svg @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 20:57:16 +0000 + + 1-bit full adder + + Layer 1 + + + + + adder + + + + + + cin + + + + + a + + + + + b + + + + + + + + + + + + + + sumout + + + + + + + + cout + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg b/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg new file mode 100644 index 000000000..ff02de2fc --- /dev/null +++ b/docs/source/manual/arch_lang/figures/multi_mode_dpram128x8_memory_circuit_model.svg @@ -0,0 +1,342 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 20:15:49 +0000 + + multi_mode_dual_port_bram 1 + + Layer 1 + + + + + + + + + + + + + + + + + + + + + + + clock + + + + + raddr[7:0] + + + + + waddr[7:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + + + + + + + + + clock + + + + + raddr[6:0] + + + + + waddr[6:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + ‘1’ + + + + + + + + + + + + + clock + + + + + raddr[7:0] + + + + + waddr[7:0] + + + + + wen + + + + + ren + + + + + data_in[3:0] + + + + + data_out[3:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + mode + + + + + + + + ‘0’ + + + + + Operating mode 2: Dual port 256 + x + 4 RAM + + + + + Operating mode 1: Dual port 128x8 RAM + + + + + Schematic: Multi-mode dual port 128x8/256x4 RAM + + + + + + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/multi_mode_ff_circuit_model.svg b/docs/source/manual/arch_lang/figures/multi_mode_ff_circuit_model.svg new file mode 100644 index 000000000..de4016044 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/multi_mode_ff_circuit_model.svg @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 18:52:28 +0000 + + multi_mode_ff + + Layer 1 + + + + + + + + + FF + + + + + D + + + + + CLK + + + + + + + + + + + + + + + + + + Q + + + + + RST + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Multi-mode FF + + + + + Q + + + + + D + + + + + MODE + + + + + CLK + + + + + RST_OP + + + + + diff --git a/docs/source/manual/arch_lang/figures/multi_mode_mult8x8_circuit_model.svg b/docs/source/manual/arch_lang/figures/multi_mode_mult8x8_circuit_model.svg new file mode 100644 index 000000000..8c9b5f2a1 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/multi_mode_mult8x8_circuit_model.svg @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 21:09:05 +0000 + + multi_mode_mult_8x8 + + Layer 1 + + + + + + + + + + + + + MULT + 8x8 + + + + + a[7:0] + + + + + b[7:0] + + + + + + + + + + + + + + out[15:0] + + + + + + + + + + + + + MULT + 4x4 + [0] + + + + + a[7:4] + + + + + b[7:4] + + + + + + + + + + + + + + out[15:8] + + + + + + + + + + + + + MULT + 4x4 + [1] + + + + + a[3:0] + + + + + b[3:0] + + + + + + + + + + + + + + out[7:0] + + + + + + + + + + + Operating mode 1: Dual 4x4 multiplier + + + + + + + + mode + + + + + Schematic: multi-mode 8x8 multiplier + + + + + + + + + + + MULT + 8x8 + + + + + a[7:0] + + + + + b[7:0] + + + + + + + + + + + + + + out[15:0] + + + + + + + + + + + Operating mode 2: 8x8 multiplier + + + + + + + + mode=‘0’ + + + + + + + + + + + + + + + + mode=‘1’ + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/single_lut3_example.svg b/docs/source/manual/arch_lang/figures/single_lut3_example.svg index 6435ff602..a6bde93c4 100644 --- a/docs/source/manual/arch_lang/figures/single_lut3_example.svg +++ b/docs/source/manual/arch_lang/figures/single_lut3_example.svg @@ -1,6 +1,6 @@ - + @@ -48,8 +48,8 @@ - Produced by OmniGraffle 7.18\n2020-11-26 19:26:01 +0000 - + Produced by OmniGraffle 7.18.4\n2021-03-15 17:35:45 +0000 + single_lut3_example Legend @@ -248,12 +248,12 @@ - + in_buf - + in_inv diff --git a/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg b/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg new file mode 100644 index 000000000..458155c98 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/single_mode_dpram128x8_memory_circuit_model.svg @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 19:57:04 +0000 + + single_mode_dual_port_bram + + Layer 1 + + + + + + + + + + + clock + + + + + raddr[6:0] + + + + + waddr[6:0] + + + + + wen + + + + + ren + + + + + data_in[7:0] + + + + + data_out[7:0] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/source/manual/arch_lang/figures/single_mode_mult8x8_circuit_model.svg b/docs/source/manual/arch_lang/figures/single_mode_mult8x8_circuit_model.svg new file mode 100644 index 000000000..41ac61370 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/single_mode_mult8x8_circuit_model.svg @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-05-24 21:09:05 +0000 + + single_mode_mult_8x8 + + Layer 1 + + + + + MULT + 8x8 + + + + + a[7:0] + + + + + b[7:0] + + + + + + + + + + + + + + out[15:0] + + + + + + + + + + + diff --git a/docs/source/manual/file_formats/bitstream_distribution_file.rst b/docs/source/manual/file_formats/bitstream_distribution_file.rst new file mode 100644 index 000000000..a1f3282d2 --- /dev/null +++ b/docs/source/manual/file_formats/bitstream_distribution_file.rst @@ -0,0 +1,50 @@ +.. _file_format_bitstream_distribution_file: + +Bitstream Distribution File (.xml) +---------------------------------- + +The bitstream distribution file aims to show + +- The total number of configuration bits under each block +- The number of configuration bits per block + +An example of design constraints is shown as follows. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +.. option:: name="" + + The block name represents the instance name which you can find in the fabric netlists + +.. option:: number_of_bits="" + + The total number of configuration bits in this block diff --git a/docs/source/manual/file_formats/bitstream_setting.rst b/docs/source/manual/file_formats/bitstream_setting.rst index b21bd0c25..764bf0c87 100644 --- a/docs/source/manual/file_formats/bitstream_setting.rst +++ b/docs/source/manual/file_formats/bitstream_setting.rst @@ -6,22 +6,68 @@ Bitstream Setting (.xml) An example of bitstream settings is shown as follows. This can define a hard-coded bitstream for a reconfigurable resource in FPGA fabrics. +.. warning:: Bitstream setting is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream. + .. code-block:: xml - + + -.. option:: pb_type="" +pb_type-related Settings +^^^^^^^^^^^^^^^^^^^^^^^^ - The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, ``pb_type="clb.fle[arithmetic].soft_adder.adder_lut4"`` +The following syntax are applicable to the XML definition tagged by ``pb_type`` in bitstream setting files. + +.. option:: name="" + + The ``pb_type`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, + + .. code-block:: xml + + pb_type="clb.fle[arithmetic].soft_adder.adder_lut4" .. option:: source="" - The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, ``source="eblif"``. + The source of the ``pb_type`` bitstream, which could be from a ``.eblif`` file. For example, + + .. code-block:: xml + + source="eblif" .. option:: content="" The content of the ``pb_type`` bitstream, which could be a keyword in a ``.eblif`` file. For example, ``content=".attr LUT"`` means that the bitstream will be extracted from the ``.attr LUT`` line which is defined under the ``.blif model`` (that is defined under the ``pb_type`` in VPR architecture file). -.. warning:: Bitstream is a feature for power-users. It may cause wrong bitstream to be generated. For example, the hard-coded bitstream is not compatible with LUTs whose nets may be swapped during routing stage (cause a change on the truth table as well as bitstream). It is users's responsibility to ensure correct bitstream. + +.. option:: is_mode_select_bitstream="" + + Can be either ``true`` or ``false``. When set ``true``, the bitstream is considered as mode-selection bitstream, which may overwrite ``mode_bits`` definition in ``pb_type_annotation`` of OpenFPGA architecture description. (See details in :ref:`annotate_vpr_arch_pb_type_annotation`) + +.. option:: bitstream_offset="" + + Specify the offset to be applied when overloading the bitstream to a target. For example, a LUT may have a 16-bit bitstream. When ``offset=1``, bitstream overloading will skip the first bit and start from the second bit of the 16-bit bitstream. + +Interconnection-related Settings +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following syntax are applicable to the XML definition tagged by ``interconnect`` in bitstream setting files. + +.. option:: name="" + + The ``interconnect`` name to be constrained, which should be the full path of a ``pb_type`` consistent with VPR's architecture description. For example, + + .. code-block:: xml + + pb_type="clb.fle[arithmetic].mux1" + +.. option:: default_path="" + + The default path denotes an input name that is consistent with VPR's architecture description. For example, in VPR architecture, there is a mux defined as + + .. code-block:: xml + + + + The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively. diff --git a/docs/source/manual/file_formats/fabric_bitstream.rst b/docs/source/manual/file_formats/fabric_bitstream.rst index ce321cc81..2def5d269 100644 --- a/docs/source/manual/file_formats/fabric_bitstream.rst +++ b/docs/source/manual/file_formats/fabric_bitstream.rst @@ -5,7 +5,7 @@ Fabric-dependent Bitstream .. _file_formats_fabric_bitstream_plain_text: -Plain text (.txt) +Plain text (.bit) ~~~~~~~~~~~~~~~~~ This file format is designed to be directly loaded to an FPGA fabric. @@ -19,40 +19,76 @@ The information depends on the type of configuration procotol. .. option:: scan_chain - A line consisting of ``0`` | ``1`` + Multiple lines consisting of ``0`` | ``1`` + + For example, a bitstream for 1 configuration regions: + + .. code-block:: xml + + 0 + 1 + 0 + 0 + + For example, a bitstream for 4 configuration regions: + + .. code-block:: xml + + 0000 + 1010 + 0110 + 0120 + + .. note:: When there are multiple configuration regions, each line may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively. .. option:: memory_bank - Multiple lines will be included, each of which is organized as
. - Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired. - The first line represents the Bit-Line address and configuration bit. - The second line represents the Word-Line address and configuration bit. + Multiple lines will be included, each of which is organized as . + The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader. + For example + + .. code-block:: verilog + + // Bitstream width (LSB -> MSB): + + The first part represents the Bit-Line address. + The second part represents the Word-Line address. + The third part represents the configuration bit. For example .. code-block:: xml - - - - + + ... - - + + + .. note:: When there are multiple configuration regions, each ```` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively. .. option:: frame_based - Multiple lines will be included, each of which is organized as
. + Multiple lines will be included, each of which is organized as ``
``. + The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader. + For example + + .. code-block:: verilog + + // Bitstream width (LSB -> MSB):
+ Note that the address may include don't care bit which is denoted as ``x``. - OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches. + + .. note:: OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches. + For example .. code-block:: xml - - + + ... - + + .. note:: When there are multiple configuration regions, each ```` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively. .. _file_formats_fabric_bitstream_xml: @@ -61,7 +97,21 @@ XML (.xml) This file format is designed to generate testbenches using external tools, e.g., CocoTB. -In principle, the file consist a number of XML node ````, each bit contains the following attributes: +In principle, the file consist a number of XML node ````, each region has a unique id, and contains a number of XML nodes ````. + +- ``id``: The unique id of a configuration region in the fabric bitstream. + +A quick example: + +.. code-block:: xml + + + + + + + +Each XML node ```` contains the following attributes: - ``id``: The unique id of the configuration bit in the fabric bitstream. diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index f02218cd3..7ed213012 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -21,3 +21,7 @@ OpenFPGA widely uses XML format for interchangable files bitstream_setting fabric_key + + io_mapping_file + + bitstream_distribution_file diff --git a/docs/source/manual/file_formats/io_mapping_file.rst b/docs/source/manual/file_formats/io_mapping_file.rst new file mode 100644 index 000000000..722f477f6 --- /dev/null +++ b/docs/source/manual/file_formats/io_mapping_file.rst @@ -0,0 +1,33 @@ +.. _file_format_io_mapping_file: + +I/O Mapping File (.xml) +----------------------- + +The I/O mapping file aims to show + +- What nets have been mapped to each I/O +- What is the directionality of each mapped I/O + +An example of design constraints is shown as follows. + +.. code-block:: xml + + + + + + + +.. option:: name="" + + The pin name of the FPGA fabric which has been mapped, which should be a valid pin defined in OpenFPGA architecture description. + + .. note:: You should be find the exact pin in the top-level module of FPGA fabric if you output the Verilog netlists. + +.. option:: net="" + + The net name which is actually mapped to a pin, which should be consistent with net definition in your ``.blif`` file. + +.. option:: dir="" + + The direction of an I/O, which can be either ``input`` or ``output``. diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst index c2a71c596..063b27542 100644 --- a/docs/source/manual/file_formats/pin_constraints_file.rst +++ b/docs/source/manual/file_formats/pin_constraints_file.rst @@ -10,7 +10,7 @@ An example of design constraints is shown as follows. .. code-block:: xml - + @@ -23,3 +23,11 @@ An example of design constraints is shown as follows. .. option:: net="" The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file. + +.. option:: default_value="" + + The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli. + + .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration. + + .. note:: The default value in pin constraint file has a higher priority than the ``default_value`` syntax in the :ref:`circuit_library`. diff --git a/docs/source/manual/file_formats/repack_design_constraints.rst b/docs/source/manual/file_formats/repack_design_constraints.rst index 5771123c2..56f40c310 100644 --- a/docs/source/manual/file_formats/repack_design_constraints.rst +++ b/docs/source/manual/file_formats/repack_design_constraints.rst @@ -3,6 +3,11 @@ Repack Design Constraints (.xml) -------------------------------- +.. warning:: For the best practice, current repack design constraints only support the net remapping between pins in the same port. Pin constraints are **NOT** allowed for two separated ports. + + - A legal pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two pins in a clock port ``clk[0:2]`` (e.g., ``clk[0] = clk0`` and ``clk[1] == clk1``). + - An **illegal** pin constraint example: when there are two clock nets, ``clk0`` and ``clk1``, pin constraints are forced on two clock ports ``clkA[0]`` and ``clkB[0]`` (e.g., ``clkA[0] = clk0`` and ``clkB[0] == clk1``). + An example of design constraints is shown as follows. .. code-block:: xml @@ -25,5 +30,5 @@ An example of design constraints is shown as follows. .. option:: net="" The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file. - + .. warning:: Design constraints is a feature for power-users. It may cause repack to fail. It is users's responsibility to ensure proper design constraints diff --git a/docs/source/manual/fpga_verilog/figures/full_testbench_block_diagram.svg b/docs/source/manual/fpga_verilog/figures/full_testbench_block_diagram.svg new file mode 100644 index 000000000..4e528898b --- /dev/null +++ b/docs/source/manual/fpga_verilog/figures/full_testbench_block_diagram.svg @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-06-03 22:42:19 +0000 + + block_diagram + + + Layer 1 + + + + + Bitstream file + + + + + + + + block_diagram + + + + + FPGA + Fabric + + + + + + + User’s + Design + + + + + + + Output + Checker + + + + + Input stimulus + + + + + + + + + + + + + + Number of + errors + + + + + FPGA output vectors + + + + + Expected output vectors + + + + + + + + + + + diff --git a/docs/source/manual/fpga_verilog/figures/full_testbench_waveform.svg b/docs/source/manual/fpga_verilog/figures/full_testbench_waveform.svg new file mode 100644 index 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+ vvv-6 + + + + + + + + + + + + Text + + Number of errors + + + + + + wavegaps_0 + + wavegap_0_0 + + gap + + + + + + + + + + + + + wavegap_1_0 + + gap + + + + + + + + + + + + + wavegap_2_0 + + gap + + + + + + + + + + + + + wavegap_3_0 + + gap + + + + + + + + + + + + + wavegap_4_0 + + gap + + + + + + + + + + + + + wavegap_5_0 + + gap + + + + + + + + + + + + + wavegap_6_0 + + gap + + + + + + + + + + + + + wavegap_7_0 + + gap + + + + + + + + + + + + + wavegap_8_0 + + gap + + + + + + + + + + + + + + + + + diff --git a/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png b/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png deleted file mode 100644 index 042fb8eaf..000000000 Binary files a/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.png and /dev/null differ diff --git a/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.svg b/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.svg new file mode 100644 index 000000000..0c0a98b3d --- /dev/null +++ b/docs/source/manual/fpga_verilog/figures/verilog_testbench_hierarchy.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-06-29 21:32:37 +0000 + + Canvas 1 + + Layer 1 + + + + + + + + + + + + + <bench_name>_include_netlist.v + + + + + + + <bench_name>_autocheck_top_tb.v + + + + + + + <bench_name>_formal_random_top_tb.v + + + + + + + <bench_name>_top_formal_verification.v + + + + + + + + + + + + + + Full testbench + + + + + Formal-oriented + testbench + + + + + diff --git a/docs/source/manual/fpga_verilog/figures/verilog_testbench_organization.png b/docs/source/manual/fpga_verilog/figures/verilog_testbench_organization.png deleted file mode 100644 index 06f6d58fa..000000000 Binary files a/docs/source/manual/fpga_verilog/figures/verilog_testbench_organization.png and /dev/null differ diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index d42be9c42..6b434e0fb 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -16,24 +16,32 @@ In this part, we will introduce the hierarchy, dependency and functionality of e +-----------------+---------+----------------+---------------+ OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented. -Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a). +Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization`. To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. .. _fig_verilog_testbench_organization: -.. figure:: figures/verilog_testbench_organization.png +.. figure:: figures/full_testbench_block_diagram.svg :scale: 50% - :alt: Functional Verification using ModelSim + :alt: Verilog testbench principles - Principles of Verilog testbenches organization: (a) block diagram and (b) waveforms. + Principles of Verilog testbenches: (1) using common input stimuli; (2) applying bitstream; (3) checking output vectors. + +.. _fig_verilog_full_testbench_waveform: + +.. figure:: figures/full_testbench_waveform.svg + :scale: 50% + :alt: Full testbench waveform + + Illustration on the waveforms in full testbench Full Testbench ~~~~~~~~~~~~~~ Full testbench aims at simulating an entire FPGA operating period, consisting of two phases: - - the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_testbench_organization` (b); + - the **Configuration Phase**, where the synthesized design bitstream is loaded to the programmable fabric, as highlighted by the green rectangle of :numref:`fig_verilog_full_testbench_waveform`; - - the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_testbench_organization` (b). Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA. + - the **Operating Phase**, where random input vectors are auto-generated to drive both Devices Under Test (DUTs), as highlighted by the red rectangle of :numref:`fig_verilog_full_testbench_waveform`. Using the full testbench, users can validate both the configuration circuits and programming fabric of an FPGA. Formal-oriented Testbench ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -50,8 +58,8 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n .. _fig_verilog_testbench_hierarchy: -.. figure:: ./figures/verilog_testbench_hierarchy.png - :scale: 90% +.. figure:: ./figures/verilog_testbench_hierarchy.svg + :scale: 100% Hierarchy of Verilog testbenches for a FPGA fabric implemented with an application @@ -65,37 +73,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n .. note:: Fabric Verilog netlists are included in this file. -.. option:: define_simulation.v - - This file includes pre-processing flags required by the testbenches, to smooth HDL simulation. - It will include the folliwng pre-procesing flags: - - - ```define AUTOCHECK_SIMULATION`` When enabled, testbench will include self-testing features. The FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. - - .. note:: OpenFPGA always enable the self-testing feature. Users can disable it by commenting out the associated line in the ``define_simulation.v``. - - - ```define ENABLE_FORMAL_VERFICATION`` When enabled, the ``_include_netlist.v`` will include the pre-configured FPGA netlist for formal verification usage. This flag is added when ``--print_formal_verification_top_netlist`` option is enabled when calling the ``write_verilog_testbench`` command. - - - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! - - - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - - .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. - - - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command. - - .. warning:: Please disable this flag if you are not using icarus iVerilog simulator. - -__ iverilog_website_ - -.. _iverilog_website: http://iverilog.icarus.com/ - - - .. option:: _autocheck_top_tb.v This is the netlist for full testbench. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst index d2461b5ef..12c4d8ff5 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst @@ -69,6 +69,49 @@ write_fabric_bitstream Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``. See file formats in :ref:`file_formats_fabric_bitstream_xml` and :ref:`file_formats_fabric_bitstream_plain_text`. + .. option:: --fast_configuration + + Reduce the bitstream size when outputing by skipping dummy configuration bits. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + + .. warning:: Fast configuration is only applicable to plain text file format! + + .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. + + .. option:: --verbose Show verbose log + +write_io_mapping +~~~~~~~~~~~~~~~~ + + Output the I/O mapping information to a file + + .. option:: --file or -f + + Specify the file name where the I/O mapping will be outputted to. + See file formats in :ref:`file_format_io_mapping_file`. + + .. option:: --verbose + + Show verbose log + +report_bitstream_distribution +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Output the bitstream distribution to a file + + .. option:: --file or -f + + Specify the file name where the bitstream distribution will be outputted to. + See file formats in :ref:`file_format_bitstream_distribution_file`. + + .. option:: --depth or -d + + Specify the maximum depth of the block which should appear in the block + + .. option:: --verbose + + Show verbose log + + diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 11c64b45f..e927d7b2c 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -6,7 +6,7 @@ FPGA-Verilog write_fabric_verilog ~~~~~~~~~~~~~~~~~~~~ - Write the Verilog netlist for FPGA fabric based on module graph + Write the Verilog netlist for FPGA fabric based on module graph. See details in :ref:`fabric_netlists`. .. option:: --file or -f @@ -24,14 +24,6 @@ write_fabric_verilog Output timing information to Verilog netlists for primitive modules - .. option:: --include_signal_init - - Output signal initialization to Verilog netlists for primitive modules - - .. option:: --support_icarus_simulator - - Output Verilog netlists with syntax that iVerilog simulatorcan accept - .. option:: --print_user_defined_template Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists @@ -40,22 +32,28 @@ write_fabric_verilog Show verbose log -write_verilog_testbench +write_full_testbench ~~~~~~~~~~~~~~~~~~~~~~~ - Write the Verilog testbench for FPGA fabric + Write the full testbench for FPGA fabric in Verilog format. See details in :ref:`fpga_verilog_testbench`. .. option:: --file or -f The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench`` + .. option:: --bitstream + + The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit`` + .. option:: --fabric_netlist_file_path Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v`` .. option:: --reference_benchmark_file_path - Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! .. option:: --pin_constraints_file or -pcf @@ -68,22 +66,139 @@ write_verilog_testbench .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. - .. option:: --print_top_testbench + .. option:: --explicit_port_mapping - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA + Use explicit port mapping when writing the Verilog netlists - .. option:: --print_formal_verification_top_netlist + .. option:: --default_net_type - Generate a top-level module which can be used in formal verification + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. - .. option:: --print_preconfig_top_testbench + .. option:: --include_signal_init - Enable pre-configured top-level testbench which is a fast verification skipping programming phase + Output signal initialization to Verilog testbench to smooth convergence in HDL simulation - .. option:: --print_simulation_ini + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. - Output an exchangeable simulation ini file, which is needed only when you need to interface different HDL simulators using openfpga flow-run scripts. For example, ``--print_simulation_ini /temp/testbench/sim.ini`` + .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + + + .. option:: --verbose + + Show verbose log + +write_preconfigured_fabric_wrapper +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the Verilog wrapper for a preconfigured FPGA fabric. See details in :ref:`fpga_verilog_testbench`. + + .. option:: --file or -f + + The output directory for the netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench`` + + .. option:: --fabric_netlist_file_path + + Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v`` + + .. option:: --pin_constraints_file or -pcf + + Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml`` + Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`. .. option:: --explicit_port_mapping Use explicit port mapping when writing the Verilog netlists + + .. option:: --default_net_type + + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. + + .. option:: --embed_bitstream + + Specify if the bitstream should be embedded to the Verilog netlists in HDL codes. Available options are ``none``, ``iverilog`` and ``modelsim``. Default value: ``modelsim``. + + .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong! + + .. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator. + +__ iverilog_website_ + +.. _iverilog_website: http://iverilog.icarus.com/ + + .. option:: --include_signal_init + + Output signal initialization to Verilog testbench to smooth convergence in HDL simulation + + .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. + + .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable. + + .. option:: --verbose + + Show verbose log + +write_preconfigured_testbench +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write the Verilog testbench for a preconfigured FPGA fabric. See details in :ref:`fpga_verilog_testbench`. + + .. option:: --file or -f + + The output directory for all the testbench netlists. We suggest the use of same output directory as fabric Verilog netlists. For example, ``--file /temp/testbench`` + + .. option:: --fabric_netlist_file_path + + Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v`` + + .. option:: --reference_benchmark_file_path + + Specify the reference benchmark Verilog file if you want to output any self-checking testbench. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. note:: If not specified, the testbench will not include any self-checking feature! + + .. option:: --pin_constraints_file or -pcf + + Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml`` + Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`. + + .. option:: --explicit_port_mapping + + Use explicit port mapping when writing the Verilog netlists + + .. option:: --default_net_type + + Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``. + + .. option:: --verbose + + Show verbose log + +write_simulation_task_info +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + Write an interchangeable file in ``.ini`` format to interface HDL simulators, such as iVerilog and Modelsim. + + .. option:: --file or -f + + Specify the file path to output simulation-related information. For example, ``--file simulation.ini`` + + .. option:: --hdl_dir + + Specify the directory path where HDL netlists are created. For example, ``--hdl_dir ./SRC`` + + .. option:: --reference_benchmark_file_path + + Must specify the reference benchmark Verilog file if you want to output any testbenches. For example, ``--reference_benchmark_file_path /temp/benchmark/counter_post_synthesis.v`` + + .. option:: --testbench_type + + Specify the type of testbenches [``preconfigured_testbench``|``full_testbench``]. By default, it is the ``preconfigured_testbench``. + + .. option:: --time_unit + + Specify a time unit to be used in SDC files. Acceptable values are string: ``as`` | ``fs`` | ``ps`` | ``ns`` | ``us`` | ``ms`` | ``ks`` | ``Ms``. By default, we will consider second (``ms``). + + .. option:: --verbose + + Show verbose log + diff --git a/docs/source/overview/motivation.rst b/docs/source/overview/motivation.rst index 0fc4d58cb..a7315ef52 100644 --- a/docs/source/overview/motivation.rst +++ b/docs/source/overview/motivation.rst @@ -1,13 +1,13 @@ Why OpenFPGA? ------------- -.. note:: If this is the first time you learn OpenFPGA, we strongly recommend you to watch the `introduction video `_ +.. note:: If this is your first time learning OpenFPGA, we strongly recommend you to watch the `introduction video `_ .. only:: html .. youtube:: ocODUGcYGqo -OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and assoicated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support. +OpenFPGA aims to be an open-source framework that enables rapid prototyping of customizable FPGA architectures. As shown in :numref:`fig_openfpga_motivation`, a conventional approach will take a large group of experienced engineers more than one year to achieve production-ready layout and associated CAD tools. In fact, most of the engineering efforts are spent on manual layouts and developing ad-hoc CAD support. .. _fig_openfpga_motivation: @@ -15,15 +15,15 @@ OpenFPGA aims to be an open-source framework that enables rapid prototyping of c :scale: 50% :alt: OpenFPGA: a fast prototyping framework for customizable FPGAs - Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are permitted to publish under proper licenses] + Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are publishable under the proper licenses] Using OpenFPGA, the development cycle in both hardware and software can be significantly accelerated. OpenFPGA can automatically generate Verilog netlists describing a full FPGA fabric based on an XML-based description file. Thanks to modern semi-custom design tools, production-ready layout generation can be achieved within 24 hours. To help sign-off, OpenFPGA can auto-generate Verilog testbenches to validate the correctness of FPGA fabric using modern verification tools. -OpenFPGA also provides native bitstream generation support based the same XML-based description file used in Verilog generation. This avoid the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use. +OpenFPGA also provides native bitstream generation support based on the same XML-based description file used in Verilog generation, avoiding the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use. -OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customized primitive circuit designed downto transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers. +OpenFPGA can support any architecture that VPR can describe, covering most of the architecture enhancements available in modern FPGAs, and hence unlocks a large design space in prototyping customizable FPGAs. In addition, OpenFPGA provides enriched syntax which allows users to customize primitive circuits designed down to transistor-level parameters. This helps developers to customize the P.P.A. (Power, Performance and Area) to the best. All these features open the door of prototyping/studying flexible FPGAs to a small group of junior engineers or researchers. In terms of tool functionality, OpenFPGA consists of the following parts: FPGA-Verilog, FPGA-SDC, FPGA-Bitstream and FPGA-SPICE. -The rest of this section will focus on detailed motivation on each of them, as depicted in :numref:`fig_openfpga_framework`. +The rest of this section will focus on detailed motivation for each of them, as depicted in :numref:`fig_openfpga_framework`. .. _fig_openfpga_framework: @@ -39,7 +39,7 @@ Fully Customizable Architecture OpenFPGA supports VPR's architecture description language, which allows users to define versatile programmable fabrics down to point-to-point interconnection. -OpenFPGA leverage VPR's architecture description by introducing an XML-based +OpenFPGA leverages VPR's architecture description by introducing an XML-based architecture annotation, enabling fully customizable FPGA fabric down to circuit elements. As illustrated in :ref:`fig_openfpga_arch_lang_coverage`, OpenFPGA's @@ -60,7 +60,9 @@ FPGA-Verilog ~~~~~~~~~~~~ Driven by the strong need in data processing applications, Field Programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern -computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. OpenFPGA, an opensource framework, aims to rapid prototype of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. +computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. + +OpenFPGA, an opensource framework, aims to rapidly prototype customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabling various backend choices, as illustrated in :ref:`fig_fpga_verilog_motivation`. .. _fig_fpga_verilog_motivation: @@ -80,7 +82,7 @@ Design constraints are indepensible in modern ASIC design flows to guarantee the OpenFPGA includes a rich SDC generator in the OpenFPGA framework to deal with both PnR constraints and sign-off timing analysis. Our flow automatically generates two sets of SDC files. -- The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable wellcontrolled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. OpenFPGA allows users to define timing constraints in the architecture description and outputs timing constraints in standard format, enabling fully timing constrained backend flow (see :ref:`fig_fpga_sdc_motivation`). +- The first set of SDC is designed for the P&R flow, where all the combinational loops are broken to enable well controlled timing-driven P&R. In addition, there are SDC files devoted to constrain pin-to-pin timing for all the resources in FPGAs, in order to obtain nicely constrained and homogeneous delays across the fabric. OpenFPGA allows users to define timing constraints in the architecture description and outputs timing constraints in standard format, enabling fully timing constrained backend flow (see :ref:`fig_fpga_sdc_motivation`). - The second set of SDC is designed for the timing analysis of a benchmark at the post P&R stage. .. _fig_fpga_sdc_motivation: @@ -98,20 +100,18 @@ The technical details can be found in our FPL'19 paper :cite:`XTang_FPL_2019`. FPGA-Bitstream ~~~~~~~~~~~~~~ -EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generator for customized FPGAs. - -Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow. This is the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics. +EDA support is essential for end-users to implement designs on a customized FPGA. OpenFPGA provides a general-purpose bitstream generator FPGA-Bitstream for any architecture that can be described by VPR. As the native CAD tool for any customized FPGA that is produced by FPGA-Verilog, FPGA-Bitstream is ready to use once users finalize the XML-based architecture description file. This eliminates the huge engineering efforts spent on developing bitstream generators for customized FPGAs. Using FPGA-Bitstream, users can launch (1) Verilog-to-Bitstream flow, the typical implementation flow for end-users; (2) Verilog-to-Verification flow. OpenFPGA can output Verilog testbenches with self-testing features to validate users' implemetations on their customized FPGA fabrics. The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019` and FPL'19 paper :cite:`XTang_FPL_2019`. FPGA-SPICE ~~~~~~~~~~ -The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages of generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs. +The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999,JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model requires updates to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages of generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs. It motivates us to develop FPGA-SPICE, an add-on for the current State-of-Art FPGA architecture exploration tools, VPR :cite:`JRose_FPGA_2012`. -FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA architectures supported by VPR. The SPICE netlists and testbenches are generated according to the placement and routing results of VPR. As a result, SPICE simulator can be used to perform precise delay and power analysis. The SPICE simulation results are useful in three aspects: (1) it can provide accurate power analysis; (2) it helps to improve the accuracy of built-in analytical models; and moreover (3) it creates opportunities in developing novel analytical models. +FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA architectures supported by VPR. The SPICE netlists and testbenches are generated according to the placement and routing results of VPR. As a result, SPICE simulator can be used to perform precise delay and power analysis. The SPICE simulation results are useful in three aspects: (1) they provide accurate power analysis; (2) they help to improve the accuracy of built-in analytical models; and moreover (3) they create opportunities in developing novel analytical models. -SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we develop an extension on the VPR architectural description language to model the transistor-level circuit designs. +SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we are developing an extension on the VPR architectural description language to model the transistor-level circuit designs. The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`. diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index 95521cc29..ee55f7c19 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -1,7 +1,7 @@ Technical Highlights -------------------- -The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of February 2021**) +The following lists of technical features were created to help users find their needs for customizing FPGA fabrics.(**as of February 2021**) Supported Circuit Designs ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -42,19 +42,21 @@ Supported Circuit Designs +-----------------+--------------+-----------+-----------------------------------------------------+ | | Configurable | No | Yes | - :ref:`circuit_model_config_latch_example` | | | Memory | | | - :ref:`circuit_model_sram_blwl_example` | -| | | | - :ref:`circuit_model_dff_example` | | | | | - :ref:`circuit_model_ccff_example` | | | | | - :ref:`circuit_model_ccff_enable_example` | | | | | - :ref:`circuit_model_ccff_scanable_example` | +-----------------+--------------+-----------+-----------------------------------------------------+ -| Block RAM | No | Yes | - **Any size** | -| | | | - Single-port | -| | | | - Dual-port | -| | | | - Fracturable | +| Data Memory | No | Yes | - **Any size** | +| | | | - :ref:`circuit_model_dff_example` | +| | | | - :ref:`circuit_model_multi_mode_ff_example` | +| | | | - Single-port Block RAM | +| | | | - :ref:`circuit_model_single_mode_dpram_example` | +| | | | - :ref:`circuit_model_multi_mode_dpram_example` | +-----------------+--------------+-----------+-----------------------------------------------------+ | | Arithmetic | No | Yes | - **Any size** | -| | Units | | | - Multiplier | -| | | | - :ref:`circuit_model_full_adder_example` | +| | Units | | | - :ref:`circuit_model_full_adder_example` | +| | | | - :ref:`circuit_model_single_mode_mult8x8_example` | +| | | | - :ref:`circuit_model_multi_mode_mult8x8_example` | +-----------------+--------------+-----------+-----------------------------------------------------+ | I/O | No | Yes | - :ref:`circuit_model_gpio_example` | | | | | - Bi-directional buffer | @@ -62,13 +64,13 @@ Supported Circuit Designs +-----------------+--------------+-----------+-----------------------------------------------------+ -* The user defined netlist could come from a standard cell +* The user defined netlist could come from a standard cell. See :ref:`tutorial_standard_cell` for details. Supported FPGA Architectures ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ We support most FPGA architectures that VPR can support! -The following are most commonly seen architectural features: +The following are the most commonly seen architectural features: +------------------------+----------------------------------------------+ | Block Type | Architecture features | diff --git a/docs/source/tutorials/arch_modeling/figures/ADDF_Example_Spypad.svg b/docs/source/tutorials/arch_modeling/figures/ADDF_Example_Spypad.svg new file mode 100644 index 000000000..4d5affee6 --- /dev/null +++ b/docs/source/tutorials/arch_modeling/figures/ADDF_Example_Spypad.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/docs/source/tutorials/arch_modeling/figures/Control_Waveforms.pdf b/docs/source/tutorials/arch_modeling/figures/Control_Waveforms.pdf new file mode 100644 index 000000000..02dbe1e62 Binary files /dev/null and b/docs/source/tutorials/arch_modeling/figures/Control_Waveforms.pdf differ diff --git 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b/docs/source/tutorials/arch_modeling/figures/spypad_waveforms.png new file mode 100644 index 000000000..948473e2c Binary files /dev/null and b/docs/source/tutorials/arch_modeling/figures/spypad_waveforms.png differ diff --git a/docs/source/tutorials/arch_modeling/index.rst b/docs/source/tutorials/arch_modeling/index.rst index 1b643641d..3649516bb 100644 --- a/docs/source/tutorials/arch_modeling/index.rst +++ b/docs/source/tutorials/arch_modeling/index.rst @@ -8,3 +8,6 @@ Architecture Modeling :maxdepth: 2 quick_start + user_defined_temp_tutorial + open_cell_libraries_tutorial + spypads_tutorial diff --git a/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst b/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst new file mode 100644 index 000000000..10dfd96b0 --- /dev/null +++ b/docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst @@ -0,0 +1,487 @@ +.. _tutorial_standard_cell: + +Build an FPGA fabric using Standard Cell Libraries +================================================== + +Introduction +~~~~~~~~~~~~ + +**In this tutorial, we will** + - Showcase how to create an architecture description based on standard cells, using OpenFPGA's circuit modeling language + - Use Skywater's Process Design Kit (`PDK`_) cell library to create an OR Gate circuit model for OpenFPGA + - Verify that the standard cell library file was correctly bound into the selected architecture file by looking at auto-generated OpenFPGA files and checking simulation waveforms in GTKWave +Through this example, we will show how to bind standard cell library files with OpenFPGA Architectures. + +.. note:: We showcase the methodology by considering the open-source Skywater 130nm PDK so that users can easily reproduce the results. + +Create and Verify the OpenFPGA Circuit Model +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. note:: In this tutorial, we focus on binding a 2-input **OR** gate from a standard cell library to a circuit model in OpenFPGA's architecture description file. Note that the approach can be generalized to any circuit model. + +For this tutorial, we start with an example where the HDL netlist of an 2-input **OR** gate that is auto-generated by OpenFPGA. After updating the architecture file, the auto-generated HDL netlist created by OpenFPGA will directly instantiate a standard cell from the open-source Skywater 130nm PDK library. +To follow along, go to the root directory of OpenFPGA and enter: + +.. code-block:: bash + + python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + +This will run a prebuilt task with OpenFPGA cell libraries. When the task is finished, there will be many auto-generated files to look through. For this tutorial, we are interested in the ``luts.v`` and ``and2_formal.vcd`` files. The **OR2** gate is used as a control circuit in the **lut6** circuit model, and the ``and2_formal.vcd`` file will have the resulting waveforms from the simulation run by the task. To open the ``luts.v`` file, run the following command: + +.. code-block:: bash + + vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v + +.. note:: Users can find full details about netlist organization in our documentation: :ref:`fabric_netlists` + +The ``luts.v`` file represents a Look Up Table within the OpenFPGA architecture. The important lines of this file for the tutorial are highlighted below. +These lines show the instantiation of OpenFPGA's **OR2** cell library. + +.. code-block:: verilog + :emphasize-lines: 58,59,72,73,74,75,76,77,78,79,80 + + + //------------------------------------------- + // FPGA Synthesizable Verilog Netlist + // Description: Look-Up Tables + // Author: Xifan TANG + // Organization: University of Utah + // Date: Tue Mar 30 15:25:03 2021 + //------------------------------------------- + //----- Time scale ----- + `timescale 1ns / 1ps + + //----- Default net type ----- + `default_nettype none + + // ----- Verilog module for frac_lut6 ----- + module frac_lut6(in, + sram, + sram_inv, + mode, + mode_inv, + lut4_out, + lut5_out, + lut6_out); + //----- INPUT PORTS ----- + input [0:5] in; + //----- INPUT PORTS ----- + input [0:63] sram; + //----- INPUT PORTS ----- + input [0:63] sram_inv; + //----- INPUT PORTS ----- + input [0:1] mode; + //----- INPUT PORTS ----- + input [0:1] mode_inv; + //----- OUTPUT PORTS ----- + output [0:3] lut4_out; + //----- OUTPUT PORTS ----- + output [0:1] lut5_out; + //----- OUTPUT PORTS ----- + output [0:0] lut6_out; + + //----- BEGIN wire-connection ports ----- + wire [0:5] in; + wire [0:3] lut4_out; + wire [0:1] lut5_out; + wire [0:0] lut6_out; + //----- END wire-connection ports ----- + + + //----- BEGIN Registered ports ----- + //----- END Registered ports ----- + + + wire [0:0] INVTX1_0_out; + wire [0:0] INVTX1_1_out; + wire [0:0] INVTX1_2_out; + wire [0:0] INVTX1_3_out; + wire [0:0] INVTX1_4_out; + wire [0:0] INVTX1_5_out; + wire [0:0] OR2_0_out; + wire [0:0] OR2_1_out; + wire [0:0] buf4_0_out; + wire [0:0] buf4_1_out; + wire [0:0] buf4_2_out; + wire [0:0] buf4_3_out; + wire [0:0] buf4_4_out; + wire [0:0] buf4_5_out; + + // ----- BEGIN Local short connections ----- + // ----- END Local short connections ----- + // ----- BEGIN Local output short connections ----- + // ----- END Local output short connections ----- + + OR2 OR2_0_ ( + .a(mode[0:0]), + .b(in[4]), + .out(OR2_0_out)); + + OR2 OR2_1_ ( + .a(mode[1]), + .b(in[5]), + .out(OR2_1_out)); + + INVTX1 INVTX1_0_ ( + .in(in[0:0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(OR2_0_out), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(OR2_1_out), + .out(INVTX1_5_out)); + + buf4 buf4_0_ ( + .in(in[0:0]), + .out(buf4_0_out)); + + buf4 buf4_1_ ( + .in(in[1]), + .out(buf4_1_out)); + + buf4 buf4_2_ ( + .in(in[2]), + .out(buf4_2_out)); + + buf4 buf4_3_ ( + .in(in[3]), + .out(buf4_3_out)); + + buf4 buf4_4_ ( + .in(OR2_0_out), + .out(buf4_4_out)); + + buf4 buf4_5_ ( + .in(OR2_1_out), + .out(buf4_5_out)); + + frac_lut6_mux frac_lut6_mux_0_ ( + .in(sram[0:63]), + .sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out, buf4_4_out, buf4_5_out}), + .sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}), + .lut4_out(lut4_out[0:3]), + .lut5_out(lut5_out[0:1]), + .lut6_out(lut6_out)); + + endmodule + // ----- END Verilog module for frac_lut6 ----- + + //----- Default net type ----- + `default_nettype none + + +We will also need to look at the control's simulation waveforms. Viewing the waveforms is done through `GTKWave`_ with the following command: + +.. code-block:: bash + + gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + +The simulation waveforms should look similar to the following :numref:`fig_control_output`: + +.. _fig_control_output: + +.. figure:: ./figures/Control_Waves2.png + :scale: 75% + + Simulation Waveforms with OpenFPGA Circuit Model + + +.. note:: The waveform inputs do not need to exactly match because the testbench provides input in random intervals. + +We have now finished creating the control and viewing the important sections for this tutorial. We can now incorporate Skywater's cell library to create a new circuit model. + +Clone Skywater PDK into OpenFPGA +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +We will be using the open-source Skywater PDK to create our circuit model. We start by cloning the Skywater PDK github repository into the OpenFPGA root directory. +Run the following command in the root directory of OpenFPGA: + +.. code-block:: bash + + git clone https://github.com/google/skywater-pdk.git + +Once the repository has been cloned, we need to build the cell libraries by running the following command in the Skywater PDK root directory: + +.. code-block:: bash + + SUBMODULE_VERSION=latest make submodules -j3 || make submodules -j1 + +This will take some time to complete due to the size of the libraries. Once the libraries are made, creating the circuit model can begin. + +Create and Verify the Standard Cell Library Circuit Model +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To create the circuit model, we will modify the ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` OpenFPGA architecture file by removing the circuit model +for OpenFPGA's **OR2** gate, replacing the circuit model with one referencing the Skywater cell library, and modifying the LUT that references the old **OR2** +circuit model to reference our new circuit model. We begin by running the following command in the root directory: + +.. code-block:: bash + + vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +We continue the circuit model creation process by replacing **LINE67** to **LINE81** with the following: + +.. code-block:: xml + + + + + + + + + + +.. note:: The name of the circuit model must be consistent with the standard cell! + +The most significant differences from the OpenFPGA Circuit Model in this section are: + - Change the ``name`` and ``prefix`` to match the module name from Skywater's cell library + - Include a path to the verilog file using ``verilog_netlist``. + +The second change to ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` is at **LINE160**, where we will be replacing the line with the following: + +.. code-block:: xml + + + +This change replaces the input of the LUT with our new circuit model. Everything is in place to begin verification. + +Verification begins by running the following command: + +.. code-block:: bash + + python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + +The task may output this error: + +.. code-block:: bash + + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - iverilog_verification run failed with returncode 1 + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>error: Unable to find the root module "and2_top_formal_verification_random_tb" in the Verilog source. + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - -->>1 error(s) during elaboration. + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Current working directory : OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run057/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to run iverilog_verification task + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Exiting . . . . . . + ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH + + +This error has occurred because IVerilog could not find the path to the Skywater PDK Cell Library we have selected. To fix this, we need to go to the +``iverilog_output.txt`` file found here: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/iverilog_output.txt + +Replace all the text within ``iverilog_output.txt`` with the following: + +.. code-block:: bash + + iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb -I ${OPENFPGA_PATH}/skywater-pdk/libraries/sky130_fd_sc_ls/latest/cells/or2 + +We can now manually rerun IVerilog, a tutorial on manually running IVerilog can be found at our :ref:`from_verilog_to_verification` tutorial. From the root +directory, run the following commands: + +.. code-block:: bash + + cd openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/ + + source iverilog_output.txt + + vvp compiled_and2 + +With IVerilog complete, we can verify that the cell library has been bound correctly by viewing the ``luts.v`` file and the waveforms with GTKWave. + +From the root directory, view the ``luts.v`` file with this command: + +.. code-block:: bash + + vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v + +Scrolling through ``luts.v``, this should be present in the file: + +.. code-block:: verilog + :emphasize-lines: 64,65,72,73,74,75,76,77,78,79,80 + + //------------------------------------------- + // FPGA Synthesizable Verilog Netlist + // Description: Look-Up Tables + // Author: Xifan TANG + // Organization: University of Utah + // Date: Tue Mar 30 20:25:06 2021 + //------------------------------------------- + //----- Time scale ----- + `timescale 1ns / 1ps + + //----- Default net type ----- + `default_nettype none + + // ----- Verilog module for frac_lut6 ----- + module frac_lut6(in, + sram, + sram_inv, + mode, + mode_inv, + lut4_out, + lut5_out, + lut6_out); + //----- INPUT PORTS ----- + input [0:5] in; + //----- INPUT PORTS ----- + input [0:63] sram; + //----- INPUT PORTS ----- + input [0:63] sram_inv; + //----- INPUT PORTS ----- + input [0:1] mode; + //----- INPUT PORTS ----- + input [0:1] mode_inv; + //----- OUTPUT PORTS ----- + output [0:3] lut4_out; + //----- OUTPUT PORTS ----- + output [0:1] lut5_out; + //----- OUTPUT PORTS ----- + output [0:0] lut6_out; + + //----- BEGIN wire-connection ports ----- + wire [0:5] in; + wire [0:3] lut4_out; + wire [0:1] lut5_out; + wire [0:0] lut6_out; + //----- END wire-connection ports ----- + + + //----- BEGIN Registered ports ----- + //----- END Registered ports ----- + + + wire [0:0] INVTX1_0_out; + wire [0:0] INVTX1_1_out; + wire [0:0] INVTX1_2_out; + wire [0:0] INVTX1_3_out; + wire [0:0] INVTX1_4_out; + wire [0:0] INVTX1_5_out; + wire [0:0] buf4_0_out; + wire [0:0] buf4_1_out; + wire [0:0] buf4_2_out; + wire [0:0] buf4_3_out; + wire [0:0] buf4_4_out; + wire [0:0] buf4_5_out; + wire [0:0] sky130_fd_sc_ls__or2_1_0_X; + wire [0:0] sky130_fd_sc_ls__or2_1_1_X; + + // ----- BEGIN Local short connections ----- + // ----- END Local short connections ----- + // ----- BEGIN Local output short connections ----- + // ----- END Local output short connections ----- + + sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_0_ ( + .A(mode[0:0]), + .B(in[4]), + .X(sky130_fd_sc_ls__or2_1_0_X)); + + sky130_fd_sc_ls__or2_1 sky130_fd_sc_ls__or2_1_1_ ( + .A(mode[1]), + .B(in[5]), + .X(sky130_fd_sc_ls__or2_1_1_X)); + + INVTX1 INVTX1_0_ ( + .in(in[0:0]), + .out(INVTX1_0_out)); + + INVTX1 INVTX1_1_ ( + .in(in[1]), + .out(INVTX1_1_out)); + + INVTX1 INVTX1_2_ ( + .in(in[2]), + .out(INVTX1_2_out)); + + INVTX1 INVTX1_3_ ( + .in(in[3]), + .out(INVTX1_3_out)); + + INVTX1 INVTX1_4_ ( + .in(sky130_fd_sc_ls__or2_1_0_X), + .out(INVTX1_4_out)); + + INVTX1 INVTX1_5_ ( + .in(sky130_fd_sc_ls__or2_1_1_X), + .out(INVTX1_5_out)); + + buf4 buf4_0_ ( + .in(in[0:0]), + .out(buf4_0_out)); + + buf4 buf4_1_ ( + .in(in[1]), + .out(buf4_1_out)); + + buf4 buf4_2_ ( + .in(in[2]), + .out(buf4_2_out)); + + buf4 buf4_3_ ( + .in(in[3]), + .out(buf4_3_out)); + + buf4 buf4_4_ ( + .in(sky130_fd_sc_ls__or2_1_0_X), + .out(buf4_4_out)); + + buf4 buf4_5_ ( + .in(sky130_fd_sc_ls__or2_1_1_X), + .out(buf4_5_out)); + + frac_lut6_mux frac_lut6_mux_0_ ( + .in(sram[0:63]), + .sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out, buf4_4_out, buf4_5_out}), + .sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out, INVTX1_4_out, INVTX1_5_out}), + .lut4_out(lut4_out[0:3]), + .lut5_out(lut5_out[0:1]), + .lut6_out(lut6_out)); + + endmodule + // ----- END Verilog module for frac_lut6 ----- + + //----- Default net type ----- + `default_nettype none + + +We can check the waveforms as well to see if they are similar with the command: + +.. code-block:: bash + + gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + +The simulation waveforms should look similar to the following :numref:`fig_custom_output`: + +.. _fig_custom_output: + +.. figure:: ./figures/Custom_Waves2.png + :scale: 75% + + Simulation Waveforms with Skywater PDK Circuit Model + +We have now verified that the Skywater PDK Cell Library has been instantiated and bound to the OpenFPGA architecture file. If you have any problems, please :ref:`contact` us. + + + +.. _PDK: https://github.com/google/skywater-pdk + +.. _GTKWave: https://github.com/gtkwave/gtkwave + + diff --git a/docs/source/tutorials/arch_modeling/spypads_tutorial.rst b/docs/source/tutorials/arch_modeling/spypads_tutorial.rst new file mode 100644 index 000000000..5ffd5ddae --- /dev/null +++ b/docs/source/tutorials/arch_modeling/spypads_tutorial.rst @@ -0,0 +1,332 @@ +Creating Spypads Using XML Syntax +================================= + +Introduction +~~~~~~~~~~~~ + +**In this tutorial, we will** + - Show the XML syntax for global outputs + - Showcase an example with spypads + - Modify an existing architecture to incorporate spypads + - Verify correctness through GTKWave + +Through this tutorial, we will show how to create spypads in OpenFPGA. + +Spypads are physical output pins on a FPGA chip through which you can read out internal signals when doing silicon-level debugging. The XML syntax for spypads and other +global signals can be found on our :ref:`circuit_library` documentation page. + +To create a spypad, the ``port type`` needs to be set to **output** and ``is_global`` and ``is_io`` need to be set to **true**: + +.. code-block:: xml + + + +When the port is syntactically correct, the outputs are independently wired from different instances to separated FPGA outputs and would physically look like :ref:`fig_gpout_ports` + + + +Pre-Built Spypads +~~~~~~~~~~~~~~~~~ + +An OpenFPGA architecture file that contains spypads and has a task that references it is the `k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml `_ +file. We can view ``k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml`` by entering the following command at the root directory of OpenFPGA: + +.. code-block:: bash + + emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml + +In this architecture file, the output ports of a 6-input Look-Up Table (LUT) are defined as spypads using the XML syntax ``is_global`` and ``is_io``. As a result, all of the outputs from the 6-input LUT will be visible in the top-level module. The output ports to the 6-input LUT are declared from **LINE181** to **LINE183** and belong to the ``frac_lut6_spypad`` ``circuit_model`` that begins at **LINE172**. + +.. code-block:: xml + + + + + + + + + + + LINE181 + LINE182 + LINE183 + + + + +The spypads are instantiated in the top-level verilog module ``fpga_top.v``. ``fpga_top.v`` is automatically generated when we run our task from the OpenFPGA root +directory. However, we need to modify the task configuration file to run the **full testbench** instead of the **formal testbench** to view the spypads' waveforms in +GTKWave. + +.. note:: To read about the differences between the **formal testbench** and the **full testbench**, please visit our page on testbenches: :ref:`testbench`. + +To open the task configuration file, run this command from the root directory of OpenFPGA: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf + +The last line of the task configuration file (**LINE44**) sets the **formal testbench** to be the desired testbench. To use the **full testbench**, comment out **LINE44**. +The file will look like this when finished: + +.. code-block:: python + :linenos: + + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Configuration file for running experiments + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs + # Each job execute fpga_flow script on combination of architecture & benchmark + # timeout_each_job is timeout for each job + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + + [GENERAL] + run_engine=openfpga_shell + power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml + power_analysis = true + spice_output=false + verilog_output=true + timeout_each_job = 20*60 + fpga_flow=vpr_blif + + [OpenFPGA_SHELL] + openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga + openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml + openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + + [ARCHITECTURES] + arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml + + [BENCHMARKS] + bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + # Cannot pass automatically. Need change in .v file to match ports + # When passed, we can replace the and2 benchmark + #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif + + [SYNTHESIS_PARAM] + bench0_top = and2 + bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act + bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + + #bench0_top = test_mode_low + #bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act + #bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v + bench0_chan_width = 300 + + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] + end_flow_with_test= + #vpr_fpga_verilog_formal_verification_top_netlist= + +Our OpenFPGA task will now run the full testbench. We run the task with the following command from the root directory of OpenFPGA: + +.. code-block:: bash + + python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs + +.. note:: Python 3.8 or later is required to run this task + +We can now see the instantiation of these spypads in ``fpga_top.v`` and ``luts.v``. We will start by viewing ``luts.v`` with the following command: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.verilog + +The spypads are coming from the ``frac_lut6_spypad`` circuit model. In ``luts.v``, the ``frac_lut6_spypad`` module is defined around **LINE150** and looks as follows: + +.. code-block:: verilog + + module frac_lut6_spypad(in, + sram, + sram_inv, + mode, + mode_inv, + lut4_out, + lut5_out, + lut6_out); + //----- INPUT PORTS ----- + input [0:5] in; + //----- INPUT PORTS ----- + input [0:63] sram; + //----- INPUT PORTS ----- + input [0:63] sram_inv; + //----- INPUT PORTS ----- + input [0:1] mode; + //----- INPUT PORTS ----- + input [0:1] mode_inv; + //----- OUTPUT PORTS ----- + output [0:3] lut4_out; + //----- OUTPUT PORTS ----- + output [0:1] lut5_out; + //----- OUTPUT PORTS ----- + output [0:0] lut6_out; + +The ``fpga_top.v`` file has some similarities. We can view the ``fpga_top.v`` file by running the following command: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v + +If we look at the module definition and ports of ``fpga_top.v`` we should see the following: + +.. code-block:: verilog + + module fpga_top(pReset, + prog_clk, + TESTEN, + set, + reset, + clk, + gfpga_pad_frac_lut6_spypad_lut4_out, + gfpga_pad_frac_lut6_spypad_lut5_out, + gfpga_pad_frac_lut6_spypad_lut6_out, + gfpga_pad_GPIO_PAD, + ccff_head, + ccff_tail); + //----- GLOBAL PORTS ----- + input [0:0] pReset; + //----- GLOBAL PORTS ----- + input [0:0] prog_clk; + //----- GLOBAL PORTS ----- + input [0:0] TESTEN; + //----- GLOBAL PORTS ----- + input [0:0] set; + //----- GLOBAL PORTS ----- + input [0:0] reset; + //----- GLOBAL PORTS ----- + input [0:0] clk; + //----- GPOUT PORTS ----- + output [0:3] gfpga_pad_frac_lut6_spypad_lut4_out; + //----- GPOUT PORTS ----- + output [0:1] gfpga_pad_frac_lut6_spypad_lut5_out; + //----- GPOUT PORTS ----- + output [0:0] gfpga_pad_frac_lut6_spypad_lut6_out; + //----- GPIO PORTS ----- + inout [0:7] gfpga_pad_GPIO_PAD; + //----- INPUT PORTS ----- + input [0:0] ccff_head; + //----- OUTPUT PORTS ----- + output [0:0] ccff_tail; + +Using :ref:`fig_gpout_ports` as a guide, we can relate our task like :numref:`fig_gpout_example` + +.. _fig_gpout_example: + +.. figure:: ./figures/lut6_Example_Spypad.svg + :scale: 100% + + An illustrative example of the ``lut6`` spypad sourced from inside a logic element. + + +We can view testbench waveforms with GTKWave by running the following command from the root directory: + +.. code-block:: bash + + gtkwave openfpga_flow/tasks/fpga_verilog/spypad/latest/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + +.. note:: Information on GTKWave can be found on our documentation page located here: :ref:`from_verilog_to_verification` + +The waveforms will appear similar to :numref:`fig_spypad_waves` + +.. _fig_spypad_waves: + +.. figure:: ./figures/spypad_waveforms.png + :width: 100% + + Waveforms of ``frac_lut6`` spypads + +Building Spypads +~~~~~~~~~~~~~~~~ + +We will modify the `k6_frac_N10_adder_chain_40nm_openfpga.xml `_ file found in OpenFPGA to expose the **sumout** output from the **ADDF** module. We can start modifying +the file by running the following command: + +.. code-block:: bash + + emacs openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +Replace **LINE214** with the following: + +.. code-block:: xml + + + +**sumout** is now a global output. **sumout** will show up in the ``fpga_top.v`` file and will have waveforms in GTKWave if we run the **full testbench**. To run the +**full testbench**, we have to modify the ``hard_adder`` configuration file: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/config/task.conf + +Comment out the last line of the file to run the **full testbench**: + +.. code-block:: python + + #vpr_fpga_verilog_formal_verification_top_netlist= + +We now run the task to see our changes: + +.. code-block:: bash + + python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + +We can view the global ports in ``fpga_top.v`` by running the following command: + +.. code-block:: bash + + emacs openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run064/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fpga_top.v + +The ``fpga_top.v`` should have the following in its module definition: + +.. code-block:: verilog + + module fpga_top(pReset, + prog_clk, + set, + reset, + clk, + gfpga_pad_ADDF_sumout, + gfpga_pad_GPIO_PAD, + ccff_head, + ccff_tail); + //----- GLOBAL PORTS ----- + input [0:0] pReset; + //----- GLOBAL PORTS ----- + input [0:0] prog_clk; + //----- GLOBAL PORTS ----- + input [0:0] set; + //----- GLOBAL PORTS ----- + input [0:0] reset; + //----- GLOBAL PORTS ----- + input [0:0] clk; + //----- GPOUT PORTS ----- + output [0:19] gfpga_pad_ADDF_sumout; + +The architecture will now look like :numref:`fig_addf_example` + +.. _fig_addf_example: + +.. figure:: ./figures/ADDF_Example_Spypad.svg + :scale: 100% + + An illustrative example of the sumout spypad sourced from an adder inside a logic element. There are 10 logic elements in a CLB, and we are looking at the 1st logic element. + +We can view the waveform by running GTKWave: + +.. code-block:: bash + + gtkwave openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/and2_formal.vcd & + +The waveform should have some changes to its value. An example of what it may look like is displayed in :numref:`fig_spy_adder` + +.. _fig_spy_adder: + +.. figure:: ./figures/spyadder_waveform.png + :width: 100% + + Waveforms of ``sumout`` spypad + +Conclusion +~~~~~~~~~~ + +In this tutorial, we have shown how to build spypads into OpenFPGA Architectures using XML Syntax. If you have any issues, feel free to :ref:`contact` us. diff --git a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst new file mode 100644 index 000000000..f2ba6e4bf --- /dev/null +++ b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst @@ -0,0 +1,176 @@ +.. _tutorial_user_def_temp: + +Integrating Custom Verilog Modules with user_defined_template.v +================================================================ + +.. only:: html + + .. youtube:: YTggSZHsTjg + +Introduction and Setup +~~~~~~~~~~~~~~~~~~~~~~ +**In this tutorial, we will** + - Provide the motivation for generating the user_defined_template.v verilog file + - Go through a generated user_defined_template.v file to demonstrate how to use it +Through this tutorial, we will show how and when to use the :ref:`user_defined_template.v ` file. + +To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA. +To follow along, go to the root directory of OpenFPGA and enter: + +.. code-block:: bash + + vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +Go to **LINE187** and replace **LINE187** with: + +.. code-block:: XML + + + +Motivation +~~~~~~~~~~ +From the OpenFPGA root directory, run the command: + +.. code-block:: bash + + python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + +Running this command should fail and produce the following errors: + +.. code-block:: bash + + ERROR - iverilog_verification run failed with returncode 21 + ERROR - command iverilog -o compiled_and2 ./SRC/and2_include_netlists.v -s and2_top_formal_verification_random_tb + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>././SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v:50: error: Unknown module type: ADDF + ERROR - -->>21 error(s) during elaboration. + ERROR - Current working directory : /research/ece/lnis/USERS/leaptrot/OpenFPGA/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/run019/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH + ERROR - Failed to run iverilog_verification task + ERROR - Exiting . . . . . . +This error log can also be found by running the following command from the root directory: + +.. code-block:: bash + + cat openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/00_and2_MIN_ROUTE_CHAN_WIDTH_out.log + +This command failed during the verification step because the path to the module definition for **ADDF** is missing. In our architecture file, user-defined verilog modules are those ```` with the key term `verilog_netlist`. The ``user_defined_template.v`` file provides a module template for incorporating Hard IPs without external library into the architecture. + +Fixing the Error +~~~~~~~~~~~~~~~~ +This error can be resolved by replacing the **LINE187** of ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` with the following: + +.. code-block:: XML + + + +The above line provides a path to generate the :ref:`user_defined_template.v ` file. +Now we can return to the root directory and run this command again: + +.. code-block:: bash + + python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + +The task should now complete without any errors. + +Fixing the Error with user_defined_template.v +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The :ref:`user_defined_template.v ` file can be found starting from the root directory and entering: + +.. code-block:: bash + + vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v + +.. note:: The ``user_defined_template.v`` file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. ``user_defined_template.v`` is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. ``user_defined_template.v`` can be included in simulation only if there are modifications to the ``user_defined_template.v``. + +To implement our own **ADDF** module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_template.v`` file with the following: + +.. code-block:: Verilog + + //------------------------------------------- + // FPGA Synthesizable Verilog Netlist + // Description: Template for user-defined Verilog modules + // Author: Xifan TANG + // Organization: University of Utah + // Date: Fri Mar 19 10:05:32 2021 + //------------------------------------------- + //----- Time scale ----- + `timescale 1ns / 1ps + + + + // ----- Template Verilog module for ADDF ----- + //----- Default net type ----- + `default_nettype none + + // ----- Verilog module for ADDF ----- + module ADDF(A, + B, + CI, + SUM, + CO); + //----- INPUT PORTS ----- + input [0:0] A; + //----- INPUT PORTS ----- + input [0:0] B; + //----- INPUT PORTS ----- + input [0:0] CI; + //----- OUTPUT PORTS ----- + output [0:0] SUM; + //----- OUTPUT PORTS ----- + output [0:0] CO; + + //----- BEGIN wire-connection ports ----- + //----- END wire-connection ports ----- + + + //----- BEGIN Registered ports ----- + //----- END Registered ports ----- + + // ----- Internal logic should start here ----- + assign SUM = A ^ B ^ CI; + assign CO = (A & B) | (A & CI) | (B & CI); + // ----- Internal logic should end here ----- + endmodule + // ----- END Verilog module for ADDF ----- + +We can now link this ``user_defined_template.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``. + +.. note:: Be sure to select the run where you modified the ``user_defined_template.v``! + +From the OpenFPGA root directory, run: + +.. code-block:: bash + + vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +At **LINE187** in verilog_netlist, put in: + +.. code-block:: XML + + ${OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/hard_adder/**YOUR_RUN_NUMBER**/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_template.v + +Finally, rerun this command from the OpenFPGA root directory to ensure it is working: + +.. code-block:: bash + + python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs + + diff --git a/docs/source/tutorials/getting_started/compile.rst b/docs/source/tutorials/getting_started/compile.rst index 8b95c995d..17d333be0 100644 --- a/docs/source/tutorials/getting_started/compile.rst +++ b/docs/source/tutorials/getting_started/compile.rst @@ -11,7 +11,7 @@ How to Compile General Guidelines ~~~~~~~~~~~~~~~~~~ -OpenFPGA uses CMake to generate the Makefile scripts +OpenFPGA uses CMake to generate the Makefile scripts. In general, please follow the steps to compile .. code-block:: shell @@ -24,13 +24,13 @@ In general, please follow the steps to compile .. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI -.. note:: recommand to use ``make -j`` to accelerate the compilation +.. note:: Recommend using ``make -j`` to accelerate the compilation, where ```` denotes the number of cores to be used in compilation. .. note:: VPR's GUI requires gtk-3, and can be enabled with ``cmake .. -DVPR_USE_EZGL=on`` **Quick Compilation Verification** -To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository +To quickly verify the tool is well compiled, users can run the following command from OpenFPGA root repository .. code-block:: shell @@ -38,7 +38,7 @@ To quickly verify the tool is well compiled, user can run the following command Dependencies ~~~~~~~~~~~~ -Full list of dependencies can be found at install_dependencies_build_ +Full list of dependencies can be found at install_dependencies_build_. In particular, OpenFPGA requires specific versions for the following dependencies: :cmake: @@ -46,6 +46,11 @@ In particular, OpenFPGA requires specific versions for the following dependencie :iverilog: version 10.1+ is required to run Verilog-to-Verification flow + +:python dependencies: + python packages are also required: + + python3 -m pip install -r requirements.txt .. _install_dependencies_build: https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh @@ -53,8 +58,8 @@ In particular, OpenFPGA requires specific versions for the following dependencie Running with the docker image ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Users can skip the traditional installation process by using Dockerized version -of the OpenFPGA tool. OpenFPGA project maintains the docker image/Github package of +Users can skip the traditional installation process by using the Dockerized version +of the OpenFPGA tool. The OpenFPGA project maintains the docker image/Github package of the latest stable version of OpenFPGA in the following repository `openfpga-master `_. This image contains precompiled OpenFPGA binaries with all prerequisites installed. @@ -76,4 +81,4 @@ This image contains precompiled OpenFPGA binaries with all prerequisites install .. note:: While running local task using docker, make sure all the additional files - are maintained in the task_directory and reference using variable ${TASK_DIR} \ No newline at end of file + are maintained in the task_directory and reference using variable ${TASK_DIR} diff --git a/docs/source/tutorials/getting_started/shell_shortcuts.rst b/docs/source/tutorials/getting_started/shell_shortcuts.rst index d8b8369e3..8671d9208 100644 --- a/docs/source/tutorials/getting_started/shell_shortcuts.rst +++ b/docs/source/tutorials/getting_started/shell_shortcuts.rst @@ -22,13 +22,13 @@ Once the ``openfpga.sh`` script is sourced, you can run any of the following com .. option:: run-task **kwarags - This command runs the specified task listed from the ``list-task`` command or from the existing directory. The command name is relative to the ``TASK_DIRECTORY``. User can provide any additional arguments which are listed `here <_openfpga_task_args>`_ to this command. + This command runs the specified task listed from the ``list-task`` command or from the existing directory. The command name is relative to the ``TASK_DIRECTORY``. Users can provide any additional arguments which are listed `here <_openfpga_task_args>`_ to this command. .. option:: run-modelsim This command runs the verification using ModelSim. The test benches are generated during the OpenFPGA run. - **Note**: user need to have ``VSIM`` install and configured + **Note**: users need to have ``VSIM`` installed and configured .. option:: run-regression-local diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp index 924e96c0e..f239a78b3 100644 --- a/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting.cpp @@ -16,6 +16,10 @@ BitstreamSetting::bitstream_pb_type_setting_range BitstreamSetting::pb_type_sett return vtr::make_range(pb_type_setting_ids_.begin(), pb_type_setting_ids_.end()); } +BitstreamSetting::bitstream_interconnect_setting_range BitstreamSetting::interconnect_settings() const { + return vtr::make_range(interconnect_setting_ids_.begin(), interconnect_setting_ids_.end()); +} + /************************************************************************ * Constructors ***********************************************************************/ @@ -51,6 +55,36 @@ std::string BitstreamSetting::pb_type_bitstream_content(const BitstreamPbTypeSet return pb_type_bitstream_contents_[pb_type_setting_id]; } +bool BitstreamSetting::is_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return is_mode_select_bitstreams_[pb_type_setting_id]; +} + +size_t BitstreamSetting::bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id) const { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + return bitstream_offsets_[pb_type_setting_id]; +} + +std::string BitstreamSetting::interconnect_name(const BitstreamInterconnectSettingId& interconnect_setting_id) const { + VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id)); + return interconnect_names_[interconnect_setting_id]; +} + +std::vector BitstreamSetting::parent_pb_type_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const { + VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id)); + return interconnect_parent_pb_type_names_[interconnect_setting_id]; +} + +std::vector BitstreamSetting::parent_mode_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const { + VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id)); + return interconnect_parent_mode_names_[interconnect_setting_id]; +} + +std::string BitstreamSetting::default_path(const BitstreamInterconnectSettingId& interconnect_setting_id) const { + VTR_ASSERT(true == valid_bitstream_interconnect_setting_id(interconnect_setting_id)); + return interconnect_default_paths_[interconnect_setting_id]; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -66,10 +100,38 @@ BitstreamPbTypeSettingId BitstreamSetting::add_bitstream_pb_type_setting(const s parent_mode_names_.push_back(parent_mode_names); pb_type_bitstream_sources_.push_back(bitstream_source); pb_type_bitstream_contents_.push_back(bitstream_content); + is_mode_select_bitstreams_.push_back(false); + bitstream_offsets_.push_back(0); return pb_type_setting_id; } +void BitstreamSetting::set_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id, + const bool& is_mode_select_bitstream) { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + is_mode_select_bitstreams_[pb_type_setting_id] = is_mode_select_bitstream; +} + +void BitstreamSetting::set_bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id, + const size_t& offset) { + VTR_ASSERT(true == valid_bitstream_pb_type_setting_id(pb_type_setting_id)); + bitstream_offsets_[pb_type_setting_id] = offset; +} + +BitstreamInterconnectSettingId BitstreamSetting::add_bitstream_interconnect_setting(const std::string& interconnect_name, + const std::vector& parent_pb_type_names, + const std::vector& parent_mode_names, + const std::string& default_path) { + BitstreamInterconnectSettingId interc_setting_id = BitstreamInterconnectSettingId(interconnect_setting_ids_.size()); + interconnect_setting_ids_.push_back(interc_setting_id); + interconnect_names_.push_back(interconnect_name); + interconnect_parent_pb_type_names_.push_back(parent_pb_type_names); + interconnect_parent_mode_names_.push_back(parent_mode_names); + interconnect_default_paths_.push_back(default_path); + + return interc_setting_id; +} + /************************************************************************ * Public Validators ***********************************************************************/ @@ -77,4 +139,8 @@ bool BitstreamSetting::valid_bitstream_pb_type_setting_id(const BitstreamPbTypeS return ( size_t(pb_type_setting_id) < pb_type_setting_ids_.size() ) && ( pb_type_setting_id == pb_type_setting_ids_[pb_type_setting_id] ); } +bool BitstreamSetting::valid_bitstream_interconnect_setting_id(const BitstreamInterconnectSettingId& interconnect_setting_id) const { + return ( size_t(interconnect_setting_id) < interconnect_setting_ids_.size() ) && ( interconnect_setting_id == interconnect_setting_ids_[interconnect_setting_id] ); +} + } /* namespace openfpga ends */ diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting.h b/libopenfpga/libarchopenfpga/src/bitstream_setting.h index d42ebe430..63cb9092b 100644 --- a/libopenfpga/libarchopenfpga/src/bitstream_setting.h +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting.h @@ -16,6 +16,10 @@ namespace openfpga { /******************************************************************** * A data structure to describe bitstream settings + * + * This data structure includes following types of settings: + * - Pb type: include definiting hard coded bitstream for pb_types (LUT or configurable pb_type for mode selection) + * - Interconnect: include defining default paths for routing multiplexers in pb_types * * Typical usage: * -------------- @@ -27,33 +31,70 @@ namespace openfpga { class BitstreamSetting { public: /* Types */ typedef vtr::vector::const_iterator bitstream_pb_type_setting_iterator; + typedef vtr::vector::const_iterator bitstream_interconnect_setting_iterator; /* Create range */ typedef vtr::Range bitstream_pb_type_setting_range; + typedef vtr::Range bitstream_interconnect_setting_range; public: /* Constructors */ BitstreamSetting(); public: /* Accessors: aggregates */ bitstream_pb_type_setting_range pb_type_settings() const; + bitstream_interconnect_setting_range interconnect_settings() const; public: /* Public Accessors */ std::string pb_type_name(const BitstreamPbTypeSettingId& pb_type_setting_id) const; std::vector parent_pb_type_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const; std::vector parent_mode_names(const BitstreamPbTypeSettingId& pb_type_setting_id) const; std::string pb_type_bitstream_source(const BitstreamPbTypeSettingId& pb_type_setting_id) const; std::string pb_type_bitstream_content(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + bool is_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + size_t bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + std::string interconnect_name(const BitstreamInterconnectSettingId& interconnect_setting_id) const; + std::vector parent_pb_type_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const; + std::vector parent_mode_names(const BitstreamInterconnectSettingId& interconnect_setting_id) const; + std::string default_path(const BitstreamInterconnectSettingId& interconnect_setting_id) const; public: /* Public Mutators */ BitstreamPbTypeSettingId add_bitstream_pb_type_setting(const std::string& pb_type_name, const std::vector& parent_pb_type_names, const std::vector& parent_mode_names, const std::string& bitstream_source, const std::string& bitstream_content); + void set_mode_select_bitstream(const BitstreamPbTypeSettingId& pb_type_setting_id, + const bool& is_mode_select_bitstream); + void set_bitstream_offset(const BitstreamPbTypeSettingId& pb_type_setting_id, + const size_t& offset); + + BitstreamInterconnectSettingId add_bitstream_interconnect_setting(const std::string& interconnect_name, + const std::vector& parent_pb_type_names, + const std::vector& parent_mode_names, + const std::string& default_path); public: /* Public Validators */ bool valid_bitstream_pb_type_setting_id(const BitstreamPbTypeSettingId& pb_type_setting_id) const; + bool valid_bitstream_interconnect_setting_id(const BitstreamInterconnectSettingId& interconnect_setting_id) const; private: /* Internal data */ + /* Pb type -related settings + * - Paths to a pb_type in the pb_graph + * - Bitstream source, data_type, offsets etc. + */ vtr::vector pb_type_setting_ids_; vtr::vector pb_type_names_; vtr::vector> parent_pb_type_names_; vtr::vector> parent_mode_names_; vtr::vector pb_type_bitstream_sources_; vtr::vector pb_type_bitstream_contents_; + /* Indicate if the bitstream is applied to mode selection bits of a pb_type */ + vtr::vector is_mode_select_bitstreams_; + /* The offset that the bitstream is applied to the original bitstream of a pb_type */ + vtr::vector bitstream_offsets_; + + /* Interconnect-related settings: + * - Name of interconnect under a given pb_type + * - The default path to be considered for a given interconnect during bitstream generation + */ + vtr::vector interconnect_setting_ids_; + vtr::vector interconnect_names_; + vtr::vector> interconnect_parent_pb_type_names_; + vtr::vector> interconnect_parent_mode_names_; + vtr::vector interconnect_default_paths_; }; } /* namespace openfpga ends */ diff --git a/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h b/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h index 009bcbfed..d5bb618e1 100644 --- a/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h +++ b/libopenfpga/libarchopenfpga/src/bitstream_setting_fwd.h @@ -13,8 +13,10 @@ #include "vtr_strong_id.h" struct bitstream_pb_type_setting_id_tag; +struct bitstream_interconnect_setting_id_tag; typedef vtr::StrongId BitstreamPbTypeSettingId; +typedef vtr::StrongId BitstreamInterconnectSettingId; /* Short declaration of class */ class BitstreamSetting; diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp index 9a369e742..1a1a7ea31 100644 --- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp +++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp @@ -86,11 +86,11 @@ std::vector PbTypeAnnotation::port_names() const { return keys; } -std::map> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const { - std::map>>::const_iterator it = operating_pb_type_ports_.find(port_name); +std::map> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const { + std::map>>::const_iterator it = operating_pb_type_ports_.find(port_name); if (it == operating_pb_type_ports_.end()) { /* Return an empty port */ - return std::map>(); + return std::map>(); } return operating_pb_type_ports_.at(port_name); } @@ -169,25 +169,25 @@ void PbTypeAnnotation::set_physical_pb_type_index_offset(const int& value) { void PbTypeAnnotation::add_pb_type_port_pair(const std::string& operating_pb_port_name, const BasicPort& physical_pb_port) { /* Give a warning if the operating_pb_port_name already exist */ - std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); + std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); /* If not exist, initialize and set a default value */ if (it == operating_pb_type_ports_.end()) { - operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0}; + operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0, 0}; /* We can return early */ return; } /* If the physical port is not in the list, we create one and set a default value */ if (0 == operating_pb_type_ports_[operating_pb_port_name].count(physical_pb_port)) { - operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0}; + operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0, 0}; } } void PbTypeAnnotation::set_physical_pin_initial_offset(const std::string& operating_pb_port_name, const BasicPort& physical_pb_port, const int& physical_pin_initial_offset) { - std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); + std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); if (it == operating_pb_type_ports_.end()) { VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n", @@ -210,7 +210,7 @@ void PbTypeAnnotation::set_physical_pin_initial_offset(const std::string& operat void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name, const BasicPort& physical_pb_port, const int& physical_pin_rotate_offset) { - std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); + std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); if (it == operating_pb_type_ports_.end()) { VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n", @@ -230,6 +230,30 @@ void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operati operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][1] = physical_pin_rotate_offset; } +void PbTypeAnnotation::set_physical_port_rotate_offset(const std::string& operating_pb_port_name, + const BasicPort& physical_pb_port, + const int& physical_port_rotate_offset) { + std::map>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name); + + if (it == operating_pb_type_ports_.end()) { + VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n", + operating_pb_port_name.c_str()); + exit(1); + } + + if (operating_pb_type_ports_[operating_pb_port_name].end() == operating_pb_type_ports_[operating_pb_port_name].find(physical_pb_port)) { + VTR_LOG_ERROR("The physical pb_type port '%s[%lu:%lu]' definition for operating pb_type port '%s' is not valid!\n", + physical_pb_port.get_name().c_str(), + physical_pb_port.get_lsb(), + physical_pb_port.get_msb(), + operating_pb_port_name.c_str()); + exit(1); + } + + operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][2] = physical_port_rotate_offset; +} + + void PbTypeAnnotation::add_interconnect_circuit_model_pair(const std::string& interc_name, const std::string& circuit_model_name) { std::map::const_iterator it = interconnect_circuit_model_names_.find(interc_name); diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h index 96383679d..2a0b8804e 100644 --- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h +++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h @@ -49,7 +49,7 @@ class PbTypeAnnotation { float physical_pb_type_index_factor() const; int physical_pb_type_index_offset() const; std::vector port_names() const; - std::map> physical_pb_type_port(const std::string& port_name) const; + std::map> physical_pb_type_port(const std::string& port_name) const; std::vector interconnect_names() const; std::string interconnect_circuit_model_name(const std::string& interc_name) const; public: /* Public mutators */ @@ -73,6 +73,9 @@ class PbTypeAnnotation { void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name, const BasicPort& physical_pb_port, const int& physical_pin_rotate_offset); + void set_physical_port_rotate_offset(const std::string& operating_pb_port_name, + const BasicPort& physical_pb_port, + const int& physical_port_rotate_offset); void add_interconnect_circuit_model_pair(const std::string& interc_name, const std::string& circuit_model_name); private: /* Internal data */ @@ -138,10 +141,10 @@ class PbTypeAnnotation { int physical_pb_type_index_offset_; /* Link from the pins under an operating pb_type to pairs of - * its physical pb_type and its pin initial & rotating offset - * - * Note that initial offset is the first element of the std::array - * Note that rotating offset is the second element of the std::array + * its physical pb_type and + * - its pin initial offset: the first element of the std::array + * - pin-level rotating offset: the second element of the std::array + * - port-level rotating offset: the third element of the std::array * * The offsets aim to align the pin indices for port of pb_type * between operating and physical modes, especially when an operating @@ -158,14 +161,21 @@ class PbTypeAnnotation { * physical pb_type bram[0].dout_a[0] with a full path memory[physical].bram[0] * physical pb_type bram[0].dout_a[1] with a full path memory[physical].bram[0] * - * For example, a rotating offset of 9 is used to map + * For example, a pin-level rotating offset of 9 is used to map + * operating pb_type mult_9x9[0].a[0] with a full path mult[frac].mult_9x9[0] + * operating pb_type mult_9x9[0].a[1] with a full path mult[frac].mult_9x9[1] + * to + * physical pb_type mult_36x36.a[0] with a full path mult[physical].mult_36x36[0] + * physical pb_type mult_36x36.a[9] with a full path mult[physical].mult_36x36[0] + * + * For example, a port-level rotating offset of 9 is used to map * operating pb_type mult_9x9[0].a[0:8] with a full path mult[frac].mult_9x9[0] * operating pb_type mult_9x9[1].a[0:8] with a full path mult[frac].mult_9x9[1] * to * physical pb_type mult_36x36.a[0:8] with a full path mult[physical].mult_36x36[0] * physical pb_type mult_36x36.a[9:17] with a full path mult[physical].mult_36x36[0] */ - std::map>> operating_pb_type_ports_; + std::map>> operating_pb_type_ports_; /* Link between the interconnects under this pb_type and circuit model names */ std::map interconnect_circuit_model_names_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp index 02f257ffe..05ffc492d 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_bitstream_setting.cpp @@ -36,11 +36,38 @@ void read_xml_bitstream_pb_type_setting(pugi::xml_node& xml_pb_type, openfpga::PbParser operating_pb_parser(name_attr); /* Add to bitstream setting */ - bitstream_setting.add_bitstream_pb_type_setting(operating_pb_parser.leaf(), - operating_pb_parser.parents(), - operating_pb_parser.modes(), - source_attr, - content_attr); + BitstreamPbTypeSettingId bitstream_pb_type_id = bitstream_setting.add_bitstream_pb_type_setting(operating_pb_parser.leaf(), + operating_pb_parser.parents(), + operating_pb_parser.modes(), + source_attr, + content_attr); + + /* Parse if the bitstream overwritting is applied to mode bits of a pb_type */ + const bool& is_mode_select_bitstream = get_attribute(xml_pb_type, "is_mode_select_bitstream", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false); + bitstream_setting.set_mode_select_bitstream(bitstream_pb_type_id, is_mode_select_bitstream); + + const int& offset = get_attribute(xml_pb_type, "bitstream_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0); + bitstream_setting.set_bitstream_offset(bitstream_pb_type_id, offset); +} + +/******************************************************************** + * Parse XML description for a pb_type annotation under a XML node + *******************************************************************/ +static +void read_xml_bitstream_interconnect_setting(pugi::xml_node& xml_pb_type, + const pugiutil::loc_data& loc_data, + openfpga::BitstreamSetting& bitstream_setting) { + const std::string& name_attr = get_attribute(xml_pb_type, "name", loc_data).as_string(); + const std::string& default_path_attr = get_attribute(xml_pb_type, "default_path", loc_data).as_string(); + + /* Parse the attributes for operating pb_type */ + openfpga::PbParser operating_pb_parser(name_attr); + + /* Add to bitstream setting */ + bitstream_setting.add_bitstream_interconnect_setting(operating_pb_parser.leaf(), + operating_pb_parser.parents(), + operating_pb_parser.modes(), + default_path_attr); } /******************************************************************** @@ -53,12 +80,19 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(pugi::xml_node& Node, /* Iterate over the children under this node, * each child should be named after */ - for (pugi::xml_node xml_pb_type : Node.children()) { + for (pugi::xml_node xml_child : Node.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_pb_type.name() != std::string("pb_type")) { - bad_tag(xml_pb_type, loc_data, Node, {"pb_type"}); + if ( (xml_child.name() != std::string("pb_type")) + && (xml_child.name() != std::string("interconnect")) ) { + bad_tag(xml_child, loc_data, Node, {"pb_type | interconnect"}); + } + + if (xml_child.name() == std::string("pb_type")) { + read_xml_bitstream_pb_type_setting(xml_child, loc_data, bitstream_setting); + } else { + VTR_ASSERT_SAFE(xml_child.name() == std::string("interconnect")); + read_xml_bitstream_interconnect_setting(xml_child, loc_data, bitstream_setting); } - read_xml_bitstream_pb_type_setting(xml_pb_type, loc_data, bitstream_setting); } return bitstream_setting; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp index 9831f6e23..f91dc99a8 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp @@ -114,6 +114,31 @@ void read_xml_pb_port_annotation(pugi::xml_node& xml_port, std::stoi(rotate_offsets[iport])); } } + + /* We have an optional attribute: physical_mode_port_rotate_offset + * Split based on the number of physical pb_type ports that have been defined + */ + const std::string& physical_port_rotate_offset_attr = get_attribute(xml_port, "physical_mode_port_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(); + + if (false == physical_port_rotate_offset_attr.empty()) { + /* Split the physical mode port attributes with space */ + openfpga::StringToken offset_tokenizer(physical_port_rotate_offset_attr); + const std::vector rotate_offsets = offset_tokenizer.split(); + + /* Error out if the offset does not match the port definition */ + if (physical_mode_ports.size() != rotate_offsets.size()) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port), + "Defined %lu physical mode ports but only %lu physical port rotate offset are defined! Expect size matching.\n", + physical_mode_ports.size(), rotate_offsets.size()); + } + + for (size_t iport = 0; iport < physical_mode_ports.size(); ++iport) { + openfpga::PortParser port_parser(physical_mode_ports[iport]); + pb_type_annotation.set_physical_port_rotate_offset(name_attr, + port_parser.port(), + std::stoi(rotate_offsets[iport])); + } + } } /******************************************************************** diff --git a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp index 1273f083a..1754fbc4b 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_bitstream_setting.cpp @@ -39,6 +39,31 @@ std::string generate_bitstream_setting_pb_type_hierarchy_name(const openfpga::Bi return hie_name; } +/******************************************************************** + * Generate the full hierarchy name for an interconnect in bitstream setting + *******************************************************************/ +static +std::string generate_bitstream_setting_interconnect_hierarchy_name(const openfpga::BitstreamSetting& bitstream_setting, + const BitstreamInterconnectSettingId& bitstream_interc_setting_id) { + /* Iterate over the parent_pb_type and modes names, they should well match */ + VTR_ASSERT_SAFE(bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id).size() == bitstream_setting.parent_mode_names(bitstream_interc_setting_id).size()); + + std::string hie_name; + + for (size_t i = 0 ; i < bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id).size(); ++i) { + hie_name += bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id)[i]; + hie_name += std::string("["); + hie_name += bitstream_setting.parent_mode_names(bitstream_interc_setting_id)[i]; + hie_name += std::string("]"); + hie_name += std::string("."); + } + + /* Add the leaf pb_type */ + hie_name += bitstream_setting.interconnect_name(bitstream_interc_setting_id); + + return hie_name; +} + /******************************************************************** * A writer to output a bitstream pb_type setting to XML format *******************************************************************/ @@ -57,6 +82,29 @@ void write_xml_bitstream_pb_type_setting(std::fstream& fp, write_xml_attribute(fp, "source", bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str()); write_xml_attribute(fp, "content", bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id).c_str()); + write_xml_attribute(fp, "is_mode_select_bitstream", bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id)); + write_xml_attribute(fp, "bitstream_offset", bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id)); + + fp << "/>" << "\n"; +} + +/******************************************************************** + * A writer to output a bitstream interconnect setting to XML format + *******************************************************************/ +static +void write_xml_bitstream_interconnect_setting(std::fstream& fp, + const char* fname, + const openfpga::BitstreamSetting& bitstream_setting, + const BitstreamInterconnectSettingId& bitstream_interc_setting_id) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + fp << "\t" << "" << "\n"; } @@ -74,11 +122,16 @@ void write_xml_bitstream_setting(std::fstream& fp, */ fp << "" << "\n"; - /* Write clock settings */ + /* Write pb_type -related settings */ for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) { write_xml_bitstream_pb_type_setting(fp, fname, bitstream_setting, bitstream_pb_type_setting_id); } + /* Write interconnect -related settings */ + for (const auto& bitstream_interc_setting_id : bitstream_setting.interconnect_settings()) { + write_xml_bitstream_interconnect_setting(fp, fname, bitstream_setting, bitstream_interc_setting_id); + } + /* Write the root node */ fp << "" << "\n"; } diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp index e9b36522c..b401f6ca8 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp @@ -144,7 +144,14 @@ void write_xml_pb_port_annotation(std::fstream& fp, physical_mode_pin_rotate_offset_attr += std::to_string(physical_pb_port_pair.second[1]); } write_xml_attribute(fp, "physical_mode_pin_rotate_offset", physical_mode_pin_rotate_offset_attr.c_str()); - + std::string physical_mode_port_rotate_offset_attr; + for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) { + if (false == physical_mode_port_rotate_offset_attr.empty()) { + physical_mode_port_rotate_offset_attr += " "; + } + physical_mode_port_rotate_offset_attr += std::to_string(physical_pb_port_pair.second[2]); + } + write_xml_attribute(fp, "physical_mode_port_rotate_offset", physical_mode_port_rotate_offset_attr.c_str()); fp << "/>" << "\n"; } diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp index 8968b8d1c..721c147d4 100644 --- a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp @@ -71,5 +71,27 @@ size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamMa return curr_index; } +/******************************************************************** + * Find the total number of configuration bits under a block + * As configuration bits are stored only under the leaf blocks, + * this function will recursively visit all the child blocks + * until reaching a leaf block, where we collect the number of bits + *******************************************************************/ +size_t rec_find_bitstream_manager_block_sum_of_bits(const BitstreamManager& bitstream_manager, + const ConfigBlockId& block) { + /* For leaf block, return directly with the number of bits, because it has not child block */ + if (0 < bitstream_manager.block_bits(block).size()) { + VTR_ASSERT_SAFE(bitstream_manager.block_children(block).empty()); + return bitstream_manager.block_bits(block).size(); + } + + size_t sum_of_bits = 0; + /* Dive to child blocks if this block has any */ + for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { + sum_of_bits += rec_find_bitstream_manager_block_sum_of_bits(bitstream_manager, child_block); + } + + return sum_of_bits; +} } /* end namespace openfpga */ diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h index 328394b01..e1e8b8567 100644 --- a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h +++ b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h @@ -22,6 +22,9 @@ std::vector find_bitstream_manager_top_blocks(const BitstreamMana size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamManager& bitstream_manager, const ConfigBitId& bit_id); +size_t rec_find_bitstream_manager_block_sum_of_bits(const BitstreamManager& bitstream_manager, + const ConfigBlockId& block); + } /* end namespace openfpga */ #endif diff --git a/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.cpp b/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.cpp new file mode 100644 index 000000000..1667b3e86 --- /dev/null +++ b/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.cpp @@ -0,0 +1,124 @@ +/******************************************************************** + * This file includes functions that report distribution of bitstream by blocks + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" +#include "openfpga_tokenizer.h" +#include "openfpga_version.h" + +#include "openfpga_reserved_words.h" + +#include "bitstream_manager_utils.h" +#include "report_arch_bitstream_distribution.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function write header information for an XML file of bitstream distribution + *******************************************************************/ +static +void report_architecture_bitstream_distribution_xml_file_head(std::fstream& fp) { + valid_file_stream(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << " " << std::endl; + fp << std::endl; +} + +/******************************************************************** + * Recursively report the bitstream distribution of a block to a file + * This function will use a Depth-First Search in outputting bitstream + * for each block + * For block with child blocks, we visit each child recursively + * The reporting can be stopped at a given maximum hierarchy level + * which is used to limit the length of the report + *******************************************************************/ +static +void rec_report_block_bitstream_distribution_to_xml_file(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const ConfigBlockId& block, + const size_t& max_hierarchy_level, + const size_t& hierarchy_level) { + valid_file_stream(fp); + + if (hierarchy_level > max_hierarchy_level) { + return; + } + + /* Write the bitstream distribution of this block */ + write_tab_to_file(fp, hierarchy_level); + fp << "" << std::endl; + + /* Dive to child blocks if this block has any */ + for (const ConfigBlockId& child_block : bitstream_manager.block_children(block)) { + rec_report_block_bitstream_distribution_to_xml_file(fp, bitstream_manager, child_block, + max_hierarchy_level, hierarchy_level + 1); + } + + write_tab_to_file(fp, hierarchy_level); + fp << "" < top_block = find_bitstream_manager_top_blocks(bitstream_manager); + /* Make sure we have only 1 top block */ + VTR_ASSERT(1 == top_block.size()); + + /* Write bitstream, block by block, in a recursive way */ + rec_report_block_bitstream_distribution_to_xml_file(fp, bitstream_manager, top_block[0], max_hierarchy_level, 0); + + /* Close file handler */ + fp.close(); + + return 0; +} + +} /* end namespace openfpga */ diff --git a/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.h b/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.h new file mode 100644 index 000000000..322a65901 --- /dev/null +++ b/libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.h @@ -0,0 +1,23 @@ +#ifndef REPORT_ARCH_BITSTREAM_DISTRIBUTION_H +#define REPORT_ARCH_BITSTREAM_DISTRIBUTION_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "bitstream_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int report_architecture_bitstream_distribution(const BitstreamManager& bitstream_manager, + const std::string& fname, + const size_t& max_hierarchy_level = 1); + +} /* end namespace openfpga */ + +#endif diff --git a/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp index 88d00601e..d71b077c4 100644 --- a/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp +++ b/libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp @@ -10,17 +10,18 @@ /* Headers from fabric key */ #include "read_xml_arch_bitstream.h" #include "write_xml_arch_bitstream.h" +#include "report_arch_bitstream_distribution.h" int main(int argc, const char** argv) { - /* Ensure we have only one or two argument */ - VTR_ASSERT((2 == argc) || (3 == argc)); + /* Ensure we have only one or two or 3 argument */ + VTR_ASSERT((2 == argc) || (3 == argc) || (4 == argc)); /* Parse the bitstream from an XML file */ openfpga::BitstreamManager test_bitstream = openfpga::read_xml_architecture_bitstream(argv[1]); VTR_LOG("Read the bitstream from an XML file: %s.\n", argv[1]); - /* Output the circuit library to an XML file + /* Output the bitstream database to an XML file * This is optional only used when there is a second argument */ if (3 <= argc) { @@ -28,6 +29,15 @@ int main(int argc, const char** argv) { VTR_LOG("Echo the bitstream to an XML file: %s.\n", argv[2]); } + /* Output the bitstream distribution to an XML file + * This is optional only used when there is a third argument + */ + if (4 <= argc) { + openfpga::report_architecture_bitstream_distribution(test_bitstream, argv[3]); + VTR_LOG("Echo the bitstream distribution to an XML file: %s.\n", + argv[3]); + } + } diff --git a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h index 2f9bae817..732247178 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h +++ b/libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h @@ -59,6 +59,9 @@ constexpr char* DEFAULT_LB_DIR_NAME = "lb/"; constexpr char* DEFAULT_RR_DIR_NAME = "routing/"; constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/"; +constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:"; +constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_"; + } /* end namespace openfpga */ #endif diff --git a/libopenfpga/libpcf/src/pin_constraints.cpp b/libopenfpga/libpcf/src/pin_constraints.cpp index 4f7a701a7..bc68b3bd8 100644 --- a/libopenfpga/libpcf/src/pin_constraints.cpp +++ b/libopenfpga/libpcf/src/pin_constraints.cpp @@ -38,6 +38,58 @@ std::string PinConstraints::net(const PinConstraintId& pin_constraint_id) const return pin_constraint_nets_[pin_constraint_id]; } +std::string PinConstraints::pin_net(const openfpga::BasicPort& pin) const { + std::string constrained_net_name; + for (const PinConstraintId& pin_constraint : pin_constraints()) { + if (pin == pin_constraint_pins_[pin_constraint]) { + constrained_net_name = net(pin_constraint); + break; + } + } + return constrained_net_name; +} + +openfpga::BasicPort PinConstraints::net_pin(const std::string& net) const { + openfpga::BasicPort constrained_pin; + for (const PinConstraintId& pin_constraint : pin_constraints()) { + if (net == pin_constraint_nets_[pin_constraint]) { + constrained_pin = pin(pin_constraint); + break; + } + } + return constrained_pin; +} + +PinConstraints::e_logic_level PinConstraints::net_default_value(const std::string& net) const { + PinConstraints::e_logic_level logic_level = PinConstraints::NUM_LOGIC_LEVELS; + for (const PinConstraintId& pin_constraint : pin_constraints()) { + if (net == pin_constraint_nets_[pin_constraint]) { + logic_level = pin_constraint_net_default_values_[pin_constraint]; + break; + } + } + return logic_level; +} + +std::string PinConstraints::net_default_value_to_string(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (PinConstraints::LOGIC_HIGH == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("1"); + } else if (PinConstraints::LOGIC_LOW == pin_constraint_net_default_values_[pin_constraint]) { + return std::string("0"); + } + return std::string(); +} + +size_t PinConstraints::net_default_value_to_int(const std::string& net) const { + if (PinConstraints::LOGIC_HIGH == net_default_value(net)) { + return 1; + } else if (PinConstraints::LOGIC_LOW == net_default_value(net)) { + return 0; + } + return -1; +} + bool PinConstraints::empty() const { return 0 == pin_constraint_ids_.size(); } @@ -49,6 +101,7 @@ void PinConstraints::reserve_pin_constraints(const size_t& num_pin_constraints) pin_constraint_ids_.reserve(num_pin_constraints); pin_constraint_pins_.reserve(num_pin_constraints); pin_constraint_nets_.reserve(num_pin_constraints); + pin_constraint_net_default_values_.reserve(num_pin_constraints); } PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin, @@ -59,10 +112,21 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& pin_constraint_ids_.push_back(pin_constraint_id); pin_constraint_pins_.push_back(pin); pin_constraint_nets_.push_back(net); + pin_constraint_net_default_values_.push_back(PinConstraints::NUM_LOGIC_LEVELS); return pin_constraint_id; } +void PinConstraints::set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value) { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + if (default_value == std::string("1")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_HIGH; + } else if (default_value == std::string("0")) { + pin_constraint_net_default_values_[pin_constraint] = PinConstraints::LOGIC_LOW; + } +} + /************************************************************************ * Internal invalidators/validators ***********************************************************************/ @@ -70,3 +134,20 @@ PinConstraintId PinConstraints::create_pin_constraint(const openfpga::BasicPort& bool PinConstraints::valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const { return ( size_t(pin_constraint_id) < pin_constraint_ids_.size() ) && ( pin_constraint_id == pin_constraint_ids_[pin_constraint_id] ); } + +bool PinConstraints::unconstrained_net(const std::string& net) const { + return net.empty(); +} + +bool PinConstraints::unmapped_net(const std::string& net) const { + return std::string(PIN_CONSTRAINT_OPEN_NET) == net; +} + +bool PinConstraints::valid_net_default_value(const PinConstraintId& pin_constraint) const { + VTR_ASSERT(valid_pin_constraint_id(pin_constraint)); + return PinConstraints::NUM_LOGIC_LEVELS != pin_constraint_net_default_values_[pin_constraint]; +} + +bool PinConstraints::valid_net_default_value(const std::string& net) const { + return PinConstraints::NUM_LOGIC_LEVELS != net_default_value(net); +} diff --git a/libopenfpga/libpcf/src/pin_constraints.h b/libopenfpga/libpcf/src/pin_constraints.h index 8b3a977c0..a60f0aae4 100644 --- a/libopenfpga/libpcf/src/pin_constraints.h +++ b/libopenfpga/libpcf/src/pin_constraints.h @@ -41,6 +41,12 @@ class PinConstraints { typedef vtr::vector::const_iterator pin_constraint_iterator; /* Create range */ typedef vtr::Range pin_constraint_range; + /* Logic value */ + enum e_logic_level { + LOGIC_HIGH, + LOGIC_LOW, + NUM_LOGIC_LEVELS + }; public: /* Constructors */ PinConstraints(); public: /* Accessors: aggregates */ @@ -52,11 +58,36 @@ class PinConstraints { /* Get the net to be constrained */ std::string net(const PinConstraintId& pin_constraint_id) const; + /* Find the net that is constrained on a pin + * TODO: this function will only return the first net found in the constraint list + */ + std::string pin_net(const openfpga::BasicPort& pin) const; + + /* Find the pin that a net is constrained to + * If not found, the return port will be an invalid BasicPort + * TODO: this function will only return the first pin found in the constraint list + */ + openfpga::BasicPort net_pin(const std::string& net) const; + + /* Find the default value that a net is constrained to + * If not found, return an invalid value + */ + e_logic_level net_default_value(const std::string& net) const; + + /* Generate the string of the default value + * If not found, return an empty string + */ + std::string net_default_value_to_string(const PinConstraintId& pin_constraint) const; + + /* Generate the integer representation of the default value + * If not found, return -1 + */ + size_t net_default_value_to_int(const std::string& net) const; + /* Check if there are any pin constraints */ bool empty() const; public: /* Public Mutators */ - /* Reserve a number of design constraints to be memory efficent */ void reserve_pin_constraints(const size_t& num_pin_constraints); @@ -64,8 +95,37 @@ class PinConstraints { PinConstraintId create_pin_constraint(const openfpga::BasicPort& pin, const std::string& net); + /* Set the default value for the net under a given pin constraint */ + void set_net_default_value(const PinConstraintId& pin_constraint, + const std::string& default_value); + public: /* Public invalidators/validators */ + /* Show if the pin constraint id is a valid for data queries */ bool valid_pin_constraint_id(const PinConstraintId& pin_constraint_id) const; + + /* Show if the net has no constraints (free to map to any pin) + * This function is used to identify the net name returned by APIs: + * - pin_net() + * - net() + */ + bool unconstrained_net(const std::string& net) const; + + /* Show if the net is defined specifically not to map to any pin + * This function is used to identify the net name returned by APIs: + * - pin_net() + * - net() + */ + bool unmapped_net(const std::string& net) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const PinConstraintId& pin_constraint) const; + + /* Check if default value is a valid one or not + * This is to check if the default value is constrained or not + */ + bool valid_net_default_value(const std::string& net) const; private: /* Internal data */ /* Unique ids for each design constraint */ vtr::vector pin_constraint_ids_; @@ -75,6 +135,9 @@ class PinConstraints { /* Nets to constraint */ vtr::vector pin_constraint_nets_; + + /* Default value of the nets to constraint */ + vtr::vector pin_constraint_net_default_values_; }; #endif diff --git a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp index b0c662da5..98527cb32 100644 --- a/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/read_xml_pin_constraints.cpp @@ -41,6 +41,14 @@ void read_xml_pin_constraint(pugi::xml_node& xml_pin_constraint, archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), "Fail to create pin constraint!\n"); } + + /* Set default value if defined */ + std::string default_value = get_attribute(xml_pin_constraint, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(); + pin_constraints.set_net_default_value(pin_constraint_id, default_value); + if (!default_value.empty() && !pin_constraints.valid_net_default_value(pin_constraint_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), + "Invalid default value for pin constraints. Expect [0|1]!\n"); + } } /******************************************************************** diff --git a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp index 80a664f3f..ef728be95 100644 --- a/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp +++ b/libopenfpga/libpcf/src/write_xml_pin_constraints.cpp @@ -44,6 +44,7 @@ int write_xml_pin_constraint(std::fstream& fp, write_xml_attribute(fp, "pin", generate_xml_port_name(pin_constraints.pin(pin_constraint)).c_str()); write_xml_attribute(fp, "net", pin_constraints.net(pin_constraint).c_str()); + write_xml_attribute(fp, "default_value", pin_constraints.net_default_value_to_string(pin_constraint).c_str()); fp << "/>" << "\n"; diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.cpp b/libopenfpga/librepackdc/src/repack_design_constraints.cpp index d19c1ba71..c32ad6bb3 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.cpp +++ b/libopenfpga/librepackdc/src/repack_design_constraints.cpp @@ -50,6 +50,20 @@ std::string RepackDesignConstraints::net(const RepackDesignConstraintId& repack_ return repack_design_constraint_nets_[repack_design_constraint_id]; } +std::string RepackDesignConstraints::find_constrained_pin_net(const std::string& pb_type, + const openfpga::BasicPort& pin) const { + std::string constrained_net_name; + for (const RepackDesignConstraintId& design_constraint : design_constraints()) { + /* If found a constraint, record the net name */ + if ( (pb_type == repack_design_constraint_pb_types_[design_constraint]) + && (pin == repack_design_constraint_pins_[design_constraint])) { + constrained_net_name = repack_design_constraint_nets_[design_constraint]; + break; + } + } + return constrained_net_name; +} + bool RepackDesignConstraints::empty() const { return 0 == repack_design_constraint_ids_.size(); } @@ -106,3 +120,11 @@ void RepackDesignConstraints::set_net(const RepackDesignConstraintId& repack_des bool RepackDesignConstraints::valid_design_constraint_id(const RepackDesignConstraintId& design_constraint_id) const { return ( size_t(design_constraint_id) < repack_design_constraint_ids_.size() ) && ( design_constraint_id == repack_design_constraint_ids_[design_constraint_id] ); } + +bool RepackDesignConstraints::unconstrained_net(const std::string& net) const { + return net.empty(); +} + +bool RepackDesignConstraints::unmapped_net(const std::string& net) const { + return std::string(REPACK_DESIGN_CONSTRAINT_OPEN_NET) == net; +} diff --git a/libopenfpga/librepackdc/src/repack_design_constraints.h b/libopenfpga/librepackdc/src/repack_design_constraints.h index c32a0aca8..8c1ca6415 100644 --- a/libopenfpga/librepackdc/src/repack_design_constraints.h +++ b/libopenfpga/librepackdc/src/repack_design_constraints.h @@ -61,6 +61,10 @@ class RepackDesignConstraints { /* Get the net to be constrained */ std::string net(const RepackDesignConstraintId& repack_design_constraint_id) const; + /* Find a constrained net */ + std::string find_constrained_pin_net(const std::string& pb_type, + const openfpga::BasicPort& pin) const; + /* Check if there are any design constraints */ bool empty() const; @@ -86,6 +90,20 @@ class RepackDesignConstraints { public: /* Public invalidators/validators */ bool valid_design_constraint_id(const RepackDesignConstraintId& repack_design_constraint_id) const; + /* Show if the net has no constraints (free to map to any pin) + * This function is used to identify the net name returned by APIs: + * - find_constrained_pin_net() + * - net() + */ + bool unconstrained_net(const std::string& net) const; + + /* Show if the net is defined specifically not to map to any pin + * This function is used to identify the net name returned by APIs: + * - find_constrained_pin_net() + * - net() + */ + bool unmapped_net(const std::string& net) const; + private: /* Internal data */ /* Unique ids for each design constraint */ vtr::vector repack_design_constraint_ids_; diff --git a/openfpga.sh b/openfpga.sh index f0ab701ee..a00b8adbd 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -21,7 +21,7 @@ if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi # inside current OpendFPGA folder check_execution_path (){ if [[ $1 != *"${OPENFPGA_PATH}"* ]]; then - echo -e "\e[33mCommand is not executed from configured OPNEFPGA directory\e[0m" + echo -e "\e[33mCommand is not executed from configured OPENFPGA directory\e[0m" fi } diff --git a/openfpga/src/annotation/annotate_bitstream_setting.cpp b/openfpga/src/annotation/annotate_bitstream_setting.cpp index fbcb92cf0..a51e73fde 100644 --- a/openfpga/src/annotation/annotate_bitstream_setting.cpp +++ b/openfpga/src/annotation/annotate_bitstream_setting.cpp @@ -12,6 +12,9 @@ #include "vtr_assert.h" #include "vtr_log.h" +/* Headers from openfpgautil library */ +#include "openfpga_tokenizer.h" + #include "pb_type_utils.h" #include "annotate_bitstream_setting.h" @@ -23,9 +26,10 @@ namespace openfpga { * - Find the pb_type and link to the bitstream source * - Find the pb_type and link to the bitstream content *******************************************************************/ -int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, - const DeviceContext& vpr_device_ctx, - VprBitstreamAnnotation& vpr_bitstream_annotation) { +static +int annotate_bitstream_pb_type_setting(const BitstreamSetting& bitstream_setting, + const DeviceContext& vpr_device_ctx, + VprBitstreamAnnotation& vpr_bitstream_annotation) { for (const auto& bitstream_pb_type_setting_id : bitstream_setting.pb_type_settings()) { /* Get the full name of pb_type */ @@ -56,17 +60,30 @@ int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, if (nullptr == target_pb_type) { continue; } + /* Found one, build annotation */ - if (std::string("eblif") == bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) { - vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF); - } else { + if (std::string("eblif") != bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id)) { /* Invalid source, error out! */ VTR_LOG_ERROR("Invalid bitstream source '%s' for pb_type '%s' which is defined in bitstream setting\n", bitstream_setting.pb_type_bitstream_source(bitstream_pb_type_setting_id).c_str(), target_pb_type_names[0].c_str()); return CMD_EXEC_FATAL_ERROR; } - vpr_bitstream_annotation.set_pb_type_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id)); + + /* Depending on the bitstream type, annotate through different entrances + * - For regular bitstream, set bitstream content, flags etc. + * - For mode-select bitstream, set mode-select bitstream content, flags etc. + */ + if (false == bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id)) { + vpr_bitstream_annotation.set_pb_type_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF); + vpr_bitstream_annotation.set_pb_type_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id)); + vpr_bitstream_annotation.set_pb_type_bitstream_offset(target_pb_type, bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id)); + } else { + VTR_ASSERT_SAFE(false == bitstream_setting.is_mode_select_bitstream(bitstream_pb_type_setting_id)); + vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_source(target_pb_type, VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF); + vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_content(target_pb_type, bitstream_setting.pb_type_bitstream_content(bitstream_pb_type_setting_id)); + vpr_bitstream_annotation.set_pb_type_mode_select_bitstream_offset(target_pb_type, bitstream_setting.bitstream_offset(bitstream_pb_type_setting_id)); + } link_success = true; } @@ -82,4 +99,135 @@ int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Annotate bitstream setting based on VPR device information + * - Find the interconnect and link to the default path id + *******************************************************************/ +static +int annotate_bitstream_interconnect_setting(const BitstreamSetting& bitstream_setting, + const DeviceContext& vpr_device_ctx, + const VprDeviceAnnotation& vpr_device_annotation, + VprBitstreamAnnotation& vpr_bitstream_annotation) { + + for (const auto& bitstream_interc_setting_id : bitstream_setting.interconnect_settings()) { + /* Get the full name of pb_type */ + std::vector target_pb_type_names; + std::vector target_pb_mode_names; + + target_pb_type_names = bitstream_setting.parent_pb_type_names(bitstream_interc_setting_id); + target_pb_mode_names = bitstream_setting.parent_mode_names(bitstream_interc_setting_id); + /* Kick out the last mode so that we can use an existing function search the pb_type in graph */ + std::string expected_physical_mode_name = target_pb_mode_names.back(); + target_pb_mode_names.pop_back(); + + std::string interconnect_name = bitstream_setting.interconnect_name(bitstream_interc_setting_id); + std::string expected_input_path = bitstream_setting.default_path(bitstream_interc_setting_id); + + /* Pb type information are located at the logic_block_types in the device context of VPR + * We iterate over the vectors and find the pb_type matches the parent_pb_type_name + */ + bool link_success = false; + + for (const t_logical_block_type& lb_type : vpr_device_ctx.logical_block_types) { + /* By pass nullptr for pb_type head */ + if (nullptr == lb_type.pb_type) { + continue; + } + /* Check the name of the top-level pb_type, if it does not match, we can bypass */ + if (target_pb_type_names[0] != std::string(lb_type.pb_type->name)) { + continue; + } + /* Match the name in the top-level, we go further to search the pb_type in the graph */ + t_pb_type* target_pb_type = try_find_pb_type_with_given_path(lb_type.pb_type, target_pb_type_names, + target_pb_mode_names); + if (nullptr == target_pb_type) { + continue; + } + + /* Found one, build annotation */ + t_mode* physical_mode = vpr_device_annotation.physical_mode(target_pb_type); + + VTR_ASSERT(nullptr != physical_mode); + /* Ensure that the annotation is only applicable to physical mode */ + if (std::string(physical_mode->name) != expected_physical_mode_name) { + VTR_LOG_ERROR("The physical mode '%s' under pb_type '%s' does not match in the bitstream setting '%s'!\n", + physical_mode->name, + target_pb_type->name, + expected_physical_mode_name.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + + /* Find the interconnect name under the physical mode of a physical pb_type */ + t_interconnect* pb_interc = find_pb_mode_interconnect(physical_mode, interconnect_name.c_str()); + + if (nullptr == pb_interc) { + VTR_LOG_ERROR("Unable to find interconnect '%s' under physical mode '%s' of pb_type '%s'!\n", + interconnect_name.c_str(), + physical_mode->name, + target_pb_type->name); + return CMD_EXEC_FATAL_ERROR; + } + + /* Find the default path and spot the path id from the input string recorded */ + StringToken input_string_tokenizer(std::string(pb_interc->input_string)); + std::vector input_paths = input_string_tokenizer.split(' '); + size_t input_path_id = input_paths.size(); + for (size_t ipath = 0; ipath < input_paths.size(); ++ipath) { + if (expected_input_path == input_paths[ipath]) { + input_path_id = ipath; + break; + } + } + /* If the input_path id is invalid, error out! */ + if (input_path_id == input_paths.size()) { + VTR_LOG_ERROR("Invalid default path '%s' for interconnect '%s' which inputs are '%s'\n", + expected_input_path.c_str(), + interconnect_name.c_str(), + pb_interc->input_string); + return CMD_EXEC_FATAL_ERROR; + } + + vpr_bitstream_annotation.set_interconnect_default_path_id(pb_interc, input_path_id); + + link_success = true; + } + + /* If fail to link bitstream setting to architecture, error out immediately */ + if (false == link_success) { + VTR_LOG_ERROR("Fail to find an interconnect '%s' with default path '%s', which is defined in bitstream setting from VPR architecture description\n", + interconnect_name.c_str(), + expected_input_path.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } + + return CMD_EXEC_SUCCESS; +} + +/******************************************************************** + * Annotate bitstream setting based on VPR device information + * - Fill pb_type -related mapping + * - Fill interconnect -related mapping + *******************************************************************/ +int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, + const DeviceContext& vpr_device_ctx, + const VprDeviceAnnotation& vpr_device_annotation, + VprBitstreamAnnotation& vpr_bitstream_annotation) { + + int status = CMD_EXEC_SUCCESS; + + status = annotate_bitstream_pb_type_setting(bitstream_setting, + vpr_device_ctx, + vpr_bitstream_annotation); + if (status == CMD_EXEC_FATAL_ERROR) { + return status; + } + + status = annotate_bitstream_interconnect_setting(bitstream_setting, + vpr_device_ctx, vpr_device_annotation, + vpr_bitstream_annotation); + + return status; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_bitstream_setting.h b/openfpga/src/annotation/annotate_bitstream_setting.h index 053ca2fbe..45d6316dd 100644 --- a/openfpga/src/annotation/annotate_bitstream_setting.h +++ b/openfpga/src/annotation/annotate_bitstream_setting.h @@ -16,6 +16,7 @@ namespace openfpga { int annotate_bitstream_setting(const BitstreamSetting& bitstream_setting, const DeviceContext& vpr_device_ctx, + const VprDeviceAnnotation& vpr_device_annotation, VprBitstreamAnnotation& vpr_bitstream_annotation); } /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp index 67a1baba8..bed7997cc 100644 --- a/openfpga/src/annotation/annotate_pb_graph.cpp +++ b/openfpga/src/annotation/annotate_pb_graph.cpp @@ -333,7 +333,7 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin, * by the pin rotate offset value * The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port */ - int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port); + int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port) + vpr_device_annotation.physical_pb_port_offset(operating_pb_graph_pin->port, candidate_port); int init_offset = vpr_device_annotation.physical_pb_pin_initial_offset(operating_pb_graph_pin->port, candidate_port); const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port, candidate_port); if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number @@ -463,6 +463,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no physical_pb_graph_node, vpr_device_annotation, verbose_output); } + /* Finish a port, accumulate the port-level offset affiliated to the port */ + if (0 == operating_pb_graph_node->num_input_pins[iport]) { + continue; + } + t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->input_pins[iport][0]); + for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) { + vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port); + } } for (int iport = 0; iport < operating_pb_graph_node->num_output_ports; ++iport) { @@ -471,6 +479,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no physical_pb_graph_node, vpr_device_annotation, verbose_output); } + /* Finish a port, accumulate the port-level offset affiliated to the port */ + if (0 == operating_pb_graph_node->num_output_pins[iport]) { + continue; + } + t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->output_pins[iport][0]); + for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) { + vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port); + } } for (int iport = 0; iport < operating_pb_graph_node->num_clock_ports; ++iport) { @@ -479,6 +495,14 @@ void annotate_physical_pb_graph_node_pins(t_pb_graph_node* operating_pb_graph_no physical_pb_graph_node, vpr_device_annotation, verbose_output); } + /* Finish a port, accumulate the port-level offset affiliated to the port */ + if (0 == operating_pb_graph_node->num_clock_pins[iport]) { + continue; + } + t_pb_graph_pin* operating_pb_graph_pin = &(operating_pb_graph_node->clock_pins[iport][0]); + for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) { + vpr_device_annotation.accumulate_physical_pb_port_rotate_offset(operating_pb_graph_pin->port, candidate_port); + } } } diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp index 92a6f6560..e4b5f972c 100644 --- a/openfpga/src/annotation/annotate_pb_types.cpp +++ b/openfpga/src/annotation/annotate_pb_types.cpp @@ -211,7 +211,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, * if not found, we assume that the physical port is the same as the operating pb_port */ for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) { - std::map> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name)); + std::map> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name)); /* If not defined in the annotation, set the default pair: * rotate_offset is 0 by default! @@ -243,6 +243,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type, vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, physical_pb_port, expected_physical_pb_port.first); vpr_device_annotation.add_physical_pb_pin_initial_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[0]); vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[1]); + vpr_device_annotation.add_physical_pb_port_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[2]); } } diff --git a/openfpga/src/annotation/annotate_physical_tiles.cpp b/openfpga/src/annotation/annotate_physical_tiles.cpp new file mode 100644 index 000000000..4c95b0754 --- /dev/null +++ b/openfpga/src/annotation/annotate_physical_tiles.cpp @@ -0,0 +1,48 @@ +/******************************************************************** + * This file includes functions to build links between pb_types + * in particular to annotate the physical mode and physical pb_type + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_time.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "annotate_physical_tiles.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Build the fast look-up for each physical tile between + * pin index and the physical port information, i.e., port name and port index + *******************************************************************/ +void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx, + VprDeviceAnnotation& vpr_device_annotation) { + + vtr::ScopedStartFinishTimer timer("Build fast look-up for physical tile pins"); + + for (const t_physical_tile_type& physical_tile : vpr_device_ctx.physical_tile_types) { + /* Count the number of pins for each sub tile */ + int num_pins_per_subtile = 0; + for (const t_physical_tile_port& tile_port : physical_tile.ports) { + num_pins_per_subtile += tile_port.num_pins; + } + /* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */ + for (int subtile_index = 0; subtile_index < physical_tile.capacity; ++subtile_index) { + for (const t_physical_tile_port& tile_port : physical_tile.ports) { + for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) { + int absolute_pin_index = subtile_index * num_pins_per_subtile + tile_port.absolute_first_pin_index + pin_index; + BasicPort tile_port_info(tile_port.name, pin_index, pin_index); + vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile, + absolute_pin_index, + tile_port_info); + vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile, + absolute_pin_index, + subtile_index); + } + } + } + } +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/annotation/annotate_physical_tiles.h b/openfpga/src/annotation/annotate_physical_tiles.h new file mode 100644 index 000000000..726461359 --- /dev/null +++ b/openfpga/src/annotation/annotate_physical_tiles.h @@ -0,0 +1,23 @@ +#ifndef ANNOTATE_PHYSICAL_TILES_H +#define ANNOTATE_PHYSICAL_TILES_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "vpr_context.h" +#include "openfpga_context.h" +#include "vpr_device_annotation.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx, + VprDeviceAnnotation& vpr_device_annotation); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/annotation/vpr_bitstream_annotation.cpp b/openfpga/src/annotation/vpr_bitstream_annotation.cpp index fdb66048c..38842cbff 100644 --- a/openfpga/src/annotation/vpr_bitstream_annotation.cpp +++ b/openfpga/src/annotation/vpr_bitstream_annotation.cpp @@ -4,6 +4,7 @@ #include "vtr_log.h" #include "vtr_assert.h" #include "vpr_bitstream_annotation.h" +#include "mux_bitstream_constants.h" /* namespace openfpga begins */ namespace openfpga { @@ -38,6 +39,56 @@ std::string VprBitstreamAnnotation::pb_type_bitstream_content(t_pb_type* pb_type return std::string(); } +size_t VprBitstreamAnnotation::pb_type_bitstream_offset(t_pb_type* pb_type) const { + auto result = bitstream_offsets_.find(pb_type); + if (result != bitstream_offsets_.end()) { + return result->second; + } + + /* Not found, return an zero offset */ + return 0; +} + +VprBitstreamAnnotation::e_bitstream_source_type VprBitstreamAnnotation::pb_type_mode_select_bitstream_source(t_pb_type* pb_type) const { + auto result = mode_select_bitstream_sources_.find(pb_type); + if (result != mode_select_bitstream_sources_.end()) { + return result->second; + } + + /* Not found, return an invalid type*/ + return NUM_BITSTREAM_SOURCE_TYPES; +} + +std::string VprBitstreamAnnotation::pb_type_mode_select_bitstream_content(t_pb_type* pb_type) const { + auto result = mode_select_bitstream_contents_.find(pb_type); + if (result != mode_select_bitstream_contents_.end()) { + return result->second; + } + + /* Not found, return an invalid type */ + return std::string(); +} + +size_t VprBitstreamAnnotation::pb_type_mode_select_bitstream_offset(t_pb_type* pb_type) const { + auto result = mode_select_bitstream_offsets_.find(pb_type); + if (result != mode_select_bitstream_offsets_.end()) { + return result->second; + } + + /* Not found, return an zero offset */ + return 0; +} + +size_t VprBitstreamAnnotation::interconnect_default_path_id(t_interconnect* interconnect) const { + auto result = interconnect_default_path_ids_.find(interconnect); + if (result != interconnect_default_path_ids_.end()) { + return result->second; + } + + /* Not found, return an invalid input id */ + return DEFAULT_PATH_ID; +} + /************************************************************************ * Public mutators ***********************************************************************/ @@ -45,10 +96,35 @@ void VprBitstreamAnnotation::set_pb_type_bitstream_source(t_pb_type* pb_type, const e_bitstream_source_type& bitstream_source) { bitstream_sources_[pb_type] = bitstream_source; } + void VprBitstreamAnnotation::set_pb_type_bitstream_content(t_pb_type* pb_type, const std::string& bitstream_content) { bitstream_contents_[pb_type] = bitstream_content; } +void VprBitstreamAnnotation::set_pb_type_bitstream_offset(t_pb_type* pb_type, + const size_t& offset) { + bitstream_offsets_[pb_type] = offset; +} + +void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_source(t_pb_type* pb_type, + const e_bitstream_source_type& bitstream_source) { + mode_select_bitstream_sources_[pb_type] = bitstream_source; +} + +void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_content(t_pb_type* pb_type, + const std::string& bitstream_content) { + mode_select_bitstream_contents_[pb_type] = bitstream_content; +} + +void VprBitstreamAnnotation::set_pb_type_mode_select_bitstream_offset(t_pb_type* pb_type, + const size_t& offset) { + mode_select_bitstream_offsets_[pb_type] = offset; +} + +void VprBitstreamAnnotation::set_interconnect_default_path_id(t_interconnect* interconnect, + const size_t& default_path_id) { + interconnect_default_path_ids_[interconnect] = default_path_id; +} } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_bitstream_annotation.h b/openfpga/src/annotation/vpr_bitstream_annotation.h index c8d4102a0..134530f25 100644 --- a/openfpga/src/annotation/vpr_bitstream_annotation.h +++ b/openfpga/src/annotation/vpr_bitstream_annotation.h @@ -33,16 +33,50 @@ class VprBitstreamAnnotation { public: /* Public accessors */ e_bitstream_source_type pb_type_bitstream_source(t_pb_type* pb_type) const; std::string pb_type_bitstream_content(t_pb_type* pb_type) const; + size_t pb_type_bitstream_offset(t_pb_type* pb_type) const; + + e_bitstream_source_type pb_type_mode_select_bitstream_source(t_pb_type* pb_type) const; + std::string pb_type_mode_select_bitstream_content(t_pb_type* pb_type) const; + size_t pb_type_mode_select_bitstream_offset(t_pb_type* pb_type) const; + size_t interconnect_default_path_id(t_interconnect* interconnect) const; public: /* Public mutators */ void set_pb_type_bitstream_source(t_pb_type* pb_type, const e_bitstream_source_type& bitstream_source); void set_pb_type_bitstream_content(t_pb_type* pb_type, const std::string& bitstream_content); + void set_pb_type_bitstream_offset(t_pb_type* pb_type, + const size_t& offset); + + void set_pb_type_mode_select_bitstream_source(t_pb_type* pb_type, + const e_bitstream_source_type& bitstream_source); + void set_pb_type_mode_select_bitstream_content(t_pb_type* pb_type, + const std::string& bitstream_content); + void set_pb_type_mode_select_bitstream_offset(t_pb_type* pb_type, + const size_t& offset); + void set_interconnect_default_path_id(t_interconnect* interconnect, + const size_t& default_path_id); private: /* Internal data */ + /* For regular bitstreams */ /* A look up for pb type to find bitstream source type */ std::map bitstream_sources_; /* Binding from pb type to bitstream content */ std::map bitstream_contents_; + /* Offset to be applied to bitstream */ + std::map bitstream_offsets_; + + /* For mode-select bitstreams */ + /* A look up for pb type to find bitstream source type */ + std::map mode_select_bitstream_sources_; + /* Binding from pb type to bitstream content */ + std::map mode_select_bitstream_contents_; + /* Offset to be applied to mode-select bitstream */ + std::map mode_select_bitstream_offsets_; + + /* A look up for interconnect to find default path indices + * Note: this is different from the default path in bitstream setting which is the index + * of inputs in the context of the interconnect input string + */ + std::map interconnect_default_path_ids_; }; } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp index f07378634..eef4fafbb 100644 --- a/openfpga/src/annotation/vpr_device_annotation.cpp +++ b/openfpga/src/annotation/vpr_device_annotation.cpp @@ -220,6 +220,21 @@ int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* operating_pb_port return physical_pb_pin_rotate_offsets_.at(operating_pb_port).at(physical_pb_port); } +int VprDeviceAnnotation::physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port) const { + /* Ensure that the pb_type is in the list */ + std::map>::const_iterator it = physical_pb_port_rotate_offsets_.find(operating_pb_port); + if (it == physical_pb_port_rotate_offsets_.end()) { + /* Default value is 0 */ + return 0; + } + if (0 == physical_pb_port_rotate_offsets_.at(operating_pb_port).count(physical_pb_port)) { + /* Default value is 0 */ + return 0; + } + return physical_pb_port_rotate_offsets_.at(operating_pb_port).at(physical_pb_port); +} + int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port, t_port* physical_pb_port) const { /* Ensure that the pb_type is in the list */ @@ -235,6 +250,21 @@ int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port, return physical_pb_pin_offsets_.at(operating_pb_port).at(physical_pb_port); } +int VprDeviceAnnotation::physical_pb_port_offset(t_port* operating_pb_port, + t_port* physical_pb_port) const { + /* Ensure that the pb_type is in the list */ + std::map>::const_iterator it = physical_pb_port_offsets_.find(operating_pb_port); + if (it == physical_pb_port_offsets_.end()) { + /* Default value is 0 */ + return 0; + } + if (0 == physical_pb_port_offsets_.at(operating_pb_port).count(physical_pb_port)) { + /* Default value is 0 */ + return 0; + } + return physical_pb_port_offsets_.at(operating_pb_port).at(physical_pb_port); +} + t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const { /* Ensure that the pb_type is in the list */ std::map::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin); @@ -278,6 +308,46 @@ LbRRGraph VprDeviceAnnotation::physical_lb_rr_graph(t_pb_graph_node* pb_graph_he return physical_lb_rr_graphs_.at(pb_graph_head); } +BasicPort VprDeviceAnnotation::physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const { + /* Try to find the physical tile in the fast look-up */ + auto physical_tile_search_result = physical_tile_pin2port_info_map_.find(physical_tile); + if (physical_tile_search_result == physical_tile_pin2port_info_map_.end()) { + /* Not found. Return an invalid port */ + return BasicPort(); + } + + /* Try to find the physical tile port info with pin index */ + auto pin_search_result = physical_tile_search_result->second.find(pin_index); + if (pin_search_result == physical_tile_search_result->second.end()) { + /* Not found. Return an invalid port */ + return BasicPort(); + } + + /* Reach here, we should find a port. Return the port information */ + return pin_search_result->second; +} + +int VprDeviceAnnotation::physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const { + /* Try to find the physical tile in the fast look-up */ + auto physical_tile_search_result = physical_tile_pin_subtile_indices_.find(physical_tile); + if (physical_tile_search_result == physical_tile_pin_subtile_indices_.end()) { + /* Not found. Return an invalid index */ + return -1; + } + + /* Try to find the physical tile port info with pin index */ + auto pin_search_result = physical_tile_search_result->second.find(pin_index); + if (pin_search_result == physical_tile_search_result->second.end()) { + /* Not found. Return an invalid index */ + return -1; + } + + /* Reach here, we should find a port. Return the port information */ + return pin_search_result->second; +} + /************************************************************************ * Public mutators ***********************************************************************/ @@ -438,6 +508,28 @@ void VprDeviceAnnotation::add_physical_pb_pin_initial_offset(t_port* operating_p physical_pb_pin_initial_offsets_[operating_pb_port][physical_pb_port] = offset; } +void VprDeviceAnnotation::add_physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port, + const int& offset) { + /* Warn any override attempt */ + std::map>::const_iterator it = physical_pb_port_rotate_offsets_.find(operating_pb_port); + if ( (it != physical_pb_port_rotate_offsets_.end()) + && (0 < physical_pb_port_rotate_offsets_[operating_pb_port].count(physical_pb_port)) ) { + VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s' port rotate offset '%d'!\n", + operating_pb_port->name, offset); + } + + physical_pb_port_rotate_offsets_[operating_pb_port][physical_pb_port] = offset; + /* We initialize the accumulated offset to 0 */ + physical_pb_port_offsets_[operating_pb_port][physical_pb_port] = 0; +} + + +void VprDeviceAnnotation::accumulate_physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port) { + physical_pb_port_offsets_[operating_pb_port][physical_pb_port] += physical_pb_port_rotate_offsets_[operating_pb_port][physical_pb_port]; +} + void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* operating_pb_port, t_port* physical_pb_port, const int& offset) { @@ -533,4 +625,16 @@ void VprDeviceAnnotation::add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_hea physical_lb_rr_graphs_[pb_graph_head] = lb_rr_graph; } +void VprDeviceAnnotation::add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const BasicPort& port) { + physical_tile_pin2port_info_map_[physical_tile][pin_index] = port; +} + +void VprDeviceAnnotation::add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const int& subtile_index) { + physical_tile_pin_subtile_indices_[physical_tile][pin_index] = subtile_index; +} + } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h index 0e290f18e..d1a0f8e99 100644 --- a/openfpga/src/annotation/vpr_device_annotation.h +++ b/openfpga/src/annotation/vpr_device_annotation.h @@ -67,6 +67,9 @@ class VprDeviceAnnotation { int physical_pb_pin_rotate_offset(t_port* operating_pb_port, t_port* physical_pb_port) const; + int physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port) const; + /**This function returns an accumulated offset. Note that the * accumulated offset is NOT the pin rotate offset specified by users * It is an aggregation of the offset during pin pairing @@ -76,11 +79,17 @@ class VprDeviceAnnotation { */ int physical_pb_pin_offset(t_port* operating_pb_port, t_port* physical_pb_port) const; + int physical_pb_port_offset(t_port* operating_pb_port, + t_port* physical_pb_port) const; t_pb_graph_pin* physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const; CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const; CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const; ArchDirectId direct_annotation(const size_t& direct) const; LbRRGraph physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const; + BasicPort physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const; + int physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index) const; public: /* Public mutators */ void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode); void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type); @@ -102,6 +111,11 @@ class VprDeviceAnnotation { void add_physical_pb_pin_initial_offset(t_port* operating_pb_port, t_port* physical_pb_port, const int& offset); + void add_physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port, + const int& offset); + void accumulate_physical_pb_port_rotate_offset(t_port* operating_pb_port, + t_port* physical_pb_port); void add_physical_pb_pin_rotate_offset(t_port* operating_pb_port, t_port* physical_pb_port, const int& offset); @@ -110,6 +124,12 @@ class VprDeviceAnnotation { void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model); void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id); void add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph); + void add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const BasicPort& port); + void add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile, + const int& pin_index, + const int& subtile_index); private: /* Internal data */ /* Pair a regular pb_type to its physical pb_type */ std::map physical_pb_types_; @@ -156,8 +176,11 @@ class VprDeviceAnnotation { std::map> physical_pb_ports_; std::map> physical_pb_pin_initial_offsets_; std::map> physical_pb_pin_rotate_offsets_; + std::map> physical_pb_port_rotate_offsets_; - /* Accumulated offsets for a physical pb_type port, just for internal usage */ + /* Accumulated offsets for a physical pb port, just for internal usage */ + std::map> physical_pb_port_offsets_; + /* Accumulated offsets for a physical pb_graph_pin, just for internal usage */ std::map> physical_pb_pin_offsets_; /* Pair a pb_port to its LSB and MSB of a physical pb_port @@ -197,6 +220,11 @@ class VprDeviceAnnotation { /* Logical type routing resource graphs built from physical modes */ std::map physical_lb_rr_graphs_; + + /* A fast look-up from pin index in physical tile to physical tile port */ + std::map> physical_tile_pin2port_info_map_; + /* A fast look-up from pin index in physical tile to sub tile index */ + std::map> physical_tile_pin_subtile_indices_; }; } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 63c5454a7..8aa8fb3b6 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -60,6 +60,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)] << " side=\"" << gsb_side_manager.to_string() << "\" index=\"" << inode + << "\" node_id=\"" << size_t(cur_rr_node) << "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size() << "\">" << std::endl; @@ -85,6 +86,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, fp << "\t\t" @@ -116,6 +118,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)] << " side=\"" << gsb_side_manager.to_string() << "\" index=\"" << inode + << "\" node_id=\"" << size_t(cur_rr_node) << "\" segment_id=\"" << size_t(src_segment_id) << "\" mux_size=\"" << driver_rr_edges.size() << "\">" @@ -126,7 +129,8 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, SideManager oppo_side = gsb_side_manager.get_opposite(); fp << "\t\t" << std::endl; @@ -144,6 +148,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, fp << "\t\t" << std::endl; @@ -152,6 +157,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix, fp << "\t\t" << std::endl; diff --git a/openfpga/src/base/io_map.cpp b/openfpga/src/base/io_map.cpp new file mode 100644 index 000000000..3012c4285 --- /dev/null +++ b/openfpga/src/base/io_map.cpp @@ -0,0 +1,54 @@ +/****************************************************************************** + * Memember functions for data structure IoMap + ******************************************************************************/ +#include "vtr_assert.h" + +#include "io_map.h" + +/* begin namespace openfpga */ +namespace openfpga { + +IoMap::io_map_range IoMap::io_map() const { + return vtr::make_range(io_map_ids_.begin(), io_map_ids_.end()); +} + +BasicPort IoMap::io_port(IoMapId io_map_id) const { + VTR_ASSERT(valid_io_map_id(io_map_id)); + return io_ports_[io_map_id]; +} + +BasicPort IoMap::io_net(IoMapId io_map_id) const { + VTR_ASSERT(valid_io_map_id(io_map_id)); + return mapped_nets_[io_map_id]; +} + +bool IoMap::is_io_output(IoMapId io_map_id) const { + VTR_ASSERT(valid_io_map_id(io_map_id)); + return IoMap::IO_MAP_DIR_OUTPUT == io_directionality_[io_map_id]; +} + +bool IoMap::is_io_input(IoMapId io_map_id) const { + VTR_ASSERT(valid_io_map_id(io_map_id)); + return IoMap::IO_MAP_DIR_INPUT == io_directionality_[io_map_id]; +} + +IoMapId IoMap::create_io_mapping(const BasicPort& port, + const BasicPort& net, + IoMap::e_direction dir) { + /* Create a new id */ + IoMapId io_map_id = IoMapId(io_map_ids_.size()); + io_map_ids_.push_back(io_map_id); + + /* Allocate related attributes */ + io_ports_.push_back(port); + mapped_nets_.push_back(net); + io_directionality_.push_back(dir); + + return io_map_id; +} + +bool IoMap::valid_io_map_id(IoMapId io_map_id) const { + return (size_t(io_map_id) < io_map_ids_.size()) && (io_map_id == io_map_ids_[io_map_id]); +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/base/io_map.h b/openfpga/src/base/io_map.h new file mode 100644 index 000000000..5bc378000 --- /dev/null +++ b/openfpga/src/base/io_map.h @@ -0,0 +1,59 @@ +#ifndef IO_MAP_H +#define IO_MAP_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include "vtr_vector.h" +#include "openfpga_port.h" +#include "io_map_fwd.h" + +/* Begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This is a data structure storing io mapping information + * - the net-to-I/O mapping + * - each I/O directionality + *******************************************************************/ +class IoMap { + public: /* Types and ranges */ + enum e_direction { + IO_MAP_DIR_INPUT, + IO_MAP_DIR_OUTPUT, + NUM_IO_MAP_DIR_TYPES + }; + typedef vtr::vector::const_iterator io_map_iterator; + typedef vtr::Range io_map_range; + public: /* Public aggregators */ + /* Find all io mapping */ + io_map_range io_map() const; + + /* Get the port of the io that is mapped */ + BasicPort io_port(IoMapId io_map_id) const; + + /* Get the net of the io that is mapped to */ + BasicPort io_net(IoMapId io_map_id) const; + + /* Query on if an io is configured as an input */ + bool is_io_input(IoMapId io_map_id) const; + + /* Query on if an io is configured as an output */ + bool is_io_output(IoMapId io_map_id) const; + public: /* Public mutators */ + /* Create a new I/O mapping */ + IoMapId create_io_mapping(const BasicPort& port, + const BasicPort& net, + e_direction dir); + public: /* Public validators/invalidators */ + bool valid_io_map_id(IoMapId io_map_id) const; + private: /* Internal Data */ + vtr::vector io_map_ids_; + vtr::vector io_ports_; + vtr::vector mapped_nets_; + vtr::vector io_directionality_; +}; + +} /* End namespace openfpga*/ + +#endif diff --git a/openfpga/src/base/io_map_fwd.h b/openfpga/src/base/io_map_fwd.h new file mode 100644 index 000000000..0de3e99c1 --- /dev/null +++ b/openfpga/src/base/io_map_fwd.h @@ -0,0 +1,23 @@ +/************************************************** + * This file includes only declarations for + * the data structures for IoMap + * Please refer to io_map.h for more details + *************************************************/ +#ifndef IO_MAP_FWD_H +#define IO_MAP_FWD_H + +#include "vtr_strong_id.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/* Strong Ids */ +struct io_map_id_tag; + +typedef vtr::StrongId IoMapId; + +class IoMap; + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index c32e9ae87..b978b200d 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -10,15 +10,21 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" +#include "openfpga_reserved_words.h" /* Headers from fpgabitstream library */ #include "read_xml_arch_bitstream.h" #include "write_xml_arch_bitstream.h" +#include "report_arch_bitstream_distribution.h" + +#include "openfpga_naming.h" #include "build_device_bitstream.h" #include "write_text_fabric_bitstream.h" #include "write_xml_fabric_bitstream.h" #include "build_fabric_bitstream.h" +#include "build_io_mapping_info.h" +#include "write_xml_io_mapping.h" #include "openfpga_bitstream.h" /* Include global variables of VPR */ @@ -86,6 +92,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_file_format = cmd.option("format"); + CommandOptionId opt_fast_config = cmd.option("fast_configuration"); /* Write fabric bitstream if required */ int status = CMD_EXEC_SUCCESS; @@ -114,11 +121,96 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, status = write_fabric_bitstream_to_text_file(openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(), openfpga_ctx.arch().config_protocol, + openfpga_ctx.fabric_global_port_info(), cmd_context.option_value(cmd, opt_file), + cmd_context.option_enable(cmd, opt_fast_config), cmd_context.option_enable(cmd, opt_verbose)); } return status; } +/******************************************************************** + * A wrapper function to call the write_io_mapping() in FPGA bitstream + *******************************************************************/ +int write_io_mapping(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + + /* Write fabric bitstream if required */ + int status = CMD_EXEC_SUCCESS; + + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + + std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + + /* Create directories */ + create_directory(src_dir_path); + + /* Create a module as the top-level fabric, and add it to the module manager */ + std::string top_module_name = generate_fpga_top_module_name(); + ModuleId top_module = openfpga_ctx.module_graph().find_module(top_module_name); + VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module)); + + /* VPR added a prefix to the output ports, remove them here */ + std::vector prefix_to_remove; + prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX)); + prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX)); + + IoMap io_map = build_fpga_io_mapping_info(openfpga_ctx.module_graph(), + top_module, + g_vpr_ctx.atom(), + g_vpr_ctx.placement(), + openfpga_ctx.io_location_map(), + openfpga_ctx.vpr_netlist_annotation(), + std::string(), + std::string(), + prefix_to_remove); + + status = write_io_mapping_to_xml_file(io_map, + cmd_context.option_value(cmd, opt_file), + cmd_context.option_enable(cmd, opt_verbose)); + + return status; +} + +/******************************************************************** + * A wrapper function to call the report_arch_bitstream_distribution() in FPGA bitstream + *******************************************************************/ +int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_file = cmd.option("file"); + + int status = CMD_EXEC_SUCCESS; + + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + + std::string src_dir_path = find_path_dir_name(cmd_context.option_value(cmd, opt_file)); + + /* Create directories */ + create_directory(src_dir_path); + + /* Default depth requirement, this is to limit the report size by default */ + int depth = 1; + CommandOptionId opt_depth = cmd.option("depth"); + if (true == cmd_context.option_enable(cmd, opt_depth)) { + depth = std::atoi(cmd_context.option_value(cmd, opt_depth).c_str()); + /* Error out if we have negative depth */ + if (0 > depth) { + VTR_LOG_ERROR("Invalid depth '%d' which should be 0 or a positive number!\n", + depth); + return CMD_EXEC_FATAL_ERROR; + } + } + + status = report_architecture_bitstream_distribution(openfpga_ctx.bitstream_manager(), + cmd_context.option_value(cmd, opt_file), + depth); + + return status; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_bitstream.h b/openfpga/src/base/openfpga_bitstream.h index c210d6bab..c04fb7656 100644 --- a/openfpga/src/base/openfpga_bitstream.h +++ b/openfpga/src/base/openfpga_bitstream.h @@ -24,6 +24,12 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context); +int write_io_mapping(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + +int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_bitstream_command.cpp b/openfpga/src/base/openfpga_bitstream_command.cpp index 6b7397a1c..a59d19adf 100644 --- a/openfpga/src/base/openfpga_bitstream_command.cpp +++ b/openfpga/src/base/openfpga_bitstream_command.cpp @@ -72,6 +72,40 @@ ShellCommandId add_openfpga_build_arch_bitstream_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("report_bitstream_distribution"); + + /* Add an option '--file' */ + CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the bitstream distribution"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--depth' */ + CommandOptionId opt_depth = shell_cmd.add_option("depth", false, "Specify the max. depth of blocks which will appear in report"); + shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'report_bitstream_distribution' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Report bitstream distribution"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, report_bitstream_distribution); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + /******************************************************************** * - Add a command to Shell environment: build_fabric_bitstream * - Add associated options @@ -117,6 +151,9 @@ ShellCommandId add_openfpga_write_fabric_bitstream_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_io_mapping"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option("file", true, "file path to output the io mapping information"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command 'fabric_bitstream' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "Write the I/O mapping information to a file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_io_mapping); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + /******************************************************************** * Top-level function to add all the commands related to FPGA-Bitstream *******************************************************************/ @@ -157,6 +224,14 @@ void add_openfpga_bitstream_commands(openfpga::Shell& shell) { cmd_dependency_build_arch_bitstream.push_back(shell_cmd_repack_id); ShellCommandId shell_cmd_build_arch_bitstream_id = add_openfpga_build_arch_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_build_arch_bitstream); + /******************************** + * Command 'report_bitstream_distribution' + */ + /* The 'report_bitstream_distribution' command should NOT be executed before 'build_architecture_bitstream' */ + std::vector cmd_dependency_report_bitstream_distribution; + cmd_dependency_build_arch_bitstream.push_back(shell_cmd_build_arch_bitstream_id); + add_openfpga_report_bitstream_distribution_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_report_bitstream_distribution); + /******************************** * Command 'build_fabric_bitstream' */ @@ -172,6 +247,14 @@ void add_openfpga_bitstream_commands(openfpga::Shell& shell) { std::vector cmd_dependency_write_fabric_bitstream; cmd_dependency_write_fabric_bitstream.push_back(shell_cmd_build_fabric_bitstream_id); add_openfpga_write_fabric_bitstream_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_write_fabric_bitstream); + + /******************************** + * Command 'write_io_mapping' + */ + /* The 'write_io_mapping' command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_write_io_mapping; + cmd_dependency_write_io_mapping.push_back(shell_cmd_build_fabric_id); + add_openfpga_write_io_mapping_command(shell, openfpga_bitstream_cmd_class, cmd_dependency_write_io_mapping); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index f33a292c6..3da3f3ae1 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -16,6 +16,7 @@ #include "vpr_device_annotation.h" #include "pb_type_utils.h" +#include "annotate_physical_tiles.h" #include "annotate_pb_types.h" #include "annotate_pb_graph.h" #include "annotate_routing.h" @@ -72,6 +73,10 @@ int link_arch(OpenfpgaContext& openfpga_ctx, CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges"); CommandOptionId opt_verbose = cmd.option("verbose"); + /* Build fast look-up between physical tile pin index and port information */ + build_physical_tile_pin2port_info(g_vpr_ctx.device(), + openfpga_ctx.mutable_vpr_device_annotation()); + /* Annotate pb_type graphs * - physical pb_type * - mode selection bits for pb_type and pb interconnect @@ -172,7 +177,9 @@ int link_arch(OpenfpgaContext& openfpga_ctx, /* Build bitstream annotation based on bitstream settings */ if (CMD_EXEC_FATAL_ERROR == annotate_bitstream_setting(openfpga_ctx.bitstream_setting(), g_vpr_ctx.device(), + openfpga_ctx.vpr_device_annotation(), openfpga_ctx.mutable_vpr_bitstream_annotation())) { + return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 192015ddf..71d9dff58 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -505,36 +505,26 @@ std::string generate_connection_block_module_name(const t_rr_type& cb_type, * This function will generate a full port name including coordinates * so that each pin in top-level netlists is unique! *********************************************************************/ -std::string generate_grid_port_name(const vtr::Point& coordinate, - const size_t& width, +std::string generate_grid_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, - const bool& for_top_netlist) { - if (true == for_top_netlist) { - std::string port_name = std::string("grid_"); - port_name += std::to_string(coordinate.x()); - port_name += std::string("__"); - port_name += std::to_string(coordinate.y()); - port_name += std::string("__pin_"); - port_name += std::to_string(height); - port_name += std::string("__"); - port_name += std::to_string(size_t(side)); - port_name += std::string("__"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - return port_name; - } - /* For non-top netlist */ - VTR_ASSERT( false == for_top_netlist ); + const BasicPort& pin_info) { + /* Ensure that the pin is 1-bit ONLY !!! */ + VTR_ASSERT(1 == pin_info.get_width()); + SideManager side_manager(side); std::string port_name = std::string(side_manager.to_string()); port_name += std::string("_width_"); port_name += std::to_string(width); port_name += std::string("_height_"); port_name += std::to_string(height); + port_name += std::string("_subtile_"); + port_name += std::to_string(subtile_index); port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); + port_name += pin_info.get_name(); + port_name += std::string("_"); + port_name += std::to_string(pin_info.get_lsb()); port_name += std::string("_"); return port_name; } @@ -547,18 +537,25 @@ std::string generate_grid_port_name(const vtr::Point& coordinate, *********************************************************************/ std::string generate_grid_duplicated_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& upper_port) { - /* For non-top netlist */ + /* Ensure that the pin is 1-bit ONLY !!! */ + VTR_ASSERT(1 == pin_info.get_width()); + SideManager side_manager(side); std::string port_name = std::string(side_manager.to_string()); port_name += std::string("_width_"); port_name += std::to_string(width); port_name += std::string("_height_"); port_name += std::to_string(height); + port_name += std::string("_subtile_"); + port_name += std::to_string(subtile_index); port_name += std::string("__pin_"); - port_name += std::to_string(pin_id); + port_name += pin_info.get_name(); + port_name += std::string("_"); + port_name += std::to_string(pin_info.get_lsb()); port_name += std::string("_"); if (true == upper_port) { @@ -571,106 +568,19 @@ std::string generate_grid_duplicated_port_name(const size_t& width, return port_name; } - /********************************************************************* - * Generate the port name for a grid in the context of a module + * Generate the port name for a grid in the context of a routing module * To keep a short and simple name, this function will not * include any grid coorindate information! - *********************************************************************/ -std::string generate_grid_module_port_name(const size_t& pin_id) { + **********************************************************************/ +std::string generate_routing_module_grid_port_name(const size_t& width, + const size_t& height, + const int& subtile_index, + const e_side& side, + const BasicPort& pin_info) { /* For non-top netlist */ std::string port_name = std::string("grid_"); - port_name += std::string("pin_"); - port_name += std::to_string(pin_id); - port_name += std::string("_"); - return port_name; -} - -/********************************************************************* - * Generate the port name for a Grid - * This is a wrapper function for generate_port_name() - * which can automatically decode the port name by the pin side and height - *********************************************************************/ -std::string generate_grid_side_port_name(const DeviceGrid& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id) { - /* Output the pins on the side*/ - size_t width = grids[coordinate.x()][coordinate.y()].type->pin_width_offset[pin_id]; - size_t height = grids[coordinate.x()][coordinate.y()].type->pin_height_offset[pin_id]; - if (true != grids[coordinate.x()][coordinate.y()].type->pinloc[width][height][side][pin_id]) { - SideManager side_manager(side); - VTR_LOG_ERROR("Fail to generate a grid pin (x=%lu, y=%lu, width=%lu, height=%lu, side=%s, index=%d)\n", - coordinate.x(), coordinate.y(), width, height, side_manager.c_str(), pin_id); - exit(1); - } - return generate_grid_port_name(coordinate, width, height, side, pin_id, true); -} - -/********************************************************************* - * Generate the port name of a grid pin for a routing module, - * which could be a switch block or a connection block - * Note that to ensure unique grid port name in the context of a routing module, - * we need a prefix which denotes the relative location of the port in the routing module - * - * The prefix is created by considering the the grid coordinate - * and switch block coordinate - * Detailed rules in conversion is as follows: - * - * top_left top_right - * +------------------------+ - * left_top | | right_top - * | Switch Block | - * | [x][y] | - * | | - * | | - * left_right | | right_bottom - * +------------------------+ - * bottom_left bottom_right - * - * +-------------------------------------------------------- - * | Grid Coordinate | Pin side of grid | module side - * +-------------------------------------------------------- - * | [x][y+1] | right | top_left - * +-------------------------------------------------------- - * | [x][y+1] | bottom | left_top - * +-------------------------------------------------------- - * | [x+1][y+1] | left | top_right - * +-------------------------------------------------------- - * | [x+1][y+1] | bottom | right_top - * +-------------------------------------------------------- - * | [x][y] | top | left_right - * +-------------------------------------------------------- - * | [x][y] | right | bottom_left - * +-------------------------------------------------------- - * | [x+1][y] | top | right_bottom - * +-------------------------------------------------------- - * | [x+1][y] | left | bottom_right - * +-------------------------------------------------------- - * - *********************************************************************/ -std::string generate_sb_module_grid_port_name(const e_side& sb_side, - const e_side& grid_side, - const size_t& pin_id) { - SideManager sb_side_manager(sb_side); - SideManager grid_side_manager(grid_side); - /* Relative location is opposite to the side in grid context */ - grid_side_manager.set_opposite(); - std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string(); - return prefix + std::string("_") + generate_grid_module_port_name(pin_id); -} - -/********************************************************************* - * Generate the port name of a grid pin for a routing module, - * which could be a switch block or a connection block - * Note that to ensure unique grid port name in the context of a routing module, - * we need a prefix which denotes the relative location of the port in the routing module - *********************************************************************/ -std::string generate_cb_module_grid_port_name(const e_side& cb_side, - const size_t& pin_id) { - SideManager side_manager(cb_side); - std::string prefix = side_manager.to_string(); - return prefix + std::string("_") + generate_grid_module_port_name(pin_id); + return port_name + generate_grid_port_name(width, height, subtile_index, side, pin_info); } /********************************************************************* diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index a3cfac08c..319e99a60 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -15,6 +15,7 @@ #include "vtr_geometry.h" #include "circuit_library.h" #include "device_grid.h" +#include "openfpga_port.h" /******************************************************************** * Function declaration @@ -134,32 +135,24 @@ std::string generate_pb_memory_instance_name(const std::string& prefix, t_pb_graph_pin* pb_graph_pin, const std::string& postfix); -std::string generate_grid_port_name(const vtr::Point& coordinate, - const size_t& width, +std::string generate_grid_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, - const bool& for_top_netlist); + const BasicPort& pin_info); std::string generate_grid_duplicated_port_name(const size_t& width, const size_t& height, + const int& subtile_index, const e_side& side, - const size_t& pin_id, + const BasicPort& pin_info, const bool& upper_port); -std::string generate_grid_module_port_name(const size_t& pin_id); - -std::string generate_grid_side_port_name(const DeviceGrid& grids, - const vtr::Point& coordinate, - const e_side& side, - const size_t& pin_id); - -std::string generate_sb_module_grid_port_name(const e_side& sb_side, - const e_side& grid_side, - const size_t& pin_id); - -std::string generate_cb_module_grid_port_name(const e_side& cb_side, - const size_t& pin_id); +std::string generate_routing_module_grid_port_name(const size_t& width, + const size_t& height, + const int& subtile_index, + const e_side& side, + const BasicPort& pin_info); std::string generate_reserved_sram_port_name(const e_circuit_model_port_type& port_type); diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 358ae2fb9..74bb744f0 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -96,20 +96,49 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct /* Find the net mapped to this pin in clustering results*/ ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j); - /* Ignore those net have never been routed */ + /* Ignore those net have never been routed: this check is valid only + * when both packer has mapped a net to the pin and the router leaves the pin to be unmapped + * This is important because we cannot bypass when router forces a valid net to be mapped + * and the net remapping has to be considered + */ if ( (ClusterNetId::INVALID() != cluster_net_id) + && (ClusterNetId::INVALID() == routing_net_id) && (true == clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id))) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is not routed\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } /* Ignore used in local cluster only, reserved one CLB pin */ if ( (ClusterNetId::INVALID() != cluster_net_id) && (0 == clustering_ctx.clb_nlist.net_sinks(cluster_net_id).size())) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it is a local net inside the cluster\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } /* If matched, we finish here */ if (routing_net_id == cluster_net_id) { + VTR_LOGV(verbose, + "Bypass net at clustered block '%s' pin 'grid[%ld][%ld].%s.%s[%d]' as it matches cluster routing\n", + clustering_ctx.clb_nlist.block_pb(blk_id)->name, + grid_coord.x(), grid_coord.y(), + clustering_ctx.clb_nlist.block_pb(blk_id)->pb_graph_node->pb_type->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->port->name, + get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)->pin_number + ); continue; } diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index ad92228f1..b912c518c 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -8,6 +8,9 @@ /* Headers from openfpgashell library */ #include "command_exit_codes.h" +/* Headers from openfpgautil library */ +#include "openfpga_scale.h" + #include "verilog_api.h" #include "openfpga_verilog.h" @@ -62,23 +65,20 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, } /******************************************************************** - * A wrapper function to call the Verilog testbench generator of FPGA-Verilog + * A wrapper function to call the full testbench generator of FPGA-Verilog *******************************************************************/ -int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, - const Command& cmd, const CommandContext& cmd_context) { +int write_full_testbench(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_output_dir = cmd.option("file"); + CommandOptionId opt_bitstream = cmd.option("bitstream"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); - CommandOptionId opt_print_top_testbench = cmd.option("print_top_testbench"); CommandOptionId opt_fast_configuration = cmd.option("fast_configuration"); - CommandOptionId opt_print_formal_verification_top_netlist = cmd.option("print_formal_verification_top_netlist"); - CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench"); - CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini"); CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_default_net_type = cmd.option("default_net_type"); CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); - CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator"); CommandOptionId opt_verbose = cmd.option("verbose"); /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog @@ -88,15 +88,14 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); - options.set_print_formal_verification_top_netlist(cmd_context.option_enable(cmd, opt_print_formal_verification_top_netlist)); - options.set_print_preconfig_top_testbench(cmd_context.option_enable(cmd, opt_print_preconfig_top_testbench)); options.set_fast_configuration(cmd_context.option_enable(cmd, opt_fast_configuration)); - options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench)); - options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini)); options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); - options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); - options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); + options.set_print_top_testbench(true); + options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); + if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { + options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); + } /* If pin constraints are enabled by command options, read the file */ PinConstraints pin_constraints; @@ -104,19 +103,174 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str()); } - return fpga_verilog_testbench(openfpga_ctx.module_graph(), - openfpga_ctx.bitstream_manager(), - openfpga_ctx.fabric_bitstream(), - g_vpr_ctx.atom(), - g_vpr_ctx.placement(), - pin_constraints, - openfpga_ctx.io_location_map(), - openfpga_ctx.fabric_global_port_info(), - openfpga_ctx.vpr_netlist_annotation(), - openfpga_ctx.arch().circuit_lib, - openfpga_ctx.simulation_setting(), - openfpga_ctx.arch().config_protocol, - options); + return fpga_verilog_full_testbench(openfpga_ctx.module_graph(), + openfpga_ctx.bitstream_manager(), + openfpga_ctx.fabric_bitstream(), + g_vpr_ctx.atom(), + g_vpr_ctx.placement(), + pin_constraints, + cmd_context.option_value(cmd, opt_bitstream), + openfpga_ctx.io_location_map(), + openfpga_ctx.fabric_global_port_info(), + openfpga_ctx.vpr_netlist_annotation(), + openfpga_ctx.arch().circuit_lib, + openfpga_ctx.simulation_setting(), + openfpga_ctx.arch().config_protocol, + options); +} + +/******************************************************************** + * A wrapper function to call the preconfigured wrapper generator of FPGA-Verilog + *******************************************************************/ +int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_output_dir = cmd.option("file"); + CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); + CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); + CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_default_net_type = cmd.option("default_net_type"); + CommandOptionId opt_include_signal_init = cmd.option("include_signal_init"); + CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream"); + CommandOptionId opt_verbose = cmd.option("verbose"); + + /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog + * Keep it independent from any other outside data structures + */ + VerilogTestbenchOption options; + options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); + options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); + options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); + options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); + options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init)); + options.set_print_formal_verification_top_netlist(true); + + if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { + options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); + } + + if (true == cmd_context.option_enable(cmd, opt_embed_bitstream)) { + options.set_embedded_bitstream_hdl_type(cmd_context.option_value(cmd, opt_embed_bitstream)); + } + + /* If pin constraints are enabled by command options, read the file */ + PinConstraints pin_constraints; + if (true == cmd_context.option_enable(cmd, opt_pcf)) { + pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str()); + } + + return fpga_verilog_preconfigured_fabric_wrapper(openfpga_ctx.module_graph(), + openfpga_ctx.bitstream_manager(), + g_vpr_ctx.atom(), + g_vpr_ctx.placement(), + pin_constraints, + openfpga_ctx.io_location_map(), + openfpga_ctx.fabric_global_port_info(), + openfpga_ctx.vpr_netlist_annotation(), + openfpga_ctx.arch().circuit_lib, + openfpga_ctx.arch().config_protocol, + options); +} + +/******************************************************************** + * A wrapper function to call the preconfigured testbench generator of FPGA-Verilog + *******************************************************************/ +int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_output_dir = cmd.option("file"); + CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); + CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); + CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); + CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); + CommandOptionId opt_default_net_type = cmd.option("default_net_type"); + CommandOptionId opt_verbose = cmd.option("verbose"); + + /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog + * Keep it independent from any other outside data structures + */ + VerilogTestbenchOption options; + options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); + options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist)); + options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); + options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); + options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); + options.set_print_preconfig_top_testbench(true); + if (true == cmd_context.option_enable(cmd, opt_default_net_type)) { + options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type)); + } + + /* If pin constraints are enabled by command options, read the file */ + PinConstraints pin_constraints; + if (true == cmd_context.option_enable(cmd, opt_pcf)) { + pin_constraints = read_xml_pin_constraints(cmd_context.option_value(cmd, opt_pcf).c_str()); + } + + return fpga_verilog_preconfigured_testbench(openfpga_ctx.module_graph(), + g_vpr_ctx.atom(), + pin_constraints, + openfpga_ctx.fabric_global_port_info(), + openfpga_ctx.vpr_netlist_annotation(), + openfpga_ctx.simulation_setting(), + options); +} + +/******************************************************************** + * A wrapper function to call the simulation task information generator of FPGA-Verilog + *******************************************************************/ +int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context) { + + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_hdl_dir = cmd.option("hdl_dir"); + CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path"); + CommandOptionId opt_tb_type = cmd.option("testbench_type"); + CommandOptionId opt_time_unit = cmd.option("time_unit"); + CommandOptionId opt_verbose = cmd.option("verbose"); + + /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog + * Keep it independent from any other outside data structures + */ + VerilogTestbenchOption options; + options.set_output_directory(cmd_context.option_value(cmd, opt_hdl_dir)); + options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark)); + options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); + options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_file)); + + if (true == cmd_context.option_enable(cmd, opt_time_unit)) { + options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit))); + } + + /* Identify testbench type */ + std::string full_tb_tag("full_testbench"); + std::string preconfig_tb_tag("preconfigured_testbench"); + if (true == cmd_context.option_enable(cmd, opt_tb_type)) { + if (std::string("preconfigured_testbench") == cmd_context.option_value(cmd, opt_tb_type)) { + options.set_print_preconfig_top_testbench(true); + } else if (std::string("full_testbench") == cmd_context.option_value(cmd, opt_tb_type)) { + options.set_print_preconfig_top_testbench(false); + options.set_print_top_testbench(true); + } else { + /* Invalid option, error out */ + VTR_LOG_ERROR("Invalid option value for testbench type: '%s'! Should be either '%s' or '%s'\n", + cmd_context.option_value(cmd, opt_tb_type).c_str(), + full_tb_tag.c_str(), + preconfig_tb_tag.c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } else { + /* Deposit default type which is the preconfigured testbench */ + options.set_print_preconfig_top_testbench(true); + } + + return fpga_verilog_simulation_task_info(openfpga_ctx.module_graph(), + openfpga_ctx.bitstream_manager(), + g_vpr_ctx.atom(), + g_vpr_ctx.placement(), + openfpga_ctx.io_location_map(), + openfpga_ctx.simulation_setting(), + openfpga_ctx.arch().config_protocol, + options); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h index 096039aab..3bbd7fab3 100644 --- a/openfpga/src/base/openfpga_verilog.h +++ b/openfpga/src/base/openfpga_verilog.h @@ -18,8 +18,17 @@ namespace openfpga { int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context); -int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, - const Command& cmd, const CommandContext& cmd_context); +int write_full_testbench(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + +int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + +int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); + +int write_simulation_task_info(const OpenfpgaContext& openfpga_ctx, + const Command& cmd, const CommandContext& cmd_context); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp index 946f0e2bf..165a0eb38 100644 --- a/openfpga/src/base/openfpga_verilog_command.cpp +++ b/openfpga/src/base/openfpga_verilog_command.cpp @@ -55,23 +55,139 @@ ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_full_testbench"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--bitstream'*/ + CommandOptionId bitstream_opt = shell_cmd.add_option("bitstream", true, "specify the bitstream to be loaded in the testbench"); + shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "specify the file path to the reference verilog netlist. If specified, the testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* add an option '--fast_configuration' */ + shell_cmd.add_option("fast_configuration", false, "reduce the period of configuration by skip certain data points"); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING); + + /* Add an option '--no_self_checking' */ + shell_cmd.add_option("no_self_checking", false, "Do not generate self-checking codes for Verilog testbenches."); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate full testbenches for an fpga fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_full_testbench); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - add a command to shell environment: write preconfigured fabric wrapper + * - add associated options + * - add command dependency + *******************************************************************/ +static +ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_preconfigured_fabric_wrapper"); + + /* add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option("file", true, "specify the output directory for hdl netlists"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist"); + shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); + + /* add an option '--pin_constraints_file in short '-pcf' */ + CommandOptionId pcf_opt = shell_cmd.add_option("pin_constraints_file", false, "specify the file path to the pin constraints"); + shell_cmd.set_option_short_name(pcf_opt, "pcf"); + shell_cmd.set_option_require_value(pcf_opt, openfpga::OPT_STRING); + + /* add an option '--explicit_port_mapping' */ + shell_cmd.add_option("explicit_port_mapping", false, "use explicit port mapping in verilog netlists"); + + /* Add an option '--default_net_type' */ + CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'"); + shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING); + + /* Add an option '--embed_bitstream' */ + CommandOptionId embed_bitstream_opt = shell_cmd.add_option("embed_bitstream", false, "Embed bitstream to the Verilog wrapper netlist; This may cause a large netlist file size"); + shell_cmd.set_option_require_value(embed_bitstream_opt, openfpga::OPT_STRING); + + /* add an option '--include_signal_init' */ + shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches"); + + /* add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "enable verbose output"); + + /* add command to the shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate a wrapper for a pre-configured fpga fabric"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_preconfigured_fabric_wrapper); + + /* add command dependency to the shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + +/******************************************************************** + * - Add a command to Shell environment: write preconfigured testbench * - Add associated options * - Add command dependency *******************************************************************/ static -ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell& shell, - const ShellCommandClassId& cmd_class_id, - const std::vector& dependent_cmds) { - Command shell_cmd("write_verilog_testbench"); +ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_preconfigured_testbench"); /* Add an option '--file' in short '-f'*/ - CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists"); + CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for HDL netlists"); shell_cmd.set_option_short_name(output_opt, "f"); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); - /* Add an option '--fabric_netlist_file_path'*/ - CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "Specify the file path to the fabric Verilog netlist"); + /* add an option '--fabric_netlist_file_path'*/ + CommandOptionId fabric_netlist_opt = shell_cmd.add_option("fabric_netlist_file_path", false, "specify the file path to the fabric hdl netlist"); shell_cmd.set_option_require_value(fabric_netlist_opt, openfpga::OPT_STRING); /* Add an option '--pin_constraints_file in short '-pcf' */ @@ -80,41 +196,69 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell& shell, + const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds) { + Command shell_cmd("write_simulation_task_info"); + + /* Add an option '--file' in short '-f'*/ + CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the file path to output simulation-related information"); + shell_cmd.set_option_short_name(output_opt, "f"); + shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); + + /* Add an option '--hdl_dir'*/ + CommandOptionId hdl_dir_opt = shell_cmd.add_option("hdl_dir", true, "Specify the directory path where HDL netlists are created"); + shell_cmd.set_option_require_value(hdl_dir_opt, openfpga::OPT_STRING); + + /* Add an option '--reference_benchmark_file_path'*/ + CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", false, "Specify the file path to the reference Verilog netlist. If specified, the testbench will include self-checking codes"); + shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING); + + /* Add an option '--testbench_type'*/ + CommandOptionId tb_type_opt = shell_cmd.add_option("testbench_type", false, "Specify the type of testbenches to be considered. Different testbenches have different simulation parameters."); + shell_cmd.set_option_require_value(tb_type_opt, openfpga::OPT_STRING); + + /* Add an option '--time_unit' */ + CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit to be used in HDL simulation. Acceptable is [a|f|p|n|u|m|k|M]s"); + shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Enable verbose output"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate an interchangable simulation task configuration file"); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info); /* Add command dependency to the Shell */ shell.set_command_dependency(shell_cmd_id, dependent_cmds); @@ -140,14 +284,44 @@ void add_openfpga_verilog_commands(openfpga::Shell& shell) { fabric_verilog_dependent_cmds); /******************************** - * Command 'write_verilog_testbench' + * Command 'write_full_testbench' */ - /* The command 'write_verilog_testbench' should NOT be executed before 'build_fabric' */ - std::vector verilog_testbench_dependent_cmds; - verilog_testbench_dependent_cmds.push_back(build_fabric_cmd_id); - add_openfpga_write_verilog_testbench_command(shell, - openfpga_verilog_cmd_class, - verilog_testbench_dependent_cmds); + /* The command 'write_full_testbench' should NOT be executed before 'build_fabric' */ + std::vector full_testbench_dependent_cmds; + full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_openfpga_write_full_testbench_command(shell, + openfpga_verilog_cmd_class, + full_testbench_dependent_cmds); + + /******************************** + * Command 'write_preconfigured_fabric_wrapper' + */ + /* The command 'write_preconfigured_fabric_wrapper' should NOT be executed before 'build_fabric' */ + std::vector preconfig_wrapper_dependent_cmds; + preconfig_wrapper_dependent_cmds.push_back(build_fabric_cmd_id); + add_openfpga_write_preconfigured_fabric_wrapper_command(shell, + openfpga_verilog_cmd_class, + preconfig_wrapper_dependent_cmds); + + /******************************** + * Command 'write_preconfigured_testbench' + */ + /* The command 'write_preconfigured_testbench' should NOT be executed before 'build_fabric' */ + std::vector preconfig_testbench_dependent_cmds; + preconfig_testbench_dependent_cmds.push_back(build_fabric_cmd_id); + add_openfpga_write_preconfigured_testbench_command(shell, + openfpga_verilog_cmd_class, + preconfig_testbench_dependent_cmds); + + /******************************** + * Command 'write_simulation_task_info' + */ + /* The command 'write_simulation_task_info' should NOT be executed before 'build_fabric' */ + std::vector sim_task_info_dependent_cmds; + sim_task_info_dependent_cmds.push_back(build_fabric_cmd_id); + add_openfpga_write_simulation_task_info_command(shell, + openfpga_verilog_cmd_class, + sim_task_info_dependent_cmds); } } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 0df7c4aa7..4b39a5cee 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -113,6 +113,7 @@ int build_device_module_graph(ModuleManager& module_manager, status = build_top_module(module_manager, decoder_lib, openfpga_ctx.arch().circuit_lib, + openfpga_ctx.vpr_device_annotation(), vpr_device_ctx.grid, openfpga_ctx.arch().tile_annotations, vpr_device_ctx.rr_graph, diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 3efc7b011..0054808a9 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -55,6 +55,7 @@ namespace openfpga { *******************************************************************/ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -87,6 +88,11 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, /* Reach here, it means this pin is on this side */ int class_id = grid_type_descriptor->pin_class[ipin]; e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; + + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); /* Generate the pin name * For each RECEIVER PIN or DRIVER PIN for direct connection, * we do not duplicate in these cases */ @@ -94,8 +100,7 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, /* Xifan: I assume that each direct connection pin must have Fc=0. */ || ( (DRIVER == pin_class_type) && (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) { - vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false); + std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info); BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); @@ -105,12 +110,12 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, * The other with a postfix of lower, indicating it is located on the lower part of a side */ VTR_ASSERT(DRIVER == pin_class_type); - std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, true); + std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, true); BasicPort grid_upper_port(upper_port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]); - std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, false); + std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, false); BasicPort grid_lower_port(lower_port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]); @@ -134,6 +139,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, @@ -162,6 +168,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index]; int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index]; + + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + for (const e_side& side : grid_pin_sides) { if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) { continue; @@ -175,8 +187,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m /* Create a net to connect the grid pin to child module pin */ ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the port in grid_module */ - vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false); + std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info); ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); @@ -200,12 +211,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m /* Create a net to connect the grid pin to child module pin */ ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the upper port in grid_module */ - std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, true); + std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, true); ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id)); /* Find the lower port in grid_module */ - std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, false); + std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, false); ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id)); @@ -238,6 +249,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -251,6 +263,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->input_pins[iport][ipin]), border_side, @@ -263,6 +276,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, @@ -274,6 +288,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->clock_pins[iport][ipin]), border_side, diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.h b/openfpga/src/fabric/build_grid_module_duplicated_pins.h index 2bdd56dea..f60aaf1c7 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.h +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.h @@ -6,6 +6,7 @@ *******************************************************************/ #include "physical_types.h" #include "module_manager.h" +#include "vpr_device_annotation.h" #include "openfpga_side_manager.h" /******************************************************************** @@ -17,6 +18,7 @@ namespace openfpga { void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); @@ -24,6 +26,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side); diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 60e44a435..a206cbdc0 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -46,6 +46,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, @@ -78,8 +79,11 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, /* Create a net to connect the grid pin to child module pin */ ModuleNetId net = module_manager.create_module_net(grid_module); /* Find the port in grid_module */ - vtr::Point dummy_coordinate; - std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false); + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info); ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); /* Grid port always has only 1 pin, it is assumed when adding these ports to the module diff --git a/openfpga/src/fabric/build_grid_module_utils.h b/openfpga/src/fabric/build_grid_module_utils.h index cf7b2d2d6..5a2a17490 100644 --- a/openfpga/src/fabric/build_grid_module_utils.h +++ b/openfpga/src/fabric/build_grid_module_utils.h @@ -9,6 +9,7 @@ #include "openfpga_interconnect_types.h" #include "module_manager.h" +#include "vpr_device_annotation.h" /******************************************************************** * Function declaration @@ -24,6 +25,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, t_pb_graph_pin* pb_graph_pin, const e_side& border_side, diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index f9af7d722..f1a56c4f1 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -41,6 +41,7 @@ namespace openfpga { static void add_grid_module_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -76,8 +77,11 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager, /* Generate the pin name, * we give a empty coordinate but it will not be used (see details in the function */ - vtr::Point dummy_coordinate; - std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false); + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info); BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]); @@ -99,6 +103,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, const ModuleId& grid_module, const ModuleId& child_module, const size_t& child_instance, + const VprDeviceAnnotation& vpr_device_annotation, t_physical_tile_type_ptr grid_type_descriptor, const e_side& border_side) { /* Ensure that we have a valid grid_type_descriptor */ @@ -112,6 +117,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->input_pins[iport][ipin]), border_side, @@ -124,6 +130,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->output_pins[iport][ipin]), border_side, @@ -135,6 +142,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager, for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) { add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module, child_module, child_instance, + vpr_device_annotation, grid_type_descriptor, &(top_pb_graph_node->clock_pins[iport][ipin]), border_side, @@ -974,6 +982,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager, static void build_physical_tile_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, + const VprDeviceAnnotation& vpr_device_annotation, const CircuitLibrary& circuit_lib, const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, @@ -1035,6 +1044,7 @@ void build_physical_tile_module(ModuleManager& module_manager, if (false == duplicate_grid_pin) { /* Default way to add these ports by following the definition in pb_types */ add_grid_module_pb_type_ports(module_manager, grid_module, + vpr_device_annotation, phy_block_type, border_side); /* Add module nets to connect the pb_type ports to sub modules */ for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) { @@ -1048,6 +1058,7 @@ void build_physical_tile_module(ModuleManager& module_manager, for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, pb_module, child_instance, + vpr_device_annotation, phy_block_type, border_side); } } @@ -1055,6 +1066,7 @@ void build_physical_tile_module(ModuleManager& module_manager, VTR_ASSERT_SAFE(true == duplicate_grid_pin); /* Add these ports with duplication */ add_grid_module_duplicated_pb_type_ports(module_manager, grid_module, + vpr_device_annotation, phy_block_type, border_side); /* Add module nets to connect the duplicated pb_type ports to sub modules */ @@ -1069,6 +1081,7 @@ void build_physical_tile_module(ModuleManager& module_manager, for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module, pb_module, child_instance, + vpr_device_annotation, phy_block_type, border_side); } } @@ -1186,6 +1199,7 @@ void build_grid_modules(ModuleManager& module_manager, &physical_tile); for (const e_side& io_type_side : io_type_sides) { build_physical_tile_module(module_manager, decoder_lib, + device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, @@ -1196,6 +1210,7 @@ void build_grid_modules(ModuleManager& module_manager, } else { /* For CLB and heterogenenous blocks */ build_physical_tile_module(module_manager, decoder_lib, + device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, diff --git a/openfpga/src/fabric/build_routing_module_utils.cpp b/openfpga/src/fabric/build_routing_module_utils.cpp index 320823ec2..86b52228d 100644 --- a/openfpga/src/fabric/build_routing_module_utils.cpp +++ b/openfpga/src/fabric/build_routing_module_utils.cpp @@ -10,6 +10,7 @@ #include "vtr_assert.h" #include "vtr_geometry.h" +#include "openfpga_side_manager.h" #include "openfpga_naming.h" #include "build_routing_module_utils.h" @@ -17,6 +18,104 @@ /* begin namespace openfpga */ namespace openfpga { +/********************************************************************* + * Generate the port name of a grid pin for a routing module, + * which could be a switch block or a connection block + * Note that to ensure unique grid port name in the context of a routing module, + * we need a prefix which denotes the relative location of the port in the routing module + * + * The prefix is created by considering the the grid coordinate + * and switch block coordinate + * Detailed rules in conversion is as follows: + * + * top_left top_right + * +------------------------+ + * left_top | | right_top + * | Switch Block | + * | [x][y] | + * | | + * | | + * left_right | | right_bottom + * +------------------------+ + * bottom_left bottom_right + * + * +-------------------------------------------------------- + * | Grid Coordinate | Pin side of grid | module side + * +-------------------------------------------------------- + * | [x][y+1] | right | top_left + * +-------------------------------------------------------- + * | [x][y+1] | bottom | left_top + * +-------------------------------------------------------- + * | [x+1][y+1] | left | top_right + * +-------------------------------------------------------- + * | [x+1][y+1] | bottom | right_top + * +-------------------------------------------------------- + * | [x][y] | top | left_right + * +-------------------------------------------------------- + * | [x][y] | right | bottom_left + * +-------------------------------------------------------- + * | [x+1][y] | top | right_bottom + * +-------------------------------------------------------- + * | [x+1][y] | left | bottom_right + * +-------------------------------------------------------- + * + *********************************************************************/ +std::string generate_sb_module_grid_port_name(const e_side& sb_side, + const e_side& grid_side, + const DeviceGrid& vpr_device_grid, + const VprDeviceAnnotation& vpr_device_annotation, + const RRGraph& rr_graph, + const RRNodeId& rr_node) { + SideManager sb_side_manager(sb_side); + SideManager grid_side_manager(grid_side); + /* Relative location is opposite to the side in grid context */ + grid_side_manager.set_opposite(); + std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string(); + + /* Collect the attributes of the rr_node required to generate the port name */ + int pin_id = rr_graph.node_pin_num(rr_node); + e_side pin_side = rr_graph.node_side(rr_node); + t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type; + int pin_width_offset = physical_tile->pin_width_offset[pin_id]; + int pin_height_offset = physical_tile->pin_height_offset[pin_id]; + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id); + VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity); + + return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info); +} + +/********************************************************************* + * Generate the port name of a grid pin for a routing module, + * which could be a switch block or a connection block + * Note that to ensure unique grid port name in the context of a routing module, + * we need a prefix which denotes the relative location of the port in the routing module + *********************************************************************/ +std::string generate_cb_module_grid_port_name(const e_side& cb_side, + const DeviceGrid& vpr_device_grid, + const VprDeviceAnnotation& vpr_device_annotation, + const RRGraph& rr_graph, + const RRNodeId& rr_node) { + + SideManager side_manager(cb_side); + std::string prefix = side_manager.to_string(); + + /* Collect the attributes of the rr_node required to generate the port name */ + int pin_id = rr_graph.node_pin_num(rr_node); + e_side pin_side = rr_graph.node_side(rr_node); + t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type; + int pin_width_offset = physical_tile->pin_width_offset[pin_id]; + int pin_height_offset = physical_tile->pin_height_offset[pin_id]; + BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id); + VTR_ASSERT(true == pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id); + VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity); + + return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info); +} + + /********************************************************************* * Find the port id and pin id for a routing track in the switch * block module with a given rr_node @@ -64,6 +163,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man ********************************************************************/ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager, const ModuleId& sb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const e_side& input_side, @@ -84,7 +185,10 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma std::string input_port_name = generate_sb_module_grid_port_name(input_side, grid_pin_side, - rr_graph.node_pin_num(input_rr_node)); + grids, + vpr_device_annotation, + rr_graph, + input_rr_node); /* Must find a valid port id in the Switch Block module */ input_port.first = module_manager.find_module_port(sb_module, input_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port.first)); @@ -109,6 +213,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma ********************************************************************/ std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, const ModuleId& sb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const std::vector& input_rr_nodes) { @@ -123,7 +229,7 @@ std::vector find_switch_block_module_input_ports(const ModuleMana VTR_ASSERT(NUM_SIDES != input_pin_side); VTR_ASSERT(-1 != index); - input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, input_rr_node)); + input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, grids, vpr_device_annotation, rr_graph, rr_gsb, input_pin_side, input_rr_node)); } return input_ports; @@ -169,6 +275,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module ********************************************************************/ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const RRNodeId& src_rr_node) { @@ -184,7 +292,10 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_ /* We need to be sure that drive_rr_node is part of the CB */ VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side)); std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_graph.node_pin_num(rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index))); + grids, + vpr_device_annotation, + rr_graph, + rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)); /* Must find a valid port id in the Switch Block module */ ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); diff --git a/openfpga/src/fabric/build_routing_module_utils.h b/openfpga/src/fabric/build_routing_module_utils.h index 3684a5d8b..446d159e9 100644 --- a/openfpga/src/fabric/build_routing_module_utils.h +++ b/openfpga/src/fabric/build_routing_module_utils.h @@ -10,6 +10,8 @@ #include "rr_gsb.h" #include "module_manager.h" #include "vpr_types.h" +#include "device_grid.h" +#include "vpr_device_annotation.h" /******************************************************************** * Function declaration @@ -20,6 +22,19 @@ namespace openfpga { typedef std::pair ModulePinInfo; +std::string generate_sb_module_grid_port_name(const e_side& sb_side, + const e_side& grid_side, + const DeviceGrid& vpr_device_grid, + const VprDeviceAnnotation& vpr_device_annotation, + const RRGraph& rr_graph, + const RRNodeId& rr_node); + +std::string generate_cb_module_grid_port_name(const e_side& cb_side, + const DeviceGrid& vpr_device_grid, + const VprDeviceAnnotation& vpr_device_annotation, + const RRGraph& rr_graph, + const RRNodeId& rr_node); + ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager, const ModuleId& sb_module, const RRGraph& rr_graph, @@ -30,6 +45,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager, const ModuleId& sb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const e_side& input_side, @@ -37,6 +54,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma std::vector find_switch_block_module_input_ports(const ModuleManager& module_manager, const ModuleId& sb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const std::vector& input_rr_nodes); @@ -50,6 +69,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager, const ModuleId& cb_module, + const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const RRGraph& rr_graph, const RRGSB& rr_gsb, const RRNodeId& src_rr_node); diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp index 46d9d2858..2996d8d23 100644 --- a/openfpga/src/fabric/build_routing_modules.cpp +++ b/openfpga/src/fabric/build_routing_modules.cpp @@ -42,6 +42,8 @@ namespace openfpga { static void build_switch_block_module_short_interc(ModuleManager& module_manager, const ModuleId& sb_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const e_side& chan_side, @@ -81,7 +83,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager, exit(1); } /* Find the name of input port */ - ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node); + ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, input_pin_side, drive_rr_node); /* The input port and output port must match in size */ BasicPort input_port = module_manager.module_port(sb_module, input_port_info.first); @@ -102,6 +104,7 @@ static void build_switch_block_mux_module(ModuleManager& module_manager, const ModuleId& sb_module, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const CircuitLibrary& circuit_lib, @@ -137,7 +140,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager, module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name); /* Generate input ports that are wired to the input bus of the routing multiplexer */ - std::vector sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes); + std::vector sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, driver_rr_nodes); /* Link input bus port to Switch Block inputs */ std::vector mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true); @@ -211,6 +214,7 @@ static void build_switch_block_interc_modules(ModuleManager& module_manager, const ModuleId& sb_module, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const CircuitLibrary& circuit_lib, @@ -234,6 +238,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, if (0 == driver_rr_nodes.size()) { /* Print a special direct connection*/ build_switch_block_module_short_interc(module_manager, sb_module, + device_annotation, + grids, rr_graph, rr_gsb, chan_side, cur_rr_node, cur_rr_node, @@ -241,6 +247,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, } else if (1 == driver_rr_nodes.size()) { /* Print a direct connection*/ build_switch_block_module_short_interc(module_manager, sb_module, + device_annotation, + grids, rr_graph, rr_gsb, chan_side, cur_rr_node, driver_rr_nodes[0], input_port_to_module_nets); @@ -249,7 +257,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager, std::vector driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node); VTR_ASSERT(1 == driver_switches.size()); build_switch_block_mux_module(module_manager, - sb_module, device_annotation, rr_graph, rr_gsb, + sb_module, device_annotation, + grids, rr_graph, rr_gsb, circuit_lib, chan_side, chan_node_id, cur_rr_node, driver_rr_nodes, @@ -327,6 +336,7 @@ static void build_switch_block_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const CircuitLibrary& circuit_lib, const e_config_protocol_type& sram_orgz_type, @@ -400,7 +410,10 @@ void build_switch_block_module(ModuleManager& module_manager, rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode))); std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode))); + grids, + device_annotation, + rr_graph, + rr_gsb.get_opin_node(side_manager.get_side(), inode)); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT); @@ -418,7 +431,8 @@ void build_switch_block_module(ModuleManager& module_manager, /* We care OUTPUT tracks at this time only */ if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { build_switch_block_interc_modules(module_manager, - sb_module, device_annotation, rr_graph, rr_gsb, + sb_module, device_annotation, + grids, rr_graph, rr_gsb, circuit_lib, side_manager.get_side(), itrack, @@ -469,6 +483,8 @@ void build_switch_block_module(ModuleManager& module_manager, static void build_connection_block_module_short_interc(ModuleManager& module_manager, const ModuleId& cb_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -507,7 +523,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager, ModulePinInfo input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node); /* Create port description for input pin of a CLB */ - ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node); + ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, src_rr_node); /* The input port and output port must match in size */ BasicPort input_port = module_manager.module_port(cb_module, input_port_info.first); @@ -529,6 +545,7 @@ static void build_connection_block_mux_module(ModuleManager& module_manager, const ModuleId& cb_module, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -595,7 +612,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager, ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0])); VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id)); BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id); - ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, cur_rr_node); + ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, cur_rr_node); BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id); /* Check port size should match */ @@ -642,6 +659,7 @@ static void build_connection_block_interc_modules(ModuleManager& module_manager, const ModuleId& cb_module, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -655,13 +673,13 @@ void build_connection_block_interc_modules(ModuleManager& module_manager, return; /* This port has no driver, skip it */ } else if (1 == rr_graph.node_in_edges(src_rr_node).size()) { /* Print a direct connection */ - build_connection_block_module_short_interc(module_manager, cb_module, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets); + build_connection_block_module_short_interc(module_manager, cb_module, device_annotation, grids, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets); } else if (1 < rr_graph.node_in_edges(src_rr_node).size()) { /* Print the multiplexer, fan_in >= 2 */ build_connection_block_mux_module(module_manager, cb_module, device_annotation, - rr_graph, rr_gsb, cb_type, + grids, rr_graph, rr_gsb, cb_type, circuit_lib, cb_ipin_side, ipin_index, input_port_to_module_nets); @@ -726,6 +744,7 @@ static void build_connection_block_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const CircuitLibrary& circuit_lib, const e_config_protocol_type& sram_orgz_type, @@ -799,7 +818,10 @@ void build_connection_block_module(ModuleManager& module_manager, const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); vtr::Point port_coord(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node)); std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_graph.node_pin_num(ipin_node)); + grids, + device_annotation, + rr_graph, + ipin_node); BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */ /* Grid outputs are inputs of switch blocks */ module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT); @@ -838,6 +860,7 @@ void build_connection_block_module(ModuleManager& module_manager, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { build_connection_block_interc_modules(module_manager, cb_module, device_annotation, + grids, rr_graph, rr_gsb, cb_type, circuit_lib, @@ -914,6 +937,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager, build_connection_block_module(module_manager, decoder_lib, device_annotation, + device_ctx.grid, device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, @@ -956,6 +980,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager, build_switch_block_module(module_manager, decoder_lib, device_annotation, + device_ctx.grid, device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, @@ -1014,6 +1039,7 @@ void build_unique_routing_modules(ModuleManager& module_manager, build_switch_block_module(module_manager, decoder_lib, device_annotation, + device_ctx.grid, device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, @@ -1028,6 +1054,7 @@ void build_unique_routing_modules(ModuleManager& module_manager, build_connection_block_module(module_manager, decoder_lib, device_annotation, + device_ctx.grid, device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, @@ -1042,6 +1069,7 @@ void build_unique_routing_modules(ModuleManager& module_manager, build_connection_block_module(module_manager, decoder_lib, device_annotation, + device_ctx.grid, device_ctx.rr_graph, circuit_lib, sram_orgz_type, sram_model, diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 9e1bd7857..56b7d4b2b 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -284,6 +284,7 @@ vtr::Matrix add_top_module_connection_block_instances(ModuleManager& mod int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraph& rr_graph, @@ -329,11 +330,13 @@ int build_top_module(ModuleManager& module_manager, /* Add module nets to connect the sub modules */ add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids, compact_routing_hierarchy, duplicate_grid_pin); /* Add inter-CLB direct connections */ add_top_module_nets_tile_direct_connections(module_manager, top_module, circuit_lib, + vpr_device_annotation, grids, grid_instance_ids, tile_direct, arch_direct); } @@ -345,7 +348,7 @@ int build_top_module(ModuleManager& module_manager, add_module_global_ports_from_child_modules(module_manager, top_module); /* Add global ports from grid ports that are defined as global in tile annotation */ - status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, grids, grid_instance_ids); + status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, vpr_device_annotation, grids, grid_instance_ids); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 1905a3b1b..d7e90a09f 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -8,6 +8,7 @@ #include #include "vtr_geometry.h" #include "device_grid.h" +#include "vpr_device_annotation.h" #include "tile_annotation.h" #include "rr_graph_obj.h" #include "device_rr_gsb.h" @@ -29,6 +30,7 @@ namespace openfpga { int build_top_module(ModuleManager& module_manager, DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraph& rr_graph, diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 870d21340..03b04cd03 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -23,6 +23,7 @@ #include "openfpga_device_grid_utils.h" #include "module_manager_utils.h" +#include "build_routing_module_utils.h" #include "build_top_module_utils.h" #include "build_top_module_connection.h" @@ -64,6 +65,7 @@ namespace openfpga { static void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -112,11 +114,17 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)); - size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index]; - size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index]; - std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; + size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index]; + BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(true == src_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, false); + src_grid_pin_info); ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); @@ -124,10 +132,12 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, /* Collect sink-related information */ vtr::Point sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)), rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode))); - size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode)); std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)), - sink_grid_pin_index); + grids, + vpr_device_annotation, + rr_graph, + module_sb.get_opin_node(side_manager.get_side(), inode)); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); @@ -184,6 +194,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager, static void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -242,8 +253,15 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module)); size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)); - size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index]; - size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index]; + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index]; + size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index]; + + BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(true == src_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); /* Pins for direct connection are NOT duplicated. * Follow the traditional recipe when adding nets! @@ -251,14 +269,14 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager * For other duplicated pins, we follow the new naming */ std::string src_grid_port_name; - if (0. == find_physical_tile_pin_Fc(grids[grid_coordinate.x()][grid_coordinate.y()].type, src_grid_pin_index)) { - src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height, + if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, src_grid_pin_index)) { + src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, false); + src_grid_pin_info); } else { - src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, + src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)), - src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]); + src_grid_pin_info, sb_side2postfix_map[side_manager.get_side()]); } ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); @@ -267,10 +285,12 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager /* Collect sink-related information */ vtr::Point sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)), rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode))); - size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode)); std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)), - sink_grid_pin_index); + grids, + vpr_device_annotation, + rr_graph, + module_sb.get_opin_node(side_manager.get_side(), inode)); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id)); BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); @@ -346,6 +366,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager static void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -397,7 +418,10 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, vtr::Point cb_src_port_coord(rr_graph.node_xlow(module_ipin_node), rr_graph.node_ylow(module_ipin_node)); std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_graph.node_pin_num(module_ipin_node)); + grids, + vpr_device_annotation, + rr_graph, + module_ipin_node); ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id)); BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id); @@ -414,11 +438,17 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module)); size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); - size_t sink_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[sink_grid_pin_index]; - size_t sink_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[sink_grid_pin_index]; - std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height, + + t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type; + size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index]; + size_t sink_grid_pin_height = grid_type_descriptor->pin_height_offset[sink_grid_pin_index]; + BasicPort sink_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(true == sink_grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, sink_grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string sink_grid_port_name = generate_grid_port_name(sink_grid_pin_width, sink_grid_pin_height, subtile_index, rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)), - sink_grid_pin_index, false); + sink_grid_pin_info); ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id)); BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id); @@ -640,6 +670,7 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, *******************************************************************/ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -661,23 +692,27 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, /* Connect the grid pins of the GSB to adjacent grids */ if (false == duplicate_grid_pin) { add_top_module_nets_connect_grids_and_sb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } else { VTR_ASSERT_SAFE(true == duplicate_grid_pin); add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids, compact_routing_hierarchy); } add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX), compact_routing_hierarchy); add_top_module_nets_connect_grids_and_cb(module_manager, top_module, + vpr_device_annotation, grids, grid_instance_ids, rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY), compact_routing_hierarchy); @@ -701,6 +736,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Point& grid_coordinate, const e_side& border_side, @@ -711,6 +747,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana /* Find the port of the grid module according to the tile annotation */ int grid_pin_start_index = physical_tile->num_pins; t_physical_tile_port physical_tile_port; + physical_tile_port.num_pins = 0; for (const t_physical_tile_port& tile_port : physical_tile->ports) { if (std::string(tile_port.name) == tile_port_to_connect.get_name()) { BasicPort ref_tile_port(tile_port.name, tile_port.num_pins); @@ -757,12 +794,16 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index]; std::vector pin_sides = find_physical_tile_pin_side(physical_tile, grid_pin_index, border_side); + BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); + VTR_ASSERT(true == grid_pin_info.is_valid()); + int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, grid_pin_index); + VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity); + /* Build nets */ for (const e_side& pin_side : pin_sides) { - std::string grid_port_name = generate_grid_port_name(grid_coordinate, - grid_pin_width, grid_pin_height, + std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index, pin_side, - grid_pin_index, false); + grid_pin_info); ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id)); @@ -789,6 +830,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids) { int status = CMD_EXEC_SUCCESS; @@ -888,6 +930,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, tile_annotation, tile_global_port, tile_port, + vpr_device_annotation, grids, vtr::Point(ix, iy), NUM_SIDES, @@ -935,6 +978,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, tile_annotation, tile_global_port, tile_port, + vpr_device_annotation, grids, io_coordinate, io_side, diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index d400205d2..dd44455a6 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -11,6 +11,7 @@ #include "rr_graph_obj.h" #include "device_rr_gsb.h" #include "tile_annotation.h" +#include "vpr_device_annotation.h" #include "module_manager.h" /******************************************************************** @@ -22,6 +23,7 @@ namespace openfpga { void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const RRGraph& rr_graph, @@ -34,6 +36,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager, int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager, const ModuleId& top_module, const TileAnnotation& tile_annotation, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids); diff --git a/openfpga/src/fabric/build_top_module_directs.cpp b/openfpga/src/fabric/build_top_module_directs.cpp index 5f53fdd5b..a30b55959 100644 --- a/openfpga/src/fabric/build_top_module_directs.cpp +++ b/openfpga/src/fabric/build_top_module_directs.cpp @@ -41,6 +41,7 @@ static void add_module_nets_tile_direct_connection(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, @@ -92,9 +93,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, /* Generate the pin name of source port/pin in the grid */ e_side src_pin_grid_side = tile_direct.from_tile_side(tile_direct_id); size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id); - size_t src_pin_width = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_width_offset[src_tile_pin]; - size_t src_pin_height = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_height_offset[src_tile_pin]; - std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false); + + t_physical_tile_type_ptr src_grid_type_descriptor = grids[src_clb_coord.x()][src_clb_coord.y()].type; + size_t src_pin_width = src_grid_type_descriptor->pin_width_offset[src_tile_pin]; + size_t src_pin_height = src_grid_type_descriptor->pin_height_offset[src_tile_pin]; + + BasicPort src_pin_info = vpr_device_annotation.physical_tile_pin_port_info(src_grid_type_descriptor, src_tile_pin); + VTR_ASSERT(true == src_pin_info.is_valid()); + int src_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(src_grid_type_descriptor, src_tile_pin); + VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < src_grid_type_descriptor->capacity); + std::string src_port_name = generate_grid_port_name(src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info); ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name); if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) { VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n", @@ -107,10 +115,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, /* Generate the pin name of sink port/pin in the grid */ e_side sink_pin_grid_side = tile_direct.to_tile_side(tile_direct_id); size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id); - size_t sink_pin_width = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_width_offset[src_tile_pin]; - size_t sink_pin_height = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_height_offset[src_tile_pin]; - std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_pin_grid_side, sink_tile_pin, false); + t_physical_tile_type_ptr sink_grid_type_descriptor = grids[des_clb_coord.x()][des_clb_coord.y()].type; + size_t sink_pin_width = sink_grid_type_descriptor->pin_width_offset[src_tile_pin]; + size_t sink_pin_height = sink_grid_type_descriptor->pin_height_offset[src_tile_pin]; + + BasicPort sink_pin_info = vpr_device_annotation.physical_tile_pin_port_info(sink_grid_type_descriptor, sink_tile_pin); + VTR_ASSERT(true == sink_pin_info.is_valid()); + int sink_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(sink_grid_type_descriptor, sink_tile_pin); + VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < sink_grid_type_descriptor->capacity); + std::string sink_port_name = generate_grid_port_name(sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info); ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id)); VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width()); @@ -141,6 +155,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager, void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, @@ -150,6 +165,7 @@ void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, for (const TileDirectId& tile_direct_id : tile_direct.directs()) { add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib, + vpr_device_annotation, grids, grid_instance_ids, tile_direct, tile_direct_id, arch_direct); diff --git a/openfpga/src/fabric/build_top_module_directs.h b/openfpga/src/fabric/build_top_module_directs.h index e9855db70..aa46f0ec8 100644 --- a/openfpga/src/fabric/build_top_module_directs.h +++ b/openfpga/src/fabric/build_top_module_directs.h @@ -9,6 +9,7 @@ #include "vtr_ndmatrix.h" #include "arch_direct.h" #include "tile_direct.h" +#include "vpr_device_annotation.h" #include "device_grid.h" #include "module_manager.h" #include "circuit_library.h" @@ -23,6 +24,7 @@ namespace openfpga { void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const vtr::Matrix& grid_instance_ids, const TileDirect& tile_direct, diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 1fb2360e9..e90d73321 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -189,6 +189,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_clustering_annotation(), openfpga_ctx.vpr_placement_annotation(), + openfpga_ctx.vpr_bitstream_annotation(), verbose); VTR_LOGV(verbose, "Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index c7eca7aee..d5241a451 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -129,6 +129,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin, t_mode* physical_mode) { @@ -197,6 +198,12 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag } } + /* Overwrite the default path if defined in bitstream annotation */ + if ( (size_t(DEFAULT_PATH_ID) == mux_input_pin_id) + && (mux_input_pin_id != bitstream_annotation.interconnect_default_path_id(cur_interc)) ) { + mux_input_pin_id = bitstream_annotation.interconnect_default_path_id(cur_interc); + } + /* Generate bitstream depend on both technology and structure of this MUX */ std::vector mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, mux_input_pin_id); @@ -266,6 +273,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, const e_circuit_pb_port_type& pb_port_type, @@ -276,7 +284,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_input_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode); @@ -288,7 +296,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode); @@ -300,7 +308,7 @@ void build_physical_block_interc_port_bitstream(BitstreamManager& bitstream_mana for (int ipin = 0; ipin < physical_pb_graph_node->num_clock_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, physical_pb, &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode); @@ -327,6 +335,7 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, t_mode* physical_mode) { @@ -348,7 +357,7 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, */ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, physical_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode); @@ -367,13 +376,13 @@ void build_physical_block_interc_bitstream(BitstreamManager& bitstream_manager, /* For each child_pb_graph_node input pins*/ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode); /* For clock pins, we should do the same work */ build_physical_block_interc_port_bitstream(bitstream_manager, parent_configurable_block, module_manager, circuit_lib, mux_lib, - atom_ctx, device_annotation, + atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode); } @@ -448,18 +457,18 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager, /* If the physical pb contains fixed bitstream, overload here */ if (false == physical_pb.fixed_bitstream(lut_pb_id).empty()) { std::string fixed_bitstream = physical_pb.fixed_bitstream(lut_pb_id); + size_t start_index = physical_pb.fixed_bitstream_offset(lut_pb_id); /* Ensure the length matches!!! */ - if (lut_bitstream.size() != fixed_bitstream.size()) { - VTR_LOG_ERROR("Unmatched length of fixed bitstream %s!Expected to be %ld bits\n", + if (lut_bitstream.size() - start_index < fixed_bitstream.size()) { + VTR_LOG_ERROR("Unmatched length of fixed bitstream %s!Expected to be less than %ld bits\n", fixed_bitstream.c_str(), - lut_bitstream.size()); + lut_bitstream.size() - start_index); exit(1); } - /* Overload here */ - lut_bitstream.clear(); - for (const char& fixed_bit : fixed_bitstream) { - VTR_ASSERT('0' == fixed_bit || '1' == fixed_bit); - lut_bitstream.push_back('1' == fixed_bit); + /* Overload the bitstream here */ + for (size_t bit_index = 0; bit_index < lut_bitstream.size(); ++bit_index) { + VTR_ASSERT('0' == fixed_bitstream[bit_index] || '1' == fixed_bitstream[bit_index]); + lut_bitstream[bit_index + start_index] = ('1' == fixed_bitstream[bit_index]); } } } @@ -469,9 +478,29 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager, std::vector mode_select_bitstream; if (true == physical_pb.valid_pb_id(lut_pb_id)) { mode_select_bitstream = generate_mode_select_bitstream(physical_pb.mode_bits(lut_pb_id)); + + /* If the physical pb contains fixed mode-select bitstream, overload here */ + if (false == physical_pb.fixed_mode_select_bitstream(lut_pb_id).empty()) { + std::string fixed_mode_select_bitstream = physical_pb.fixed_mode_select_bitstream(lut_pb_id); + size_t mode_bits_start_index = physical_pb.fixed_mode_select_bitstream_offset(lut_pb_id); + /* Ensure the length matches!!! */ + if (mode_select_bitstream.size() - mode_bits_start_index < fixed_mode_select_bitstream.size()) { + VTR_LOG_ERROR("Unmatched length of fixed mode_select_bitstream %s!Expected to be less than %ld bits\n", + fixed_mode_select_bitstream.c_str(), + mode_select_bitstream.size() - mode_bits_start_index); + exit(1); + } + /* Overload the bitstream here */ + for (size_t bit_index = 0; bit_index < fixed_mode_select_bitstream.size(); ++bit_index) { + VTR_ASSERT('0' == fixed_mode_select_bitstream[bit_index] || '1' == fixed_mode_select_bitstream[bit_index]); + mode_select_bitstream[bit_index + mode_bits_start_index] = ('1' == fixed_mode_select_bitstream[bit_index]); + } + + } } else { /* get default mode_bits */ mode_select_bitstream = generate_mode_select_bitstream(device_annotation.pb_type_mode_bits(lut_pb_type)); } + /* Conjunct the mode-select bitstream to the lut bitstream */ for (const bool& bit : mode_select_bitstream) { lut_bitstream.push_back(bit); @@ -514,6 +543,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, const MuxLibrary& mux_lib, const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const e_side& border_side, const PhysicalPb& physical_pb, const PhysicalPbId& pb_id, @@ -558,7 +588,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, rec_build_physical_block_bitstream(bitstream_manager, pb_configurable_block, module_manager, circuit_lib, mux_lib, atom_ctx, - device_annotation, + device_annotation, bitstream_annotation, border_side, physical_pb, child_pb, &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), @@ -603,7 +633,7 @@ void rec_build_physical_block_bitstream(BitstreamManager& bitstream_manager, build_physical_block_interc_bitstream(bitstream_manager, pb_configurable_block, module_manager, circuit_lib, mux_lib, atom_ctx, - device_annotation, + device_annotation, bitstream_annotation, physical_pb_graph_node, physical_pb, physical_mode); } @@ -624,6 +654,7 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids, const vtr::Point& grid_coord, const e_side& border_side) { @@ -672,7 +703,8 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, module_manager, circuit_lib, mux_lib, atom_ctx, - device_annotation, border_side, + device_annotation, bitstream_annotation, + border_side, PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z); } else { @@ -687,7 +719,8 @@ void build_physical_block_bitstream(BitstreamManager& bitstream_manager, rec_build_physical_block_bitstream(bitstream_manager, grid_configurable_block, module_manager, circuit_lib, mux_lib, atom_ctx, - device_annotation, border_side, + device_annotation, bitstream_annotation, + border_side, phy_pb, top_pb_id, pb_graph_head, z); } } @@ -711,6 +744,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) { VTR_LOGV(verbose, "Generating bitstream for core grids..."); @@ -733,7 +767,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, + place_annotation, bitstream_annotation, grids, grid_coord, NUM_SIDES); } } @@ -760,7 +794,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, + place_annotation, bitstream_annotation, grids, io_coordinate, io_side); } } diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index be2425c5a..9d2c3d010 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -14,6 +14,7 @@ #include "vpr_device_annotation.h" #include "vpr_clustering_annotation.h" #include "vpr_placement_annotation.h" +#include "vpr_bitstream_annotation.h" /******************************************************************** * Function declaration @@ -32,6 +33,7 @@ void build_grid_bitstream(BitstreamManager& bitstream_manager, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, + const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp new file mode 100644 index 000000000..3eb10fe37 --- /dev/null +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.cpp @@ -0,0 +1,156 @@ +/******************************************************************** + * This file includes functions that build io mapping information + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from archopenfpga library */ +#include "openfpga_naming.h" + +#include "module_manager_utils.h" +#include "build_io_mapping_info.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function + * - builds the net-to-I/O mapping + * - identifies each I/O directionality + * - return a database containing the above information + * + * TODO: This function duplicates codes from + * function: print_verilog_testbench_connect_fpga_ios() in + * source file: verilog_testbench_utils.cpp + * Should consider how to merge the codes and share same builder function + *******************************************************************/ +IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager, + const ModuleId& top_module, + const AtomContext& atom_ctx, + const PlacementContext& place_ctx, + const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& output_port_prefix_to_remove) { + IoMap io_map; + + /* Only mappable i/o ports can be considered */ + std::vector module_io_ports; + for (const ModuleManager::e_module_port_type& module_io_port_type : MODULE_IO_PORT_TYPES) { + for (const ModulePortId& gpio_port_id : module_manager.module_port_ids_by_type(top_module, module_io_port_type)) { + /* Only care mappable I/O */ + if (false == module_manager.port_is_mappable_io(top_module, gpio_port_id)) { + continue; + } + module_io_ports.push_back(gpio_port_id); + } + } + + /* Type mapping between VPR block and Module port */ + std::map atom_block_type_to_module_port_type; + atom_block_type_to_module_port_type[AtomBlockType::INPAD] = ModuleManager::MODULE_GPIN_PORT; + atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] = ModuleManager::MODULE_GPOUT_PORT; + + /* Type mapping between VPR block and io mapping direction */ + std::map atom_block_type_to_io_map_direction; + atom_block_type_to_io_map_direction[AtomBlockType::INPAD] = IoMap::IO_MAP_DIR_INPUT; + atom_block_type_to_io_map_direction[AtomBlockType::OUTPAD] = IoMap::IO_MAP_DIR_OUTPUT; + + for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { + /* Bypass non-I/O atom blocks ! */ + if ( (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) + && (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) ) { + continue; + } + + /* If there is a GPIO port, use it directly + * Otherwise, should find a GPIN for INPAD + * or should find a GPOUT for OUTPAD + */ + std::pair mapped_module_io_info = std::make_pair(ModulePortId::INVALID(), -1); + for (const ModulePortId& module_io_port_id : module_io_ports) { + const BasicPort& module_io_port = module_manager.module_port(top_module, module_io_port_id); + + /* Find the index of the mapped GPIO in top-level FPGA fabric */ + size_t temp_io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z, + module_io_port.get_name()); + + /* Bypass invalid index (not mapped to this GPIO port) */ + if (size_t(-1) == temp_io_index) { + continue; + } + + /* If the port is an GPIO port, just use it */ + if (ModuleManager::MODULE_GPIO_PORT == module_manager.port_type(top_module, module_io_port_id)) { + mapped_module_io_info = std::make_pair(module_io_port_id, temp_io_index); + break; + } + + /* If this is an INPAD, we can use an GPIN port (if available) */ + if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type(atom_blk)] == module_manager.port_type(top_module, module_io_port_id)) { + mapped_module_io_info = std::make_pair(module_io_port_id, temp_io_index); + break; + } + } + + /* We must find a valid one */ + VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, mapped_module_io_info.first)); + VTR_ASSERT(size_t(-1) != mapped_module_io_info.second); + + /* Ensure that IO index is in range */ + BasicPort module_mapped_io_port = module_manager.module_port(top_module, mapped_module_io_info.first); + size_t io_index = mapped_module_io_info.second; + + /* Set the port pin index */ + VTR_ASSERT(io_index < module_mapped_io_port.get_width()); + module_mapped_io_port.set_width(io_index, io_index); + + /* The block may be renamed as it contains special characters which violate Verilog syntax */ + std::string block_name = atom_ctx.nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + + /* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1 + * In addition, the input and output ports may have different postfix in naming + * due to verification context! Here, we give full customization on naming + */ + BasicPort benchmark_io_port; + if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { + benchmark_io_port.set_name(std::string(block_name + io_input_port_name_postfix)); + benchmark_io_port.set_width(1); + } else { + VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); + /* VPR may have added a prefix to the output ports, remove them here */ + std::string output_block_name = block_name; + for (const std::string& prefix_to_remove : output_port_prefix_to_remove) { + if (!prefix_to_remove.empty()) { + if (0 == output_block_name.find(prefix_to_remove)) { + output_block_name.erase(0, prefix_to_remove.length()); + break; + } + } + } + + benchmark_io_port.set_name(std::string(output_block_name + io_output_port_name_postfix)); + benchmark_io_port.set_width(1); + } + + io_map.create_io_mapping(module_mapped_io_port, + benchmark_io_port, + atom_block_type_to_io_map_direction[atom_ctx.nlist.block_type(atom_blk)]); + } + + return io_map; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/build_io_mapping_info.h b/openfpga/src/fpga_bitstream/build_io_mapping_info.h new file mode 100644 index 000000000..01f4b1d61 --- /dev/null +++ b/openfpga/src/fpga_bitstream/build_io_mapping_info.h @@ -0,0 +1,34 @@ +#ifndef BUILD_IO_MAPPING_INFO_H +#define BUILD_IO_MAPPING_INFO_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include +#include "module_manager.h" +#include "vpr_context.h" +#include "io_location_map.h" +#include "io_map.h" +#include "vpr_netlist_annotation.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager, + const ModuleId& top_module, + const AtomContext& atom_ctx, + const PlacementContext& place_ctx, + const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& output_port_prefix_to_remove); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_bitstream/fast_configuration.cpp b/openfpga/src/fpga_bitstream/fast_configuration.cpp new file mode 100644 index 000000000..5b3ec0301 --- /dev/null +++ b/openfpga/src/fpga_bitstream/fast_configuration.cpp @@ -0,0 +1,128 @@ +/******************************************************************** + * This file includes functions that are used to create + * an auto-check top-level testbench for a FPGA fabric + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_log.h" +#include "vtr_assert.h" + +#include "fabric_global_port_info_utils.h" +#include "fast_configuration.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Identify if fast configuration is applicable base on the availability + * of programming reset and programming set ports of the FPGA fabric + *******************************************************************/ +bool is_fast_configuration_applicable(const FabricGlobalPortInfo& global_ports) { + /* Preparation: find all the reset/set ports for programming usage */ + std::vector global_prog_reset_ports = find_fabric_global_programming_reset_ports(global_ports); + std::vector global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports); + + /* Identify if we can apply fast configuration */ + if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is not applicable\n"); + return false; + } + + return true; +} + +/******************************************************************** + * Decide if we should use reset or set signal to acheive fast configuration + * - If only one type signal is specified, we use that type + * For example, only reset signal is defined, we will use reset + * - If both are defined, pick the one that will bring bigger reduction + * i.e., larger number of configuration bits can be skipped + *******************************************************************/ +bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, + const FabricGlobalPortInfo& global_ports, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + /* Preparation: find all the reset/set ports for programming usage */ + std::vector global_prog_reset_ports = find_fabric_global_programming_reset_ports(global_ports); + std::vector global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports); + + /* Early exit conditions */ + if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) { + return false; + } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + return true; + } + + /* If both types of ports are not defined, the fast configuration is not applicable */ + VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); + bool bit_value_to_skip = false; + + VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); + + size_t num_ones_to_skip = 0; + size_t num_zeros_to_skip = 0; + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: { + /* We can only skip the ones/zeros at the beginning of the bitstream */ + /* Count how many logic '1' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + /* Count how many logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_zeros_to_skip++; + } + break; + } + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + /* Count how many logic '1' and logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + num_zeros_to_skip++; + } else { + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + } + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid configuration protocol type!\n"); + exit(1); + } + + VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), + num_zeros_to_skip, fabric_bitstream.num_bits()); + + VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), + num_ones_to_skip, fabric_bitstream.num_bits()); + + /* By default, we prefer to skip zeros (when the numbers are the same */ + if (num_ones_to_skip > num_zeros_to_skip) { + VTR_LOG("Will use set signal in fast configuration\n"); + bit_value_to_skip = true; + } else { + VTR_LOG("Will use reset signal in fast configuration\n"); + } + + return bit_value_to_skip; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/fast_configuration.h b/openfpga/src/fpga_bitstream/fast_configuration.h new file mode 100644 index 000000000..eb161d1b2 --- /dev/null +++ b/openfpga/src/fpga_bitstream/fast_configuration.h @@ -0,0 +1,30 @@ +#ifndef FAST_CONFIGURATION_H +#define FAST_CONFIGURATION_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include +#include "fabric_global_port_info.h" +#include "config_protocol.h" +#include "bitstream_manager.h" +#include "fabric_bitstream.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +bool is_fast_configuration_applicable(const FabricGlobalPortInfo& global_ports); + +bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, + const FabricGlobalPortInfo& global_ports, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp index f96747212..5338d7b09 100644 --- a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp @@ -13,73 +13,235 @@ /* Headers from openfpgautil library */ #include "openfpga_digest.h" +#include "openfpga_version.h" #include "openfpga_naming.h" +#include "fast_configuration.h" #include "bitstream_manager_utils.h" +#include "fabric_bitstream_utils.h" #include "write_text_fabric_bitstream.h" /* begin namespace openfpga */ namespace openfpga { /******************************************************************** - * Write a configuration bit into a plain text file - * The format depends on the type of configuration protocol - * - Vanilla (standalone): just put down pure 0|1 bitstream - * - Configuration chain: just put down pure 0|1 bitstream - * - Memory bank : - * - Frame-based configuration protocol :
+ * This function write header information to a bitstream file + *******************************************************************/ +static +void write_fabric_bitstream_text_file_head(std::fstream& fp) { + valid_file_stream(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "// Fabric bitstream" << std::endl; + fp << "// Version: " << openfpga::VERSION << std::endl; + fp << "// Date: " << std::ctime(&end_time); +} + +/******************************************************************** + * Write the flatten fabric bitstream to a plain text file * * Return: * - 0 if succeed * - 1 if critical errors occured *******************************************************************/ static -int write_fabric_config_bit_to_text_file(std::fstream& fp, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream, - const FabricBitId& fabric_bit, - const e_config_protocol_type& config_type) { +int write_flatten_fabric_bitstream_to_text_file(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { if (false == valid_file_stream(fp)) { return 1; } - switch (config_type) { - case CONFIG_MEM_STANDALONE: - case CONFIG_MEM_SCAN_CHAIN: + /* Output bitstream size information */ + fp << "// Bitstream length: " << fabric_bitstream.num_bits() << std::endl; + + /* Output bitstream data */ + for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) { fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit)); - break; - case CONFIG_MEM_MEMORY_BANK: { - for (const char& addr_bit : fabric_bitstream.bit_bl_address(fabric_bit)) { - fp << addr_bit; - } - write_space_to_file(fp, 1); - for (const char& addr_bit : fabric_bitstream.bit_wl_address(fabric_bit)) { - fp << addr_bit; - } - write_space_to_file(fp, 1); - fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit)); - fp << "\n"; - break; - } - case CONFIG_MEM_FRAME_BASED: { - for (const char& addr_bit : fabric_bitstream.bit_address(fabric_bit)) { - fp << addr_bit; - } - write_space_to_file(fp, 1); - fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit)); - fp << "\n"; - break; - } - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid configuration protocol type!\n"); - return 1; } return 0; } +/******************************************************************** + * Write the fabric bitstream fitting a configuration chain protocol + * to a plain text file + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_config_chain_fabric_bitstream_to_text_file(std::fstream& fp, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + int status = 0; + + size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); + ConfigChainFabricBitstream regional_bitstreams = build_config_chain_fabric_bitstream_by_region(bitstream_manager, fabric_bitstream); + + /* For fast configuration, the bitstream size counts from the first bit '1' */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = find_configuration_chain_fabric_bitstream_size_to_be_skipped(fabric_bitstream, bitstream_manager, bit_value_to_skip); + VTR_ASSERT(num_bits_to_skip < regional_bitstream_max_size); + VTR_LOG("Fast configuration will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_bits_to_skip / (float) regional_bitstream_max_size, + num_bits_to_skip, regional_bitstream_max_size); + } + + /* Output bitstream size information */ + fp << "// Bitstream length: " << regional_bitstream_max_size - num_bits_to_skip << std::endl; + fp << "// Bitstream width (LSB -> MSB): " << fabric_bitstream.num_regions() << std::endl; + + /* Output bitstream data */ + for (size_t ibit = num_bits_to_skip; ibit < regional_bitstream_max_size; ++ibit) { + for (const auto& region_bitstream : regional_bitstreams) { + fp << region_bitstream[ibit]; + } + if (ibit < regional_bitstream_max_size - 1) { + fp << std::endl; + } + } + + return status; +} + +/******************************************************************** + * Write the fabric bitstream fitting a memory bank protocol + * to a plain text file + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_memory_bank_fabric_bitstream_to_text_file(std::fstream& fp, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const FabricBitstream& fabric_bitstream) { + int status = 0; + + MemoryBankFabricBitstream fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream); + + /* The address sizes and data input sizes are the same across any element, + * just get it from the 1st element to save runtime + */ + size_t bl_addr_size = fabric_bits_by_addr.begin()->first.first.size(); + size_t wl_addr_size = fabric_bits_by_addr.begin()->first.second.size(); + size_t din_size = fabric_bits_by_addr.begin()->second.size(); + + /* Identify and output bitstream size information */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = fabric_bits_by_addr.size() - find_memory_bank_fast_configuration_fabric_bitstream_size(fabric_bitstream, bit_value_to_skip); + VTR_ASSERT(num_bits_to_skip < fabric_bits_by_addr.size()); + VTR_LOG("Fast configuration will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_bits_to_skip / (float) fabric_bits_by_addr.size(), + num_bits_to_skip, fabric_bits_by_addr.size()); + } + + /* Output information about how to intepret the bitstream */ + fp << "// Bitstream length: " << fabric_bits_by_addr.size() - num_bits_to_skip << std::endl; + fp << "// Bitstream width (LSB -> MSB): "; + fp << ""; + fp << ""; + fp << ""; + fp << std::endl; + + for (const auto& addr_din_pair : fabric_bits_by_addr) { + /* When fast configuration is enabled, + * the rule to skip any configuration bit should consider the whole data input values. + * Only all the bits in the din port match the value to be skipped, + * the programming cycle can be skipped! + */ + if (true == fast_configuration) { + if (addr_din_pair.second == std::vector(addr_din_pair.second.size(), bit_value_to_skip)) { + continue; + } + } + + /* Write BL address code */ + fp << addr_din_pair.first.first; + /* Write WL address code */ + fp << addr_din_pair.first.second; + /* Write data input */ + for (const bool& din_value : addr_din_pair.second) { + fp << din_value; + } + fp << std::endl; + } + + return status; +} + +/******************************************************************** + * Write the fabric bitstream fitting a frame-based protocol + * to a plain text file + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_frame_based_fabric_bitstream_to_text_file(std::fstream& fp, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const FabricBitstream& fabric_bitstream) { + int status = 0; + + FrameFabricBitstream fabric_bits_by_addr = build_frame_based_fabric_bitstream_by_address(fabric_bitstream); + + /* The address sizes and data input sizes are the same across any element, + * just get it from the 1st element to save runtime + */ + size_t addr_size = fabric_bits_by_addr.begin()->first.size(); + size_t din_size = fabric_bits_by_addr.begin()->second.size(); + + /* Identify and output bitstream size information */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = fabric_bits_by_addr.size() - find_frame_based_fast_configuration_fabric_bitstream_size(fabric_bitstream, bit_value_to_skip); + VTR_ASSERT(num_bits_to_skip < fabric_bits_by_addr.size()); + VTR_LOG("Fast configuration will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_bits_to_skip / (float) fabric_bits_by_addr.size(), + num_bits_to_skip, fabric_bits_by_addr.size()); + } + + /* Output information about how to intepret the bitstream */ + fp << "// Bitstream length: " << fabric_bits_by_addr.size() - num_bits_to_skip << std::endl; + fp << "// Bitstream width (LSB -> MSB):
" << std::endl; + + for (const auto& addr_din_pair : fabric_bits_by_addr) { + /* When fast configuration is enabled, + * the rule to skip any configuration bit should consider the whole data input values. + * Only all the bits in the din port match the value to be skipped, + * the programming cycle can be skipped! + */ + if (true == fast_configuration) { + if (addr_din_pair.second == std::vector(addr_din_pair.second.size(), bit_value_to_skip)) { + continue; + } + } + + /* Write address code */ + fp << addr_din_pair.first; + + /* Write data input */ + for (const bool& din_value : addr_din_pair.second) { + fp << din_value; + } + fp << std::endl; + } + + return status; +} + /******************************************************************** * Write the fabric bitstream to a plain text file * Notes: @@ -95,7 +257,9 @@ int write_fabric_config_bit_to_text_file(std::fstream& fp, int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const ConfigProtocol& config_protocol, + const FabricGlobalPortInfo& global_ports, const std::string& fname, + const bool& fast_configuration, const bool& verbose) { /* Ensure that we have a valid file name */ if (true == fname.empty()) { @@ -111,17 +275,56 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage check_file_stream(fname.c_str(), fp); + bool apply_fast_configuration = is_fast_configuration_applicable(global_ports) && fast_configuration; + if (fast_configuration && apply_fast_configuration != fast_configuration) { + VTR_LOG_WARN("Disable fast configuration even it is enabled by user\n"); + } + + bool bit_value_to_skip = false; + if (apply_fast_configuration) { + bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), + global_ports, + bitstream_manager, + fabric_bitstream); + } + + /* Write file head */ + write_fabric_bitstream_text_file_head(fp); + /* Output fabric bitstream to the file */ int status = 0; - for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) { - status = write_fabric_config_bit_to_text_file(fp, bitstream_manager, - fabric_bitstream, - fabric_bit, - config_protocol.type()); - if (1 == status) { - break; - } + switch (config_protocol.type()) { + case CONFIG_MEM_STANDALONE: + status = write_flatten_fabric_bitstream_to_text_file(fp, + bitstream_manager, + fabric_bitstream); + break; + case CONFIG_MEM_SCAN_CHAIN: + status = write_config_chain_fabric_bitstream_to_text_file(fp, + apply_fast_configuration, + bit_value_to_skip, + bitstream_manager, + fabric_bitstream); + break; + case CONFIG_MEM_MEMORY_BANK: + status = write_memory_bank_fabric_bitstream_to_text_file(fp, + apply_fast_configuration, + bit_value_to_skip, + fabric_bitstream); + break; + case CONFIG_MEM_FRAME_BASED: + status = write_frame_based_fabric_bitstream_to_text_file(fp, + apply_fast_configuration, + bit_value_to_skip, + fabric_bitstream); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid configuration protocol type!\n"); + status = 1; } + + /* Print an end to the file here */ fp << std::endl; diff --git a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h index 9582a185c..17811f439 100644 --- a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h @@ -9,6 +9,7 @@ #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "config_protocol.h" +#include "fabric_global_port_info.h" /******************************************************************** * Function declaration @@ -20,7 +21,9 @@ namespace openfpga { int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const ConfigProtocol& config_protocol, + const FabricGlobalPortInfo& global_ports, const std::string& fname, + const bool& fast_configuration, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp index 32d5a209c..adc12ce73 100644 --- a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp @@ -71,12 +71,13 @@ int write_fabric_config_bit_to_xml_file(std::fstream& fp, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const FabricBitId& fabric_bit, - const e_config_protocol_type& config_type) { + const e_config_protocol_type& config_type, + const int& xml_hierarchy_depth) { if (false == valid_file_stream(fp)) { return 1; } - write_tab_to_file(fp, 1); + write_tab_to_file(fp, xml_hierarchy_depth); fp << "\n"; - write_tab_to_file(fp, 2); + write_tab_to_file(fp, xml_hierarchy_depth + 1); fp << "\n"; return 0; } +/******************************************************************** + * Write the fabric bitstream in a specific configuration region to an XML file + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_fabric_regional_config_bit_to_xml_file(std::fstream& fp, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream, + const FabricBitRegionId& fabric_region, + const e_config_protocol_type& config_type, + const int& xml_hierarchy_depth) { + if (false == valid_file_stream(fp)) { + return 1; + } + + int status = 0; + + write_tab_to_file(fp, xml_hierarchy_depth); + fp << "\n"; + + for (const FabricBitId& fabric_bit : fabric_bitstream.region_bits(fabric_region)) { + status = write_fabric_config_bit_to_xml_file(fp, bitstream_manager, + fabric_bitstream, + fabric_bit, + config_type, + xml_hierarchy_depth + 1); + if (1 == status) { + return status; + } + } + + write_tab_to_file(fp, xml_hierarchy_depth); + fp << "\n"; + + return status; +} + /******************************************************************** * Write the fabric bitstream to an XML file * Notes: @@ -173,15 +218,17 @@ int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager /* Write XML head */ write_fabric_bitstream_xml_file_head(fp); + int xml_hierarchy_depth = 0; fp << "\n"; /* Output fabric bitstream to the file */ int status = 0; - for (const FabricBitId& fabric_bit : fabric_bitstream.bits()) { - status = write_fabric_config_bit_to_xml_file(fp, bitstream_manager, - fabric_bitstream, - fabric_bit, - config_protocol.type()); + for (const FabricBitRegionId& region : fabric_bitstream.regions()) { + status = write_fabric_regional_config_bit_to_xml_file(fp, bitstream_manager, + fabric_bitstream, + region, + config_protocol.type(), + xml_hierarchy_depth + 1); if (1 == status) { break; } diff --git a/openfpga/src/fpga_bitstream/write_xml_io_mapping.cpp b/openfpga/src/fpga_bitstream/write_xml_io_mapping.cpp new file mode 100644 index 000000000..5b3f383b1 --- /dev/null +++ b/openfpga/src/fpga_bitstream/write_xml_io_mapping.cpp @@ -0,0 +1,145 @@ +/******************************************************************** + * This file includes functions that output io mapping information + * to files in XML format + *******************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "openfpga_digest.h" + +/* Headers from archopenfpga library */ +#include "openfpga_naming.h" + +#include "openfpga_version.h" + +#include "build_io_mapping_info.h" +#include "write_xml_io_mapping.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * This function write header information to an I/O mapping file + *******************************************************************/ +static +void write_io_mapping_xml_file_head(std::fstream& fp) { + valid_file_stream(fp); + + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + + fp << "" << std::endl; + fp << std::endl; +} + +/******************************************************************** + * Write an io mapping pair to an XML file + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +static +int write_io_mapping_pair_to_xml_file(std::fstream& fp, + const IoMap& io_map, + const IoMapId& io_map_id, + int xml_hierarchy_depth) { + if (false == valid_file_stream(fp)) { + return 1; + } + + write_tab_to_file(fp, xml_hierarchy_depth); + + BasicPort io_port = io_map.io_port(io_map_id); + fp << "\n"; + + return 0; +} + +/******************************************************************** + * Write the io mapping information to an XML file + * Notes: + * - This file is designed for users to learn + * - what nets are mapped to each I/O is mapped, io[0] -> netA + * - what directionality is applied to each I/O, io[0] -> input + * + * Return: + * - 0 if succeed + * - 1 if critical errors occured + *******************************************************************/ +int write_io_mapping_to_xml_file(const IoMap& io_map, + const std::string& fname, + const bool& verbose) { + /* Ensure that we have a valid file name */ + if (true == fname.empty()) { + VTR_LOG_ERROR("Received empty file name to output io_mapping!\n\tPlease specify a valid file name.\n"); + return 1; + } + + std::string timer_message = std::string("Write I/O mapping into xml file '") + fname + std::string("'"); + vtr::ScopedStartFinishTimer timer(timer_message); + + /* Create the file stream */ + std::fstream fp; + fp.open(fname, std::fstream::out | std::fstream::trunc); + + check_file_stream(fname.c_str(), fp); + + /* Write XML head */ + write_io_mapping_xml_file_head(fp); + + int xml_hierarchy_depth = 0; + fp << "\n"; + + /* Output fabric bitstream to the file */ + int status = 0; + int io_map_cnt = 0; + for (const auto& io_map_id : io_map.io_map()) { + status = write_io_mapping_pair_to_xml_file(fp, + io_map, io_map_id, + xml_hierarchy_depth + 1); + io_map_cnt++; + if (1 == status) { + break; + } + } + + /* Print an end to the file here */ + fp << "\n"; + + VTR_LOGV(verbose, + "Outputted %d I/O mapping to file '%s'\n", + io_map_cnt, + fname.c_str()); + + /* Close file handler */ + fp.close(); + + return status; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/fpga_bitstream/write_xml_io_mapping.h b/openfpga/src/fpga_bitstream/write_xml_io_mapping.h new file mode 100644 index 000000000..330106141 --- /dev/null +++ b/openfpga/src/fpga_bitstream/write_xml_io_mapping.h @@ -0,0 +1,25 @@ +#ifndef WRITE_XML_IO_MAPPING_H +#define WRITE_XML_IO_MAPPING_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include +#include "vpr_context.h" +#include "io_map.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { + +int write_io_mapping_to_xml_file(const IoMap& io_map, + const std::string& fname, + const bool& verbose); + +} /* end namespace openfpga */ + +#endif diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp index 22495d31a..1cdbb0798 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp @@ -16,6 +16,7 @@ #include "openfpga_reserved_words.h" #include "openfpga_naming.h" +#include "build_routing_module_utils.h" #include "sdc_writer_utils.h" #include "analysis_sdc_writer_utils.h" #include "analysis_sdc_routing_writer.h" @@ -33,6 +34,8 @@ static void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -140,7 +143,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, } std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_graph.node_pin_num(ipin_node)); + grids, + device_annotation, + rr_graph, + ipin_node); /* Find the port in unique mirror! */ if (true == compact_routing_hierarchy) { @@ -149,7 +155,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp, const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord); const RRNodeId& unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode); port_name = generate_cb_module_grid_port_name(cb_ipin_side, - rr_graph.node_pin_num(unique_mirror_ipin_node)); + grids, + device_annotation, + rr_graph, + unique_mirror_ipin_node); } /* Ensure we have this port in the module! */ @@ -211,6 +220,8 @@ static void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -233,6 +244,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, print_analysis_sdc_disable_cb_unused_resources(fp, atom_ctx, module_manager, + device_annotation, + grids, rr_graph, routing_annotation, device_rr_gsb, @@ -250,6 +263,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp, void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -257,6 +272,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx, module_manager, + device_annotation, + grids, rr_graph, routing_annotation, device_rr_gsb, @@ -264,6 +281,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx, module_manager, + device_annotation, + grids, rr_graph, routing_annotation, device_rr_gsb, @@ -280,6 +299,8 @@ static void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -370,7 +391,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(opin_node), - rr_graph.node_pin_num(opin_node)); + grids, + device_annotation, + rr_graph, + opin_node); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -380,7 +404,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(unique_mirror_opin_node), - rr_graph.node_pin_num(unique_mirror_opin_node)); + grids, + device_annotation, + rr_graph, + unique_mirror_opin_node); } @@ -432,7 +459,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(opin_node), - rr_graph.node_pin_num(opin_node)); + grids, + device_annotation, + rr_graph, + opin_node); if (true == compact_routing_hierarchy) { /* Note: use GSB coordinate when inquire for unique modules!!! */ @@ -442,7 +472,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, port_name = generate_sb_module_grid_port_name(side_manager.get_side(), rr_graph.node_side(unique_mirror_opin_node), - rr_graph.node_pin_num(unique_mirror_opin_node)); + grids, + device_annotation, + rr_graph, + unique_mirror_opin_node); } @@ -512,6 +545,8 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp, void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -534,6 +569,8 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, print_analysis_sdc_disable_sb_unused_resources(fp, atom_ctx, module_manager, + device_annotation, + grids, rr_graph, routing_annotation, device_rr_gsb, diff --git a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h index e50bc73b6..d864169f1 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h +++ b/openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h @@ -8,6 +8,7 @@ #include #include "vpr_context.h" #include "module_manager.h" +#include "device_grid.h" #include "device_rr_gsb.h" #include "vpr_routing_annotation.h" @@ -21,6 +22,8 @@ namespace openfpga { void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, @@ -29,6 +32,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp, void print_analysis_sdc_disable_unused_sbs(std::fstream& fp, const AtomContext& atom_ctx, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const VprRoutingAnnotation& routing_annotation, const DeviceRRGSB& device_rr_gsb, diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp index 12defbac7..2af28902b 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp @@ -267,6 +267,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option, print_analysis_sdc_disable_unused_cbs(fp, vpr_ctx.atom(), openfpga_ctx.module_graph(), + openfpga_ctx.vpr_device_annotation(), + vpr_ctx.device().grid, vpr_ctx.device().rr_graph, openfpga_ctx.vpr_routing_annotation(), openfpga_ctx.device_rr_gsb(), @@ -276,6 +278,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option, print_analysis_sdc_disable_unused_sbs(fp, vpr_ctx.atom(), openfpga_ctx.module_graph(), + openfpga_ctx.vpr_device_annotation(), + vpr_ctx.device().grid, vpr_ctx.device().rr_graph, openfpga_ctx.vpr_routing_annotation(), openfpga_ctx.device_rr_gsb(), diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp index 1491d161d..29cd5eae2 100644 --- a/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp +++ b/openfpga/src/fpga_sdc/analysis_sdc_writer_utils.cpp @@ -103,7 +103,7 @@ void disable_analysis_module_input_pin_net_sinks(std::fstream& fp, VTR_ASSERT(!sink_instance_name.empty()); /* Get the input id that is used! Disable the unused inputs! */ fp << "set_disable_timing "; - fp << parent_instance_name; + fp << parent_instance_name << "/"; fp << sink_instance_name << "/"; fp << generate_sdc_port(sink_port); fp << std::endl; @@ -228,7 +228,7 @@ void disable_analysis_module_output_pin_net_sinks(std::fstream& fp, VTR_ASSERT(!sink_instance_name.empty()); /* Get the input id that is used! Disable the unused inputs! */ fp << "set_disable_timing "; - fp << parent_instance_name; + fp << parent_instance_name << "/"; fp << sink_instance_name << "/"; fp << generate_sdc_port(sink_port); fp << std::endl; diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp index 8f7c92046..156f78ff1 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp @@ -20,6 +20,7 @@ /* Headers from openfpgautil library */ #include "openfpga_port.h" #include "openfpga_digest.h" +#include "openfpga_scale.h" #include "sdc_writer_naming.h" #include "sdc_writer_utils.h" @@ -59,6 +60,7 @@ void print_pnr_sdc_clock_port(std::fstream& fp, *******************************************************************/ static void print_pnr_sdc_global_clock_ports(std::fstream& fp, + const float& time_unit, const ModuleManager& module_manager, const ModuleId& top_module, const FabricGlobalPortInfo& fabric_global_port_info, @@ -103,7 +105,7 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp, print_pnr_sdc_clock_port(fp, port_to_constrain, - clock_period); + clock_period / time_unit); } } } @@ -118,6 +120,7 @@ void print_pnr_sdc_global_clock_ports(std::fstream& fp, *******************************************************************/ static void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, + const float& time_unit, const float& operating_critical_path_delay, const ModuleManager& module_manager, const ModuleId& top_module, @@ -144,7 +147,7 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, print_pnr_sdc_clock_port(fp, port_to_constrain, - clock_period); + clock_period / time_unit); } } } @@ -161,6 +164,7 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp, * In general, we do not recommend to do this *******************************************************************/ void print_pnr_sdc_global_ports(const std::string& sdc_dir, + const float& time_unit, const ModuleManager& module_manager, const ModuleId& top_module, const FabricGlobalPortInfo& global_ports, @@ -183,12 +187,15 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir, /* Generate the descriptions*/ print_sdc_file_header(fp, std::string("Clock contraints for PnR")); - print_pnr_sdc_global_clock_ports(fp, + /* Print time unit for the SDC file */ + print_sdc_timescale(fp, time_unit_to_string(time_unit)); + + print_pnr_sdc_global_clock_ports(fp, time_unit, module_manager, top_module, global_ports, sim_setting); if (true == constrain_non_clock_port) { - print_pnr_sdc_global_non_clock_ports(fp, + print_pnr_sdc_global_non_clock_ports(fp, time_unit, 1./sim_setting.default_operating_clock_frequency(), module_manager, top_module, global_ports); diff --git a/openfpga/src/fpga_sdc/pnr_sdc_global_port.h b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h index 15808e623..ae12a5a21 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_global_port.h +++ b/openfpga/src/fpga_sdc/pnr_sdc_global_port.h @@ -18,6 +18,7 @@ namespace openfpga { void print_pnr_sdc_global_ports(const std::string& sdc_dir, + const float& time_unit, const ModuleManager& module_manager, const ModuleId& top_module, const FabricGlobalPortInfo& global_ports, diff --git a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp index b56f8acf0..352658d2e 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp @@ -83,7 +83,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, t_pb_graph_node* des_pb_graph_node = des_pb_graph_pin->parent_node; /* Find the src module in module manager */ - std::string src_module_name = generate_physical_block_module_name(src_pb_graph_pin->parent_node->pb_type); + std::string src_module_name = generate_physical_block_module_name(src_pb_graph_node->pb_type); ModuleId src_module = module_manager.find_module(src_module_name); VTR_ASSERT(true == module_manager.valid_module_id(src_module)); @@ -104,6 +104,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, src_instance_name += std::to_string(instance_id); src_instance_name += "_"; } else { + VTR_ASSERT_SAFE(true == module_manager.instance_name(parent_module, src_module, instance_id).empty()); src_instance_name += module_manager.instance_name(parent_module, src_module, instance_id); } } @@ -113,7 +114,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, src_port.set_width(src_pb_graph_pin->pin_number, src_pb_graph_pin->pin_number); /* Find the des module in module manager */ - std::string des_module_name = generate_physical_block_module_name(des_pb_graph_pin->parent_node->pb_type); + std::string des_module_name = generate_physical_block_module_name(des_pb_graph_node->pb_type); ModuleId des_module = module_manager.find_module(des_module_name); VTR_ASSERT(true == module_manager.valid_module_id(des_module)); ModulePortId des_module_port_id = module_manager.find_module_port(des_module, generate_pb_type_port_name(des_pb_graph_pin->port)); @@ -133,6 +134,7 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, des_instance_name += std::to_string(instance_id); des_instance_name += "_"; } else { + VTR_ASSERT_SAFE(true != module_manager.instance_name(parent_module, des_module, instance_id).empty()); des_instance_name += module_manager.instance_name(parent_module, des_module, instance_id); } } @@ -150,17 +152,11 @@ void print_pnr_sdc_constrain_pb_pin_interc_timing(std::fstream& fp, /* Give full path if hierarchical is not enabled */ std::string src_module_path = src_instance_name; if (false == hierarchical) { - if (true == src_instance_name.empty()) { - src_instance_name = generate_instance_name(src_module_name, 0); - } src_module_path = module_path + src_instance_name; } std::string des_module_path = des_instance_name; if (false == hierarchical) { - if (true == des_instance_name.empty()) { - des_instance_name = generate_instance_name(des_module_name, 0); - } des_module_path = module_path + des_instance_name; } @@ -521,7 +517,7 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir, rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, hierarchical, - format_dir_path(module_path + std::string(physical_mode->pb_type_children[ipb].name)), + format_dir_path(module_path + generate_physical_block_instance_name(&(physical_mode->pb_type_children[ipb]), ipb)), module_manager, device_annotation, &(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]), @@ -582,6 +578,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); std::string module_path = format_dir_path(root_path + grid_module_name); + module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index)); rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, @@ -603,6 +600,7 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir, VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); std::string module_path = format_dir_path(root_path + grid_module_name); + module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index)); rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir, time_unit, diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp index 2b4f232b7..bf14c35c2 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp @@ -55,6 +55,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, const std::string& module_path, const ModuleManager& module_manager, const ModuleId& sb_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const e_side& output_node_side, @@ -68,19 +70,21 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, /* Find the module port corresponding to the output rr_node */ ModulePinInfo module_output_port = find_switch_block_module_chan_port(module_manager, - sb_module, - rr_graph, - rr_gsb, - output_node_side, - output_rr_node, - OUT_PORT); + sb_module, + rr_graph, + rr_gsb, + output_node_side, + output_rr_node, + OUT_PORT); /* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */ std::vector module_input_ports = find_switch_block_module_input_ports(module_manager, - sb_module, - rr_graph, - rr_gsb, - get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node)); + sb_module, + grids, + device_annotation, + rr_graph, + rr_gsb, + get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node)); /* Find timing constraints for each path (edge) */ std::map switch_delays; @@ -143,6 +147,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, const bool& hierarchical, const std::string& module_path, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const bool& constrain_zero_delay_paths) { @@ -186,6 +192,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir, hierarchical, module_path, module_manager, sb_module, + device_annotation, + grids, rr_graph, rr_gsb, side_manager.get_side(), @@ -207,6 +215,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths) { @@ -239,6 +249,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di hierarchical, module_path, module_manager, + device_annotation, + grids, rr_graph, rr_gsb, constrain_zero_delay_paths); @@ -255,6 +267,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths) { @@ -286,6 +300,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di hierarchical, module_path, module_manager, + device_annotation, + grids, rr_graph, rr_gsb, constrain_zero_delay_paths); @@ -303,6 +319,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, const std::string& module_path, const ModuleManager& module_manager, const ModuleId& cb_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -338,6 +356,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, /* Find the module port corresponding to the output rr_node */ ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager, cb_module, + grids, + device_annotation, rr_graph, rr_gsb, output_rr_node); @@ -405,6 +425,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, const bool& hierarchical, const std::string& module_path, const ModuleManager& module_manager, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -499,6 +521,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, time_unit, hierarchical, module_path, module_manager, cb_module, + device_annotation, + grids, rr_graph, rr_gsb, cb_type, ipin_rr_node, constrain_zero_delay_paths); @@ -519,6 +543,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const t_rr_type& cb_type, @@ -554,6 +580,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di hierarchical, module_path, module_manager, + device_annotation, + grids, rr_graph, rr_gsb, cb_type, @@ -572,6 +600,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths) { @@ -582,6 +612,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit, hierarchical, module_manager, top_module, + device_annotation, + grids, rr_graph, device_rr_gsb, CHANX, @@ -590,6 +622,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit, hierarchical, module_manager, top_module, + device_annotation, + grids, rr_graph, device_rr_gsb, CHANY, @@ -605,6 +639,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths) { @@ -633,6 +669,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di hierarchical, module_path, module_manager, + device_annotation, + grids, rr_graph, unique_mirror, CHANX, @@ -658,6 +696,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di hierarchical, module_path, module_manager, + device_annotation, + grids, rr_graph, unique_mirror, CHANY, diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h index d95c03a00..42af7675d 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h @@ -9,6 +9,8 @@ #include "module_manager.h" #include "device_rr_gsb.h" #include "rr_graph_obj.h" +#include "device_grid.h" +#include "vpr_device_annotation.h" /******************************************************************** * Function declaration @@ -22,6 +24,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths); @@ -31,6 +35,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths); @@ -40,6 +46,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths); @@ -49,6 +57,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di const bool& hierarchical, const ModuleManager& module_manager, const ModuleId& top_module, + const VprDeviceAnnotation& device_annotation, + const DeviceGrid& grids, const RRGraph& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& constrain_zero_delay_paths); diff --git a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp index fd74cfba7..1bd025871 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_writer.cpp @@ -336,6 +336,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, /* Constrain global ports */ if (true == sdc_options.constrain_global_port()) { print_pnr_sdc_global_ports(sdc_options.sdc_dir(), + sdc_options.time_unit(), module_manager, top_module, global_ports, sim_setting, sdc_options.constrain_non_clock_global_port()); @@ -382,6 +383,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, sdc_options.hierarchical(), module_manager, top_module, + device_annotation, + device_ctx.grid, device_ctx.rr_graph, device_rr_gsb, sdc_options.constrain_zero_delay_paths()); @@ -392,6 +395,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, sdc_options.hierarchical(), module_manager, top_module, + device_annotation, + device_ctx.grid, device_ctx.rr_graph, device_rr_gsb, sdc_options.constrain_zero_delay_paths()); @@ -416,6 +421,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, sdc_options.hierarchical(), module_manager, top_module, + device_annotation, + device_ctx.grid, device_ctx.rr_graph, device_rr_gsb, sdc_options.constrain_zero_delay_paths()); @@ -426,6 +433,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options, sdc_options.hierarchical(), module_manager, top_module, + device_annotation, + device_ctx.grid, device_ctx.rr_graph, device_rr_gsb, sdc_options.constrain_zero_delay_paths()); diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index 424f85c42..b22de5920 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -32,8 +32,7 @@ #include "verilog_api.h" /* begin namespace openfpga */ -namespace openfpga -{ +namespace openfpga { /******************************************************************** * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation @@ -141,29 +140,26 @@ void fpga_fabric_verilog(ModuleManager &module_manager, } /******************************************************************** - * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation + * A top-level function of FPGA-Verilog which focuses on full testbench generation * This function will generate - * - A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark - * - Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors - * - Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. - * This testbench is created for quick verification and formal verification purpose. * - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated ********************************************************************/ -int fpga_verilog_testbench(const ModuleManager &module_manager, - const BitstreamManager &bitstream_manager, - const FabricBitstream &fabric_bitstream, - const AtomContext &atom_ctx, - const PlacementContext &place_ctx, - const PinConstraints& pin_constraints, - const IoLocationMap &io_location_map, - const FabricGlobalPortInfo &fabric_global_port_info, - const VprNetlistAnnotation &netlist_annotation, - const CircuitLibrary &circuit_lib, - const SimulationSetting &simulation_setting, - const ConfigProtocol &config_protocol, - const VerilogTestbenchOption &options) { +int fpga_verilog_full_testbench(const ModuleManager &module_manager, + const BitstreamManager &bitstream_manager, + const FabricBitstream &fabric_bitstream, + const AtomContext &atom_ctx, + const PlacementContext &place_ctx, + const PinConstraints& pin_constraints, + const std::string& bitstream_file, + const IoLocationMap &io_location_map, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation &netlist_annotation, + const CircuitLibrary &circuit_lib, + const SimulationSetting &simulation_setting, + const ConfigProtocol &config_protocol, + const VerilogTestbenchOption &options) { - vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n"); + vtr::ScopedStartFinishTimer timer("Write Verilog full testbenches for FPGA fabric\n"); std::string src_dir_path = format_dir_path(options.output_directory()); @@ -174,81 +170,166 @@ int fpga_verilog_testbench(const ModuleManager &module_manager, /* Create directories */ create_directory(src_dir_path); - /* Output preprocessing flags for HDL simulations */ - print_verilog_simulation_preprocessing_flags(std::string(src_dir_path), - options); - - /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */ - if (true == options.print_formal_verification_top_netlist()) { - std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX); - status = print_verilog_preconfig_top_module(module_manager, bitstream_manager, - config_protocol, - circuit_lib, fabric_global_port_info, - atom_ctx, place_ctx, - pin_constraints, - io_location_map, - netlist_annotation, - netlist_name, - formal_verification_top_netlist_file_path, - options.explicit_port_mapping()); - if (status == CMD_EXEC_FATAL_ERROR) { - return status; - } - } - - if (true == options.print_preconfig_top_testbench()) { - /* Generate top-level testbench using random vectors */ - std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); - print_verilog_random_top_testbench(netlist_name, - random_top_testbench_file_path, - atom_ctx, - netlist_annotation, - pin_constraints, - simulation_setting, - options.explicit_port_mapping()); - } - /* Generate full testbench for verification, including configuration phase and operating phase */ - if (true == options.print_top_testbench()) { - std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); - print_verilog_top_testbench(module_manager, - bitstream_manager, fabric_bitstream, - circuit_lib, - config_protocol, - fabric_global_port_info, - atom_ctx, place_ctx, - pin_constraints, - io_location_map, - netlist_annotation, - netlist_name, - top_testbench_file_path, - simulation_setting, - options); - } - - /* Generate exchangeable files which contains simulation settings */ - if (true == options.print_simulation_ini()) { - std::string simulation_ini_file_name = options.simulation_ini_path(); - VTR_ASSERT(true != options.simulation_ini_path().empty()); - print_verilog_simulation_info(simulation_ini_file_name, - netlist_name, - src_dir_path, - atom_ctx, place_ctx, io_location_map, - module_manager, - config_protocol.type(), - bitstream_manager.num_bits(), - simulation_setting.num_clock_cycles(), - simulation_setting.programming_clock_frequency(), - simulation_setting.default_operating_clock_frequency()); - } + std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); + print_verilog_full_testbench(module_manager, + bitstream_manager, fabric_bitstream, + circuit_lib, + config_protocol, + fabric_global_port_info, + atom_ctx, place_ctx, + pin_constraints, + bitstream_file, + io_location_map, + netlist_annotation, + netlist_name, + top_testbench_file_path, + simulation_setting, + options); /* Generate a Verilog file including all the netlists that have been generated */ - print_verilog_testbench_include_netlists(src_dir_path, - netlist_name, - options.fabric_netlist_file_path(), - options.reference_benchmark_file_path()); + print_verilog_full_testbench_include_netlists(src_dir_path, + netlist_name, + options.fabric_netlist_file_path(), + options.reference_benchmark_file_path(), + options.no_self_checking()); return status; } +/******************************************************************** + * A top-level function of FPGA-Verilog which focuses on full testbench generation + * This function will generate + * - A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark + ********************************************************************/ +int fpga_verilog_preconfigured_fabric_wrapper(const ModuleManager &module_manager, + const BitstreamManager &bitstream_manager, + const AtomContext &atom_ctx, + const PlacementContext &place_ctx, + const PinConstraints& pin_constraints, + const IoLocationMap &io_location_map, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation &netlist_annotation, + const CircuitLibrary &circuit_lib, + const ConfigProtocol &config_protocol, + const VerilogTestbenchOption &options) { + + vtr::ScopedStartFinishTimer timer("Write a wrapper module for a preconfigured FPGA fabric\n"); + + std::string src_dir_path = format_dir_path(options.output_directory()); + + std::string netlist_name = atom_ctx.nlist.netlist_name(); + + int status = CMD_EXEC_SUCCESS; + + /* Create directories */ + create_directory(src_dir_path); + + /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */ + std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX); + status = print_verilog_preconfig_top_module(module_manager, bitstream_manager, + config_protocol, + circuit_lib, fabric_global_port_info, + atom_ctx, place_ctx, + pin_constraints, + io_location_map, + netlist_annotation, + netlist_name, + formal_verification_top_netlist_file_path, + options); + + return status; +} + +/******************************************************************** + * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation + * This function will generate + * - Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. + * This testbench is created for quick verification and formal verification purpose. + ********************************************************************/ +int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager, + const AtomContext &atom_ctx, + const PinConstraints& pin_constraints, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation &netlist_annotation, + const SimulationSetting &simulation_setting, + const VerilogTestbenchOption &options) { + + vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for a preconfigured FPGA fabric\n"); + + std::string src_dir_path = format_dir_path(options.output_directory()); + + std::string netlist_name = atom_ctx.nlist.netlist_name(); + + int status = CMD_EXEC_SUCCESS; + + /* Create directories */ + create_directory(src_dir_path); + + /* Generate top-level testbench using random vectors */ + std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); + print_verilog_random_top_testbench(netlist_name, + random_top_testbench_file_path, + atom_ctx, + netlist_annotation, + module_manager, + fabric_global_port_info, + pin_constraints, + simulation_setting, + options); + + /* Generate a Verilog file including all the netlists that have been generated */ + print_verilog_preconfigured_testbench_include_netlists(src_dir_path, + netlist_name, + options.fabric_netlist_file_path(), + options.reference_benchmark_file_path(), + options.no_self_checking()); + + return status; +} + +/******************************************************************** + * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation + * This function will generate + * - An interchangable file containing simulation task configuration + ********************************************************************/ +int fpga_verilog_simulation_task_info(const ModuleManager &module_manager, + const BitstreamManager &bitstream_manager, + const AtomContext &atom_ctx, + const PlacementContext &place_ctx, + const IoLocationMap &io_location_map, + const SimulationSetting &simulation_setting, + const ConfigProtocol &config_protocol, + const VerilogTestbenchOption &options) { + + vtr::ScopedStartFinishTimer timer("Write interchangeable simulation task configuration\n"); + + std::string src_dir_path = format_dir_path(options.output_directory()); + + std::string netlist_name = atom_ctx.nlist.netlist_name(); + + int status = CMD_EXEC_SUCCESS; + + /* Create directories */ + create_directory(src_dir_path); + + /* Generate exchangeable files which contains simulation settings */ + std::string simulation_ini_file_name = options.simulation_ini_path(); + VTR_ASSERT(true != options.simulation_ini_path().empty()); + print_verilog_simulation_info(simulation_ini_file_name, + options, + netlist_name, + src_dir_path, + atom_ctx, place_ctx, io_location_map, + module_manager, + config_protocol.type(), + bitstream_manager.num_bits(), + simulation_setting.num_clock_cycles(), + simulation_setting.programming_clock_frequency(), + simulation_setting.default_operating_clock_frequency()); + + return status; +} + + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 6c3ec190e..934dc08f7 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -43,20 +43,49 @@ void fpga_fabric_verilog(ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const FabricVerilogOption& options); -int fpga_verilog_testbench(const ModuleManager& module_manager, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream, - const AtomContext& atom_ctx, - const PlacementContext& place_ctx, - const PinConstraints& pin_constraints, - const IoLocationMap& io_location_map, - const FabricGlobalPortInfo &fabric_global_port_info, - const VprNetlistAnnotation& netlist_annotation, - const CircuitLibrary& circuit_lib, - const SimulationSetting& simulation_parameters, - const ConfigProtocol& config_protocol, - const VerilogTestbenchOption& options); +int fpga_verilog_full_testbench(const ModuleManager& module_manager, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream, + const AtomContext& atom_ctx, + const PlacementContext& place_ctx, + const PinConstraints& pin_constraints, + const std::string& bitstream_file, + const IoLocationMap& io_location_map, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation& netlist_annotation, + const CircuitLibrary& circuit_lib, + const SimulationSetting& simulation_parameters, + const ConfigProtocol& config_protocol, + const VerilogTestbenchOption& options); +int fpga_verilog_preconfigured_fabric_wrapper(const ModuleManager &module_manager, + const BitstreamManager &bitstream_manager, + const AtomContext &atom_ctx, + const PlacementContext &place_ctx, + const PinConstraints& pin_constraints, + const IoLocationMap &io_location_map, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation &netlist_annotation, + const CircuitLibrary &circuit_lib, + const ConfigProtocol &config_protocol, + const VerilogTestbenchOption &options); + +int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager, + const AtomContext &atom_ctx, + const PinConstraints& pin_constraints, + const FabricGlobalPortInfo &fabric_global_port_info, + const VprNetlistAnnotation &netlist_annotation, + const SimulationSetting &simulation_setting, + const VerilogTestbenchOption &options); + +int fpga_verilog_simulation_task_info(const ModuleManager &module_manager, + const BitstreamManager &bitstream_manager, + const AtomContext &atom_ctx, + const PlacementContext &place_ctx, + const IoLocationMap &io_location_map, + const SimulationSetting &simulation_setting, + const ConfigProtocol &config_protocol, + const VerilogTestbenchOption &options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index b0bacad37..09974ca12 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -90,14 +90,15 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, /******************************************************************** * Print a file that includes all the netlists - * including the fabric netlists and testbenches + * including the fabric netlists and full testbenches * that have been generated and user-defined. * Some netlists are open to compile under specific preprocessing flags *******************************************************************/ -void print_verilog_testbench_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& fabric_netlist_file, - const std::string& reference_benchmark_file) { +void print_verilog_full_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file, + const bool& no_self_checking) { std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX); /* Create the file stream */ @@ -110,11 +111,52 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir, /* Print the title */ print_verilog_file_header(fp, std::string("Netlist Summary")); - /* Print preprocessing flags */ - print_verilog_comment(fp, std::string("------ Include simulation defines -----")); - print_verilog_include_netlist(fp, src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)); + /* Include FPGA top module */ + print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); + if (true == fabric_netlist_file.empty()) { + print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME)); + } else { + VTR_ASSERT_SAFE(false == fabric_netlist_file.empty()); + print_verilog_include_netlist(fp, fabric_netlist_file); + } fp << std::endl; + /* Include reference benchmark netlist only when auto-check flag is enabled */ + if (!no_self_checking) { + print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); + fp << std::endl; + } + + /* Include top-level testbench only when auto-check flag is enabled */ + print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); + + /* Close the file stream */ + fp.close(); +} + +/******************************************************************** + * Print a file that includes all the netlists + * including the fabric netlists and preconfigured testbenches + * that have been generated and user-defined. + * Some netlists are open to compile under specific preprocessing flags + *******************************************************************/ +void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file, + const bool& no_self_checking) { + std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + check_file_stream(verilog_fname.c_str(), fp); + + /* Print the title */ + print_verilog_file_header(fp, std::string("Netlist Summary")); + /* Include FPGA top module */ print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); if (true == fabric_netlist_file.empty()) { @@ -126,34 +168,16 @@ void print_verilog_testbench_include_netlists(const std::string& src_dir, fp << std::endl; /* Include reference benchmark netlist only when auto-check flag is enabled */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - fp << "\t"; - print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); - print_verilog_endif(fp); - fp << std::endl; + if (!no_self_checking) { + print_verilog_include_netlist(fp, std::string(reference_benchmark_file)); + fp << std::endl; + } - /* Include formal verification netlists only when formal verification flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG)); - fp << "\t"; + /* Include formal verification netlists */ print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX)); - /* Include formal verification testbench only when formal simulation flag is enabled */ - fp << "\t"; - print_verilog_preprocessing_flag(fp, std::string(FORMAL_SIMULATION_FLAG)); - fp << "\t\t"; + /* Include formal verification testbench */ print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); - fp << "\t"; - print_verilog_endif(fp); - - print_verilog_endif(fp); - fp << std::endl; - - /* Include top-level testbench only when auto-check flag is enabled */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - fp << "\t"; - print_verilog_include_netlist(fp, src_dir + circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX)); - print_verilog_endif(fp); - fp << std::endl; /* Close the file stream */ fp.close(); @@ -188,63 +212,4 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, fp.close(); } -/******************************************************************** - * Print a Verilog file containing simulation-related preprocessing flags - *******************************************************************/ -void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, - const VerilogTestbenchOption& verilog_testbench_opts) { - - std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME); - - /* Create the file stream */ - std::fstream fp; - fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - check_file_stream(verilog_fname.c_str(), fp); - - /* Print the title */ - print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); - - /* To enable signal initialization */ - if (true == verilog_testbench_opts.include_signal_init()) { - print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1); - fp << std::endl; - } - - /* To enable functional verfication with Icarus */ - if (true == verilog_testbench_opts.support_icarus_simulator()) { - print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1); - fp << std::endl; - } - - /* To enable manualy checked simulation */ - if (true == verilog_testbench_opts.print_top_testbench()) { - print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1); - fp << std::endl; - } - - /* To enable auto-checked simulation */ - if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) - || (true == verilog_testbench_opts.print_top_testbench()) ) { - print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1); - fp << std::endl; - } - - /* To enable pre-configured FPGA simulation */ - if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) { - print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1); - fp << std::endl; - } - - /* To enable pre-configured FPGA simulation */ - if (true == verilog_testbench_opts.print_preconfig_top_testbench()) { - print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1); - fp << std::endl; - } - - /* Close the file stream */ - fp.close(); -} - } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h index 0fdf2338b..5adca1f1c 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h @@ -21,17 +21,21 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager, const std::string& src_dir, const CircuitLibrary& circuit_lib); -void print_verilog_testbench_include_netlists(const std::string& src_dir, - const std::string& circuit_name, - const std::string& fabric_netlist_file, - const std::string& reference_benchmark_file); +void print_verilog_full_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file, + const bool& no_self_checking); + +void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir, + const std::string& circuit_name, + const std::string& fabric_netlist_file, + const std::string& reference_benchmark_file, + const bool& no_self_checking); void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, const FabricVerilogOption& fabric_verilog_opts); -void print_verilog_simulation_preprocessing_flags(const std::string& src_dir, - const VerilogTestbenchOption& verilog_testbench_opts); - } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h index 0275a40a7..639c1575a 100644 --- a/openfpga/src/fpga_verilog/verilog_constants.h +++ b/openfpga/src/fpga_verilog/verilog_constants.h @@ -7,18 +7,8 @@ constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v"; constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation -constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation -constexpr char* VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation -constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification -constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification -constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification - constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms"; -// Icarus variables and flag -constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches -// End of Icarus variables and flag - constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v"; constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; constexpr char* VERILOG_TOP_POSTFIX = "_top.v"; @@ -27,7 +17,6 @@ constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_autocheck_top_tb.v"; /* !!! must be consist with the modelsim_autocheck_testbench_module_postfix */ constexpr char* RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_formal_random_top_tb.v"; constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v"; -constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v"; constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v"; constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v"; constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v"; diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 860cc39a8..47fc6a13d 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -16,9 +16,11 @@ /* Headers from openfpgautil library */ #include "openfpga_port.h" #include "openfpga_digest.h" +#include "openfpga_reserved_words.h" #include "openfpga_atom_netlist_utils.h" #include "simulation_utils.h" +#include "fabric_global_port_info_utils.h" #include "verilog_constants.h" #include "verilog_writer_utils.h" @@ -39,7 +41,6 @@ constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT"; constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT"; constexpr char* ERROR_COUNTER = "nb_error"; constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start"; -constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; /******************************************************************** * Print the module ports for the Verilog testbench @@ -55,12 +56,13 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, const std::string& circuit_name, const std::vector& clock_port_names, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation) { + const VprNetlistAnnotation& netlist_annotation, + const VerilogTestbenchOption& options) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_default_net_type_declaration(fp, - VERILOG_DEFAULT_NET_TYPE_NONE); + options.default_net_type()); /* Print the declaration for the module */ fp << "module " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ";" << std::endl; @@ -82,16 +84,17 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), - std::string(AUTOCHECKED_SIMULATION_FLAG)); + options.no_self_checking()); /* Instantiate an integer to count the number of error * and determine if the simulation succeed or failed */ - print_verilog_comment(fp, std::string("----- Error counter -------")); - fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; + if (!options.no_self_checking()) { + print_verilog_comment(fp, std::string("----- Error counter -------")); + fp << "\tinteger " << ERROR_COUNTER << "= 0;" << std::endl; + /* Add an empty line as splitter */ + fp << std::endl; + } } /******************************************************************** @@ -102,13 +105,12 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - + /* Instanciate benchmark */ print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); /* Do NOT use explicit port mapping here: @@ -124,18 +126,13 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(BENCHMARK_PORT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); /* Add an empty line as splitter */ fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; } /******************************************************************** @@ -160,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, + PinConstraints(), explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); @@ -168,6 +166,82 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Generate random stimulus for the reset port + * This function is designed to drive the reset port of a benchmark module + * The reset signal will be + * - enabled in the 1st clock cycle + * - disabled in the rest of clock cycles + *******************************************************************/ +static +void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, + const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names, + const BasicPort& clock_port) { + valid_file_stream(fp); + + print_verilog_comment(fp, "----- Begin reset signal generation -----"); + + for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { + /* Bypass non-input atom blocks ! */ + if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) { + continue; + } + + /* The block may be renamed as it contains special characters which violate Verilog syntax */ + std::string block_name = atom_ctx.nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + + /* Bypass clock ports because their stimulus cannot be random */ + if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) { + continue; + } + + /* Bypass any constained net that are mapped to a global port of the FPGA fabric + * because their stimulus cannot be random + */ + if (false == port_is_fabric_global_reset_port(global_ports, module_manager, pin_constraints.net_pin(block_name))) { + continue; + } + + /* Generete stimuli for this net which is how reset signal works */ + BasicPort reset_port(block_name, 1); + size_t initial_value = 1; + if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { + initial_value = 0; + } + + fp << "initial" << std::endl; + fp << "\tbegin" << std::endl; + fp << "\t"; + std::vector initial_values(reset_port.get_width(), initial_value); + fp << "\t"; + fp << generate_verilog_port_constant_values(reset_port, initial_values); + fp << ";" << std::endl; + + /* Flip the reset at the second negative edge of the clock port + * So the generic reset stimuli is applicable to both synchronous reset and asynchronous reset + * This is because the reset is activated in a complete clock cycle + * This gaurantees that even for synchronous reset, the reset can be sensed in the 1st rising/falling + * edge of the clock signal + */ + fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; + fp << "\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ");" << std::endl; + print_verilog_register_connection(fp, reset_port, reset_port, true); + fp << "\tend" << std::endl; + } + + print_verilog_comment(fp, "----- End reset signal generation -----"); + + fp << std::endl; +} + /********************************************************************* * Top-level function in this file: * Create a Verilog testbench using random input vectors @@ -197,9 +271,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const SimulationSetting& simulation_parameters, - const bool& explicit_port_mapping) { + const VerilogTestbenchOption &options) { std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'"); /* Start time count */ @@ -220,17 +296,20 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Start of testbench */ - print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation); + print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation, options); /* Call defined top-level module */ print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation, - explicit_port_mapping); + options.explicit_port_mapping()); /* Call defined benchmark */ - print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, - atom_ctx, netlist_annotation, - explicit_port_mapping); + if (!options.no_self_checking()) { + print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, + atom_ctx, netlist_annotation, + pin_constraints, + options.explicit_port_mapping()); + } /* Find clock port to be used */ std::vector clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME)); @@ -240,37 +319,53 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, pin_constraints, simulation_parameters, clock_ports); + /* TODO: use the first clock now because we do not have information how the reset is + * correlated to clock ports. Once we have such information, the limitation should be removed! + */ + print_verilog_random_testbench_reset_stimuli(fp, + atom_ctx, + netlist_annotation, + module_manager, + global_ports, + pin_constraints, + clock_port_names, + clock_ports[0]); + print_verilog_testbench_random_stimuli(fp, atom_ctx, netlist_annotation, + module_manager, + global_ports, + pin_constraints, clock_port_names, std::string(CHECKFLAG_PORT_POSTFIX), - clock_ports); + clock_ports, + options.no_self_checking()); - print_verilog_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(FORMAL_TB_SIM_START_PORT_NAME), - std::string(BENCHMARK_PORT_POSTFIX), - std::string(FPGA_PORT_POSTFIX), - std::string(CHECKFLAG_PORT_POSTFIX), - std::string(ERROR_COUNTER), - atom_ctx, - netlist_annotation, - clock_port_names, - std::string(DEFAULT_CLOCK_NAME)); + if (!options.no_self_checking()) { + print_verilog_testbench_check(fp, + std::string(FORMAL_TB_SIM_START_PORT_NAME), + std::string(BENCHMARK_PORT_POSTFIX), + std::string(FPGA_PORT_POSTFIX), + std::string(CHECKFLAG_PORT_POSTFIX), + std::string(ERROR_COUNTER), + atom_ctx, + netlist_annotation, + clock_port_names, + std::string(DEFAULT_CLOCK_NAME)); + } - float simulation_time = find_operating_phase_simulation_time(MAGIC_NUMBER_FOR_SIMULATION_TIME, - simulation_parameters.num_clock_cycles(), + float simulation_time = find_operating_phase_simulation_time(simulation_parameters.num_clock_cycles(), 1./simulation_parameters.default_operating_clock_frequency(), VERILOG_SIM_TIMESCALE); /* Add Icarus requirement */ print_verilog_timeout_and_vcd(fp, - std::string(ICARUS_SIMULATOR_FLAG), std::string(circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)), std::string(circuit_name + std::string("_formal.vcd")), std::string(FORMAL_TB_SIM_START_PORT_NAME), std::string(ERROR_COUNTER), - simulation_time); + simulation_time, + options.no_self_checking()); /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h index d89652df9..d58bae969 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h @@ -7,7 +7,10 @@ #include #include "vpr_context.h" #include "pin_constraints.h" +#include "module_manager.h" +#include "fabric_global_port_info.h" #include "simulation_setting.h" +#include "verilog_testbench_options.h" /******************************************************************** * Function declaration @@ -20,9 +23,11 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const SimulationSetting& simulation_parameters, - const bool& explicit_port_mapping); + const VerilogTestbenchOption &options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 542eadc2e..e797151a8 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -135,16 +135,10 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, BasicPort module_clock_pin(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]); /* If the clock port name is in the pin constraints, we should wire it to the constrained pin */ - std::string constrained_net_name; - for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) { - if (module_clock_pin == pin_constraints.pin(pin_constraint)) { - constrained_net_name = pin_constraints.net(pin_constraint); - break; - } - } + std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin); /* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */ - if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name) + if ( (true == pin_constraints.unmapped_net(constrained_net_name)) || (true == benchmark_clock_port_names.empty())) { std::vector default_values(1, fabric_global_ports.global_port_default_value(global_port_id)); print_verilog_wire_constant_values(fp, module_clock_pin, default_values); @@ -152,7 +146,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, } std::string clock_name_to_connect; - if (!constrained_net_name.empty()) { + if (!pin_constraints.unconstrained_net(constrained_net_name)) { clock_name_to_connect = constrained_net_name; } else { /* Otherwise, we must have a clear one-to-one clock net corresponding!!! */ @@ -173,8 +167,27 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, } /* For other ports, give an default value */ - std::vector default_values(module_global_port.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); - print_verilog_wire_constant_values(fp, module_global_port, default_values); + for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) { + BasicPort module_global_pin(module_global_port.get_name(), + module_global_port.pins()[pin_id], + module_global_port.pins()[pin_id]); + + /* If the global port name is in the pin constraints, we should wire it to the constrained pin */ + std::string constrained_net_name = pin_constraints.pin_net(module_global_pin); + + /* - If constrained to a given net in the benchmark, we connect the global pin to the net + * - If constrained to an open net in the benchmark, we assign it to a default value + */ + if ( (false == pin_constraints.unconstrained_net(constrained_net_name)) + && (false == pin_constraints.unmapped_net(constrained_net_name))) { + BasicPort benchmark_pin(constrained_net_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1); + print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false); + } else { + VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name); + std::vector default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); + print_verilog_wire_constant_values(fp, module_global_pin, default_values); + } + } } print_verilog_comment(fp, std::string("----- End Connect Global ports of FPGA top module -----")); @@ -191,16 +204,18 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, * while uses 'force' syntax to impost the bitstream at mem_inv port *******************************************************************/ static -void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, - const ModuleManager &module_manager, - const ModuleId &top_module, - const BitstreamManager &bitstream_manager, - const bool& output_datab_bits) { +void print_verilog_preconfig_top_module_force_bitstream(std::fstream &fp, + const ModuleManager &module_manager, + const ModuleId &top_module, + const BitstreamManager &bitstream_manager, + const bool& output_datab_bits) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment(fp, std::string("----- Begin assign bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; + for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) { /* We only cares blocks with configuration bits */ if (0 == bitstream_manager.block_bits(config_block_id).size()) { @@ -229,31 +244,9 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { config_data_values.push_back(bitstream_manager.bit_value(config_bit)); } - print_verilog_wire_constant_values(fp, config_data_port, config_data_values); - } - - if (true == output_datab_bits) { - fp << "initial begin" << std::endl; - - for (const ConfigBlockId &config_block_id : bitstream_manager.blocks()) { - /* We only cares blocks with configuration bits */ - if (0 == bitstream_manager.block_bits(config_block_id).size()) { - continue; - } - /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); - /* Drop the first block, which is the top module, it should be replaced by the instance name here */ - /* Ensure that this is the module we want to drop! */ - VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); - block_hierarchy.erase(block_hierarchy.begin()); - /* Build the full hierarchy path */ - std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME); - for (const ConfigBlockId &temp_block : block_hierarchy) { - bit_hierarchy_path += std::string("."); - bit_hierarchy_path += bitstream_manager.block_name(temp_block); - } - bit_hierarchy_path += std::string("."); + print_verilog_force_wire_constant_values(fp, config_data_port, config_data_values); + if (true == output_datab_bits) { /* Find the bit index in the parent block */ BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(), bitstream_manager.block_bits(config_block_id).size()); @@ -264,10 +257,10 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream &fp, } print_verilog_force_wire_constant_values(fp, config_datab_port, config_datab_values); } - - fp << "end" << std::endl; } + fp << "end" << std::endl; + print_verilog_comment(fp, std::string("----- End assign bitstream to configuration memories -----")); } @@ -351,7 +344,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, const ModuleId &top_module, const CircuitLibrary& circuit_lib, const CircuitModelId& mem_model, - const BitstreamManager &bitstream_manager) { + const BitstreamManager &bitstream_manager, + const e_embedded_bitstream_hdl_type& embedded_bitstream_hdl_type) { /* Skip the datab port if there is only 1 output port in memory model * Currently, it assumes that the data output port is always defined while datab is optional @@ -366,21 +360,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp, print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); - print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG)); - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, - bitstream_manager, - output_datab_bits); - - fp << "`else" << std::endl; - - /* Use assign syntax for Icarus simulator */ - print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, + if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) { + print_verilog_preconfig_top_module_force_bitstream(fp, module_manager, top_module, bitstream_manager, output_datab_bits); - - print_verilog_endif(fp); + /* Use deposit syntax for other simulators */ + } else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) { + print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, + bitstream_manager, + output_datab_bits); + } print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } @@ -429,7 +419,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, const VprNetlistAnnotation &netlist_annotation, const std::string &circuit_name, const std::string &verilog_fname, - const bool &explicit_port_mapping) { + const VerilogTestbenchOption& options) { std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'"); int status = CMD_EXEC_SUCCESS; @@ -449,7 +439,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, print_verilog_file_header(fp, title); print_verilog_default_net_type_declaration(fp, - VERILOG_DEFAULT_NET_TYPE_NONE); + options.default_net_type()); /* Print module declaration and ports */ print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation); @@ -464,7 +454,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, /* Instanciate FPGA top-level module */ print_verilog_testbench_fpga_instance(fp, module_manager, top_module, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), - explicit_port_mapping); + options.explicit_port_mapping()); /* Find clock ports in benchmark */ std::vector benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); @@ -489,17 +479,23 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager, CircuitModelId sram_model = config_protocol.memory_model(); VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model)); - /* Assign FPGA internal SRAM/Memory ports to bitstream values */ + /* Assign FPGA internal SRAM/Memory ports to bitstream values, only output when needed */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, circuit_lib, sram_model, - bitstream_manager); + bitstream_manager, + options.embedded_bitstream_hdl_type()); - /* Add signal initialization */ - print_verilog_testbench_signal_initialization(fp, - std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), - circuit_lib, - module_manager, - top_module); + /* Add signal initialization: + * Bypass writing codes to files due to the autogenerated codes are very large. + */ + if (true == options.include_signal_init()) { + print_verilog_testbench_signal_initialization(fp, + std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME), + circuit_lib, + module_manager, + top_module, + false); + } /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h index ff82dea94..01bb12f08 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h @@ -15,6 +15,7 @@ #include "fabric_global_port_info.h" #include "config_protocol.h" #include "vpr_netlist_annotation.h" +#include "verilog_testbench_options.h" /******************************************************************** * Function declaration @@ -35,7 +36,7 @@ int print_verilog_preconfig_top_module(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, - const bool& explicit_port_mapping); + const VerilogTestbenchOption& options); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp index eb9bf94d9..9ed82a131 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp @@ -13,6 +13,7 @@ #include "vtr_time.h" /* Headers from openfpgautil library */ +#include "openfpga_scale.h" #include "openfpga_digest.h" #include "openfpga_reserved_words.h" @@ -31,6 +32,7 @@ namespace openfpga { * information, in order to interface different Verilog simulators ********************************************************************/ void print_verilog_simulation_info(const std::string& ini_fname, + const VerilogTestbenchOption& options, const std::string& circuit_name, const std::string& src_dir, const AtomContext& atom_ctx, @@ -57,24 +59,39 @@ void print_verilog_simulation_info(const std::string& ini_fname, VTR_ASSERT(true != ini_fname.empty()); mINI::INIStructure ini; - // std::map units_map; - // units_map['s']=1; // units_map['ms']=1E-3; // units_map['us']=1E-6; - // units_map['ns']=1E-9; // units_map['ps']=1E-12; // units_map['fs']=1E-15; - /* Compute simulation time period */ - float simulation_time_period = find_simulation_time_period(1E-3, - num_program_clock_cycles, - 1. / prog_clock_freq, - num_operating_clock_cycles, - 1. / op_clock_freq); + /* Compute simulation time period: full testbench and pre-configured testbench has different length + * Currently, we only support the two types. And one of them must be enabled when outputting this file + */ + float simulation_time_period = 0.; + if (options.print_top_testbench()) { + simulation_time_period = find_simulation_time_period(options.time_unit(), + num_program_clock_cycles, + 1. / prog_clock_freq, + num_operating_clock_cycles, + 1. / op_clock_freq); + } else { + VTR_ASSERT(options.print_preconfig_top_testbench()); + simulation_time_period = find_operating_phase_simulation_time(num_operating_clock_cycles, + 1. / op_clock_freq, + options.time_unit()); + } + /* Identify the testbench file name depending on the type */ + std::string top_tb_name; + if (options.print_top_testbench()) { + top_tb_name = circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); + } else { + VTR_ASSERT(options.print_preconfig_top_testbench()); + top_tb_name = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX); + } /* Basic information */ ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject"; ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name; - ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX); + ini["SIMULATION_DECK"]["TOP_TB"] = top_tb_name; ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period); - ini["SIMULATION_DECK"]["UNIT "] = "ms"; + ini["SIMULATION_DECK"]["UNIT "] = unit_to_string(options.time_unit()); ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX)); diff --git a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h index 8806a71ac..9493a4e68 100644 --- a/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h +++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h @@ -9,6 +9,7 @@ #include "config_protocol.h" #include "vpr_context.h" #include "io_location_map.h" +#include "verilog_testbench_options.h" /******************************************************************** * Function declaration @@ -18,6 +19,7 @@ namespace openfpga { void print_verilog_simulation_info(const std::string& ini_fname, + const VerilogTestbenchOption& options, const std::string& circuit_name, const std::string& src_dir, const AtomContext& atom_ctx, diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp index b39adef43..2af484a46 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp @@ -21,8 +21,10 @@ VerilogTestbenchOption::VerilogTestbenchOption() { print_top_testbench_ = false; simulation_ini_path_.clear(); explicit_port_mapping_ = false; - support_icarus_simulator_ = false; include_signal_init_ = false; + default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM; + time_unit_ = 1E-3; verbose_output_ = false; } @@ -73,8 +75,20 @@ bool VerilogTestbenchOption::include_signal_init() const { return include_signal_init_; } -bool VerilogTestbenchOption::support_icarus_simulator() const { - return support_icarus_simulator_; +bool VerilogTestbenchOption::no_self_checking() const { + return reference_benchmark_file_path_.empty(); +} + +e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const { + return default_net_type_; +} + +float VerilogTestbenchOption::time_unit() const { + return time_unit_; +} + +e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_type() const { + return embedded_bitstream_hdl_type_; } bool VerilogTestbenchOption::verbose_output() const { @@ -137,8 +151,39 @@ void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) { include_signal_init_ = enabled; } -void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) { - support_icarus_simulator_ = enabled; +void VerilogTestbenchOption::set_default_net_type(const std::string& default_net_type) { + /* Decode from net type string */; + if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) { + default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; + } else if (default_net_type == std::string(VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE])) { + default_net_type_ = VERILOG_DEFAULT_NET_TYPE_WIRE; + } else { + VTR_LOG_WARN("Invalid default net type: '%s'! Expect ['%s'|'%s']\n", + default_net_type.c_str(), + VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE], + VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE]); + } +} + +void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type) { + /* Decode from HDL type string */; + if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) { + embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES; + } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG])) { + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG; + } else if (embedded_bitstream_hdl_type == std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM])) { + embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM; + } else { + VTR_LOG_WARN("Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n", + embedded_bitstream_hdl_type.c_str(), + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES], + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG], + EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]); + } +} + +void VerilogTestbenchOption::set_time_unit(const float& time_unit) { + time_unit_ = time_unit; } void VerilogTestbenchOption::set_verbose_output(const bool& enabled) { diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h index 492740f8e..23481c2b6 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_options.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h @@ -5,10 +5,20 @@ * Include header files required by the data structure definition *******************************************************************/ #include +#include "verilog_port_types.h" /* Begin namespace openfpga */ namespace openfpga { +/* Embedded bitstream code style */ +enum e_embedded_bitstream_hdl_type { + EMBEDDED_BITSTREAM_HDL_IVERILOG, + EMBEDDED_BITSTREAM_HDL_MODELSIM, + NUM_EMBEDDED_BITSTREAM_HDL_TYPES +}; + +constexpr std::array EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types + /******************************************************************** * Options for Verilog Testbench generator * Typicall usage: @@ -33,7 +43,10 @@ class VerilogTestbenchOption { std::string simulation_ini_path() const; bool explicit_port_mapping() const; bool include_signal_init() const; - bool support_icarus_simulator() const; + bool no_self_checking() const; + e_verilog_default_net_type default_net_type() const; + e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const; + float time_unit() const; bool verbose_output() const; public: /* Public validator */ bool validate() const; @@ -57,7 +70,9 @@ class VerilogTestbenchOption { void set_print_simulation_ini(const std::string& simulation_ini_path); void set_explicit_port_mapping(const bool& enabled); void set_include_signal_init(const bool& enabled); - void set_support_icarus_simulator(const bool& enabled); + void set_default_net_type(const std::string& default_net_type); + void set_time_unit(const float& time_unit); + void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type); void set_verbose_output(const bool& enabled); private: /* Internal Data */ std::string output_directory_; @@ -70,8 +85,10 @@ class VerilogTestbenchOption { /* Print simulation ini is enabled only when the path is not empty */ std::string simulation_ini_path_; bool explicit_port_mapping_; - bool support_icarus_simulator_; bool include_signal_init_; + e_verilog_default_net_type default_net_type_; + e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_; + float time_unit_; bool verbose_output_; }; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index b445e07f9..3542cdcfc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -21,6 +21,7 @@ #include "verilog_port_types.h" #include "module_manager_utils.h" +#include "fabric_global_port_info_utils.h" #include "verilog_constants.h" #include "verilog_writer_utils.h" @@ -68,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -98,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, if (true == use_explicit_port_map) { fp << "." << block_name << module_input_port_postfix << "("; } + + /* Polarity of some input may have to be inverted, as defined in pin constraints + * For example, the reset signal of the benchmark is active low + * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) + * However, to ensure correct stimuli to the benchmark, we have to invert the signal + */ + if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + fp << "~"; + } fp << block_name; if (true == use_explicit_port_map) { fp << ")"; @@ -299,29 +310,23 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, * Note that: these codes are tuned for Icarus simulator!!! *******************************************************************/ void print_verilog_timeout_and_vcd(std::fstream& fp, - const std::string& icarus_preprocessing_flag, const std::string& module_name, const std::string& vcd_fname, const std::string& simulation_start_counter_name, const std::string& error_counter_name, - const float& simulation_time) { + const float& simulation_time, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); - /* The following verilog codes are tuned for Icarus */ - print_verilog_preprocessing_flag(fp, icarus_preprocessing_flag); - - print_verilog_comment(fp, std::string("----- Begin Icarus requirement -------")); + print_verilog_comment(fp, std::string("----- Begin output waveform to VCD file-------")); fp << "\tinitial begin" << std::endl; fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; fp << "\t\t$dumpvars(1, " << module_name << ");" << std::endl; fp << "\tend" << std::endl; - /* Condition ends for the Icarus requirement */ - print_verilog_endif(fp); - - print_verilog_comment(fp, std::string("----- END Icarus requirement -------")); + print_verilog_comment(fp, std::string("----- END output waveform to VCD file -------")); /* Add an empty line as splitter */ fp << std::endl; @@ -329,16 +334,27 @@ void print_verilog_timeout_and_vcd(std::fstream& fp, BasicPort sim_start_port(simulation_start_counter_name, 1); fp << "initial begin" << std::endl; - fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; + + if (!no_self_checking) { + fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl; + } + fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; fp << "\t$display(\"Simulation start\");" << std::endl; print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------")); fp << "\t#" << std::setprecision(10) << simulation_time << std::endl; - fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl; - fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; - fp << "\tend else begin" << std::endl; - fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl; - fp << "\tend" << std::endl; + + if (!no_self_checking) { + fp << "\tif(" << error_counter_name << " == 0) begin" << std::endl; + fp << "\t\t$display(\"Simulation Succeed\");" << std::endl; + fp << "\tend else begin" << std::endl; + fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << error_counter_name << ");" << std::endl; + fp << "\tend" << std::endl; + } else { + VTR_ASSERT_SAFE(no_self_checking); + fp << "\t$display(\"Simulation Succeed\");" << std::endl; + } + fp << "\t$finish;" << std::endl; fp << "end" << std::endl; @@ -372,7 +388,6 @@ std::vector generate_verilog_testbench_clock_port(const std::vector
 clock_ports = generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); @@ -466,9 +479,6 @@ void print_verilog_testbench_check(std::fstream& fp, fp << std::endl; } - /* Condition ends */ - print_verilog_endif(fp); - /* Add an empty line as splitter */ fp << std::endl; } @@ -537,9 +547,13 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp, void print_verilog_testbench_random_stimuli(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const std::vector& clock_port_names, const std::string& check_flag_port_postfix, - const std::vector& clock_ports) { + const std::vector& clock_ports, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -560,36 +574,45 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, block_name = netlist_annotation.block_name(atom_blk); } - /* Bypass clock ports */ + /* Bypass clock ports because their stimulus cannot be random */ if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) { continue; } + /* Bypass any constained net that are mapped to a global port of the FPGA fabric + * because their stimulus cannot be random + */ + if (true == port_is_fabric_global_reset_port(global_ports, module_manager, pin_constraints.net_pin(block_name))) { + continue; + } + /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { fp << "\t\t" << block_name << " <= 1'b0;" << std::endl; } } - /* Add an empty line as splitter */ - fp << std::endl; - /* Set 0 to registers for checking flags */ - for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { - /* Bypass non-I/O atom blocks ! */ - if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { - continue; + if (!no_self_checking) { + /* Add an empty line as splitter */ + fp << std::endl; + + for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { + /* Bypass non-I/O atom blocks ! */ + if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { + continue; + } + + /* The block may be renamed as it contains special characters which violate Verilog syntax */ + std::string block_name = atom_ctx.nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + + /* Each logical block assumes a single-width port */ + BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; } - - /* The block may be renamed as it contains special characters which violate Verilog syntax */ - std::string block_name = atom_ctx.nlist.block_name(atom_blk); - if (true == netlist_annotation.is_block_renamed(atom_blk)) { - block_name = netlist_annotation.block_name(atom_blk); - } - - /* Each logical block assumes a single-width port */ - BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1); - fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << " <= 1'b0;" << std::endl; } fp << "\tend" << std::endl; @@ -620,11 +643,18 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, block_name = netlist_annotation.block_name(atom_blk); } - /* Bypass clock ports */ + /* Bypass clock ports because their stimulus cannot be random */ if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) { continue; } + /* Bypass any constained net that are mapped to a global port of the FPGA fabric + * because their stimulus cannot be random + */ + if (true == port_is_fabric_global_reset_port(global_ports, module_manager, pin_constraints.net_pin(block_name))) { + continue; + } + /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { fp << "\t\t" << block_name << " <= $random;" << std::endl; @@ -653,7 +683,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, - const std::string& autocheck_preprocessing_flag) { + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -707,11 +737,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(autocheck_preprocessing_flag)); - - /* Add an empty line as splitter */ - fp << std::endl; + if (no_self_checking) { + return; + } /* Instantiate wire for benchmark output */ print_verilog_comment(fp, std::string("----- Benchmark outputs -------")); @@ -756,12 +784,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, /* Add an empty line as splitter */ fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; } /******************************************************************** @@ -780,7 +802,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst const std::vector& circuit_input_ports, const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module) { + const ModuleId& primitive_module, + const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -808,7 +831,8 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst child_hie_path, circuit_lib, circuit_model, circuit_input_ports, module_manager, child_module, - primitive_module); + primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -817,7 +841,6 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; - fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl; for (const auto& input_port : circuit_input_ports) { /* Only for formal verification: deposite a zero signal values */ @@ -827,22 +850,17 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst fp << "\t\t$deposit("; fp << child_hie_path << "."; fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false); - fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); - fp << ");" << std::endl; - } - fp << "\t`else" << std::endl; + + if (!deposit_random_values) { - /* Regular case: deposite initial signal values: a random value */ - for (const auto& input_port : circuit_input_ports) { - BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port)); - input_port_info.set_origin_port_width(input_port_info.get_width()); - fp << "\t\t$deposit("; - fp << child_hie_path << "."; - fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info, false); - fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl; + fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0'); + fp << ");" << std::endl; + } else { + VTR_ASSERT_SAFE(deposit_random_values); + fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl; + } } - fp << "\t`endif\n" << std::endl; fp << "\tend" << std::endl; print_verilog_comment(fp, std::string("------ END driver initialization -----")); } @@ -860,7 +878,8 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, const std::string& top_instance_name, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module) { + const ModuleId& top_module, + const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -900,7 +919,6 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, /* Add signal initialization Verilog codes */ fp << std::endl; - fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl; for (const CircuitModelId& signal_init_circuit_model : signal_init_circuit_models) { /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module(circuit_lib.model_name(signal_init_circuit_model)); @@ -911,10 +929,9 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp, top_instance_name, circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, top_module, - primitive_module); + primitive_module, + deposit_random_values); } - - fp << "`endif" << std::endl; } } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index a2eca17cd..d06f267c9 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -12,6 +12,7 @@ #include "vpr_context.h" #include "io_location_map.h" #include "vpr_netlist_annotation.h" +#include "fabric_global_port_info.h" #include "pin_constraints.h" #include "simulation_setting.h" @@ -22,9 +23,6 @@ /* begin namespace openfpga */ namespace openfpga { -constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:"; -constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_"; - void print_verilog_testbench_fpga_instance(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, @@ -40,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map); void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, @@ -54,18 +53,17 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, const size_t& unused_io_value); void print_verilog_timeout_and_vcd(std::fstream& fp, - const std::string& icarus_preprocessing_flag, const std::string& module_name, const std::string& vcd_fname, const std::string& simulation_start_counter_name, const std::string& error_counter_name, - const float& simulation_time); + const float& simulation_time, + const bool& no_self_checking); std::vector generate_verilog_testbench_clock_port(const std::vector& clock_port_names, const std::string& default_clock_name); void print_verilog_testbench_check(std::fstream& fp, - const std::string& autochecked_preprocessing_flag, const std::string& simulation_start_counter_name, const std::string& benchmark_port_postfix, const std::string& fpga_port_postfix, @@ -84,9 +82,13 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp, void print_verilog_testbench_random_stimuli(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const std::vector& clock_port_names, const std::string& check_flag_port_postfix, - const std::vector& clock_ports); + const std::vector& clock_ports, + const bool& no_self_checking); void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, @@ -95,13 +97,14 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, - const std::string& autocheck_preprocessing_flag); + const bool& no_self_checking); void print_verilog_testbench_signal_initialization(std::fstream& fp, const std::string& top_instance_name, const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module); + const ModuleId& top_module, + const bool& deposit_random_values); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 828779ec6..e4778c292 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -22,6 +22,7 @@ #include "simulation_utils.h" #include "openfpga_atom_netlist_utils.h" +#include "fast_configuration.h" #include "fabric_bitstream_utils.h" #include "fabric_global_port_info_utils.h" @@ -47,7 +48,6 @@ constexpr char* TOP_TESTBENCH_PROG_TASK_NAME = "prog_cycle_task"; constexpr char* TOP_TESTBENCH_SIM_START_PORT_NAME = "sim_start"; -constexpr int TOP_TESTBENCH_MAGIC_NUMBER_FOR_SIMULATION_TIME = 200; constexpr char* TOP_TESTBENCH_ERROR_COUNTER = "nb_error"; constexpr char* TOP_TB_RESET_PORT_NAME = "greset"; @@ -60,6 +60,12 @@ constexpr char* TOP_TB_OP_CLOCK_PORT_PREFIX = "operating_clk_"; constexpr char* TOP_TB_PROG_CLOCK_PORT_NAME = "prog_clock"; constexpr char* TOP_TB_INOUT_REG_POSTFIX = "_reg"; constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg"; +constexpr char* TOP_TB_BITSTREAM_LENGTH_VARIABLE = "BITSTREAM_LENGTH"; +constexpr char* TOP_TB_BITSTREAM_WIDTH_VARIABLE = "BITSTREAM_WIDTH"; +constexpr char* TOP_TB_BITSTREAM_MEM_REG_NAME = "bit_mem"; +constexpr char* TOP_TB_BITSTREAM_INDEX_REG_NAME = "bit_index"; +constexpr char* TOP_TB_BITSTREAM_ITERATOR_REG_NAME = "ibit"; +constexpr char* TOP_TB_BITSTREAM_SKIP_FLAG_REG_NAME = "skip_bits"; constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb"; @@ -258,21 +264,17 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, } /******************************************************************** - * Wire the global ports of FPGA fabric to local wires + * Wire the global clock ports of FPGA fabric to local wires *******************************************************************/ static -void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const FabricGlobalPortInfo& fabric_global_port_info, - const SimulationSetting& simulation_parameters, - const bool& active_global_prog_reset, - const bool& active_global_prog_set) { +void print_verilog_top_testbench_global_clock_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info, + const SimulationSetting& simulation_parameters) { /* Validate the file stream */ valid_file_stream(fp); - print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----")); - /* Connect global clock ports to operating or programming clock signal */ for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) { if (false == fabric_global_port_info.global_port_is_clock(fabric_global_port)) { @@ -317,6 +319,18 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, 1 == fabric_global_port_info.global_port_default_value(fabric_global_port)); } } +} + +/******************************************************************** + * Wire the global config done ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_global_config_done_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info) { + /* Validate the file stream */ + valid_file_stream(fp); /* Connect global configuration done ports to configuration done signal */ for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) { @@ -341,6 +355,20 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, stimuli_config_done_port, 1 == fabric_global_port_info.global_port_default_value(fabric_global_port)); } +} + +/******************************************************************** + * Wire the global reset ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const PinConstraints& pin_constraints, + const FabricGlobalPortInfo& fabric_global_port_info, + const bool& active_global_prog_reset) { + /* Validate the file stream */ + valid_file_stream(fp); /* Connect global reset ports to operating or programming reset signal */ for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) { @@ -373,20 +401,58 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME)); stimuli_reset_port.set_width(1); } - /* Wire the port to the input stimuli: - * The wiring will be inverted if the default value of the global port is 1 - * Otherwise, the wiring will not be inverted! - */ - if (true == activate) { - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_reset_port, - 1 == fabric_global_port_info.global_port_default_value(fabric_global_port)); - } else { - VTR_ASSERT_SAFE(false == activate); - print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), - std::vector(1, fabric_global_port_info.global_port_default_value(fabric_global_port))); + + BasicPort module_global_port_info = module_manager.module_port(top_module, module_global_port); + + for (size_t pin_id = 0; pin_id < module_global_port_info.pins().size(); ++pin_id) { + BasicPort module_global_pin(module_global_port_info.get_name(), + module_global_port_info.pins()[pin_id], + module_global_port_info.pins()[pin_id]); + + /* Regular reset port can be mapped by a net from user design */ + if (false == fabric_global_port_info.global_port_is_prog(fabric_global_port)) { + /* If the global port name is in the pin constraints, we should wire it to the constrained pin */ + std::string constrained_net_name = pin_constraints.pin_net(module_global_pin); + + /* - If constrained to a given net in the benchmark, we connect the global pin to the net */ + if ( (false == pin_constraints.unconstrained_net(constrained_net_name)) + && (false == pin_constraints.unmapped_net(constrained_net_name))) { + BasicPort benchmark_pin(constrained_net_name, 1); + print_verilog_wire_connection(fp, module_global_pin, + benchmark_pin, + false); + continue; /* Finish the net assignment for this reset pin */ + } + } + + /* Wire the port to the input stimuli: + * The wiring will be inverted if the default value of the global port is 1 + * Otherwise, the wiring will not be inverted! + */ + if (true == activate) { + print_verilog_wire_connection(fp, module_global_pin, + stimuli_reset_port, + 1 == fabric_global_port_info.global_port_default_value(fabric_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_global_pin, + std::vector(1, fabric_global_port_info.global_port_default_value(fabric_global_port))); + } } } +} + +/******************************************************************** + * Wire the global set ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_global_set_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info, + const bool& active_global_prog_set) { + /* Validate the file stream */ + valid_file_stream(fp); /* Connect global set ports to operating or programming set signal */ for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) { @@ -438,6 +504,18 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, std::vector(1, fabric_global_port_info.global_port_default_value(fabric_global_port))); } } +} + +/******************************************************************** + * Wire the regular global ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_regular_global_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricGlobalPortInfo& fabric_global_port_info) { + /* Validate the file stream */ + valid_file_stream(fp); /* For the rest of global ports, wire them to constant signals */ for (const FabricGlobalPortId& fabric_global_port : fabric_global_port_info.global_ports()) { @@ -478,6 +556,55 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, std::vector default_values(module_port.get_width(), fabric_global_port_info.global_port_default_value(fabric_global_port)); print_verilog_wire_constant_values(fp, module_port, default_values); } +} + +/******************************************************************** + * Wire the global ports of FPGA fabric to local wires + *******************************************************************/ +static +void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& top_module, + const PinConstraints& pin_constraints, + const FabricGlobalPortInfo& fabric_global_port_info, + const SimulationSetting& simulation_parameters, + const bool& active_global_prog_reset, + const bool& active_global_prog_set) { + /* Validate the file stream */ + valid_file_stream(fp); + + print_verilog_comment(fp, std::string("----- Begin connecting global ports of FPGA fabric to stimuli -----")); + + print_verilog_top_testbench_global_clock_ports_stimuli(fp, + module_manager, + top_module, + fabric_global_port_info, + simulation_parameters); + + print_verilog_top_testbench_global_config_done_ports_stimuli(fp, + module_manager, + top_module, + fabric_global_port_info); + + + print_verilog_top_testbench_global_reset_ports_stimuli(fp, + module_manager, + top_module, + pin_constraints, + fabric_global_port_info, + active_global_prog_reset); + + print_verilog_top_testbench_global_set_ports_stimuli(fp, + module_manager, + top_module, + fabric_global_port_info, + active_global_prog_set); + + + print_verilog_top_testbench_regular_global_ports_stimuli(fp, + module_manager, + top_module, + fabric_global_port_info); print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----")); } @@ -574,12 +701,13 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const PinConstraints& pin_constraints, const SimulationSetting& simulation_parameters, const ConfigProtocol& config_protocol, - const std::string& circuit_name){ + const std::string& circuit_name, + const VerilogTestbenchOption& options) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_default_net_type_declaration(fp, - VERILOG_DEFAULT_NET_TYPE_NONE); + options.default_net_type()); /* Print module definition */ fp << "module " << circuit_name << std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX); @@ -680,13 +808,15 @@ void print_verilog_top_testbench_ports(std::fstream& fp, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::string(AUTOCHECKED_SIMULATION_FLAG)); + options.no_self_checking()); /* Instantiate an integer to count the number of error and * determine if the simulation succeed or failed */ - print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----")); - fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl; + if (!options.no_self_checking()) { + print_verilog_comment(fp, std::string("----- Error counter: Deposit an error for config_done signal is not raised at the beginning -----")); + fp << "\tinteger " << TOP_TESTBENCH_ERROR_COUNTER << "= 1;" << std::endl; + } } /******************************************************************** @@ -782,13 +912,12 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); - /* Benchmark is instanciated conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG)); - + /* Instanciate benchmark */ print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------")); /* Do NOT use explicit port mapping here: @@ -804,241 +933,13 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); /* Add an empty line as splitter */ fp << std::endl; - - /* Condition ends for the benchmark instanciation */ - print_verilog_endif(fp); - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print tasks (processes) in Verilog format, - * which is very useful in generating stimuli for each clock cycle - * This function is tuned for configuration-chain manipulation: - * During each programming cycle, we feed the input of scan chain with a memory bit - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task_configuration_chain(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module) { - - /* Validate the file stream */ - valid_file_stream(fp); - - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); - BasicPort cc_head_port = module_manager.module_port(top_module, cc_head_port_id); - BasicPort cc_head_value(generate_configuration_chain_head_name() + std::string("_val"), cc_head_port.get_width()); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Feed the scan-chain input at each falling edge of programming clock - * It aims at avoid racing the programming clock (scan-chain data changes at the rising edge). - */ - print_verilog_comment(fp, std::string("----- Task: input values during a programming clock cycle -----")); - fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, cc_head_value) << ";" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cc_head_value); - fp << ";" << std::endl; - - fp << "\tend" << std::endl; - fp << "endtask" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print tasks (processes) in Verilog format, - * which is very useful in generating stimuli for each clock cycle - * This function is tuned for memory bank manipulation: - * During each programming cycle, we feed - * - an address to the BL address port of top module - * - an address to the WL address port of top module - * - a data input to the din port of top module - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task_memory_bank(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module) { - - /* Validate the file stream */ - valid_file_stream(fp); - - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - - ModulePortId bl_addr_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_BL_ADDRESS_PORT_NAME)); - BasicPort bl_addr_port = module_manager.module_port(top_module, bl_addr_port_id); - BasicPort bl_addr_value = bl_addr_port; - bl_addr_value.set_name(std::string(MEMORY_BL_PORT_NAME) + std::string("_val")); - - ModulePortId wl_addr_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_WL_ADDRESS_PORT_NAME)); - BasicPort wl_addr_port = module_manager.module_port(top_module, wl_addr_port_id); - BasicPort wl_addr_value = wl_addr_port; - wl_addr_value.set_name(std::string(MEMORY_WL_PORT_NAME) + std::string("_val")); - - ModulePortId din_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_DATA_IN_PORT_NAME)); - BasicPort din_port = module_manager.module_port(top_module, din_port_id); - BasicPort din_value = din_port; - din_value.set_name(std::string(DECODER_DATA_IN_PORT_NAME) + std::string("_val")); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Feed the address and data input at each falling edge of programming clock - * As the enable signal is wired to the programming clock, we should synchronize - * address and data with the enable signal - */ - print_verilog_comment(fp, std::string("----- Task: assign BL and WL address, and data values at rising edge of enable signal -----")); - fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, bl_addr_value) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, wl_addr_value) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_value); - fp << ";" << std::endl; - fp << std::endl; - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_value); - fp << ";" << std::endl; - fp << std::endl; - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, din_value); - fp << ";" << std::endl; - fp << std::endl; - - fp << "\tend" << std::endl; - fp << "endtask" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - - -/******************************************************************** - * Print tasks (processes) in Verilog format, - * which is very useful in generating stimuli for each clock cycle - * This function is tuned for frame-based memory manipulation: - * During each programming cycle, we feed - * - an address to the address port of top module - * - a data input to the din port of top module - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task_frame_decoder(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module) { - - /* Validate the file stream */ - valid_file_stream(fp); - - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - - ModulePortId addr_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_ADDRESS_PORT_NAME)); - BasicPort addr_port = module_manager.module_port(top_module, addr_port_id); - BasicPort addr_value = addr_port; - addr_value.set_name(std::string(DECODER_ADDRESS_PORT_NAME) + std::string("_val")); - - ModulePortId din_port_id = module_manager.find_module_port(top_module, - std::string(DECODER_DATA_IN_PORT_NAME)); - BasicPort din_port = module_manager.module_port(top_module, din_port_id); - BasicPort din_value = din_port; - din_value.set_name(std::string(DECODER_DATA_IN_PORT_NAME) + std::string("_val")); - - /* Add an empty line as splitter */ - fp << std::endl; - - /* Feed the address and data input at each falling edge of programming clock - * As the enable signal is wired to the programming clock, we should synchronize - * address and data with the enable signal - */ - print_verilog_comment(fp, std::string("----- Task: assign address and data values at rising edge of enable signal -----")); - fp << "task " << std::string(TOP_TESTBENCH_PROG_TASK_NAME) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, addr_value) << ";" << std::endl; - fp << generate_verilog_port(VERILOG_PORT_INPUT, din_value) << ";" << std::endl; - fp << "\tbegin" << std::endl; - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_value); - fp << ";" << std::endl; - fp << std::endl; - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port); - fp << " = "; - fp << generate_verilog_port(VERILOG_PORT_CONKT, din_value); - fp << ";" << std::endl; - fp << std::endl; - - fp << "\tend" << std::endl; - fp << "endtask" << std::endl; - - /* Add an empty line as splitter */ - fp << std::endl; -} - -/******************************************************************** - * Print tasks, which is very useful in generating stimuli for each clock cycle - *******************************************************************/ -static -void print_verilog_top_testbench_load_bitstream_task(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, - const ModuleManager& module_manager, - const ModuleId& top_module) { - switch (sram_orgz_type) { - case CONFIG_MEM_STANDALONE: - /* No need to have a specific task. Loading is done in 1 clock cycle */ - break; - case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_load_bitstream_task_configuration_chain(fp, - module_manager, - top_module); - break; - case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_load_bitstream_task_memory_bank(fp, - module_manager, - top_module); - break; - case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_load_bitstream_task_frame_decoder(fp, - module_manager, - top_module); - break; - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid type of SRAM organization!\n"); - exit(1); - } } /******************************************************************** @@ -1248,11 +1149,11 @@ void print_verilog_top_testbench_configuration_protocol_stimulus(std::fstream& f * We will load the bitstream in the second clock cycle, right after the first reset cycle *******************************************************************/ static -void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream) { +void print_verilog_full_testbench_vanilla_bitstream(std::fstream& fp, + const std::string& bitstream_file, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ valid_file_stream(fp); @@ -1266,6 +1167,15 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, ModulePortId wl_port_id = module_manager.find_module_port(top_module, std::string(MEMORY_WL_PORT_NAME)); BasicPort wl_port = module_manager.module_port(top_module, wl_port_id); + /* Define a constant for the bitstream length */ + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_LENGTH_VARIABLE), fabric_bitstream.num_bits()); + + /* Declare local variables for bitstream loading in Verilog */ + print_verilog_comment(fp, "----- Virtual memory to store the bitstream from external file -----"); + fp << "reg [0:`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " - 1] "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0:0];"; + fp << std::endl; + /* Initial value should be the first configuration bits * In the rest of programming cycles, * configuration bits are fed at the falling edge of programming clock. @@ -1286,6 +1196,9 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, fp << generate_verilog_port_constant_values(wl_port, initial_wl_values); fp << ";" << std::endl; + print_verilog_comment(fp, "----- Preload bitstream file to a virtual memory -----"); + fp << "\t"; + fp << "$readmemb(\"" << bitstream_file << "\", " << TOP_TB_BITSTREAM_MEM_REG_NAME << ");"; fp << std::endl; fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ") begin" << std::endl; @@ -1296,19 +1209,11 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, fp << generate_verilog_port_constant_values(wl_port, enabled_wl_values); fp << ";" << std::endl; - size_t ibit = 0; - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - BasicPort cur_bl_port(bl_port); - cur_bl_port.set_width(ibit, ibit); - - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, cur_bl_port); - fp << " = "; - fp << "1'b" << (size_t)bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)); - fp << ";" << std::endl; - - ibit++; - } + fp << "\t\t\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_port); + fp << " <= "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0]"; + fp << ";" << std::endl; fp << "\t\tend" << std::endl; @@ -1334,102 +1239,6 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } -/******************************************************************** - * Decide if we should use reset or set signal to acheive fast configuration - * - If only one type signal is specified, we use that type - * For example, only reset signal is defined, we will use reset - * - If both are defined, pick the one that will bring bigger reduction - * i.e., larger number of configuration bits can be skipped - *******************************************************************/ -static -bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, - const bool& fast_configuration, - const std::vector& global_prog_reset_ports, - const std::vector& global_prog_set_ports, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream) { - - /* Early exit conditions */ - if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) { - return false; - } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { - return true; - } else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { - /* If both types of ports are not defined, the fast configuration should be turned off */ - VTR_ASSERT(false == fast_configuration); - return false; - } - - VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); - bool bit_value_to_skip = false; - - VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); - - size_t num_ones_to_skip = 0; - size_t num_zeros_to_skip = 0; - - /* Branch on the type of configuration protocol */ - switch (config_protocol_type) { - case CONFIG_MEM_STANDALONE: - break; - case CONFIG_MEM_SCAN_CHAIN: { - /* We can only skip the ones/zeros at the beginning of the bitstream */ - /* Count how many logic '1' bits we can skip */ - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - break; - } - VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); - num_ones_to_skip++; - } - /* Count how many logic '0' bits we can skip */ - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - break; - } - VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); - num_zeros_to_skip++; - } - break; - } - case CONFIG_MEM_MEMORY_BANK: - case CONFIG_MEM_FRAME_BASED: { - /* Count how many logic '1' and logic '0' bits we can skip */ - for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { - num_zeros_to_skip++; - } else { - VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); - num_ones_to_skip++; - } - } - break; - } - default: - VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid SRAM organization type!\n"); - exit(1); - } - - VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", - 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), - num_zeros_to_skip, fabric_bitstream.num_bits()); - - VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", - 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), - num_ones_to_skip, fabric_bitstream.num_bits()); - - /* By default, we prefer to skip zeros (when the numbers are the same */ - if (num_ones_to_skip > num_zeros_to_skip) { - VTR_LOG("Will use set signal in fast configuration\n"); - bit_value_to_skip = true; - } else { - VTR_LOG("Will use reset signal in fast configuration\n"); - } - - return bit_value_to_skip; -} - /******************************************************************** * Print stimulus for a FPGA fabric with a configuration chain protocol * where configuration bits are programming in serial (one by one) @@ -1443,35 +1252,18 @@ bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& * we should create voltage waveforms only after programming phase *******************************************************************/ static -void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, - const bool& fast_configuration, - const bool& bit_value_to_skip, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream) { +void print_verilog_full_testbench_configuration_chain_bitstream(std::fstream& fp, + const std::string& bitstream_file, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ valid_file_stream(fp); - /* Initial value should be the first configuration bits - * In the rest of programming cycles, - * configuration bits are fed at the falling edge of programming clock. - * We do not care the value of scan_chain head during the first programming cycle - * It is reset anyway - */ - ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); - BasicPort config_chain_head_port = module_manager.module_port(top_module, cc_head_port_id); - std::vector initial_values(config_chain_head_port.get_width(), 0); - print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - print_verilog_comment(fp, "----- Configuration chain default input -----"); - fp << "\t\t"; - fp << generate_verilog_port_constant_values(config_chain_head_port, initial_values); - fp << ";"; - - fp << std::endl; /* Find the longest bitstream */ size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); @@ -1483,85 +1275,181 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, } VTR_ASSERT(num_bits_to_skip < regional_bitstream_max_size); - /* Reorganize the regional bitstreams to be the same size */ - std::vector> regional_bitstreams; - regional_bitstreams.reserve(fabric_bitstream.regions().size()); - for (const FabricBitRegionId& region : fabric_bitstream.regions()) { - std::vector curr_regional_bitstream; - curr_regional_bitstream.resize(regional_bitstream_max_size, false); - /* Starting index should consider the offset between the current bitstream size and - * the maximum size of regional bitstream - */ - size_t offset = regional_bitstream_max_size - fabric_bitstream.region_bits(region).size(); - for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { - curr_regional_bitstream[offset] = bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)); - offset++; - } - VTR_ASSERT(offset == regional_bitstream_max_size); - - /* Add the adapt sub-bitstream */ - regional_bitstreams.push_back(curr_regional_bitstream); - } + /* Define a constant for the bitstream length */ + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_LENGTH_VARIABLE), regional_bitstream_max_size - num_bits_to_skip); + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_WIDTH_VARIABLE), fabric_bitstream.num_regions()); - /* Attention: when the fast configuration is enabled, we will start from the first bit '1' - * This requires a reset signal (as we forced in the first clock cycle) - * - * Note that bitstream may come from different regions - * The bitstream value to be loaded should be organized as follows - * - * cycleA - * | - * Region 0: 0|00000001111101010 - * Region 1: | 00000011010101 - * Region 2: | 0010101111000110 - * - * Zero bits will be added to the head of those bitstreams are shorter - * than the longest bitstream + /* Initial value should be the first configuration bits + * In the rest of programming cycles, + * configuration bits are fed at the falling edge of programming clock. + * We do not care the value of scan_chain head during the first programming cycle + * It is reset anyway */ - for (size_t ibit = num_bits_to_skip; ibit < regional_bitstream_max_size; ++ibit) { - std::vector curr_cc_head_val; - curr_cc_head_val.reserve(fabric_bitstream.regions().size()); - for (const auto& region_bitstream : regional_bitstreams) { - curr_cc_head_val.push_back((size_t)region_bitstream[ibit]); - } + ModulePortId cc_head_port_id = module_manager.find_module_port(top_module, generate_configuration_chain_head_name()); + BasicPort config_chain_head_port = module_manager.module_port(top_module, cc_head_port_id); + std::vector initial_values(config_chain_head_port.get_width(), 0); - fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); - fp << "(" << generate_verilog_constant_values(curr_cc_head_val) << ");" << std::endl; - } + /* Declare local variables for bitstream loading in Verilog */ + print_verilog_comment(fp, "----- Virtual memory to store the bitstream from external file -----"); + fp << "reg [0:`" << TOP_TB_BITSTREAM_WIDTH_VARIABLE << " - 1] "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0:`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " - 1];"; + fp << std::endl; - /* Raise the flag of configuration done when bitstream loading is complete */ - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; + fp << "reg [$clog2(`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << "):0] " << TOP_TB_BITSTREAM_INDEX_REG_NAME << ";" << std::endl; + + BasicPort bit_skip_reg(TOP_TB_BITSTREAM_SKIP_FLAG_REG_NAME, 1); + print_verilog_comment(fp, "----- Registers used for fast configuration logic -----"); + fp << "reg [$clog2(`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << "):0] " << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << ";" << std::endl; + fp << generate_verilog_port(VERILOG_PORT_REG, bit_skip_reg) << ";" << std::endl; + + print_verilog_comment(fp, "----- Preload bitstream file to a virtual memory -----"); + fp << "initial begin" << std::endl; + fp << "\t"; + fp << "$readmemb(\"" << bitstream_file << "\", " << TOP_TB_BITSTREAM_MEM_REG_NAME << ");"; + fp << std::endl; + + print_verilog_comment(fp, "----- Configuration chain default input -----"); + fp << "\t"; + fp << generate_verilog_port_constant_values(config_chain_head_port, initial_values, true); + fp << ";"; + fp << std::endl; + + fp << "\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0"; + fp << ";"; + fp << std::endl; + + std::vector bit_skip_values(bit_skip_reg.get_width(), fast_configuration ? 1 : 0); + fp << "\t"; + fp << generate_verilog_port_constant_values(bit_skip_reg, bit_skip_values, true); + fp << ";"; + fp << std::endl; + + fp << "\t"; + fp << "for (" << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << " = 0; "; + fp << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << " < `" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " + 1; "; + fp << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << " = " << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << " + 1)"; + fp << " begin"; + fp << std::endl; + + fp << "\t\t"; + fp << "if ("; + fp << generate_verilog_constant_values(std::vector(fabric_bitstream.num_regions(), bit_value_to_skip)); + fp << " == "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[" << TOP_TB_BITSTREAM_ITERATOR_REG_NAME << "]"; + fp << ")"; + fp << " begin"; + fp << std::endl; - BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); + fp << "if ("; + fp << generate_verilog_constant_values(std::vector(bit_skip_reg.get_width(), 1)); + fp << " == "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, bit_skip_reg) << ")"; + fp << " begin"; + fp << std::endl; + + fp << "\t\t\t\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; fp << " <= "; - std::vector config_done_enable_values(config_done_port.get_width(), 1); - fp << generate_verilog_constant_values(config_done_enable_values); + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " + 1"; fp << ";" << std::endl; - fp << "\tend" << std::endl; + fp << "\t\t\t"; + fp << "end"; + fp << std::endl; + + fp << "\t\t"; + fp << "end else begin"; + fp << std::endl; + + fp << "\t\t\t"; + fp << generate_verilog_port_constant_values(bit_skip_reg, std::vector(bit_skip_reg.get_width(), 0), true); + fp << ";" << std::endl; + + fp << "\t\t"; + fp << "end"; + fp << std::endl; + + fp << "\t"; + fp << "end"; + fp << std::endl; + + fp << "end"; + fp << std::endl; + + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX), 1); + fp << "always"; + fp << " @(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ")"; + fp << " begin"; + fp << std::endl; + + fp << "\t"; + fp << "if ("; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " >= "; + fp << "`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE; + fp << ") begin"; + fp << std::endl; + + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); + fp << "\t\t"; + std::vector config_done_final_values(config_done_port.get_width(), 1); + fp << generate_verilog_port_constant_values(config_done_port, config_done_final_values, true); + fp << ";" << std::endl; + + fp << "\t"; + fp << "end else begin"; + fp << std::endl; + + fp << "\t\t"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, config_chain_head_port); + fp << " <= "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[" << TOP_TB_BITSTREAM_INDEX_REG_NAME << "]"; + fp << ";" << std::endl; + + fp << "\t\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " <= "; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " + 1"; + fp << ";" << std::endl; + + fp << "\t"; + fp << "end"; + fp << std::endl; + + fp << "end"; + fp << std::endl; + print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } /******************************************************************** * Print stimulus for a FPGA fabric with a memory bank configuration protocol * where configuration bits are programming in serial (one by one) - * - * We will use the programming task function created before *******************************************************************/ static -void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, - const bool& fast_configuration, - const bool& bit_value_to_skip, - const ModuleManager& module_manager, - const ModuleId& top_module, - const FabricBitstream& fabric_bitstream) { +void print_verilog_full_testbench_memory_bank_bitstream(std::fstream& fp, + const std::string& bitstream_file, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ valid_file_stream(fp); - /* Feed addresss and data input pair one by one + /* Reorganize the fabric bitstream by the same address across regions */ + MemoryBankFabricBitstream fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream); + + /* For fast configuration, identify the final bitstream size to be used */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = fabric_bits_by_addr.size() - find_memory_bank_fast_configuration_fabric_bitstream_size(fabric_bitstream, bit_value_to_skip); + } + VTR_ASSERT(num_bits_to_skip < fabric_bits_by_addr.size()); + + /* Feed address and data input pair one by one * Note: the first cycle is reserved for programming reset * We should give dummy values */ @@ -1580,107 +1468,129 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); std::vector initial_din_values(din_port.get_width(), 0); - print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; - print_verilog_comment(fp, "----- Address port default input -----"); - fp << "\t\t"; + /* Define a constant for the bitstream length */ + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_LENGTH_VARIABLE), fabric_bits_by_addr.size() - num_bits_to_skip); + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_WIDTH_VARIABLE), bl_addr_port.get_width() + wl_addr_port.get_width() + din_port.get_width()); + + /* Declare local variables for bitstream loading in Verilog */ + print_verilog_comment(fp, "----- Virtual memory to store the bitstream from external file -----"); + fp << "reg [0:`" << TOP_TB_BITSTREAM_WIDTH_VARIABLE << " - 1] "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0:`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " - 1];"; + fp << std::endl; + + fp << "reg [$clog2(`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << "):0] " << TOP_TB_BITSTREAM_INDEX_REG_NAME << ";" << std::endl; + + print_verilog_comment(fp, "----- Preload bitstream file to a virtual memory -----"); + fp << "initial begin" << std::endl; + fp << "\t"; + fp << "$readmemb(\"" << bitstream_file << "\", " << TOP_TB_BITSTREAM_MEM_REG_NAME << ");"; + fp << std::endl; + + print_verilog_comment(fp, "----- Bit-Line Address port default input -----"); + fp << "\t"; fp << generate_verilog_port_constant_values(bl_addr_port, initial_bl_addr_values); fp << ";"; fp << std::endl; - fp << "\t\t"; + print_verilog_comment(fp, "----- Word-Line Address port default input -----"); + fp << "\t"; fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values); fp << ";"; fp << std::endl; print_verilog_comment(fp, "----- Data-input port default input -----"); - fp << "\t\t"; + fp << "\t"; fp << generate_verilog_port_constant_values(din_port, initial_din_values); fp << ";"; - fp << std::endl; - /* Reorganize the fabric bitstream by the same address across regions */ - std::map, std::vector> fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream); + fp << "\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0"; + fp << ";"; + fp << std::endl; - for (const auto& addr_din_pair : fabric_bits_by_addr) { - /* When fast configuration is enabled, - * the rule to skip any configuration bit should consider the whole data input values. - * Only all the bits in the din port match the value to be skipped, - * the programming cycle can be skipped! - */ - if (true == fast_configuration) { - bool skip_curr_bits = true; - for (const bool& bit : addr_din_pair.second) { - if (bit_value_to_skip != bit) { - skip_curr_bits = false; - break; - } - } + fp << "end"; + fp << std::endl; - if (true == skip_curr_bits) { - continue; - } - } + print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX), 1); + fp << "always"; + fp << " @(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ")"; + fp << " begin"; + fp << std::endl; - fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); - fp << "(" << bl_addr_port.get_width() << "'b"; - VTR_ASSERT(bl_addr_port.get_width() == addr_din_pair.first.first.length()); - fp << addr_din_pair.first.first; - - fp << ", "; - fp << wl_addr_port.get_width() << "'b"; - VTR_ASSERT(wl_addr_port.get_width() == addr_din_pair.first.second.length()); - fp << addr_din_pair.first.second; - - fp << ", "; - fp << din_port.get_width() << "'b"; - VTR_ASSERT(din_port.get_width() == addr_din_pair.second.size()); - for (const bool& din_value : addr_din_pair.second) { - if (true == din_value) { - fp << "1"; - } else { - VTR_ASSERT(false == din_value); - fp << "0"; - } - } - fp << ");" << std::endl; - } - - /* Raise the flag of configuration done when bitstream loading is complete */ - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; + fp << "\t"; + fp << "if ("; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " >= "; + fp << "`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE; + fp << ") begin"; + fp << std::endl; BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); - fp << " <= "; - std::vector config_done_enable_values(config_done_port.get_width(), 1); - fp << generate_verilog_constant_values(config_done_enable_values); + fp << "\t\t"; + std::vector config_done_final_values(config_done_port.get_width(), 1); + fp << generate_verilog_port_constant_values(config_done_port, config_done_final_values, true); fp << ";" << std::endl; - fp << "\tend" << std::endl; + fp << "\t"; + fp << "end else begin"; + fp << std::endl; + + fp << "\t\t"; + fp << "{"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, bl_addr_port); + fp << ", "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, wl_addr_port); + fp << ", "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port); + fp << "}"; + fp << " <= "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[" << TOP_TB_BITSTREAM_INDEX_REG_NAME << "]"; + fp << ";" << std::endl; + + fp << "\t\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " <= "; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " + 1"; + fp << ";" << std::endl; + + fp << "\t"; + fp << "end"; + fp << std::endl; + + fp << "end"; + fp << std::endl; + print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } /******************************************************************** * Print stimulus for a FPGA fabric with a frame-based configuration protocol * where configuration bits are programming in serial (one by one) - * - * We will use the programming task function created before *******************************************************************/ static -void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, - const bool& fast_configuration, - const bool& bit_value_to_skip, - const ModuleManager& module_manager, - const ModuleId& top_module, - const FabricBitstream& fabric_bitstream) { +void print_verilog_full_testbench_frame_decoder_bitstream(std::fstream& fp, + const std::string& bitstream_file, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const ModuleManager& module_manager, + const ModuleId& top_module, + const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ valid_file_stream(fp); - /* Feed addresss and data input pair one by one + /* Reorganize the fabric bitstream by the same address across regions */ + FrameFabricBitstream fabric_bits_by_addr = build_frame_based_fabric_bitstream_by_address(fabric_bitstream); + + /* For fast configuration, identify the final bitstream size to be used */ + size_t num_bits_to_skip = 0; + if (true == fast_configuration) { + num_bits_to_skip = fabric_bits_by_addr.size() - find_frame_based_fast_configuration_fabric_bitstream_size(fabric_bitstream, bit_value_to_skip); + } + VTR_ASSERT(num_bits_to_skip < fabric_bits_by_addr.size()); + + /* Feed address and data input pair one by one * Note: the first cycle is reserved for programming reset * We should give dummy values */ @@ -1694,139 +1604,203 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); std::vector initial_din_values(din_port.get_width(), 0); - print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); - fp << "initial" << std::endl; - fp << "\tbegin" << std::endl; + /* Define a constant for the bitstream length */ + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_LENGTH_VARIABLE), fabric_bits_by_addr.size() - num_bits_to_skip); + print_verilog_define_flag(fp, std::string(TOP_TB_BITSTREAM_WIDTH_VARIABLE), addr_port.get_width() + din_port.get_width()); + + /* Declare local variables for bitstream loading in Verilog */ + print_verilog_comment(fp, "----- Virtual memory to store the bitstream from external file -----"); + fp << "reg [0:`" << TOP_TB_BITSTREAM_WIDTH_VARIABLE << " - 1] "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[0:`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << " - 1];"; + fp << std::endl; + + fp << "reg [$clog2(`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE << "):0] " << TOP_TB_BITSTREAM_INDEX_REG_NAME << ";" << std::endl; + + print_verilog_comment(fp, "----- Preload bitstream file to a virtual memory -----"); + fp << "initial begin" << std::endl; + fp << "\t"; + fp << "$readmemb(\"" << bitstream_file << "\", " << TOP_TB_BITSTREAM_MEM_REG_NAME << ");"; + fp << std::endl; + print_verilog_comment(fp, "----- Address port default input -----"); - fp << "\t\t"; + fp << "\t"; fp << generate_verilog_port_constant_values(addr_port, initial_addr_values); fp << ";"; fp << std::endl; print_verilog_comment(fp, "----- Data-input port default input -----"); - fp << "\t\t"; + fp << "\t"; fp << generate_verilog_port_constant_values(din_port, initial_din_values); fp << ";"; - fp << std::endl; - /* Reorganize the fabric bitstream by the same address across regions */ - std::map> fabric_bits_by_addr = build_frame_based_fabric_bitstream_by_address(fabric_bitstream); + fp << "\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0"; + fp << ";"; + fp << std::endl; - for (const auto& addr_din_pair : fabric_bits_by_addr) { - /* When fast configuration is enabled, - * the rule to skip any configuration bit should consider the whole data input values. - * Only all the bits in the din port match the value to be skipped, - * the programming cycle can be skipped! - */ - if (true == fast_configuration) { - bool skip_curr_bits = true; - for (const bool& bit : addr_din_pair.second) { - if (bit_value_to_skip != bit) { - skip_curr_bits = false; - break; - } - } + fp << "end"; + fp << std::endl; - if (true == skip_curr_bits) { - continue; - } - } + print_verilog_comment(fp, "----- Begin bitstream loading during configuration phase -----"); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + std::string(TOP_TB_CLOCK_REG_POSTFIX), 1); + fp << "always"; + fp << " @(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ")"; + fp << " begin"; + fp << std::endl; - fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); - fp << "(" << addr_port.get_width() << "'b"; - VTR_ASSERT(addr_port.get_width() == addr_din_pair.first.size()); - fp << addr_din_pair.first; - fp << ", "; - fp << din_port.get_width() << "'b"; - VTR_ASSERT(din_port.get_width() == addr_din_pair.second.size()); - for (const bool& din_value : addr_din_pair.second) { - if (true == din_value) { - fp << "1"; - } else { - VTR_ASSERT(false == din_value); - fp << "0"; - } - } - fp << ");" << std::endl; - } - - /* Disable the address and din - fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME); - fp << "(" << addr_port.get_width() << "'b"; - std::vector all_zero_addr(addr_port.get_width(), 0); - for (const size_t& addr_bit : all_zero_addr) { - fp << addr_bit; - } - fp << ", "; - fp << generate_verilog_constant_values(initial_din_values); - fp << ");" << std::endl; - */ - - /* Raise the flag of configuration done when bitstream loading is complete */ - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - fp << "\t\t@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, prog_clock_port) << ");" << std::endl; + fp << "\t"; + fp << "if ("; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " >= "; + fp << "`" << TOP_TB_BITSTREAM_LENGTH_VARIABLE; + fp << ") begin"; + fp << std::endl; BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); - fp << "\t\t\t"; - fp << generate_verilog_port(VERILOG_PORT_CONKT, config_done_port); - fp << " <= "; - std::vector config_done_enable_values(config_done_port.get_width(), 1); - fp << generate_verilog_constant_values(config_done_enable_values); + fp << "\t\t"; + std::vector config_done_final_values(config_done_port.get_width(), 1); + fp << generate_verilog_port_constant_values(config_done_port, config_done_final_values, true); fp << ";" << std::endl; - fp << "\tend" << std::endl; + fp << "\t"; + fp << "end else begin"; + fp << std::endl; + + fp << "\t\t"; + fp << "{"; + fp << generate_verilog_port(VERILOG_PORT_CONKT, addr_port); + fp << ", "; + fp << generate_verilog_port(VERILOG_PORT_CONKT, din_port); + fp << "}"; + fp << " <= "; + fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "[" << TOP_TB_BITSTREAM_INDEX_REG_NAME << "]"; + fp << ";" << std::endl; + + fp << "\t\t"; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME; + fp << " <= "; + fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " + 1"; + fp << ";" << std::endl; + + fp << "\t"; + fp << "end"; + fp << std::endl; + + fp << "end"; + fp << std::endl; + print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } /******************************************************************** - * Generate the stimuli for the top-level testbench + * Generate the stimuli for the full testbench * The simulation consists of two phases: configuration phase and operation phase * Configuration bits are loaded serially. * This is actually what we do for a physical FPGA *******************************************************************/ static -void print_verilog_top_testbench_bitstream(std::fstream& fp, - const e_config_protocol_type& config_protocol_type, - const bool& fast_configuration, - const bool& bit_value_to_skip, - const ModuleManager& module_manager, - const ModuleId& top_module, - const BitstreamManager& bitstream_manager, - const FabricBitstream& fabric_bitstream) { +void print_verilog_full_testbench_bitstream(std::fstream& fp, + const std::string& bitstream_file, + const e_config_protocol_type& config_protocol_type, + const bool& fast_configuration, + const bool& bit_value_to_skip, + const ModuleManager& module_manager, + const ModuleId& top_module, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { /* Branch on the type of configuration protocol */ switch (config_protocol_type) { case CONFIG_MEM_STANDALONE: - print_verilog_top_testbench_vanilla_bitstream(fp, - module_manager, top_module, - bitstream_manager, fabric_bitstream); + print_verilog_full_testbench_vanilla_bitstream(fp, + bitstream_file, + module_manager, + top_module, + fabric_bitstream); + break; case CONFIG_MEM_SCAN_CHAIN: - print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, - bit_value_to_skip, - module_manager, top_module, - bitstream_manager, fabric_bitstream); + print_verilog_full_testbench_configuration_chain_bitstream(fp, bitstream_file, + fast_configuration, + bit_value_to_skip, + module_manager, top_module, + bitstream_manager, + fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: - print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, - bit_value_to_skip, - module_manager, top_module, - fabric_bitstream); + print_verilog_full_testbench_memory_bank_bitstream(fp, bitstream_file, + fast_configuration, + bit_value_to_skip, + module_manager, top_module, + fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, - bit_value_to_skip, - module_manager, top_module, - fabric_bitstream); + print_verilog_full_testbench_frame_decoder_bitstream(fp, bitstream_file, + fast_configuration, + bit_value_to_skip, + module_manager, top_module, + fabric_bitstream); + break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, - "Invalid SRAM organization type!\n"); + "Invalid configuration protocol type!\n"); exit(1); } } + +/******************************************************************** + * Connect proper stimuli to the reset port + * This function is designed to drive the reset port of a benchmark module + *******************************************************************/ +static +void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, + const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names) { + valid_file_stream(fp); + + print_verilog_comment(fp, "----- Begin reset signal generation -----"); + + for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { + /* Bypass non-input atom blocks ! */ + if (AtomBlockType::INPAD != atom_ctx.nlist.block_type(atom_blk)) { + continue; + } + + /* The block may be renamed as it contains special characters which violate Verilog syntax */ + std::string block_name = atom_ctx.nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + + /* Bypass clock ports because their stimulus cannot be random */ + if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) { + continue; + } + + /* Bypass any constained net that are mapped to a global port of the FPGA fabric + * because their stimulus cannot be random + */ + if (false == port_is_fabric_global_reset_port(global_ports, module_manager, pin_constraints.net_pin(block_name))) { + continue; + } + + size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); + + /* Connect stimuli to greset with an optional inversion, depending on the default value */ + BasicPort reset_port(block_name, 1); + print_verilog_wire_connection(fp, reset_port, + BasicPort(TOP_TB_RESET_PORT_NAME, 1), + 1 == initial_value); + } +} + /******************************************************************** * Add auto-check codes for the full testbench * in particular for the configuration phase: @@ -1835,16 +1809,12 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_check(std::fstream& fp, - const std::string& autochecked_preprocessing_flag, const std::string& config_done_port_name, const std::string& error_counter_name) { /* Validate the file stream */ valid_file_stream(fp); - /* Add output autocheck conditionally: only when a preprocessing flag is enable */ - print_verilog_preprocessing_flag(fp, autochecked_preprocessing_flag); - print_verilog_comment(fp, std::string("----- Configuration done must be raised in the end -------")); BasicPort config_done_port(config_done_port_name, 1); @@ -1858,15 +1828,12 @@ void print_verilog_top_testbench_check(std::fstream& fp, write_tab_to_file(fp, 1); fp << "end" << std::endl; - /* Condition ends */ - print_verilog_endif(fp); - /* Add an empty line as splitter */ fp << std::endl; } /******************************************************************** - * The top-level function to generate a testbench, in order to verify: + * The top-level function to generate a full testbench, in order to verify: * 1. Configuration phase of the FPGA fabric, where the bitstream is * loaded to the configuration protocol of the FPGA fabric * 2. Operating phase of the FPGA fabric, where input stimuli are @@ -1885,7 +1852,7 @@ void print_verilog_top_testbench_check(std::fstream& fp, * +-----------+ +------------+ * *******************************************************************/ -void print_verilog_top_testbench(const ModuleManager& module_manager, +int print_verilog_full_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const CircuitLibrary& circuit_lib, @@ -1894,6 +1861,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const AtomContext& atom_ctx, const PlacementContext& place_ctx, const PinConstraints& pin_constraints, + const std::string& bitstream_file, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, @@ -1917,7 +1885,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, check_file_stream(verilog_fname.c_str(), fp); /* Generate a brief description on the Verilog file*/ - std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; + std::string title = std::string("FPGA Verilog full testbench for top-level netlist of design: ") + circuit_name; print_verilog_file_header(fp, title); /* Find the top_module */ @@ -1932,17 +1900,14 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, std::vector global_prog_set_ports = find_fabric_global_programming_set_ports(global_ports); /* Identify if we can apply fast configuration */ - bool apply_fast_configuration = fast_configuration; - if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) - && (true == fast_configuration)) { - VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); - apply_fast_configuration = false; + bool apply_fast_configuration = fast_configuration && is_fast_configuration_applicable(global_ports); + bool bit_value_to_skip = false; + if (true == apply_fast_configuration) { + bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), + global_ports, + bitstream_manager, + fabric_bitstream); } - bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), - apply_fast_configuration, - global_prog_reset_ports, - global_prog_set_ports, - bitstream_manager, fabric_bitstream); /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, @@ -1950,7 +1915,8 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, clock_port_names, pin_constraints, simulation_parameters, config_protocol, - circuit_name); + circuit_name, + options); /* Find the clock period */ float prog_clock_period = (1./simulation_parameters.programming_clock_frequency()); @@ -2011,6 +1977,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Generate stimuli for global ports or connect them to existed signals */ print_verilog_top_testbench_global_ports_stimuli(fp, module_manager, top_module, + pin_constraints, global_ports, simulation_parameters, active_global_prog_reset, @@ -2030,23 +1997,23 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE); /* Instanciate input benchmark */ - print_verilog_top_testbench_benchmark_instance(fp, - circuit_name, - atom_ctx, - netlist_annotation, - explicit_port_mapping); - - /* Print tasks used for loading bitstreams */ - print_verilog_top_testbench_load_bitstream_task(fp, - config_protocol.type(), - module_manager, top_module); + if (!options.no_self_checking()) { + print_verilog_top_testbench_benchmark_instance(fp, + circuit_name, + atom_ctx, + netlist_annotation, + pin_constraints, + explicit_port_mapping); + } /* load bitstream to FPGA fabric in a configuration phase */ - print_verilog_top_testbench_bitstream(fp, config_protocol.type(), - apply_fast_configuration, - bit_value_to_skip, - module_manager, top_module, - bitstream_manager, fabric_bitstream); + print_verilog_full_testbench_bitstream(fp, + bitstream_file, + config_protocol.type(), + apply_fast_configuration, + bit_value_to_skip, + module_manager, top_module, + bitstream_manager, fabric_bitstream); /* Add signal initialization: * Bypass writing codes to files due to the autogenerated codes are very large. @@ -2056,34 +2023,47 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME), circuit_lib, module_manager, - top_module); + top_module, + true); } + /* Add stimuli for reset, set, clock and iopad signals */ + print_verilog_top_testbench_reset_stimuli(fp, + atom_ctx, + netlist_annotation, + module_manager, + global_ports, + pin_constraints, + clock_port_names); print_verilog_testbench_random_stimuli(fp, atom_ctx, netlist_annotation, + module_manager, + global_ports, + pin_constraints, clock_port_names, std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1))); + std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)), + options.no_self_checking()); - /* Add output autocheck */ - print_verilog_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), - std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), - std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), - std::string(TOP_TESTBENCH_ERROR_COUNTER), - atom_ctx, - netlist_annotation, - clock_port_names, - std::string(TOP_TB_OP_CLOCK_PORT_NAME)); + if (!options.no_self_checking()) { + /* Add output autocheck */ + print_verilog_testbench_check(fp, + std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), + std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), + std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), + std::string(TOP_TESTBENCH_ERROR_COUNTER), + atom_ctx, + netlist_annotation, + clock_port_names, + std::string(TOP_TB_OP_CLOCK_PORT_NAME)); - /* Add autocheck for configuration phase */ - print_verilog_top_testbench_check(fp, - std::string(AUTOCHECKED_SIMULATION_FLAG), - std::string(TOP_TB_CONFIG_DONE_PORT_NAME), - std::string(TOP_TESTBENCH_ERROR_COUNTER)); + /* Add autocheck for configuration phase */ + print_verilog_top_testbench_check(fp, + std::string(TOP_TB_CONFIG_DONE_PORT_NAME), + std::string(TOP_TESTBENCH_ERROR_COUNTER)); + } /* Find simulation time */ float simulation_time = find_simulation_time_period(VERILOG_SIM_TIMESCALE, @@ -2097,12 +2077,12 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, * Always ceil the simulation time so that we test a sufficient length of period!!! */ print_verilog_timeout_and_vcd(fp, - std::string(ICARUS_SIMULATOR_FLAG), std::string(circuit_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)), std::string(circuit_name + std::string("_formal.vcd")), std::string(TOP_TESTBENCH_SIM_START_PORT_NAME), std::string(TOP_TESTBENCH_ERROR_COUNTER), - std::ceil(simulation_time)); + std::ceil(simulation_time), + options.no_self_checking()); /* Testbench ends*/ @@ -2110,6 +2090,9 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Close the file stream */ fp.close(); + + return 0; } + } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index ca36d61e9..aff108d72 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -26,7 +26,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_top_testbench(const ModuleManager& module_manager, +int print_verilog_full_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, const CircuitLibrary& circuit_lib, @@ -35,6 +35,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const AtomContext& atom_ctx, const PlacementContext& place_ctx, const PinConstraints& pin_constraints, + const std::string& bitstream_file, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index c4544a123..9a55968b0 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -488,7 +488,7 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p && (0 == port_info.get_lsb()) && (1 == port_info.get_origin_port_width())) { size_str.clear(); - } else if ((1 == port_info.get_width()) && (0 != port_info.get_lsb())) { + } else if ((1 == port_info.get_width())) { size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; } verilog_line = port_info.get_name() + size_str; @@ -724,14 +724,20 @@ std::string generate_verilog_constant_values(const std::vector& const_va * Generate a verilog port with a deposite of constant values ********************************************************************/ std::string generate_verilog_port_constant_values(const BasicPort& output_port, - const std::vector& const_values) { + const std::vector& const_values, + const bool& is_register) { std::string port_str; /* Must check: the port width matches */ VTR_ASSERT( const_values.size() == output_port.get_width() ); port_str = generate_verilog_port(VERILOG_PORT_CONKT, output_port); - port_str += " = "; + if (is_register) { + port_str += " <= "; + } else { + VTR_ASSERT_SAFE(!is_register); + port_str += " = "; + } port_str += generate_verilog_constant_values(const_values); return port_str; } diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 61f13385e..09a5dba7a 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -108,7 +108,8 @@ std::string generate_verilog_constant_values(const std::vector& const_va const bool& short_constant = true); std::string generate_verilog_port_constant_values(const BasicPort& output_port, - const std::vector& const_values); + const std::vector& const_values, + const bool& is_register = false); void print_verilog_wire_constant_values(std::fstream& fp, const BasicPort& output_port, diff --git a/openfpga/src/repack/physical_pb.cpp b/openfpga/src/repack/physical_pb.cpp index c64f05f07..a614d128a 100644 --- a/openfpga/src/repack/physical_pb.cpp +++ b/openfpga/src/repack/physical_pb.cpp @@ -107,6 +107,21 @@ std::string PhysicalPb::fixed_bitstream(const PhysicalPbId& pb) const { return fixed_bitstreams_[pb]; } +size_t PhysicalPb::fixed_bitstream_offset(const PhysicalPbId& pb) const { + VTR_ASSERT(true == valid_pb_id(pb)); + return fixed_bitstream_offsets_[pb]; +} + +std::string PhysicalPb::fixed_mode_select_bitstream(const PhysicalPbId& pb) const { + VTR_ASSERT(true == valid_pb_id(pb)); + return fixed_mode_select_bitstreams_[pb]; +} + +size_t PhysicalPb::fixed_mode_select_bitstream_offset(const PhysicalPbId& pb) const { + VTR_ASSERT(true == valid_pb_id(pb)); + return fixed_mode_select_bitstream_offsets_[pb]; +} + /****************************************************************************** * Private Mutators ******************************************************************************/ @@ -133,7 +148,11 @@ PhysicalPbId PhysicalPb::create_pb(const t_pb_graph_node* pb_graph_node) { truth_tables_.emplace_back(); mode_bits_.emplace_back(); + fixed_bitstreams_.emplace_back(); + fixed_bitstream_offsets_.push_back(0); + fixed_mode_select_bitstreams_.emplace_back(); + fixed_mode_select_bitstream_offsets_.push_back(0); /* Register in the name2id map */ type2id_map_[pb_graph_node] = pb; @@ -218,6 +237,24 @@ void PhysicalPb::set_fixed_bitstream(const PhysicalPbId& pb, fixed_bitstreams_[pb] = fixed_bitstream; } +void PhysicalPb::set_fixed_bitstream_offset(const PhysicalPbId& pb, + const size_t& offset) { + VTR_ASSERT(true == valid_pb_id(pb)); + fixed_bitstream_offsets_[pb] = offset; +} + +void PhysicalPb::set_fixed_mode_select_bitstream(const PhysicalPbId& pb, + const std::string& fixed_bitstream) { + VTR_ASSERT(true == valid_pb_id(pb)); + fixed_mode_select_bitstreams_[pb] = fixed_bitstream; +} + +void PhysicalPb::set_fixed_mode_select_bitstream_offset(const PhysicalPbId& pb, + const size_t& offset) { + VTR_ASSERT(true == valid_pb_id(pb)); + fixed_mode_select_bitstream_offsets_[pb] = offset; +} + /****************************************************************************** * Private validators/invalidators ******************************************************************************/ diff --git a/openfpga/src/repack/physical_pb.h b/openfpga/src/repack/physical_pb.h index 078cc6bc9..7ce42a3c8 100644 --- a/openfpga/src/repack/physical_pb.h +++ b/openfpga/src/repack/physical_pb.h @@ -55,6 +55,9 @@ class PhysicalPb { std::map truth_tables(const PhysicalPbId& pb) const; std::vector mode_bits(const PhysicalPbId& pb) const; std::string fixed_bitstream(const PhysicalPbId& pb) const; + size_t fixed_bitstream_offset(const PhysicalPbId& pb) const; + std::string fixed_mode_select_bitstream(const PhysicalPbId& pb) const; + size_t fixed_mode_select_bitstream_offset(const PhysicalPbId& pb) const; public: /* Public mutators */ PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node); void add_child(const PhysicalPbId& parent, @@ -75,6 +78,12 @@ class PhysicalPb { const bool& wire_lut_output); void set_fixed_bitstream(const PhysicalPbId& pb, const std::string& fixed_bitstream); + void set_fixed_bitstream_offset(const PhysicalPbId& pb, + const size_t& offset); + void set_fixed_mode_select_bitstream(const PhysicalPbId& pb, + const std::string& fixed_bitstream); + void set_fixed_mode_select_bitstream_offset(const PhysicalPbId& pb, + const size_t& offset); public: /* Public validators/invalidators */ bool valid_pb_id(const PhysicalPbId& pb_id) const; bool empty() const; @@ -98,6 +107,10 @@ class PhysicalPb { vtr::vector> mode_bits_; vtr::vector fixed_bitstreams_; + vtr::vector fixed_bitstream_offsets_; + + vtr::vector fixed_mode_select_bitstreams_; + vtr::vector fixed_mode_select_bitstream_offsets_; /* Fast lookup */ std::map type2id_map_; diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 3611909bb..7538c675a 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -28,6 +28,8 @@ namespace openfpga { * - sink is an input of a primitive pb_type * * Note: + * - This function is applicable ONLY to single-mode pb_types!!! Because their routing traces + * are deterministic: there is only 1 valid path from a source pin to a sink pin!!! * - If there is a fan-out of the current source pb graph pin is not a direct interconnection * the direct search should stop. * - This function is designed for pb graph without local routing @@ -58,6 +60,11 @@ bool rec_direct_search_sink_pb_graph_pins(const t_pb_graph_pin* source_pb_pin, std::vector sink_pb_pins_to_search; + /* Only support single-mode pb_type!!! */ + //if (1 != source_pb_pin->parent_node->pb_type->num_modes) { + // return false; + //} + for (int iedge = 0; iedge < source_pb_pin->num_output_edges; ++iedge) { if (DIRECT_INTERC != source_pb_pin->output_edges[iedge]->interconnect->type) { return false; @@ -230,6 +237,38 @@ std::vector find_routed_pb_graph_pins_atom_net(const t_pb* pb, return sink_pb_pins; } +/*************************************************************************************** + * This function will find the actual routing traces of the demanded net + * There is a specific search space applied when searching the routing traces: + * - ONLY applicable to the pb_pin of top-level pb_graph_node + * - candidate can be limited to a set of pb pins + ***************************************************************************************/ +static +std::vector find_pb_route_by_atom_net(const t_pb* pb, + const t_pb_graph_pin* source_pb_pin, + const AtomNetId& atom_net_id) { + VTR_ASSERT(true == source_pb_pin->parent_node->is_root()); + + std::vector pb_route_indices; + + for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { + /* Bypass unused pins */ + if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) { + continue; + } + /* Get the driver pb pin id, it must be valid */ + if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { + continue; + } + + if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { + pb_route_indices.push_back(pin); + } + } + + return pb_route_indices; +} + /*************************************************************************************** * This function will find the actual source_pb_pin that is mapped by packed in the pb route * As the inputs of clustered block may be renamed during routing, @@ -422,18 +461,7 @@ void add_lb_router_nets(LbRouter& lb_router, AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; /* Check if the net information is constrained or not */ - std::string constrained_net_name; - for (const RepackDesignConstraintId& design_constraint : design_constraints.design_constraints()) { - /* All the pin must have only 1 bit */ - VTR_ASSERT_SAFE(1 == design_constraints.pin(design_constraint).get_width()); - /* If found a constraint, record the net name */ - if ( (std::string(lb_type->pb_type->name) == design_constraints.pb_type(design_constraint)) - && (std::string(source_pb_pin->port->name) == design_constraints.pin(design_constraint).get_name()) - && (size_t(source_pb_pin->pin_number) == design_constraints.pin(design_constraint).get_lsb())) { - constrained_net_name = design_constraints.net(design_constraint); - break; - } - } + std::string constrained_net_name = design_constraints.find_constrained_pin_net(std::string(lb_type->pb_type->name), BasicPort(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number)); /* Find the constrained net mapped to this pin in clustering results */ AtomNetId constrained_atom_net_id = AtomNetId::INVALID(); @@ -443,16 +471,21 @@ void add_lb_router_nets(LbRouter& lb_router, * - if this is valid net name, find the net id from atom_netlist * and overwrite the atom net id to mapped */ - if (!constrained_net_name.empty()) { - if (std::string(REPACK_DESIGN_CONSTRAINT_OPEN_NET) != constrained_net_name) { - constrained_atom_net_id = atom_ctx.nlist.find_net(constrained_net_name); - if (false == atom_ctx.nlist.valid_net_id(constrained_atom_net_id)) { - VTR_LOG_WARN("Invalid net '%s' to be constrained! Will drop the constraint in repacking\n", - constrained_net_name.c_str()); - } + if ( (!design_constraints.unconstrained_net(constrained_net_name)) + && (!design_constraints.unmapped_net(constrained_net_name))) { + constrained_atom_net_id = atom_ctx.nlist.find_net(constrained_net_name); + if (false == atom_ctx.nlist.valid_net_id(constrained_atom_net_id)) { + VTR_LOG_WARN("Invalid net '%s' to be constrained! Will drop the constraint in repacking\n", + constrained_net_name.c_str()); + } else { + VTR_ASSERT_SAFE(false == atom_ctx.nlist.valid_net_id(constrained_atom_net_id)); + VTR_LOGV(verbose, + "Accept net '%s' to be constrained on pin '%s[%d]' during repacking\n", + constrained_net_name.c_str(), + source_pb_pin->port->name, + source_pb_pin->pin_number); } - } else { - VTR_ASSERT_SAFE(constrained_net_name.empty()); + } else if (design_constraints.unconstrained_net(constrained_net_name)) { constrained_atom_net_id = atom_net_id; } @@ -486,18 +519,35 @@ void add_lb_router_nets(LbRouter& lb_router, LbRRNodeId source_lb_rr_node = lb_rr_graph.find_node(LB_INTERMEDIATE, source_pb_pin); VTR_ASSERT(true == lb_rr_graph.valid_node_id(source_lb_rr_node)); + /* Output verbose messages for debugging only */ + VTR_LOGV(verbose, + "Pb route for Net %s:\n", + atom_ctx.nlist.net_name(atom_net_id_to_route).c_str()); + /* As the pin remapping is allowed during routing, we should * - Find the routing traces from packing results which is mapped to the net * from the same port (as remapping is allowed for pins in the same port only) * - Find the source pb_graph_pin that drives the routing traces during packing * - Then we can find the sink nodes + * + * When there is a pin constraint applied. The routing trace + * - Find the routing traces from packing results which is mapped to the net + * with the same port constraints */ - std::vector pb_route_indices = find_pb_route_remapped_source_pb_pin(pb, source_pb_pin, atom_net_id_to_route); + std::vector pb_route_indices; + if (design_constraints.unconstrained_net(constrained_net_name)) { + pb_route_indices = find_pb_route_remapped_source_pb_pin(pb, source_pb_pin, atom_net_id_to_route); + } else { + VTR_ASSERT_SAFE(!design_constraints.unconstrained_net(constrained_net_name)); + pb_route_indices = find_pb_route_by_atom_net(pb, source_pb_pin, atom_net_id_to_route); + } /* It could happen that the constrained net is NOT used in this clb, we just skip it for routing * For example, a clkB net is never mapped to any ports in the pb that is clocked by clkA net * */ int pb_route_index; if (0 == pb_route_indices.size()) { + VTR_LOGV(verbose, + "Bypass routing due to no routing traces found\n"); continue; } else { VTR_ASSERT(1 == pb_route_indices.size()); @@ -512,9 +562,6 @@ void add_lb_router_nets(LbRouter& lb_router, VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); /* Output verbose messages for debugging only */ - VTR_LOGV(verbose, - "Pb route for Net %s:\n", - atom_ctx.nlist.net_name(atom_net_id_to_route).c_str()); VTR_LOGV(verbose, "Source node:\n\t%s -> %s\n", source_pb_pin->to_string().c_str(), diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp index b1beeb00d..52f81dcdb 100644 --- a/openfpga/src/utils/fabric_bitstream_utils.cpp +++ b/openfpga/src/utils/fabric_bitstream_utils.cpp @@ -67,6 +67,43 @@ size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(const Fabric return num_bits_to_skip; } +/******************************************************************** + * Build a fabric bitstream which can be directly loaded to a configuration + * chain (either single-head or multi-bit) + * We will organize the bitstreams in each region and align them + * Logic '0' bits may be deposited to those bitstream whose length is smaller + * than the maximum bitstream among all the regions + * For example: + * Region 0: 000000001111101010 <- max. bitstream length + * Region 1: 00000011010101 <- shorter bitstream than the max.; add zeros to the head + * Region 2: 0010101111000110 <- shorter bitstream than the max.; add zeros to the head + *******************************************************************/ +ConfigChainFabricBitstream build_config_chain_fabric_bitstream_by_region(const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + /* Find the longest bitstream */ + size_t regional_bitstream_max_size = find_fabric_regional_bitstream_max_size(fabric_bitstream); + + ConfigChainFabricBitstream regional_bitstreams; + regional_bitstreams.reserve(fabric_bitstream.regions().size()); + for (const FabricBitRegionId& region : fabric_bitstream.regions()) { + std::vector curr_regional_bitstream; + curr_regional_bitstream.resize(regional_bitstream_max_size, false); + /* Starting index should consider the offset between the current bitstream size and + * the maximum size of regional bitstream + */ + size_t offset = regional_bitstream_max_size - fabric_bitstream.region_bits(region).size(); + for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { + curr_regional_bitstream[offset] = bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)); + offset++; + } + VTR_ASSERT(offset == regional_bitstream_max_size); + + /* Add the adapt sub-bitstream */ + regional_bitstreams.push_back(curr_regional_bitstream); + } + return regional_bitstreams; +} + /******************************************************************** * Reorganize the fabric bitstream for frame-based protocol * by the same address across regions: @@ -78,8 +115,8 @@ size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(const Fabric * * Note: the std::map may cause large memory footprint for large bitstream databases! *******************************************************************/ -std::map> build_frame_based_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream) { - std::map> fabric_bits_by_addr; +FrameFabricBitstream build_frame_based_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream) { + FrameFabricBitstream fabric_bits_by_addr; for (const FabricBitRegionId& region : fabric_bitstream.regions()) { for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { /* Create string for address */ @@ -129,7 +166,7 @@ std::map> build_frame_based_fabric_bitstream_by_a *******************************************************************/ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream, const bool& bit_value_to_skip) { - std::map> fabric_bits_by_addr = build_frame_based_fabric_bitstream_by_address(fabric_bitstream); + FrameFabricBitstream fabric_bits_by_addr = build_frame_based_fabric_bitstream_by_address(fabric_bitstream); size_t num_bits = 0; @@ -161,8 +198,8 @@ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBit * * Note: the std::map may cause large memory footprint for large bitstream databases! *******************************************************************/ -std::map, std::vector> build_memory_bank_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream) { - std::map, std::vector> fabric_bits_by_addr; +MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream) { + MemoryBankFabricBitstream fabric_bits_by_addr; for (const FabricBitRegionId& region : fabric_bitstream.regions()) { for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { /* Create string for BL address */ @@ -217,7 +254,7 @@ std::map, std::vector> build_memory_ba *******************************************************************/ size_t find_memory_bank_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream, const bool& bit_value_to_skip) { - std::map, std::vector> fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream); + MemoryBankFabricBitstream fabric_bits_by_addr = build_memory_bank_fabric_bitstream_by_address(fabric_bitstream); size_t num_bits = 0; diff --git a/openfpga/src/utils/fabric_bitstream_utils.h b/openfpga/src/utils/fabric_bitstream_utils.h index e34464a89..4da8c3c92 100644 --- a/openfpga/src/utils/fabric_bitstream_utils.h +++ b/openfpga/src/utils/fabric_bitstream_utils.h @@ -25,12 +25,21 @@ size_t find_configuration_chain_fabric_bitstream_size_to_be_skipped(const Fabric const BitstreamManager& bitstream_manager, const bool& bit_value_to_skip); -std::map> build_frame_based_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream); +/* Alias to a specific organization of bitstreams for frame-based configuration protocol */ +typedef std::vector> ConfigChainFabricBitstream; +ConfigChainFabricBitstream build_config_chain_fabric_bitstream_by_region(const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream); + +/* Alias to a specific organization of bitstreams for frame-based configuration protocol */ +typedef std::map> FrameFabricBitstream; +FrameFabricBitstream build_frame_based_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream); size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream, const bool& bit_value_to_skip); -std::map, std::vector> build_memory_bank_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream); +/* Alias to a specific organization of bitstreams for memory bank configuration protocol */ +typedef std::map, std::vector> MemoryBankFabricBitstream; +MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream); size_t find_memory_bank_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream, const bool& bit_value_to_skip); diff --git a/openfpga/src/utils/fabric_global_port_info_utils.cpp b/openfpga/src/utils/fabric_global_port_info_utils.cpp index 3200a8fbd..9fbd707c5 100644 --- a/openfpga/src/utils/fabric_global_port_info_utils.cpp +++ b/openfpga/src/utils/fabric_global_port_info_utils.cpp @@ -11,6 +11,8 @@ #include "vtr_assert.h" #include "vtr_log.h" +#include "openfpga_naming.h" + #include "fabric_global_port_info_utils.h" /* begin namespace openfpga */ @@ -58,4 +60,51 @@ std::vector find_fabric_global_programming_set_ports(const F return global_prog_set_ports; } +/******************************************************************** + * Identify if a port is in the list of fabric global port + * and its functionality is a reset port which is not used for programming FPGAs + *******************************************************************/ +bool port_is_fabric_global_reset_port(const FabricGlobalPortInfo& fabric_global_port_info, + const ModuleManager& module_manager, + const BasicPort& port) { + /* Find the top_module: the fabric global ports are always part of the ports of the top module */ + ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + for (const FabricGlobalPortId& fabric_global_port_id : fabric_global_port_info.global_ports()) { + if ( (false == fabric_global_port_info.global_port_is_reset(fabric_global_port_id)) + || (true == fabric_global_port_info.global_port_is_prog(fabric_global_port_id))) { + continue; + } + + BasicPort module_global_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(fabric_global_port_id)); + if ( (true == module_global_port.mergeable(port)) + && (true == module_global_port.contained(port)) ) { + return true; + } + } + + return false; +} + +/******************************************************************** + * Find a global port with a given name + *******************************************************************/ +FabricGlobalPortId find_fabric_global_port(const FabricGlobalPortInfo& fabric_global_port_info, + const ModuleManager& module_manager, + const BasicPort& port) { + /* Find the top_module: the fabric global ports are always part of the ports of the top module */ + ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); + VTR_ASSERT(true == module_manager.valid_module_id(top_module)); + + for (const FabricGlobalPortId& fabric_global_port_id : fabric_global_port_info.global_ports()) { + BasicPort module_global_port = module_manager.module_port(top_module, fabric_global_port_info.global_module_port(fabric_global_port_id)); + if ( (true == module_global_port.mergeable(port)) + && (true == module_global_port.contained(port)) ) { + return fabric_global_port_id; + } + } + return FabricGlobalPortId::INVALID(); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/fabric_global_port_info_utils.h b/openfpga/src/utils/fabric_global_port_info_utils.h index 457c0018e..99611bc8b 100644 --- a/openfpga/src/utils/fabric_global_port_info_utils.h +++ b/openfpga/src/utils/fabric_global_port_info_utils.h @@ -6,6 +6,7 @@ *******************************************************************/ #include #include "fabric_global_port_info.h" +#include "module_manager.h" /******************************************************************** * Function declaration @@ -18,6 +19,14 @@ std::vector find_fabric_global_programming_reset_ports(const std::vector find_fabric_global_programming_set_ports(const FabricGlobalPortInfo& fabric_global_port_info); +bool port_is_fabric_global_reset_port(const FabricGlobalPortInfo& fabric_global_port_info, + const ModuleManager& module_manager, + const BasicPort& port); + +FabricGlobalPortId find_fabric_global_port(const FabricGlobalPortInfo& fabric_global_port_info, + const ModuleManager& module_manager, + const BasicPort& port); + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index adecd847c..2b366c305 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -304,7 +304,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, VTR_ASSERT(atom_blk); phy_pb.add_atom_block(physical_pb, atom_blk); - + /* if the operating pb type has bitstream annotation, * bind the bitstream value from atom block to the physical pb */ @@ -313,17 +313,55 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb, std::vector tokens = tokenizer.split(" "); /* FIXME: The token-level check should be done much earlier!!! */ VTR_ASSERT(2 == tokens.size()); + /* The token is typically organized as <.param|.attr> */ if (std::string(".param") == tokens[0]) { for (const auto& param_search : atom_ctx.nlist.block_params(atom_blk)) { - if (param_search.first == tokens[1]) { - phy_pb.set_fixed_bitstream(physical_pb, param_search.second); - } + /* Bypass unmatched parameter identifier */ + if (param_search.first != tokens[1]) { + continue; + } + phy_pb.set_fixed_bitstream(physical_pb, param_search.second); + phy_pb.set_fixed_bitstream_offset(physical_pb, bitstream_annotation.pb_type_bitstream_offset(pb_type)); } } else if (std::string(".attr") == tokens[0]) { for (const auto& attr_search : atom_ctx.nlist.block_attrs(atom_blk)) { + /* Bypass unmatched parameter identifier */ if (attr_search.first == tokens[1]) { - phy_pb.set_fixed_bitstream(physical_pb, attr_search.second); - } + continue; + } + phy_pb.set_fixed_bitstream(physical_pb, attr_search.second); + phy_pb.set_fixed_bitstream_offset(physical_pb, bitstream_annotation.pb_type_bitstream_offset(pb_type)); + } + } + } + + + /* if the operating pb type has mode-select bitstream annotation, + * bind the bitstream value from atom block to the physical pb + */ + if (VprBitstreamAnnotation::e_bitstream_source_type::BITSTREAM_SOURCE_EBLIF == bitstream_annotation.pb_type_mode_select_bitstream_source(pb_type)) { + StringToken tokenizer = bitstream_annotation.pb_type_mode_select_bitstream_content(pb_type); + std::vector tokens = tokenizer.split(" "); + /* FIXME: The token-level check should be done much earlier!!! */ + VTR_ASSERT(2 == tokens.size()); + /* The token is typically organized as <.param|.attr> */ + if (std::string(".param") == tokens[0]) { + for (const auto& param_search : atom_ctx.nlist.block_params(atom_blk)) { + /* Bypass unmatched parameter identifier */ + if (param_search.first != tokens[1]) { + continue; + } + phy_pb.set_fixed_mode_select_bitstream(physical_pb, param_search.second); + phy_pb.set_fixed_mode_select_bitstream_offset(physical_pb, bitstream_annotation.pb_type_mode_select_bitstream_offset(pb_type)); + } + } else if (std::string(".attr") == tokens[0]) { + for (const auto& attr_search : atom_ctx.nlist.block_attrs(atom_blk)) { + /* Bypass unmatched parameter identifier */ + if (attr_search.first == tokens[1]) { + continue; + } + phy_pb.set_fixed_mode_select_bitstream(physical_pb, attr_search.second); + phy_pb.set_fixed_mode_select_bitstream_offset(physical_pb, bitstream_annotation.pb_type_mode_select_bitstream_offset(pb_type)); } } } diff --git a/openfpga/src/utils/simulation_utils.cpp b/openfpga/src/utils/simulation_utils.cpp index 87a04976d..df56bf91b 100644 --- a/openfpga/src/utils/simulation_utils.cpp +++ b/openfpga/src/utils/simulation_utils.cpp @@ -14,14 +14,13 @@ namespace openfpga { /******************************************************************** * Compute the time period for the simulation *******************************************************************/ -float find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, +float find_operating_phase_simulation_time(const int& num_op_clock_cycles, const float& op_clock_period, const float& timescale) { /* Take into account the prog_reset and reset cycles * 1e9 is to change the unit to ns rather than second */ - return ((float)factor * (float)num_op_clock_cycles * op_clock_period) / timescale; + return ((float)num_op_clock_cycles * op_clock_period) / timescale; } /******************************************************************** diff --git a/openfpga/src/utils/simulation_utils.h b/openfpga/src/utils/simulation_utils.h index c82999bc9..3d5e6bba2 100644 --- a/openfpga/src/utils/simulation_utils.h +++ b/openfpga/src/utils/simulation_utils.h @@ -12,8 +12,7 @@ /* begin namespace openfpga */ namespace openfpga { -float find_operating_phase_simulation_time(const int& factor, - const int& num_op_clock_cycles, +float find_operating_phase_simulation_time(const int& num_op_clock_cycles, const float& op_clock_period, const float& timescale); diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_cra.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_cra.v new file mode 100644 index 000000000..66a4226bd --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_cra.v @@ -0,0 +1,196 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Codec Register Access Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +// CVS Log +// +// $Id: ac97_cra.v,v 1.3 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_cra.v,v $ +// Revision 1.3 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_cra(clk, rst, + + crac_we, crac_din, crac_out, + crac_wr_done, crac_rd_done, + + valid, out_slt1, out_slt2, + in_slt2, + + crac_valid, crac_wr + ); + +input clk, rst; +input crac_we; +output [15:0] crac_din; +input [31:0] crac_out; +output crac_wr_done, crac_rd_done; + +input valid; +output [19:0] out_slt1; +output [19:0] out_slt2; +input [19:0] in_slt2; + +output crac_valid; +output crac_wr; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg crac_wr; +reg crac_rd; +reg crac_rd_done; +reg [15:0] crac_din; +reg crac_we_r; +reg valid_r; +wire valid_ne; +wire valid_pe; +reg rdd1, rdd2, rdd3; + +//////////////////////////////////////////////////////////////////// +// +// Codec Register Data Path +// + +// Control +assign out_slt1[19] = crac_out[31]; +assign out_slt1[18:12] = crac_out[22:16]; +assign out_slt1[11:0] = 12'h0; + +// Write Data +assign out_slt2[19:4] = crac_out[15:0]; +assign out_slt2[3:0] = 4'h0; + +// Read Data +always @(posedge clk or negedge rst) + begin + if(!rst) crac_din <= #1 16'h0; + else + if(crac_rd_done) crac_din <= #1 in_slt2[19:4]; + end + +//////////////////////////////////////////////////////////////////// +// +// Codec Register Access Tracking +// + +assign crac_valid = crac_wr | crac_rd; + +always @(posedge clk) + crac_we_r <= #1 crac_we; + +always @(posedge clk or negedge rst) + if(!rst) crac_wr <= #1 1'b0; + else + if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1; + else + if(valid_ne) crac_wr <= #1 1'b0; + +assign crac_wr_done = crac_wr & valid_ne; + +always @(posedge clk or negedge rst) + if(!rst) crac_rd <= #1 1'b0; + else + if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1; + else + if(rdd1 & valid_pe) crac_rd <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd1 <= #1 1'b0; + else + if(crac_rd & valid_ne) rdd1 <= #1 1'b1; + else + if(!crac_rd) rdd1 <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd2 <= #1 1'b0; + else + if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1; + else + if(crac_rd_done) rdd2 <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) rdd3 <= #1 1'b0; + else + if(rdd2 & valid_pe) rdd3 <= #1 1'b1; + else + if(crac_rd_done) rdd3 <= #1 1'b0; + +always @(posedge clk) + crac_rd_done <= #1 rdd3 & valid_pe; + +always @(posedge clk) + valid_r <= #1 valid; + +assign valid_ne = !valid & valid_r; + +assign valid_pe = valid & !valid_r; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_defines.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_defines.v new file mode 100644 index 000000000..7667c26a0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_defines.v @@ -0,0 +1,173 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_defines.v,v 1.5 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_defines.v,v $ +// Revision 1.5 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.4 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`timescale 1ns / 10ps + +///////////////////////////////////////////////////////////////////// +// This AC97 Controller supports up to 6 Output and 3 Input Channels. +// Comment out the define statement for which channels you do not wish +// to support in your implementation. The main Left and Right channels +// are always supported. + +// Surround Left + Right +`define AC97_SURROUND 1 + +// Center Channel +`define AC97_CENTER 1 + +// LFE Channel +`define AC97_LFE 1 + +// Stereo Input +`define AC97_SIN 1 + +// Mono Microphone Input +`define AC97_MICIN 1 + +///////////////////////////////////////////////////////////////////// +// +// This define selects how the WISHBONE interface determines if +// the internal register file is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define AC97_REG_SEL (wb_addr_i[31:29] == 3'h0) + +///////////////////////////////////////////////////////////////////// +// +// This is a prescaler that generates a pulse every 250 nS. +// The value here should one less than the actually calculated +// value. +// For a 200 MHz wishbone clock, this value is 49 (50-1). +`define AC97_250_PS 6'h31 + +///////////////////////////////////////////////////////////////////// +// +// AC97 Cold reset Must be asserted for at least 1uS. The AC97 +// controller will stretch the reset pulse to at least 1uS. +// The reset timer is driven by the AC97_250_PS prescaler. +// This value should probably be never changed. Adjust the +// AC97_250_PS instead. +`define AC97_RST_DEL 3'h4 + +///////////////////////////////////////////////////////////////////// +// +// This value indicates for how long the resume signaling (asserting sync) +// should be done. This counter is driven by the AC97_250_PS prescaler. +// This value times 250nS is the duration of the resume signaling. +// The actual value must be incremented by one, as we do not know +// the current state of the prescaler, and must somehow insure we +// meet the minimum 1uS length. This value should probably be never +// changed. Modify the AC97_250_PS instead. +`define AC97_RES_SIG 3'h5 + +///////////////////////////////////////////////////////////////////// +// +// If the bit clock is absent for at least two "predicted" bit +// clock periods (163 nS) we should signal "suspended". +// This value defines how many WISHBONE cycles must pass without +// any change on the bit clock input before we signal "suspended". +// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles. +`define AC97_SUSP_DET 6'h21 + +///////////////////////////////////////////////////////////////////// +// +// Select FIFO Depth. For most applications a FIFO depth of 4 should +// be sufficient. For systems with slow interrupt processing or slow +// DMA response or systems with low internal bus bandwidth you might +// want to increase the FIFO sizes to reduce the interrupt/DMA service +// request frequencies. +// Service request frequency can be calculated as follows: +// Channel bandwidth / FIFO size = Service Request Frequency +// For Example: 48KHz / 4 = 12 kHz +// +// Select Input FIFO depth by uncommenting ONE of the following define +// statements: +`define AC97_IN_FIFO_DEPTH_4 +//`define AC97_IN_FIFO_DEPTH_8 +//`define AC97_IN_FIFO_DEPTH_16 +// +// Select Output FIFO depth by uncommenting ONE of the following define +// statements: +`define AC97_OUT_FIFO_DEPTH_4 +//`define AC97_OUT_FIFO_DEPTH_8 +//`define AC97_OUT_FIFO_DEPTH_16 + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_if.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_if.v new file mode 100644 index 000000000..da10b165e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_if.v @@ -0,0 +1,220 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// DMA Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_dma_if.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_dma_if.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_dma_if(clk, rst, + o3_status, o4_status, o6_status, o7_status, o8_status, o9_status, + o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty, + i3_status, i4_status, i6_status, + i3_full, i4_full, i6_full, + + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + + dma_req, dma_ack); + +input clk, rst; +input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status; +input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty; +input [1:0] i3_status, i4_status, i6_status; +input i3_full, i4_full, i6_full; +input [7:0] oc0_cfg; +input [7:0] oc1_cfg; +input [7:0] oc2_cfg; +input [7:0] oc3_cfg; +input [7:0] oc4_cfg; +input [7:0] oc5_cfg; +input [7:0] ic0_cfg; +input [7:0] ic1_cfg; +input [7:0] ic2_cfg; +output [8:0] dma_req; +input [8:0] dma_ack; + +//////////////////////////////////////////////////////////////////// +// +// DMA Request Modules +// + +ac97_dma_req u0(.clk( clk ), + .rst( rst ), + .cfg( oc0_cfg ), + .status( o3_status ), + .full_empty( o3_empty ), + .dma_req( dma_req[0] ), + .dma_ack( dma_ack[0] ) + ); + +ac97_dma_req u1(.clk( clk ), + .rst( rst ), + .cfg( oc1_cfg ), + .status( o4_status ), + .full_empty( o4_empty ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ) + ); + +`ifdef AC97_CENTER +ac97_dma_req u2(.clk( clk ), + .rst( rst ), + .cfg( oc2_cfg ), + .status( o6_status ), + .full_empty( o6_empty ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ) + ); +`else +assign dma_req[2] = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_dma_req u3(.clk( clk ), + .rst( rst ), + .cfg( oc3_cfg ), + .status( o7_status ), + .full_empty( o7_empty ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ) + ); + +ac97_dma_req u4(.clk( clk ), + .rst( rst ), + .cfg( oc4_cfg ), + .status( o8_status ), + .full_empty( o8_empty ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ) + ); +`else +assign dma_req[3] = 1'b0; +assign dma_req[4] = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_dma_req u5(.clk( clk ), + .rst( rst ), + .cfg( oc5_cfg ), + .status( o9_status ), + .full_empty( o9_empty ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ) + ); +`else +assign dma_req[5] = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_dma_req u6(.clk( clk ), + .rst( rst ), + .cfg( ic0_cfg ), + .status( i3_status ), + .full_empty( i3_full ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ) + ); + +ac97_dma_req u7(.clk( clk ), + .rst( rst ), + .cfg( ic1_cfg ), + .status( i4_status ), + .full_empty( i4_full ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ) + ); +`else +assign dma_req[6] = 1'b0; +assign dma_req[7] = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_dma_req u8(.clk( clk ), + .rst( rst ), + .cfg( ic2_cfg ), + .status( i6_status ), + .full_empty( i6_full ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ) + ); +`else +assign dma_req[8] = 1'b0; +`endif + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_req.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_req.v new file mode 100644 index 000000000..853dbefbf --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_dma_req.v @@ -0,0 +1,119 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// DMA Request Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_dma_req.v,v 1.3 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_dma_req.v,v $ +// Revision 1.3 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack); +input clk, rst; +input [7:0] cfg; +input [1:0] status; +input full_empty; +output dma_req; +input dma_ack; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// +reg dma_req_d; +reg dma_req_r1; +reg dma_req; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(cfg or status or full_empty) + case(cfg[5:4]) // synopsys parallel_case full_case + // REQ = Ch_EN & DMA_EN & Status + // 1/4 full/empty + 2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0)); + // 1/2 full/empty + 2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0)); + // 3/4 full/empty + 2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3)); + 2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty; + endcase + +always @(posedge clk) + dma_req_r1 <= #1 dma_req_d & !dma_ack; + +always @(posedge clk or negedge rst) + if(!rst) dma_req <= #1 1'b0; + else + if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1; + else + if(dma_ack) dma_req <= #1 1'b0; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_fifo_ctrl.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_fifo_ctrl.v new file mode 100644 index 000000000..9db66a0f7 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_fifo_ctrl.v @@ -0,0 +1,117 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// FIFO Control Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_fifo_ctrl.v,v 1.3 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_fifo_ctrl.v,v $ +// Revision 1.3 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:49 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_fifo_ctrl( clk, + valid, ch_en, srs, full_empty, req, crdy, + en_out, en_out_l + ); +input clk; +input valid; +input ch_en; // Channel Enable +input srs; // Sample Rate Select +input full_empty; // Fifo Status +input req; // Codec Request +input crdy; // Codec Ready +output en_out; // Output read/write pulse +output en_out_l; // Latched Output + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg en_out_l, en_out_l2; +reg full_empty_r; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + if(!valid) full_empty_r <= #1 full_empty; + +always @(posedge clk) + if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) ) + en_out_l <= #1 1'b1; + else + if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) ) + en_out_l <= #1 1'b0; + +always @(posedge clk) + en_out_l2 <= #1 en_out_l & valid; + +assign en_out = en_out_l & !en_out_l2 & valid; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_in_fifo.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_in_fifo.v new file mode 100644 index 000000000..e0710005d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_in_fifo.v @@ -0,0 +1,342 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Output FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_in_fifo.v,v 1.5 2002/11/14 17:10:12 rudi Exp $ +// +// $Date: 2002/11/14 17:10:12 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_in_fifo.v,v $ +// Revision 1.5 2002/11/14 17:10:12 rudi +// Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. +// +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +`ifdef AC97_IN_FIFO_DEPTH_4 + +// 4 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:3]; +reg [31:0] dout; + +reg [3:0] wp; +reg [2:0] rp; + +wire [3:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 4'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2); + +always @(posedge clk) + if(!en) rp <= #1 3'h0; + else + if(re) rp <= #1 rp + 3'h1; + +always @(posedge clk) + status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[1:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp; + +endmodule + +`endif + +`ifdef AC97_IN_FIFO_DEPTH_8 + +// 8 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:7]; +reg [31:0] dout; + +reg [4:0] wp; +reg [3:0] rp; + +wire [4:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 5'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2); + +always @(posedge clk) + if(!en) rp <= #1 4'h0; + else + if(re) rp <= #1 rp + 4'h1; + +always @(posedge clk) + status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[2:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp; + +endmodule + +`endif + + +`ifdef AC97_IN_FIFO_DEPTH_16 + +// 16 entry deep verion of the input FIFO + +module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [19:0] din; +input we; +output [31:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:15]; +reg [31:0] dout; + +reg [5:0] wp; +reg [4:0] rp; + +wire [5:0] wp_p1; + +reg [1:0] status; +reg [15:0] din_tmp1; +reg [31:0] din_tmp; +wire m16b; +reg full, empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 6'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2); + +always @(posedge clk) + if(!en) rp <= #1 5'h0; + else + if(re) rp <= #1 rp + 5'h1; + +always @(posedge clk) + status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1); + +always @(posedge clk) + empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0); + +always @(posedge clk) + full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]); + +// Fifo Output +always @(posedge clk) + dout <= #1 mem[ rp[3:0] ]; + +// Fifo Input Half Word Latch +always @(posedge clk) + if(we & !wp[0]) din_tmp1 <= #1 din[19:4]; + +always @(mode or din_tmp1 or din) + case(mode) // synopsys parallel_case full_case + 2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output + 2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output + 2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output + endcase + +always @(posedge clk) + if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp; + +endmodule + +`endif diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_int.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_int.v new file mode 100644 index 000000000..082f9dacc --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_int.v @@ -0,0 +1,126 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Interrupt Logic //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_int.v,v 1.3 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_int.v,v $ +// Revision 1.3 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:18 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_int(clk, rst, + + // Register File Interface + int_set, + + // FIFO Interface + cfg, status, full_empty, full, empty, re, we + ); + +input clk, rst; +output [2:0] int_set; + +input [7:0] cfg; +input [1:0] status; +input full_empty, full, empty, re, we; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [2:0] int_set; + +//////////////////////////////////////////////////////////////////// +// +// Interrupt Logic +// + +always @(posedge clk or negedge rst) + if(!rst) int_set[0] <= #1 1'b0; + else + case(cfg[5:4]) // synopsys parallel_case full_case + // 1/4 full/empty + 2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0)); + // 1/2 full/empty + 2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0)); + // 3/4 full/empty + 2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3)); + 2'h3: int_set[0] <= #1 cfg[0] & full_empty; + endcase + +always @(posedge clk or negedge rst) + if(!rst) int_set[1] <= #1 1'b0; + else + if(empty & re) int_set[1] <= #1 1'b1; + +always @(posedge clk or negedge rst) + if(!rst) int_set[2] <= #1 1'b0; + else + if(full & we) int_set[2] <= #1 1'b1; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_out_fifo.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_out_fifo.v new file mode 100644 index 000000000..a2fb29e6d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_out_fifo.v @@ -0,0 +1,348 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Output FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_out_fifo.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_out_fifo.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/11 03:21:22 rudi +// +// - Added defines to select fifo depth between 4, 8 and 16 entries. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +`ifdef AC97_OUT_FIFO_DEPTH_4 + +// 4 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:3]; + +reg [2:0] wp; +reg [3:0] rp; + +wire [2:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 3'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 3'h1; + +always @(posedge clk) + if(!en) rp <= #1 4'h0; + else + if(re & m16b) rp <= #1 rp + 4'h1; + else + if(re & !m16b) rp <= #1 rp + 4'h2; + +always @(posedge clk) + status <= #1 (wp[1:0] - rp[2:1]) - 2'h1; + +wire [3:0] rp_p1 = rp[3:0] + 4'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]); + +// Fifo Output +assign dout_tmp = mem[ rp[2:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + +always @(posedge clk) + if(we) mem[wp[1:0]] <= #1 din; + +endmodule + +`endif + +`ifdef AC97_OUT_FIFO_DEPTH_8 + +// 8 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:7]; + +reg [3:0] wp; +reg [4:0] rp; + +wire [3:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 4'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 4'h1; + +always @(posedge clk) + if(!en) rp <= #1 5'h0; + else + if(re & m16b) rp <= #1 rp + 5'h1; + else + if(re & !m16b) rp <= #1 rp + 5'h2; + +always @(posedge clk) + status <= #1 (wp[2:1] - rp[3:2]) - 2'h1; + +wire [4:0] rp_p1 = rp[4:0] + 5'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]); + +// Fifo Output +assign dout_tmp = mem[ rp[3:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + + +always @(posedge clk) + if(we) mem[wp[2:0]] <= #1 din; + +endmodule + +`endif + + +`ifdef AC97_OUT_FIFO_DEPTH_16 + +// 16 Entry Deep version of the Output FIFO + +module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty); + +input clk, rst; +input en; +input [1:0] mode; +input [31:0] din; +input we; +output [19:0] dout; +input re; +output [1:0] status; +output full; +output empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] mem[0:15]; + +reg [4:0] wp; +reg [5:0] rp; + +wire [4:0] wp_p1; + +reg [1:0] status; +reg [19:0] dout; +wire [31:0] dout_tmp; +wire [15:0] dout_tmp1; +wire m16b; +reg empty; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign m16b = (mode == 2'h0); // 16 Bit Mode + +always @(posedge clk) + if(!en) wp <= #1 5'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 4'h1; + +always @(posedge clk) + if(!en) rp <= #1 6'h0; + else + if(re & m16b) rp <= #1 rp + 6'h1; + else + if(re & !m16b) rp <= #1 rp + 6'h2; + +always @(posedge clk) + status <= #1 (wp[3:2] - rp[4:3]) - 2'h1; + +wire [5:0] rp_p1 = rp[5:0] + 6'h1; + +always @(posedge clk) + empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1); + +assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]); + +// Fifo Output +assign dout_tmp = mem[ rp[4:1] ]; + +// Fifo Output Half Word Select +assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0]; + +always @(posedge clk) + if(!en) dout <= #1 20'h0; + else + if(re) + case(mode) // synopsys parallel_case full_case + 2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output + 2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output + 2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output + endcase + + +always @(posedge clk) + if(we) mem[wp[3:0]] <= #1 din; + +endmodule + +`endif diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_prc.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_prc.v new file mode 100644 index 000000000..f7881f28b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_prc.v @@ -0,0 +1,336 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// PCM Request Controller //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_prc.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_prc.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:17 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_prc(clk, rst, + + // SR Slot Interface + valid, in_valid, out_slt0, + in_slt0, in_slt1, + + // Codec Register Access + crac_valid, crac_wr, + + // Channel Configuration + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + + // FIFO Status + o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, + o9_empty, i3_full, i4_full, i6_full, + + // FIFO Control + o3_re, o4_re, o6_re, o7_re, o8_re, o9_re, + i3_we, i4_we, i6_we + + ); +input clk, rst; + +input valid; +input [2:0] in_valid; +output [15:0] out_slt0; +input [15:0] in_slt0; +input [19:0] in_slt1; + +input crac_valid; +input crac_wr; + +input [7:0] oc0_cfg; +input [7:0] oc1_cfg; +input [7:0] oc2_cfg; +input [7:0] oc3_cfg; +input [7:0] oc4_cfg; +input [7:0] oc5_cfg; + +input [7:0] ic0_cfg; +input [7:0] ic1_cfg; +input [7:0] ic2_cfg; + +input o3_empty; +input o4_empty; +input o6_empty; +input o7_empty; +input o8_empty; +input o9_empty; +input i3_full; +input i4_full; +input i6_full; + +output o3_re; +output o4_re; +output o6_re; +output o7_re; +output o8_re; +output o9_re; +output i3_we; +output i4_we; +output i6_we; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire o3_re_l; +wire o4_re_l; +wire o6_re_l; +wire o7_re_l; +wire o8_re_l; +wire o9_re_l; + +reg crac_valid_r; +reg crac_wr_r; + +//////////////////////////////////////////////////////////////////// +// +// Output Tag Assembly +// + +assign out_slt0[15] = |out_slt0[14:6]; + +assign out_slt0[14] = crac_valid_r; +assign out_slt0[13] = crac_wr_r; + +assign out_slt0[12] = o3_re_l; +assign out_slt0[11] = o4_re_l; +assign out_slt0[10] = 1'b0; +assign out_slt0[09] = o6_re_l; +assign out_slt0[08] = o7_re_l; +assign out_slt0[07] = o8_re_l; +assign out_slt0[06] = o9_re_l; +assign out_slt0[5:0] = 6'h0; + +//////////////////////////////////////////////////////////////////// +// +// FIFO Control +// + +always @(posedge clk) + if(valid) crac_valid_r <= #1 crac_valid; + +always @(posedge clk) + if(valid) crac_wr_r <= #1 crac_valid & crac_wr; + +// Output Channel 0 (Out Slot 3) +ac97_fifo_ctrl u0( + .clk( clk ), + .valid( valid ), + .ch_en( oc0_cfg[0] ), + .srs( oc0_cfg[1] ), + .full_empty( o3_empty ), + .req( ~in_slt1[11] ), + .crdy( in_slt0[15] ), + .en_out( o3_re ), + .en_out_l( o3_re_l ) + ); + +// Output Channel 1 (Out Slot 4) +ac97_fifo_ctrl u1( + .clk( clk ), + .valid( valid ), + .ch_en( oc1_cfg[0] ), + .srs( oc1_cfg[1] ), + .full_empty( o4_empty ), + .req( ~in_slt1[10] ), + .crdy( in_slt0[15] ), + .en_out( o4_re ), + .en_out_l( o4_re_l ) + ); + +`ifdef AC97_CENTER +// Output Channel 2 (Out Slot 6) +ac97_fifo_ctrl u2( + .clk( clk ), + .valid( valid ), + .ch_en( oc2_cfg[0] ), + .srs( oc2_cfg[1] ), + .full_empty( o6_empty ), + .req( ~in_slt1[8] ), + .crdy( in_slt0[15] ), + .en_out( o6_re ), + .en_out_l( o6_re_l ) + ); +`else +assign o6_re = 1'b0; +assign o6_re_l = 1'b0; +`endif + +`ifdef AC97_SURROUND +// Output Channel 3 (Out Slot 7) +ac97_fifo_ctrl u3( + .clk( clk ), + .valid( valid ), + .ch_en( oc3_cfg[0] ), + .srs( oc3_cfg[1] ), + .full_empty( o7_empty ), + .req( ~in_slt1[7] ), + .crdy( in_slt0[15] ), + .en_out( o7_re ), + .en_out_l( o7_re_l ) + ); + +// Output Channel 4 (Out Slot 8) +ac97_fifo_ctrl u4( + .clk( clk ), + .valid( valid ), + .ch_en( oc4_cfg[0] ), + .srs( oc4_cfg[1] ), + .full_empty( o8_empty ), + .req( ~in_slt1[6] ), + .crdy( in_slt0[15] ), + .en_out( o8_re ), + .en_out_l( o8_re_l ) + ); +`else +assign o7_re = 1'b0; +assign o7_re_l = 1'b0; +assign o8_re = 1'b0; +assign o8_re_l = 1'b0; +`endif + +`ifdef AC97_LFE +// Output Channel 5 (Out Slot 9) +ac97_fifo_ctrl u5( + .clk( clk ), + .valid( valid ), + .ch_en( oc5_cfg[0] ), + .srs( oc5_cfg[1] ), + .full_empty( o9_empty ), + .req( ~in_slt1[5] ), + .crdy( in_slt0[15] ), + .en_out( o9_re ), + .en_out_l( o9_re_l ) + ); +`else +assign o9_re = 1'b0; +assign o9_re_l = 1'b0; +`endif + +`ifdef AC97_SIN +// Input Channel 0 (In Slot 3) +ac97_fifo_ctrl u6( + .clk( clk ), + .valid( in_valid[0] ), + .ch_en( ic0_cfg[0] ), + .srs( ic0_cfg[1] ), + .full_empty( i3_full ), + .req( in_slt0[12] ), + .crdy( in_slt0[15] ), + .en_out( i3_we ), + .en_out_l( ) + ); + +// Input Channel 1 (In Slot 4) +ac97_fifo_ctrl u7( + .clk( clk ), + .valid( in_valid[1] ), + .ch_en( ic1_cfg[0] ), + .srs( ic1_cfg[1] ), + .full_empty( i4_full ), + .req( in_slt0[11] ), + .crdy( in_slt0[15] ), + .en_out( i4_we ), + .en_out_l( ) + ); +`else +assign i3_we = 1'b0; +assign i4_we = 1'b0; +`endif + +`ifdef AC97_MICIN +// Input Channel 2 (In Slot 6) +ac97_fifo_ctrl u8( + .clk( clk ), + .valid( in_valid[2] ), + .ch_en( ic2_cfg[0] ), + .srs( ic2_cfg[1] ), + .full_empty( i6_full ), + .req( in_slt0[9] ), + .crdy( in_slt0[15] ), + .en_out( i6_we ), + .en_out_l( ) + ); +`else +assign i6_we = 1'b0; +`endif + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rf.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rf.v new file mode 100644 index 000000000..57839b982 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rf.v @@ -0,0 +1,306 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_rf.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_rf.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:17 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_rf(clk, rst, + + adr, rf_dout, rf_din, + rf_we, rf_re, int, ac97_rst_force, + resume_req, suspended, + + crac_we, crac_din, crac_out, + crac_rd_done, crac_wr_done, + + oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg, + ic0_cfg, ic1_cfg, ic2_cfg, + oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set, + oc4_int_set, oc5_int_set, + ic0_int_set, ic1_int_set, ic2_int_set + + ); + +input clk,rst; + +input [3:0] adr; +output [31:0] rf_dout; +input [31:0] rf_din; +input rf_we; +input rf_re; +output int; +output ac97_rst_force; +output resume_req; +input suspended; + +output crac_we; +input [15:0] crac_din; +output [31:0] crac_out; +input crac_rd_done, crac_wr_done; + +output [7:0] oc0_cfg; +output [7:0] oc1_cfg; +output [7:0] oc2_cfg; +output [7:0] oc3_cfg; +output [7:0] oc4_cfg; +output [7:0] oc5_cfg; + +output [7:0] ic0_cfg; +output [7:0] ic1_cfg; +output [7:0] ic2_cfg; + +input [2:0] oc0_int_set; +input [2:0] oc1_int_set; +input [2:0] oc2_int_set; +input [2:0] oc3_int_set; +input [2:0] oc4_int_set; +input [2:0] oc5_int_set; +input [2:0] ic0_int_set; +input [2:0] ic1_int_set; +input [2:0] ic2_int_set; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] rf_dout; + +reg [31:0] csr_r; +reg [31:0] occ0_r; +reg [15:0] occ1_r; +reg [23:0] icc_r; +reg [31:0] crac_r; +reg [28:0] intm_r; +reg [28:0] ints_r; +reg int; +wire [28:0] int_all; +wire [31:0] csr, occ0, occ1, icc, crac, intm, ints; +reg [15:0] crac_dout_r; +reg ac97_rst_force; +reg resume_req; + +// Aliases +assign csr = {30'h0, suspended, 1'h0}; +assign occ0 = occ0_r; +assign occ1 = {16'h0, occ1_r}; +assign icc = {8'h0, icc_r}; +assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din}; +assign intm = {3'h0, intm_r}; +assign ints = {3'h0, ints_r}; + +assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r}; + +//////////////////////////////////////////////////////////////////// +// +// Register WISHBONE Interface +// + +always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints) + case(adr[2:0]) // synopsys parallel_case full_case + 0: rf_dout = csr; + 1: rf_dout = occ0; + 2: rf_dout = occ1; + 3: rf_dout = icc; + 4: rf_dout = crac; + 5: rf_dout = intm; + 6: rf_dout = ints; + endcase + +always @(posedge clk or negedge rst) + if(!rst) csr_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din; + +always @(posedge clk) + if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0]; + else ac97_rst_force <= #1 1'b0; + +always @(posedge clk) + if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1]; + else resume_req <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) occ0_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din; + +always @(posedge clk or negedge rst) + if(!rst) occ1_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0]; + +always @(posedge clk or negedge rst) + if(!rst) icc_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0]; + +assign crac_we = rf_we & (adr[2:0]==3'h4); + +always @(posedge clk or negedge rst) + if(!rst) crac_r <= #1 1'b0; + else + if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]}; + +always @(posedge clk) + if(crac_we) crac_dout_r <= #1 rf_din[15:0]; + +always @(posedge clk or negedge rst) + if(!rst) intm_r <= #1 1'b0; + else + if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0]; + +// Interrupt Source Register +always @(posedge clk or negedge rst) + if(!rst) ints_r <= #1 1'b0; + else + if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0; + else + begin + if(crac_rd_done) ints_r[0] <= #1 1'b1; + if(crac_wr_done) ints_r[1] <= #1 1'b1; + if(oc0_int_set[0]) ints_r[2] <= #1 1'b1; + if(oc0_int_set[1]) ints_r[3] <= #1 1'b1; + if(oc0_int_set[2]) ints_r[4] <= #1 1'b1; + if(oc1_int_set[0]) ints_r[5] <= #1 1'b1; + if(oc1_int_set[1]) ints_r[6] <= #1 1'b1; + if(oc1_int_set[2]) ints_r[7] <= #1 1'b1; +`ifdef AC97_CENTER + if(oc2_int_set[0]) ints_r[8] <= #1 1'b1; + if(oc2_int_set[1]) ints_r[9] <= #1 1'b1; + if(oc2_int_set[2]) ints_r[10] <= #1 1'b1; +`endif + +`ifdef AC97_SURROUND + if(oc3_int_set[0]) ints_r[11] <= #1 1'b1; + if(oc3_int_set[1]) ints_r[12] <= #1 1'b1; + if(oc3_int_set[2]) ints_r[13] <= #1 1'b1; + if(oc4_int_set[0]) ints_r[14] <= #1 1'b1; + if(oc4_int_set[1]) ints_r[15] <= #1 1'b1; + if(oc4_int_set[2]) ints_r[16] <= #1 1'b1; +`endif + +`ifdef AC97_LFE + if(oc5_int_set[0]) ints_r[17] <= #1 1'b1; + if(oc5_int_set[1]) ints_r[18] <= #1 1'b1; + if(oc5_int_set[2]) ints_r[19] <= #1 1'b1; +`endif + +`ifdef AC97_SIN + if(ic0_int_set[0]) ints_r[20] <= #1 1'b1; + if(ic0_int_set[1]) ints_r[21] <= #1 1'b1; + if(ic0_int_set[2]) ints_r[22] <= #1 1'b1; + if(ic1_int_set[0]) ints_r[23] <= #1 1'b1; + if(ic1_int_set[1]) ints_r[24] <= #1 1'b1; + if(ic1_int_set[2]) ints_r[25] <= #1 1'b1; +`endif + +`ifdef AC97_MICIN + if(ic2_int_set[0]) ints_r[26] <= #1 1'b1; + if(ic2_int_set[1]) ints_r[27] <= #1 1'b1; + if(ic2_int_set[2]) ints_r[28] <= #1 1'b1; +`endif + end + +//////////////////////////////////////////////////////////////////// +// +// Register Internal Interface +// + +assign oc0_cfg = occ0[7:0]; +assign oc1_cfg = occ0[15:8]; +assign oc2_cfg = occ0[23:16]; +assign oc3_cfg = occ0[31:24]; +assign oc4_cfg = occ1[7:0]; +assign oc5_cfg = occ1[15:8]; + +assign ic0_cfg = icc[7:0]; +assign ic1_cfg = icc[15:8]; +assign ic2_cfg = icc[23:16]; + +//////////////////////////////////////////////////////////////////// +// +// Interrupt Generation +// + +assign int_all = intm_r & ints_r; + +always @(posedge clk) + int <= #1 |int_all; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rst.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rst.v new file mode 100644 index 000000000..8b16bcfa4 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_rst.v @@ -0,0 +1,103 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Reset Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_rst.v,v 1.1 2001/08/03 06:54:50 rudi Exp $ +// +// $Date: 2001/08/03 06:54:50 $ +// $Revision: 1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_rst.v,v $ +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:19 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_); +input clk, rst; +input rst_force; +output ps_ce; +output ac97_rst_; + +reg ac97_rst_; +reg [2:0] cnt; +wire ce; +wire to; +reg [5:0] ps_cnt; +wire ps_ce; + +always @(posedge clk or negedge rst) + if(!rst) ac97_rst_ <= #1 0; + else + if(rst_force) ac97_rst_ <= #1 0; + else + if(to) ac97_rst_ <= #1 1; + +assign to = (cnt == `AC97_RST_DEL); + +always @(posedge clk or negedge rst) + if(!rst) cnt <= #1 0; + else + if(rst_force) cnt <= #1 0; + else + if(ce) cnt <= #1 cnt + 1; + +assign ce = ps_ce & (cnt != `AC97_RST_DEL); + +always @(posedge clk or negedge rst) + if(!rst) ps_cnt <= #1 0; + else + if(ps_ce | rst_force) ps_cnt <= #1 0; + else ps_cnt <= #1 ps_cnt + 1; + +assign ps_ce = (ps_cnt == `AC97_250_PS); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sin.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sin.v new file mode 100644 index 000000000..9a8d8b405 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sin.v @@ -0,0 +1,145 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Input Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_sin.v,v 1.2 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_sin.v,v $ +// Revision 1.2 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_sin(clk, rst, + + out_le, slt0, slt1, slt2, slt3, slt4, + slt6, + + sdata_in + ); + +input clk, rst; + +// -------------------------------------- +// Misc Signals +input [5:0] out_le; +output [15:0] slt0; +output [19:0] slt1; +output [19:0] slt2; +output [19:0] slt3; +output [19:0] slt4; +output [19:0] slt6; + +// -------------------------------------- +// AC97 Codec Interface +input sdata_in; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg sdata_in_r; +reg [19:0] sr; + +reg [15:0] slt0; +reg [19:0] slt1; +reg [19:0] slt2; +reg [19:0] slt3; +reg [19:0] slt4; +reg [19:0] slt6; + +//////////////////////////////////////////////////////////////////// +// +// Output Registers +// + +always @(posedge clk) + if(out_le[0]) slt0 <= #1 sr[15:0]; + +always @(posedge clk) + if(out_le[1]) slt1 <= #1 sr; + +always @(posedge clk) + if(out_le[2]) slt2 <= #1 sr; + +always @(posedge clk) + if(out_le[3]) slt3 <= #1 sr; + +always @(posedge clk) + if(out_le[4]) slt4 <= #1 sr; + +always @(posedge clk) + if(out_le[5]) slt6 <= #1 sr; + +//////////////////////////////////////////////////////////////////// +// +// Serial Shift Register +// + +always @(negedge clk) + sdata_in_r <= #1 sdata_in; + +always @(posedge clk) + sr <= #1 {sr[18:0], sdata_in_r }; + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_soc.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_soc.v new file mode 100644 index 000000000..2236d1e1c --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_soc.v @@ -0,0 +1,205 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Output Controller //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_soc.v,v 1.3 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_soc.v,v $ +// Revision 1.3 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.2 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_soc(clk, wclk, rst, + ps_ce, resume, suspended, + sync, out_le, in_valid, ld, valid + ); + +input clk, wclk, rst; +input ps_ce; +input resume; +output suspended; +output sync; +output [5:0] out_le; +output [2:0] in_valid; +output ld; +output valid; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [7:0] cnt; +reg sync_beat; +reg sync_resume; +reg [5:0] out_le; +reg ld; +reg valid; +reg [2:0] in_valid; +reg bit_clk_r; +reg bit_clk_r1; +reg bit_clk_e; +reg suspended; +wire to; +reg [5:0] to_cnt; +reg [3:0] res_cnt; +wire resume_done; + +assign sync = sync_beat | sync_resume; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk or negedge rst) + if(!rst) cnt <= #1 8'hff; + else + if(suspended) cnt <= #1 8'hff; + else cnt <= #1 cnt + 8'h1; + +always @(posedge clk) + ld <= #1 (cnt == 8'h00); + +always @(posedge clk) + sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10)); + +always @(posedge clk) + valid <= #1 (cnt > 8'h39); + +always @(posedge clk) + out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable + +always @(posedge clk) + out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable + +always @(posedge clk) + out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable + +always @(posedge clk) + out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable + +always @(posedge clk) + out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable + +always @(posedge clk) + out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable + +always @(posedge clk) + in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid + +always @(posedge clk) + in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid + +always @(posedge clk) + in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid + +//////////////////////////////////////////////////////////////////// +// +// Suspend Detect +// + +always @(posedge wclk) + bit_clk_r <= #1 clk; + +always @(posedge wclk) + bit_clk_r1 <= #1 bit_clk_r; + +always @(posedge wclk) + bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1); + +always @(posedge wclk) + suspended <= #1 to; + +assign to = (to_cnt == `AC97_SUSP_DET); + +always @(posedge wclk or negedge rst) + if(!rst) to_cnt <= #1 6'h0; + else + if(bit_clk_e) to_cnt <= #1 6'h0; + else + if(!to) to_cnt <= #1 to_cnt + 6'h1; + +//////////////////////////////////////////////////////////////////// +// +// Resume Signaling +// + +always @(posedge wclk or negedge rst) + if(!rst) sync_resume <= #1 1'b0; + else + if(resume_done) sync_resume <= #1 1'b0; + else + if(suspended & resume) sync_resume <= #1 1'b1; + +assign resume_done = (res_cnt == `AC97_RES_SIG); + +always @(posedge wclk) + if(!sync_resume) res_cnt <= #1 4'h0; + else + if(ps_ce) res_cnt <= #1 res_cnt + 4'h1; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sout.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sout.v new file mode 100644 index 000000000..7d9d34b73 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_sout.v @@ -0,0 +1,183 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// Serial Output Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_sout.v,v 1.2 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_sout.v,v $ +// Revision 1.2 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:15 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_sout(clk, rst, + + so_ld, slt0, slt1, slt2, slt3, slt4, + slt6, slt7, slt8, slt9, + + sdata_out + ); + +input clk, rst; + +// -------------------------------------- +// Misc Signals +input so_ld; +input [15:0] slt0; +input [19:0] slt1; +input [19:0] slt2; +input [19:0] slt3; +input [19:0] slt4; +input [19:0] slt6; +input [19:0] slt7; +input [19:0] slt8; +input [19:0] slt9; + +// -------------------------------------- +// AC97 Codec Interface +output sdata_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire sdata_out; + +reg [15:0] slt0_r; +reg [19:0] slt1_r; +reg [19:0] slt2_r; +reg [19:0] slt3_r; +reg [19:0] slt4_r; +reg [19:0] slt5_r; +reg [19:0] slt6_r; +reg [19:0] slt7_r; +reg [19:0] slt8_r; +reg [19:0] slt9_r; +reg [19:0] slt10_r; +reg [19:0] slt11_r; +reg [19:0] slt12_r; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +//////////////////////////////////////////////////////////////////// +// +// Serial Shift Register +// + +assign sdata_out = slt0_r[15]; + +always @(posedge clk) + if(so_ld) slt0_r <= #1 slt0; + else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]}; + +always @(posedge clk) + if(so_ld) slt1_r <= #1 slt1; + else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]}; + +always @(posedge clk) + if(so_ld) slt2_r <= #1 slt2; + else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]}; + +always @(posedge clk) + if(so_ld) slt3_r <= #1 slt3; + else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]}; + +always @(posedge clk) + if(so_ld) slt4_r <= #1 slt4; + else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]}; + +always @(posedge clk) + if(so_ld) slt5_r <= #1 20'h0; + else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]}; + +always @(posedge clk) + if(so_ld) slt6_r <= #1 slt6; + else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]}; + +always @(posedge clk) + if(so_ld) slt7_r <= #1 slt7; + else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]}; + +always @(posedge clk) + if(so_ld) slt8_r <= #1 slt8; + else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]}; + +always @(posedge clk) + if(so_ld) slt9_r <= #1 slt9; + else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]}; + +always @(posedge clk) + if(so_ld) slt10_r <= #1 20'h0; + else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]}; + +always @(posedge clk) + if(so_ld) slt11_r <= #1 20'h0; + else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]}; + +always @(posedge clk) + if(so_ld) slt12_r <= #1 20'h0; + else slt12_r <= #1 {slt12_r[18:0], 1'b0 }; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_top.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_top.v new file mode 100644 index 000000000..3460d4a45 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_top.v @@ -0,0 +1,761 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_top.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_top.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:14 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_top(clk_i, rst_i, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + int_o, dma_req_o, dma_ack_i, + suspended_o, + + bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i, + ac97_reset_pad_o_ + ); + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE SLAVE INTERFACE +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// -------------------------------------- +// Misc Signals +output int_o; +output [8:0] dma_req_o; +input [8:0] dma_ack_i; + +// -------------------------------------- +// Suspend Resume Interface +output suspended_o; + +// -------------------------------------- +// AC97 Codec Interface +input bit_clk_pad_i; +output sync_pad_o; +output sdata_pad_o; +input sdata_pad_i; +output ac97_reset_pad_o_; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +// Serial Output register interface +wire [15:0] out_slt0; +wire [19:0] out_slt1; +wire [19:0] out_slt2; +wire [19:0] out_slt3; +wire [19:0] out_slt4; +wire [19:0] out_slt6; +wire [19:0] out_slt7; +wire [19:0] out_slt8; +wire [19:0] out_slt9; + +// Serial Input register interface +wire [15:0] in_slt0; +wire [19:0] in_slt1; +wire [19:0] in_slt2; +wire [19:0] in_slt3; +wire [19:0] in_slt4; +wire [19:0] in_slt6; + +// Serial IO Controller Interface +wire ld; +wire valid; +wire [5:0] out_le; +wire [2:0] in_valid; +wire ps_ce; + +// Valid Sync +reg valid_s1, valid_s; +reg [2:0] in_valid_s1, in_valid_s; + +// Out FIFO interface +wire [31:0] wb_din; +wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode; +wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re; +wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status; +wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full; +wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty; + +// In FIFO interface +wire [31:0] i3_dout, i4_dout, i6_dout; +wire [1:0] i3_mode, i4_mode, i6_mode; +wire i3_we, i4_we, i6_we; +wire i3_re, i4_re, i6_re; +wire [1:0] i3_status, i4_status, i6_status; +wire i3_full, i4_full, i6_full; +wire i3_empty, i4_empty, i6_empty; + +// Register File Interface +wire [3:0] adr; +wire [31:0] rf_dout; +wire [31:0] rf_din; +wire rf_we; +wire rf_re; +wire ac97_rst_force; +wire resume_req; +wire crac_we; +wire [15:0] crac_din; +wire [31:0] crac_out; +wire [7:0] oc0_cfg; +wire [7:0] oc1_cfg; +wire [7:0] oc2_cfg; +wire [7:0] oc3_cfg; +wire [7:0] oc4_cfg; +wire [7:0] oc5_cfg; +wire [7:0] ic0_cfg; +wire [7:0] ic1_cfg; +wire [7:0] ic2_cfg; +wire [2:0] oc0_int_set; +wire [2:0] oc1_int_set; +wire [2:0] oc2_int_set; +wire [2:0] oc3_int_set; +wire [2:0] oc4_int_set; +wire [2:0] oc5_int_set; +wire [2:0] ic0_int_set; +wire [2:0] ic1_int_set; +wire [2:0] ic2_int_set; + +// CRA Module interface +wire crac_valid; +wire crac_wr; +wire crac_wr_done, crac_rd_done; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// Sync Valid to WISHBONE Clock +always @(posedge clk_i) + valid_s1 <= #1 valid; + +always @(posedge clk_i) + valid_s <= #1 valid_s1; + +always @(posedge clk_i) + in_valid_s1 <= #1 in_valid; + +always @(posedge clk_i) + in_valid_s <= #1 in_valid_s1; + +// "valid_s" Indicates when any of the outputs to the output S/R may +// change or when outputs from input S/R may be sampled +assign o3_mode = oc0_cfg[3:2]; +assign o4_mode = oc1_cfg[3:2]; +assign o6_mode = oc2_cfg[3:2]; +assign o7_mode = oc3_cfg[3:2]; +assign o8_mode = oc4_cfg[3:2]; +assign o9_mode = oc5_cfg[3:2]; +assign i3_mode = ic0_cfg[3:2]; +assign i4_mode = ic1_cfg[3:2]; +assign i6_mode = ic2_cfg[3:2]; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +ac97_sout u0( + .clk( bit_clk_pad_i ), + .rst( rst_i ), + .so_ld( ld ), + .slt0( out_slt0 ), + .slt1( out_slt1 ), + .slt2( out_slt2 ), + .slt3( out_slt3 ), + .slt4( out_slt4 ), + .slt6( out_slt6 ), + .slt7( out_slt7 ), + .slt8( out_slt8 ), + .slt9( out_slt9 ), + .sdata_out( sdata_pad_o ) + ); + +ac97_sin u1( + .clk( bit_clk_pad_i ), + .rst( rst_i ), + .out_le( out_le ), + .slt0( in_slt0 ), + .slt1( in_slt1 ), + .slt2( in_slt2 ), + .slt3( in_slt3 ), + .slt4( in_slt4 ), + .slt6( in_slt6 ), + .sdata_in( sdata_pad_i ) + ); + +ac97_soc u2( + .clk( bit_clk_pad_i ), + .wclk( clk_i ), + .rst( rst_i ), + .ps_ce( ps_ce ), + .resume( resume_req ), + .suspended( suspended_o ), + .sync( sync_pad_o ), + .out_le( out_le ), + .in_valid( in_valid ), + .ld( ld ), + .valid( valid ) + ); + +ac97_out_fifo u3( + .clk( clk_i ), + .rst( rst_i ), + .en( oc0_cfg[0] ), + .mode( o3_mode ), + .din( wb_din ), + .we( o3_we ), + .dout( out_slt3 ), + .re( o3_re ), + .status( o3_status ), + .full( o3_full ), + .empty( o3_empty ) + ); + +ac97_out_fifo u4( + .clk( clk_i ), + .rst( rst_i ), + .en( oc1_cfg[0] ), + .mode( o4_mode ), + .din( wb_din ), + .we( o4_we ), + .dout( out_slt4 ), + .re( o4_re ), + .status( o4_status ), + .full( o4_full ), + .empty( o4_empty ) + ); + +`ifdef AC97_CENTER +ac97_out_fifo u5( + .clk( clk_i ), + .rst( rst_i ), + .en( oc2_cfg[0] ), + .mode( o6_mode ), + .din( wb_din ), + .we( o6_we ), + .dout( out_slt6 ), + .re( o6_re ), + .status( o6_status ), + .full( o6_full ), + .empty( o6_empty ) + ); +`else +assign out_slt6 = 20'h0; +assign o6_status = 2'h0; +assign o6_full = 1'b0; +assign o6_empty = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_out_fifo u6( + .clk( clk_i ), + .rst( rst_i ), + .en( oc3_cfg[0] ), + .mode( o7_mode ), + .din( wb_din ), + .we( o7_we ), + .dout( out_slt7 ), + .re( o7_re ), + .status( o7_status ), + .full( o7_full ), + .empty( o7_empty ) + ); + +ac97_out_fifo u7( + .clk( clk_i ), + .rst( rst_i ), + .en( oc4_cfg[0] ), + .mode( o8_mode ), + .din( wb_din ), + .we( o8_we ), + .dout( out_slt8 ), + .re( o8_re ), + .status( o8_status ), + .full( o8_full ), + .empty( o8_empty ) + ); +`else +assign out_slt7 = 20'h0; +assign o7_status = 2'h0; +assign o7_full = 1'b0; +assign o7_empty = 1'b0; +assign out_slt8 = 20'h0; +assign o8_status = 2'h0; +assign o8_full = 1'b0; +assign o8_empty = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_out_fifo u8( + .clk( clk_i ), + .rst( rst_i ), + .en( oc5_cfg[0] ), + .mode( o9_mode ), + .din( wb_din ), + .we( o9_we ), + .dout( out_slt9 ), + .re( o9_re ), + .status( o9_status ), + .full( o9_full ), + .empty( o9_empty ) + ); +`else +assign out_slt9 = 20'h0; +assign o9_status = 2'h0; +assign o9_full = 1'b0; +assign o9_empty = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_in_fifo u9( + .clk( clk_i ), + .rst( rst_i ), + .en( ic0_cfg[0] ), + .mode( i3_mode ), + .din( in_slt3 ), + .we( i3_we ), + .dout( i3_dout ), + .re( i3_re ), + .status( i3_status ), + .full( i3_full ), + .empty( i3_empty ) + ); + +ac97_in_fifo u10( + .clk( clk_i ), + .rst( rst_i ), + .en( ic1_cfg[0] ), + .mode( i4_mode ), + .din( in_slt4 ), + .we( i4_we ), + .dout( i4_dout ), + .re( i4_re ), + .status( i4_status ), + .full( i4_full ), + .empty( i4_empty ) + ); +`else +assign i3_dout = 20'h0; +assign i3_status = 2'h0; +assign i3_full = 1'b0; +assign i3_empty = 1'b0; +assign i4_dout = 20'h0; +assign i4_status = 2'h0; +assign i4_full = 1'b0; +assign i4_empty = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_in_fifo u11( + .clk( clk_i ), + .rst( rst_i ), + .en( ic2_cfg[0] ), + .mode( i6_mode ), + .din( in_slt6 ), + .we( i6_we ), + .dout( i6_dout ), + .re( i6_re ), + .status( i6_status ), + .full( i6_full ), + .empty( i6_empty ) + ); +`else +assign i6_dout = 20'h0; +assign i6_status = 2'h0; +assign i6_full = 1'b0; +assign i6_empty = 1'b0; +`endif + +ac97_wb_if u12( + .clk( clk_i ), + .rst( rst_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( wb_data_o ), + .wb_addr_i( wb_addr_i ), + .wb_sel_i( wb_sel_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( wb_ack_o ), + .wb_err_o( wb_err_o ), + .adr( adr ), + .dout( wb_din ), + .rf_din( rf_dout ), + .i3_din( i3_dout ), + .i4_din( i4_dout ), + .i6_din( i6_dout ), + .rf_we( rf_we ), + .rf_re( rf_re ), + .o3_we( o3_we ), + .o4_we( o4_we ), + .o6_we( o6_we ), + .o7_we( o7_we ), + .o8_we( o8_we ), + .o9_we( o9_we ), + .i3_re( i3_re ), + .i4_re( i4_re ), + .i6_re( i6_re ) + ); + +ac97_rf u13( .clk( clk_i ), + .rst( rst_i ), + .adr( adr ), + .rf_dout( rf_dout ), + .rf_din( wb_din ), + .rf_we( rf_we ), + .rf_re( rf_re ), + .int( int_o ), + .ac97_rst_force(ac97_rst_force ), + .resume_req( resume_req ), + .suspended( suspended_o ), + .crac_we( crac_we ), + .crac_din( crac_din ), + .crac_out( crac_out ), + .crac_wr_done( crac_wr_done ), + .crac_rd_done( crac_rd_done ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .oc0_int_set( oc0_int_set ), + .oc1_int_set( oc1_int_set ), + .oc2_int_set( oc2_int_set ), + .oc3_int_set( oc3_int_set ), + .oc4_int_set( oc4_int_set ), + .oc5_int_set( oc5_int_set ), + .ic0_int_set( ic0_int_set ), + .ic1_int_set( ic1_int_set ), + .ic2_int_set( ic2_int_set ) + ); + +ac97_prc u14( .clk( clk_i ), + .rst( rst_i ), + .valid( valid_s ), + .in_valid( in_valid_s ), + .out_slt0( out_slt0 ), + .in_slt0( in_slt0 ), + .in_slt1( in_slt1 ), + .crac_valid( crac_valid ), + .crac_wr( crac_wr ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .o3_empty( o3_empty ), + .o4_empty( o4_empty ), + .o6_empty( o6_empty ), + .o7_empty( o7_empty ), + .o8_empty( o8_empty ), + .o9_empty( o9_empty ), + .i3_full( i3_full ), + .i4_full( i4_full ), + .i6_full( i6_full ), + .o3_re( o3_re ), + .o4_re( o4_re ), + .o6_re( o6_re ), + .o7_re( o7_re ), + .o8_re( o8_re ), + .o9_re( o9_re ), + .i3_we( i3_we ), + .i4_we( i4_we ), + .i6_we( i6_we ) + ); + +ac97_cra u15( .clk( clk_i ), + .rst( rst_i ), + .crac_we( crac_we ), + .crac_din( crac_din ), + .crac_out( crac_out ), + .crac_wr_done( crac_wr_done ), + .crac_rd_done( crac_rd_done ), + .valid( valid_s ), + .out_slt1( out_slt1 ), + .out_slt2( out_slt2 ), + .in_slt2( in_slt2 ), + .crac_valid( crac_valid ), + .crac_wr( crac_wr ) + ); + +ac97_dma_if u16(.clk( clk_i ), + .rst( rst_i ), + .o3_status( o3_status ), + .o4_status( o4_status ), + .o6_status( o6_status ), + .o7_status( o7_status ), + .o8_status( o8_status ), + .o9_status( o9_status ), + .o3_empty( o3_empty ), + .o4_empty( o4_empty ), + .o6_empty( o6_empty ), + .o7_empty( o7_empty ), + .o8_empty( o8_empty ), + .o9_empty( o9_empty ), + .i3_status( i3_status ), + .i4_status( i4_status ), + .i6_status( i6_status ), + .i3_full( i3_full ), + .i4_full( i4_full ), + .i6_full( i6_full ), + .oc0_cfg( oc0_cfg ), + .oc1_cfg( oc1_cfg ), + .oc2_cfg( oc2_cfg ), + .oc3_cfg( oc3_cfg ), + .oc4_cfg( oc4_cfg ), + .oc5_cfg( oc5_cfg ), + .ic0_cfg( ic0_cfg ), + .ic1_cfg( ic1_cfg ), + .ic2_cfg( ic2_cfg ), + .dma_req( dma_req_o ), + .dma_ack( dma_ack_i ) + ); + +ac97_int u17( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc0_int_set ), + .cfg( oc0_cfg ), + .status( o3_status ), + .full_empty( o3_empty ), + .full( o3_full ), + .empty( o3_empty ), + .re( o3_re ), + .we( o3_we ) + ); + +ac97_int u18( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc1_int_set ), + .cfg( oc1_cfg ), + .status( o4_status ), + .full_empty( o4_empty ), + .full( o4_full ), + .empty( o4_empty ), + .re( o4_re ), + .we( o4_we ) + ); + +`ifdef AC97_CENTER +ac97_int u19( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc2_int_set ), + .cfg( oc2_cfg ), + .status( o6_status ), + .full_empty( o6_empty ), + .full( o6_full ), + .empty( o6_empty ), + .re( o6_re ), + .we( o6_we ) + ); +`else +assign oc2_int_set = 1'b0; +`endif + +`ifdef AC97_SURROUND +ac97_int u20( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc3_int_set ), + .cfg( oc3_cfg ), + .status( o7_status ), + .full_empty( o7_empty ), + .full( o7_full ), + .empty( o7_empty ), + .re( o7_re ), + .we( o7_we ) + ); + +ac97_int u21( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc4_int_set ), + .cfg( oc4_cfg ), + .status( o8_status ), + .full_empty( o8_empty ), + .full( o8_full ), + .empty( o8_empty ), + .re( o8_re ), + .we( o8_we ) + ); +`else +assign oc3_int_set = 1'b0; +assign oc4_int_set = 1'b0; +`endif + +`ifdef AC97_LFE +ac97_int u22( + .clk( clk_i ), + .rst( rst_i ), + .int_set( oc5_int_set ), + .cfg( oc5_cfg ), + .status( o9_status ), + .full_empty( o9_empty ), + .full( o9_full ), + .empty( o9_empty ), + .re( o9_re ), + .we( o9_we ) + ); +`else +assign oc5_int_set = 1'b0; +`endif + +`ifdef AC97_SIN +ac97_int u23( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic0_int_set ), + .cfg( ic0_cfg ), + .status( i3_status ), + .full_empty( i3_full ), + .full( i3_full ), + .empty( i3_empty ), + .re( i3_re ), + .we( i3_we ) + ); + +ac97_int u24( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic1_int_set ), + .cfg( ic1_cfg ), + .status( i4_status ), + .full_empty( i4_full ), + .full( i4_full ), + .empty( i4_empty ), + .re( i4_re ), + .we( i4_we ) + ); +`else +assign ic0_int_set = 1'b0; +assign ic1_int_set = 1'b0; +`endif + +`ifdef AC97_MICIN +ac97_int u25( + .clk( clk_i ), + .rst( rst_i ), + .int_set( ic2_int_set ), + .cfg( ic2_cfg ), + .status( i6_status ), + .full_empty( i6_full ), + .full( i6_full ), + .empty( i6_empty ), + .re( i6_re ), + .we( i6_we ) + ); +`else +assign ic2_int_set = 1'b0; +`endif + +ac97_rst u26( + .clk( clk_i ), + .rst( rst_i ), + .rst_force( ac97_rst_force ), + .ps_ce( ps_ce ), + .ac97_rst_( ac97_reset_pad_o_ ) + ); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_wb_if.v b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_wb_if.v new file mode 100644 index 000000000..aa9ed8156 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/ac97_wb_if.v @@ -0,0 +1,204 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE AC 97 Controller //// +//// WISHBONE Interface Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: ac97_wb_if.v,v 1.4 2002/09/19 06:30:56 rudi Exp $ +// +// $Date: 2002/09/19 06:30:56 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: ac97_wb_if.v,v $ +// Revision 1.4 2002/09/19 06:30:56 rudi +// Fixed a bug reported by Igor. Apparently this bug only shows up when +// the WB clock is very low (2x bit_clk). Updated Copyright header. +// +// Revision 1.3 2002/03/05 04:44:05 rudi +// +// - Fixed the order of the thrash hold bits to match the spec. +// - Many minor synthesis cleanup items ... +// +// Revision 1.2 2001/08/10 08:09:42 rudi +// +// - Removed RTY_O output. +// - Added Clock and Reset Inputs to documentation. +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 06:54:50 rudi +// +// +// - Changed to new directory structure +// +// Revision 1.1.1.1 2001/05/19 02:29:16 rudi +// Initial Checkin +// +// +// +// + +`include "ac97_defines.v" + +module ac97_wb_if(clk, rst, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + adr, dout, rf_din, i3_din, i4_din, i6_din, + rf_we, rf_re, o3_we, o4_we, o6_we, o7_we, o8_we, o9_we, + i3_re, i4_re, i6_re + + ); + +input clk,rst; + +// WISHBONE Interface +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// Internal Interface +output [3:0] adr; +output [31:0] dout; +input [31:0] rf_din, i3_din, i4_din, i6_din; +output rf_we; +output rf_re; +output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +output i3_re, i4_re, i6_re; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [31:0] wb_data_o; +reg [31:0] dout; +reg wb_ack_o; + +reg rf_we; +reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we; +reg i3_re, i4_re, i6_re; + +reg we1, we2; +wire we; +reg re2, re1; +wire re; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +assign adr = wb_addr_i[5:2]; + +assign wb_err_o = 1'b0; + +always @(posedge clk) + dout <= #1 wb_data_i; + +always @(posedge clk) + case(wb_addr_i[6:2]) // synopsys parallel_case full_case + 5'he: wb_data_o <= #1 i3_din; + 5'hf: wb_data_o <= #1 i4_din; + 5'h10: wb_data_o <= #1 i6_din; + default: wb_data_o <= #1 rf_din; + endcase + +always @(posedge clk) + re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL; + +always @(posedge clk) + re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ; + +assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i; + +assign rf_re = re & (wb_addr_i[6:2] < 5'h8); + +always @(posedge clk) + we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL; + +always @(posedge clk) + we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i; + +assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i; + +always @(posedge clk) + wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o; + +always @(posedge clk) + rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8); + +always @(posedge clk) + o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8); + +always @(posedge clk) + o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9); + +always @(posedge clk) + o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha); + +always @(posedge clk) + o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb); + +always @(posedge clk) + o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc); + +always @(posedge clk) + o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd); + +always @(posedge clk) + i3_re <= #1 re & (wb_addr_i[6:2] == 5'he); + +always @(posedge clk) + i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf); + +always @(posedge clk) + i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_cipher_top.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_cipher_top.v new file mode 100644 index 000000000..a0acaeb48 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_cipher_top.v @@ -0,0 +1,256 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES Cipher Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_cipher_top.v,v 1.1.1.1 2002/11/09 11:22:48 rudi Exp $ +// +// $Date: 2002/11/09 11:22:48 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_cipher_top.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:48 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out ); +input clk, rst; +input ld; +output done; +input [127:0] key; +input [127:0] text_in; +output [127:0] text_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [31:0] w0, w1, w2, w3; +reg [127:0] text_in_r; +reg [127:0] text_out; +reg [7:0] sa00, sa01, sa02, sa03; +reg [7:0] sa10, sa11, sa12, sa13; +reg [7:0] sa20, sa21, sa22, sa23; +reg [7:0] sa30, sa31, sa32, sa33; +wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next; +wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next; +wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next; +wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next; +wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub; +wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub; +wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub; +wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub; +wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr; +wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr; +wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr; +wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr; +wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc; +wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc; +wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc; +wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc; +reg done, ld_r; +reg [3:0] dcnt; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + if(!rst) dcnt <= #1 4'h0; + else + if(ld) dcnt <= #1 4'hb; + else + if(|dcnt) dcnt <= #1 dcnt - 4'h1; + +always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld; +always @(posedge clk) if(ld) text_in_r <= #1 text_in; +always @(posedge clk) ld_r <= #1 ld; + +//////////////////////////////////////////////////////////////////// +// +// Initial Permutation (AddRoundKey) +// + +always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next; +always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next; +always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next; +always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next; +always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next; +always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next; +always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next; +always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next; +always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next; +always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next; +always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next; +always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next; +always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next; +always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next; +always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next; +always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next; + +//////////////////////////////////////////////////////////////////// +// +// Round Permutations +// + +assign sa00_sr = sa00_sub; +assign sa01_sr = sa01_sub; +assign sa02_sr = sa02_sub; +assign sa03_sr = sa03_sub; +assign sa10_sr = sa11_sub; +assign sa11_sr = sa12_sub; +assign sa12_sr = sa13_sub; +assign sa13_sr = sa10_sub; +assign sa20_sr = sa22_sub; +assign sa21_sr = sa23_sub; +assign sa22_sr = sa20_sub; +assign sa23_sr = sa21_sub; +assign sa30_sr = sa33_sub; +assign sa31_sr = sa30_sub; +assign sa32_sr = sa31_sub; +assign sa33_sr = sa32_sub; +assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr); +assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr); +assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr); +assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr); +assign sa00_next = sa00_mc ^ w0[31:24]; +assign sa01_next = sa01_mc ^ w1[31:24]; +assign sa02_next = sa02_mc ^ w2[31:24]; +assign sa03_next = sa03_mc ^ w3[31:24]; +assign sa10_next = sa10_mc ^ w0[23:16]; +assign sa11_next = sa11_mc ^ w1[23:16]; +assign sa12_next = sa12_mc ^ w2[23:16]; +assign sa13_next = sa13_mc ^ w3[23:16]; +assign sa20_next = sa20_mc ^ w0[15:08]; +assign sa21_next = sa21_mc ^ w1[15:08]; +assign sa22_next = sa22_mc ^ w2[15:08]; +assign sa23_next = sa23_mc ^ w3[15:08]; +assign sa30_next = sa30_mc ^ w0[07:00]; +assign sa31_next = sa31_mc ^ w1[07:00]; +assign sa32_next = sa32_mc ^ w2[07:00]; +assign sa33_next = sa33_mc ^ w3[07:00]; + +//////////////////////////////////////////////////////////////////// +// +// Final text output +// + +always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24]; +always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24]; +always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24]; +always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24]; +always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16]; +always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16]; +always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16]; +always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16]; +always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08]; +always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08]; +always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08]; +always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08]; +always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00]; +always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00]; +always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00]; +always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00]; + +//////////////////////////////////////////////////////////////////// +// +// Generic Functions +// + +function [31:0] mix_col; +input [7:0] s0,s1,s2,s3; +reg [7:0] s0_o,s1_o,s2_o,s3_o; +begin +mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3; +mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3; +mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3; +mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3); +end +endfunction + +function [7:0] xtime; +input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}}); +endfunction + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +aes_key_expand_128 u0( + .clk( clk ), + .kld( ld ), + .key( key ), + .wo_0( w0 ), + .wo_1( w1 ), + .wo_2( w2 ), + .wo_3( w3 )); + +aes_sbox us00( .a( sa00 ), .d( sa00_sub )); +aes_sbox us01( .a( sa01 ), .d( sa01_sub )); +aes_sbox us02( .a( sa02 ), .d( sa02_sub )); +aes_sbox us03( .a( sa03 ), .d( sa03_sub )); +aes_sbox us10( .a( sa10 ), .d( sa10_sub )); +aes_sbox us11( .a( sa11 ), .d( sa11_sub )); +aes_sbox us12( .a( sa12 ), .d( sa12_sub )); +aes_sbox us13( .a( sa13 ), .d( sa13_sub )); +aes_sbox us20( .a( sa20 ), .d( sa20_sub )); +aes_sbox us21( .a( sa21 ), .d( sa21_sub )); +aes_sbox us22( .a( sa22 ), .d( sa22_sub )); +aes_sbox us23( .a( sa23 ), .d( sa23_sub )); +aes_sbox us30( .a( sa30 ), .d( sa30_sub )); +aes_sbox us31( .a( sa31 ), .d( sa31_sub )); +aes_sbox us32( .a( sa32 ), .d( sa32_sub )); +aes_sbox us33( .a( sa33 ), .d( sa33_sub )); + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_cipher_top.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_cipher_top.v new file mode 100644 index 000000000..51b3525ac --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_cipher_top.v @@ -0,0 +1,327 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES Inverse Cipher Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_inv_cipher_top.v,v 1.1.1.1 2002/11/09 11:22:53 rudi Exp $ +// +// $Date: 2002/11/09 11:22:53 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_inv_cipher_top.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:53 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out ); +input clk, rst; +input kld, ld; +output done; +input [127:0] key; +input [127:0] text_in; +output [127:0] text_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [31:0] wk0, wk1, wk2, wk3; +reg [31:0] w0, w1, w2, w3; +reg [127:0] text_in_r; +reg [127:0] text_out; +reg [7:0] sa00, sa01, sa02, sa03; +reg [7:0] sa10, sa11, sa12, sa13; +reg [7:0] sa20, sa21, sa22, sa23; +reg [7:0] sa30, sa31, sa32, sa33; +wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next; +wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next; +wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next; +wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next; +wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub; +wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub; +wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub; +wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub; +wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr; +wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr; +wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr; +wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr; +wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark; +wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark; +wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark; +wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark; +reg ld_r, go, done; +reg [3:0] dcnt; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + if(!rst) dcnt <= #1 4'h0; + else + if(done) dcnt <= #1 4'h0; + else + if(ld) dcnt <= #1 4'h1; + else + if(go) dcnt <= #1 dcnt + 4'h1; + +always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld; + +always @(posedge clk) + if(!rst) go <= #1 1'b0; + else + if(ld) go <= #1 1'b1; + else + if(done) go <= #1 1'b0; + +always @(posedge clk) if(ld) text_in_r <= #1 text_in; + +always @(posedge clk) ld_r <= #1 ld; + +//////////////////////////////////////////////////////////////////// +// +// Initial Permutation +// + +always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next; +always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next; +always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next; +always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next; +always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next; +always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next; +always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next; +always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next; +always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next; +always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next; +always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next; +always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next; +always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next; +always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next; +always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next; +always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next; + +//////////////////////////////////////////////////////////////////// +// +// Round Permutations +// + +assign sa00_sr = sa00; +assign sa01_sr = sa01; +assign sa02_sr = sa02; +assign sa03_sr = sa03; +assign sa10_sr = sa13; +assign sa11_sr = sa10; +assign sa12_sr = sa11; +assign sa13_sr = sa12; +assign sa20_sr = sa22; +assign sa21_sr = sa23; +assign sa22_sr = sa20; +assign sa23_sr = sa21; +assign sa30_sr = sa31; +assign sa31_sr = sa32; +assign sa32_sr = sa33; +assign sa33_sr = sa30; +assign sa00_ark = sa00_sub ^ w0[31:24]; +assign sa01_ark = sa01_sub ^ w1[31:24]; +assign sa02_ark = sa02_sub ^ w2[31:24]; +assign sa03_ark = sa03_sub ^ w3[31:24]; +assign sa10_ark = sa10_sub ^ w0[23:16]; +assign sa11_ark = sa11_sub ^ w1[23:16]; +assign sa12_ark = sa12_sub ^ w2[23:16]; +assign sa13_ark = sa13_sub ^ w3[23:16]; +assign sa20_ark = sa20_sub ^ w0[15:08]; +assign sa21_ark = sa21_sub ^ w1[15:08]; +assign sa22_ark = sa22_sub ^ w2[15:08]; +assign sa23_ark = sa23_sub ^ w3[15:08]; +assign sa30_ark = sa30_sub ^ w0[07:00]; +assign sa31_ark = sa31_sub ^ w1[07:00]; +assign sa32_ark = sa32_sub ^ w2[07:00]; +assign sa33_ark = sa33_sub ^ w3[07:00]; +assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark); +assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark); +assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark); +assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark); + +//////////////////////////////////////////////////////////////////// +// +// Final Text Output +// + +always @(posedge clk) text_out[127:120] <= #1 sa00_ark; +always @(posedge clk) text_out[095:088] <= #1 sa01_ark; +always @(posedge clk) text_out[063:056] <= #1 sa02_ark; +always @(posedge clk) text_out[031:024] <= #1 sa03_ark; +always @(posedge clk) text_out[119:112] <= #1 sa10_ark; +always @(posedge clk) text_out[087:080] <= #1 sa11_ark; +always @(posedge clk) text_out[055:048] <= #1 sa12_ark; +always @(posedge clk) text_out[023:016] <= #1 sa13_ark; +always @(posedge clk) text_out[111:104] <= #1 sa20_ark; +always @(posedge clk) text_out[079:072] <= #1 sa21_ark; +always @(posedge clk) text_out[047:040] <= #1 sa22_ark; +always @(posedge clk) text_out[015:008] <= #1 sa23_ark; +always @(posedge clk) text_out[103:096] <= #1 sa30_ark; +always @(posedge clk) text_out[071:064] <= #1 sa31_ark; +always @(posedge clk) text_out[039:032] <= #1 sa32_ark; +always @(posedge clk) text_out[007:000] <= #1 sa33_ark; + +//////////////////////////////////////////////////////////////////// +// +// Generic Functions +// + +function [31:0] inv_mix_col; +input [7:0] s0,s1,s2,s3; +begin +inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3); +inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3); +inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3); +inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3); +end +endfunction + +// Some synthesis tools don't like xtime being called recursevly ... +function [7:0] pmul_e; +input [7:0] b; +reg [7:0] two,four,eight; +begin +two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two; +end +endfunction + +function [7:0] pmul_9; +input [7:0] b; +reg [7:0] two,four,eight; +begin +two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b; +end +endfunction + +function [7:0] pmul_d; +input [7:0] b; +reg [7:0] two,four,eight; +begin +two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b; +end +endfunction + +function [7:0] pmul_b; +input [7:0] b; +reg [7:0] two,four,eight; +begin +two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b; +end +endfunction + +function [7:0] xtime; +input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}}); +endfunction + +//////////////////////////////////////////////////////////////////// +// +// Key Buffer +// + +reg [127:0] kb[10:0]; +reg [3:0] kcnt; +reg kdone; +reg kb_ld; + +always @(posedge clk) + if(!rst) kcnt <= #1 4'ha; + else + if(kld) kcnt <= #1 4'ha; + else + if(kb_ld) kcnt <= #1 kcnt - 4'h1; + +always @(posedge clk) + if(!rst) kb_ld <= #1 1'b0; + else + if(kld) kb_ld <= #1 1'b1; + else + if(kcnt==4'h0) kb_ld <= #1 1'b0; + +always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld; +always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0}; +always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt]; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +aes_key_expand_128 u0( + .clk( clk ), + .kld( kld ), + .key( key ), + .wo_0( wk0 ), + .wo_1( wk1 ), + .wo_2( wk2 ), + .wo_3( wk3 )); + +aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub )); +aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub )); +aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub )); +aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub )); +aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub )); +aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub )); +aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub )); +aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub )); +aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub )); +aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub )); +aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub )); +aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub )); +aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub )); +aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub )); +aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub )); +aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub )); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_sbox.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_sbox.v new file mode 100644 index 000000000..323181eba --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_inv_sbox.v @@ -0,0 +1,328 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES Inverse SBOX (ROM) //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_inv_sbox.v,v 1.1.1.1 2002/11/09 11:22:55 rudi Exp $ +// +// $Date: 2002/11/09 11:22:55 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_inv_sbox.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:55 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_inv_sbox(a,d); +input [7:0] a; +output [7:0] d; +reg [7:0] d; + +always @(a) + case(a) // synopsys full_case parallel_case + 8'h00: d=8'h52; + 8'h01: d=8'h09; + 8'h02: d=8'h6a; + 8'h03: d=8'hd5; + 8'h04: d=8'h30; + 8'h05: d=8'h36; + 8'h06: d=8'ha5; + 8'h07: d=8'h38; + 8'h08: d=8'hbf; + 8'h09: d=8'h40; + 8'h0a: d=8'ha3; + 8'h0b: d=8'h9e; + 8'h0c: d=8'h81; + 8'h0d: d=8'hf3; + 8'h0e: d=8'hd7; + 8'h0f: d=8'hfb; + 8'h10: d=8'h7c; + 8'h11: d=8'he3; + 8'h12: d=8'h39; + 8'h13: d=8'h82; + 8'h14: d=8'h9b; + 8'h15: d=8'h2f; + 8'h16: d=8'hff; + 8'h17: d=8'h87; + 8'h18: d=8'h34; + 8'h19: d=8'h8e; + 8'h1a: d=8'h43; + 8'h1b: d=8'h44; + 8'h1c: d=8'hc4; + 8'h1d: d=8'hde; + 8'h1e: d=8'he9; + 8'h1f: d=8'hcb; + 8'h20: d=8'h54; + 8'h21: d=8'h7b; + 8'h22: d=8'h94; + 8'h23: d=8'h32; + 8'h24: d=8'ha6; + 8'h25: d=8'hc2; + 8'h26: d=8'h23; + 8'h27: d=8'h3d; + 8'h28: d=8'hee; + 8'h29: d=8'h4c; + 8'h2a: d=8'h95; + 8'h2b: d=8'h0b; + 8'h2c: d=8'h42; + 8'h2d: d=8'hfa; + 8'h2e: d=8'hc3; + 8'h2f: d=8'h4e; + 8'h30: d=8'h08; + 8'h31: d=8'h2e; + 8'h32: d=8'ha1; + 8'h33: d=8'h66; + 8'h34: d=8'h28; + 8'h35: d=8'hd9; + 8'h36: d=8'h24; + 8'h37: d=8'hb2; + 8'h38: d=8'h76; + 8'h39: d=8'h5b; + 8'h3a: d=8'ha2; + 8'h3b: d=8'h49; + 8'h3c: d=8'h6d; + 8'h3d: d=8'h8b; + 8'h3e: d=8'hd1; + 8'h3f: d=8'h25; + 8'h40: d=8'h72; + 8'h41: d=8'hf8; + 8'h42: d=8'hf6; + 8'h43: d=8'h64; + 8'h44: d=8'h86; + 8'h45: d=8'h68; + 8'h46: d=8'h98; + 8'h47: d=8'h16; + 8'h48: d=8'hd4; + 8'h49: d=8'ha4; + 8'h4a: d=8'h5c; + 8'h4b: d=8'hcc; + 8'h4c: d=8'h5d; + 8'h4d: d=8'h65; + 8'h4e: d=8'hb6; + 8'h4f: d=8'h92; + 8'h50: d=8'h6c; + 8'h51: d=8'h70; + 8'h52: d=8'h48; + 8'h53: d=8'h50; + 8'h54: d=8'hfd; + 8'h55: d=8'hed; + 8'h56: d=8'hb9; + 8'h57: d=8'hda; + 8'h58: d=8'h5e; + 8'h59: d=8'h15; + 8'h5a: d=8'h46; + 8'h5b: d=8'h57; + 8'h5c: d=8'ha7; + 8'h5d: d=8'h8d; + 8'h5e: d=8'h9d; + 8'h5f: d=8'h84; + 8'h60: d=8'h90; + 8'h61: d=8'hd8; + 8'h62: d=8'hab; + 8'h63: d=8'h00; + 8'h64: d=8'h8c; + 8'h65: d=8'hbc; + 8'h66: d=8'hd3; + 8'h67: d=8'h0a; + 8'h68: d=8'hf7; + 8'h69: d=8'he4; + 8'h6a: d=8'h58; + 8'h6b: d=8'h05; + 8'h6c: d=8'hb8; + 8'h6d: d=8'hb3; + 8'h6e: d=8'h45; + 8'h6f: d=8'h06; + 8'h70: d=8'hd0; + 8'h71: d=8'h2c; + 8'h72: d=8'h1e; + 8'h73: d=8'h8f; + 8'h74: d=8'hca; + 8'h75: d=8'h3f; + 8'h76: d=8'h0f; + 8'h77: d=8'h02; + 8'h78: d=8'hc1; + 8'h79: d=8'haf; + 8'h7a: d=8'hbd; + 8'h7b: d=8'h03; + 8'h7c: d=8'h01; + 8'h7d: d=8'h13; + 8'h7e: d=8'h8a; + 8'h7f: d=8'h6b; + 8'h80: d=8'h3a; + 8'h81: d=8'h91; + 8'h82: d=8'h11; + 8'h83: d=8'h41; + 8'h84: d=8'h4f; + 8'h85: d=8'h67; + 8'h86: d=8'hdc; + 8'h87: d=8'hea; + 8'h88: d=8'h97; + 8'h89: d=8'hf2; + 8'h8a: d=8'hcf; + 8'h8b: d=8'hce; + 8'h8c: d=8'hf0; + 8'h8d: d=8'hb4; + 8'h8e: d=8'he6; + 8'h8f: d=8'h73; + 8'h90: d=8'h96; + 8'h91: d=8'hac; + 8'h92: d=8'h74; + 8'h93: d=8'h22; + 8'h94: d=8'he7; + 8'h95: d=8'had; + 8'h96: d=8'h35; + 8'h97: d=8'h85; + 8'h98: d=8'he2; + 8'h99: d=8'hf9; + 8'h9a: d=8'h37; + 8'h9b: d=8'he8; + 8'h9c: d=8'h1c; + 8'h9d: d=8'h75; + 8'h9e: d=8'hdf; + 8'h9f: d=8'h6e; + 8'ha0: d=8'h47; + 8'ha1: d=8'hf1; + 8'ha2: d=8'h1a; + 8'ha3: d=8'h71; + 8'ha4: d=8'h1d; + 8'ha5: d=8'h29; + 8'ha6: d=8'hc5; + 8'ha7: d=8'h89; + 8'ha8: d=8'h6f; + 8'ha9: d=8'hb7; + 8'haa: d=8'h62; + 8'hab: d=8'h0e; + 8'hac: d=8'haa; + 8'had: d=8'h18; + 8'hae: d=8'hbe; + 8'haf: d=8'h1b; + 8'hb0: d=8'hfc; + 8'hb1: d=8'h56; + 8'hb2: d=8'h3e; + 8'hb3: d=8'h4b; + 8'hb4: d=8'hc6; + 8'hb5: d=8'hd2; + 8'hb6: d=8'h79; + 8'hb7: d=8'h20; + 8'hb8: d=8'h9a; + 8'hb9: d=8'hdb; + 8'hba: d=8'hc0; + 8'hbb: d=8'hfe; + 8'hbc: d=8'h78; + 8'hbd: d=8'hcd; + 8'hbe: d=8'h5a; + 8'hbf: d=8'hf4; + 8'hc0: d=8'h1f; + 8'hc1: d=8'hdd; + 8'hc2: d=8'ha8; + 8'hc3: d=8'h33; + 8'hc4: d=8'h88; + 8'hc5: d=8'h07; + 8'hc6: d=8'hc7; + 8'hc7: d=8'h31; + 8'hc8: d=8'hb1; + 8'hc9: d=8'h12; + 8'hca: d=8'h10; + 8'hcb: d=8'h59; + 8'hcc: d=8'h27; + 8'hcd: d=8'h80; + 8'hce: d=8'hec; + 8'hcf: d=8'h5f; + 8'hd0: d=8'h60; + 8'hd1: d=8'h51; + 8'hd2: d=8'h7f; + 8'hd3: d=8'ha9; + 8'hd4: d=8'h19; + 8'hd5: d=8'hb5; + 8'hd6: d=8'h4a; + 8'hd7: d=8'h0d; + 8'hd8: d=8'h2d; + 8'hd9: d=8'he5; + 8'hda: d=8'h7a; + 8'hdb: d=8'h9f; + 8'hdc: d=8'h93; + 8'hdd: d=8'hc9; + 8'hde: d=8'h9c; + 8'hdf: d=8'hef; + 8'he0: d=8'ha0; + 8'he1: d=8'he0; + 8'he2: d=8'h3b; + 8'he3: d=8'h4d; + 8'he4: d=8'hae; + 8'he5: d=8'h2a; + 8'he6: d=8'hf5; + 8'he7: d=8'hb0; + 8'he8: d=8'hc8; + 8'he9: d=8'heb; + 8'hea: d=8'hbb; + 8'heb: d=8'h3c; + 8'hec: d=8'h83; + 8'hed: d=8'h53; + 8'hee: d=8'h99; + 8'hef: d=8'h61; + 8'hf0: d=8'h17; + 8'hf1: d=8'h2b; + 8'hf2: d=8'h04; + 8'hf3: d=8'h7e; + 8'hf4: d=8'hba; + 8'hf5: d=8'h77; + 8'hf6: d=8'hd6; + 8'hf7: d=8'h26; + 8'hf8: d=8'he1; + 8'hf9: d=8'h69; + 8'hfa: d=8'h14; + 8'hfb: d=8'h63; + 8'hfc: d=8'h55; + 8'hfd: d=8'h21; + 8'hfe: d=8'h0c; + 8'hff: d=8'h7d; + endcase +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_key_expand_128.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_key_expand_128.v new file mode 100644 index 000000000..ddc74b732 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_key_expand_128.v @@ -0,0 +1,87 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES Key Expand Block (for 128 bit keys) //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_key_expand_128.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $ +// +// $Date: 2002/11/09 11:22:38 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_key_expand_128.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:38 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3); +input clk; +input kld; +input [127:0] key; +output [31:0] wo_0, wo_1, wo_2, wo_3; +reg [31:0] w[3:0]; +wire [31:0] tmp_w; +wire [31:0] subword; +wire [31:0] rcon; + +assign wo_0 = w[0]; +assign wo_1 = w[1]; +assign wo_2 = w[2]; +assign wo_3 = w[3]; +always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon; +always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon; +always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon; +always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon; +assign tmp_w = w[3]; +aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24])); +aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16])); +aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08])); +aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00])); +aes_rcon r0( .clk(clk), .kld(kld), .out(rcon)); +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_rcon.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_rcon.v new file mode 100644 index 000000000..c2c0a1242 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_rcon.v @@ -0,0 +1,96 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES RCON Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_rcon.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $ +// +// $Date: 2002/11/09 11:22:38 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_rcon.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:38 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_rcon(clk, kld, out); +input clk; +input kld; +output [31:0] out; +reg [31:0] out; +reg [3:0] rcnt; +wire [3:0] rcnt_next; + +always @(posedge clk) + if(kld) out <= #1 32'h01_00_00_00; + else out <= #1 frcon(rcnt_next); + +assign rcnt_next = rcnt + 4'h1; +always @(posedge clk) + if(kld) rcnt <= #1 4'h0; + else rcnt <= #1 rcnt_next; + +function [31:0] frcon; +input [3:0] i; +case(i) // synopsys parallel_case + 4'h0: frcon=32'h01_00_00_00; + 4'h1: frcon=32'h02_00_00_00; + 4'h2: frcon=32'h04_00_00_00; + 4'h3: frcon=32'h08_00_00_00; + 4'h4: frcon=32'h10_00_00_00; + 4'h5: frcon=32'h20_00_00_00; + 4'h6: frcon=32'h40_00_00_00; + 4'h7: frcon=32'h80_00_00_00; + 4'h8: frcon=32'h1b_00_00_00; + 4'h9: frcon=32'h36_00_00_00; + default: frcon=32'h00_00_00_00; +endcase +endfunction + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_sbox.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_sbox.v new file mode 100644 index 000000000..e01d75ef8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/aes_sbox.v @@ -0,0 +1,329 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// AES SBOX (ROM) //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/aes_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: aes_sbox.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $ +// +// $Date: 2002/11/09 11:22:38 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: aes_sbox.v,v $ +// Revision 1.1.1.1 2002/11/09 11:22:38 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +module aes_sbox(a,d); +input [7:0] a; +output [7:0] d; +reg [7:0] d; + +always @(a) + case(a) // synopsys full_case parallel_case + 8'h00: d=8'h63; + 8'h01: d=8'h7c; + 8'h02: d=8'h77; + 8'h03: d=8'h7b; + 8'h04: d=8'hf2; + 8'h05: d=8'h6b; + 8'h06: d=8'h6f; + 8'h07: d=8'hc5; + 8'h08: d=8'h30; + 8'h09: d=8'h01; + 8'h0a: d=8'h67; + 8'h0b: d=8'h2b; + 8'h0c: d=8'hfe; + 8'h0d: d=8'hd7; + 8'h0e: d=8'hab; + 8'h0f: d=8'h76; + 8'h10: d=8'hca; + 8'h11: d=8'h82; + 8'h12: d=8'hc9; + 8'h13: d=8'h7d; + 8'h14: d=8'hfa; + 8'h15: d=8'h59; + 8'h16: d=8'h47; + 8'h17: d=8'hf0; + 8'h18: d=8'had; + 8'h19: d=8'hd4; + 8'h1a: d=8'ha2; + 8'h1b: d=8'haf; + 8'h1c: d=8'h9c; + 8'h1d: d=8'ha4; + 8'h1e: d=8'h72; + 8'h1f: d=8'hc0; + 8'h20: d=8'hb7; + 8'h21: d=8'hfd; + 8'h22: d=8'h93; + 8'h23: d=8'h26; + 8'h24: d=8'h36; + 8'h25: d=8'h3f; + 8'h26: d=8'hf7; + 8'h27: d=8'hcc; + 8'h28: d=8'h34; + 8'h29: d=8'ha5; + 8'h2a: d=8'he5; + 8'h2b: d=8'hf1; + 8'h2c: d=8'h71; + 8'h2d: d=8'hd8; + 8'h2e: d=8'h31; + 8'h2f: d=8'h15; + 8'h30: d=8'h04; + 8'h31: d=8'hc7; + 8'h32: d=8'h23; + 8'h33: d=8'hc3; + 8'h34: d=8'h18; + 8'h35: d=8'h96; + 8'h36: d=8'h05; + 8'h37: d=8'h9a; + 8'h38: d=8'h07; + 8'h39: d=8'h12; + 8'h3a: d=8'h80; + 8'h3b: d=8'he2; + 8'h3c: d=8'heb; + 8'h3d: d=8'h27; + 8'h3e: d=8'hb2; + 8'h3f: d=8'h75; + 8'h40: d=8'h09; + 8'h41: d=8'h83; + 8'h42: d=8'h2c; + 8'h43: d=8'h1a; + 8'h44: d=8'h1b; + 8'h45: d=8'h6e; + 8'h46: d=8'h5a; + 8'h47: d=8'ha0; + 8'h48: d=8'h52; + 8'h49: d=8'h3b; + 8'h4a: d=8'hd6; + 8'h4b: d=8'hb3; + 8'h4c: d=8'h29; + 8'h4d: d=8'he3; + 8'h4e: d=8'h2f; + 8'h4f: d=8'h84; + 8'h50: d=8'h53; + 8'h51: d=8'hd1; + 8'h52: d=8'h00; + 8'h53: d=8'hed; + 8'h54: d=8'h20; + 8'h55: d=8'hfc; + 8'h56: d=8'hb1; + 8'h57: d=8'h5b; + 8'h58: d=8'h6a; + 8'h59: d=8'hcb; + 8'h5a: d=8'hbe; + 8'h5b: d=8'h39; + 8'h5c: d=8'h4a; + 8'h5d: d=8'h4c; + 8'h5e: d=8'h58; + 8'h5f: d=8'hcf; + 8'h60: d=8'hd0; + 8'h61: d=8'hef; + 8'h62: d=8'haa; + 8'h63: d=8'hfb; + 8'h64: d=8'h43; + 8'h65: d=8'h4d; + 8'h66: d=8'h33; + 8'h67: d=8'h85; + 8'h68: d=8'h45; + 8'h69: d=8'hf9; + 8'h6a: d=8'h02; + 8'h6b: d=8'h7f; + 8'h6c: d=8'h50; + 8'h6d: d=8'h3c; + 8'h6e: d=8'h9f; + 8'h6f: d=8'ha8; + 8'h70: d=8'h51; + 8'h71: d=8'ha3; + 8'h72: d=8'h40; + 8'h73: d=8'h8f; + 8'h74: d=8'h92; + 8'h75: d=8'h9d; + 8'h76: d=8'h38; + 8'h77: d=8'hf5; + 8'h78: d=8'hbc; + 8'h79: d=8'hb6; + 8'h7a: d=8'hda; + 8'h7b: d=8'h21; + 8'h7c: d=8'h10; + 8'h7d: d=8'hff; + 8'h7e: d=8'hf3; + 8'h7f: d=8'hd2; + 8'h80: d=8'hcd; + 8'h81: d=8'h0c; + 8'h82: d=8'h13; + 8'h83: d=8'hec; + 8'h84: d=8'h5f; + 8'h85: d=8'h97; + 8'h86: d=8'h44; + 8'h87: d=8'h17; + 8'h88: d=8'hc4; + 8'h89: d=8'ha7; + 8'h8a: d=8'h7e; + 8'h8b: d=8'h3d; + 8'h8c: d=8'h64; + 8'h8d: d=8'h5d; + 8'h8e: d=8'h19; + 8'h8f: d=8'h73; + 8'h90: d=8'h60; + 8'h91: d=8'h81; + 8'h92: d=8'h4f; + 8'h93: d=8'hdc; + 8'h94: d=8'h22; + 8'h95: d=8'h2a; + 8'h96: d=8'h90; + 8'h97: d=8'h88; + 8'h98: d=8'h46; + 8'h99: d=8'hee; + 8'h9a: d=8'hb8; + 8'h9b: d=8'h14; + 8'h9c: d=8'hde; + 8'h9d: d=8'h5e; + 8'h9e: d=8'h0b; + 8'h9f: d=8'hdb; + 8'ha0: d=8'he0; + 8'ha1: d=8'h32; + 8'ha2: d=8'h3a; + 8'ha3: d=8'h0a; + 8'ha4: d=8'h49; + 8'ha5: d=8'h06; + 8'ha6: d=8'h24; + 8'ha7: d=8'h5c; + 8'ha8: d=8'hc2; + 8'ha9: d=8'hd3; + 8'haa: d=8'hac; + 8'hab: d=8'h62; + 8'hac: d=8'h91; + 8'had: d=8'h95; + 8'hae: d=8'he4; + 8'haf: d=8'h79; + 8'hb0: d=8'he7; + 8'hb1: d=8'hc8; + 8'hb2: d=8'h37; + 8'hb3: d=8'h6d; + 8'hb4: d=8'h8d; + 8'hb5: d=8'hd5; + 8'hb6: d=8'h4e; + 8'hb7: d=8'ha9; + 8'hb8: d=8'h6c; + 8'hb9: d=8'h56; + 8'hba: d=8'hf4; + 8'hbb: d=8'hea; + 8'hbc: d=8'h65; + 8'hbd: d=8'h7a; + 8'hbe: d=8'hae; + 8'hbf: d=8'h08; + 8'hc0: d=8'hba; + 8'hc1: d=8'h78; + 8'hc2: d=8'h25; + 8'hc3: d=8'h2e; + 8'hc4: d=8'h1c; + 8'hc5: d=8'ha6; + 8'hc6: d=8'hb4; + 8'hc7: d=8'hc6; + 8'hc8: d=8'he8; + 8'hc9: d=8'hdd; + 8'hca: d=8'h74; + 8'hcb: d=8'h1f; + 8'hcc: d=8'h4b; + 8'hcd: d=8'hbd; + 8'hce: d=8'h8b; + 8'hcf: d=8'h8a; + 8'hd0: d=8'h70; + 8'hd1: d=8'h3e; + 8'hd2: d=8'hb5; + 8'hd3: d=8'h66; + 8'hd4: d=8'h48; + 8'hd5: d=8'h03; + 8'hd6: d=8'hf6; + 8'hd7: d=8'h0e; + 8'hd8: d=8'h61; + 8'hd9: d=8'h35; + 8'hda: d=8'h57; + 8'hdb: d=8'hb9; + 8'hdc: d=8'h86; + 8'hdd: d=8'hc1; + 8'hde: d=8'h1d; + 8'hdf: d=8'h9e; + 8'he0: d=8'he1; + 8'he1: d=8'hf8; + 8'he2: d=8'h98; + 8'he3: d=8'h11; + 8'he4: d=8'h69; + 8'he5: d=8'hd9; + 8'he6: d=8'h8e; + 8'he7: d=8'h94; + 8'he8: d=8'h9b; + 8'he9: d=8'h1e; + 8'hea: d=8'h87; + 8'heb: d=8'he9; + 8'hec: d=8'hce; + 8'hed: d=8'h55; + 8'hee: d=8'h28; + 8'hef: d=8'hdf; + 8'hf0: d=8'h8c; + 8'hf1: d=8'ha1; + 8'hf2: d=8'h89; + 8'hf3: d=8'h0d; + 8'hf4: d=8'hbf; + 8'hf5: d=8'he6; + 8'hf6: d=8'h42; + 8'hf7: d=8'h68; + 8'hf8: d=8'h41; + 8'hf9: d=8'h99; + 8'hfa: d=8'h2d; + 8'hfb: d=8'h0f; + 8'hfc: d=8'hb0; + 8'hfd: d=8'h54; + 8'hfe: d=8'hbb; + 8'hff: d=8'h16; + endcase + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/timescale.v b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/timescale.v new file mode 100644 index 000000000..ff9e265a8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps diff --git a/openfpga_flow/benchmarks/iwls2005/des/README.txt b/openfpga_flow/benchmarks/iwls2005/des/README.txt new file mode 100644 index 000000000..eedc74c9a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/README.txt @@ -0,0 +1,145 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES CORE //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + + +Triple DES Core +=============== +Attached is a Triple DES core implementation in verilog. It takes +three standard 56 bit keys and 64 bits of data as input and generates +a 64 bit encrypted/decrypted result. Two implementations are provided: + +1) Area Optimized (CBC Mode) + This is a sequential implementation and needs 48 cycles to complete + a full encryption/decryption cycle. + + +2) Performance Optimized (EBC Mode) + This is a pipelined implementation that has a 48 cycle pipeline + (plus 1 input and 1 output register). It can perform a complete + encryption/decryption every cycle. + +Performance +=========== +1) Area Optimized (CBC Mode) + 0.18u UMC ASIC process: 5.5K gates, > 160 Mhz + Spartan IIe 100-6 : 1450 LUTs (about 60%), 88MHz + +2) Performance Optimized (EBC Mode) + 0.18u UMC ASIC process: 55K Gates, 300MHz (19.2 Gbits/sec) + Virtex-II-1500-6: 79% utilization, 166Mhz (10.6 Gbits/sec) + + + +DES Core +======== +Attached is a DES core implementation in verilog. It takes a standard +56 bit key and 64 bits of data as input and generates a 64 bit +encrypted/decrypted result. Two implementations are provided: + +1) Area Optimized (CBC Mode) + This is a sequential implementation and needs 16 cycles to complete + a full encryption/decryption cycle. + + +2) Performance Optimized (EBC Mode) + This is a pipelined implementation that has a 16 cycle pipeline + (plus 1 input and 1 output register). It can perform a complete + encryption/decryption every cycle. + + +Performance +=========== +1) Area Optimized (CBC Mode) + 0.18u UMC ASIC process: >155Mhz 3K Gates + Altera APEX 20KE-1: 1106 lcells >27MHz + Altera FLEX 10K50E-1: 1283 lcells >43MHz + +2) Performance Optimized (EBC Mode) + 0.18u UMC ASIC process: >290Mhz 28K Gates + Altera APEX 20KE-1: 6688 lcells >53MHz + Altera FLEX 10K130E-1: 6485 lcells >76 Mhz + + + +Status +====== +31-Oct-2002 Added Triple DES +05-Oct-2001 Added decrypt input (Thanks to Mark Cynar for + providing the code) + Reorganized directory structure + Added Makefile + Cleaned up test benches +03-Feb-2001 Initial Release + + +Directory Structure +=================== +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +- verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output + + +About the Author +================ +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/crp.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/crp.v new file mode 100644 index 000000000..5985f2f1a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/crp.v @@ -0,0 +1,69 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// CRP //// +//// DES Crypt Module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module crp(P, R, K_sub); +output [1:32] P; +input [1:32] R; +input [1:48] K_sub; + +wire [1:48] E; +wire [1:48] X; +wire [1:32] S; + +assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5], + R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11], + R[12], R[13], R[12], R[13], R[14], R[15], R[16], + R[17], R[16], R[17], R[18], R[19], R[20], R[21], + R[20], R[21], R[22], R[23], R[24], R[25], R[24], + R[25], R[26], R[27], R[28], R[29], R[28], R[29], + R[30], R[31], R[32], R[1]}; + +assign X = E ^ K_sub; + +sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) ); +sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) ); +sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) ); +sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) ); +sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) ); +sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) ); +sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) ); +sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) ); + +assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28], + S[17], S[1], S[15], S[23], S[26], S[5], S[18], + S[31], S[10], S[2], S[8], S[24], S[14], S[32], + S[27], S[3], S[9], S[19], S[13], S[30], S[6], + S[22], S[11], S[4], S[25]}; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des.v new file mode 100644 index 000000000..d8e30e28c --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des.v @@ -0,0 +1,95 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES //// +//// DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des(desOut, desIn, key, decrypt, roundSel, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key; +input decrypt; +input [3:0] roundSel; +input clk; + +wire [1:48] K_sub; +wire [1:64] IP, FP; +reg [1:32] L, R; +wire [1:32] Xin; +wire [1:32] Lout, Rout; +wire [1:32] out; + +assign Lout = (roundSel == 0) ? IP[33:64] : R; +assign Xin = (roundSel == 0) ? IP[01:32] : L; +assign Rout = Xin ^ out; +assign FP = { Rout, Lout}; + +crp u0( .P(out), .R(Lout), .K_sub(K_sub) ); + +always @(posedge clk) + L <= #1 Lout; + +always @(posedge clk) + R <= #1 Rout; + +// Select a subkey from key. +key_sel u1( + .K_sub( K_sub ), + .K( key ), + .roundSel( roundSel ), + .decrypt( decrypt ) + ); + +// Perform initial permutation +assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46], + desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28], + desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10], + desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58], + desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40], + desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31], + desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13], + desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61], + desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43], + desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25], + desIn[33], desIn[41], desIn[49], desIn[57] }; + +// Perform final permutation +assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], + FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], + FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], + FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], + FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], + FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27], + FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], + FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] }; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des3.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des3.v new file mode 100644 index 000000000..37004a5cb --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/des3.v @@ -0,0 +1,148 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES //// +//// DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des3(desOut, desIn, key1, key2, key3, decrypt, roundSel, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key1; +input [55:0] key2; +input [55:0] key3; +input decrypt; +input [5:0] roundSel; +input clk; + +wire [1:48] K_sub; +wire [1:64] IP, FP, tmp; +reg [1:64] FP_R; +reg [1:32] L, R; +wire [1:32] Xin; +wire [1:32] Lout; +wire [1:32] Rout; +wire [1:32] out; + +//assign Lout = (roundSel == 0) ? IP[33:64] : R; +//assign Xin = (roundSel == 0) ? IP[01:32] : L; + + +assign Lout = (roundSel == 0) ? IP[33:64] : + ( (roundSel == 16) ? FP_R[33:64] : + ( (roundSel == 32) ? FP_R[33:64] : + R )); + +assign Xin = (roundSel == 0) ? IP[01:32] : + ( (roundSel == 16) ? FP_R[01:32] : + ( (roundSel == 32) ? FP_R[01:32] : + L )); + + + +/* +always @(roundSel or IP or tmp or R or FP) + case(roundSel) + 6'h0: Lout = IP[33:64]; + 6'h10: Lout = FP[33:64]; + 6'h20: Lout = FP[33:64]; + default: Lout = R; + endcase + +always @(roundSel or IP or tmp or L or FP) + case(roundSel) + 6'h0: Xin = IP[01:32]; + 6'h10: Xin = FP[01:32]; + 6'h20: Xin = FP[01:32]; + default: Xin = L; + endcase +*/ + +always @(posedge clk) + FP_R <= #1 FP; + +assign Rout = Xin ^ out; +assign FP = { Rout, Lout}; + +crp u0( .P(out), .R(Lout), .K_sub(K_sub) ); + +always @(posedge clk) + L <= #1 Lout; + +always @(posedge clk) + R <= #1 Rout; + +// Select a subkey from key. +key_sel3 u1( + .K_sub( K_sub ), + .key1( key1 ), + .key2( key2 ), + .key3( key3 ), + .roundSel( roundSel ), + .decrypt( decrypt ) + ); + +assign tmp[1:64] = { desOut[06], desOut[14], desOut[22], desOut[30], desOut[38], desOut[46], + desOut[54], desOut[62], desOut[04], desOut[12], desOut[20], desOut[28], + desOut[36], desOut[44], desOut[52], desOut[60], desOut[02], desOut[10], + desOut[18], desOut[26], desOut[34], desOut[42], desOut[50], desOut[58], + desOut[00], desOut[08], desOut[16], desOut[24], desOut[32], desOut[40], + desOut[48], desOut[56], desOut[07], desOut[15], desOut[23], desOut[31], + desOut[39], desOut[47], desOut[55], desOut[63], desOut[05], desOut[13], + desOut[21], desOut[29], desOut[37], desOut[45], desOut[53], desOut[61], + desOut[03], desOut[11], desOut[19], desOut[27], desOut[35], desOut[43], + desOut[51], desOut[59], desOut[01], desOut[09], desOut[17], desOut[25], + desOut[33], desOut[41], desOut[49], desOut[57] }; + +// Perform initial permutation +assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46], + desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28], + desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10], + desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58], + desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40], + desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31], + desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13], + desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61], + desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43], + desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25], + desIn[33], desIn[41], desIn[49], desIn[57] }; + +// Perform final permutation +assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], + FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], + FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], + FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], + FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], + FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27], + FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], + FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] }; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel.v new file mode 100644 index 000000000..8ee15e084 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel.v @@ -0,0 +1,464 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL_Half //// +//// Select one of 16 sub-keys for round //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// Original: Rudolf Usselmann //// +//// //// +//// Modified : 2004/07/10 //// +//// Modified: Sakamoto YASUHIRO //// +//// Modified: for about Half slices decreased //// +//// (XILINX SPARTAN2 Number of SLICEs 546 to 258) //// +//// Web : http://hp.vector.co.jp/authors/VA014069 //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module key_sel(K_sub, K, roundSel, decrypt); +output [1:48] K_sub; +input [55:0] K; +input [3:0] roundSel; +input decrypt; + +reg [1:48] K_sub; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8; + +//// Modified: for about Half slices decreased +wire [2:0] roundSelH; // ADD Sakamoto +wire decryptH; // ADD Sakamoto + +assign roundSelH[2:0] = roundSel[3] ? (~roundSel[2:0]) : roundSel[2:0]; +assign decryptH = decrypt ^ roundSel[3]; + +always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or roundSelH) + case (roundSelH) // synopsys full_case parallel_case + 0: K_sub = K1; + 1: K_sub = K2; + 2: K_sub = K3; + 3: K_sub = K4; + 4: K_sub = K5; + 5: K_sub = K6; + 6: K_sub = K7; + 7: K_sub = K8; + endcase + + +assign K8[1] = decryptH ? K[6] : K[24]; +assign K8[2] = decryptH ? K[27] : K[20]; +assign K8[3] = decryptH ? K[10] : K[3] ; +assign K8[4] = decryptH ? K[19] : K[12]; +assign K8[5] = decryptH ? K[54] : K[47]; +assign K8[6] = decryptH ? K[25] : K[18]; +assign K8[7] = decryptH ? K[11] : K[4] ; +assign K8[8] = decryptH ? K[47] : K[40]; +assign K8[9] = decryptH ? K[13] : K[6] ; +assign K8[10] = decryptH ? K[32] : K[25]; +assign K8[11] = decryptH ? K[55] : K[48]; +assign K8[12] = decryptH ? K[3] : K[53]; +assign K8[13] = decryptH ? K[12] : K[5] ; +assign K8[14] = decryptH ? K[41] : K[34]; +assign K8[15] = decryptH ? K[17] : K[10]; +assign K8[16] = decryptH ? K[18] : K[11]; +assign K8[17] = decryptH ? K[33] : K[26]; +assign K8[18] = decryptH ? K[46] : K[39]; +assign K8[19] = decryptH ? K[20] : K[13]; +assign K8[20] = decryptH ? K[39] : K[32]; +assign K8[21] = decryptH ? K[40] : K[33]; +assign K8[22] = decryptH ? K[48] : K[41]; +assign K8[23] = decryptH ? K[24] : K[17]; +assign K8[24] = decryptH ? K[4] : K[54]; +assign K8[25] = decryptH ? K[52] : K[45]; +assign K8[26] = decryptH ? K[15] : K[8] ; +assign K8[27] = decryptH ? K[9] : K[2] ; +assign K8[28] = decryptH ? K[51] : K[44]; +assign K8[29] = decryptH ? K[35] : K[28]; +assign K8[30] = decryptH ? K[36] : K[29]; +assign K8[31] = decryptH ? K[2] : K[50]; +assign K8[32] = decryptH ? K[45] : K[38]; +assign K8[33] = decryptH ? K[8] : K[1] ; +assign K8[34] = decryptH ? K[21] : K[14]; +assign K8[35] = decryptH ? K[23] : K[16]; +assign K8[36] = decryptH ? K[42] : K[35]; +assign K8[37] = decryptH ? K[14] : K[7] ; +assign K8[38] = decryptH ? K[49] : K[42]; +assign K8[39] = decryptH ? K[38] : K[31]; +assign K8[40] = decryptH ? K[43] : K[36]; +assign K8[41] = decryptH ? K[30] : K[23]; +assign K8[42] = decryptH ? K[22] : K[15]; +assign K8[43] = decryptH ? K[28] : K[21]; +assign K8[44] = decryptH ? K[0] : K[52]; +assign K8[45] = decryptH ? K[1] : K[49]; +assign K8[46] = decryptH ? K[44] : K[37]; +assign K8[47] = decryptH ? K[50] : K[43]; +assign K8[48] = decryptH ? K[16] : K[9] ; + +assign K7[1] = decryptH ? K[20] : K[10]; +assign K7[2] = decryptH ? K[41] : K[6] ; +assign K7[3] = decryptH ? K[24] : K[46]; +assign K7[4] = decryptH ? K[33] : K[55]; +assign K7[5] = decryptH ? K[11] : K[33]; +assign K7[6] = decryptH ? K[39] : K[4] ; +assign K7[7] = decryptH ? K[25] : K[47]; +assign K7[8] = decryptH ? K[4] : K[26]; +assign K7[9] = decryptH ? K[27] : K[17]; +assign K7[10] = decryptH ? K[46] : K[11]; +assign K7[11] = decryptH ? K[12] : K[34]; +assign K7[12] = decryptH ? K[17] : K[39]; +assign K7[13] = decryptH ? K[26] : K[48]; +assign K7[14] = decryptH ? K[55] : K[20]; +assign K7[15] = decryptH ? K[6] : K[53]; +assign K7[16] = decryptH ? K[32] : K[54]; +assign K7[17] = decryptH ? K[47] : K[12]; +assign K7[18] = decryptH ? K[3] : K[25]; +assign K7[19] = decryptH ? K[34] : K[24]; +assign K7[20] = decryptH ? K[53] : K[18]; +assign K7[21] = decryptH ? K[54] : K[19]; +assign K7[22] = decryptH ? K[5] : K[27]; +assign K7[23] = decryptH ? K[13] : K[3] ; +assign K7[24] = decryptH ? K[18] : K[40]; +assign K7[25] = decryptH ? K[7] : K[31]; +assign K7[26] = decryptH ? K[29] : K[49]; +assign K7[27] = decryptH ? K[23] : K[43]; +assign K7[28] = decryptH ? K[38] : K[30]; +assign K7[29] = decryptH ? K[49] : K[14]; +assign K7[30] = decryptH ? K[50] : K[15]; +assign K7[31] = decryptH ? K[16] : K[36]; +assign K7[32] = decryptH ? K[0] : K[51]; +assign K7[33] = decryptH ? K[22] : K[42]; +assign K7[34] = decryptH ? K[35] : K[0] ; +assign K7[35] = decryptH ? K[37] : K[2] ; +assign K7[36] = decryptH ? K[1] : K[21]; +assign K7[37] = decryptH ? K[28] : K[52]; +assign K7[38] = decryptH ? K[8] : K[28]; +assign K7[39] = decryptH ? K[52] : K[44]; +assign K7[40] = decryptH ? K[2] : K[22]; +assign K7[41] = decryptH ? K[44] : K[9] ; +assign K7[42] = decryptH ? K[36] : K[1] ; +assign K7[43] = decryptH ? K[42] : K[7] ; +assign K7[44] = decryptH ? K[14] : K[38]; +assign K7[45] = decryptH ? K[15] : K[35]; +assign K7[46] = decryptH ? K[31] : K[23]; +assign K7[47] = decryptH ? K[9] : K[29]; +assign K7[48] = decryptH ? K[30] : K[50]; + +assign K6[1] = decryptH ? K[34] : K[53]; +assign K6[2] = decryptH ? K[55] : K[17]; +assign K6[3] = decryptH ? K[13] : K[32]; +assign K6[4] = decryptH ? K[47] : K[41]; +assign K6[5] = decryptH ? K[25] : K[19]; +assign K6[6] = decryptH ? K[53] : K[47]; +assign K6[7] = decryptH ? K[39] : K[33]; +assign K6[8] = decryptH ? K[18] : K[12]; +assign K6[9] = decryptH ? K[41] : K[3] ; +assign K6[10] = decryptH ? K[3] : K[54]; +assign K6[11] = decryptH ? K[26] : K[20]; +assign K6[12] = decryptH ? K[6] : K[25]; +assign K6[13] = decryptH ? K[40] : K[34]; +assign K6[14] = decryptH ? K[12] : K[6] ; +assign K6[15] = decryptH ? K[20] : K[39]; +assign K6[16] = decryptH ? K[46] : K[40]; +assign K6[17] = decryptH ? K[4] : K[55]; +assign K6[18] = decryptH ? K[17] : K[11]; +assign K6[19] = decryptH ? K[48] : K[10]; +assign K6[20] = decryptH ? K[10] : K[4] ; +assign K6[21] = decryptH ? K[11] : K[5] ; +assign K6[22] = decryptH ? K[19] : K[13]; +assign K6[23] = decryptH ? K[27] : K[46]; +assign K6[24] = decryptH ? K[32] : K[26]; +assign K6[25] = decryptH ? K[21] : K[44]; +assign K6[26] = decryptH ? K[43] : K[35]; +assign K6[27] = decryptH ? K[37] : K[29]; +assign K6[28] = decryptH ? K[52] : K[16]; +assign K6[29] = decryptH ? K[8] : K[0] ; +assign K6[30] = decryptH ? K[9] : K[1] ; +assign K6[31] = decryptH ? K[30] : K[22]; +assign K6[32] = decryptH ? K[14] : K[37]; +assign K6[33] = decryptH ? K[36] : K[28]; +assign K6[34] = decryptH ? K[49] : K[45]; +assign K6[35] = decryptH ? K[51] : K[43]; +assign K6[36] = decryptH ? K[15] : K[7] ; +assign K6[37] = decryptH ? K[42] : K[38]; +assign K6[38] = decryptH ? K[22] : K[14]; +assign K6[39] = decryptH ? K[7] : K[30]; +assign K6[40] = decryptH ? K[16] : K[8] ; +assign K6[41] = decryptH ? K[31] : K[50]; +assign K6[42] = decryptH ? K[50] : K[42]; +assign K6[43] = decryptH ? K[1] : K[52]; +assign K6[44] = decryptH ? K[28] : K[51]; +assign K6[45] = decryptH ? K[29] : K[21]; +assign K6[46] = decryptH ? K[45] : K[9] ; +assign K6[47] = decryptH ? K[23] : K[15]; +assign K6[48] = decryptH ? K[44] : K[36]; + +assign K5[1] = decryptH ? K[48] : K[39]; +assign K5[2] = decryptH ? K[12] : K[3] ; +assign K5[3] = decryptH ? K[27] : K[18]; +assign K5[4] = decryptH ? K[4] : K[27]; +assign K5[5] = decryptH ? K[39] : K[5] ; +assign K5[6] = decryptH ? K[10] : K[33]; +assign K5[7] = decryptH ? K[53] : K[19]; +assign K5[8] = decryptH ? K[32] : K[55]; +assign K5[9] = decryptH ? K[55] : K[46]; +assign K5[10] = decryptH ? K[17] : K[40]; +assign K5[11] = decryptH ? K[40] : K[6] ; +assign K5[12] = decryptH ? K[20] : K[11]; +assign K5[13] = decryptH ? K[54] : K[20]; +assign K5[14] = decryptH ? K[26] : K[17]; +assign K5[15] = decryptH ? K[34] : K[25]; +assign K5[16] = decryptH ? K[3] : K[26]; +assign K5[17] = decryptH ? K[18] : K[41]; +assign K5[18] = decryptH ? K[6] : K[54]; +assign K5[19] = decryptH ? K[5] : K[53]; +assign K5[20] = decryptH ? K[24] : K[47]; +assign K5[21] = decryptH ? K[25] : K[48]; +assign K5[22] = decryptH ? K[33] : K[24]; +assign K5[23] = decryptH ? K[41] : K[32]; +assign K5[24] = decryptH ? K[46] : K[12]; +assign K5[25] = decryptH ? K[35] : K[30]; +assign K5[26] = decryptH ? K[2] : K[21]; +assign K5[27] = decryptH ? K[51] : K[15]; +assign K5[28] = decryptH ? K[7] : K[2] ; +assign K5[29] = decryptH ? K[22] : K[45]; +assign K5[30] = decryptH ? K[23] : K[42]; +assign K5[31] = decryptH ? K[44] : K[8] ; +assign K5[32] = decryptH ? K[28] : K[23]; +assign K5[33] = decryptH ? K[50] : K[14]; +assign K5[34] = decryptH ? K[8] : K[31]; +assign K5[35] = decryptH ? K[38] : K[29]; +assign K5[36] = decryptH ? K[29] : K[52]; +assign K5[37] = decryptH ? K[1] : K[51]; +assign K5[38] = decryptH ? K[36] : K[0] ; +assign K5[39] = decryptH ? K[21] : K[16]; +assign K5[40] = decryptH ? K[30] : K[49]; +assign K5[41] = decryptH ? K[45] : K[36]; +assign K5[42] = decryptH ? K[9] : K[28]; +assign K5[43] = decryptH ? K[15] : K[38]; +assign K5[44] = decryptH ? K[42] : K[37]; +assign K5[45] = decryptH ? K[43] : K[7] ; +assign K5[46] = decryptH ? K[0] : K[50]; +assign K5[47] = decryptH ? K[37] : K[1] ; +assign K5[48] = decryptH ? K[31] : K[22]; + +assign K4[1] = decryptH ? K[5] : K[25]; +assign K4[2] = decryptH ? K[26] : K[46]; +assign K4[3] = decryptH ? K[41] : K[4] ; +assign K4[4] = decryptH ? K[18] : K[13]; +assign K4[5] = decryptH ? K[53] : K[48]; +assign K4[6] = decryptH ? K[24] : K[19]; +assign K4[7] = decryptH ? K[10] : K[5] ; +assign K4[8] = decryptH ? K[46] : K[41]; +assign K4[9] = decryptH ? K[12] : K[32]; +assign K4[10] = decryptH ? K[6] : K[26]; +assign K4[11] = decryptH ? K[54] : K[17]; +assign K4[12] = decryptH ? K[34] : K[54]; +assign K4[13] = decryptH ? K[11] : K[6] ; +assign K4[14] = decryptH ? K[40] : K[3] ; +assign K4[15] = decryptH ? K[48] : K[11]; +assign K4[16] = decryptH ? K[17] : K[12]; +assign K4[17] = decryptH ? K[32] : K[27]; +assign K4[18] = decryptH ? K[20] : K[40]; +assign K4[19] = decryptH ? K[19] : K[39]; +assign K4[20] = decryptH ? K[13] : K[33]; +assign K4[21] = decryptH ? K[39] : K[34]; +assign K4[22] = decryptH ? K[47] : K[10]; +assign K4[23] = decryptH ? K[55] : K[18]; +assign K4[24] = decryptH ? K[3] : K[55]; +assign K4[25] = decryptH ? K[49] : K[16]; +assign K4[26] = decryptH ? K[16] : K[7] ; +assign K4[27] = decryptH ? K[38] : K[1] ; +assign K4[28] = decryptH ? K[21] : K[43]; +assign K4[29] = decryptH ? K[36] : K[31]; +assign K4[30] = decryptH ? K[37] : K[28]; +assign K4[31] = decryptH ? K[31] : K[49]; +assign K4[32] = decryptH ? K[42] : K[9] ; +assign K4[33] = decryptH ? K[9] : K[0] ; +assign K4[34] = decryptH ? K[22] : K[44]; +assign K4[35] = decryptH ? K[52] : K[15]; +assign K4[36] = decryptH ? K[43] : K[38]; +assign K4[37] = decryptH ? K[15] : K[37]; +assign K4[38] = decryptH ? K[50] : K[45]; +assign K4[39] = decryptH ? K[35] : K[2] ; +assign K4[40] = decryptH ? K[44] : K[35]; +assign K4[41] = decryptH ? K[0] : K[22]; +assign K4[42] = decryptH ? K[23] : K[14]; +assign K4[43] = decryptH ? K[29] : K[51]; +assign K4[44] = decryptH ? K[1] : K[23]; +assign K4[45] = decryptH ? K[2] : K[52]; +assign K4[46] = decryptH ? K[14] : K[36]; +assign K4[47] = decryptH ? K[51] : K[42]; +assign K4[48] = decryptH ? K[45] : K[8] ; + +assign K3[1] = decryptH ? K[19] : K[11]; +assign K3[2] = decryptH ? K[40] : K[32]; +assign K3[3] = decryptH ? K[55] : K[47]; +assign K3[4] = decryptH ? K[32] : K[24]; +assign K3[5] = decryptH ? K[10] : K[34]; +assign K3[6] = decryptH ? K[13] : K[5] ; +assign K3[7] = decryptH ? K[24] : K[48]; +assign K3[8] = decryptH ? K[3] : K[27]; +assign K3[9] = decryptH ? K[26] : K[18]; +assign K3[10] = decryptH ? K[20] : K[12]; +assign K3[11] = decryptH ? K[11] : K[3] ; +assign K3[12] = decryptH ? K[48] : K[40]; +assign K3[13] = decryptH ? K[25] : K[17]; +assign K3[14] = decryptH ? K[54] : K[46]; +assign K3[15] = decryptH ? K[5] : K[54]; +assign K3[16] = decryptH ? K[6] : K[55]; +assign K3[17] = decryptH ? K[46] : K[13]; +assign K3[18] = decryptH ? K[34] : K[26]; +assign K3[19] = decryptH ? K[33] : K[25]; +assign K3[20] = decryptH ? K[27] : K[19]; +assign K3[21] = decryptH ? K[53] : K[20]; +assign K3[22] = decryptH ? K[4] : K[53]; +assign K3[23] = decryptH ? K[12] : K[4] ; +assign K3[24] = decryptH ? K[17] : K[41]; +assign K3[25] = decryptH ? K[8] : K[2] ; +assign K3[26] = decryptH ? K[30] : K[52]; +assign K3[27] = decryptH ? K[52] : K[42]; +assign K3[28] = decryptH ? K[35] : K[29]; +assign K3[29] = decryptH ? K[50] : K[44]; +assign K3[30] = decryptH ? K[51] : K[14]; +assign K3[31] = decryptH ? K[45] : K[35]; +assign K3[32] = decryptH ? K[1] : K[50]; +assign K3[33] = decryptH ? K[23] : K[45]; +assign K3[34] = decryptH ? K[36] : K[30]; +assign K3[35] = decryptH ? K[7] : K[1] ; +assign K3[36] = decryptH ? K[2] : K[51]; +assign K3[37] = decryptH ? K[29] : K[23]; +assign K3[38] = decryptH ? K[9] : K[31]; +assign K3[39] = decryptH ? K[49] : K[43]; +assign K3[40] = decryptH ? K[31] : K[21]; +assign K3[41] = decryptH ? K[14] : K[8] ; +assign K3[42] = decryptH ? K[37] : K[0] ; +assign K3[43] = decryptH ? K[43] : K[37]; +assign K3[44] = decryptH ? K[15] : K[9] ; +assign K3[45] = decryptH ? K[16] : K[38]; +assign K3[46] = decryptH ? K[28] : K[22]; +assign K3[47] = decryptH ? K[38] : K[28]; +assign K3[48] = decryptH ? K[0] : K[49]; + +assign K2[1] = decryptH ? K[33] : K[54]; +assign K2[2] = decryptH ? K[54] : K[18]; +assign K2[3] = decryptH ? K[12] : K[33]; +assign K2[4] = decryptH ? K[46] : K[10]; +assign K2[5] = decryptH ? K[24] : K[20]; +assign K2[6] = decryptH ? K[27] : K[48]; +assign K2[7] = decryptH ? K[13] : K[34]; +assign K2[8] = decryptH ? K[17] : K[13]; +assign K2[9] = decryptH ? K[40] : K[4] ; +assign K2[10] = decryptH ? K[34] : K[55]; +assign K2[11] = decryptH ? K[25] : K[46]; +assign K2[12] = decryptH ? K[5] : K[26]; +assign K2[13] = decryptH ? K[39] : K[3] ; +assign K2[14] = decryptH ? K[11] : K[32]; +assign K2[15] = decryptH ? K[19] : K[40]; +assign K2[16] = decryptH ? K[20] : K[41]; +assign K2[17] = decryptH ? K[3] : K[24]; +assign K2[18] = decryptH ? K[48] : K[12]; +assign K2[19] = decryptH ? K[47] : K[11]; +assign K2[20] = decryptH ? K[41] : K[5] ; +assign K2[21] = decryptH ? K[10] : K[6] ; +assign K2[22] = decryptH ? K[18] : K[39]; +assign K2[23] = decryptH ? K[26] : K[47]; +assign K2[24] = decryptH ? K[6] : K[27]; +assign K2[25] = decryptH ? K[22] : K[43]; +assign K2[26] = decryptH ? K[44] : K[38]; +assign K2[27] = decryptH ? K[7] : K[28]; +assign K2[28] = decryptH ? K[49] : K[15]; +assign K2[29] = decryptH ? K[9] : K[30]; +assign K2[30] = decryptH ? K[38] : K[0] ; +assign K2[31] = decryptH ? K[0] : K[21]; +assign K2[32] = decryptH ? K[15] : K[36]; +assign K2[33] = decryptH ? K[37] : K[31]; +assign K2[34] = decryptH ? K[50] : K[16]; +assign K2[35] = decryptH ? K[21] : K[42]; +assign K2[36] = decryptH ? K[16] : K[37]; +assign K2[37] = decryptH ? K[43] : K[9] ; +assign K2[38] = decryptH ? K[23] : K[44]; +assign K2[39] = decryptH ? K[8] : K[29]; +assign K2[40] = decryptH ? K[45] : K[7] ; +assign K2[41] = decryptH ? K[28] : K[49]; +assign K2[42] = decryptH ? K[51] : K[45]; +assign K2[43] = decryptH ? K[2] : K[23]; +assign K2[44] = decryptH ? K[29] : K[50]; +assign K2[45] = decryptH ? K[30] : K[51]; +assign K2[46] = decryptH ? K[42] : K[8] ; +assign K2[47] = decryptH ? K[52] : K[14]; +assign K2[48] = decryptH ? K[14] : K[35]; + +assign K1[1] = decryptH ? K[40] : K[47]; +assign K1[2] = decryptH ? K[4] : K[11]; +assign K1[3] = decryptH ? K[19] : K[26]; +assign K1[4] = decryptH ? K[53] : K[3] ; +assign K1[5] = decryptH ? K[6] : K[13]; +assign K1[6] = decryptH ? K[34] : K[41]; +assign K1[7] = decryptH ? K[20] : K[27]; +assign K1[8] = decryptH ? K[24] : K[6] ; +assign K1[9] = decryptH ? K[47] : K[54]; +assign K1[10] = decryptH ? K[41] : K[48]; +assign K1[11] = decryptH ? K[32] : K[39]; +assign K1[12] = decryptH ? K[12] : K[19]; +assign K1[13] = decryptH ? K[46] : K[53]; +assign K1[14] = decryptH ? K[18] : K[25]; +assign K1[15] = decryptH ? K[26] : K[33]; +assign K1[16] = decryptH ? K[27] : K[34]; +assign K1[17] = decryptH ? K[10] : K[17]; +assign K1[18] = decryptH ? K[55] : K[5] ; +assign K1[19] = decryptH ? K[54] : K[4] ; +assign K1[20] = decryptH ? K[48] : K[55]; +assign K1[21] = decryptH ? K[17] : K[24]; +assign K1[22] = decryptH ? K[25] : K[32]; +assign K1[23] = decryptH ? K[33] : K[40]; +assign K1[24] = decryptH ? K[13] : K[20]; +assign K1[25] = decryptH ? K[29] : K[36]; +assign K1[26] = decryptH ? K[51] : K[31]; +assign K1[27] = decryptH ? K[14] : K[21]; +assign K1[28] = decryptH ? K[1] : K[8] ; +assign K1[29] = decryptH ? K[16] : K[23]; +assign K1[30] = decryptH ? K[45] : K[52]; +assign K1[31] = decryptH ? K[7] : K[14]; +assign K1[32] = decryptH ? K[22] : K[29]; +assign K1[33] = decryptH ? K[44] : K[51]; +assign K1[34] = decryptH ? K[2] : K[9] ; +assign K1[35] = decryptH ? K[28] : K[35]; +assign K1[36] = decryptH ? K[23] : K[30]; +assign K1[37] = decryptH ? K[50] : K[2] ; +assign K1[38] = decryptH ? K[30] : K[37]; +assign K1[39] = decryptH ? K[15] : K[22]; +assign K1[40] = decryptH ? K[52] : K[0] ; +assign K1[41] = decryptH ? K[35] : K[42]; +assign K1[42] = decryptH ? K[31] : K[38]; +assign K1[43] = decryptH ? K[9] : K[16]; +assign K1[44] = decryptH ? K[36] : K[43]; +assign K1[45] = decryptH ? K[37] : K[44]; +assign K1[46] = decryptH ? K[49] : K[1] ; +assign K1[47] = decryptH ? K[0] : K[7] ; +assign K1[48] = decryptH ? K[21] : K[28]; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel3.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel3.v new file mode 100644 index 000000000..9f232c41d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/key_sel3.v @@ -0,0 +1,865 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL //// +//// Select one of 16 sub-keys for round //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt); +output [1:48] K_sub; +input [55:0] key1, key2, key3; +input [5:0] roundSel; +input decrypt; + +wire decrypt_int; +reg [55:0] K; +reg [1:48] K_sub; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; + +always @(roundSel or decrypt or key1 or key2 or key3) + case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case + 3'b0_00: K = key1; + 3'b0_01: K = key2; + 3'b0_10: K = key3; + 3'b1_00: K = key3; + 3'b1_01: K = key2; + 3'b1_10: K = key1; + endcase + +assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt; + +always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10 + or K11 or K12 or K13 or K14 or K15 or K16 or roundSel) + case(roundSel[3:0]) // synopsys full_case parallel_case + 0: K_sub = K1; + 1: K_sub = K2; + 2: K_sub = K3; + 3: K_sub = K4; + 4: K_sub = K5; + 5: K_sub = K6; + 6: K_sub = K7; + 7: K_sub = K8; + 8: K_sub = K9; + 9: K_sub = K10; + 10: K_sub = K11; + 11: K_sub = K12; + 12: K_sub = K13; + 13: K_sub = K14; + 14: K_sub = K15; + 15: K_sub = K16; + endcase + + +assign K16[1] = decrypt_int ? K[47] : K[40]; +assign K16[2] = decrypt_int ? K[11] : K[4]; +assign K16[3] = decrypt_int ? K[26] : K[19]; +assign K16[4] = decrypt_int ? K[3] : K[53]; +assign K16[5] = decrypt_int ? K[13] : K[6]; +assign K16[6] = decrypt_int ? K[41] : K[34]; +assign K16[7] = decrypt_int ? K[27] : K[20]; +assign K16[8] = decrypt_int ? K[6] : K[24]; +assign K16[9] = decrypt_int ? K[54] : K[47]; +assign K16[10] = decrypt_int ? K[48] : K[41]; +assign K16[11] = decrypt_int ? K[39] : K[32]; +assign K16[12] = decrypt_int ? K[19] : K[12]; +assign K16[13] = decrypt_int ? K[53] : K[46]; +assign K16[14] = decrypt_int ? K[25] : K[18]; +assign K16[15] = decrypt_int ? K[33] : K[26]; +assign K16[16] = decrypt_int ? K[34] : K[27]; +assign K16[17] = decrypt_int ? K[17] : K[10]; +assign K16[18] = decrypt_int ? K[5] : K[55]; +assign K16[19] = decrypt_int ? K[4] : K[54]; +assign K16[20] = decrypt_int ? K[55] : K[48]; +assign K16[21] = decrypt_int ? K[24] : K[17]; +assign K16[22] = decrypt_int ? K[32] : K[25]; +assign K16[23] = decrypt_int ? K[40] : K[33]; +assign K16[24] = decrypt_int ? K[20] : K[13]; +assign K16[25] = decrypt_int ? K[36] : K[29]; +assign K16[26] = decrypt_int ? K[31] : K[51]; +assign K16[27] = decrypt_int ? K[21] : K[14]; +assign K16[28] = decrypt_int ? K[8] : K[1]; +assign K16[29] = decrypt_int ? K[23] : K[16]; +assign K16[30] = decrypt_int ? K[52] : K[45]; +assign K16[31] = decrypt_int ? K[14] : K[7]; +assign K16[32] = decrypt_int ? K[29] : K[22]; +assign K16[33] = decrypt_int ? K[51] : K[44]; +assign K16[34] = decrypt_int ? K[9] : K[2]; +assign K16[35] = decrypt_int ? K[35] : K[28]; +assign K16[36] = decrypt_int ? K[30] : K[23]; +assign K16[37] = decrypt_int ? K[2] : K[50]; +assign K16[38] = decrypt_int ? K[37] : K[30]; +assign K16[39] = decrypt_int ? K[22] : K[15]; +assign K16[40] = decrypt_int ? K[0] : K[52]; +assign K16[41] = decrypt_int ? K[42] : K[35]; +assign K16[42] = decrypt_int ? K[38] : K[31]; +assign K16[43] = decrypt_int ? K[16] : K[9]; +assign K16[44] = decrypt_int ? K[43] : K[36]; +assign K16[45] = decrypt_int ? K[44] : K[37]; +assign K16[46] = decrypt_int ? K[1] : K[49]; +assign K16[47] = decrypt_int ? K[7] : K[0]; +assign K16[48] = decrypt_int ? K[28] : K[21]; + +assign K15[1] = decrypt_int ? K[54] : K[33]; +assign K15[2] = decrypt_int ? K[18] : K[54]; +assign K15[3] = decrypt_int ? K[33] : K[12]; +assign K15[4] = decrypt_int ? K[10] : K[46]; +assign K15[5] = decrypt_int ? K[20] : K[24]; +assign K15[6] = decrypt_int ? K[48] : K[27]; +assign K15[7] = decrypt_int ? K[34] : K[13]; +assign K15[8] = decrypt_int ? K[13] : K[17]; +assign K15[9] = decrypt_int ? K[4] : K[40]; +assign K15[10] = decrypt_int ? K[55] : K[34]; +assign K15[11] = decrypt_int ? K[46] : K[25]; +assign K15[12] = decrypt_int ? K[26] : K[5]; +assign K15[13] = decrypt_int ? K[3] : K[39]; +assign K15[14] = decrypt_int ? K[32] : K[11]; +assign K15[15] = decrypt_int ? K[40] : K[19]; +assign K15[16] = decrypt_int ? K[41] : K[20]; +assign K15[17] = decrypt_int ? K[24] : K[3]; +assign K15[18] = decrypt_int ? K[12] : K[48]; +assign K15[19] = decrypt_int ? K[11] : K[47]; +assign K15[20] = decrypt_int ? K[5] : K[41]; +assign K15[21] = decrypt_int ? K[6] : K[10]; +assign K15[22] = decrypt_int ? K[39] : K[18]; +assign K15[23] = decrypt_int ? K[47] : K[26]; +assign K15[24] = decrypt_int ? K[27] : K[6]; +assign K15[25] = decrypt_int ? K[43] : K[22]; +assign K15[26] = decrypt_int ? K[38] : K[44]; +assign K15[27] = decrypt_int ? K[28] : K[7]; +assign K15[28] = decrypt_int ? K[15] : K[49]; +assign K15[29] = decrypt_int ? K[30] : K[9]; +assign K15[30] = decrypt_int ? K[0] : K[38]; +assign K15[31] = decrypt_int ? K[21] : K[0]; +assign K15[32] = decrypt_int ? K[36] : K[15]; +assign K15[33] = decrypt_int ? K[31] : K[37]; +assign K15[34] = decrypt_int ? K[16] : K[50]; +assign K15[35] = decrypt_int ? K[42] : K[21]; +assign K15[36] = decrypt_int ? K[37] : K[16]; +assign K15[37] = decrypt_int ? K[9] : K[43]; +assign K15[38] = decrypt_int ? K[44] : K[23]; +assign K15[39] = decrypt_int ? K[29] : K[8]; +assign K15[40] = decrypt_int ? K[7] : K[45]; +assign K15[41] = decrypt_int ? K[49] : K[28]; +assign K15[42] = decrypt_int ? K[45] : K[51]; +assign K15[43] = decrypt_int ? K[23] : K[2]; +assign K15[44] = decrypt_int ? K[50] : K[29]; +assign K15[45] = decrypt_int ? K[51] : K[30]; +assign K15[46] = decrypt_int ? K[8] : K[42]; +assign K15[47] = decrypt_int ? K[14] : K[52]; +assign K15[48] = decrypt_int ? K[35] : K[14]; + +assign K14[1] = decrypt_int ? K[11] : K[19]; +assign K14[2] = decrypt_int ? K[32] : K[40]; +assign K14[3] = decrypt_int ? K[47] : K[55]; +assign K14[4] = decrypt_int ? K[24] : K[32]; +assign K14[5] = decrypt_int ? K[34] : K[10]; +assign K14[6] = decrypt_int ? K[5] : K[13]; +assign K14[7] = decrypt_int ? K[48] : K[24]; +assign K14[8] = decrypt_int ? K[27] : K[3]; +assign K14[9] = decrypt_int ? K[18] : K[26]; +assign K14[10] = decrypt_int ? K[12] : K[20]; +assign K14[11] = decrypt_int ? K[3] : K[11]; +assign K14[12] = decrypt_int ? K[40] : K[48]; +assign K14[13] = decrypt_int ? K[17] : K[25]; +assign K14[14] = decrypt_int ? K[46] : K[54]; +assign K14[15] = decrypt_int ? K[54] : K[5]; +assign K14[16] = decrypt_int ? K[55] : K[6]; +assign K14[17] = decrypt_int ? K[13] : K[46]; +assign K14[18] = decrypt_int ? K[26] : K[34]; +assign K14[19] = decrypt_int ? K[25] : K[33]; +assign K14[20] = decrypt_int ? K[19] : K[27]; +assign K14[21] = decrypt_int ? K[20] : K[53]; +assign K14[22] = decrypt_int ? K[53] : K[4]; +assign K14[23] = decrypt_int ? K[4] : K[12]; +assign K14[24] = decrypt_int ? K[41] : K[17]; +assign K14[25] = decrypt_int ? K[2] : K[8]; +assign K14[26] = decrypt_int ? K[52] : K[30]; +assign K14[27] = decrypt_int ? K[42] : K[52]; +assign K14[28] = decrypt_int ? K[29] : K[35]; +assign K14[29] = decrypt_int ? K[44] : K[50]; +assign K14[30] = decrypt_int ? K[14] : K[51]; +assign K14[31] = decrypt_int ? K[35] : K[45]; +assign K14[32] = decrypt_int ? K[50] : K[1]; +assign K14[33] = decrypt_int ? K[45] : K[23]; +assign K14[34] = decrypt_int ? K[30] : K[36]; +assign K14[35] = decrypt_int ? K[1] : K[7]; +assign K14[36] = decrypt_int ? K[51] : K[2]; +assign K14[37] = decrypt_int ? K[23] : K[29]; +assign K14[38] = decrypt_int ? K[31] : K[9]; +assign K14[39] = decrypt_int ? K[43] : K[49]; +assign K14[40] = decrypt_int ? K[21] : K[31]; +assign K14[41] = decrypt_int ? K[8] : K[14]; +assign K14[42] = decrypt_int ? K[0] : K[37]; +assign K14[43] = decrypt_int ? K[37] : K[43]; +assign K14[44] = decrypt_int ? K[9] : K[15]; +assign K14[45] = decrypt_int ? K[38] : K[16]; +assign K14[46] = decrypt_int ? K[22] : K[28]; +assign K14[47] = decrypt_int ? K[28] : K[38]; +assign K14[48] = decrypt_int ? K[49] : K[0]; + +assign K13[1] = decrypt_int ? K[25] : K[5]; +assign K13[2] = decrypt_int ? K[46] : K[26]; +assign K13[3] = decrypt_int ? K[4] : K[41]; +assign K13[4] = decrypt_int ? K[13] : K[18]; +assign K13[5] = decrypt_int ? K[48] : K[53]; +assign K13[6] = decrypt_int ? K[19] : K[24]; +assign K13[7] = decrypt_int ? K[5] : K[10]; +assign K13[8] = decrypt_int ? K[41] : K[46]; +assign K13[9] = decrypt_int ? K[32] : K[12]; +assign K13[10] = decrypt_int ? K[26] : K[6]; +assign K13[11] = decrypt_int ? K[17] : K[54]; +assign K13[12] = decrypt_int ? K[54] : K[34]; +assign K13[13] = decrypt_int ? K[6] : K[11]; +assign K13[14] = decrypt_int ? K[3] : K[40]; +assign K13[15] = decrypt_int ? K[11] : K[48]; +assign K13[16] = decrypt_int ? K[12] : K[17]; +assign K13[17] = decrypt_int ? K[27] : K[32]; +assign K13[18] = decrypt_int ? K[40] : K[20]; +assign K13[19] = decrypt_int ? K[39] : K[19]; +assign K13[20] = decrypt_int ? K[33] : K[13]; +assign K13[21] = decrypt_int ? K[34] : K[39]; +assign K13[22] = decrypt_int ? K[10] : K[47]; +assign K13[23] = decrypt_int ? K[18] : K[55]; +assign K13[24] = decrypt_int ? K[55] : K[3]; +assign K13[25] = decrypt_int ? K[16] : K[49]; +assign K13[26] = decrypt_int ? K[7] : K[16]; +assign K13[27] = decrypt_int ? K[1] : K[38]; +assign K13[28] = decrypt_int ? K[43] : K[21]; +assign K13[29] = decrypt_int ? K[31] : K[36]; +assign K13[30] = decrypt_int ? K[28] : K[37]; +assign K13[31] = decrypt_int ? K[49] : K[31]; +assign K13[32] = decrypt_int ? K[9] : K[42]; +assign K13[33] = decrypt_int ? K[0] : K[9]; +assign K13[34] = decrypt_int ? K[44] : K[22]; +assign K13[35] = decrypt_int ? K[15] : K[52]; +assign K13[36] = decrypt_int ? K[38] : K[43]; +assign K13[37] = decrypt_int ? K[37] : K[15]; +assign K13[38] = decrypt_int ? K[45] : K[50]; +assign K13[39] = decrypt_int ? K[2] : K[35]; +assign K13[40] = decrypt_int ? K[35] : K[44]; +assign K13[41] = decrypt_int ? K[22] : K[0]; +assign K13[42] = decrypt_int ? K[14] : K[23]; +assign K13[43] = decrypt_int ? K[51] : K[29]; +assign K13[44] = decrypt_int ? K[23] : K[1]; +assign K13[45] = decrypt_int ? K[52] : K[2]; +assign K13[46] = decrypt_int ? K[36] : K[14]; +assign K13[47] = decrypt_int ? K[42] : K[51]; +assign K13[48] = decrypt_int ? K[8] : K[45]; + +assign K12[1] = decrypt_int ? K[39] : K[48]; +assign K12[2] = decrypt_int ? K[3] : K[12]; +assign K12[3] = decrypt_int ? K[18] : K[27]; +assign K12[4] = decrypt_int ? K[27] : K[4]; +assign K12[5] = decrypt_int ? K[5] : K[39]; +assign K12[6] = decrypt_int ? K[33] : K[10]; +assign K12[7] = decrypt_int ? K[19] : K[53]; +assign K12[8] = decrypt_int ? K[55] : K[32]; +assign K12[9] = decrypt_int ? K[46] : K[55]; +assign K12[10] = decrypt_int ? K[40] : K[17]; +assign K12[11] = decrypt_int ? K[6] : K[40]; +assign K12[12] = decrypt_int ? K[11] : K[20]; +assign K12[13] = decrypt_int ? K[20] : K[54]; +assign K12[14] = decrypt_int ? K[17] : K[26]; +assign K12[15] = decrypt_int ? K[25] : K[34]; +assign K12[16] = decrypt_int ? K[26] : K[3]; +assign K12[17] = decrypt_int ? K[41] : K[18]; +assign K12[18] = decrypt_int ? K[54] : K[6]; +assign K12[19] = decrypt_int ? K[53] : K[5]; +assign K12[20] = decrypt_int ? K[47] : K[24]; +assign K12[21] = decrypt_int ? K[48] : K[25]; +assign K12[22] = decrypt_int ? K[24] : K[33]; +assign K12[23] = decrypt_int ? K[32] : K[41]; +assign K12[24] = decrypt_int ? K[12] : K[46]; +assign K12[25] = decrypt_int ? K[30] : K[35]; +assign K12[26] = decrypt_int ? K[21] : K[2]; +assign K12[27] = decrypt_int ? K[15] : K[51]; +assign K12[28] = decrypt_int ? K[2] : K[7]; +assign K12[29] = decrypt_int ? K[45] : K[22]; +assign K12[30] = decrypt_int ? K[42] : K[23]; +assign K12[31] = decrypt_int ? K[8] : K[44]; +assign K12[32] = decrypt_int ? K[23] : K[28]; +assign K12[33] = decrypt_int ? K[14] : K[50]; +assign K12[34] = decrypt_int ? K[31] : K[8]; +assign K12[35] = decrypt_int ? K[29] : K[38]; +assign K12[36] = decrypt_int ? K[52] : K[29]; +assign K12[37] = decrypt_int ? K[51] : K[1]; +assign K12[38] = decrypt_int ? K[0] : K[36]; +assign K12[39] = decrypt_int ? K[16] : K[21]; +assign K12[40] = decrypt_int ? K[49] : K[30]; +assign K12[41] = decrypt_int ? K[36] : K[45]; +assign K12[42] = decrypt_int ? K[28] : K[9]; +assign K12[43] = decrypt_int ? K[38] : K[15]; +assign K12[44] = decrypt_int ? K[37] : K[42]; +assign K12[45] = decrypt_int ? K[7] : K[43]; +assign K12[46] = decrypt_int ? K[50] : K[0]; +assign K12[47] = decrypt_int ? K[1] : K[37]; +assign K12[48] = decrypt_int ? K[22] : K[31]; + +assign K11[1] = decrypt_int ? K[53] : K[34]; +assign K11[2] = decrypt_int ? K[17] : K[55]; +assign K11[3] = decrypt_int ? K[32] : K[13]; +assign K11[4] = decrypt_int ? K[41] : K[47]; +assign K11[5] = decrypt_int ? K[19] : K[25]; +assign K11[6] = decrypt_int ? K[47] : K[53]; +assign K11[7] = decrypt_int ? K[33] : K[39]; +assign K11[8] = decrypt_int ? K[12] : K[18]; +assign K11[9] = decrypt_int ? K[3] : K[41]; +assign K11[10] = decrypt_int ? K[54] : K[3]; +assign K11[11] = decrypt_int ? K[20] : K[26]; +assign K11[12] = decrypt_int ? K[25] : K[6]; +assign K11[13] = decrypt_int ? K[34] : K[40]; +assign K11[14] = decrypt_int ? K[6] : K[12]; +assign K11[15] = decrypt_int ? K[39] : K[20]; +assign K11[16] = decrypt_int ? K[40] : K[46]; +assign K11[17] = decrypt_int ? K[55] : K[4]; +assign K11[18] = decrypt_int ? K[11] : K[17]; +assign K11[19] = decrypt_int ? K[10] : K[48]; +assign K11[20] = decrypt_int ? K[4] : K[10]; +assign K11[21] = decrypt_int ? K[5] : K[11]; +assign K11[22] = decrypt_int ? K[13] : K[19]; +assign K11[23] = decrypt_int ? K[46] : K[27]; +assign K11[24] = decrypt_int ? K[26] : K[32]; +assign K11[25] = decrypt_int ? K[44] : K[21]; +assign K11[26] = decrypt_int ? K[35] : K[43]; +assign K11[27] = decrypt_int ? K[29] : K[37]; +assign K11[28] = decrypt_int ? K[16] : K[52]; +assign K11[29] = decrypt_int ? K[0] : K[8]; +assign K11[30] = decrypt_int ? K[1] : K[9]; +assign K11[31] = decrypt_int ? K[22] : K[30]; +assign K11[32] = decrypt_int ? K[37] : K[14]; +assign K11[33] = decrypt_int ? K[28] : K[36]; +assign K11[34] = decrypt_int ? K[45] : K[49]; +assign K11[35] = decrypt_int ? K[43] : K[51]; +assign K11[36] = decrypt_int ? K[7] : K[15]; +assign K11[37] = decrypt_int ? K[38] : K[42]; +assign K11[38] = decrypt_int ? K[14] : K[22]; +assign K11[39] = decrypt_int ? K[30] : K[7]; +assign K11[40] = decrypt_int ? K[8] : K[16]; +assign K11[41] = decrypt_int ? K[50] : K[31]; +assign K11[42] = decrypt_int ? K[42] : K[50]; +assign K11[43] = decrypt_int ? K[52] : K[1]; +assign K11[44] = decrypt_int ? K[51] : K[28]; +assign K11[45] = decrypt_int ? K[21] : K[29]; +assign K11[46] = decrypt_int ? K[9] : K[45]; +assign K11[47] = decrypt_int ? K[15] : K[23]; +assign K11[48] = decrypt_int ? K[36] : K[44]; + +assign K10[1] = decrypt_int ? K[10] : K[20]; +assign K10[2] = decrypt_int ? K[6] : K[41]; +assign K10[3] = decrypt_int ? K[46] : K[24]; +assign K10[4] = decrypt_int ? K[55] : K[33]; +assign K10[5] = decrypt_int ? K[33] : K[11]; +assign K10[6] = decrypt_int ? K[4] : K[39]; +assign K10[7] = decrypt_int ? K[47] : K[25]; +assign K10[8] = decrypt_int ? K[26] : K[4]; +assign K10[9] = decrypt_int ? K[17] : K[27]; +assign K10[10] = decrypt_int ? K[11] : K[46]; +assign K10[11] = decrypt_int ? K[34] : K[12]; +assign K10[12] = decrypt_int ? K[39] : K[17]; +assign K10[13] = decrypt_int ? K[48] : K[26]; +assign K10[14] = decrypt_int ? K[20] : K[55]; +assign K10[15] = decrypt_int ? K[53] : K[6]; +assign K10[16] = decrypt_int ? K[54] : K[32]; +assign K10[17] = decrypt_int ? K[12] : K[47]; +assign K10[18] = decrypt_int ? K[25] : K[3]; +assign K10[19] = decrypt_int ? K[24] : K[34]; +assign K10[20] = decrypt_int ? K[18] : K[53]; +assign K10[21] = decrypt_int ? K[19] : K[54]; +assign K10[22] = decrypt_int ? K[27] : K[5]; +assign K10[23] = decrypt_int ? K[3] : K[13]; +assign K10[24] = decrypt_int ? K[40] : K[18]; +assign K10[25] = decrypt_int ? K[31] : K[7]; +assign K10[26] = decrypt_int ? K[49] : K[29]; +assign K10[27] = decrypt_int ? K[43] : K[23]; +assign K10[28] = decrypt_int ? K[30] : K[38]; +assign K10[29] = decrypt_int ? K[14] : K[49]; +assign K10[30] = decrypt_int ? K[15] : K[50]; +assign K10[31] = decrypt_int ? K[36] : K[16]; +assign K10[32] = decrypt_int ? K[51] : K[0]; +assign K10[33] = decrypt_int ? K[42] : K[22]; +assign K10[34] = decrypt_int ? K[0] : K[35]; +assign K10[35] = decrypt_int ? K[2] : K[37]; +assign K10[36] = decrypt_int ? K[21] : K[1]; +assign K10[37] = decrypt_int ? K[52] : K[28]; +assign K10[38] = decrypt_int ? K[28] : K[8]; +assign K10[39] = decrypt_int ? K[44] : K[52]; +assign K10[40] = decrypt_int ? K[22] : K[2]; +assign K10[41] = decrypt_int ? K[9] : K[44]; +assign K10[42] = decrypt_int ? K[1] : K[36]; +assign K10[43] = decrypt_int ? K[7] : K[42]; +assign K10[44] = decrypt_int ? K[38] : K[14]; +assign K10[45] = decrypt_int ? K[35] : K[15]; +assign K10[46] = decrypt_int ? K[23] : K[31]; +assign K10[47] = decrypt_int ? K[29] : K[9]; +assign K10[48] = decrypt_int ? K[50] : K[30]; + +assign K9[1] = decrypt_int ? K[24] : K[6]; +assign K9[2] = decrypt_int ? K[20] : K[27]; +assign K9[3] = decrypt_int ? K[3] : K[10]; +assign K9[4] = decrypt_int ? K[12] : K[19]; +assign K9[5] = decrypt_int ? K[47] : K[54]; +assign K9[6] = decrypt_int ? K[18] : K[25]; +assign K9[7] = decrypt_int ? K[4] : K[11]; +assign K9[8] = decrypt_int ? K[40] : K[47]; +assign K9[9] = decrypt_int ? K[6] : K[13]; +assign K9[10] = decrypt_int ? K[25] : K[32]; +assign K9[11] = decrypt_int ? K[48] : K[55]; +assign K9[12] = decrypt_int ? K[53] : K[3]; +assign K9[13] = decrypt_int ? K[5] : K[12]; +assign K9[14] = decrypt_int ? K[34] : K[41]; +assign K9[15] = decrypt_int ? K[10] : K[17]; +assign K9[16] = decrypt_int ? K[11] : K[18]; +assign K9[17] = decrypt_int ? K[26] : K[33]; +assign K9[18] = decrypt_int ? K[39] : K[46]; +assign K9[19] = decrypt_int ? K[13] : K[20]; +assign K9[20] = decrypt_int ? K[32] : K[39]; +assign K9[21] = decrypt_int ? K[33] : K[40]; +assign K9[22] = decrypt_int ? K[41] : K[48]; +assign K9[23] = decrypt_int ? K[17] : K[24]; +assign K9[24] = decrypt_int ? K[54] : K[4]; +assign K9[25] = decrypt_int ? K[45] : K[52]; +assign K9[26] = decrypt_int ? K[8] : K[15]; +assign K9[27] = decrypt_int ? K[2] : K[9]; +assign K9[28] = decrypt_int ? K[44] : K[51]; +assign K9[29] = decrypt_int ? K[28] : K[35]; +assign K9[30] = decrypt_int ? K[29] : K[36]; +assign K9[31] = decrypt_int ? K[50] : K[2]; +assign K9[32] = decrypt_int ? K[38] : K[45]; +assign K9[33] = decrypt_int ? K[1] : K[8]; +assign K9[34] = decrypt_int ? K[14] : K[21]; +assign K9[35] = decrypt_int ? K[16] : K[23]; +assign K9[36] = decrypt_int ? K[35] : K[42]; +assign K9[37] = decrypt_int ? K[7] : K[14]; +assign K9[38] = decrypt_int ? K[42] : K[49]; +assign K9[39] = decrypt_int ? K[31] : K[38]; +assign K9[40] = decrypt_int ? K[36] : K[43]; +assign K9[41] = decrypt_int ? K[23] : K[30]; +assign K9[42] = decrypt_int ? K[15] : K[22]; +assign K9[43] = decrypt_int ? K[21] : K[28]; +assign K9[44] = decrypt_int ? K[52] : K[0]; +assign K9[45] = decrypt_int ? K[49] : K[1]; +assign K9[46] = decrypt_int ? K[37] : K[44]; +assign K9[47] = decrypt_int ? K[43] : K[50]; +assign K9[48] = decrypt_int ? K[9] : K[16]; + +assign K8[1] = decrypt_int ? K[6] : K[24]; +assign K8[2] = decrypt_int ? K[27] : K[20]; +assign K8[3] = decrypt_int ? K[10] : K[3]; +assign K8[4] = decrypt_int ? K[19] : K[12]; +assign K8[5] = decrypt_int ? K[54] : K[47]; +assign K8[6] = decrypt_int ? K[25] : K[18]; +assign K8[7] = decrypt_int ? K[11] : K[4]; +assign K8[8] = decrypt_int ? K[47] : K[40]; +assign K8[9] = decrypt_int ? K[13] : K[6]; +assign K8[10] = decrypt_int ? K[32] : K[25]; +assign K8[11] = decrypt_int ? K[55] : K[48]; +assign K8[12] = decrypt_int ? K[3] : K[53]; +assign K8[13] = decrypt_int ? K[12] : K[5]; +assign K8[14] = decrypt_int ? K[41] : K[34]; +assign K8[15] = decrypt_int ? K[17] : K[10]; +assign K8[16] = decrypt_int ? K[18] : K[11]; +assign K8[17] = decrypt_int ? K[33] : K[26]; +assign K8[18] = decrypt_int ? K[46] : K[39]; +assign K8[19] = decrypt_int ? K[20] : K[13]; +assign K8[20] = decrypt_int ? K[39] : K[32]; +assign K8[21] = decrypt_int ? K[40] : K[33]; +assign K8[22] = decrypt_int ? K[48] : K[41]; +assign K8[23] = decrypt_int ? K[24] : K[17]; +assign K8[24] = decrypt_int ? K[4] : K[54]; +assign K8[25] = decrypt_int ? K[52] : K[45]; +assign K8[26] = decrypt_int ? K[15] : K[8]; +assign K8[27] = decrypt_int ? K[9] : K[2]; +assign K8[28] = decrypt_int ? K[51] : K[44]; +assign K8[29] = decrypt_int ? K[35] : K[28]; +assign K8[30] = decrypt_int ? K[36] : K[29]; +assign K8[31] = decrypt_int ? K[2] : K[50]; +assign K8[32] = decrypt_int ? K[45] : K[38]; +assign K8[33] = decrypt_int ? K[8] : K[1]; +assign K8[34] = decrypt_int ? K[21] : K[14]; +assign K8[35] = decrypt_int ? K[23] : K[16]; +assign K8[36] = decrypt_int ? K[42] : K[35]; +assign K8[37] = decrypt_int ? K[14] : K[7]; +assign K8[38] = decrypt_int ? K[49] : K[42]; +assign K8[39] = decrypt_int ? K[38] : K[31]; +assign K8[40] = decrypt_int ? K[43] : K[36]; +assign K8[41] = decrypt_int ? K[30] : K[23]; +assign K8[42] = decrypt_int ? K[22] : K[15]; +assign K8[43] = decrypt_int ? K[28] : K[21]; +assign K8[44] = decrypt_int ? K[0] : K[52]; +assign K8[45] = decrypt_int ? K[1] : K[49]; +assign K8[46] = decrypt_int ? K[44] : K[37]; +assign K8[47] = decrypt_int ? K[50] : K[43]; +assign K8[48] = decrypt_int ? K[16] : K[9]; + +assign K7[1] = decrypt_int ? K[20] : K[10]; +assign K7[2] = decrypt_int ? K[41] : K[6]; +assign K7[3] = decrypt_int ? K[24] : K[46]; +assign K7[4] = decrypt_int ? K[33] : K[55]; +assign K7[5] = decrypt_int ? K[11] : K[33]; +assign K7[6] = decrypt_int ? K[39] : K[4]; +assign K7[7] = decrypt_int ? K[25] : K[47]; +assign K7[8] = decrypt_int ? K[4] : K[26]; +assign K7[9] = decrypt_int ? K[27] : K[17]; +assign K7[10] = decrypt_int ? K[46] : K[11]; +assign K7[11] = decrypt_int ? K[12] : K[34]; +assign K7[12] = decrypt_int ? K[17] : K[39]; +assign K7[13] = decrypt_int ? K[26] : K[48]; +assign K7[14] = decrypt_int ? K[55] : K[20]; +assign K7[15] = decrypt_int ? K[6] : K[53]; +assign K7[16] = decrypt_int ? K[32] : K[54]; +assign K7[17] = decrypt_int ? K[47] : K[12]; +assign K7[18] = decrypt_int ? K[3] : K[25]; +assign K7[19] = decrypt_int ? K[34] : K[24]; +assign K7[20] = decrypt_int ? K[53] : K[18]; +assign K7[21] = decrypt_int ? K[54] : K[19]; +assign K7[22] = decrypt_int ? K[5] : K[27]; +assign K7[23] = decrypt_int ? K[13] : K[3]; +assign K7[24] = decrypt_int ? K[18] : K[40]; +assign K7[25] = decrypt_int ? K[7] : K[31]; +assign K7[26] = decrypt_int ? K[29] : K[49]; +assign K7[27] = decrypt_int ? K[23] : K[43]; +assign K7[28] = decrypt_int ? K[38] : K[30]; +assign K7[29] = decrypt_int ? K[49] : K[14]; +assign K7[30] = decrypt_int ? K[50] : K[15]; +assign K7[31] = decrypt_int ? K[16] : K[36]; +assign K7[32] = decrypt_int ? K[0] : K[51]; +assign K7[33] = decrypt_int ? K[22] : K[42]; +assign K7[34] = decrypt_int ? K[35] : K[0]; +assign K7[35] = decrypt_int ? K[37] : K[2]; +assign K7[36] = decrypt_int ? K[1] : K[21]; +assign K7[37] = decrypt_int ? K[28] : K[52]; +assign K7[38] = decrypt_int ? K[8] : K[28]; +assign K7[39] = decrypt_int ? K[52] : K[44]; +assign K7[40] = decrypt_int ? K[2] : K[22]; +assign K7[41] = decrypt_int ? K[44] : K[9]; +assign K7[42] = decrypt_int ? K[36] : K[1]; +assign K7[43] = decrypt_int ? K[42] : K[7]; +assign K7[44] = decrypt_int ? K[14] : K[38]; +assign K7[45] = decrypt_int ? K[15] : K[35]; +assign K7[46] = decrypt_int ? K[31] : K[23]; +assign K7[47] = decrypt_int ? K[9] : K[29]; +assign K7[48] = decrypt_int ? K[30] : K[50]; + +assign K6[1] = decrypt_int ? K[34] : K[53]; +assign K6[2] = decrypt_int ? K[55] : K[17]; +assign K6[3] = decrypt_int ? K[13] : K[32]; +assign K6[4] = decrypt_int ? K[47] : K[41]; +assign K6[5] = decrypt_int ? K[25] : K[19]; +assign K6[6] = decrypt_int ? K[53] : K[47]; +assign K6[7] = decrypt_int ? K[39] : K[33]; +assign K6[8] = decrypt_int ? K[18] : K[12]; +assign K6[9] = decrypt_int ? K[41] : K[3]; +assign K6[10] = decrypt_int ? K[3] : K[54]; +assign K6[11] = decrypt_int ? K[26] : K[20]; +assign K6[12] = decrypt_int ? K[6] : K[25]; +assign K6[13] = decrypt_int ? K[40] : K[34]; +assign K6[14] = decrypt_int ? K[12] : K[6]; +assign K6[15] = decrypt_int ? K[20] : K[39]; +assign K6[16] = decrypt_int ? K[46] : K[40]; +assign K6[17] = decrypt_int ? K[4] : K[55]; +assign K6[18] = decrypt_int ? K[17] : K[11]; +assign K6[19] = decrypt_int ? K[48] : K[10]; +assign K6[20] = decrypt_int ? K[10] : K[4]; +assign K6[21] = decrypt_int ? K[11] : K[5]; +assign K6[22] = decrypt_int ? K[19] : K[13]; +assign K6[23] = decrypt_int ? K[27] : K[46]; +assign K6[24] = decrypt_int ? K[32] : K[26]; +assign K6[25] = decrypt_int ? K[21] : K[44]; +assign K6[26] = decrypt_int ? K[43] : K[35]; +assign K6[27] = decrypt_int ? K[37] : K[29]; +assign K6[28] = decrypt_int ? K[52] : K[16]; +assign K6[29] = decrypt_int ? K[8] : K[0]; +assign K6[30] = decrypt_int ? K[9] : K[1]; +assign K6[31] = decrypt_int ? K[30] : K[22]; +assign K6[32] = decrypt_int ? K[14] : K[37]; +assign K6[33] = decrypt_int ? K[36] : K[28]; +assign K6[34] = decrypt_int ? K[49] : K[45]; +assign K6[35] = decrypt_int ? K[51] : K[43]; +assign K6[36] = decrypt_int ? K[15] : K[7]; +assign K6[37] = decrypt_int ? K[42] : K[38]; +assign K6[38] = decrypt_int ? K[22] : K[14]; +assign K6[39] = decrypt_int ? K[7] : K[30]; +assign K6[40] = decrypt_int ? K[16] : K[8]; +assign K6[41] = decrypt_int ? K[31] : K[50]; +assign K6[42] = decrypt_int ? K[50] : K[42]; +assign K6[43] = decrypt_int ? K[1] : K[52]; +assign K6[44] = decrypt_int ? K[28] : K[51]; +assign K6[45] = decrypt_int ? K[29] : K[21]; +assign K6[46] = decrypt_int ? K[45] : K[9]; +assign K6[47] = decrypt_int ? K[23] : K[15]; +assign K6[48] = decrypt_int ? K[44] : K[36]; + +assign K5[1] = decrypt_int ? K[48] : K[39]; +assign K5[2] = decrypt_int ? K[12] : K[3]; +assign K5[3] = decrypt_int ? K[27] : K[18]; +assign K5[4] = decrypt_int ? K[4] : K[27]; +assign K5[5] = decrypt_int ? K[39] : K[5]; +assign K5[6] = decrypt_int ? K[10] : K[33]; +assign K5[7] = decrypt_int ? K[53] : K[19]; +assign K5[8] = decrypt_int ? K[32] : K[55]; +assign K5[9] = decrypt_int ? K[55] : K[46]; +assign K5[10] = decrypt_int ? K[17] : K[40]; +assign K5[11] = decrypt_int ? K[40] : K[6]; +assign K5[12] = decrypt_int ? K[20] : K[11]; +assign K5[13] = decrypt_int ? K[54] : K[20]; +assign K5[14] = decrypt_int ? K[26] : K[17]; +assign K5[15] = decrypt_int ? K[34] : K[25]; +assign K5[16] = decrypt_int ? K[3] : K[26]; +assign K5[17] = decrypt_int ? K[18] : K[41]; +assign K5[18] = decrypt_int ? K[6] : K[54]; +assign K5[19] = decrypt_int ? K[5] : K[53]; +assign K5[20] = decrypt_int ? K[24] : K[47]; +assign K5[21] = decrypt_int ? K[25] : K[48]; +assign K5[22] = decrypt_int ? K[33] : K[24]; +assign K5[23] = decrypt_int ? K[41] : K[32]; +assign K5[24] = decrypt_int ? K[46] : K[12]; +assign K5[25] = decrypt_int ? K[35] : K[30]; +assign K5[26] = decrypt_int ? K[2] : K[21]; +assign K5[27] = decrypt_int ? K[51] : K[15]; +assign K5[28] = decrypt_int ? K[7] : K[2]; +assign K5[29] = decrypt_int ? K[22] : K[45]; +assign K5[30] = decrypt_int ? K[23] : K[42]; +assign K5[31] = decrypt_int ? K[44] : K[8]; +assign K5[32] = decrypt_int ? K[28] : K[23]; +assign K5[33] = decrypt_int ? K[50] : K[14]; +assign K5[34] = decrypt_int ? K[8] : K[31]; +assign K5[35] = decrypt_int ? K[38] : K[29]; +assign K5[36] = decrypt_int ? K[29] : K[52]; +assign K5[37] = decrypt_int ? K[1] : K[51]; +assign K5[38] = decrypt_int ? K[36] : K[0]; +assign K5[39] = decrypt_int ? K[21] : K[16]; +assign K5[40] = decrypt_int ? K[30] : K[49]; +assign K5[41] = decrypt_int ? K[45] : K[36]; +assign K5[42] = decrypt_int ? K[9] : K[28]; +assign K5[43] = decrypt_int ? K[15] : K[38]; +assign K5[44] = decrypt_int ? K[42] : K[37]; +assign K5[45] = decrypt_int ? K[43] : K[7]; +assign K5[46] = decrypt_int ? K[0] : K[50]; +assign K5[47] = decrypt_int ? K[37] : K[1]; +assign K5[48] = decrypt_int ? K[31] : K[22]; + +assign K4[1] = decrypt_int ? K[5] : K[25]; +assign K4[2] = decrypt_int ? K[26] : K[46]; +assign K4[3] = decrypt_int ? K[41] : K[4]; +assign K4[4] = decrypt_int ? K[18] : K[13]; +assign K4[5] = decrypt_int ? K[53] : K[48]; +assign K4[6] = decrypt_int ? K[24] : K[19]; +assign K4[7] = decrypt_int ? K[10] : K[5]; +assign K4[8] = decrypt_int ? K[46] : K[41]; +assign K4[9] = decrypt_int ? K[12] : K[32]; +assign K4[10] = decrypt_int ? K[6] : K[26]; +assign K4[11] = decrypt_int ? K[54] : K[17]; +assign K4[12] = decrypt_int ? K[34] : K[54]; +assign K4[13] = decrypt_int ? K[11] : K[6]; +assign K4[14] = decrypt_int ? K[40] : K[3]; +assign K4[15] = decrypt_int ? K[48] : K[11]; +assign K4[16] = decrypt_int ? K[17] : K[12]; +assign K4[17] = decrypt_int ? K[32] : K[27]; +assign K4[18] = decrypt_int ? K[20] : K[40]; +assign K4[19] = decrypt_int ? K[19] : K[39]; +assign K4[20] = decrypt_int ? K[13] : K[33]; +assign K4[21] = decrypt_int ? K[39] : K[34]; +assign K4[22] = decrypt_int ? K[47] : K[10]; +assign K4[23] = decrypt_int ? K[55] : K[18]; +assign K4[24] = decrypt_int ? K[3] : K[55]; +assign K4[25] = decrypt_int ? K[49] : K[16]; +assign K4[26] = decrypt_int ? K[16] : K[7]; +assign K4[27] = decrypt_int ? K[38] : K[1]; +assign K4[28] = decrypt_int ? K[21] : K[43]; +assign K4[29] = decrypt_int ? K[36] : K[31]; +assign K4[30] = decrypt_int ? K[37] : K[28]; +assign K4[31] = decrypt_int ? K[31] : K[49]; +assign K4[32] = decrypt_int ? K[42] : K[9]; +assign K4[33] = decrypt_int ? K[9] : K[0]; +assign K4[34] = decrypt_int ? K[22] : K[44]; +assign K4[35] = decrypt_int ? K[52] : K[15]; +assign K4[36] = decrypt_int ? K[43] : K[38]; +assign K4[37] = decrypt_int ? K[15] : K[37]; +assign K4[38] = decrypt_int ? K[50] : K[45]; +assign K4[39] = decrypt_int ? K[35] : K[2]; +assign K4[40] = decrypt_int ? K[44] : K[35]; +assign K4[41] = decrypt_int ? K[0] : K[22]; +assign K4[42] = decrypt_int ? K[23] : K[14]; +assign K4[43] = decrypt_int ? K[29] : K[51]; +assign K4[44] = decrypt_int ? K[1] : K[23]; +assign K4[45] = decrypt_int ? K[2] : K[52]; +assign K4[46] = decrypt_int ? K[14] : K[36]; +assign K4[47] = decrypt_int ? K[51] : K[42]; +assign K4[48] = decrypt_int ? K[45] : K[8]; + +assign K3[1] = decrypt_int ? K[19] : K[11]; +assign K3[2] = decrypt_int ? K[40] : K[32]; +assign K3[3] = decrypt_int ? K[55] : K[47]; +assign K3[4] = decrypt_int ? K[32] : K[24]; +assign K3[5] = decrypt_int ? K[10] : K[34]; +assign K3[6] = decrypt_int ? K[13] : K[5]; +assign K3[7] = decrypt_int ? K[24] : K[48]; +assign K3[8] = decrypt_int ? K[3] : K[27]; +assign K3[9] = decrypt_int ? K[26] : K[18]; +assign K3[10] = decrypt_int ? K[20] : K[12]; +assign K3[11] = decrypt_int ? K[11] : K[3]; +assign K3[12] = decrypt_int ? K[48] : K[40]; +assign K3[13] = decrypt_int ? K[25] : K[17]; +assign K3[14] = decrypt_int ? K[54] : K[46]; +assign K3[15] = decrypt_int ? K[5] : K[54]; +assign K3[16] = decrypt_int ? K[6] : K[55]; +assign K3[17] = decrypt_int ? K[46] : K[13]; +assign K3[18] = decrypt_int ? K[34] : K[26]; +assign K3[19] = decrypt_int ? K[33] : K[25]; +assign K3[20] = decrypt_int ? K[27] : K[19]; +assign K3[21] = decrypt_int ? K[53] : K[20]; +assign K3[22] = decrypt_int ? K[4] : K[53]; +assign K3[23] = decrypt_int ? K[12] : K[4]; +assign K3[24] = decrypt_int ? K[17] : K[41]; +assign K3[25] = decrypt_int ? K[8] : K[2]; +assign K3[26] = decrypt_int ? K[30] : K[52]; +assign K3[27] = decrypt_int ? K[52] : K[42]; +assign K3[28] = decrypt_int ? K[35] : K[29]; +assign K3[29] = decrypt_int ? K[50] : K[44]; +assign K3[30] = decrypt_int ? K[51] : K[14]; +assign K3[31] = decrypt_int ? K[45] : K[35]; +assign K3[32] = decrypt_int ? K[1] : K[50]; +assign K3[33] = decrypt_int ? K[23] : K[45]; +assign K3[34] = decrypt_int ? K[36] : K[30]; +assign K3[35] = decrypt_int ? K[7] : K[1]; +assign K3[36] = decrypt_int ? K[2] : K[51]; +assign K3[37] = decrypt_int ? K[29] : K[23]; +assign K3[38] = decrypt_int ? K[9] : K[31]; +assign K3[39] = decrypt_int ? K[49] : K[43]; +assign K3[40] = decrypt_int ? K[31] : K[21]; +assign K3[41] = decrypt_int ? K[14] : K[8]; +assign K3[42] = decrypt_int ? K[37] : K[0]; +assign K3[43] = decrypt_int ? K[43] : K[37]; +assign K3[44] = decrypt_int ? K[15] : K[9]; +assign K3[45] = decrypt_int ? K[16] : K[38]; +assign K3[46] = decrypt_int ? K[28] : K[22]; +assign K3[47] = decrypt_int ? K[38] : K[28]; +assign K3[48] = decrypt_int ? K[0] : K[49]; + +assign K2[1] = decrypt_int ? K[33] : K[54]; +assign K2[2] = decrypt_int ? K[54] : K[18]; +assign K2[3] = decrypt_int ? K[12] : K[33]; +assign K2[4] = decrypt_int ? K[46] : K[10]; +assign K2[5] = decrypt_int ? K[24] : K[20]; +assign K2[6] = decrypt_int ? K[27] : K[48]; +assign K2[7] = decrypt_int ? K[13] : K[34]; +assign K2[8] = decrypt_int ? K[17] : K[13]; +assign K2[9] = decrypt_int ? K[40] : K[4]; +assign K2[10] = decrypt_int ? K[34] : K[55]; +assign K2[11] = decrypt_int ? K[25] : K[46]; +assign K2[12] = decrypt_int ? K[5] : K[26]; +assign K2[13] = decrypt_int ? K[39] : K[3]; +assign K2[14] = decrypt_int ? K[11] : K[32]; +assign K2[15] = decrypt_int ? K[19] : K[40]; +assign K2[16] = decrypt_int ? K[20] : K[41]; +assign K2[17] = decrypt_int ? K[3] : K[24]; +assign K2[18] = decrypt_int ? K[48] : K[12]; +assign K2[19] = decrypt_int ? K[47] : K[11]; +assign K2[20] = decrypt_int ? K[41] : K[5]; +assign K2[21] = decrypt_int ? K[10] : K[6]; +assign K2[22] = decrypt_int ? K[18] : K[39]; +assign K2[23] = decrypt_int ? K[26] : K[47]; +assign K2[24] = decrypt_int ? K[6] : K[27]; +assign K2[25] = decrypt_int ? K[22] : K[43]; +assign K2[26] = decrypt_int ? K[44] : K[38]; +assign K2[27] = decrypt_int ? K[7] : K[28]; +assign K2[28] = decrypt_int ? K[49] : K[15]; +assign K2[29] = decrypt_int ? K[9] : K[30]; +assign K2[30] = decrypt_int ? K[38] : K[0]; +assign K2[31] = decrypt_int ? K[0] : K[21]; +assign K2[32] = decrypt_int ? K[15] : K[36]; +assign K2[33] = decrypt_int ? K[37] : K[31]; +assign K2[34] = decrypt_int ? K[50] : K[16]; +assign K2[35] = decrypt_int ? K[21] : K[42]; +assign K2[36] = decrypt_int ? K[16] : K[37]; +assign K2[37] = decrypt_int ? K[43] : K[9]; +assign K2[38] = decrypt_int ? K[23] : K[44]; +assign K2[39] = decrypt_int ? K[8] : K[29]; +assign K2[40] = decrypt_int ? K[45] : K[7]; +assign K2[41] = decrypt_int ? K[28] : K[49]; +assign K2[42] = decrypt_int ? K[51] : K[45]; +assign K2[43] = decrypt_int ? K[2] : K[23]; +assign K2[44] = decrypt_int ? K[29] : K[50]; +assign K2[45] = decrypt_int ? K[30] : K[51]; +assign K2[46] = decrypt_int ? K[42] : K[8]; +assign K2[47] = decrypt_int ? K[52] : K[14]; +assign K2[48] = decrypt_int ? K[14] : K[35]; + +assign K1[1] = decrypt_int ? K[40] : K[47]; +assign K1[2] = decrypt_int ? K[4] : K[11]; +assign K1[3] = decrypt_int ? K[19] : K[26]; +assign K1[4] = decrypt_int ? K[53] : K[3]; +assign K1[5] = decrypt_int ? K[6] : K[13]; +assign K1[6] = decrypt_int ? K[34] : K[41]; +assign K1[7] = decrypt_int ? K[20] : K[27]; +assign K1[8] = decrypt_int ? K[24] : K[6]; +assign K1[9] = decrypt_int ? K[47] : K[54]; +assign K1[10] = decrypt_int ? K[41] : K[48]; +assign K1[11] = decrypt_int ? K[32] : K[39]; +assign K1[12] = decrypt_int ? K[12] : K[19]; +assign K1[13] = decrypt_int ? K[46] : K[53]; +assign K1[14] = decrypt_int ? K[18] : K[25]; +assign K1[15] = decrypt_int ? K[26] : K[33]; +assign K1[16] = decrypt_int ? K[27] : K[34]; +assign K1[17] = decrypt_int ? K[10] : K[17]; +assign K1[18] = decrypt_int ? K[55] : K[5]; +assign K1[19] = decrypt_int ? K[54] : K[4]; +assign K1[20] = decrypt_int ? K[48] : K[55]; +assign K1[21] = decrypt_int ? K[17] : K[24]; +assign K1[22] = decrypt_int ? K[25] : K[32]; +assign K1[23] = decrypt_int ? K[33] : K[40]; +assign K1[24] = decrypt_int ? K[13] : K[20]; +assign K1[25] = decrypt_int ? K[29] : K[36]; +assign K1[26] = decrypt_int ? K[51] : K[31]; +assign K1[27] = decrypt_int ? K[14] : K[21]; +assign K1[28] = decrypt_int ? K[1] : K[8]; +assign K1[29] = decrypt_int ? K[16] : K[23]; +assign K1[30] = decrypt_int ? K[45] : K[52]; +assign K1[31] = decrypt_int ? K[7] : K[14]; +assign K1[32] = decrypt_int ? K[22] : K[29]; +assign K1[33] = decrypt_int ? K[44] : K[51]; +assign K1[34] = decrypt_int ? K[2] : K[9]; +assign K1[35] = decrypt_int ? K[28] : K[35]; +assign K1[36] = decrypt_int ? K[23] : K[30]; +assign K1[37] = decrypt_int ? K[50] : K[2]; +assign K1[38] = decrypt_int ? K[30] : K[37]; +assign K1[39] = decrypt_int ? K[15] : K[22]; +assign K1[40] = decrypt_int ? K[52] : K[0]; +assign K1[41] = decrypt_int ? K[35] : K[42]; +assign K1[42] = decrypt_int ? K[31] : K[38]; +assign K1[43] = decrypt_int ? K[9] : K[16]; +assign K1[44] = decrypt_int ? K[36] : K[43]; +assign K1[45] = decrypt_int ? K[37] : K[44]; +assign K1[46] = decrypt_int ? K[49] : K[1]; +assign K1[47] = decrypt_int ? K[0] : K[7]; +assign K1[48] = decrypt_int ? K[21] : K[28]; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox1.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox1.v new file mode 100644 index 000000000..76d5e22f6 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox1.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox1(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 14; + 1: dout = 4; + 2: dout = 13; + 3: dout = 1; + 4: dout = 2; + 5: dout = 15; + 6: dout = 11; + 7: dout = 8; + 8: dout = 3; + 9: dout = 10; + 10: dout = 6; + 11: dout = 12; + 12: dout = 5; + 13: dout = 9; + 14: dout = 0; + 15: dout = 7; + + 16: dout = 0; + 17: dout = 15; + 18: dout = 7; + 19: dout = 4; + 20: dout = 14; + 21: dout = 2; + 22: dout = 13; + 23: dout = 1; + 24: dout = 10; + 25: dout = 6; + 26: dout = 12; + 27: dout = 11; + 28: dout = 9; + 29: dout = 5; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 4; + 33: dout = 1; + 34: dout = 14; + 35: dout = 8; + 36: dout = 13; + 37: dout = 6; + 38: dout = 2; + 39: dout = 11; + 40: dout = 15; + 41: dout = 12; + 42: dout = 9; + 43: dout = 7; + 44: dout = 3; + 45: dout = 10; + 46: dout = 5; + 47: dout = 0; + + 48: dout = 15; + 49: dout = 12; + 50: dout = 8; + 51: dout = 2; + 52: dout = 4; + 53: dout = 9; + 54: dout = 1; + 55: dout = 7; + 56: dout = 5; + 57: dout = 11; + 58: dout = 3; + 59: dout = 14; + 60: dout = 10; + 61: dout = 0; + 62: dout = 6; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox2.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox2.v new file mode 100644 index 000000000..aa505f3a2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox2.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox2(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 15; + 1: dout = 1; + 2: dout = 8; + 3: dout = 14; + 4: dout = 6; + 5: dout = 11; + 6: dout = 3; + 7: dout = 4; + 8: dout = 9; + 9: dout = 7; + 10: dout = 2; + 11: dout = 13; + 12: dout = 12; + 13: dout = 0; + 14: dout = 5; + 15: dout = 10; + + 16: dout = 3; + 17: dout = 13; + 18: dout = 4; + 19: dout = 7; + 20: dout = 15; + 21: dout = 2; + 22: dout = 8; + 23: dout = 14; + 24: dout = 12; + 25: dout = 0; + 26: dout = 1; + 27: dout = 10; + 28: dout = 6; + 29: dout = 9; + 30: dout = 11; + 31: dout = 5; + + 32: dout = 0; + 33: dout = 14; + 34: dout = 7; + 35: dout = 11; + 36: dout = 10; + 37: dout = 4; + 38: dout = 13; + 39: dout = 1; + 40: dout = 5; + 41: dout = 8; + 42: dout = 12; + 43: dout = 6; + 44: dout = 9; + 45: dout = 3; + 46: dout = 2; + 47: dout = 15; + + 48: dout = 13; + 49: dout = 8; + 50: dout = 10; + 51: dout = 1; + 52: dout = 3; + 53: dout = 15; + 54: dout = 4; + 55: dout = 2; + 56: dout = 11; + 57: dout = 6; + 58: dout = 7; + 59: dout = 12; + 60: dout = 0; + 61: dout = 5; + 62: dout = 14; + 63: dout = 9; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox3.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox3.v new file mode 100644 index 000000000..0c6cddf03 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox3.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox3(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 10; + 1: dout = 0; + 2: dout = 9; + 3: dout = 14; + 4: dout = 6; + 5: dout = 3; + 6: dout = 15; + 7: dout = 5; + 8: dout = 1; + 9: dout = 13; + 10: dout = 12; + 11: dout = 7; + 12: dout = 11; + 13: dout = 4; + 14: dout = 2; + 15: dout = 8; + + 16: dout = 13; + 17: dout = 7; + 18: dout = 0; + 19: dout = 9; + 20: dout = 3; + 21: dout = 4; + 22: dout = 6; + 23: dout = 10; + 24: dout = 2; + 25: dout = 8; + 26: dout = 5; + 27: dout = 14; + 28: dout = 12; + 29: dout = 11; + 30: dout = 15; + 31: dout = 1; + + 32: dout = 13; + 33: dout = 6; + 34: dout = 4; + 35: dout = 9; + 36: dout = 8; + 37: dout = 15; + 38: dout = 3; + 39: dout = 0; + 40: dout = 11; + 41: dout = 1; + 42: dout = 2; + 43: dout = 12; + 44: dout = 5; + 45: dout = 10; + 46: dout = 14; + 47: dout = 7; + + 48: dout = 1; + 49: dout = 10; + 50: dout = 13; + 51: dout = 0; + 52: dout = 6; + 53: dout = 9; + 54: dout = 8; + 55: dout = 7; + 56: dout = 4; + 57: dout = 15; + 58: dout = 14; + 59: dout = 3; + 60: dout = 11; + 61: dout = 5; + 62: dout = 2; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox4.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox4.v new file mode 100644 index 000000000..ec531c1e8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox4.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox4(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 7; + 1: dout = 13; + 2: dout = 14; + 3: dout = 3; + 4: dout = 0; + 5: dout = 6; + 6: dout = 9; + 7: dout = 10; + 8: dout = 1; + 9: dout = 2; + 10: dout = 8; + 11: dout = 5; + 12: dout = 11; + 13: dout = 12; + 14: dout = 4; + 15: dout = 15; + + 16: dout = 13; + 17: dout = 8; + 18: dout = 11; + 19: dout = 5; + 20: dout = 6; + 21: dout = 15; + 22: dout = 0; + 23: dout = 3; + 24: dout = 4; + 25: dout = 7; + 26: dout = 2; + 27: dout = 12; + 28: dout = 1; + 29: dout = 10; + 30: dout = 14; + 31: dout = 9; + + 32: dout = 10; + 33: dout = 6; + 34: dout = 9; + 35: dout = 0; + 36: dout = 12; + 37: dout = 11; + 38: dout = 7; + 39: dout = 13; + 40: dout = 15; + 41: dout = 1; + 42: dout = 3; + 43: dout = 14; + 44: dout = 5; + 45: dout = 2; + 46: dout = 8; + 47: dout = 4; + + 48: dout = 3; + 49: dout = 15; + 50: dout = 0; + 51: dout = 6; + 52: dout = 10; + 53: dout = 1; + 54: dout = 13; + 55: dout = 8; + 56: dout = 9; + 57: dout = 4; + 58: dout = 5; + 59: dout = 11; + 60: dout = 12; + 61: dout = 7; + 62: dout = 2; + 63: dout = 14; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox5.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox5.v new file mode 100644 index 000000000..f874c25cc --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox5.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox5(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 2; + 1: dout = 12; + 2: dout = 4; + 3: dout = 1; + 4: dout = 7; + 5: dout = 10; + 6: dout = 11; + 7: dout = 6; + 8: dout = 8; + 9: dout = 5; + 10: dout = 3; + 11: dout = 15; + 12: dout = 13; + 13: dout = 0; + 14: dout = 14; + 15: dout = 9; + + 16: dout = 14; + 17: dout = 11; + 18: dout = 2; + 19: dout = 12; + 20: dout = 4; + 21: dout = 7; + 22: dout = 13; + 23: dout = 1; + 24: dout = 5; + 25: dout = 0; + 26: dout = 15; + 27: dout = 10; + 28: dout = 3; + 29: dout = 9; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 4; + 33: dout = 2; + 34: dout = 1; + 35: dout = 11; + 36: dout = 10; + 37: dout = 13; + 38: dout = 7; + 39: dout = 8; + 40: dout = 15; + 41: dout = 9; + 42: dout = 12; + 43: dout = 5; + 44: dout = 6; + 45: dout = 3; + 46: dout = 0; + 47: dout = 14; + + 48: dout = 11; + 49: dout = 8; + 50: dout = 12; + 51: dout = 7; + 52: dout = 1; + 53: dout = 14; + 54: dout = 2; + 55: dout = 13; + 56: dout = 6; + 57: dout = 15; + 58: dout = 0; + 59: dout = 9; + 60: dout = 10; + 61: dout = 4; + 62: dout = 5; + 63: dout = 3; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox6.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox6.v new file mode 100644 index 000000000..58fc86af0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox6.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox6(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 12; + 1: dout = 1; + 2: dout = 10; + 3: dout = 15; + 4: dout = 9; + 5: dout = 2; + 6: dout = 6; + 7: dout = 8; + 8: dout = 0; + 9: dout = 13; + 10: dout = 3; + 11: dout = 4; + 12: dout = 14; + 13: dout = 7; + 14: dout = 5; + 15: dout = 11; + + 16: dout = 10; + 17: dout = 15; + 18: dout = 4; + 19: dout = 2; + 20: dout = 7; + 21: dout = 12; + 22: dout = 9; + 23: dout = 5; + 24: dout = 6; + 25: dout = 1; + 26: dout = 13; + 27: dout = 14; + 28: dout = 0; + 29: dout = 11; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 9; + 33: dout = 14; + 34: dout = 15; + 35: dout = 5; + 36: dout = 2; + 37: dout = 8; + 38: dout = 12; + 39: dout = 3; + 40: dout = 7; + 41: dout = 0; + 42: dout = 4; + 43: dout = 10; + 44: dout = 1; + 45: dout = 13; + 46: dout = 11; + 47: dout = 6; + + 48: dout = 4; + 49: dout = 3; + 50: dout = 2; + 51: dout = 12; + 52: dout = 9; + 53: dout = 5; + 54: dout = 15; + 55: dout = 10; + 56: dout = 11; + 57: dout = 14; + 58: dout = 1; + 59: dout = 7; + 60: dout = 6; + 61: dout = 0; + 62: dout = 8; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox7.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox7.v new file mode 100644 index 000000000..f27957e2f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox7.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox7(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 4; + 1: dout = 11; + 2: dout = 2; + 3: dout = 14; + 4: dout = 15; + 5: dout = 0; + 6: dout = 8; + 7: dout = 13; + 8: dout = 3; + 9: dout = 12; + 10: dout = 9; + 11: dout = 7; + 12: dout = 5; + 13: dout = 10; + 14: dout = 6; + 15: dout = 1; + + 16: dout = 13; + 17: dout = 0; + 18: dout = 11; + 19: dout = 7; + 20: dout = 4; + 21: dout = 9; + 22: dout = 1; + 23: dout = 10; + 24: dout = 14; + 25: dout = 3; + 26: dout = 5; + 27: dout = 12; + 28: dout = 2; + 29: dout = 15; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 1; + 33: dout = 4; + 34: dout = 11; + 35: dout = 13; + 36: dout = 12; + 37: dout = 3; + 38: dout = 7; + 39: dout = 14; + 40: dout = 10; + 41: dout = 15; + 42: dout = 6; + 43: dout = 8; + 44: dout = 0; + 45: dout = 5; + 46: dout = 9; + 47: dout = 2; + + 48: dout = 6; + 49: dout = 11; + 50: dout = 13; + 51: dout = 8; + 52: dout = 1; + 53: dout = 4; + 54: dout = 10; + 55: dout = 7; + 56: dout = 9; + 57: dout = 5; + 58: dout = 0; + 59: dout = 15; + 60: dout = 14; + 61: dout = 2; + 62: dout = 3; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox8.v b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox8.v new file mode 100644 index 000000000..5ebad6388 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/sbox8.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox8(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 13; + 1: dout = 2; + 2: dout = 8; + 3: dout = 4; + 4: dout = 6; + 5: dout = 15; + 6: dout = 11; + 7: dout = 1; + 8: dout = 10; + 9: dout = 9; + 10: dout = 3; + 11: dout = 14; + 12: dout = 5; + 13: dout = 0; + 14: dout = 12; + 15: dout = 7; + + 16: dout = 1; + 17: dout = 15; + 18: dout = 13; + 19: dout = 8; + 20: dout = 10; + 21: dout = 3; + 22: dout = 7; + 23: dout = 4; + 24: dout = 12; + 25: dout = 5; + 26: dout = 6; + 27: dout = 11; + 28: dout = 0; + 29: dout = 14; + 30: dout = 9; + 31: dout = 2; + + 32: dout = 7; + 33: dout = 11; + 34: dout = 4; + 35: dout = 1; + 36: dout = 9; + 37: dout = 12; + 38: dout = 14; + 39: dout = 2; + 40: dout = 0; + 41: dout = 6; + 42: dout = 10; + 43: dout = 13; + 44: dout = 15; + 45: dout = 3; + 46: dout = 5; + 47: dout = 8; + + 48: dout = 2; + 49: dout = 1; + 50: dout = 14; + 51: dout = 7; + 52: dout = 4; + 53: dout = 10; + 54: dout = 8; + 55: dout = 13; + 56: dout = 15; + 57: dout = 12; + 58: dout = 9; + 59: dout = 0; + 60: dout = 3; + 61: dout = 5; + 62: dout = 6; + 63: dout = 11; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/crp.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/crp.v new file mode 100644 index 000000000..5985f2f1a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/crp.v @@ -0,0 +1,69 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// CRP //// +//// DES Crypt Module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module crp(P, R, K_sub); +output [1:32] P; +input [1:32] R; +input [1:48] K_sub; + +wire [1:48] E; +wire [1:48] X; +wire [1:32] S; + +assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5], + R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11], + R[12], R[13], R[12], R[13], R[14], R[15], R[16], + R[17], R[16], R[17], R[18], R[19], R[20], R[21], + R[20], R[21], R[22], R[23], R[24], R[25], R[24], + R[25], R[26], R[27], R[28], R[29], R[28], R[29], + R[30], R[31], R[32], R[1]}; + +assign X = E ^ K_sub; + +sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) ); +sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) ); +sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) ); +sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) ); +sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) ); +sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) ); +sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) ); +sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) ); + +assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28], + S[17], S[1], S[15], S[23], S[26], S[5], S[18], + S[31], S[10], S[2], S[8], S[24], S[14], S[32], + S[27], S[3], S[9], S[19], S[13], S[30], S[6], + S[22], S[11], S[4], S[25]}; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des.v new file mode 100644 index 000000000..151f83863 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des.v @@ -0,0 +1,236 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DES //// +//// DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des(desOut, desIn, key, decrypt, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key; +input decrypt; +input clk; + +wire [1:64] IP, FP; +reg [63:0] desIn_r; +reg [55:0] key_r; +reg [63:0] desOut; +reg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15; +reg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15; +wire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; + +// Register the 56 bit key +always @(posedge clk) + key_r <= #1 key; + +// Register the 64 bit input +always @(posedge clk) + desIn_r <= #1 desIn; + +// XOR 32 bit out15 with 32 bit L14 ( FP 1:32 ) +// then concatinate the 32 bit R14 value ( FP 33:64 ) +// This value ( FP 1:64 ) is then registered by the desOut[63:0] register +assign FP = { (out15 ^ L14), R14}; + +// Key schedule provides a linear means of intermixing the 56 bit key to form a +// different 48 bit key for each of the 16 bit rounds +key_sel uk( + .clk( clk ), + .K( key_r ), + .decrypt( decrypt ), + .K1( K1 ), + .K2( K2 ), + .K3( K3 ), + .K4( K4 ), + .K5( K5 ), + .K6( K6 ), + .K7( K7 ), + .K8( K8 ), + .K9( K9 ), + .K10( K10 ), + .K11( K11 ), + .K12( K12 ), + .K13( K13 ), + .K14( K14 ), + .K15( K15 ), + .K16( K16 ) + ); + +// 16 CRP blocks +crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) ); +crp u1( .P(out1), .R(R0), .K_sub(K2) ); +crp u2( .P(out2), .R(R1), .K_sub(K3) ); +crp u3( .P(out3), .R(R2), .K_sub(K4) ); +crp u4( .P(out4), .R(R3), .K_sub(K5) ); +crp u5( .P(out5), .R(R4), .K_sub(K6) ); +crp u6( .P(out6), .R(R5), .K_sub(K7) ); +crp u7( .P(out7), .R(R6), .K_sub(K8) ); +crp u8( .P(out8), .R(R7), .K_sub(K9) ); +crp u9( .P(out9), .R(R8), .K_sub(K10) ); +crp u10( .P(out10), .R(R9), .K_sub(K11) ); +crp u11( .P(out11), .R(R10), .K_sub(K12) ); +crp u12( .P(out12), .R(R11), .K_sub(K13) ); +crp u13( .P(out13), .R(R12), .K_sub(K14) ); +crp u14( .P(out14), .R(R13), .K_sub(K15) ); +crp u15( .P(out15), .R(R14), .K_sub(K16) ); + +// 32 bit L0 get upper 32 bits of IP +always @(posedge clk) + L0 <= #1 IP[33:64]; + +// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0 +always @(posedge clk) + R0 <= #1 IP[01:32] ^ out0; + +// 32 bit L1 gets 32 bit R0 +always @(posedge clk) + L1 <= #1 R0; + +// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1 +always @(posedge clk) + R1 <= #1 L0 ^ out1; + +// 32 bit L2 gets 32 bit R1 +always @(posedge clk) + L2 <= #1 R1; + +// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2 +always @(posedge clk) + R2 <= #1 L1 ^ out2; + +always @(posedge clk) + L3 <= #1 R2; + +always @(posedge clk) + R3 <= #1 L2 ^ out3; + +always @(posedge clk) + L4 <= #1 R3; + +always @(posedge clk) + R4 <= #1 L3 ^ out4; + +always @(posedge clk) + L5 <= #1 R4; + +always @(posedge clk) + R5 <= #1 L4 ^ out5; + +always @(posedge clk) + L6 <= #1 R5; + +always @(posedge clk) + R6 <= #1 L5 ^ out6; + +always @(posedge clk) + L7 <= #1 R6; + +always @(posedge clk) + R7 <= #1 L6 ^ out7; + +always @(posedge clk) + L8 <= #1 R7; + +always @(posedge clk) + R8 <= #1 L7 ^ out8; + +always @(posedge clk) + L9 <= #1 R8; + +always @(posedge clk) + R9 <= #1 L8 ^ out9; + +always @(posedge clk) + L10 <= #1 R9; + +always @(posedge clk) + R10 <= #1 L9 ^ out10; + +always @(posedge clk) + L11 <= #1 R10; + +always @(posedge clk) + R11 <= #1 L10 ^ out11; + +always @(posedge clk) + L12 <= #1 R11; + +always @(posedge clk) + R12 <= #1 L11 ^ out12; + +always @(posedge clk) + L13 <= #1 R12; + +always @(posedge clk) + R13 <= #1 L12 ^ out13; + +always @(posedge clk) + L14 <= #1 R13; + +always @(posedge clk) + R14 <= #1 L13 ^ out14; + +// 32 bit L15 gets 32 bit R14 +always @(posedge clk) + L15 <= #1 R14; + +// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15 +always @(posedge clk) + R15 <= #1 L14 ^ out15; + +// Perform the initial permutationi with the registerd desIn +assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46], + desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28], + desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10], + desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58], + desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40], + desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31], + desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13], + desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61], + desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43], + desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25], + desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] }; + +// Perform the final permutation +always @(posedge clk) + desOut <= #1 { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], + FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], + FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], + FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], + FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], + FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27], + FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], + FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] }; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v new file mode 100644 index 000000000..d9a4e7f4f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/des3.v @@ -0,0 +1,79 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Tripple DES //// +//// Tripple DES Top Level module //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module des3(desOut, desIn, key1, key2, key3, decrypt, clk); +output [63:0] desOut; +input [63:0] desIn; +input [55:0] key1; +input [55:0] key2; +input [55:0] key3; +input decrypt; +input clk; + +wire [55:0] key_a; +wire [55:0] key_b; +wire [55:0] key_c; +wire [63:0] stage1_out, stage2_out; +reg [55:0] key_b_r [16:0]; +reg [55:0] key_c_r [33:0]; +integer i; + +assign key_a = decrypt ? key3 : key1; +assign key_b = key2; +assign key_c = decrypt ? key1 : key3; + +always @(posedge clk) + key_b_r[0] <= #1 key_b; + +always @(posedge clk) + for(i=0;i<16;i=i+1) + key_b_r[i+1] <= #1 key_b_r[i]; + + +always @(posedge clk) + key_c_r[0] <= #1 key_c; + +always @(posedge clk) + for(i=0;i<33;i=i+1) + key_c_r[i+1] <= #1 key_c_r[i]; + +des u0( .desOut(stage1_out), .desIn(desIn), .key(key_a), .decrypt(decrypt), .clk(clk) ); + +des u1( .desOut(stage2_out), .desIn(stage1_out), .key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) ); + +des u2( .desOut(desOut), .desIn(stage2_out), .key(key_c_r[33]), .decrypt(decrypt), .clk(clk) ); + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel.v new file mode 100644 index 000000000..c5598d61d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel.v @@ -0,0 +1,852 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL //// +//// Generate 16 pipelined sub-keys //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module key_sel(clk, K, decrypt, K1, K2, K3, K4, K5, K6, K7, K8, K9, + K10, K11, K12, K13, K14, K15, K16); +input clk; +input [55:0] K; +input decrypt; +output [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +output [1:48] K10, K11, K12, K13, K14, K15, K16; + +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; +reg [55:0] K_r0, K_r1, K_r2, K_r3, K_r4, K_r5, K_r6, K_r7; +reg [55:0] K_r8, K_r9, K_r10, K_r11, K_r12, K_r13, K_r14; + +always @(posedge clk) + begin + K_r0 <= #1 K; + K_r1 <= #1 K_r0; + K_r2 <= #1 K_r1; + K_r3 <= #1 K_r2; + K_r4 <= #1 K_r3; + K_r5 <= #1 K_r4; + K_r6 <= #1 K_r5; + K_r7 <= #1 K_r6; + K_r8 <= #1 K_r7; + K_r9 <= #1 K_r8; + K_r10 <= #1 K_r9; + K_r11 <= #1 K_r10; + K_r12 <= #1 K_r11; + K_r13 <= #1 K_r12; + K_r14 <= #1 K_r13; + end + +assign K16[1] = decrypt ? K_r14[47] : K_r14[40]; +assign K16[2] = decrypt ? K_r14[11] : K_r14[4]; +assign K16[3] = decrypt ? K_r14[26] : K_r14[19]; +assign K16[4] = decrypt ? K_r14[3] : K_r14[53]; +assign K16[5] = decrypt ? K_r14[13] : K_r14[6]; +assign K16[6] = decrypt ? K_r14[41] : K_r14[34]; +assign K16[7] = decrypt ? K_r14[27] : K_r14[20]; +assign K16[8] = decrypt ? K_r14[6] : K_r14[24]; +assign K16[9] = decrypt ? K_r14[54] : K_r14[47]; +assign K16[10] = decrypt ? K_r14[48] : K_r14[41]; +assign K16[11] = decrypt ? K_r14[39] : K_r14[32]; +assign K16[12] = decrypt ? K_r14[19] : K_r14[12]; +assign K16[13] = decrypt ? K_r14[53] : K_r14[46]; +assign K16[14] = decrypt ? K_r14[25] : K_r14[18]; +assign K16[15] = decrypt ? K_r14[33] : K_r14[26]; +assign K16[16] = decrypt ? K_r14[34] : K_r14[27]; +assign K16[17] = decrypt ? K_r14[17] : K_r14[10]; +assign K16[18] = decrypt ? K_r14[5] : K_r14[55]; +assign K16[19] = decrypt ? K_r14[4] : K_r14[54]; +assign K16[20] = decrypt ? K_r14[55] : K_r14[48]; +assign K16[21] = decrypt ? K_r14[24] : K_r14[17]; +assign K16[22] = decrypt ? K_r14[32] : K_r14[25]; +assign K16[23] = decrypt ? K_r14[40] : K_r14[33]; +assign K16[24] = decrypt ? K_r14[20] : K_r14[13]; +assign K16[25] = decrypt ? K_r14[36] : K_r14[29]; +assign K16[26] = decrypt ? K_r14[31] : K_r14[51]; +assign K16[27] = decrypt ? K_r14[21] : K_r14[14]; +assign K16[28] = decrypt ? K_r14[8] : K_r14[1]; +assign K16[29] = decrypt ? K_r14[23] : K_r14[16]; +assign K16[30] = decrypt ? K_r14[52] : K_r14[45]; +assign K16[31] = decrypt ? K_r14[14] : K_r14[7]; +assign K16[32] = decrypt ? K_r14[29] : K_r14[22]; +assign K16[33] = decrypt ? K_r14[51] : K_r14[44]; +assign K16[34] = decrypt ? K_r14[9] : K_r14[2]; +assign K16[35] = decrypt ? K_r14[35] : K_r14[28]; +assign K16[36] = decrypt ? K_r14[30] : K_r14[23]; +assign K16[37] = decrypt ? K_r14[2] : K_r14[50]; +assign K16[38] = decrypt ? K_r14[37] : K_r14[30]; +assign K16[39] = decrypt ? K_r14[22] : K_r14[15]; +assign K16[40] = decrypt ? K_r14[0] : K_r14[52]; +assign K16[41] = decrypt ? K_r14[42] : K_r14[35]; +assign K16[42] = decrypt ? K_r14[38] : K_r14[31]; +assign K16[43] = decrypt ? K_r14[16] : K_r14[9]; +assign K16[44] = decrypt ? K_r14[43] : K_r14[36]; +assign K16[45] = decrypt ? K_r14[44] : K_r14[37]; +assign K16[46] = decrypt ? K_r14[1] : K_r14[49]; +assign K16[47] = decrypt ? K_r14[7] : K_r14[0]; +assign K16[48] = decrypt ? K_r14[28] : K_r14[21]; + +assign K15[1] = decrypt ? K_r13[54] : K_r13[33]; +assign K15[2] = decrypt ? K_r13[18] : K_r13[54]; +assign K15[3] = decrypt ? K_r13[33] : K_r13[12]; +assign K15[4] = decrypt ? K_r13[10] : K_r13[46]; +assign K15[5] = decrypt ? K_r13[20] : K_r13[24]; +assign K15[6] = decrypt ? K_r13[48] : K_r13[27]; +assign K15[7] = decrypt ? K_r13[34] : K_r13[13]; +assign K15[8] = decrypt ? K_r13[13] : K_r13[17]; +assign K15[9] = decrypt ? K_r13[4] : K_r13[40]; +assign K15[10] = decrypt ? K_r13[55] : K_r13[34]; +assign K15[11] = decrypt ? K_r13[46] : K_r13[25]; +assign K15[12] = decrypt ? K_r13[26] : K_r13[5]; +assign K15[13] = decrypt ? K_r13[3] : K_r13[39]; +assign K15[14] = decrypt ? K_r13[32] : K_r13[11]; +assign K15[15] = decrypt ? K_r13[40] : K_r13[19]; +assign K15[16] = decrypt ? K_r13[41] : K_r13[20]; +assign K15[17] = decrypt ? K_r13[24] : K_r13[3]; +assign K15[18] = decrypt ? K_r13[12] : K_r13[48]; +assign K15[19] = decrypt ? K_r13[11] : K_r13[47]; +assign K15[20] = decrypt ? K_r13[5] : K_r13[41]; +assign K15[21] = decrypt ? K_r13[6] : K_r13[10]; +assign K15[22] = decrypt ? K_r13[39] : K_r13[18]; +assign K15[23] = decrypt ? K_r13[47] : K_r13[26]; +assign K15[24] = decrypt ? K_r13[27] : K_r13[6]; +assign K15[25] = decrypt ? K_r13[43] : K_r13[22]; +assign K15[26] = decrypt ? K_r13[38] : K_r13[44]; +assign K15[27] = decrypt ? K_r13[28] : K_r13[7]; +assign K15[28] = decrypt ? K_r13[15] : K_r13[49]; +assign K15[29] = decrypt ? K_r13[30] : K_r13[9]; +assign K15[30] = decrypt ? K_r13[0] : K_r13[38]; +assign K15[31] = decrypt ? K_r13[21] : K_r13[0]; +assign K15[32] = decrypt ? K_r13[36] : K_r13[15]; +assign K15[33] = decrypt ? K_r13[31] : K_r13[37]; +assign K15[34] = decrypt ? K_r13[16] : K_r13[50]; +assign K15[35] = decrypt ? K_r13[42] : K_r13[21]; +assign K15[36] = decrypt ? K_r13[37] : K_r13[16]; +assign K15[37] = decrypt ? K_r13[9] : K_r13[43]; +assign K15[38] = decrypt ? K_r13[44] : K_r13[23]; +assign K15[39] = decrypt ? K_r13[29] : K_r13[8]; +assign K15[40] = decrypt ? K_r13[7] : K_r13[45]; +assign K15[41] = decrypt ? K_r13[49] : K_r13[28]; +assign K15[42] = decrypt ? K_r13[45] : K_r13[51]; +assign K15[43] = decrypt ? K_r13[23] : K_r13[2]; +assign K15[44] = decrypt ? K_r13[50] : K_r13[29]; +assign K15[45] = decrypt ? K_r13[51] : K_r13[30]; +assign K15[46] = decrypt ? K_r13[8] : K_r13[42]; +assign K15[47] = decrypt ? K_r13[14] : K_r13[52]; +assign K15[48] = decrypt ? K_r13[35] : K_r13[14]; + +assign K14[1] = decrypt ? K_r12[11] : K_r12[19]; +assign K14[2] = decrypt ? K_r12[32] : K_r12[40]; +assign K14[3] = decrypt ? K_r12[47] : K_r12[55]; +assign K14[4] = decrypt ? K_r12[24] : K_r12[32]; +assign K14[5] = decrypt ? K_r12[34] : K_r12[10]; +assign K14[6] = decrypt ? K_r12[5] : K_r12[13]; +assign K14[7] = decrypt ? K_r12[48] : K_r12[24]; +assign K14[8] = decrypt ? K_r12[27] : K_r12[3]; +assign K14[9] = decrypt ? K_r12[18] : K_r12[26]; +assign K14[10] = decrypt ? K_r12[12] : K_r12[20]; +assign K14[11] = decrypt ? K_r12[3] : K_r12[11]; +assign K14[12] = decrypt ? K_r12[40] : K_r12[48]; +assign K14[13] = decrypt ? K_r12[17] : K_r12[25]; +assign K14[14] = decrypt ? K_r12[46] : K_r12[54]; +assign K14[15] = decrypt ? K_r12[54] : K_r12[5]; +assign K14[16] = decrypt ? K_r12[55] : K_r12[6]; +assign K14[17] = decrypt ? K_r12[13] : K_r12[46]; +assign K14[18] = decrypt ? K_r12[26] : K_r12[34]; +assign K14[19] = decrypt ? K_r12[25] : K_r12[33]; +assign K14[20] = decrypt ? K_r12[19] : K_r12[27]; +assign K14[21] = decrypt ? K_r12[20] : K_r12[53]; +assign K14[22] = decrypt ? K_r12[53] : K_r12[4]; +assign K14[23] = decrypt ? K_r12[4] : K_r12[12]; +assign K14[24] = decrypt ? K_r12[41] : K_r12[17]; +assign K14[25] = decrypt ? K_r12[2] : K_r12[8]; +assign K14[26] = decrypt ? K_r12[52] : K_r12[30]; +assign K14[27] = decrypt ? K_r12[42] : K_r12[52]; +assign K14[28] = decrypt ? K_r12[29] : K_r12[35]; +assign K14[29] = decrypt ? K_r12[44] : K_r12[50]; +assign K14[30] = decrypt ? K_r12[14] : K_r12[51]; +assign K14[31] = decrypt ? K_r12[35] : K_r12[45]; +assign K14[32] = decrypt ? K_r12[50] : K_r12[1]; +assign K14[33] = decrypt ? K_r12[45] : K_r12[23]; +assign K14[34] = decrypt ? K_r12[30] : K_r12[36]; +assign K14[35] = decrypt ? K_r12[1] : K_r12[7]; +assign K14[36] = decrypt ? K_r12[51] : K_r12[2]; +assign K14[37] = decrypt ? K_r12[23] : K_r12[29]; +assign K14[38] = decrypt ? K_r12[31] : K_r12[9]; +assign K14[39] = decrypt ? K_r12[43] : K_r12[49]; +assign K14[40] = decrypt ? K_r12[21] : K_r12[31]; +assign K14[41] = decrypt ? K_r12[8] : K_r12[14]; +assign K14[42] = decrypt ? K_r12[0] : K_r12[37]; +assign K14[43] = decrypt ? K_r12[37] : K_r12[43]; +assign K14[44] = decrypt ? K_r12[9] : K_r12[15]; +assign K14[45] = decrypt ? K_r12[38] : K_r12[16]; +assign K14[46] = decrypt ? K_r12[22] : K_r12[28]; +assign K14[47] = decrypt ? K_r12[28] : K_r12[38]; +assign K14[48] = decrypt ? K_r12[49] : K_r12[0]; + +assign K13[1] = decrypt ? K_r11[25] : K_r11[5]; +assign K13[2] = decrypt ? K_r11[46] : K_r11[26]; +assign K13[3] = decrypt ? K_r11[4] : K_r11[41]; +assign K13[4] = decrypt ? K_r11[13] : K_r11[18]; +assign K13[5] = decrypt ? K_r11[48] : K_r11[53]; +assign K13[6] = decrypt ? K_r11[19] : K_r11[24]; +assign K13[7] = decrypt ? K_r11[5] : K_r11[10]; +assign K13[8] = decrypt ? K_r11[41] : K_r11[46]; +assign K13[9] = decrypt ? K_r11[32] : K_r11[12]; +assign K13[10] = decrypt ? K_r11[26] : K_r11[6]; +assign K13[11] = decrypt ? K_r11[17] : K_r11[54]; +assign K13[12] = decrypt ? K_r11[54] : K_r11[34]; +assign K13[13] = decrypt ? K_r11[6] : K_r11[11]; +assign K13[14] = decrypt ? K_r11[3] : K_r11[40]; +assign K13[15] = decrypt ? K_r11[11] : K_r11[48]; +assign K13[16] = decrypt ? K_r11[12] : K_r11[17]; +assign K13[17] = decrypt ? K_r11[27] : K_r11[32]; +assign K13[18] = decrypt ? K_r11[40] : K_r11[20]; +assign K13[19] = decrypt ? K_r11[39] : K_r11[19]; +assign K13[20] = decrypt ? K_r11[33] : K_r11[13]; +assign K13[21] = decrypt ? K_r11[34] : K_r11[39]; +assign K13[22] = decrypt ? K_r11[10] : K_r11[47]; +assign K13[23] = decrypt ? K_r11[18] : K_r11[55]; +assign K13[24] = decrypt ? K_r11[55] : K_r11[3]; +assign K13[25] = decrypt ? K_r11[16] : K_r11[49]; +assign K13[26] = decrypt ? K_r11[7] : K_r11[16]; +assign K13[27] = decrypt ? K_r11[1] : K_r11[38]; +assign K13[28] = decrypt ? K_r11[43] : K_r11[21]; +assign K13[29] = decrypt ? K_r11[31] : K_r11[36]; +assign K13[30] = decrypt ? K_r11[28] : K_r11[37]; +assign K13[31] = decrypt ? K_r11[49] : K_r11[31]; +assign K13[32] = decrypt ? K_r11[9] : K_r11[42]; +assign K13[33] = decrypt ? K_r11[0] : K_r11[9]; +assign K13[34] = decrypt ? K_r11[44] : K_r11[22]; +assign K13[35] = decrypt ? K_r11[15] : K_r11[52]; +assign K13[36] = decrypt ? K_r11[38] : K_r11[43]; +assign K13[37] = decrypt ? K_r11[37] : K_r11[15]; +assign K13[38] = decrypt ? K_r11[45] : K_r11[50]; +assign K13[39] = decrypt ? K_r11[2] : K_r11[35]; +assign K13[40] = decrypt ? K_r11[35] : K_r11[44]; +assign K13[41] = decrypt ? K_r11[22] : K_r11[0]; +assign K13[42] = decrypt ? K_r11[14] : K_r11[23]; +assign K13[43] = decrypt ? K_r11[51] : K_r11[29]; +assign K13[44] = decrypt ? K_r11[23] : K_r11[1]; +assign K13[45] = decrypt ? K_r11[52] : K_r11[2]; +assign K13[46] = decrypt ? K_r11[36] : K_r11[14]; +assign K13[47] = decrypt ? K_r11[42] : K_r11[51]; +assign K13[48] = decrypt ? K_r11[8] : K_r11[45]; + +assign K12[1] = decrypt ? K_r10[39] : K_r10[48]; +assign K12[2] = decrypt ? K_r10[3] : K_r10[12]; +assign K12[3] = decrypt ? K_r10[18] : K_r10[27]; +assign K12[4] = decrypt ? K_r10[27] : K_r10[4]; +assign K12[5] = decrypt ? K_r10[5] : K_r10[39]; +assign K12[6] = decrypt ? K_r10[33] : K_r10[10]; +assign K12[7] = decrypt ? K_r10[19] : K_r10[53]; +assign K12[8] = decrypt ? K_r10[55] : K_r10[32]; +assign K12[9] = decrypt ? K_r10[46] : K_r10[55]; +assign K12[10] = decrypt ? K_r10[40] : K_r10[17]; +assign K12[11] = decrypt ? K_r10[6] : K_r10[40]; +assign K12[12] = decrypt ? K_r10[11] : K_r10[20]; +assign K12[13] = decrypt ? K_r10[20] : K_r10[54]; +assign K12[14] = decrypt ? K_r10[17] : K_r10[26]; +assign K12[15] = decrypt ? K_r10[25] : K_r10[34]; +assign K12[16] = decrypt ? K_r10[26] : K_r10[3]; +assign K12[17] = decrypt ? K_r10[41] : K_r10[18]; +assign K12[18] = decrypt ? K_r10[54] : K_r10[6]; +assign K12[19] = decrypt ? K_r10[53] : K_r10[5]; +assign K12[20] = decrypt ? K_r10[47] : K_r10[24]; +assign K12[21] = decrypt ? K_r10[48] : K_r10[25]; +assign K12[22] = decrypt ? K_r10[24] : K_r10[33]; +assign K12[23] = decrypt ? K_r10[32] : K_r10[41]; +assign K12[24] = decrypt ? K_r10[12] : K_r10[46]; +assign K12[25] = decrypt ? K_r10[30] : K_r10[35]; +assign K12[26] = decrypt ? K_r10[21] : K_r10[2]; +assign K12[27] = decrypt ? K_r10[15] : K_r10[51]; +assign K12[28] = decrypt ? K_r10[2] : K_r10[7]; +assign K12[29] = decrypt ? K_r10[45] : K_r10[22]; +assign K12[30] = decrypt ? K_r10[42] : K_r10[23]; +assign K12[31] = decrypt ? K_r10[8] : K_r10[44]; +assign K12[32] = decrypt ? K_r10[23] : K_r10[28]; +assign K12[33] = decrypt ? K_r10[14] : K_r10[50]; +assign K12[34] = decrypt ? K_r10[31] : K_r10[8]; +assign K12[35] = decrypt ? K_r10[29] : K_r10[38]; +assign K12[36] = decrypt ? K_r10[52] : K_r10[29]; +assign K12[37] = decrypt ? K_r10[51] : K_r10[1]; +assign K12[38] = decrypt ? K_r10[0] : K_r10[36]; +assign K12[39] = decrypt ? K_r10[16] : K_r10[21]; +assign K12[40] = decrypt ? K_r10[49] : K_r10[30]; +assign K12[41] = decrypt ? K_r10[36] : K_r10[45]; +assign K12[42] = decrypt ? K_r10[28] : K_r10[9]; +assign K12[43] = decrypt ? K_r10[38] : K_r10[15]; +assign K12[44] = decrypt ? K_r10[37] : K_r10[42]; +assign K12[45] = decrypt ? K_r10[7] : K_r10[43]; +assign K12[46] = decrypt ? K_r10[50] : K_r10[0]; +assign K12[47] = decrypt ? K_r10[1] : K_r10[37]; +assign K12[48] = decrypt ? K_r10[22] : K_r10[31]; + +assign K11[1] = decrypt ? K_r9[53] : K_r9[34]; +assign K11[2] = decrypt ? K_r9[17] : K_r9[55]; +assign K11[3] = decrypt ? K_r9[32] : K_r9[13]; +assign K11[4] = decrypt ? K_r9[41] : K_r9[47]; +assign K11[5] = decrypt ? K_r9[19] : K_r9[25]; +assign K11[6] = decrypt ? K_r9[47] : K_r9[53]; +assign K11[7] = decrypt ? K_r9[33] : K_r9[39]; +assign K11[8] = decrypt ? K_r9[12] : K_r9[18]; +assign K11[9] = decrypt ? K_r9[3] : K_r9[41]; +assign K11[10] = decrypt ? K_r9[54] : K_r9[3]; +assign K11[11] = decrypt ? K_r9[20] : K_r9[26]; +assign K11[12] = decrypt ? K_r9[25] : K_r9[6]; +assign K11[13] = decrypt ? K_r9[34] : K_r9[40]; +assign K11[14] = decrypt ? K_r9[6] : K_r9[12]; +assign K11[15] = decrypt ? K_r9[39] : K_r9[20]; +assign K11[16] = decrypt ? K_r9[40] : K_r9[46]; +assign K11[17] = decrypt ? K_r9[55] : K_r9[4]; +assign K11[18] = decrypt ? K_r9[11] : K_r9[17]; +assign K11[19] = decrypt ? K_r9[10] : K_r9[48]; +assign K11[20] = decrypt ? K_r9[4] : K_r9[10]; +assign K11[21] = decrypt ? K_r9[5] : K_r9[11]; +assign K11[22] = decrypt ? K_r9[13] : K_r9[19]; +assign K11[23] = decrypt ? K_r9[46] : K_r9[27]; +assign K11[24] = decrypt ? K_r9[26] : K_r9[32]; +assign K11[25] = decrypt ? K_r9[44] : K_r9[21]; +assign K11[26] = decrypt ? K_r9[35] : K_r9[43]; +assign K11[27] = decrypt ? K_r9[29] : K_r9[37]; +assign K11[28] = decrypt ? K_r9[16] : K_r9[52]; +assign K11[29] = decrypt ? K_r9[0] : K_r9[8]; +assign K11[30] = decrypt ? K_r9[1] : K_r9[9]; +assign K11[31] = decrypt ? K_r9[22] : K_r9[30]; +assign K11[32] = decrypt ? K_r9[37] : K_r9[14]; +assign K11[33] = decrypt ? K_r9[28] : K_r9[36]; +assign K11[34] = decrypt ? K_r9[45] : K_r9[49]; +assign K11[35] = decrypt ? K_r9[43] : K_r9[51]; +assign K11[36] = decrypt ? K_r9[7] : K_r9[15]; +assign K11[37] = decrypt ? K_r9[38] : K_r9[42]; +assign K11[38] = decrypt ? K_r9[14] : K_r9[22]; +assign K11[39] = decrypt ? K_r9[30] : K_r9[7]; +assign K11[40] = decrypt ? K_r9[8] : K_r9[16]; +assign K11[41] = decrypt ? K_r9[50] : K_r9[31]; +assign K11[42] = decrypt ? K_r9[42] : K_r9[50]; +assign K11[43] = decrypt ? K_r9[52] : K_r9[1]; +assign K11[44] = decrypt ? K_r9[51] : K_r9[28]; +assign K11[45] = decrypt ? K_r9[21] : K_r9[29]; +assign K11[46] = decrypt ? K_r9[9] : K_r9[45]; +assign K11[47] = decrypt ? K_r9[15] : K_r9[23]; +assign K11[48] = decrypt ? K_r9[36] : K_r9[44]; + +assign K10[1] = decrypt ? K_r8[10] : K_r8[20]; +assign K10[2] = decrypt ? K_r8[6] : K_r8[41]; +assign K10[3] = decrypt ? K_r8[46] : K_r8[24]; +assign K10[4] = decrypt ? K_r8[55] : K_r8[33]; +assign K10[5] = decrypt ? K_r8[33] : K_r8[11]; +assign K10[6] = decrypt ? K_r8[4] : K_r8[39]; +assign K10[7] = decrypt ? K_r8[47] : K_r8[25]; +assign K10[8] = decrypt ? K_r8[26] : K_r8[4]; +assign K10[9] = decrypt ? K_r8[17] : K_r8[27]; +assign K10[10] = decrypt ? K_r8[11] : K_r8[46]; +assign K10[11] = decrypt ? K_r8[34] : K_r8[12]; +assign K10[12] = decrypt ? K_r8[39] : K_r8[17]; +assign K10[13] = decrypt ? K_r8[48] : K_r8[26]; +assign K10[14] = decrypt ? K_r8[20] : K_r8[55]; +assign K10[15] = decrypt ? K_r8[53] : K_r8[6]; +assign K10[16] = decrypt ? K_r8[54] : K_r8[32]; +assign K10[17] = decrypt ? K_r8[12] : K_r8[47]; +assign K10[18] = decrypt ? K_r8[25] : K_r8[3]; +assign K10[19] = decrypt ? K_r8[24] : K_r8[34]; +assign K10[20] = decrypt ? K_r8[18] : K_r8[53]; +assign K10[21] = decrypt ? K_r8[19] : K_r8[54]; +assign K10[22] = decrypt ? K_r8[27] : K_r8[5]; +assign K10[23] = decrypt ? K_r8[3] : K_r8[13]; +assign K10[24] = decrypt ? K_r8[40] : K_r8[18]; +assign K10[25] = decrypt ? K_r8[31] : K_r8[7]; +assign K10[26] = decrypt ? K_r8[49] : K_r8[29]; +assign K10[27] = decrypt ? K_r8[43] : K_r8[23]; +assign K10[28] = decrypt ? K_r8[30] : K_r8[38]; +assign K10[29] = decrypt ? K_r8[14] : K_r8[49]; +assign K10[30] = decrypt ? K_r8[15] : K_r8[50]; +assign K10[31] = decrypt ? K_r8[36] : K_r8[16]; +assign K10[32] = decrypt ? K_r8[51] : K_r8[0]; +assign K10[33] = decrypt ? K_r8[42] : K_r8[22]; +assign K10[34] = decrypt ? K_r8[0] : K_r8[35]; +assign K10[35] = decrypt ? K_r8[2] : K_r8[37]; +assign K10[36] = decrypt ? K_r8[21] : K_r8[1]; +assign K10[37] = decrypt ? K_r8[52] : K_r8[28]; +assign K10[38] = decrypt ? K_r8[28] : K_r8[8]; +assign K10[39] = decrypt ? K_r8[44] : K_r8[52]; +assign K10[40] = decrypt ? K_r8[22] : K_r8[2]; +assign K10[41] = decrypt ? K_r8[9] : K_r8[44]; +assign K10[42] = decrypt ? K_r8[1] : K_r8[36]; +assign K10[43] = decrypt ? K_r8[7] : K_r8[42]; +assign K10[44] = decrypt ? K_r8[38] : K_r8[14]; +assign K10[45] = decrypt ? K_r8[35] : K_r8[15]; +assign K10[46] = decrypt ? K_r8[23] : K_r8[31]; +assign K10[47] = decrypt ? K_r8[29] : K_r8[9]; +assign K10[48] = decrypt ? K_r8[50] : K_r8[30]; + +assign K9[1] = decrypt ? K_r7[24] : K_r7[6]; +assign K9[2] = decrypt ? K_r7[20] : K_r7[27]; +assign K9[3] = decrypt ? K_r7[3] : K_r7[10]; +assign K9[4] = decrypt ? K_r7[12] : K_r7[19]; +assign K9[5] = decrypt ? K_r7[47] : K_r7[54]; +assign K9[6] = decrypt ? K_r7[18] : K_r7[25]; +assign K9[7] = decrypt ? K_r7[4] : K_r7[11]; +assign K9[8] = decrypt ? K_r7[40] : K_r7[47]; +assign K9[9] = decrypt ? K_r7[6] : K_r7[13]; +assign K9[10] = decrypt ? K_r7[25] : K_r7[32]; +assign K9[11] = decrypt ? K_r7[48] : K_r7[55]; +assign K9[12] = decrypt ? K_r7[53] : K_r7[3]; +assign K9[13] = decrypt ? K_r7[5] : K_r7[12]; +assign K9[14] = decrypt ? K_r7[34] : K_r7[41]; +assign K9[15] = decrypt ? K_r7[10] : K_r7[17]; +assign K9[16] = decrypt ? K_r7[11] : K_r7[18]; +assign K9[17] = decrypt ? K_r7[26] : K_r7[33]; +assign K9[18] = decrypt ? K_r7[39] : K_r7[46]; +assign K9[19] = decrypt ? K_r7[13] : K_r7[20]; +assign K9[20] = decrypt ? K_r7[32] : K_r7[39]; +assign K9[21] = decrypt ? K_r7[33] : K_r7[40]; +assign K9[22] = decrypt ? K_r7[41] : K_r7[48]; +assign K9[23] = decrypt ? K_r7[17] : K_r7[24]; +assign K9[24] = decrypt ? K_r7[54] : K_r7[4]; +assign K9[25] = decrypt ? K_r7[45] : K_r7[52]; +assign K9[26] = decrypt ? K_r7[8] : K_r7[15]; +assign K9[27] = decrypt ? K_r7[2] : K_r7[9]; +assign K9[28] = decrypt ? K_r7[44] : K_r7[51]; +assign K9[29] = decrypt ? K_r7[28] : K_r7[35]; +assign K9[30] = decrypt ? K_r7[29] : K_r7[36]; +assign K9[31] = decrypt ? K_r7[50] : K_r7[2]; +assign K9[32] = decrypt ? K_r7[38] : K_r7[45]; +assign K9[33] = decrypt ? K_r7[1] : K_r7[8]; +assign K9[34] = decrypt ? K_r7[14] : K_r7[21]; +assign K9[35] = decrypt ? K_r7[16] : K_r7[23]; +assign K9[36] = decrypt ? K_r7[35] : K_r7[42]; +assign K9[37] = decrypt ? K_r7[7] : K_r7[14]; +assign K9[38] = decrypt ? K_r7[42] : K_r7[49]; +assign K9[39] = decrypt ? K_r7[31] : K_r7[38]; +assign K9[40] = decrypt ? K_r7[36] : K_r7[43]; +assign K9[41] = decrypt ? K_r7[23] : K_r7[30]; +assign K9[42] = decrypt ? K_r7[15] : K_r7[22]; +assign K9[43] = decrypt ? K_r7[21] : K_r7[28]; +assign K9[44] = decrypt ? K_r7[52] : K_r7[0]; +assign K9[45] = decrypt ? K_r7[49] : K_r7[1]; +assign K9[46] = decrypt ? K_r7[37] : K_r7[44]; +assign K9[47] = decrypt ? K_r7[43] : K_r7[50]; +assign K9[48] = decrypt ? K_r7[9] : K_r7[16]; + +assign K8[1] = decrypt ? K_r6[6] : K_r6[24]; +assign K8[2] = decrypt ? K_r6[27] : K_r6[20]; +assign K8[3] = decrypt ? K_r6[10] : K_r6[3]; +assign K8[4] = decrypt ? K_r6[19] : K_r6[12]; +assign K8[5] = decrypt ? K_r6[54] : K_r6[47]; +assign K8[6] = decrypt ? K_r6[25] : K_r6[18]; +assign K8[7] = decrypt ? K_r6[11] : K_r6[4]; +assign K8[8] = decrypt ? K_r6[47] : K_r6[40]; +assign K8[9] = decrypt ? K_r6[13] : K_r6[6]; +assign K8[10] = decrypt ? K_r6[32] : K_r6[25]; +assign K8[11] = decrypt ? K_r6[55] : K_r6[48]; +assign K8[12] = decrypt ? K_r6[3] : K_r6[53]; +assign K8[13] = decrypt ? K_r6[12] : K_r6[5]; +assign K8[14] = decrypt ? K_r6[41] : K_r6[34]; +assign K8[15] = decrypt ? K_r6[17] : K_r6[10]; +assign K8[16] = decrypt ? K_r6[18] : K_r6[11]; +assign K8[17] = decrypt ? K_r6[33] : K_r6[26]; +assign K8[18] = decrypt ? K_r6[46] : K_r6[39]; +assign K8[19] = decrypt ? K_r6[20] : K_r6[13]; +assign K8[20] = decrypt ? K_r6[39] : K_r6[32]; +assign K8[21] = decrypt ? K_r6[40] : K_r6[33]; +assign K8[22] = decrypt ? K_r6[48] : K_r6[41]; +assign K8[23] = decrypt ? K_r6[24] : K_r6[17]; +assign K8[24] = decrypt ? K_r6[4] : K_r6[54]; +assign K8[25] = decrypt ? K_r6[52] : K_r6[45]; +assign K8[26] = decrypt ? K_r6[15] : K_r6[8]; +assign K8[27] = decrypt ? K_r6[9] : K_r6[2]; +assign K8[28] = decrypt ? K_r6[51] : K_r6[44]; +assign K8[29] = decrypt ? K_r6[35] : K_r6[28]; +assign K8[30] = decrypt ? K_r6[36] : K_r6[29]; +assign K8[31] = decrypt ? K_r6[2] : K_r6[50]; +assign K8[32] = decrypt ? K_r6[45] : K_r6[38]; +assign K8[33] = decrypt ? K_r6[8] : K_r6[1]; +assign K8[34] = decrypt ? K_r6[21] : K_r6[14]; +assign K8[35] = decrypt ? K_r6[23] : K_r6[16]; +assign K8[36] = decrypt ? K_r6[42] : K_r6[35]; +assign K8[37] = decrypt ? K_r6[14] : K_r6[7]; +assign K8[38] = decrypt ? K_r6[49] : K_r6[42]; +assign K8[39] = decrypt ? K_r6[38] : K_r6[31]; +assign K8[40] = decrypt ? K_r6[43] : K_r6[36]; +assign K8[41] = decrypt ? K_r6[30] : K_r6[23]; +assign K8[42] = decrypt ? K_r6[22] : K_r6[15]; +assign K8[43] = decrypt ? K_r6[28] : K_r6[21]; +assign K8[44] = decrypt ? K_r6[0] : K_r6[52]; +assign K8[45] = decrypt ? K_r6[1] : K_r6[49]; +assign K8[46] = decrypt ? K_r6[44] : K_r6[37]; +assign K8[47] = decrypt ? K_r6[50] : K_r6[43]; +assign K8[48] = decrypt ? K_r6[16] : K_r6[9]; + +assign K7[1] = decrypt ? K_r5[20] : K_r5[10]; +assign K7[2] = decrypt ? K_r5[41] : K_r5[6]; +assign K7[3] = decrypt ? K_r5[24] : K_r5[46]; +assign K7[4] = decrypt ? K_r5[33] : K_r5[55]; +assign K7[5] = decrypt ? K_r5[11] : K_r5[33]; +assign K7[6] = decrypt ? K_r5[39] : K_r5[4]; +assign K7[7] = decrypt ? K_r5[25] : K_r5[47]; +assign K7[8] = decrypt ? K_r5[4] : K_r5[26]; +assign K7[9] = decrypt ? K_r5[27] : K_r5[17]; +assign K7[10] = decrypt ? K_r5[46] : K_r5[11]; +assign K7[11] = decrypt ? K_r5[12] : K_r5[34]; +assign K7[12] = decrypt ? K_r5[17] : K_r5[39]; +assign K7[13] = decrypt ? K_r5[26] : K_r5[48]; +assign K7[14] = decrypt ? K_r5[55] : K_r5[20]; +assign K7[15] = decrypt ? K_r5[6] : K_r5[53]; +assign K7[16] = decrypt ? K_r5[32] : K_r5[54]; +assign K7[17] = decrypt ? K_r5[47] : K_r5[12]; +assign K7[18] = decrypt ? K_r5[3] : K_r5[25]; +assign K7[19] = decrypt ? K_r5[34] : K_r5[24]; +assign K7[20] = decrypt ? K_r5[53] : K_r5[18]; +assign K7[21] = decrypt ? K_r5[54] : K_r5[19]; +assign K7[22] = decrypt ? K_r5[5] : K_r5[27]; +assign K7[23] = decrypt ? K_r5[13] : K_r5[3]; +assign K7[24] = decrypt ? K_r5[18] : K_r5[40]; +assign K7[25] = decrypt ? K_r5[7] : K_r5[31]; +assign K7[26] = decrypt ? K_r5[29] : K_r5[49]; +assign K7[27] = decrypt ? K_r5[23] : K_r5[43]; +assign K7[28] = decrypt ? K_r5[38] : K_r5[30]; +assign K7[29] = decrypt ? K_r5[49] : K_r5[14]; +assign K7[30] = decrypt ? K_r5[50] : K_r5[15]; +assign K7[31] = decrypt ? K_r5[16] : K_r5[36]; +assign K7[32] = decrypt ? K_r5[0] : K_r5[51]; +assign K7[33] = decrypt ? K_r5[22] : K_r5[42]; +assign K7[34] = decrypt ? K_r5[35] : K_r5[0]; +assign K7[35] = decrypt ? K_r5[37] : K_r5[2]; +assign K7[36] = decrypt ? K_r5[1] : K_r5[21]; +assign K7[37] = decrypt ? K_r5[28] : K_r5[52]; +assign K7[38] = decrypt ? K_r5[8] : K_r5[28]; +assign K7[39] = decrypt ? K_r5[52] : K_r5[44]; +assign K7[40] = decrypt ? K_r5[2] : K_r5[22]; +assign K7[41] = decrypt ? K_r5[44] : K_r5[9]; +assign K7[42] = decrypt ? K_r5[36] : K_r5[1]; +assign K7[43] = decrypt ? K_r5[42] : K_r5[7]; +assign K7[44] = decrypt ? K_r5[14] : K_r5[38]; +assign K7[45] = decrypt ? K_r5[15] : K_r5[35]; +assign K7[46] = decrypt ? K_r5[31] : K_r5[23]; +assign K7[47] = decrypt ? K_r5[9] : K_r5[29]; +assign K7[48] = decrypt ? K_r5[30] : K_r5[50]; + +assign K6[1] = decrypt ? K_r4[34] : K_r4[53]; +assign K6[2] = decrypt ? K_r4[55] : K_r4[17]; +assign K6[3] = decrypt ? K_r4[13] : K_r4[32]; +assign K6[4] = decrypt ? K_r4[47] : K_r4[41]; +assign K6[5] = decrypt ? K_r4[25] : K_r4[19]; +assign K6[6] = decrypt ? K_r4[53] : K_r4[47]; +assign K6[7] = decrypt ? K_r4[39] : K_r4[33]; +assign K6[8] = decrypt ? K_r4[18] : K_r4[12]; +assign K6[9] = decrypt ? K_r4[41] : K_r4[3]; +assign K6[10] = decrypt ? K_r4[3] : K_r4[54]; +assign K6[11] = decrypt ? K_r4[26] : K_r4[20]; +assign K6[12] = decrypt ? K_r4[6] : K_r4[25]; +assign K6[13] = decrypt ? K_r4[40] : K_r4[34]; +assign K6[14] = decrypt ? K_r4[12] : K_r4[6]; +assign K6[15] = decrypt ? K_r4[20] : K_r4[39]; +assign K6[16] = decrypt ? K_r4[46] : K_r4[40]; +assign K6[17] = decrypt ? K_r4[4] : K_r4[55]; +assign K6[18] = decrypt ? K_r4[17] : K_r4[11]; +assign K6[19] = decrypt ? K_r4[48] : K_r4[10]; +assign K6[20] = decrypt ? K_r4[10] : K_r4[4]; +assign K6[21] = decrypt ? K_r4[11] : K_r4[5]; +assign K6[22] = decrypt ? K_r4[19] : K_r4[13]; +assign K6[23] = decrypt ? K_r4[27] : K_r4[46]; +assign K6[24] = decrypt ? K_r4[32] : K_r4[26]; +assign K6[25] = decrypt ? K_r4[21] : K_r4[44]; +assign K6[26] = decrypt ? K_r4[43] : K_r4[35]; +assign K6[27] = decrypt ? K_r4[37] : K_r4[29]; +assign K6[28] = decrypt ? K_r4[52] : K_r4[16]; +assign K6[29] = decrypt ? K_r4[8] : K_r4[0]; +assign K6[30] = decrypt ? K_r4[9] : K_r4[1]; +assign K6[31] = decrypt ? K_r4[30] : K_r4[22]; +assign K6[32] = decrypt ? K_r4[14] : K_r4[37]; +assign K6[33] = decrypt ? K_r4[36] : K_r4[28]; +assign K6[34] = decrypt ? K_r4[49] : K_r4[45]; +assign K6[35] = decrypt ? K_r4[51] : K_r4[43]; +assign K6[36] = decrypt ? K_r4[15] : K_r4[7]; +assign K6[37] = decrypt ? K_r4[42] : K_r4[38]; +assign K6[38] = decrypt ? K_r4[22] : K_r4[14]; +assign K6[39] = decrypt ? K_r4[7] : K_r4[30]; +assign K6[40] = decrypt ? K_r4[16] : K_r4[8]; +assign K6[41] = decrypt ? K_r4[31] : K_r4[50]; +assign K6[42] = decrypt ? K_r4[50] : K_r4[42]; +assign K6[43] = decrypt ? K_r4[1] : K_r4[52]; +assign K6[44] = decrypt ? K_r4[28] : K_r4[51]; +assign K6[45] = decrypt ? K_r4[29] : K_r4[21]; +assign K6[46] = decrypt ? K_r4[45] : K_r4[9]; +assign K6[47] = decrypt ? K_r4[23] : K_r4[15]; +assign K6[48] = decrypt ? K_r4[44] : K_r4[36]; + +assign K5[1] = decrypt ? K_r3[48] : K_r3[39]; +assign K5[2] = decrypt ? K_r3[12] : K_r3[3]; +assign K5[3] = decrypt ? K_r3[27] : K_r3[18]; +assign K5[4] = decrypt ? K_r3[4] : K_r3[27]; +assign K5[5] = decrypt ? K_r3[39] : K_r3[5]; +assign K5[6] = decrypt ? K_r3[10] : K_r3[33]; +assign K5[7] = decrypt ? K_r3[53] : K_r3[19]; +assign K5[8] = decrypt ? K_r3[32] : K_r3[55]; +assign K5[9] = decrypt ? K_r3[55] : K_r3[46]; +assign K5[10] = decrypt ? K_r3[17] : K_r3[40]; +assign K5[11] = decrypt ? K_r3[40] : K_r3[6]; +assign K5[12] = decrypt ? K_r3[20] : K_r3[11]; +assign K5[13] = decrypt ? K_r3[54] : K_r3[20]; +assign K5[14] = decrypt ? K_r3[26] : K_r3[17]; +assign K5[15] = decrypt ? K_r3[34] : K_r3[25]; +assign K5[16] = decrypt ? K_r3[3] : K_r3[26]; +assign K5[17] = decrypt ? K_r3[18] : K_r3[41]; +assign K5[18] = decrypt ? K_r3[6] : K_r3[54]; +assign K5[19] = decrypt ? K_r3[5] : K_r3[53]; +assign K5[20] = decrypt ? K_r3[24] : K_r3[47]; +assign K5[21] = decrypt ? K_r3[25] : K_r3[48]; +assign K5[22] = decrypt ? K_r3[33] : K_r3[24]; +assign K5[23] = decrypt ? K_r3[41] : K_r3[32]; +assign K5[24] = decrypt ? K_r3[46] : K_r3[12]; +assign K5[25] = decrypt ? K_r3[35] : K_r3[30]; +assign K5[26] = decrypt ? K_r3[2] : K_r3[21]; +assign K5[27] = decrypt ? K_r3[51] : K_r3[15]; +assign K5[28] = decrypt ? K_r3[7] : K_r3[2]; +assign K5[29] = decrypt ? K_r3[22] : K_r3[45]; +assign K5[30] = decrypt ? K_r3[23] : K_r3[42]; +assign K5[31] = decrypt ? K_r3[44] : K_r3[8]; +assign K5[32] = decrypt ? K_r3[28] : K_r3[23]; +assign K5[33] = decrypt ? K_r3[50] : K_r3[14]; +assign K5[34] = decrypt ? K_r3[8] : K_r3[31]; +assign K5[35] = decrypt ? K_r3[38] : K_r3[29]; +assign K5[36] = decrypt ? K_r3[29] : K_r3[52]; +assign K5[37] = decrypt ? K_r3[1] : K_r3[51]; +assign K5[38] = decrypt ? K_r3[36] : K_r3[0]; +assign K5[39] = decrypt ? K_r3[21] : K_r3[16]; +assign K5[40] = decrypt ? K_r3[30] : K_r3[49]; +assign K5[41] = decrypt ? K_r3[45] : K_r3[36]; +assign K5[42] = decrypt ? K_r3[9] : K_r3[28]; +assign K5[43] = decrypt ? K_r3[15] : K_r3[38]; +assign K5[44] = decrypt ? K_r3[42] : K_r3[37]; +assign K5[45] = decrypt ? K_r3[43] : K_r3[7]; +assign K5[46] = decrypt ? K_r3[0] : K_r3[50]; +assign K5[47] = decrypt ? K_r3[37] : K_r3[1]; +assign K5[48] = decrypt ? K_r3[31] : K_r3[22]; + +assign K4[1] = decrypt ? K_r2[5] : K_r2[25]; +assign K4[2] = decrypt ? K_r2[26] : K_r2[46]; +assign K4[3] = decrypt ? K_r2[41] : K_r2[4]; +assign K4[4] = decrypt ? K_r2[18] : K_r2[13]; +assign K4[5] = decrypt ? K_r2[53] : K_r2[48]; +assign K4[6] = decrypt ? K_r2[24] : K_r2[19]; +assign K4[7] = decrypt ? K_r2[10] : K_r2[5]; +assign K4[8] = decrypt ? K_r2[46] : K_r2[41]; +assign K4[9] = decrypt ? K_r2[12] : K_r2[32]; +assign K4[10] = decrypt ? K_r2[6] : K_r2[26]; +assign K4[11] = decrypt ? K_r2[54] : K_r2[17]; +assign K4[12] = decrypt ? K_r2[34] : K_r2[54]; +assign K4[13] = decrypt ? K_r2[11] : K_r2[6]; +assign K4[14] = decrypt ? K_r2[40] : K_r2[3]; +assign K4[15] = decrypt ? K_r2[48] : K_r2[11]; +assign K4[16] = decrypt ? K_r2[17] : K_r2[12]; +assign K4[17] = decrypt ? K_r2[32] : K_r2[27]; +assign K4[18] = decrypt ? K_r2[20] : K_r2[40]; +assign K4[19] = decrypt ? K_r2[19] : K_r2[39]; +assign K4[20] = decrypt ? K_r2[13] : K_r2[33]; +assign K4[21] = decrypt ? K_r2[39] : K_r2[34]; +assign K4[22] = decrypt ? K_r2[47] : K_r2[10]; +assign K4[23] = decrypt ? K_r2[55] : K_r2[18]; +assign K4[24] = decrypt ? K_r2[3] : K_r2[55]; +assign K4[25] = decrypt ? K_r2[49] : K_r2[16]; +assign K4[26] = decrypt ? K_r2[16] : K_r2[7]; +assign K4[27] = decrypt ? K_r2[38] : K_r2[1]; +assign K4[28] = decrypt ? K_r2[21] : K_r2[43]; +assign K4[29] = decrypt ? K_r2[36] : K_r2[31]; +assign K4[30] = decrypt ? K_r2[37] : K_r2[28]; +assign K4[31] = decrypt ? K_r2[31] : K_r2[49]; +assign K4[32] = decrypt ? K_r2[42] : K_r2[9]; +assign K4[33] = decrypt ? K_r2[9] : K_r2[0]; +assign K4[34] = decrypt ? K_r2[22] : K_r2[44]; +assign K4[35] = decrypt ? K_r2[52] : K_r2[15]; +assign K4[36] = decrypt ? K_r2[43] : K_r2[38]; +assign K4[37] = decrypt ? K_r2[15] : K_r2[37]; +assign K4[38] = decrypt ? K_r2[50] : K_r2[45]; +assign K4[39] = decrypt ? K_r2[35] : K_r2[2]; +assign K4[40] = decrypt ? K_r2[44] : K_r2[35]; +assign K4[41] = decrypt ? K_r2[0] : K_r2[22]; +assign K4[42] = decrypt ? K_r2[23] : K_r2[14]; +assign K4[43] = decrypt ? K_r2[29] : K_r2[51]; +assign K4[44] = decrypt ? K_r2[1] : K_r2[23]; +assign K4[45] = decrypt ? K_r2[2] : K_r2[52]; +assign K4[46] = decrypt ? K_r2[14] : K_r2[36]; +assign K4[47] = decrypt ? K_r2[51] : K_r2[42]; +assign K4[48] = decrypt ? K_r2[45] : K_r2[8]; + +assign K3[1] = decrypt ? K_r1[19] : K_r1[11]; +assign K3[2] = decrypt ? K_r1[40] : K_r1[32]; +assign K3[3] = decrypt ? K_r1[55] : K_r1[47]; +assign K3[4] = decrypt ? K_r1[32] : K_r1[24]; +assign K3[5] = decrypt ? K_r1[10] : K_r1[34]; +assign K3[6] = decrypt ? K_r1[13] : K_r1[5]; +assign K3[7] = decrypt ? K_r1[24] : K_r1[48]; +assign K3[8] = decrypt ? K_r1[3] : K_r1[27]; +assign K3[9] = decrypt ? K_r1[26] : K_r1[18]; +assign K3[10] = decrypt ? K_r1[20] : K_r1[12]; +assign K3[11] = decrypt ? K_r1[11] : K_r1[3]; +assign K3[12] = decrypt ? K_r1[48] : K_r1[40]; +assign K3[13] = decrypt ? K_r1[25] : K_r1[17]; +assign K3[14] = decrypt ? K_r1[54] : K_r1[46]; +assign K3[15] = decrypt ? K_r1[5] : K_r1[54]; +assign K3[16] = decrypt ? K_r1[6] : K_r1[55]; +assign K3[17] = decrypt ? K_r1[46] : K_r1[13]; +assign K3[18] = decrypt ? K_r1[34] : K_r1[26]; +assign K3[19] = decrypt ? K_r1[33] : K_r1[25]; +assign K3[20] = decrypt ? K_r1[27] : K_r1[19]; +assign K3[21] = decrypt ? K_r1[53] : K_r1[20]; +assign K3[22] = decrypt ? K_r1[4] : K_r1[53]; +assign K3[23] = decrypt ? K_r1[12] : K_r1[4]; +assign K3[24] = decrypt ? K_r1[17] : K_r1[41]; +assign K3[25] = decrypt ? K_r1[8] : K_r1[2]; +assign K3[26] = decrypt ? K_r1[30] : K_r1[52]; +assign K3[27] = decrypt ? K_r1[52] : K_r1[42]; +assign K3[28] = decrypt ? K_r1[35] : K_r1[29]; +assign K3[29] = decrypt ? K_r1[50] : K_r1[44]; +assign K3[30] = decrypt ? K_r1[51] : K_r1[14]; +assign K3[31] = decrypt ? K_r1[45] : K_r1[35]; +assign K3[32] = decrypt ? K_r1[1] : K_r1[50]; +assign K3[33] = decrypt ? K_r1[23] : K_r1[45]; +assign K3[34] = decrypt ? K_r1[36] : K_r1[30]; +assign K3[35] = decrypt ? K_r1[7] : K_r1[1]; +assign K3[36] = decrypt ? K_r1[2] : K_r1[51]; +assign K3[37] = decrypt ? K_r1[29] : K_r1[23]; +assign K3[38] = decrypt ? K_r1[9] : K_r1[31]; +assign K3[39] = decrypt ? K_r1[49] : K_r1[43]; +assign K3[40] = decrypt ? K_r1[31] : K_r1[21]; +assign K3[41] = decrypt ? K_r1[14] : K_r1[8]; +assign K3[42] = decrypt ? K_r1[37] : K_r1[0]; +assign K3[43] = decrypt ? K_r1[43] : K_r1[37]; +assign K3[44] = decrypt ? K_r1[15] : K_r1[9]; +assign K3[45] = decrypt ? K_r1[16] : K_r1[38]; +assign K3[46] = decrypt ? K_r1[28] : K_r1[22]; +assign K3[47] = decrypt ? K_r1[38] : K_r1[28]; +assign K3[48] = decrypt ? K_r1[0] : K_r1[49]; + +assign K2[1] = decrypt ? K_r0[33] : K_r0[54]; +assign K2[2] = decrypt ? K_r0[54] : K_r0[18]; +assign K2[3] = decrypt ? K_r0[12] : K_r0[33]; +assign K2[4] = decrypt ? K_r0[46] : K_r0[10]; +assign K2[5] = decrypt ? K_r0[24] : K_r0[20]; +assign K2[6] = decrypt ? K_r0[27] : K_r0[48]; +assign K2[7] = decrypt ? K_r0[13] : K_r0[34]; +assign K2[8] = decrypt ? K_r0[17] : K_r0[13]; +assign K2[9] = decrypt ? K_r0[40] : K_r0[4]; +assign K2[10] = decrypt ? K_r0[34] : K_r0[55]; +assign K2[11] = decrypt ? K_r0[25] : K_r0[46]; +assign K2[12] = decrypt ? K_r0[5] : K_r0[26]; +assign K2[13] = decrypt ? K_r0[39] : K_r0[3]; +assign K2[14] = decrypt ? K_r0[11] : K_r0[32]; +assign K2[15] = decrypt ? K_r0[19] : K_r0[40]; +assign K2[16] = decrypt ? K_r0[20] : K_r0[41]; +assign K2[17] = decrypt ? K_r0[3] : K_r0[24]; +assign K2[18] = decrypt ? K_r0[48] : K_r0[12]; +assign K2[19] = decrypt ? K_r0[47] : K_r0[11]; +assign K2[20] = decrypt ? K_r0[41] : K_r0[5]; +assign K2[21] = decrypt ? K_r0[10] : K_r0[6]; +assign K2[22] = decrypt ? K_r0[18] : K_r0[39]; +assign K2[23] = decrypt ? K_r0[26] : K_r0[47]; +assign K2[24] = decrypt ? K_r0[6] : K_r0[27]; +assign K2[25] = decrypt ? K_r0[22] : K_r0[43]; +assign K2[26] = decrypt ? K_r0[44] : K_r0[38]; +assign K2[27] = decrypt ? K_r0[7] : K_r0[28]; +assign K2[28] = decrypt ? K_r0[49] : K_r0[15]; +assign K2[29] = decrypt ? K_r0[9] : K_r0[30]; +assign K2[30] = decrypt ? K_r0[38] : K_r0[0]; +assign K2[31] = decrypt ? K_r0[0] : K_r0[21]; +assign K2[32] = decrypt ? K_r0[15] : K_r0[36]; +assign K2[33] = decrypt ? K_r0[37] : K_r0[31]; +assign K2[34] = decrypt ? K_r0[50] : K_r0[16]; +assign K2[35] = decrypt ? K_r0[21] : K_r0[42]; +assign K2[36] = decrypt ? K_r0[16] : K_r0[37]; +assign K2[37] = decrypt ? K_r0[43] : K_r0[9]; +assign K2[38] = decrypt ? K_r0[23] : K_r0[44]; +assign K2[39] = decrypt ? K_r0[8] : K_r0[29]; +assign K2[40] = decrypt ? K_r0[45] : K_r0[7]; +assign K2[41] = decrypt ? K_r0[28] : K_r0[49]; +assign K2[42] = decrypt ? K_r0[51] : K_r0[45]; +assign K2[43] = decrypt ? K_r0[2] : K_r0[23]; +assign K2[44] = decrypt ? K_r0[29] : K_r0[50]; +assign K2[45] = decrypt ? K_r0[30] : K_r0[51]; +assign K2[46] = decrypt ? K_r0[42] : K_r0[8]; +assign K2[47] = decrypt ? K_r0[52] : K_r0[14]; +assign K2[48] = decrypt ? K_r0[14] : K_r0[35]; + +assign K1[1] = decrypt ? K[40] : K[47]; +assign K1[2] = decrypt ? K[4] : K[11]; +assign K1[3] = decrypt ? K[19] : K[26]; +assign K1[4] = decrypt ? K[53] : K[3]; +assign K1[5] = decrypt ? K[6] : K[13]; +assign K1[6] = decrypt ? K[34] : K[41]; +assign K1[7] = decrypt ? K[20] : K[27]; +assign K1[8] = decrypt ? K[24] : K[6]; +assign K1[9] = decrypt ? K[47] : K[54]; +assign K1[10] = decrypt ? K[41] : K[48]; +assign K1[11] = decrypt ? K[32] : K[39]; +assign K1[12] = decrypt ? K[12] : K[19]; +assign K1[13] = decrypt ? K[46] : K[53]; +assign K1[14] = decrypt ? K[18] : K[25]; +assign K1[15] = decrypt ? K[26] : K[33]; +assign K1[16] = decrypt ? K[27] : K[34]; +assign K1[17] = decrypt ? K[10] : K[17]; +assign K1[18] = decrypt ? K[55] : K[5]; +assign K1[19] = decrypt ? K[54] : K[4]; +assign K1[20] = decrypt ? K[48] : K[55]; +assign K1[21] = decrypt ? K[17] : K[24]; +assign K1[22] = decrypt ? K[25] : K[32]; +assign K1[23] = decrypt ? K[33] : K[40]; +assign K1[24] = decrypt ? K[13] : K[20]; +assign K1[25] = decrypt ? K[29] : K[36]; +assign K1[26] = decrypt ? K[51] : K[31]; +assign K1[27] = decrypt ? K[14] : K[21]; +assign K1[28] = decrypt ? K[1] : K[8]; +assign K1[29] = decrypt ? K[16] : K[23]; +assign K1[30] = decrypt ? K[45] : K[52]; +assign K1[31] = decrypt ? K[7] : K[14]; +assign K1[32] = decrypt ? K[22] : K[29]; +assign K1[33] = decrypt ? K[44] : K[51]; +assign K1[34] = decrypt ? K[2] : K[9]; +assign K1[35] = decrypt ? K[28] : K[35]; +assign K1[36] = decrypt ? K[23] : K[30]; +assign K1[37] = decrypt ? K[50] : K[2]; +assign K1[38] = decrypt ? K[30] : K[37]; +assign K1[39] = decrypt ? K[15] : K[22]; +assign K1[40] = decrypt ? K[52] : K[0]; +assign K1[41] = decrypt ? K[35] : K[42]; +assign K1[42] = decrypt ? K[31] : K[38]; +assign K1[43] = decrypt ? K[9] : K[16]; +assign K1[44] = decrypt ? K[36] : K[43]; +assign K1[45] = decrypt ? K[37] : K[44]; +assign K1[46] = decrypt ? K[49] : K[1]; +assign K1[47] = decrypt ? K[0] : K[7]; +assign K1[48] = decrypt ? K[21] : K[28]; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel3.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel3.v new file mode 100644 index 000000000..9f232c41d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/key_sel3.v @@ -0,0 +1,865 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// KEY_SEL //// +//// Select one of 16 sub-keys for round //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt); +output [1:48] K_sub; +input [55:0] key1, key2, key3; +input [5:0] roundSel; +input decrypt; + +wire decrypt_int; +reg [55:0] K; +reg [1:48] K_sub; +wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9; +wire [1:48] K10, K11, K12, K13, K14, K15, K16; + +always @(roundSel or decrypt or key1 or key2 or key3) + case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case + 3'b0_00: K = key1; + 3'b0_01: K = key2; + 3'b0_10: K = key3; + 3'b1_00: K = key3; + 3'b1_01: K = key2; + 3'b1_10: K = key1; + endcase + +assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt; + +always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10 + or K11 or K12 or K13 or K14 or K15 or K16 or roundSel) + case(roundSel[3:0]) // synopsys full_case parallel_case + 0: K_sub = K1; + 1: K_sub = K2; + 2: K_sub = K3; + 3: K_sub = K4; + 4: K_sub = K5; + 5: K_sub = K6; + 6: K_sub = K7; + 7: K_sub = K8; + 8: K_sub = K9; + 9: K_sub = K10; + 10: K_sub = K11; + 11: K_sub = K12; + 12: K_sub = K13; + 13: K_sub = K14; + 14: K_sub = K15; + 15: K_sub = K16; + endcase + + +assign K16[1] = decrypt_int ? K[47] : K[40]; +assign K16[2] = decrypt_int ? K[11] : K[4]; +assign K16[3] = decrypt_int ? K[26] : K[19]; +assign K16[4] = decrypt_int ? K[3] : K[53]; +assign K16[5] = decrypt_int ? K[13] : K[6]; +assign K16[6] = decrypt_int ? K[41] : K[34]; +assign K16[7] = decrypt_int ? K[27] : K[20]; +assign K16[8] = decrypt_int ? K[6] : K[24]; +assign K16[9] = decrypt_int ? K[54] : K[47]; +assign K16[10] = decrypt_int ? K[48] : K[41]; +assign K16[11] = decrypt_int ? K[39] : K[32]; +assign K16[12] = decrypt_int ? K[19] : K[12]; +assign K16[13] = decrypt_int ? K[53] : K[46]; +assign K16[14] = decrypt_int ? K[25] : K[18]; +assign K16[15] = decrypt_int ? K[33] : K[26]; +assign K16[16] = decrypt_int ? K[34] : K[27]; +assign K16[17] = decrypt_int ? K[17] : K[10]; +assign K16[18] = decrypt_int ? K[5] : K[55]; +assign K16[19] = decrypt_int ? K[4] : K[54]; +assign K16[20] = decrypt_int ? K[55] : K[48]; +assign K16[21] = decrypt_int ? K[24] : K[17]; +assign K16[22] = decrypt_int ? K[32] : K[25]; +assign K16[23] = decrypt_int ? K[40] : K[33]; +assign K16[24] = decrypt_int ? K[20] : K[13]; +assign K16[25] = decrypt_int ? K[36] : K[29]; +assign K16[26] = decrypt_int ? K[31] : K[51]; +assign K16[27] = decrypt_int ? K[21] : K[14]; +assign K16[28] = decrypt_int ? K[8] : K[1]; +assign K16[29] = decrypt_int ? K[23] : K[16]; +assign K16[30] = decrypt_int ? K[52] : K[45]; +assign K16[31] = decrypt_int ? K[14] : K[7]; +assign K16[32] = decrypt_int ? K[29] : K[22]; +assign K16[33] = decrypt_int ? K[51] : K[44]; +assign K16[34] = decrypt_int ? K[9] : K[2]; +assign K16[35] = decrypt_int ? K[35] : K[28]; +assign K16[36] = decrypt_int ? K[30] : K[23]; +assign K16[37] = decrypt_int ? K[2] : K[50]; +assign K16[38] = decrypt_int ? K[37] : K[30]; +assign K16[39] = decrypt_int ? K[22] : K[15]; +assign K16[40] = decrypt_int ? K[0] : K[52]; +assign K16[41] = decrypt_int ? K[42] : K[35]; +assign K16[42] = decrypt_int ? K[38] : K[31]; +assign K16[43] = decrypt_int ? K[16] : K[9]; +assign K16[44] = decrypt_int ? K[43] : K[36]; +assign K16[45] = decrypt_int ? K[44] : K[37]; +assign K16[46] = decrypt_int ? K[1] : K[49]; +assign K16[47] = decrypt_int ? K[7] : K[0]; +assign K16[48] = decrypt_int ? K[28] : K[21]; + +assign K15[1] = decrypt_int ? K[54] : K[33]; +assign K15[2] = decrypt_int ? K[18] : K[54]; +assign K15[3] = decrypt_int ? K[33] : K[12]; +assign K15[4] = decrypt_int ? K[10] : K[46]; +assign K15[5] = decrypt_int ? K[20] : K[24]; +assign K15[6] = decrypt_int ? K[48] : K[27]; +assign K15[7] = decrypt_int ? K[34] : K[13]; +assign K15[8] = decrypt_int ? K[13] : K[17]; +assign K15[9] = decrypt_int ? K[4] : K[40]; +assign K15[10] = decrypt_int ? K[55] : K[34]; +assign K15[11] = decrypt_int ? K[46] : K[25]; +assign K15[12] = decrypt_int ? K[26] : K[5]; +assign K15[13] = decrypt_int ? K[3] : K[39]; +assign K15[14] = decrypt_int ? K[32] : K[11]; +assign K15[15] = decrypt_int ? K[40] : K[19]; +assign K15[16] = decrypt_int ? K[41] : K[20]; +assign K15[17] = decrypt_int ? K[24] : K[3]; +assign K15[18] = decrypt_int ? K[12] : K[48]; +assign K15[19] = decrypt_int ? K[11] : K[47]; +assign K15[20] = decrypt_int ? K[5] : K[41]; +assign K15[21] = decrypt_int ? K[6] : K[10]; +assign K15[22] = decrypt_int ? K[39] : K[18]; +assign K15[23] = decrypt_int ? K[47] : K[26]; +assign K15[24] = decrypt_int ? K[27] : K[6]; +assign K15[25] = decrypt_int ? K[43] : K[22]; +assign K15[26] = decrypt_int ? K[38] : K[44]; +assign K15[27] = decrypt_int ? K[28] : K[7]; +assign K15[28] = decrypt_int ? K[15] : K[49]; +assign K15[29] = decrypt_int ? K[30] : K[9]; +assign K15[30] = decrypt_int ? K[0] : K[38]; +assign K15[31] = decrypt_int ? K[21] : K[0]; +assign K15[32] = decrypt_int ? K[36] : K[15]; +assign K15[33] = decrypt_int ? K[31] : K[37]; +assign K15[34] = decrypt_int ? K[16] : K[50]; +assign K15[35] = decrypt_int ? K[42] : K[21]; +assign K15[36] = decrypt_int ? K[37] : K[16]; +assign K15[37] = decrypt_int ? K[9] : K[43]; +assign K15[38] = decrypt_int ? K[44] : K[23]; +assign K15[39] = decrypt_int ? K[29] : K[8]; +assign K15[40] = decrypt_int ? K[7] : K[45]; +assign K15[41] = decrypt_int ? K[49] : K[28]; +assign K15[42] = decrypt_int ? K[45] : K[51]; +assign K15[43] = decrypt_int ? K[23] : K[2]; +assign K15[44] = decrypt_int ? K[50] : K[29]; +assign K15[45] = decrypt_int ? K[51] : K[30]; +assign K15[46] = decrypt_int ? K[8] : K[42]; +assign K15[47] = decrypt_int ? K[14] : K[52]; +assign K15[48] = decrypt_int ? K[35] : K[14]; + +assign K14[1] = decrypt_int ? K[11] : K[19]; +assign K14[2] = decrypt_int ? K[32] : K[40]; +assign K14[3] = decrypt_int ? K[47] : K[55]; +assign K14[4] = decrypt_int ? K[24] : K[32]; +assign K14[5] = decrypt_int ? K[34] : K[10]; +assign K14[6] = decrypt_int ? K[5] : K[13]; +assign K14[7] = decrypt_int ? K[48] : K[24]; +assign K14[8] = decrypt_int ? K[27] : K[3]; +assign K14[9] = decrypt_int ? K[18] : K[26]; +assign K14[10] = decrypt_int ? K[12] : K[20]; +assign K14[11] = decrypt_int ? K[3] : K[11]; +assign K14[12] = decrypt_int ? K[40] : K[48]; +assign K14[13] = decrypt_int ? K[17] : K[25]; +assign K14[14] = decrypt_int ? K[46] : K[54]; +assign K14[15] = decrypt_int ? K[54] : K[5]; +assign K14[16] = decrypt_int ? K[55] : K[6]; +assign K14[17] = decrypt_int ? K[13] : K[46]; +assign K14[18] = decrypt_int ? K[26] : K[34]; +assign K14[19] = decrypt_int ? K[25] : K[33]; +assign K14[20] = decrypt_int ? K[19] : K[27]; +assign K14[21] = decrypt_int ? K[20] : K[53]; +assign K14[22] = decrypt_int ? K[53] : K[4]; +assign K14[23] = decrypt_int ? K[4] : K[12]; +assign K14[24] = decrypt_int ? K[41] : K[17]; +assign K14[25] = decrypt_int ? K[2] : K[8]; +assign K14[26] = decrypt_int ? K[52] : K[30]; +assign K14[27] = decrypt_int ? K[42] : K[52]; +assign K14[28] = decrypt_int ? K[29] : K[35]; +assign K14[29] = decrypt_int ? K[44] : K[50]; +assign K14[30] = decrypt_int ? K[14] : K[51]; +assign K14[31] = decrypt_int ? K[35] : K[45]; +assign K14[32] = decrypt_int ? K[50] : K[1]; +assign K14[33] = decrypt_int ? K[45] : K[23]; +assign K14[34] = decrypt_int ? K[30] : K[36]; +assign K14[35] = decrypt_int ? K[1] : K[7]; +assign K14[36] = decrypt_int ? K[51] : K[2]; +assign K14[37] = decrypt_int ? K[23] : K[29]; +assign K14[38] = decrypt_int ? K[31] : K[9]; +assign K14[39] = decrypt_int ? K[43] : K[49]; +assign K14[40] = decrypt_int ? K[21] : K[31]; +assign K14[41] = decrypt_int ? K[8] : K[14]; +assign K14[42] = decrypt_int ? K[0] : K[37]; +assign K14[43] = decrypt_int ? K[37] : K[43]; +assign K14[44] = decrypt_int ? K[9] : K[15]; +assign K14[45] = decrypt_int ? K[38] : K[16]; +assign K14[46] = decrypt_int ? K[22] : K[28]; +assign K14[47] = decrypt_int ? K[28] : K[38]; +assign K14[48] = decrypt_int ? K[49] : K[0]; + +assign K13[1] = decrypt_int ? K[25] : K[5]; +assign K13[2] = decrypt_int ? K[46] : K[26]; +assign K13[3] = decrypt_int ? K[4] : K[41]; +assign K13[4] = decrypt_int ? K[13] : K[18]; +assign K13[5] = decrypt_int ? K[48] : K[53]; +assign K13[6] = decrypt_int ? K[19] : K[24]; +assign K13[7] = decrypt_int ? K[5] : K[10]; +assign K13[8] = decrypt_int ? K[41] : K[46]; +assign K13[9] = decrypt_int ? K[32] : K[12]; +assign K13[10] = decrypt_int ? K[26] : K[6]; +assign K13[11] = decrypt_int ? K[17] : K[54]; +assign K13[12] = decrypt_int ? K[54] : K[34]; +assign K13[13] = decrypt_int ? K[6] : K[11]; +assign K13[14] = decrypt_int ? K[3] : K[40]; +assign K13[15] = decrypt_int ? K[11] : K[48]; +assign K13[16] = decrypt_int ? K[12] : K[17]; +assign K13[17] = decrypt_int ? K[27] : K[32]; +assign K13[18] = decrypt_int ? K[40] : K[20]; +assign K13[19] = decrypt_int ? K[39] : K[19]; +assign K13[20] = decrypt_int ? K[33] : K[13]; +assign K13[21] = decrypt_int ? K[34] : K[39]; +assign K13[22] = decrypt_int ? K[10] : K[47]; +assign K13[23] = decrypt_int ? K[18] : K[55]; +assign K13[24] = decrypt_int ? K[55] : K[3]; +assign K13[25] = decrypt_int ? K[16] : K[49]; +assign K13[26] = decrypt_int ? K[7] : K[16]; +assign K13[27] = decrypt_int ? K[1] : K[38]; +assign K13[28] = decrypt_int ? K[43] : K[21]; +assign K13[29] = decrypt_int ? K[31] : K[36]; +assign K13[30] = decrypt_int ? K[28] : K[37]; +assign K13[31] = decrypt_int ? K[49] : K[31]; +assign K13[32] = decrypt_int ? K[9] : K[42]; +assign K13[33] = decrypt_int ? K[0] : K[9]; +assign K13[34] = decrypt_int ? K[44] : K[22]; +assign K13[35] = decrypt_int ? K[15] : K[52]; +assign K13[36] = decrypt_int ? K[38] : K[43]; +assign K13[37] = decrypt_int ? K[37] : K[15]; +assign K13[38] = decrypt_int ? K[45] : K[50]; +assign K13[39] = decrypt_int ? K[2] : K[35]; +assign K13[40] = decrypt_int ? K[35] : K[44]; +assign K13[41] = decrypt_int ? K[22] : K[0]; +assign K13[42] = decrypt_int ? K[14] : K[23]; +assign K13[43] = decrypt_int ? K[51] : K[29]; +assign K13[44] = decrypt_int ? K[23] : K[1]; +assign K13[45] = decrypt_int ? K[52] : K[2]; +assign K13[46] = decrypt_int ? K[36] : K[14]; +assign K13[47] = decrypt_int ? K[42] : K[51]; +assign K13[48] = decrypt_int ? K[8] : K[45]; + +assign K12[1] = decrypt_int ? K[39] : K[48]; +assign K12[2] = decrypt_int ? K[3] : K[12]; +assign K12[3] = decrypt_int ? K[18] : K[27]; +assign K12[4] = decrypt_int ? K[27] : K[4]; +assign K12[5] = decrypt_int ? K[5] : K[39]; +assign K12[6] = decrypt_int ? K[33] : K[10]; +assign K12[7] = decrypt_int ? K[19] : K[53]; +assign K12[8] = decrypt_int ? K[55] : K[32]; +assign K12[9] = decrypt_int ? K[46] : K[55]; +assign K12[10] = decrypt_int ? K[40] : K[17]; +assign K12[11] = decrypt_int ? K[6] : K[40]; +assign K12[12] = decrypt_int ? K[11] : K[20]; +assign K12[13] = decrypt_int ? K[20] : K[54]; +assign K12[14] = decrypt_int ? K[17] : K[26]; +assign K12[15] = decrypt_int ? K[25] : K[34]; +assign K12[16] = decrypt_int ? K[26] : K[3]; +assign K12[17] = decrypt_int ? K[41] : K[18]; +assign K12[18] = decrypt_int ? K[54] : K[6]; +assign K12[19] = decrypt_int ? K[53] : K[5]; +assign K12[20] = decrypt_int ? K[47] : K[24]; +assign K12[21] = decrypt_int ? K[48] : K[25]; +assign K12[22] = decrypt_int ? K[24] : K[33]; +assign K12[23] = decrypt_int ? K[32] : K[41]; +assign K12[24] = decrypt_int ? K[12] : K[46]; +assign K12[25] = decrypt_int ? K[30] : K[35]; +assign K12[26] = decrypt_int ? K[21] : K[2]; +assign K12[27] = decrypt_int ? K[15] : K[51]; +assign K12[28] = decrypt_int ? K[2] : K[7]; +assign K12[29] = decrypt_int ? K[45] : K[22]; +assign K12[30] = decrypt_int ? K[42] : K[23]; +assign K12[31] = decrypt_int ? K[8] : K[44]; +assign K12[32] = decrypt_int ? K[23] : K[28]; +assign K12[33] = decrypt_int ? K[14] : K[50]; +assign K12[34] = decrypt_int ? K[31] : K[8]; +assign K12[35] = decrypt_int ? K[29] : K[38]; +assign K12[36] = decrypt_int ? K[52] : K[29]; +assign K12[37] = decrypt_int ? K[51] : K[1]; +assign K12[38] = decrypt_int ? K[0] : K[36]; +assign K12[39] = decrypt_int ? K[16] : K[21]; +assign K12[40] = decrypt_int ? K[49] : K[30]; +assign K12[41] = decrypt_int ? K[36] : K[45]; +assign K12[42] = decrypt_int ? K[28] : K[9]; +assign K12[43] = decrypt_int ? K[38] : K[15]; +assign K12[44] = decrypt_int ? K[37] : K[42]; +assign K12[45] = decrypt_int ? K[7] : K[43]; +assign K12[46] = decrypt_int ? K[50] : K[0]; +assign K12[47] = decrypt_int ? K[1] : K[37]; +assign K12[48] = decrypt_int ? K[22] : K[31]; + +assign K11[1] = decrypt_int ? K[53] : K[34]; +assign K11[2] = decrypt_int ? K[17] : K[55]; +assign K11[3] = decrypt_int ? K[32] : K[13]; +assign K11[4] = decrypt_int ? K[41] : K[47]; +assign K11[5] = decrypt_int ? K[19] : K[25]; +assign K11[6] = decrypt_int ? K[47] : K[53]; +assign K11[7] = decrypt_int ? K[33] : K[39]; +assign K11[8] = decrypt_int ? K[12] : K[18]; +assign K11[9] = decrypt_int ? K[3] : K[41]; +assign K11[10] = decrypt_int ? K[54] : K[3]; +assign K11[11] = decrypt_int ? K[20] : K[26]; +assign K11[12] = decrypt_int ? K[25] : K[6]; +assign K11[13] = decrypt_int ? K[34] : K[40]; +assign K11[14] = decrypt_int ? K[6] : K[12]; +assign K11[15] = decrypt_int ? K[39] : K[20]; +assign K11[16] = decrypt_int ? K[40] : K[46]; +assign K11[17] = decrypt_int ? K[55] : K[4]; +assign K11[18] = decrypt_int ? K[11] : K[17]; +assign K11[19] = decrypt_int ? K[10] : K[48]; +assign K11[20] = decrypt_int ? K[4] : K[10]; +assign K11[21] = decrypt_int ? K[5] : K[11]; +assign K11[22] = decrypt_int ? K[13] : K[19]; +assign K11[23] = decrypt_int ? K[46] : K[27]; +assign K11[24] = decrypt_int ? K[26] : K[32]; +assign K11[25] = decrypt_int ? K[44] : K[21]; +assign K11[26] = decrypt_int ? K[35] : K[43]; +assign K11[27] = decrypt_int ? K[29] : K[37]; +assign K11[28] = decrypt_int ? K[16] : K[52]; +assign K11[29] = decrypt_int ? K[0] : K[8]; +assign K11[30] = decrypt_int ? K[1] : K[9]; +assign K11[31] = decrypt_int ? K[22] : K[30]; +assign K11[32] = decrypt_int ? K[37] : K[14]; +assign K11[33] = decrypt_int ? K[28] : K[36]; +assign K11[34] = decrypt_int ? K[45] : K[49]; +assign K11[35] = decrypt_int ? K[43] : K[51]; +assign K11[36] = decrypt_int ? K[7] : K[15]; +assign K11[37] = decrypt_int ? K[38] : K[42]; +assign K11[38] = decrypt_int ? K[14] : K[22]; +assign K11[39] = decrypt_int ? K[30] : K[7]; +assign K11[40] = decrypt_int ? K[8] : K[16]; +assign K11[41] = decrypt_int ? K[50] : K[31]; +assign K11[42] = decrypt_int ? K[42] : K[50]; +assign K11[43] = decrypt_int ? K[52] : K[1]; +assign K11[44] = decrypt_int ? K[51] : K[28]; +assign K11[45] = decrypt_int ? K[21] : K[29]; +assign K11[46] = decrypt_int ? K[9] : K[45]; +assign K11[47] = decrypt_int ? K[15] : K[23]; +assign K11[48] = decrypt_int ? K[36] : K[44]; + +assign K10[1] = decrypt_int ? K[10] : K[20]; +assign K10[2] = decrypt_int ? K[6] : K[41]; +assign K10[3] = decrypt_int ? K[46] : K[24]; +assign K10[4] = decrypt_int ? K[55] : K[33]; +assign K10[5] = decrypt_int ? K[33] : K[11]; +assign K10[6] = decrypt_int ? K[4] : K[39]; +assign K10[7] = decrypt_int ? K[47] : K[25]; +assign K10[8] = decrypt_int ? K[26] : K[4]; +assign K10[9] = decrypt_int ? K[17] : K[27]; +assign K10[10] = decrypt_int ? K[11] : K[46]; +assign K10[11] = decrypt_int ? K[34] : K[12]; +assign K10[12] = decrypt_int ? K[39] : K[17]; +assign K10[13] = decrypt_int ? K[48] : K[26]; +assign K10[14] = decrypt_int ? K[20] : K[55]; +assign K10[15] = decrypt_int ? K[53] : K[6]; +assign K10[16] = decrypt_int ? K[54] : K[32]; +assign K10[17] = decrypt_int ? K[12] : K[47]; +assign K10[18] = decrypt_int ? K[25] : K[3]; +assign K10[19] = decrypt_int ? K[24] : K[34]; +assign K10[20] = decrypt_int ? K[18] : K[53]; +assign K10[21] = decrypt_int ? K[19] : K[54]; +assign K10[22] = decrypt_int ? K[27] : K[5]; +assign K10[23] = decrypt_int ? K[3] : K[13]; +assign K10[24] = decrypt_int ? K[40] : K[18]; +assign K10[25] = decrypt_int ? K[31] : K[7]; +assign K10[26] = decrypt_int ? K[49] : K[29]; +assign K10[27] = decrypt_int ? K[43] : K[23]; +assign K10[28] = decrypt_int ? K[30] : K[38]; +assign K10[29] = decrypt_int ? K[14] : K[49]; +assign K10[30] = decrypt_int ? K[15] : K[50]; +assign K10[31] = decrypt_int ? K[36] : K[16]; +assign K10[32] = decrypt_int ? K[51] : K[0]; +assign K10[33] = decrypt_int ? K[42] : K[22]; +assign K10[34] = decrypt_int ? K[0] : K[35]; +assign K10[35] = decrypt_int ? K[2] : K[37]; +assign K10[36] = decrypt_int ? K[21] : K[1]; +assign K10[37] = decrypt_int ? K[52] : K[28]; +assign K10[38] = decrypt_int ? K[28] : K[8]; +assign K10[39] = decrypt_int ? K[44] : K[52]; +assign K10[40] = decrypt_int ? K[22] : K[2]; +assign K10[41] = decrypt_int ? K[9] : K[44]; +assign K10[42] = decrypt_int ? K[1] : K[36]; +assign K10[43] = decrypt_int ? K[7] : K[42]; +assign K10[44] = decrypt_int ? K[38] : K[14]; +assign K10[45] = decrypt_int ? K[35] : K[15]; +assign K10[46] = decrypt_int ? K[23] : K[31]; +assign K10[47] = decrypt_int ? K[29] : K[9]; +assign K10[48] = decrypt_int ? K[50] : K[30]; + +assign K9[1] = decrypt_int ? K[24] : K[6]; +assign K9[2] = decrypt_int ? K[20] : K[27]; +assign K9[3] = decrypt_int ? K[3] : K[10]; +assign K9[4] = decrypt_int ? K[12] : K[19]; +assign K9[5] = decrypt_int ? K[47] : K[54]; +assign K9[6] = decrypt_int ? K[18] : K[25]; +assign K9[7] = decrypt_int ? K[4] : K[11]; +assign K9[8] = decrypt_int ? K[40] : K[47]; +assign K9[9] = decrypt_int ? K[6] : K[13]; +assign K9[10] = decrypt_int ? K[25] : K[32]; +assign K9[11] = decrypt_int ? K[48] : K[55]; +assign K9[12] = decrypt_int ? K[53] : K[3]; +assign K9[13] = decrypt_int ? K[5] : K[12]; +assign K9[14] = decrypt_int ? K[34] : K[41]; +assign K9[15] = decrypt_int ? K[10] : K[17]; +assign K9[16] = decrypt_int ? K[11] : K[18]; +assign K9[17] = decrypt_int ? K[26] : K[33]; +assign K9[18] = decrypt_int ? K[39] : K[46]; +assign K9[19] = decrypt_int ? K[13] : K[20]; +assign K9[20] = decrypt_int ? K[32] : K[39]; +assign K9[21] = decrypt_int ? K[33] : K[40]; +assign K9[22] = decrypt_int ? K[41] : K[48]; +assign K9[23] = decrypt_int ? K[17] : K[24]; +assign K9[24] = decrypt_int ? K[54] : K[4]; +assign K9[25] = decrypt_int ? K[45] : K[52]; +assign K9[26] = decrypt_int ? K[8] : K[15]; +assign K9[27] = decrypt_int ? K[2] : K[9]; +assign K9[28] = decrypt_int ? K[44] : K[51]; +assign K9[29] = decrypt_int ? K[28] : K[35]; +assign K9[30] = decrypt_int ? K[29] : K[36]; +assign K9[31] = decrypt_int ? K[50] : K[2]; +assign K9[32] = decrypt_int ? K[38] : K[45]; +assign K9[33] = decrypt_int ? K[1] : K[8]; +assign K9[34] = decrypt_int ? K[14] : K[21]; +assign K9[35] = decrypt_int ? K[16] : K[23]; +assign K9[36] = decrypt_int ? K[35] : K[42]; +assign K9[37] = decrypt_int ? K[7] : K[14]; +assign K9[38] = decrypt_int ? K[42] : K[49]; +assign K9[39] = decrypt_int ? K[31] : K[38]; +assign K9[40] = decrypt_int ? K[36] : K[43]; +assign K9[41] = decrypt_int ? K[23] : K[30]; +assign K9[42] = decrypt_int ? K[15] : K[22]; +assign K9[43] = decrypt_int ? K[21] : K[28]; +assign K9[44] = decrypt_int ? K[52] : K[0]; +assign K9[45] = decrypt_int ? K[49] : K[1]; +assign K9[46] = decrypt_int ? K[37] : K[44]; +assign K9[47] = decrypt_int ? K[43] : K[50]; +assign K9[48] = decrypt_int ? K[9] : K[16]; + +assign K8[1] = decrypt_int ? K[6] : K[24]; +assign K8[2] = decrypt_int ? K[27] : K[20]; +assign K8[3] = decrypt_int ? K[10] : K[3]; +assign K8[4] = decrypt_int ? K[19] : K[12]; +assign K8[5] = decrypt_int ? K[54] : K[47]; +assign K8[6] = decrypt_int ? K[25] : K[18]; +assign K8[7] = decrypt_int ? K[11] : K[4]; +assign K8[8] = decrypt_int ? K[47] : K[40]; +assign K8[9] = decrypt_int ? K[13] : K[6]; +assign K8[10] = decrypt_int ? K[32] : K[25]; +assign K8[11] = decrypt_int ? K[55] : K[48]; +assign K8[12] = decrypt_int ? K[3] : K[53]; +assign K8[13] = decrypt_int ? K[12] : K[5]; +assign K8[14] = decrypt_int ? K[41] : K[34]; +assign K8[15] = decrypt_int ? K[17] : K[10]; +assign K8[16] = decrypt_int ? K[18] : K[11]; +assign K8[17] = decrypt_int ? K[33] : K[26]; +assign K8[18] = decrypt_int ? K[46] : K[39]; +assign K8[19] = decrypt_int ? K[20] : K[13]; +assign K8[20] = decrypt_int ? K[39] : K[32]; +assign K8[21] = decrypt_int ? K[40] : K[33]; +assign K8[22] = decrypt_int ? K[48] : K[41]; +assign K8[23] = decrypt_int ? K[24] : K[17]; +assign K8[24] = decrypt_int ? K[4] : K[54]; +assign K8[25] = decrypt_int ? K[52] : K[45]; +assign K8[26] = decrypt_int ? K[15] : K[8]; +assign K8[27] = decrypt_int ? K[9] : K[2]; +assign K8[28] = decrypt_int ? K[51] : K[44]; +assign K8[29] = decrypt_int ? K[35] : K[28]; +assign K8[30] = decrypt_int ? K[36] : K[29]; +assign K8[31] = decrypt_int ? K[2] : K[50]; +assign K8[32] = decrypt_int ? K[45] : K[38]; +assign K8[33] = decrypt_int ? K[8] : K[1]; +assign K8[34] = decrypt_int ? K[21] : K[14]; +assign K8[35] = decrypt_int ? K[23] : K[16]; +assign K8[36] = decrypt_int ? K[42] : K[35]; +assign K8[37] = decrypt_int ? K[14] : K[7]; +assign K8[38] = decrypt_int ? K[49] : K[42]; +assign K8[39] = decrypt_int ? K[38] : K[31]; +assign K8[40] = decrypt_int ? K[43] : K[36]; +assign K8[41] = decrypt_int ? K[30] : K[23]; +assign K8[42] = decrypt_int ? K[22] : K[15]; +assign K8[43] = decrypt_int ? K[28] : K[21]; +assign K8[44] = decrypt_int ? K[0] : K[52]; +assign K8[45] = decrypt_int ? K[1] : K[49]; +assign K8[46] = decrypt_int ? K[44] : K[37]; +assign K8[47] = decrypt_int ? K[50] : K[43]; +assign K8[48] = decrypt_int ? K[16] : K[9]; + +assign K7[1] = decrypt_int ? K[20] : K[10]; +assign K7[2] = decrypt_int ? K[41] : K[6]; +assign K7[3] = decrypt_int ? K[24] : K[46]; +assign K7[4] = decrypt_int ? K[33] : K[55]; +assign K7[5] = decrypt_int ? K[11] : K[33]; +assign K7[6] = decrypt_int ? K[39] : K[4]; +assign K7[7] = decrypt_int ? K[25] : K[47]; +assign K7[8] = decrypt_int ? K[4] : K[26]; +assign K7[9] = decrypt_int ? K[27] : K[17]; +assign K7[10] = decrypt_int ? K[46] : K[11]; +assign K7[11] = decrypt_int ? K[12] : K[34]; +assign K7[12] = decrypt_int ? K[17] : K[39]; +assign K7[13] = decrypt_int ? K[26] : K[48]; +assign K7[14] = decrypt_int ? K[55] : K[20]; +assign K7[15] = decrypt_int ? K[6] : K[53]; +assign K7[16] = decrypt_int ? K[32] : K[54]; +assign K7[17] = decrypt_int ? K[47] : K[12]; +assign K7[18] = decrypt_int ? K[3] : K[25]; +assign K7[19] = decrypt_int ? K[34] : K[24]; +assign K7[20] = decrypt_int ? K[53] : K[18]; +assign K7[21] = decrypt_int ? K[54] : K[19]; +assign K7[22] = decrypt_int ? K[5] : K[27]; +assign K7[23] = decrypt_int ? K[13] : K[3]; +assign K7[24] = decrypt_int ? K[18] : K[40]; +assign K7[25] = decrypt_int ? K[7] : K[31]; +assign K7[26] = decrypt_int ? K[29] : K[49]; +assign K7[27] = decrypt_int ? K[23] : K[43]; +assign K7[28] = decrypt_int ? K[38] : K[30]; +assign K7[29] = decrypt_int ? K[49] : K[14]; +assign K7[30] = decrypt_int ? K[50] : K[15]; +assign K7[31] = decrypt_int ? K[16] : K[36]; +assign K7[32] = decrypt_int ? K[0] : K[51]; +assign K7[33] = decrypt_int ? K[22] : K[42]; +assign K7[34] = decrypt_int ? K[35] : K[0]; +assign K7[35] = decrypt_int ? K[37] : K[2]; +assign K7[36] = decrypt_int ? K[1] : K[21]; +assign K7[37] = decrypt_int ? K[28] : K[52]; +assign K7[38] = decrypt_int ? K[8] : K[28]; +assign K7[39] = decrypt_int ? K[52] : K[44]; +assign K7[40] = decrypt_int ? K[2] : K[22]; +assign K7[41] = decrypt_int ? K[44] : K[9]; +assign K7[42] = decrypt_int ? K[36] : K[1]; +assign K7[43] = decrypt_int ? K[42] : K[7]; +assign K7[44] = decrypt_int ? K[14] : K[38]; +assign K7[45] = decrypt_int ? K[15] : K[35]; +assign K7[46] = decrypt_int ? K[31] : K[23]; +assign K7[47] = decrypt_int ? K[9] : K[29]; +assign K7[48] = decrypt_int ? K[30] : K[50]; + +assign K6[1] = decrypt_int ? K[34] : K[53]; +assign K6[2] = decrypt_int ? K[55] : K[17]; +assign K6[3] = decrypt_int ? K[13] : K[32]; +assign K6[4] = decrypt_int ? K[47] : K[41]; +assign K6[5] = decrypt_int ? K[25] : K[19]; +assign K6[6] = decrypt_int ? K[53] : K[47]; +assign K6[7] = decrypt_int ? K[39] : K[33]; +assign K6[8] = decrypt_int ? K[18] : K[12]; +assign K6[9] = decrypt_int ? K[41] : K[3]; +assign K6[10] = decrypt_int ? K[3] : K[54]; +assign K6[11] = decrypt_int ? K[26] : K[20]; +assign K6[12] = decrypt_int ? K[6] : K[25]; +assign K6[13] = decrypt_int ? K[40] : K[34]; +assign K6[14] = decrypt_int ? K[12] : K[6]; +assign K6[15] = decrypt_int ? K[20] : K[39]; +assign K6[16] = decrypt_int ? K[46] : K[40]; +assign K6[17] = decrypt_int ? K[4] : K[55]; +assign K6[18] = decrypt_int ? K[17] : K[11]; +assign K6[19] = decrypt_int ? K[48] : K[10]; +assign K6[20] = decrypt_int ? K[10] : K[4]; +assign K6[21] = decrypt_int ? K[11] : K[5]; +assign K6[22] = decrypt_int ? K[19] : K[13]; +assign K6[23] = decrypt_int ? K[27] : K[46]; +assign K6[24] = decrypt_int ? K[32] : K[26]; +assign K6[25] = decrypt_int ? K[21] : K[44]; +assign K6[26] = decrypt_int ? K[43] : K[35]; +assign K6[27] = decrypt_int ? K[37] : K[29]; +assign K6[28] = decrypt_int ? K[52] : K[16]; +assign K6[29] = decrypt_int ? K[8] : K[0]; +assign K6[30] = decrypt_int ? K[9] : K[1]; +assign K6[31] = decrypt_int ? K[30] : K[22]; +assign K6[32] = decrypt_int ? K[14] : K[37]; +assign K6[33] = decrypt_int ? K[36] : K[28]; +assign K6[34] = decrypt_int ? K[49] : K[45]; +assign K6[35] = decrypt_int ? K[51] : K[43]; +assign K6[36] = decrypt_int ? K[15] : K[7]; +assign K6[37] = decrypt_int ? K[42] : K[38]; +assign K6[38] = decrypt_int ? K[22] : K[14]; +assign K6[39] = decrypt_int ? K[7] : K[30]; +assign K6[40] = decrypt_int ? K[16] : K[8]; +assign K6[41] = decrypt_int ? K[31] : K[50]; +assign K6[42] = decrypt_int ? K[50] : K[42]; +assign K6[43] = decrypt_int ? K[1] : K[52]; +assign K6[44] = decrypt_int ? K[28] : K[51]; +assign K6[45] = decrypt_int ? K[29] : K[21]; +assign K6[46] = decrypt_int ? K[45] : K[9]; +assign K6[47] = decrypt_int ? K[23] : K[15]; +assign K6[48] = decrypt_int ? K[44] : K[36]; + +assign K5[1] = decrypt_int ? K[48] : K[39]; +assign K5[2] = decrypt_int ? K[12] : K[3]; +assign K5[3] = decrypt_int ? K[27] : K[18]; +assign K5[4] = decrypt_int ? K[4] : K[27]; +assign K5[5] = decrypt_int ? K[39] : K[5]; +assign K5[6] = decrypt_int ? K[10] : K[33]; +assign K5[7] = decrypt_int ? K[53] : K[19]; +assign K5[8] = decrypt_int ? K[32] : K[55]; +assign K5[9] = decrypt_int ? K[55] : K[46]; +assign K5[10] = decrypt_int ? K[17] : K[40]; +assign K5[11] = decrypt_int ? K[40] : K[6]; +assign K5[12] = decrypt_int ? K[20] : K[11]; +assign K5[13] = decrypt_int ? K[54] : K[20]; +assign K5[14] = decrypt_int ? K[26] : K[17]; +assign K5[15] = decrypt_int ? K[34] : K[25]; +assign K5[16] = decrypt_int ? K[3] : K[26]; +assign K5[17] = decrypt_int ? K[18] : K[41]; +assign K5[18] = decrypt_int ? K[6] : K[54]; +assign K5[19] = decrypt_int ? K[5] : K[53]; +assign K5[20] = decrypt_int ? K[24] : K[47]; +assign K5[21] = decrypt_int ? K[25] : K[48]; +assign K5[22] = decrypt_int ? K[33] : K[24]; +assign K5[23] = decrypt_int ? K[41] : K[32]; +assign K5[24] = decrypt_int ? K[46] : K[12]; +assign K5[25] = decrypt_int ? K[35] : K[30]; +assign K5[26] = decrypt_int ? K[2] : K[21]; +assign K5[27] = decrypt_int ? K[51] : K[15]; +assign K5[28] = decrypt_int ? K[7] : K[2]; +assign K5[29] = decrypt_int ? K[22] : K[45]; +assign K5[30] = decrypt_int ? K[23] : K[42]; +assign K5[31] = decrypt_int ? K[44] : K[8]; +assign K5[32] = decrypt_int ? K[28] : K[23]; +assign K5[33] = decrypt_int ? K[50] : K[14]; +assign K5[34] = decrypt_int ? K[8] : K[31]; +assign K5[35] = decrypt_int ? K[38] : K[29]; +assign K5[36] = decrypt_int ? K[29] : K[52]; +assign K5[37] = decrypt_int ? K[1] : K[51]; +assign K5[38] = decrypt_int ? K[36] : K[0]; +assign K5[39] = decrypt_int ? K[21] : K[16]; +assign K5[40] = decrypt_int ? K[30] : K[49]; +assign K5[41] = decrypt_int ? K[45] : K[36]; +assign K5[42] = decrypt_int ? K[9] : K[28]; +assign K5[43] = decrypt_int ? K[15] : K[38]; +assign K5[44] = decrypt_int ? K[42] : K[37]; +assign K5[45] = decrypt_int ? K[43] : K[7]; +assign K5[46] = decrypt_int ? K[0] : K[50]; +assign K5[47] = decrypt_int ? K[37] : K[1]; +assign K5[48] = decrypt_int ? K[31] : K[22]; + +assign K4[1] = decrypt_int ? K[5] : K[25]; +assign K4[2] = decrypt_int ? K[26] : K[46]; +assign K4[3] = decrypt_int ? K[41] : K[4]; +assign K4[4] = decrypt_int ? K[18] : K[13]; +assign K4[5] = decrypt_int ? K[53] : K[48]; +assign K4[6] = decrypt_int ? K[24] : K[19]; +assign K4[7] = decrypt_int ? K[10] : K[5]; +assign K4[8] = decrypt_int ? K[46] : K[41]; +assign K4[9] = decrypt_int ? K[12] : K[32]; +assign K4[10] = decrypt_int ? K[6] : K[26]; +assign K4[11] = decrypt_int ? K[54] : K[17]; +assign K4[12] = decrypt_int ? K[34] : K[54]; +assign K4[13] = decrypt_int ? K[11] : K[6]; +assign K4[14] = decrypt_int ? K[40] : K[3]; +assign K4[15] = decrypt_int ? K[48] : K[11]; +assign K4[16] = decrypt_int ? K[17] : K[12]; +assign K4[17] = decrypt_int ? K[32] : K[27]; +assign K4[18] = decrypt_int ? K[20] : K[40]; +assign K4[19] = decrypt_int ? K[19] : K[39]; +assign K4[20] = decrypt_int ? K[13] : K[33]; +assign K4[21] = decrypt_int ? K[39] : K[34]; +assign K4[22] = decrypt_int ? K[47] : K[10]; +assign K4[23] = decrypt_int ? K[55] : K[18]; +assign K4[24] = decrypt_int ? K[3] : K[55]; +assign K4[25] = decrypt_int ? K[49] : K[16]; +assign K4[26] = decrypt_int ? K[16] : K[7]; +assign K4[27] = decrypt_int ? K[38] : K[1]; +assign K4[28] = decrypt_int ? K[21] : K[43]; +assign K4[29] = decrypt_int ? K[36] : K[31]; +assign K4[30] = decrypt_int ? K[37] : K[28]; +assign K4[31] = decrypt_int ? K[31] : K[49]; +assign K4[32] = decrypt_int ? K[42] : K[9]; +assign K4[33] = decrypt_int ? K[9] : K[0]; +assign K4[34] = decrypt_int ? K[22] : K[44]; +assign K4[35] = decrypt_int ? K[52] : K[15]; +assign K4[36] = decrypt_int ? K[43] : K[38]; +assign K4[37] = decrypt_int ? K[15] : K[37]; +assign K4[38] = decrypt_int ? K[50] : K[45]; +assign K4[39] = decrypt_int ? K[35] : K[2]; +assign K4[40] = decrypt_int ? K[44] : K[35]; +assign K4[41] = decrypt_int ? K[0] : K[22]; +assign K4[42] = decrypt_int ? K[23] : K[14]; +assign K4[43] = decrypt_int ? K[29] : K[51]; +assign K4[44] = decrypt_int ? K[1] : K[23]; +assign K4[45] = decrypt_int ? K[2] : K[52]; +assign K4[46] = decrypt_int ? K[14] : K[36]; +assign K4[47] = decrypt_int ? K[51] : K[42]; +assign K4[48] = decrypt_int ? K[45] : K[8]; + +assign K3[1] = decrypt_int ? K[19] : K[11]; +assign K3[2] = decrypt_int ? K[40] : K[32]; +assign K3[3] = decrypt_int ? K[55] : K[47]; +assign K3[4] = decrypt_int ? K[32] : K[24]; +assign K3[5] = decrypt_int ? K[10] : K[34]; +assign K3[6] = decrypt_int ? K[13] : K[5]; +assign K3[7] = decrypt_int ? K[24] : K[48]; +assign K3[8] = decrypt_int ? K[3] : K[27]; +assign K3[9] = decrypt_int ? K[26] : K[18]; +assign K3[10] = decrypt_int ? K[20] : K[12]; +assign K3[11] = decrypt_int ? K[11] : K[3]; +assign K3[12] = decrypt_int ? K[48] : K[40]; +assign K3[13] = decrypt_int ? K[25] : K[17]; +assign K3[14] = decrypt_int ? K[54] : K[46]; +assign K3[15] = decrypt_int ? K[5] : K[54]; +assign K3[16] = decrypt_int ? K[6] : K[55]; +assign K3[17] = decrypt_int ? K[46] : K[13]; +assign K3[18] = decrypt_int ? K[34] : K[26]; +assign K3[19] = decrypt_int ? K[33] : K[25]; +assign K3[20] = decrypt_int ? K[27] : K[19]; +assign K3[21] = decrypt_int ? K[53] : K[20]; +assign K3[22] = decrypt_int ? K[4] : K[53]; +assign K3[23] = decrypt_int ? K[12] : K[4]; +assign K3[24] = decrypt_int ? K[17] : K[41]; +assign K3[25] = decrypt_int ? K[8] : K[2]; +assign K3[26] = decrypt_int ? K[30] : K[52]; +assign K3[27] = decrypt_int ? K[52] : K[42]; +assign K3[28] = decrypt_int ? K[35] : K[29]; +assign K3[29] = decrypt_int ? K[50] : K[44]; +assign K3[30] = decrypt_int ? K[51] : K[14]; +assign K3[31] = decrypt_int ? K[45] : K[35]; +assign K3[32] = decrypt_int ? K[1] : K[50]; +assign K3[33] = decrypt_int ? K[23] : K[45]; +assign K3[34] = decrypt_int ? K[36] : K[30]; +assign K3[35] = decrypt_int ? K[7] : K[1]; +assign K3[36] = decrypt_int ? K[2] : K[51]; +assign K3[37] = decrypt_int ? K[29] : K[23]; +assign K3[38] = decrypt_int ? K[9] : K[31]; +assign K3[39] = decrypt_int ? K[49] : K[43]; +assign K3[40] = decrypt_int ? K[31] : K[21]; +assign K3[41] = decrypt_int ? K[14] : K[8]; +assign K3[42] = decrypt_int ? K[37] : K[0]; +assign K3[43] = decrypt_int ? K[43] : K[37]; +assign K3[44] = decrypt_int ? K[15] : K[9]; +assign K3[45] = decrypt_int ? K[16] : K[38]; +assign K3[46] = decrypt_int ? K[28] : K[22]; +assign K3[47] = decrypt_int ? K[38] : K[28]; +assign K3[48] = decrypt_int ? K[0] : K[49]; + +assign K2[1] = decrypt_int ? K[33] : K[54]; +assign K2[2] = decrypt_int ? K[54] : K[18]; +assign K2[3] = decrypt_int ? K[12] : K[33]; +assign K2[4] = decrypt_int ? K[46] : K[10]; +assign K2[5] = decrypt_int ? K[24] : K[20]; +assign K2[6] = decrypt_int ? K[27] : K[48]; +assign K2[7] = decrypt_int ? K[13] : K[34]; +assign K2[8] = decrypt_int ? K[17] : K[13]; +assign K2[9] = decrypt_int ? K[40] : K[4]; +assign K2[10] = decrypt_int ? K[34] : K[55]; +assign K2[11] = decrypt_int ? K[25] : K[46]; +assign K2[12] = decrypt_int ? K[5] : K[26]; +assign K2[13] = decrypt_int ? K[39] : K[3]; +assign K2[14] = decrypt_int ? K[11] : K[32]; +assign K2[15] = decrypt_int ? K[19] : K[40]; +assign K2[16] = decrypt_int ? K[20] : K[41]; +assign K2[17] = decrypt_int ? K[3] : K[24]; +assign K2[18] = decrypt_int ? K[48] : K[12]; +assign K2[19] = decrypt_int ? K[47] : K[11]; +assign K2[20] = decrypt_int ? K[41] : K[5]; +assign K2[21] = decrypt_int ? K[10] : K[6]; +assign K2[22] = decrypt_int ? K[18] : K[39]; +assign K2[23] = decrypt_int ? K[26] : K[47]; +assign K2[24] = decrypt_int ? K[6] : K[27]; +assign K2[25] = decrypt_int ? K[22] : K[43]; +assign K2[26] = decrypt_int ? K[44] : K[38]; +assign K2[27] = decrypt_int ? K[7] : K[28]; +assign K2[28] = decrypt_int ? K[49] : K[15]; +assign K2[29] = decrypt_int ? K[9] : K[30]; +assign K2[30] = decrypt_int ? K[38] : K[0]; +assign K2[31] = decrypt_int ? K[0] : K[21]; +assign K2[32] = decrypt_int ? K[15] : K[36]; +assign K2[33] = decrypt_int ? K[37] : K[31]; +assign K2[34] = decrypt_int ? K[50] : K[16]; +assign K2[35] = decrypt_int ? K[21] : K[42]; +assign K2[36] = decrypt_int ? K[16] : K[37]; +assign K2[37] = decrypt_int ? K[43] : K[9]; +assign K2[38] = decrypt_int ? K[23] : K[44]; +assign K2[39] = decrypt_int ? K[8] : K[29]; +assign K2[40] = decrypt_int ? K[45] : K[7]; +assign K2[41] = decrypt_int ? K[28] : K[49]; +assign K2[42] = decrypt_int ? K[51] : K[45]; +assign K2[43] = decrypt_int ? K[2] : K[23]; +assign K2[44] = decrypt_int ? K[29] : K[50]; +assign K2[45] = decrypt_int ? K[30] : K[51]; +assign K2[46] = decrypt_int ? K[42] : K[8]; +assign K2[47] = decrypt_int ? K[52] : K[14]; +assign K2[48] = decrypt_int ? K[14] : K[35]; + +assign K1[1] = decrypt_int ? K[40] : K[47]; +assign K1[2] = decrypt_int ? K[4] : K[11]; +assign K1[3] = decrypt_int ? K[19] : K[26]; +assign K1[4] = decrypt_int ? K[53] : K[3]; +assign K1[5] = decrypt_int ? K[6] : K[13]; +assign K1[6] = decrypt_int ? K[34] : K[41]; +assign K1[7] = decrypt_int ? K[20] : K[27]; +assign K1[8] = decrypt_int ? K[24] : K[6]; +assign K1[9] = decrypt_int ? K[47] : K[54]; +assign K1[10] = decrypt_int ? K[41] : K[48]; +assign K1[11] = decrypt_int ? K[32] : K[39]; +assign K1[12] = decrypt_int ? K[12] : K[19]; +assign K1[13] = decrypt_int ? K[46] : K[53]; +assign K1[14] = decrypt_int ? K[18] : K[25]; +assign K1[15] = decrypt_int ? K[26] : K[33]; +assign K1[16] = decrypt_int ? K[27] : K[34]; +assign K1[17] = decrypt_int ? K[10] : K[17]; +assign K1[18] = decrypt_int ? K[55] : K[5]; +assign K1[19] = decrypt_int ? K[54] : K[4]; +assign K1[20] = decrypt_int ? K[48] : K[55]; +assign K1[21] = decrypt_int ? K[17] : K[24]; +assign K1[22] = decrypt_int ? K[25] : K[32]; +assign K1[23] = decrypt_int ? K[33] : K[40]; +assign K1[24] = decrypt_int ? K[13] : K[20]; +assign K1[25] = decrypt_int ? K[29] : K[36]; +assign K1[26] = decrypt_int ? K[51] : K[31]; +assign K1[27] = decrypt_int ? K[14] : K[21]; +assign K1[28] = decrypt_int ? K[1] : K[8]; +assign K1[29] = decrypt_int ? K[16] : K[23]; +assign K1[30] = decrypt_int ? K[45] : K[52]; +assign K1[31] = decrypt_int ? K[7] : K[14]; +assign K1[32] = decrypt_int ? K[22] : K[29]; +assign K1[33] = decrypt_int ? K[44] : K[51]; +assign K1[34] = decrypt_int ? K[2] : K[9]; +assign K1[35] = decrypt_int ? K[28] : K[35]; +assign K1[36] = decrypt_int ? K[23] : K[30]; +assign K1[37] = decrypt_int ? K[50] : K[2]; +assign K1[38] = decrypt_int ? K[30] : K[37]; +assign K1[39] = decrypt_int ? K[15] : K[22]; +assign K1[40] = decrypt_int ? K[52] : K[0]; +assign K1[41] = decrypt_int ? K[35] : K[42]; +assign K1[42] = decrypt_int ? K[31] : K[38]; +assign K1[43] = decrypt_int ? K[9] : K[16]; +assign K1[44] = decrypt_int ? K[36] : K[43]; +assign K1[45] = decrypt_int ? K[37] : K[44]; +assign K1[46] = decrypt_int ? K[49] : K[1]; +assign K1[47] = decrypt_int ? K[0] : K[7]; +assign K1[48] = decrypt_int ? K[21] : K[28]; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox1.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox1.v new file mode 100644 index 000000000..76d5e22f6 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox1.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox1(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 14; + 1: dout = 4; + 2: dout = 13; + 3: dout = 1; + 4: dout = 2; + 5: dout = 15; + 6: dout = 11; + 7: dout = 8; + 8: dout = 3; + 9: dout = 10; + 10: dout = 6; + 11: dout = 12; + 12: dout = 5; + 13: dout = 9; + 14: dout = 0; + 15: dout = 7; + + 16: dout = 0; + 17: dout = 15; + 18: dout = 7; + 19: dout = 4; + 20: dout = 14; + 21: dout = 2; + 22: dout = 13; + 23: dout = 1; + 24: dout = 10; + 25: dout = 6; + 26: dout = 12; + 27: dout = 11; + 28: dout = 9; + 29: dout = 5; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 4; + 33: dout = 1; + 34: dout = 14; + 35: dout = 8; + 36: dout = 13; + 37: dout = 6; + 38: dout = 2; + 39: dout = 11; + 40: dout = 15; + 41: dout = 12; + 42: dout = 9; + 43: dout = 7; + 44: dout = 3; + 45: dout = 10; + 46: dout = 5; + 47: dout = 0; + + 48: dout = 15; + 49: dout = 12; + 50: dout = 8; + 51: dout = 2; + 52: dout = 4; + 53: dout = 9; + 54: dout = 1; + 55: dout = 7; + 56: dout = 5; + 57: dout = 11; + 58: dout = 3; + 59: dout = 14; + 60: dout = 10; + 61: dout = 0; + 62: dout = 6; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox2.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox2.v new file mode 100644 index 000000000..aa505f3a2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox2.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox2(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 15; + 1: dout = 1; + 2: dout = 8; + 3: dout = 14; + 4: dout = 6; + 5: dout = 11; + 6: dout = 3; + 7: dout = 4; + 8: dout = 9; + 9: dout = 7; + 10: dout = 2; + 11: dout = 13; + 12: dout = 12; + 13: dout = 0; + 14: dout = 5; + 15: dout = 10; + + 16: dout = 3; + 17: dout = 13; + 18: dout = 4; + 19: dout = 7; + 20: dout = 15; + 21: dout = 2; + 22: dout = 8; + 23: dout = 14; + 24: dout = 12; + 25: dout = 0; + 26: dout = 1; + 27: dout = 10; + 28: dout = 6; + 29: dout = 9; + 30: dout = 11; + 31: dout = 5; + + 32: dout = 0; + 33: dout = 14; + 34: dout = 7; + 35: dout = 11; + 36: dout = 10; + 37: dout = 4; + 38: dout = 13; + 39: dout = 1; + 40: dout = 5; + 41: dout = 8; + 42: dout = 12; + 43: dout = 6; + 44: dout = 9; + 45: dout = 3; + 46: dout = 2; + 47: dout = 15; + + 48: dout = 13; + 49: dout = 8; + 50: dout = 10; + 51: dout = 1; + 52: dout = 3; + 53: dout = 15; + 54: dout = 4; + 55: dout = 2; + 56: dout = 11; + 57: dout = 6; + 58: dout = 7; + 59: dout = 12; + 60: dout = 0; + 61: dout = 5; + 62: dout = 14; + 63: dout = 9; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox3.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox3.v new file mode 100644 index 000000000..0c6cddf03 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox3.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox3(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 10; + 1: dout = 0; + 2: dout = 9; + 3: dout = 14; + 4: dout = 6; + 5: dout = 3; + 6: dout = 15; + 7: dout = 5; + 8: dout = 1; + 9: dout = 13; + 10: dout = 12; + 11: dout = 7; + 12: dout = 11; + 13: dout = 4; + 14: dout = 2; + 15: dout = 8; + + 16: dout = 13; + 17: dout = 7; + 18: dout = 0; + 19: dout = 9; + 20: dout = 3; + 21: dout = 4; + 22: dout = 6; + 23: dout = 10; + 24: dout = 2; + 25: dout = 8; + 26: dout = 5; + 27: dout = 14; + 28: dout = 12; + 29: dout = 11; + 30: dout = 15; + 31: dout = 1; + + 32: dout = 13; + 33: dout = 6; + 34: dout = 4; + 35: dout = 9; + 36: dout = 8; + 37: dout = 15; + 38: dout = 3; + 39: dout = 0; + 40: dout = 11; + 41: dout = 1; + 42: dout = 2; + 43: dout = 12; + 44: dout = 5; + 45: dout = 10; + 46: dout = 14; + 47: dout = 7; + + 48: dout = 1; + 49: dout = 10; + 50: dout = 13; + 51: dout = 0; + 52: dout = 6; + 53: dout = 9; + 54: dout = 8; + 55: dout = 7; + 56: dout = 4; + 57: dout = 15; + 58: dout = 14; + 59: dout = 3; + 60: dout = 11; + 61: dout = 5; + 62: dout = 2; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox4.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox4.v new file mode 100644 index 000000000..ec531c1e8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox4.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox4(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 7; + 1: dout = 13; + 2: dout = 14; + 3: dout = 3; + 4: dout = 0; + 5: dout = 6; + 6: dout = 9; + 7: dout = 10; + 8: dout = 1; + 9: dout = 2; + 10: dout = 8; + 11: dout = 5; + 12: dout = 11; + 13: dout = 12; + 14: dout = 4; + 15: dout = 15; + + 16: dout = 13; + 17: dout = 8; + 18: dout = 11; + 19: dout = 5; + 20: dout = 6; + 21: dout = 15; + 22: dout = 0; + 23: dout = 3; + 24: dout = 4; + 25: dout = 7; + 26: dout = 2; + 27: dout = 12; + 28: dout = 1; + 29: dout = 10; + 30: dout = 14; + 31: dout = 9; + + 32: dout = 10; + 33: dout = 6; + 34: dout = 9; + 35: dout = 0; + 36: dout = 12; + 37: dout = 11; + 38: dout = 7; + 39: dout = 13; + 40: dout = 15; + 41: dout = 1; + 42: dout = 3; + 43: dout = 14; + 44: dout = 5; + 45: dout = 2; + 46: dout = 8; + 47: dout = 4; + + 48: dout = 3; + 49: dout = 15; + 50: dout = 0; + 51: dout = 6; + 52: dout = 10; + 53: dout = 1; + 54: dout = 13; + 55: dout = 8; + 56: dout = 9; + 57: dout = 4; + 58: dout = 5; + 59: dout = 11; + 60: dout = 12; + 61: dout = 7; + 62: dout = 2; + 63: dout = 14; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox5.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox5.v new file mode 100644 index 000000000..f874c25cc --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox5.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox5(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 2; + 1: dout = 12; + 2: dout = 4; + 3: dout = 1; + 4: dout = 7; + 5: dout = 10; + 6: dout = 11; + 7: dout = 6; + 8: dout = 8; + 9: dout = 5; + 10: dout = 3; + 11: dout = 15; + 12: dout = 13; + 13: dout = 0; + 14: dout = 14; + 15: dout = 9; + + 16: dout = 14; + 17: dout = 11; + 18: dout = 2; + 19: dout = 12; + 20: dout = 4; + 21: dout = 7; + 22: dout = 13; + 23: dout = 1; + 24: dout = 5; + 25: dout = 0; + 26: dout = 15; + 27: dout = 10; + 28: dout = 3; + 29: dout = 9; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 4; + 33: dout = 2; + 34: dout = 1; + 35: dout = 11; + 36: dout = 10; + 37: dout = 13; + 38: dout = 7; + 39: dout = 8; + 40: dout = 15; + 41: dout = 9; + 42: dout = 12; + 43: dout = 5; + 44: dout = 6; + 45: dout = 3; + 46: dout = 0; + 47: dout = 14; + + 48: dout = 11; + 49: dout = 8; + 50: dout = 12; + 51: dout = 7; + 52: dout = 1; + 53: dout = 14; + 54: dout = 2; + 55: dout = 13; + 56: dout = 6; + 57: dout = 15; + 58: dout = 0; + 59: dout = 9; + 60: dout = 10; + 61: dout = 4; + 62: dout = 5; + 63: dout = 3; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox6.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox6.v new file mode 100644 index 000000000..58fc86af0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox6.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox6(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 12; + 1: dout = 1; + 2: dout = 10; + 3: dout = 15; + 4: dout = 9; + 5: dout = 2; + 6: dout = 6; + 7: dout = 8; + 8: dout = 0; + 9: dout = 13; + 10: dout = 3; + 11: dout = 4; + 12: dout = 14; + 13: dout = 7; + 14: dout = 5; + 15: dout = 11; + + 16: dout = 10; + 17: dout = 15; + 18: dout = 4; + 19: dout = 2; + 20: dout = 7; + 21: dout = 12; + 22: dout = 9; + 23: dout = 5; + 24: dout = 6; + 25: dout = 1; + 26: dout = 13; + 27: dout = 14; + 28: dout = 0; + 29: dout = 11; + 30: dout = 3; + 31: dout = 8; + + 32: dout = 9; + 33: dout = 14; + 34: dout = 15; + 35: dout = 5; + 36: dout = 2; + 37: dout = 8; + 38: dout = 12; + 39: dout = 3; + 40: dout = 7; + 41: dout = 0; + 42: dout = 4; + 43: dout = 10; + 44: dout = 1; + 45: dout = 13; + 46: dout = 11; + 47: dout = 6; + + 48: dout = 4; + 49: dout = 3; + 50: dout = 2; + 51: dout = 12; + 52: dout = 9; + 53: dout = 5; + 54: dout = 15; + 55: dout = 10; + 56: dout = 11; + 57: dout = 14; + 58: dout = 1; + 59: dout = 7; + 60: dout = 6; + 61: dout = 0; + 62: dout = 8; + 63: dout = 13; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox7.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox7.v new file mode 100644 index 000000000..f27957e2f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox7.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox7(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 4; + 1: dout = 11; + 2: dout = 2; + 3: dout = 14; + 4: dout = 15; + 5: dout = 0; + 6: dout = 8; + 7: dout = 13; + 8: dout = 3; + 9: dout = 12; + 10: dout = 9; + 11: dout = 7; + 12: dout = 5; + 13: dout = 10; + 14: dout = 6; + 15: dout = 1; + + 16: dout = 13; + 17: dout = 0; + 18: dout = 11; + 19: dout = 7; + 20: dout = 4; + 21: dout = 9; + 22: dout = 1; + 23: dout = 10; + 24: dout = 14; + 25: dout = 3; + 26: dout = 5; + 27: dout = 12; + 28: dout = 2; + 29: dout = 15; + 30: dout = 8; + 31: dout = 6; + + 32: dout = 1; + 33: dout = 4; + 34: dout = 11; + 35: dout = 13; + 36: dout = 12; + 37: dout = 3; + 38: dout = 7; + 39: dout = 14; + 40: dout = 10; + 41: dout = 15; + 42: dout = 6; + 43: dout = 8; + 44: dout = 0; + 45: dout = 5; + 46: dout = 9; + 47: dout = 2; + + 48: dout = 6; + 49: dout = 11; + 50: dout = 13; + 51: dout = 8; + 52: dout = 1; + 53: dout = 4; + 54: dout = 10; + 55: dout = 7; + 56: dout = 9; + 57: dout = 5; + 58: dout = 0; + 59: dout = 15; + 60: dout = 14; + 61: dout = 2; + 62: dout = 3; + 63: dout = 12; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox8.v b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox8.v new file mode 100644 index 000000000..5ebad6388 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/sbox8.v @@ -0,0 +1,113 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SBOX //// +//// The SBOX is essentially a 64x4 ROM //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +module sbox8(addr, dout); +input [1:6] addr; +output [1:4] dout; +reg [1:4] dout; + +always @(addr) begin + case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case + 0: dout = 13; + 1: dout = 2; + 2: dout = 8; + 3: dout = 4; + 4: dout = 6; + 5: dout = 15; + 6: dout = 11; + 7: dout = 1; + 8: dout = 10; + 9: dout = 9; + 10: dout = 3; + 11: dout = 14; + 12: dout = 5; + 13: dout = 0; + 14: dout = 12; + 15: dout = 7; + + 16: dout = 1; + 17: dout = 15; + 18: dout = 13; + 19: dout = 8; + 20: dout = 10; + 21: dout = 3; + 22: dout = 7; + 23: dout = 4; + 24: dout = 12; + 25: dout = 5; + 26: dout = 6; + 27: dout = 11; + 28: dout = 0; + 29: dout = 14; + 30: dout = 9; + 31: dout = 2; + + 32: dout = 7; + 33: dout = 11; + 34: dout = 4; + 35: dout = 1; + 36: dout = 9; + 37: dout = 12; + 38: dout = 14; + 39: dout = 2; + 40: dout = 0; + 41: dout = 6; + 42: dout = 10; + 43: dout = 13; + 44: dout = 15; + 45: dout = 3; + 46: dout = 5; + 47: dout = 8; + + 48: dout = 2; + 49: dout = 1; + 50: dout = 14; + 51: dout = 7; + 52: dout = 4; + 53: dout = 10; + 54: dout = 8; + 55: dout = 13; + 56: dout = 15; + 57: dout = 12; + 58: dout = 9; + 59: dout = 0; + 60: dout = 3; + 61: dout = 5; + 62: dout = 6; + 63: dout = 11; + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_clockgen.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_clockgen.v new file mode 100644 index 000000000..c967d6f93 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_clockgen.v @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clockgen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_clockgen.v,v $ +// Revision 1.4 2005/02/21 12:48:05 igorm +// Warning fixes. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:55 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`include "timescale.v" + +module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) + +output Mdc; // Output clock +output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. +output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. + +reg Mdc; +reg [7:0] Counter; + +wire CountEq0; +wire [7:0] CounterPreset; +wire [7:0] TempDivider; + + +assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 +assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period + + +// Counter counts half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Counter[7:0] <= #Tp 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= #Tp CounterPreset[7:0]; + end + else + Counter[7:0] <= #Tp Counter - 8'h1; + end +end + + +// Mdc is asserted every other half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Mdc <= #Tp 1'b0; + else + begin + if(CountEq0) + Mdc <= #Tp ~Mdc; + end +end + + +assign CountEq0 = Counter == 8'h0; +assign MdcEn = CountEq0 & ~Mdc; +assign MdcEn_n = CountEq0 & Mdc; + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_crc.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_crc.v new file mode 100644 index 000000000..5fe30503a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_crc.v @@ -0,0 +1,148 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_crc.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_crc.v,v $ +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/19 18:16:40 mohor +// TxClk changed to MTxClk (as discribed in the documentation). +// Crc changed so only one file can be used instead of two. +// +// Revision 1.2 2001/06/19 10:38:07 mohor +// Minor changes in header. +// +// Revision 1.1 2001/06/19 10:27:57 mohor +// TxEthMAC initial release. +// +// +// + + +`include "timescale.v" + +module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); + + +parameter Tp = 1; + +input Clk; +input Reset; +input [3:0] Data; +input Enable; +input Initialize; + +output [31:0] Crc; +output CrcError; + +reg [31:0] Crc; + +wire [31:0] CrcNext; + + +assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); +assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); +assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); +assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); +assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; +assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; +assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; +assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; +assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; +assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; +assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; +assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; +assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; +assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; +assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; +assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; +assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; +assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; +assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; +assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; +assign CrcNext[20] = Crc[16]; +assign CrcNext[21] = Crc[17]; +assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; +assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; +assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; +assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; +assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; +assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; +assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; +assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; +assign CrcNext[30] = Crc[26]; +assign CrcNext[31] = Crc[27]; + + +always @ (posedge Clk or posedge Reset) +begin + if (Reset) + Crc <= #1 32'hffffffff; + else + if(Initialize) + Crc <= #Tp 32'hffffffff; + else + Crc <= #Tp CrcNext; +end + +assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_defines.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_defines.v new file mode 100644 index 000000000..b2d593d99 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_defines.v @@ -0,0 +1,348 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_defines.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is available in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_defines.v,v $ +// Revision 1.34 2005/02/21 12:48:06 igorm +// Warning fixes. +// +// Revision 1.33 2003/11/12 18:24:58 tadejm +// WISHBONE slave changed and tested from only 32-bit accesss to byte access. +// +// Revision 1.32 2003/10/17 07:46:13 markom +// mbist signals updated according to newest convention +// +// Revision 1.31 2003/08/14 16:42:58 simons +// Artisan ram instance added. +// +// Revision 1.30 2003/06/13 11:55:37 mohor +// Define file in eth_cop.v is changed to eth_defines.v. Some defines were +// moved from tb_eth_defines.v to eth_defines.v. +// +// Revision 1.29 2002/11/19 18:13:49 mohor +// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. +// +// Revision 1.28 2002/11/15 14:27:15 mohor +// Since r_Rst bit is not used any more, default value is changed to 0xa000. +// +// Revision 1.27 2002/11/01 18:19:34 mohor +// Defines fixed to use generic RAM by default. +// +// Revision 1.26 2002/10/24 18:53:03 mohor +// fpga define added. +// +// Revision 1.3 2002/10/11 16:57:54 igorm +// eth_defines.v tagged with rel_5 used. +// +// Revision 1.25 2002/10/10 16:47:44 mohor +// Defines changed to have ETH_ prolog. +// ETH_WISHBONE_B# define added. +// +// Revision 1.24 2002/10/10 16:33:11 mohor +// Bist added. +// +// Revision 1.23 2002/09/23 18:22:48 mohor +// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet +// core. +// +// Revision 1.22 2002/09/04 18:36:49 mohor +// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). +// +// Revision 1.21 2002/08/16 22:09:47 mohor +// Defines for register width added. mii_rst signal in MIIMODER register +// changed. +// +// Revision 1.20 2002/08/14 19:31:48 mohor +// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No +// need to multiply or devide any more. +// +// Revision 1.19 2002/07/23 15:28:31 mohor +// Ram , used for BDs changed from generic_spram to eth_spram_256x32. +// +// Revision 1.18 2002/05/03 10:15:50 mohor +// Outputs registered. Reset changed for eth_wishbone module. +// +// Revision 1.17 2002/04/24 08:52:19 mohor +// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" +// bug fixed. +// +// Revision 1.16 2002/03/19 12:53:29 mohor +// Some defines that are used in testbench only were moved to tb_eth_defines.v +// file. +// +// Revision 1.15 2002/02/26 16:11:32 mohor +// Number of interrupts changed +// +// Revision 1.14 2002/02/16 14:03:44 mohor +// Registered trimmed. Unused registers removed. +// +// Revision 1.13 2002/02/16 13:06:33 mohor +// EXTERNAL_DMA used instead of WISHBONE_DMA. +// +// Revision 1.12 2002/02/15 10:58:31 mohor +// Changed that were lost with last update put back to the file. +// +// Revision 1.11 2002/02/14 20:19:41 billditt +// Modified for Address Checking, +// addition of eth_addrcheck.v +// +// Revision 1.10 2002/02/12 17:01:19 mohor +// HASH0 and HASH1 registers added. + +// Revision 1.9 2002/02/08 16:21:54 mohor +// Rx status is written back to the BD. +// +// Revision 1.8 2002/02/05 16:44:38 mohor +// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 +// MHz. Statuses, overrun, control frame transmission and reception still need +// to be fixed. +// +// Revision 1.7 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.6 2001/12/05 15:00:16 mohor +// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors +// instead of the number of RX descriptors). +// +// Revision 1.5 2001/12/05 10:21:37 mohor +// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. +// +// Revision 1.4 2001/11/13 14:23:56 mohor +// Generic memory model is used. Defines are changed for the same reason. +// +// Revision 1.3 2001/10/18 12:07:11 mohor +// Status signals changed, Adress decoding changed, interrupt controller +// added. +// +// Revision 1.2 2001/09/24 15:02:56 mohor +// Defines changed (All precede with ETH_). Small changes because some +// tools generate warnings when two operands are together. Synchronization +// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC +// demands). +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// +// +// +// + + + +//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS + +`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus + +// Ethernet implemented in Xilinx Chips (uncomment following lines) +// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo +// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors + // Core is going to be implemented in Virtex FPGA and contains Virtex + // specific elements. + +// Ethernet implemented in Altera Chips (uncomment following lines) +//`define ETH_ALTERA_ALTSYNCRAM + +// Ethernet implemented in ASIC with Virtual Silicon RAMs +// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation) + +// Ethernet implemented in ASIC with Artisan RAMs +// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation) + +// Uncomment when Avalon bus is used +//`define ETH_AVALON_BUS + +`define ETH_MODER_ADR 8'h0 // 0x0 +`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 +`define ETH_INT_MASK_ADR 8'h2 // 0x8 +`define ETH_IPGT_ADR 8'h3 // 0xC +`define ETH_IPGR1_ADR 8'h4 // 0x10 +`define ETH_IPGR2_ADR 8'h5 // 0x14 +`define ETH_PACKETLEN_ADR 8'h6 // 0x18 +`define ETH_COLLCONF_ADR 8'h7 // 0x1C +`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 +`define ETH_CTRLMODER_ADR 8'h9 // 0x24 +`define ETH_MIIMODER_ADR 8'hA // 0x28 +`define ETH_MIICOMMAND_ADR 8'hB // 0x2C +`define ETH_MIIADDRESS_ADR 8'hC // 0x30 +`define ETH_MIITX_DATA_ADR 8'hD // 0x34 +`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 +`define ETH_MIISTATUS_ADR 8'hF // 0x3C +`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 +`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 +`define ETH_HASH0_ADR 8'h12 // 0x48 +`define ETH_HASH1_ADR 8'h13 // 0x4C +`define ETH_TX_CTRL_ADR 8'h14 // 0x50 +`define ETH_RX_CTRL_ADR 8'h15 // 0x54 + + +`define ETH_MODER_DEF_0 8'h00 +`define ETH_MODER_DEF_1 8'hA0 +`define ETH_MODER_DEF_2 1'h0 +`define ETH_INT_MASK_DEF_0 7'h0 +`define ETH_IPGT_DEF_0 7'h12 +`define ETH_IPGR1_DEF_0 7'h0C +`define ETH_IPGR2_DEF_0 7'h12 +`define ETH_PACKETLEN_DEF_0 8'h00 +`define ETH_PACKETLEN_DEF_1 8'h06 +`define ETH_PACKETLEN_DEF_2 8'h40 +`define ETH_PACKETLEN_DEF_3 8'h00 +`define ETH_COLLCONF_DEF_0 6'h3f +`define ETH_COLLCONF_DEF_2 4'hF +`define ETH_TX_BD_NUM_DEF_0 8'h40 +`define ETH_CTRLMODER_DEF_0 3'h0 +`define ETH_MIIMODER_DEF_0 8'h64 +`define ETH_MIIMODER_DEF_1 1'h0 +`define ETH_MIIADDRESS_DEF_0 5'h00 +`define ETH_MIIADDRESS_DEF_1 5'h00 +`define ETH_MIITX_DATA_DEF_0 8'h00 +`define ETH_MIITX_DATA_DEF_1 8'h00 +`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB +`define ETH_MAC_ADDR0_DEF_0 8'h00 +`define ETH_MAC_ADDR0_DEF_1 8'h00 +`define ETH_MAC_ADDR0_DEF_2 8'h00 +`define ETH_MAC_ADDR0_DEF_3 8'h00 +`define ETH_MAC_ADDR1_DEF_0 8'h00 +`define ETH_MAC_ADDR1_DEF_1 8'h00 +`define ETH_HASH0_DEF_0 8'h00 +`define ETH_HASH0_DEF_1 8'h00 +`define ETH_HASH0_DEF_2 8'h00 +`define ETH_HASH0_DEF_3 8'h00 +`define ETH_HASH1_DEF_0 8'h00 +`define ETH_HASH1_DEF_1 8'h00 +`define ETH_HASH1_DEF_2 8'h00 +`define ETH_HASH1_DEF_3 8'h00 +`define ETH_TX_CTRL_DEF_0 8'h00 // +`define ETH_TX_CTRL_DEF_1 8'h00 // +`define ETH_TX_CTRL_DEF_2 1'h0 // +`define ETH_RX_CTRL_DEF_0 8'h00 +`define ETH_RX_CTRL_DEF_1 8'h00 + + +`define ETH_MODER_WIDTH_0 8 +`define ETH_MODER_WIDTH_1 8 +`define ETH_MODER_WIDTH_2 1 +`define ETH_INT_SOURCE_WIDTH_0 7 +`define ETH_INT_MASK_WIDTH_0 7 +`define ETH_IPGT_WIDTH_0 7 +`define ETH_IPGR1_WIDTH_0 7 +`define ETH_IPGR2_WIDTH_0 7 +`define ETH_PACKETLEN_WIDTH_0 8 +`define ETH_PACKETLEN_WIDTH_1 8 +`define ETH_PACKETLEN_WIDTH_2 8 +`define ETH_PACKETLEN_WIDTH_3 8 +`define ETH_COLLCONF_WIDTH_0 6 +`define ETH_COLLCONF_WIDTH_2 4 +`define ETH_TX_BD_NUM_WIDTH_0 8 +`define ETH_CTRLMODER_WIDTH_0 3 +`define ETH_MIIMODER_WIDTH_0 8 +`define ETH_MIIMODER_WIDTH_1 1 +`define ETH_MIICOMMAND_WIDTH_0 3 +`define ETH_MIIADDRESS_WIDTH_0 5 +`define ETH_MIIADDRESS_WIDTH_1 5 +`define ETH_MIITX_DATA_WIDTH_0 8 +`define ETH_MIITX_DATA_WIDTH_1 8 +`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB +`define ETH_MIISTATUS_WIDTH 3 // not written from WB +`define ETH_MAC_ADDR0_WIDTH_0 8 +`define ETH_MAC_ADDR0_WIDTH_1 8 +`define ETH_MAC_ADDR0_WIDTH_2 8 +`define ETH_MAC_ADDR0_WIDTH_3 8 +`define ETH_MAC_ADDR1_WIDTH_0 8 +`define ETH_MAC_ADDR1_WIDTH_1 8 +`define ETH_HASH0_WIDTH_0 8 +`define ETH_HASH0_WIDTH_1 8 +`define ETH_HASH0_WIDTH_2 8 +`define ETH_HASH0_WIDTH_3 8 +`define ETH_HASH1_WIDTH_0 8 +`define ETH_HASH1_WIDTH_1 8 +`define ETH_HASH1_WIDTH_2 8 +`define ETH_HASH1_WIDTH_3 8 +`define ETH_TX_CTRL_WIDTH_0 8 +`define ETH_TX_CTRL_WIDTH_1 8 +`define ETH_TX_CTRL_WIDTH_2 1 +`define ETH_RX_CTRL_WIDTH_0 8 +`define ETH_RX_CTRL_WIDTH_1 8 + + +// Outputs are registered (uncomment when needed) +`define ETH_REGISTERED_OUTPUTS + +// Settings for TX FIFO +`define ETH_TX_FIFO_CNT_WIDTH 5 +`define ETH_TX_FIFO_DEPTH 16 +`define ETH_TX_FIFO_DATA_WIDTH 32 + +// Settings for RX FIFO +`define ETH_RX_FIFO_CNT_WIDTH 5 +`define ETH_RX_FIFO_DEPTH 16 +`define ETH_RX_FIFO_DATA_WIDTH 32 + +// Burst length +`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH +`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH + +// WISHBONE interface is Revision B3 compliant (uncomment when needed) +//`define ETH_WISHBONE_B3 + + +// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted. +`define ETH_BASE 32'hd0000000 +`define ETH_WIDTH 32'h800 +`define MEMORY_BASE 32'h2000 +`define MEMORY_WIDTH 32'h10000 + +`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) +`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) +`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) +`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) +// Previous defines are only needed for eth_cop.v + diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_fifo.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_fifo.v new file mode 100644 index 000000000..8f90a2e36 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_fifo.v @@ -0,0 +1,189 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_fifo.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_fifo.v,v $ +// Revision 1.4 2005/02/21 12:48:07 igorm +// Warning fixes. +// +// Revision 1.3 2002/04/22 13:45:52 mohor +// Generic ram or Xilinx ram can be used in fifo (selectable by setting +// ETH_FIFO_XILINX in eth_defines.v). +// +// Revision 1.2 2002/03/25 13:33:04 mohor +// When clear and read/write are active at the same time, cnt and pointers are +// set to 1. +// +// Revision 1.1 2002/02/05 16:44:39 mohor +// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 +// MHz. Statuses, overrun, control frame transmission and reception still need +// to be fixed. +// +// + +`include "eth_defines.v" +`include "timescale.v" + +module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt); + +parameter DATA_WIDTH = 32; +parameter DEPTH = 8; +parameter CNT_WIDTH = 4; + +parameter Tp = 1; + +input clk; +input reset; +input write; +input read; +input clear; +input [DATA_WIDTH-1:0] data_in; + +output [DATA_WIDTH-1:0] data_out; +output almost_full; +output full; +output almost_empty; +output empty; +output [CNT_WIDTH-1:0] cnt; + +`ifdef ETH_FIFO_XILINX +`else + `ifdef ETH_ALTERA_ALTSYNCRAM + `else + reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; + reg [DATA_WIDTH-1:0] data_out; + `endif +`endif + +reg [CNT_WIDTH-1:0] cnt; +reg [CNT_WIDTH-2:0] read_pointer; +reg [CNT_WIDTH-2:0] write_pointer; + + +always @ (posedge clk or posedge reset) +begin + if(reset) + cnt <=#Tp 0; + else + if(clear) + cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write}; + else + if(read ^ write) + if(read) + cnt <=#Tp cnt - 1'b1; + else + cnt <=#Tp cnt + 1'b1; +end + +always @ (posedge clk or posedge reset) +begin + if(reset) + read_pointer <=#Tp 0; + else + if(clear) + read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read}; + else + if(read & ~empty) + read_pointer <=#Tp read_pointer + 1'b1; +end + +always @ (posedge clk or posedge reset) +begin + if(reset) + write_pointer <=#Tp 0; + else + if(clear) + write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write}; + else + if(write & ~full) + write_pointer <=#Tp write_pointer + 1'b1; +end + +assign empty = ~(|cnt); +assign almost_empty = cnt == 1; +assign full = cnt == DEPTH; +assign almost_full = &cnt[CNT_WIDTH-2:0]; + + + +`ifdef ETH_FIFO_XILINX + xilinx_dist_ram_16x32 fifo + ( .data_out(data_out), + .we(write & ~full), + .data_in(data_in), + .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer), + .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), + .wclk(clk) + ); +`else // !ETH_FIFO_XILINX +`ifdef ETH_ALTERA_ALTSYNCRAM + altera_dpram_16x32 altera_dpram_16x32_inst + ( + .data (data_in), + .wren (write & ~full), + .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), + .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), + .clock (clk), + .q (data_out) + ); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE +`else // !ETH_ALTERA_ALTSYNCRAM + always @ (posedge clk) + begin + if(write & clear) + fifo[0] <=#Tp data_in; + else + if(write & ~full) + fifo[write_pointer] <=#Tp data_in; + end + + + always @ (posedge clk) + begin + if(clear) + data_out <=#Tp fifo[0]; + else + data_out <=#Tp fifo[read_pointer]; + end +`endif // !ETH_ALTERA_ALTSYNCRAM +`endif // !ETH_FIFO_XILINX + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_maccontrol.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_maccontrol.v new file mode 100644 index 000000000..b93cc1626 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_maccontrol.v @@ -0,0 +1,274 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_maccontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_maccontrol.v,v $ +// Revision 1.7 2003/01/22 13:49:26 tadejm +// When control packets were received, they were ignored in some cases. +// +// Revision 1.6 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.5 2002/11/21 00:14:39 mohor +// TxDone and TxAbort changed so they're not propagated to the wishbone +// module when control frame is transmitted. +// +// Revision 1.4 2002/11/19 17:37:32 mohor +// When control frame (PAUSE) was sent, status was written in the +// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. +// Only TXC interrupt is set. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.1 2001/07/03 12:51:54 mohor +// Initial release of the MAC Control module. +// +// +// +// + + +`include "timescale.v" + + +module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn, + TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd, + ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV, + MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut, + TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm, + ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2 + ); + + +parameter Tp = 1; + + +input MTxClk; // Transmit clock (from PHY) +input MRxClk; // Receive clock (from PHY) +input TxReset; // Transmit reset +input RxReset; // Receive reset +input TPauseRq; // Transmit control frame (from host) +input [7:0] TxDataIn; // Transmit packet data byte (from host) +input TxStartFrmIn; // Transmit packet start frame input (from host) +input TxUsedDataIn; // Transmit packet used data (from TxEthMAC) +input TxEndFrmIn; // Transmit packet end frame input (from host) +input TxDoneIn; // Transmit packet done (from TxEthMAC) +input TxAbortIn; // Transmit packet abort (input from TxEthMAC) +input PadIn; // Padding (input from registers) +input CrcEnIn; // Crc append (input from registers) +input [7:0] RxData; // Receive Packet Data (from RxEthMAC) +input RxValid; // Received a valid packet +input RxStartFrm; // Receive packet start frame (input from RxEthMAC) +input RxEndFrm; // Receive packet end frame (input from RxEthMAC) +input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC) +input ReceivedPacketGood; // Received packet is good +input ReceivedLengthOK; // Length of the received packet is OK +input TxFlow; // Tx flow control (from registers) +input RxFlow; // Rx flow control (from registers) +input DlyCrcEn; // Delayed CRC enabled (from registers) +input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers) +input [47:0] MAC; // MAC address (from registers) +input RxStatusWriteLatched_sync2; +input r_PassAll; + +output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) +output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC) +output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC) +output TxDoneOut; // Transmit packet done (to host) +output TxAbortOut; // Transmit packet aborted (to host) +output TxUsedDataOut; // Transmit packet used data (to host) +output PadOut; // Padding (output to TxEthMAC) +output CrcEnOut; // Crc append (output to TxEthMAC) +output WillSendControlFrame; +output TxCtrlEndFrm; +output ReceivedPauseFrm; +output ControlFrmAddressOK; +output SetPauseTimer; + +reg TxUsedDataOutDetected; +reg TxAbortInLatched; +reg TxDoneInLatched; +reg MuxedDone; +reg MuxedAbort; + +wire Pause; +wire TxCtrlStartFrm; +wire [7:0] ControlData; +wire CtrlMux; +wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC) +wire BlockTxDone; + + +// Signal TxUsedDataOut was detected (a transfer is already in progress) +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + TxUsedDataOutDetected <= #Tp 1'b0; + else + if(TxDoneIn | TxAbortIn) + TxUsedDataOutDetected <= #Tp 1'b0; + else + if(TxUsedDataOut) + TxUsedDataOutDetected <= #Tp 1'b1; +end + + +// Latching variables +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + begin + TxAbortInLatched <= #Tp 1'b0; + TxDoneInLatched <= #Tp 1'b0; + end + else + begin + TxAbortInLatched <= #Tp TxAbortIn; + TxDoneInLatched <= #Tp TxDoneIn; + end +end + + + +// Generating muxed abort signal +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + MuxedAbort <= #Tp 1'b0; + else + if(TxStartFrmIn) + MuxedAbort <= #Tp 1'b0; + else + if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected) + MuxedAbort <= #Tp 1'b1; +end + + +// Generating muxed done signal +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + MuxedDone <= #Tp 1'b0; + else + if(TxStartFrmIn) + MuxedDone <= #Tp 1'b0; + else + if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected) + MuxedDone <= #Tp 1'b1; +end + + +// TxDoneOut +assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) : + ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn); + +// TxAbortOut +assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) : + ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn); + +// TxUsedDataOut +assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn; + +// TxStartFrmOut +assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause); + + +// TxEndFrmOut +assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn; + + +// TxDataOut[7:0] +assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0]; + + +// PadOut +assign PadOut = PadIn | SendingCtrlFrm; + + +// CrcEnOut +assign CrcEnOut = CrcEnIn | SendingCtrlFrm; + + + +// Connecting receivecontrol module +eth_receivecontrol receivecontrol1 +( + .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), + .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), + .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn), + .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK), + .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected), + .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK), + .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer) +); + + +eth_transmitcontrol transmitcontrol1 +( + .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut), + .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq), + .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV), + .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm), + .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone) +); + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_macstatus.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_macstatus.v new file mode 100644 index 000000000..bb96d6b10 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_macstatus.v @@ -0,0 +1,428 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_macstatus.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is available in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_macstatus.v,v $ +// Revision 1.17 2005/03/21 20:07:18 igorm +// Some small fixes + some troubles fixed. +// +// Revision 1.16 2005/02/21 10:42:11 igorm +// Defer indication fixed. +// +// Revision 1.15 2003/01/30 13:28:19 tadejm +// Defer indication changed. +// +// Revision 1.14 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.13 2002/11/13 22:30:58 tadejm +// Late collision is reported only when not in the full duplex. +// Sample is taken (for status) as soon as MRxDV is not valid (regardless +// of the received byte cnt). +// +// Revision 1.12 2002/09/12 14:50:16 mohor +// CarrierSenseLost bug fixed when operating in full duplex mode. +// +// Revision 1.11 2002/09/04 18:38:03 mohor +// CarrierSenseLost status is not set when working in loopback mode. +// +// Revision 1.10 2002/07/25 18:17:46 mohor +// InvalidSymbol generation changed. +// +// Revision 1.9 2002/04/22 13:51:44 mohor +// Short frame and ReceivedLengthOK were not detected correctly. +// +// Revision 1.8 2002/02/18 10:40:17 mohor +// Small fixes. +// +// Revision 1.7 2002/02/15 17:07:39 mohor +// Status was not written correctly when frames were discarted because of +// address mismatch. +// +// Revision 1.6 2002/02/11 09:18:21 mohor +// Tx status is written back to the BD. +// +// Revision 1.5 2002/02/08 16:21:54 mohor +// Rx status is written back to the BD. +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// +// +// +// + +`include "timescale.v" + + +module eth_macstatus( + MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError, + MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting, + RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, + InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision, + r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn, + LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured, + RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm, + StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback, + r_FullD + ); + + + +parameter Tp = 1; + + +input MRxClk; +input Reset; +input RxCrcError; +input MRxErr; +input MRxDV; + +input RxStateSFD; +input [1:0] RxStateData; +input RxStatePreamble; +input RxStateIdle; +input Transmitting; +input [15:0] RxByteCnt; +input RxByteCntEq0; +input RxByteCntGreat2; +input RxByteCntMaxFrame; +input [3:0] MRxD; +input Collision; +input [5:0] CollValid; +input r_RecSmall; +input [15:0] r_MinFL; +input [15:0] r_MaxFL; +input r_HugEn; +input StartTxDone; +input StartTxAbort; +input [3:0] RetryCnt; +input MTxClk; +input MaxCollisionOccured; +input LateCollision; +input DeferIndication; +input TxStartFrm; +input StatePreamble; +input [1:0] StateData; +input CarrierSense; +input TxUsedData; +input Loopback; +input r_FullD; + + +output ReceivedLengthOK; +output ReceiveEnd; +output ReceivedPacketGood; +output InvalidSymbol; +output LatchedCrcError; +output RxLateCollision; +output ShortFrame; +output DribbleNibble; +output ReceivedPacketTooBig; +output LoadRxStatus; +output [3:0] RetryCntLatched; +output RetryLimit; +output LateCollLatched; +output DeferLatched; +input RstDeferLatched; +output CarrierSenseLost; +output LatchedMRxErr; + + +reg ReceiveEnd; + +reg LatchedCrcError; +reg LatchedMRxErr; +reg LoadRxStatus; +reg InvalidSymbol; +reg [3:0] RetryCntLatched; +reg RetryLimit; +reg LateCollLatched; +reg DeferLatched; +reg CarrierSenseLost; + +wire TakeSample; +wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps + +// Crc error +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LatchedCrcError <=#Tp 1'b0; + else + if(RxStateSFD) + LatchedCrcError <=#Tp 1'b0; + else + if(RxStateData[0]) + LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; +end + + +// LatchedMRxErr +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LatchedMRxErr <=#Tp 1'b0; + else + if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting)) + LatchedMRxErr <=#Tp 1'b1; + else + LatchedMRxErr <=#Tp 1'b0; +end + + +// ReceivedPacketGood +assign ReceivedPacketGood = ~LatchedCrcError; + + +// ReceivedLengthOK +assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0]; + + + + + +// Time to take a sample +//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 | +assign TakeSample = (|RxStateData) & (~MRxDV) | + RxStateData[0] & MRxDV & RxByteCntMaxFrame; + + +// LoadRxStatus +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LoadRxStatus <=#Tp 1'b0; + else + LoadRxStatus <=#Tp TakeSample; +end + + + +// ReceiveEnd +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ReceiveEnd <=#Tp 1'b0; + else + ReceiveEnd <=#Tp LoadRxStatus; +end + + +// Invalid Symbol received during 100Mbps mode +assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he; + + +// InvalidSymbol +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + InvalidSymbol <=#Tp 1'b0; + else + if(LoadRxStatus & ~SetInvalidSymbol) + InvalidSymbol <=#Tp 1'b0; + else + if(SetInvalidSymbol) + InvalidSymbol <=#Tp 1'b1; +end + + +// Late Collision + +reg RxLateCollision; +reg RxColWindow; +// Collision Window +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxLateCollision <=#Tp 1'b0; + else + if(LoadRxStatus) + RxLateCollision <=#Tp 1'b0; + else + if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall)) + RxLateCollision <=#Tp 1'b1; +end + +// Collision Window +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxColWindow <=#Tp 1'b1; + else + if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) + RxColWindow <=#Tp 1'b0; + else + if(RxStateIdle) + RxColWindow <=#Tp 1'b1; +end + + +// ShortFrame +reg ShortFrame; +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ShortFrame <=#Tp 1'b0; + else + if(LoadRxStatus) + ShortFrame <=#Tp 1'b0; + else + if(TakeSample) + ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0]; +end + + +// DribbleNibble +reg DribbleNibble; +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + DribbleNibble <=#Tp 1'b0; + else + if(RxStateSFD) + DribbleNibble <=#Tp 1'b0; + else + if(~MRxDV & RxStateData[1]) + DribbleNibble <=#Tp 1'b1; +end + + +reg ReceivedPacketTooBig; +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ReceivedPacketTooBig <=#Tp 1'b0; + else + if(LoadRxStatus) + ReceivedPacketTooBig <=#Tp 1'b0; + else + if(TakeSample) + ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; +end + + + +// Latched Retry counter for tx status +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + RetryCntLatched <=#Tp 4'h0; + else + if(StartTxDone | StartTxAbort) + RetryCntLatched <=#Tp RetryCnt; +end + + +// Latched Retransmission limit +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + RetryLimit <=#Tp 1'h0; + else + if(StartTxDone | StartTxAbort) + RetryLimit <=#Tp MaxCollisionOccured; +end + + +// Latched Late Collision +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + LateCollLatched <=#Tp 1'b0; + else + if(StartTxDone | StartTxAbort) + LateCollLatched <=#Tp LateCollision; +end + + + +// Latched Defer state +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + DeferLatched <=#Tp 1'b0; + else + if(DeferIndication) + DeferLatched <=#Tp 1'b1; + else + if(RstDeferLatched) + DeferLatched <=#Tp 1'b0; +end + + +// CarrierSenseLost +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + CarrierSenseLost <=#Tp 1'b0; + else + if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD) + CarrierSenseLost <=#Tp 1'b1; + else + if(TxStartFrm) + CarrierSenseLost <=#Tp 1'b0; +end + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_miim.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_miim.v new file mode 100644 index 000000000..217012786 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_miim.v @@ -0,0 +1,451 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_miim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_miim.v,v $ +// Revision 1.7 2005/03/21 20:07:18 igorm +// Some small fixes + some troubles fixed. +// +// Revision 1.6 2005/02/21 12:48:07 igorm +// Warning fixes. +// +// Revision 1.5 2003/05/16 10:08:27 mohor +// Busy was set 2 cycles too late. Reported by Dennis Scott. +// +// Revision 1.4 2002/08/14 18:32:10 mohor +// - Busy signal was not set on time when scan status operation was performed +// and clock was divided with more than 2. +// - Nvalid remains valid two more clocks (was previously cleared too soon). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`include "timescale.v" + + +module eth_miim +( + Clk, + Reset, + Divider, + NoPre, + CtrlData, + Rgad, + Fiad, + WCtrlData, + RStat, + ScanStat, + Mdi, + Mdo, + MdoEn, + Mdc, + Busy, + Prsd, + LinkFail, + Nvalid, + WCtrlDataStart, + RStatStart, + UpdateMIIRX_DATAReg +); + + + +input Clk; // Host Clock +input Reset; // General Reset +input [7:0] Divider; // Divider for the host clock +input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) +input [4:0] Rgad; // Register Address (within the PHY) +input [4:0] Fiad; // PHY Address +input NoPre; // No Preamble (no 32-bit preamble) +input WCtrlData; // Write Control Data operation +input RStat; // Read Status operation +input ScanStat; // Scan Status operation +input Mdi; // MII Management Data In + +output Mdc; // MII Management Data Clock +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable +output Busy; // Busy Signal +output LinkFail; // Link Integrity Signal +output Nvalid; // Invalid Status (qualifier for the valid scan result) + +output [15:0] Prsd; // Read Status Data (data read from the PHY) + +output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +parameter Tp = 1; + + +reg Nvalid; +reg EndBusy_d; // Pre-end Busy signal +reg EndBusy; // End Busy signal (stops the operation in progress) + +reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle +reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles +reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles +reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) +reg WCtrlDataStart_q; +reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle +reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles + +reg RStat_q1; // Read Status operation delayed 1 Clk cycle +reg RStat_q2; // Read Status operation delayed 2 Clk cycles +reg RStat_q3; // Read Status operation delayed 3 Clk cycles +reg RStatStart; // Start Read Status Command (positive edge detected) +reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle +reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles + +reg ScanStat_q1; // Scan Status operation delayed 1 cycle +reg ScanStat_q2; // Scan Status operation delayed 2 cycles +reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn + +wire WriteDataOp; // Write Data Operation (positive edge detected) +wire ReadStatusOp; // Read Status Operation (positive edge detected) +wire ScanStatusOp; // Scan Status Operation (positive edge detected) +wire StartOp; // Start Operation (start of any of the preceding operations) +wire EndOp; // End of Operation + +reg InProgress; // Operation in progress +reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle +reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles +reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles + +reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +reg [6:0] BitCounter; // Bit Counter + + +wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. +wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. +wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +wire MdcEn_n; + +wire LatchByte1_d2; +wire LatchByte0_d2; +reg LatchByte1_d; +reg LatchByte0_d; +reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register + +reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + + + + + +// Generation of the EndBusy signal. It is used for ending the MII Management operation. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + EndBusy_d <= #Tp 1'b0; + EndBusy <= #Tp 1'b0; + end + else + begin + EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; + EndBusy <= #Tp EndBusy_d; + end +end + + +// Update MII RX_DATA register +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + UpdateMIIRX_DATAReg <= #Tp 0; + else + if(EndBusy & ~WCtrlDataStart_q) + UpdateMIIRX_DATAReg <= #Tp 1; + else + UpdateMIIRX_DATAReg <= #Tp 0; +end + + + +// Generation of the delayed signals used for positive edge triggering. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlData_q1 <= #Tp 1'b0; + WCtrlData_q2 <= #Tp 1'b0; + WCtrlData_q3 <= #Tp 1'b0; + + RStat_q1 <= #Tp 1'b0; + RStat_q2 <= #Tp 1'b0; + RStat_q3 <= #Tp 1'b0; + + ScanStat_q1 <= #Tp 1'b0; + ScanStat_q2 <= #Tp 1'b0; + SyncStatMdcEn <= #Tp 1'b0; + end + else + begin + WCtrlData_q1 <= #Tp WCtrlData; + WCtrlData_q2 <= #Tp WCtrlData_q1; + WCtrlData_q3 <= #Tp WCtrlData_q2; + + RStat_q1 <= #Tp RStat; + RStat_q2 <= #Tp RStat_q1; + RStat_q3 <= #Tp RStat_q2; + + ScanStat_q1 <= #Tp ScanStat; + ScanStat_q2 <= #Tp ScanStat_q1; + if(MdcEn) + SyncStatMdcEn <= #Tp ScanStat_q2; + end +end + + +// Generation of the Start Commands (Write Control Data or Read Status) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart <= #Tp 1'b0; + WCtrlDataStart_q <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(EndBusy) + begin + WCtrlDataStart <= #Tp 1'b0; + RStatStart <= #Tp 1'b0; + end + else + begin + if(WCtrlData_q2 & ~WCtrlData_q3) + WCtrlDataStart <= #Tp 1'b1; + if(RStat_q2 & ~RStat_q3) + RStatStart <= #Tp 1'b1; + WCtrlDataStart_q <= #Tp WCtrlDataStart; + end + end +end + + +// Generation of the Nvalid signal (indicates when the status is invalid) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Nvalid <= #Tp 1'b0; + else + begin + if(~InProgress_q2 & InProgress_q3) + begin + Nvalid <= #Tp 1'b0; + end + else + begin + if(ScanStat_q2 & ~SyncStatMdcEn) + Nvalid <= #Tp 1'b1; + end + end +end + +// Signals used for the generation of the Operation signals (positive edge) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart_q1 <= #Tp 1'b0; + WCtrlDataStart_q2 <= #Tp 1'b0; + + RStatStart_q1 <= #Tp 1'b0; + RStatStart_q2 <= #Tp 1'b0; + + InProgress_q1 <= #Tp 1'b0; + InProgress_q2 <= #Tp 1'b0; + InProgress_q3 <= #Tp 1'b0; + + LatchByte0_d <= #Tp 1'b0; + LatchByte1_d <= #Tp 1'b0; + + LatchByte <= #Tp 2'b00; + end + else + begin + if(MdcEn) + begin + WCtrlDataStart_q1 <= #Tp WCtrlDataStart; + WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; + + RStatStart_q1 <= #Tp RStatStart; + RStatStart_q2 <= #Tp RStatStart_q1; + + LatchByte[0] <= #Tp LatchByte0_d; + LatchByte[1] <= #Tp LatchByte1_d; + + LatchByte0_d <= #Tp LatchByte0_d2; + LatchByte1_d <= #Tp LatchByte1_d2; + + InProgress_q1 <= #Tp InProgress; + InProgress_q2 <= #Tp InProgress_q1; + InProgress_q3 <= #Tp InProgress_q2; + end + end +end + + +// Generation of the Operation signals +assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; +assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; +assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; +assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; + +// Busy +assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; + + +// Generation of the InProgress signal (indicates when an operation is in progress) +// Generation of the WriteOp signal (indicates when a write is in progress) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + else + begin + if(MdcEn) + begin + if(StartOp) + begin + if(~InProgress) + WriteOp <= #Tp WriteDataOp; + InProgress <= #Tp 1'b1; + end + else + begin + if(EndOp) + begin + InProgress <= #Tp 1'b0; + WriteOp <= #Tp 1'b0; + end + end + end + end +end + + + +// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + BitCounter[6:0] <= #Tp 7'h0; + else + begin + if(MdcEn) + begin + if(InProgress) + begin + if(NoPre & ( BitCounter == 7'h0 )) + BitCounter[6:0] <= #Tp 7'h21; + else + BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; + end + else + BitCounter[6:0] <= #Tp 7'h0; + end + end +end + + +// Operation ends when the Bit Counter reaches 63 +assign EndOp = BitCounter==63; + +assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); +assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); +assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); +assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); + + +// Latch Byte selects which part of Read Status Data is updated from the shift register +assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; +assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; + + +// Connecting the Clock Generator Module +eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) + ); + +// Connecting the Shift Register Module +eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), + .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), + .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) + ); + +// Connecting the Output Control Module +eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), + .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), + .Mdo(Mdo), .MdoEn(MdoEn) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_outputcontrol.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_outputcontrol.v new file mode 100644 index 000000000..bffdd6ac2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_outputcontrol.v @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_outputcontrol.v,v $ +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`include "timescale.v" + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +parameter Tp = 1; + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= #Tp 1'b0; + MdoEn_d <= #Tp 1'b0; + MdoEn <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; + MdoEn_d <= #Tp MdoEn_2d; + MdoEn <= #Tp MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= #Tp 1'b0; + Mdo_d <= #Tp 1'b0; + Mdo <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= #Tp ~SerialEn & BitCounter<32; + Mdo_d <= #Tp ShiftedBit | Mdo_2d; + Mdo <= #Tp Mdo_d; + end + end +end + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_random.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_random.v new file mode 100644 index 000000000..9757e2498 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_random.v @@ -0,0 +1,144 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_random.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_random.v,v $ +// Revision 1.4 2003/06/13 11:26:08 mohor +// Binary operator used instead of unary (xnor). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/19 18:16:40 mohor +// TxClk changed to MTxClk (as discribed in the documentation). +// Crc changed so only one file can be used instead of two. +// +// Revision 1.2 2001/06/19 10:38:07 mohor +// Minor changes in header. +// +// Revision 1.1 2001/06/19 10:27:57 mohor +// TxEthMAC initial release. +// +// +// +// + +`include "timescale.v" + +module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, + RandomEq0, RandomEqByteCnt); + +parameter Tp = 1; + +input MTxClk; +input Reset; +input StateJam; +input StateJam_q; +input [3:0] RetryCnt; +input [15:0] NibCnt; +input [9:0] ByteCnt; +output RandomEq0; +output RandomEqByteCnt; + +wire Feedback; +reg [9:0] x; +wire [9:0] Random; +reg [9:0] RandomLatched; + + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + x[9:0] <= #Tp 0; + else + x[9:0] <= #Tp {x[8:0], Feedback}; +end + +assign Feedback = ~(x[2] ^ x[9]); + +assign Random [0] = x[0]; +assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0; +assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0; +assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0; +assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0; +assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0; +assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0; +assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0; +assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0; +assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0; + + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + RandomLatched <= #Tp 10'h000; + else + begin + if(StateJam & StateJam_q) + RandomLatched <= #Tp Random; + end +end + +// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff. +assign RandomEq0 = RandomLatched == 10'h0; + +assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_receivecontrol.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_receivecontrol.v new file mode 100644 index 000000000..2edec86b2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_receivecontrol.v @@ -0,0 +1,441 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_receivecontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_receivecontrol.v,v $ +// Revision 1.5 2003/01/22 13:49:26 tadejm +// When control packets were received, they were ignored in some cases. +// +// Revision 1.4 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.1 2001/07/03 12:51:54 mohor +// Initial release of the MAC Control module. +// +// +// +// +// + + +`include "timescale.v" + + +module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm, + RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn, + TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood, + TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK, + RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer + ); + +parameter Tp = 1; + + +input MTxClk; +input MRxClk; +input TxReset; +input RxReset; +input [7:0] RxData; +input RxValid; +input RxStartFrm; +input RxEndFrm; +input RxFlow; +input ReceiveEnd; +input [47:0]MAC; +input DlyCrcEn; +input TxDoneIn; +input TxAbortIn; +input TxStartFrmOut; +input ReceivedLengthOK; +input ReceivedPacketGood; +input TxUsedDataOutDetected; +input RxStatusWriteLatched_sync2; +input r_PassAll; + +output Pause; +output ReceivedPauseFrm; +output AddressOK; +output SetPauseTimer; + + +reg Pause; +reg AddressOK; // Multicast or unicast address detected +reg TypeLengthOK; // Type/Length field contains 0x8808 +reg DetectionWindow; // Detection of the PAUSE frame is possible within this window +reg OpCodeOK; // PAUSE opcode detected (0x0001) +reg [2:0] DlyCrcCnt; +reg [4:0] ByteCnt; +reg [15:0] AssembledTimerValue; +reg [15:0] LatchedTimerValue; +reg ReceivedPauseFrm; +reg ReceivedPauseFrmWAddr; +reg PauseTimerEq0_sync1; +reg PauseTimerEq0_sync2; +reg [15:0] PauseTimer; +reg Divider2; +reg [5:0] SlotTimer; + +wire [47:0] ReservedMulticast; // 0x0180C2000001 +wire [15:0] TypeLength; // 0x8808 +wire ResetByteCnt; // +wire IncrementByteCnt; // +wire ByteCntEq0; // ByteCnt = 0 +wire ByteCntEq1; // ByteCnt = 1 +wire ByteCntEq2; // ByteCnt = 2 +wire ByteCntEq3; // ByteCnt = 3 +wire ByteCntEq4; // ByteCnt = 4 +wire ByteCntEq5; // ByteCnt = 5 +wire ByteCntEq12; // ByteCnt = 12 +wire ByteCntEq13; // ByteCnt = 13 +wire ByteCntEq14; // ByteCnt = 14 +wire ByteCntEq15; // ByteCnt = 15 +wire ByteCntEq16; // ByteCnt = 16 +wire ByteCntEq17; // ByteCnt = 17 +wire ByteCntEq18; // ByteCnt = 18 +wire DecrementPauseTimer; // +wire PauseTimerEq0; // +wire ResetSlotTimer; // +wire IncrementSlotTimer; // +wire SlotFinished; // + + + +// Reserved multicast address and Type/Length for PAUSE control +assign ReservedMulticast = 48'h0180C2000001; +assign TypeLength = 16'h8808; + + +// Address Detection (Multicast or unicast) +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + AddressOK <= #Tp 1'b0; + else + if(DetectionWindow & ByteCntEq0) + AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; + else + if(DetectionWindow & ByteCntEq1) + AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; + else + if(DetectionWindow & ByteCntEq2) + AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; + else + if(DetectionWindow & ByteCntEq3) + AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; + else + if(DetectionWindow & ByteCntEq4) + AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; + else + if(DetectionWindow & ByteCntEq5) + AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; + else + if(ReceiveEnd) + AddressOK <= #Tp 1'b0; +end + + + +// TypeLengthOK (Type/Length Control frame detected) +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + TypeLengthOK <= #Tp 1'b0; + else + if(DetectionWindow & ByteCntEq12) + TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); + else + if(DetectionWindow & ByteCntEq13) + TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; + else + if(ReceiveEnd) + TypeLengthOK <= #Tp 1'b0; +end + + + +// Latch Control Frame Opcode +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + OpCodeOK <= #Tp 1'b0; + else + if(ByteCntEq16) + OpCodeOK <= #Tp 1'b0; + else + begin + if(DetectionWindow & ByteCntEq14) + OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00; + + if(DetectionWindow & ByteCntEq15) + OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; + end +end + + +// ReceivedPauseFrmWAddr (+Address Check) +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + ReceivedPauseFrmWAddr <= #Tp 1'b0; + else + if(ReceiveEnd) + ReceivedPauseFrmWAddr <= #Tp 1'b0; + else + if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK) + ReceivedPauseFrmWAddr <= #Tp 1'b1; +end + + + +// Assembling 16-bit timer value from two 8-bit data +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + AssembledTimerValue[15:0] <= #Tp 16'h0; + else + if(RxStartFrm) + AssembledTimerValue[15:0] <= #Tp 16'h0; + else + begin + if(DetectionWindow & ByteCntEq16) + AssembledTimerValue[15:8] <= #Tp RxData[7:0]; + if(DetectionWindow & ByteCntEq17) + AssembledTimerValue[7:0] <= #Tp RxData[7:0]; + end +end + + +// Detection window (while PAUSE detection is possible) +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + DetectionWindow <= #Tp 1'b1; + else + if(ByteCntEq18) + DetectionWindow <= #Tp 1'b0; + else + if(ReceiveEnd) + DetectionWindow <= #Tp 1'b1; +end + + + +// Latching Timer Value +always @ (posedge MRxClk or posedge RxReset ) +begin + if(RxReset) + LatchedTimerValue[15:0] <= #Tp 16'h0; + else + if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) + LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0]; + else + if(ReceiveEnd) + LatchedTimerValue[15:0] <= #Tp 16'h0; +end + + + +// Delayed CEC counter +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + DlyCrcCnt <= #Tp 3'h0; + else + if(RxValid & RxEndFrm) + DlyCrcCnt <= #Tp 3'h0; + else + if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2]) + DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; +end + + +assign ResetByteCnt = RxEndFrm; +assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]); + + +// Byte counter +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + ByteCnt[4:0] <= #Tp 5'h0; + else + if(ResetByteCnt) + ByteCnt[4:0] <= #Tp 5'h0; + else + if(IncrementByteCnt) + ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1; +end + + +assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0; +assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1; +assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2; +assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3; +assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4; +assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5; +assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C; +assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D; +assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E; +assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F; +assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10; +assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11; +assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow; + + +assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow; +assign DecrementPauseTimer = SlotFinished & |PauseTimer; + + +// PauseTimer[15:0] +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + PauseTimer[15:0] <= #Tp 16'h0; + else + if(SetPauseTimer) + PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0]; + else + if(DecrementPauseTimer) + PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1; +end + +assign PauseTimerEq0 = ~(|PauseTimer[15:0]); + + + +// Synchronization of the pause timer +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + begin + PauseTimerEq0_sync1 <= #Tp 1'b1; + PauseTimerEq0_sync2 <= #Tp 1'b1; + end + else + begin + PauseTimerEq0_sync1 <= #Tp PauseTimerEq0; + PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1; + end +end + + +// Pause signal generation +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + Pause <= #Tp 1'b0; + else + if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut) + Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2; +end + + +// Divider2 is used for incrementing the Slot timer every other clock +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + Divider2 <= #Tp 1'b0; + else + if(|PauseTimer[15:0] & RxFlow) + Divider2 <= #Tp ~Divider2; + else + Divider2 <= #Tp 1'b0; +end + + +assign ResetSlotTimer = RxReset; +assign IncrementSlotTimer = Pause & RxFlow & Divider2; + + +// SlotTimer +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + SlotTimer[5:0] <= #Tp 6'h0; + else + if(ResetSlotTimer) + SlotTimer[5:0] <= #Tp 6'h0; + else + if(IncrementSlotTimer) + SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1; +end + + +assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes) + + + +// Pause Frame received +always @ (posedge MRxClk or posedge RxReset) +begin + if(RxReset) + ReceivedPauseFrm <=#Tp 1'b0; + else + if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll)) + ReceivedPauseFrm <=#Tp 1'b0; + else + if(ByteCntEq16 & TypeLengthOK & OpCodeOK) + ReceivedPauseFrm <=#Tp 1'b1; +end + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_register.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_register.v new file mode 100644 index 000000000..265561e18 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_register.v @@ -0,0 +1,111 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_register.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_register.v,v $ +// Revision 1.6 2002/08/16 22:10:12 mohor +// Synchronous reset added. +// +// Revision 1.5 2002/08/16 12:33:27 mohor +// Parameter ResetValue changed to capital letters. +// +// Revision 1.4 2002/02/26 16:18:08 mohor +// Reset values are passed to registers through parameters +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// +// +// +// +// +// + +`include "timescale.v" + + +module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); + +parameter WIDTH = 8; // default parameter of the register width +parameter RESET_VALUE = 0; + +input [WIDTH-1:0] DataIn; + +input Write; +input Clk; +input Reset; +input SyncReset; + +output [WIDTH-1:0] DataOut; +reg [WIDTH-1:0] DataOut; + + + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + DataOut<=#1 RESET_VALUE; + else + if(SyncReset) + DataOut<=#1 RESET_VALUE; + else + if(Write) // write + DataOut<=#1 DataIn; +end + + + +endmodule // Register diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_registers.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_registers.v new file mode 100644 index 000000000..48aacc3d5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_registers.v @@ -0,0 +1,1184 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_registers.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_registers.v,v $ +// Revision 1.29 2005/03/21 20:07:18 igorm +// Some small fixes + some troubles fixed. +// +// Revision 1.28 2004/04/26 15:26:23 igorm +// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the +// previous update of the core. +// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. +// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER +// register. (thanks to Mathias and Torbjorn) +// - Multicast reception was fixed. Thanks to Ulrich Gries +// +// Revision 1.27 2004/04/26 11:42:17 igorm +// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. +// +// Revision 1.26 2003/11/12 18:24:59 tadejm +// WISHBONE slave changed and tested from only 32-bit accesss to byte access. +// +// Revision 1.25 2003/04/18 16:26:25 mohor +// RxBDAddress was updated also when value to r_TxBDNum was written with +// greater value than allowed. +// +// Revision 1.24 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.23 2002/11/19 18:13:49 mohor +// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. +// +// Revision 1.22 2002/11/14 18:37:20 mohor +// r_Rst signal does not reset any module any more and is removed from the design. +// +// Revision 1.21 2002/09/10 10:35:23 mohor +// Ethernet debug registers removed. +// +// Revision 1.20 2002/09/04 18:40:25 mohor +// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to +// the control frames connected. +// +// Revision 1.19 2002/08/19 16:01:40 mohor +// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. +// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut. +// +// Revision 1.18 2002/08/16 22:28:23 mohor +// Syntax error fixed. +// +// Revision 1.17 2002/08/16 22:23:03 mohor +// Syntax error fixed. +// +// Revision 1.16 2002/08/16 22:14:22 mohor +// Synchronous reset added to all registers. Defines used for width. r_MiiMRst +// changed from bit position 10 to 9. +// +// Revision 1.15 2002/08/14 18:26:37 mohor +// LinkFailRegister is reflecting the status of the PHY's link fail status bit. +// +// Revision 1.14 2002/04/22 14:03:44 mohor +// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled +// or not. +// +// Revision 1.13 2002/02/26 16:18:09 mohor +// Reset values are passed to registers through parameters +// +// Revision 1.12 2002/02/17 13:23:42 mohor +// Define missmatch fixed. +// +// Revision 1.11 2002/02/16 14:03:44 mohor +// Registered trimmed. Unused registers removed. +// +// Revision 1.10 2002/02/15 11:08:25 mohor +// File format fixed a bit. +// +// Revision 1.9 2002/02/14 20:19:41 billditt +// Modified for Address Checking, +// addition of eth_addrcheck.v +// +// Revision 1.8 2002/02/12 17:01:19 mohor +// HASH0 and HASH1 registers added. + +// Revision 1.7 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.6 2001/12/05 15:00:16 mohor +// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors +// instead of the number of RX descriptors). +// +// Revision 1.5 2001/12/05 10:22:19 mohor +// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. +// +// Revision 1.4 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.3 2001/10/18 12:07:11 mohor +// Status signals changed, Adress decoding changed, interrupt controller +// added. +// +// Revision 1.2 2001/09/24 15:02:56 mohor +// Defines changed (All precede with ETH_). Small changes because some +// tools generate warnings when two operands are together. Synchronization +// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC +// demands). +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// +// +// +// +// + +`include "eth_defines.v" +`include "timescale.v" + + +module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, + r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn, + r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG, + r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, + TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, + r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, + r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, + r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, + r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, + LinkFail, r_MAC, WCtrlDataStart, RStatStart, + UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, + r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, + StartTxDone, TxClk, RxClk, SetPauseTimer + ); + +parameter Tp = 1; + +input [31:0] DataIn; +input [7:0] Address; + +input Rw; +input [3:0] Cs; +input Clk; +input Reset; + +input WCtrlDataStart; +input RStatStart; + +input UpdateMIIRX_DATAReg; +input [15:0] Prsd; + +output [31:0] DataOut; +reg [31:0] DataOut; + +output r_RecSmall; +output r_Pad; +output r_HugEn; +output r_CrcEn; +output r_DlyCrcEn; +output r_FullD; +output r_ExDfrEn; +output r_NoBckof; +output r_LoopBck; +output r_IFG; +output r_Pro; +output r_Iam; +output r_Bro; +output r_NoPre; +output r_TxEn; +output r_RxEn; +output [31:0] r_HASH0; +output [31:0] r_HASH1; + +input TxB_IRQ; +input TxE_IRQ; +input RxB_IRQ; +input RxE_IRQ; +input Busy_IRQ; + +output [6:0] r_IPGT; + +output [6:0] r_IPGR1; + +output [6:0] r_IPGR2; + +output [15:0] r_MinFL; +output [15:0] r_MaxFL; + +output [3:0] r_MaxRet; +output [5:0] r_CollValid; + +output r_TxFlow; +output r_RxFlow; +output r_PassAll; + +output r_MiiNoPre; +output [7:0] r_ClkDiv; + +output r_WCtrlData; +output r_RStat; +output r_ScanStat; + +output [4:0] r_RGAD; +output [4:0] r_FIAD; + +output [15:0]r_CtrlData; + + +input NValid_stat; +input Busy_stat; +input LinkFail; + +output [47:0]r_MAC; +output [7:0] r_TxBDNum; +output int_o; +output [15:0]r_TxPauseTV; +output r_TxPauseRq; +input RstTxPauseRq; +input TxCtrlEndFrm; +input StartTxDone; +input TxClk; +input RxClk; +input SetPauseTimer; + +reg irq_txb; +reg irq_txe; +reg irq_rxb; +reg irq_rxe; +reg irq_busy; +reg irq_txc; +reg irq_rxc; + +reg SetTxCIrq_txclk; +reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3; +reg SetTxCIrq; +reg ResetTxCIrq_sync1, ResetTxCIrq_sync2; + +reg SetRxCIrq_rxclk; +reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3; +reg SetRxCIrq; +reg ResetRxCIrq_sync1; +reg ResetRxCIrq_sync2; +reg ResetRxCIrq_sync3; + +wire [3:0] Write = Cs & {4{Rw}}; +wire Read = (|Cs) & ~Rw; + +wire MODER_Sel = (Address == `ETH_MODER_ADR ); +wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR ); +wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR ); +wire IPGT_Sel = (Address == `ETH_IPGT_ADR ); +wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR ); +wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR ); +wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR ); +wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR ); + +wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR ); +wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR ); +wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR ); +wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR ); +wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR ); +wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR ); +wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR ); +wire HASH0_Sel = (Address == `ETH_HASH0_ADR ); +wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); +wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); +wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); +wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); + + +wire [2:0] MODER_Wr; +wire [0:0] INT_SOURCE_Wr; +wire [0:0] INT_MASK_Wr; +wire [0:0] IPGT_Wr; +wire [0:0] IPGR1_Wr; +wire [0:0] IPGR2_Wr; +wire [3:0] PACKETLEN_Wr; +wire [2:0] COLLCONF_Wr; +wire [0:0] CTRLMODER_Wr; +wire [1:0] MIIMODER_Wr; +wire [0:0] MIICOMMAND_Wr; +wire [1:0] MIIADDRESS_Wr; +wire [1:0] MIITX_DATA_Wr; +wire MIIRX_DATA_Wr; +wire [3:0] MAC_ADDR0_Wr; +wire [1:0] MAC_ADDR1_Wr; +wire [3:0] HASH0_Wr; +wire [3:0] HASH1_Wr; +wire [2:0] TXCTRL_Wr; +wire [0:0] TX_BD_NUM_Wr; + +assign MODER_Wr[0] = Write[0] & MODER_Sel; +assign MODER_Wr[1] = Write[1] & MODER_Sel; +assign MODER_Wr[2] = Write[2] & MODER_Sel; +assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel; +assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel; +assign IPGT_Wr[0] = Write[0] & IPGT_Sel; +assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel; +assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel; +assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel; +assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel; +assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel; +assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel; +assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel; +assign COLLCONF_Wr[1] = 1'b0; // Not used +assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel; + +assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel; +assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel; +assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel; +assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel; +assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel; +assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel; +assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel; +assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel; +assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; +assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel; +assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel; +assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel; +assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel; +assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel; +assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel; +assign HASH0_Wr[0] = Write[0] & HASH0_Sel; +assign HASH0_Wr[1] = Write[1] & HASH0_Sel; +assign HASH0_Wr[2] = Write[2] & HASH0_Sel; +assign HASH0_Wr[3] = Write[3] & HASH0_Sel; +assign HASH1_Wr[0] = Write[0] & HASH1_Sel; +assign HASH1_Wr[1] = Write[1] & HASH1_Sel; +assign HASH1_Wr[2] = Write[2] & HASH1_Sel; +assign HASH1_Wr[3] = Write[3] & HASH1_Sel; +assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel; +assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel; +assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel; +assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80); + + + +wire [31:0] MODEROut; +wire [31:0] INT_SOURCEOut; +wire [31:0] INT_MASKOut; +wire [31:0] IPGTOut; +wire [31:0] IPGR1Out; +wire [31:0] IPGR2Out; +wire [31:0] PACKETLENOut; +wire [31:0] COLLCONFOut; +wire [31:0] CTRLMODEROut; +wire [31:0] MIIMODEROut; +wire [31:0] MIICOMMANDOut; +wire [31:0] MIIADDRESSOut; +wire [31:0] MIITX_DATAOut; +wire [31:0] MIIRX_DATAOut; +wire [31:0] MIISTATUSOut; +wire [31:0] MAC_ADDR0Out; +wire [31:0] MAC_ADDR1Out; +wire [31:0] TX_BD_NUMOut; +wire [31:0] HASH0Out; +wire [31:0] HASH1Out; +wire [31:0] TXCTRLOut; + +// MODER Register +eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 + ( + .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]), + .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]), + .Write (MODER_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1 + ( + .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]), + .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]), + .Write (MODER_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2 + ( + .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]), + .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]), + .Write (MODER_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0; + +// INT_MASK Register +eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0 + ( + .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]), + .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]), + .Write (INT_MASK_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0; + +// IPGT Register +eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0 + ( + .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]), + .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]), + .Write (IPGT_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0; + +// IPGR1 Register +eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0 + ( + .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]), + .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]), + .Write (IPGR1_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0; + +// IPGR2 Register +eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0 + ( + .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]), + .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]), + .Write (IPGR2_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0; + +// PACKETLEN Register +eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0 + ( + .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]), + .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]), + .Write (PACKETLEN_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1 + ( + .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]), + .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]), + .Write (PACKETLEN_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2 + ( + .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]), + .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]), + .Write (PACKETLEN_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3 + ( + .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]), + .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]), + .Write (PACKETLEN_Wr[3]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); + +// COLLCONF Register +eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0 + ( + .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]), + .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]), + .Write (COLLCONF_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2 + ( + .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]), + .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]), + .Write (COLLCONF_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0; +assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0; + +// TX_BD_NUM Register +eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0 + ( + .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), + .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), + .Write (TX_BD_NUM_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0; + +// CTRLMODER Register +eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0 + ( + .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]), + .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]), + .Write (CTRLMODER_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0; + +// MIIMODER Register +eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0 + ( + .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]), + .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]), + .Write (MIIMODER_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1 + ( + .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]), + .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]), + .Write (MIIMODER_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0; + +// MIICOMMAND Register +eth_register #(1, 0) MIICOMMAND0 + ( + .DataIn (DataIn[0]), + .DataOut (MIICOMMANDOut[0]), + .Write (MIICOMMAND_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(1, 0) MIICOMMAND1 + ( + .DataIn (DataIn[1]), + .DataOut (MIICOMMANDOut[1]), + .Write (MIICOMMAND_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (RStatStart) + ); +eth_register #(1, 0) MIICOMMAND2 + ( + .DataIn (DataIn[2]), + .DataOut (MIICOMMANDOut[2]), + .Write (MIICOMMAND_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (WCtrlDataStart) + ); +assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0; + +// MIIADDRESSRegister +eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0 + ( + .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), + .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), + .Write (MIIADDRESS_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1 + ( + .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), + .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), + .Write (MIIADDRESS_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0; +assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0; + +// MIITX_DATA Register +eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0 + ( + .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), + .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), + .Write (MIITX_DATA_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1 + ( + .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), + .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), + .Write (MIITX_DATA_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0; + +// MIIRX_DATA Register +eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA + ( + .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]), + .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]), + .Write (MIIRX_DATA_Wr), // not written from WB + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0; + +// MAC_ADDR0 Register +eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0 + ( + .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), + .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), + .Write (MAC_ADDR0_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1 + ( + .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), + .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), + .Write (MAC_ADDR0_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2 + ( + .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), + .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), + .Write (MAC_ADDR0_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3 + ( + .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), + .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), + .Write (MAC_ADDR0_Wr[3]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); + +// MAC_ADDR1 Register +eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0 + ( + .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), + .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), + .Write (MAC_ADDR1_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1 + ( + .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), + .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), + .Write (MAC_ADDR1_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0; + +// RXHASH0 Register +eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0 + ( + .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]), + .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]), + .Write (HASH0_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1 + ( + .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]), + .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]), + .Write (HASH0_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2 + ( + .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]), + .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]), + .Write (HASH0_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3 + ( + .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]), + .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]), + .Write (HASH0_Wr[3]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); + +// RXHASH1 Register +eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0 + ( + .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]), + .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]), + .Write (HASH1_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1 + ( + .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]), + .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]), + .Write (HASH1_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2 + ( + .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]), + .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]), + .Write (HASH1_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3 + ( + .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]), + .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]), + .Write (HASH1_Wr[3]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); + +// TXCTRL Register +eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0 + ( + .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]), + .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]), + .Write (TXCTRL_Wr[0]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1 + ( + .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]), + .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]), + .Write (TXCTRL_Wr[1]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (1'b0) + ); +eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset + ( + .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]), + .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]), + .Write (TXCTRL_Wr[2]), + .Clk (Clk), + .Reset (Reset), + .SyncReset (RstTxPauseRq) + ); +assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0; + + + +// Reading data from registers +always @ (Address or Read or MODEROut or INT_SOURCEOut or + INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or + PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or + MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or + MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or + HASH0Out or HASH1Out or TXCTRLOut + ) +begin + if(Read) // read + begin + case(Address) + `ETH_MODER_ADR : DataOut<=MODEROut; + `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; + `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut; + `ETH_IPGT_ADR : DataOut<=IPGTOut; + `ETH_IPGR1_ADR : DataOut<=IPGR1Out; + `ETH_IPGR2_ADR : DataOut<=IPGR2Out; + `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut; + `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut; + `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut; + `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut; + `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; + `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; + `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; + `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; + `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; + `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; + `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; + `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; + `ETH_HASH0_ADR : DataOut<=HASH0Out; + `ETH_HASH1_ADR : DataOut<=HASH1Out; + `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut; + + default: DataOut<=32'h0; + endcase + end + else + DataOut<=32'h0; +end + + +assign r_RecSmall = MODEROut[16]; +assign r_Pad = MODEROut[15]; +assign r_HugEn = MODEROut[14]; +assign r_CrcEn = MODEROut[13]; +assign r_DlyCrcEn = MODEROut[12]; +// assign r_Rst = MODEROut[11]; This signal is not used any more +assign r_FullD = MODEROut[10]; +assign r_ExDfrEn = MODEROut[9]; +assign r_NoBckof = MODEROut[8]; +assign r_LoopBck = MODEROut[7]; +assign r_IFG = MODEROut[6]; +assign r_Pro = MODEROut[5]; +assign r_Iam = MODEROut[4]; +assign r_Bro = MODEROut[3]; +assign r_NoPre = MODEROut[2]; +assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD. +assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD. + +assign r_IPGT[6:0] = IPGTOut[6:0]; + +assign r_IPGR1[6:0] = IPGR1Out[6:0]; + +assign r_IPGR2[6:0] = IPGR2Out[6:0]; + +assign r_MinFL[15:0] = PACKETLENOut[31:16]; +assign r_MaxFL[15:0] = PACKETLENOut[15:0]; + +assign r_MaxRet[3:0] = COLLCONFOut[19:16]; +assign r_CollValid[5:0] = COLLCONFOut[5:0]; + +assign r_TxFlow = CTRLMODEROut[2]; +assign r_RxFlow = CTRLMODEROut[1]; +assign r_PassAll = CTRLMODEROut[0]; + +assign r_MiiNoPre = MIIMODEROut[8]; +assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; + +assign r_WCtrlData = MIICOMMANDOut[2]; +assign r_RStat = MIICOMMANDOut[1]; +assign r_ScanStat = MIICOMMANDOut[0]; + +assign r_RGAD[4:0] = MIIADDRESSOut[12:8]; +assign r_FIAD[4:0] = MIIADDRESSOut[4:0]; + +assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; + +assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0; +assign MIISTATUSOut[2] = NValid_stat ; +assign MIISTATUSOut[1] = Busy_stat ; +assign MIISTATUSOut[0] = LinkFail ; + +assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; +assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; +assign r_HASH1[31:0] = HASH1Out; +assign r_HASH0[31:0] = HASH0Out; + +assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; + +assign r_TxPauseTV[15:0] = TXCTRLOut[15:0]; +assign r_TxPauseRq = TXCTRLOut[16]; + + +// Synchronizing TxC Interrupt +always @ (posedge TxClk or posedge Reset) +begin + if(Reset) + SetTxCIrq_txclk <=#Tp 1'b0; + else + if(TxCtrlEndFrm & StartTxDone & r_TxFlow) + SetTxCIrq_txclk <=#Tp 1'b1; + else + if(ResetTxCIrq_sync2) + SetTxCIrq_txclk <=#Tp 1'b0; +end + + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetTxCIrq_sync1 <=#Tp 1'b0; + else + SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetTxCIrq_sync2 <=#Tp 1'b0; + else + SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetTxCIrq_sync3 <=#Tp 1'b0; + else + SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetTxCIrq <=#Tp 1'b0; + else + SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3; +end + +always @ (posedge TxClk or posedge Reset) +begin + if(Reset) + ResetTxCIrq_sync1 <=#Tp 1'b0; + else + ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2; +end + +always @ (posedge TxClk or posedge Reset) +begin + if(Reset) + ResetTxCIrq_sync2 <=#Tp 1'b0; + else + ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; +end + + +// Synchronizing RxC Interrupt +always @ (posedge RxClk or posedge Reset) +begin + if(Reset) + SetRxCIrq_rxclk <=#Tp 1'b0; + else + if(SetPauseTimer & r_RxFlow) + SetRxCIrq_rxclk <=#Tp 1'b1; + else + if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) + SetRxCIrq_rxclk <=#Tp 1'b0; +end + + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetRxCIrq_sync1 <=#Tp 1'b0; + else + SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetRxCIrq_sync2 <=#Tp 1'b0; + else + SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetRxCIrq_sync3 <=#Tp 1'b0; + else + SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + SetRxCIrq <=#Tp 1'b0; + else + SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3; +end + +always @ (posedge RxClk or posedge Reset) +begin + if(Reset) + ResetRxCIrq_sync1 <=#Tp 1'b0; + else + ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; +end + +always @ (posedge RxClk or posedge Reset) +begin + if(Reset) + ResetRxCIrq_sync2 <=#Tp 1'b0; + else + ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; +end + +always @ (posedge RxClk or posedge Reset) +begin + if(Reset) + ResetRxCIrq_sync3 <=#Tp 1'b0; + else + ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; +end + + + +// Interrupt generation +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_txb <= 1'b0; + else + if(TxB_IRQ) + irq_txb <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[0]) + irq_txb <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_txe <= 1'b0; + else + if(TxE_IRQ) + irq_txe <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[1]) + irq_txe <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_rxb <= 1'b0; + else + if(RxB_IRQ) + irq_rxb <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[2]) + irq_rxb <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_rxe <= 1'b0; + else + if(RxE_IRQ) + irq_rxe <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[3]) + irq_rxe <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_busy <= 1'b0; + else + if(Busy_IRQ) + irq_busy <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[4]) + irq_busy <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_txc <= 1'b0; + else + if(SetTxCIrq) + irq_txc <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[5]) + irq_txc <= #Tp 1'b0; +end + +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + irq_rxc <= 1'b0; + else + if(SetRxCIrq) + irq_rxc <= #Tp 1'b1; + else + if(INT_SOURCE_Wr[0] & DataIn[6]) + irq_rxc <= #Tp 1'b0; +end + +// Generating interrupt signal +assign int_o = irq_txb & INT_MASKOut[0] | + irq_txe & INT_MASKOut[1] | + irq_rxb & INT_MASKOut[2] | + irq_rxe & INT_MASKOut[3] | + irq_busy & INT_MASKOut[4] | + irq_txc & INT_MASKOut[5] | + irq_rxc & INT_MASKOut[6] ; + +// For reading interrupt status +assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb}; + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxaddrcheck.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxaddrcheck.v new file mode 100644 index 000000000..b357cf617 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxaddrcheck.v @@ -0,0 +1,211 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_rxaddrcheck.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/cores/ethmac/ //// +//// //// +//// Author(s): //// +//// - Bill Dittenhofer (billditt@aol.com) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_rxaddrcheck.v,v $ +// Revision 1.9 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.8 2002/11/19 17:34:52 mohor +// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying +// that a frame was received because of the promiscous mode. +// +// Revision 1.7 2002/09/04 18:41:06 mohor +// Bug when last byte of destination address was not checked fixed. +// +// Revision 1.6 2002/03/20 15:14:11 mohor +// When in promiscous mode some frames were not received correctly. Fixed. +// +// Revision 1.5 2002/03/02 21:06:32 mohor +// Log info was missing. +// +// +// Revision 1.1 2002/02/08 12:51:54 ditt +// Initial release of the ethernet addresscheck module. +// +// +// +// +// + + +`include "timescale.v" + + +module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro, + ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5, + ByteCntEq6, ByteCntEq7, HASH0, HASH1, + CrcHash, CrcHashGood, StateData, RxEndFrm, + Multicast, MAC, RxAbort, AddressMiss, PassAll, + ControlFrmAddressOK + ); + +parameter Tp = 1; + + input MRxClk; + input Reset; + input [7:0] RxData; + input Broadcast; + input r_Bro; + input r_Pro; + input ByteCntEq2; + input ByteCntEq3; + input ByteCntEq4; + input ByteCntEq5; + input ByteCntEq6; + input ByteCntEq7; + input [31:0] HASH0; + input [31:0] HASH1; + input [5:0] CrcHash; + input CrcHashGood; + input Multicast; + input [47:0] MAC; + input [1:0] StateData; + input RxEndFrm; + input PassAll; + input ControlFrmAddressOK; + + output RxAbort; + output AddressMiss; + + wire BroadcastOK; + wire ByteCntEq2; + wire ByteCntEq3; + wire ByteCntEq4; + wire ByteCntEq5; + wire RxAddressInvalid; + wire RxCheckEn; + wire HashBit; + wire [31:0] IntHash; + reg [7:0] ByteHash; + reg MulticastOK; + reg UnicastOK; + reg RxAbort; + reg AddressMiss; + +assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro); + +assign BroadcastOK = Broadcast & ~r_Bro; + +assign RxCheckEn = | StateData; + + // Address Error Reported at end of address cycle + // RxAbort clears after one cycle + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxAbort <= #Tp 1'b0; + else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn) + RxAbort <= #Tp 1'b1; + else + RxAbort <= #Tp 1'b0; +end + + +// This ff holds the "Address Miss" information that is written to the RX BD status. +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + AddressMiss <= #Tp 1'b0; + else if(ByteCntEq7 & RxCheckEn) + AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); +end + + +// Hash Address Check, Multicast +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + MulticastOK <= #Tp 1'b0; + else if(RxEndFrm | RxAbort) + MulticastOK <= #Tp 1'b0; + else if(CrcHashGood & Multicast) + MulticastOK <= #Tp HashBit; +end + + +// Address Detection (unicast) +// start with ByteCntEq2 due to delay of addres from RxData +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + UnicastOK <= #Tp 1'b0; + else + if(RxCheckEn & ByteCntEq2) + UnicastOK <= #Tp RxData[7:0] == MAC[47:40]; + else + if(RxCheckEn & ByteCntEq3) + UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK; + else + if(RxCheckEn & ByteCntEq4) + UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK; + else + if(RxCheckEn & ByteCntEq5) + UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK; + else + if(RxCheckEn & ByteCntEq6) + UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK; + else + if(RxCheckEn & ByteCntEq7) + UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK; + else + if(RxEndFrm | RxAbort) + UnicastOK <= #Tp 1'b0; +end + +assign IntHash = (CrcHash[5])? HASH1 : HASH0; + +always@(CrcHash or IntHash) +begin + case(CrcHash[4:3]) + 2'b00: ByteHash = IntHash[7:0]; + 2'b01: ByteHash = IntHash[15:8]; + 2'b10: ByteHash = IntHash[23:16]; + 2'b11: ByteHash = IntHash[31:24]; + endcase +end + +assign HashBit = ByteHash[CrcHash[2:0]]; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxcounters.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxcounters.v new file mode 100644 index 000000000..7ff678e30 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxcounters.v @@ -0,0 +1,221 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_rxcounters.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_rxcounters.v,v $ +// Revision 1.6 2005/02/21 11:00:57 igorm +// Delayed CRC fixed. +// +// Revision 1.5 2002/02/15 11:13:29 mohor +// Format of the file changed a bit. +// +// Revision 1.4 2002/02/14 20:19:41 billditt +// Modified for Address Checking, +// addition of eth_addrcheck.v +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.1 2001/06/27 21:26:19 mohor +// Initial release of the RxEthMAC module. +// +// +// +// +// +// + + +`include "timescale.v" + + +module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble, + MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24, + ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6, + ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut + ); + +parameter Tp = 1; + +input MRxClk; +input Reset; +input MRxDV; +input StateSFD; +input [1:0] StateData; +input MRxDEqD; +input StateIdle; +input StateDrop; +input DlyCrcEn; +input StatePreamble; +input Transmitting; +input HugEn; +input [15:0] MaxFL; +input r_IFG; + +output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns) +output [3:0] DlyCrcCnt; // Delayed CRC counter +output ByteCntEq0; // Byte counter = 0 +output ByteCntEq1; // Byte counter = 1 +output ByteCntEq2; // Byte counter = 2 +output ByteCntEq3; // Byte counter = 3 +output ByteCntEq4; // Byte counter = 4 +output ByteCntEq5; // Byte counter = 5 +output ByteCntEq6; // Byte counter = 6 +output ByteCntEq7; // Byte counter = 7 +output ByteCntGreat2; // Byte counter > 2 +output ByteCntSmall7; // Byte counter < 7 +output ByteCntMaxFrame; // Byte counter = MaxFL +output [15:0] ByteCntOut; // Byte counter + +wire ResetByteCounter; +wire IncrementByteCounter; +wire ResetIFGCounter; +wire IncrementIFGCounter; +wire ByteCntMax; + +reg [15:0] ByteCnt; +reg [3:0] DlyCrcCnt; +reg [4:0] IFGCounter; + +wire [15:0] ByteCntDelayed; + + + +assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame); + +assign IncrementByteCounter = ~ResetByteCounter & MRxDV & + (StatePreamble | StateSFD | StateIdle & ~Transmitting | + StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt) + ); + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ByteCnt[15:0] <= #Tp 16'h0; + else + begin + if(ResetByteCounter) + ByteCnt[15:0] <= #Tp 16'h0; + else + if(IncrementByteCounter) + ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; + end +end + +assign ByteCntDelayed = ByteCnt + 3'h4; +assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt; + +assign ByteCntEq0 = ByteCnt == 16'h0; +assign ByteCntEq1 = ByteCnt == 16'h1; +assign ByteCntEq2 = ByteCnt == 16'h2; +assign ByteCntEq3 = ByteCnt == 16'h3; +assign ByteCntEq4 = ByteCnt == 16'h4; +assign ByteCntEq5 = ByteCnt == 16'h5; +assign ByteCntEq6 = ByteCnt == 16'h6; +assign ByteCntEq7 = ByteCnt == 16'h7; +assign ByteCntGreat2 = ByteCnt > 16'h2; +assign ByteCntSmall7 = ByteCnt < 16'h7; +assign ByteCntMax = ByteCnt == 16'hffff; +assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn; + + +assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop; + +assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24; + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + IFGCounter[4:0] <= #Tp 5'h0; + else + begin + if(ResetIFGCounter) + IFGCounter[4:0] <= #Tp 5'h0; + else + if(IncrementIFGCounter) + IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1; + end +end + + + +assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1 + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + DlyCrcCnt[3:0] <= #Tp 4'h0; + else + begin + if(DlyCrcCnt[3:0] == 4'h9) + DlyCrcCnt[3:0] <= #Tp 4'h0; + else + if(DlyCrcEn & StateSFD) + DlyCrcCnt[3:0] <= #Tp 4'h1; + else + if(DlyCrcEn & (|DlyCrcCnt[3:0])) + DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1; + end +end + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxethmac.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxethmac.v new file mode 100644 index 000000000..c68c805e1 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxethmac.v @@ -0,0 +1,380 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_rxethmac.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_rxethmac.v,v $ +// Revision 1.13 2005/02/21 12:48:07 igorm +// Warning fixes. +// +// Revision 1.12 2004/04/26 15:26:23 igorm +// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the +// previous update of the core. +// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. +// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER +// register. (thanks to Mathias and Torbjorn) +// - Multicast reception was fixed. Thanks to Ulrich Gries +// +// Revision 1.11 2004/03/17 09:32:15 igorm +// Multicast detection fixed. Only the LSB of the first byte is checked. +// +// Revision 1.10 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.9 2002/11/19 17:35:35 mohor +// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying +// that a frame was received because of the promiscous mode. +// +// Revision 1.8 2002/02/16 07:15:27 mohor +// Testbench fixed, code simplified, unused signals removed. +// +// Revision 1.7 2002/02/15 13:44:28 mohor +// RxAbort is an output. No need to have is declared as wire. +// +// Revision 1.6 2002/02/15 11:17:48 mohor +// File format changed. +// +// Revision 1.5 2002/02/14 20:48:43 billditt +// Addition of new module eth_addrcheck.v +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.1 2001/06/27 21:26:19 mohor +// Initial release of the RxEthMAC module. +// +// +// +// +// + +`include "timescale.v" + + +module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn, + RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2, + ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData, + MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK + ); + +parameter Tp = 1; + + + +input MRxClk; +input MRxDV; +input [3:0] MRxD; +input Transmitting; +input HugEn; +input DlyCrcEn; +input [15:0] MaxFL; +input r_IFG; +input Reset; +input [47:0] MAC; // Station Address +input r_Bro; // broadcast disable +input r_Pro; // promiscuous enable +input [31:0] r_HASH0; // lower 4 bytes Hash Table +input [31:0] r_HASH1; // upper 4 bytes Hash Table +input PassAll; +input ControlFrmAddressOK; + +output [7:0] RxData; +output RxValid; +output RxStartFrm; +output RxEndFrm; +output [15:0] ByteCnt; +output ByteCntEq0; +output ByteCntGreat2; +output ByteCntMaxFrame; +output CrcError; +output StateIdle; +output StatePreamble; +output StateSFD; +output [1:0] StateData; +output RxAbort; +output AddressMiss; + +reg [7:0] RxData; +reg RxValid; +reg RxStartFrm; +reg RxEndFrm; +reg Broadcast; +reg Multicast; +reg [5:0] CrcHash; +reg CrcHashGood; +reg DelayData; +reg [7:0] LatchedByte; +reg [7:0] RxData_d; +reg RxValid_d; +reg RxStartFrm_d; +reg RxEndFrm_d; + +wire MRxDEqD; +wire MRxDEq5; +wire StateDrop; +wire ByteCntEq1; +wire ByteCntEq2; +wire ByteCntEq3; +wire ByteCntEq4; +wire ByteCntEq5; +wire ByteCntEq6; +wire ByteCntEq7; +wire ByteCntSmall7; +wire [31:0] Crc; +wire Enable_Crc; +wire Initialize_Crc; +wire [3:0] Data_Crc; +wire GenerateRxValid; +wire GenerateRxStartFrm; +wire GenerateRxEndFrm; +wire DribbleRxEndFrm; +wire [3:0] DlyCrcCnt; +wire IFGCounterEq24; + +assign MRxDEqD = MRxD == 4'hd; +assign MRxDEq5 = MRxD == 4'h5; + + +// Rx State Machine module +eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0), + .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5), + .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame), + .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble), + .StateSFD(StateSFD), .StateDrop(StateDrop) + ); + + +// Rx Counters module +eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle), + .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop), + .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn), + .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG), + .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0), + .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3), + .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6), + .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2), + .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame), + .ByteCntOut(ByteCnt) + ); + +// Rx Address Check + +eth_rxaddrcheck rxaddrcheck1 + (.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), + .Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), + .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2), + .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), + .HASH0(r_HASH0), .HASH1(r_HASH1), + .CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData), + .Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort), + .RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll), + .ControlFrmAddressOK(ControlFrmAddressOK) + ); + + +assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame); +assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9; + +assign Data_Crc[0] = MRxD[3]; +assign Data_Crc[1] = MRxD[2]; +assign Data_Crc[2] = MRxD[1]; +assign Data_Crc[3] = MRxD[0]; + + +// Connecting module Crc +eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), + .Crc(Crc), .CrcError(CrcError) + ); + + + +// Latching CRC for use in the hash table + +always @ (posedge MRxClk) +begin + CrcHashGood <= #Tp StateData[0] & ByteCntEq6; +end + +always @ (posedge MRxClk) +begin + if(Reset | StateIdle) + CrcHash[5:0] <= #Tp 6'h0; + else + if(StateData[0] & ByteCntEq6) + CrcHash[5:0] <= #Tp Crc[31:26]; +end + + +// Output byte stream +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + RxData_d[7:0] <= #Tp 8'h0; + DelayData <= #Tp 1'b0; + LatchedByte[7:0] <= #Tp 8'h0; + RxData[7:0] <= #Tp 8'h0; + end + else + begin + LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte + DelayData <= #Tp StateData[0]; + + if(GenerateRxValid) + RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state + else + if(~DelayData) + RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active. + + RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte + end +end + + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + Broadcast <= #Tp 1'b0; + else + begin + if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7) + Broadcast <= #Tp 1'b0; + else + if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1) + Broadcast <= #Tp 1'b1; + else + if(RxAbort | RxEndFrm) + Broadcast <= #Tp 1'b0; + end +end + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + Multicast <= #Tp 1'b0; + else + begin + if(StateData[0] & ByteCntEq1 & LatchedByte[0]) + Multicast <= #Tp 1'b1; + else if(RxAbort | RxEndFrm) + Multicast <= #Tp 1'b0; + end +end + + +assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3); + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + RxValid_d <= #Tp 1'b0; + RxValid <= #Tp 1'b0; + end + else + begin + RxValid_d <= #Tp GenerateRxValid; + RxValid <= #Tp RxValid_d; + end +end + + +assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn); + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + RxStartFrm_d <= #Tp 1'b0; + RxStartFrm <= #Tp 1'b0; + end + else + begin + RxStartFrm_d <= #Tp GenerateRxStartFrm; + RxStartFrm <= #Tp RxStartFrm_d; + end +end + + +assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame); +assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2; + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + RxEndFrm_d <= #Tp 1'b0; + RxEndFrm <= #Tp 1'b0; + end + else + begin + RxEndFrm_d <= #Tp GenerateRxEndFrm; + RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm; + end +end + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxstatem.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxstatem.v new file mode 100644 index 000000000..783dfe6a4 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_rxstatem.v @@ -0,0 +1,200 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_rxstatem.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_rxstatem.v,v $ +// Revision 1.6 2002/11/13 22:28:26 tadejm +// StartIdle state changed (not important the size of the packet). +// StartData1 activates only while ByteCnt is smaller than the MaxFrame. +// +// Revision 1.5 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.4 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.3 2001/10/18 12:07:11 mohor +// Status signals changed, Adress decoding changed, interrupt controller +// added. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.2 2001/07/03 12:55:41 mohor +// Minor changes because of the synthesys warnings. +// +// +// Revision 1.1 2001/06/27 21:26:19 mohor +// Initial release of the RxEthMAC module. +// +// +// +// + + +`include "timescale.v" + + +module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD, + IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD, + StateDrop + ); + +parameter Tp = 1; + +input MRxClk; +input Reset; +input MRxDV; +input ByteCntEq0; +input ByteCntGreat2; +input MRxDEq5; +input Transmitting; +input MRxDEqD; +input IFGCounterEq24; +input ByteCntMaxFrame; + +output [1:0] StateData; +output StateIdle; +output StateDrop; +output StatePreamble; +output StateSFD; + +reg StateData0; +reg StateData1; +reg StateIdle; +reg StateDrop; +reg StatePreamble; +reg StateSFD; + +wire StartIdle; +wire StartDrop; +wire StartData0; +wire StartData1; +wire StartPreamble; +wire StartSFD; + + +// Defining the next state +assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData)); + +assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting); + +assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble); + +assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1); + +assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame); + +assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD + | StateData0 & ByteCntMaxFrame + ); + +// Rx State Machine +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + StateIdle <= #Tp 1'b0; + StateDrop <= #Tp 1'b1; + StatePreamble <= #Tp 1'b0; + StateSFD <= #Tp 1'b0; + StateData0 <= #Tp 1'b0; + StateData1 <= #Tp 1'b0; + end + else + begin + if(StartPreamble | StartSFD | StartDrop) + StateIdle <= #Tp 1'b0; + else + if(StartIdle) + StateIdle <= #Tp 1'b1; + + if(StartIdle) + StateDrop <= #Tp 1'b0; + else + if(StartDrop) + StateDrop <= #Tp 1'b1; + + if(StartSFD | StartIdle | StartDrop) + StatePreamble <= #Tp 1'b0; + else + if(StartPreamble) + StatePreamble <= #Tp 1'b1; + + if(StartPreamble | StartIdle | StartData0 | StartDrop) + StateSFD <= #Tp 1'b0; + else + if(StartSFD) + StateSFD <= #Tp 1'b1; + + if(StartIdle | StartData1 | StartDrop) + StateData0 <= #Tp 1'b0; + else + if(StartData0) + StateData0 <= #Tp 1'b1; + + if(StartIdle | StartData0 | StartDrop) + StateData1 <= #Tp 1'b0; + else + if(StartData1) + StateData1 <= #Tp 1'b1; + end +end + +assign StateData[1:0] = {StateData1, StateData0}; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_shiftreg.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_shiftreg.v new file mode 100644 index 000000000..9a9ef66ea --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_shiftreg.v @@ -0,0 +1,154 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_shiftreg.v,v $ +// Revision 1.6 2005/03/08 14:45:09 igorm +// Case statement improved for synthesys. +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`include "timescale.v" + + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= #Tp 8'h0; + Prsd[15:0] <= #Tp 16'h0; + LinkFail <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) // synopsys parallel_case full_case + 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; + endcase + end + else + begin + ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_spram_256x32.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_spram_256x32.v new file mode 100644 index 000000000..f1de63a6d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_spram_256x32.v @@ -0,0 +1,312 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_spram_256x32.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is available in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_spram_256x32.v,v $ +// Revision 1.10 2005/02/21 12:48:07 igorm +// Warning fixes. +// +// Revision 1.9 2003/12/05 12:43:06 tadejm +// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. +// +// Revision 1.8 2003/12/04 14:59:13 simons +// Lapsus fixed (!we -> ~we). +// +// Revision 1.7 2003/11/12 18:24:59 tadejm +// WISHBONE slave changed and tested from only 32-bit accesss to byte access. +// +// Revision 1.6 2003/10/17 07:46:15 markom +// mbist signals updated according to newest convention +// +// Revision 1.5 2003/08/14 16:42:58 simons +// Artisan ram instance added. +// +// Revision 1.4 2002/10/18 17:04:20 tadejm +// Changed BIST scan signals. +// +// Revision 1.3 2002/10/10 16:29:30 mohor +// BIST added. +// +// Revision 1.2 2002/09/23 18:24:31 mohor +// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). +// +// Revision 1.1 2002/07/23 16:36:09 mohor +// ethernet spram added. So far a generic ram and xilinx RAMB4 are used. +// +// +// + +`include "eth_defines.v" +`include "timescale.v" + +module eth_spram_256x32( + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, do + +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + + + +); + + // + // Generic synchronous single-port RAM interface + // + input clk; // Clock, rising edge + input rst; // Reset, active high + input ce; // Chip enable input, active high + input [3:0] we; // Write enable input, active high + input oe; // Output enable input, active high + input [7:0] addr; // address bus inputs + input [31:0] di; // input data bus + output [31:0] do; // output data bus + + +`ifdef ETH_BIST + input mbist_si_i; // bist scan serial in + output mbist_so_o; // bist scan serial out + input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +`ifdef ETH_XILINX_RAMB4 + + /*RAMB4_S16 ram0 + ( + .DO (do[15:0]), + .ADDR (addr), + .DI (di[15:0]), + .EN (ce), + .CLK (clk), + .WE (we), + .RST (rst) + ); + + RAMB4_S16 ram1 + ( + .DO (do[31:16]), + .ADDR (addr), + .DI (di[31:16]), + .EN (ce), + .CLK (clk), + .WE (we), + .RST (rst) + );*/ + + RAMB4_S8 ram0 + ( + .DO (do[7:0]), + .ADDR ({1'b0, addr}), + .DI (di[7:0]), + .EN (ce), + .CLK (clk), + .WE (we[0]), + .RST (rst) + ); + + RAMB4_S8 ram1 + ( + .DO (do[15:8]), + .ADDR ({1'b0, addr}), + .DI (di[15:8]), + .EN (ce), + .CLK (clk), + .WE (we[1]), + .RST (rst) + ); + + RAMB4_S8 ram2 + ( + .DO (do[23:16]), + .ADDR ({1'b0, addr}), + .DI (di[23:16]), + .EN (ce), + .CLK (clk), + .WE (we[2]), + .RST (rst) + ); + + RAMB4_S8 ram3 + ( + .DO (do[31:24]), + .ADDR ({1'b0, addr}), + .DI (di[31:24]), + .EN (ce), + .CLK (clk), + .WE (we[3]), + .RST (rst) + ); + +`else // !ETH_XILINX_RAMB4 +`ifdef ETH_VIRTUAL_SILICON_RAM + `ifdef ETH_BIST + //vs_hdsp_256x32_bist ram0_bist + vs_hdsp_256x32_bw_bist ram0_bist + `else + //vs_hdsp_256x32 ram0 + vs_hdsp_256x32_bw ram0 + `endif + ( + .CK (clk), + .CEN (!ce), + .WEN (~we), + .OEN (!oe), + .ADR (addr), + .DI (di), + .DOUT (do) + + `ifdef ETH_BIST + , + // debug chain signals + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) + `endif + ); + +`else // !ETH_VIRTUAL_SILICON_RAM + +`ifdef ETH_ARTISAN_RAM + `ifdef ETH_BIST + //art_hssp_256x32_bist ram0_bist + art_hssp_256x32_bw_bist ram0_bist + `else + //art_hssp_256x32 ram0 + art_hssp_256x32_bw ram0 + `endif + ( + .CLK (clk), + .CEN (!ce), + .WEN (~we), + .OEN (!oe), + .A (addr), + .D (di), + .Q (do) + + `ifdef ETH_BIST + , + // debug chain signals + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) + `endif + ); + +`else // !ETH_ARTISAN_RAM +`ifdef ETH_ALTERA_ALTSYNCRAM + + altera_spram_256x32 altera_spram_256x32_inst + ( + .address (addr), + .wren (ce & we), + .clock (clk), + .data (di), + .q (do) + ); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE + +`else // !ETH_ALTERA_ALTSYNCRAM + + + // + // Generic single-port synchronous RAM model + // + + // + // Generic RAM's registers and wires + // + reg [ 7: 0] mem0 [255:0]; // RAM content + reg [15: 8] mem1 [255:0]; // RAM content + reg [23:16] mem2 [255:0]; // RAM content + reg [31:24] mem3 [255:0]; // RAM content + wire [31:0] q; // RAM output + reg [7:0] raddr; // RAM read address + // + // Data output drivers + // + assign do = (oe & ce) ? q : {32{1'bz}}; + + // + // RAM read and write + // + + // read operation + always@(posedge clk) + if (ce) // && !we) + raddr <= #1 addr; // read address needs to be registered to read clock + + assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]}; + + // write operation + always@(posedge clk) + begin + if (ce && we[3]) + mem3[addr] <= #1 di[31:24]; + if (ce && we[2]) + mem2[addr] <= #1 di[23:16]; + if (ce && we[1]) + mem1[addr] <= #1 di[15: 8]; + if (ce && we[0]) + mem0[addr] <= #1 di[ 7: 0]; + end + + // Task prints range of memory + // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. + task print_ram; + input [7:0] start; + input [7:0] finish; + integer rnum; + begin + for (rnum=start;rnum<=finish;rnum=rnum+1) + $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]); + end + endtask + +`endif // !ETH_ALTERA_ALTSYNCRAM +`endif // !ETH_ARTISAN_RAM +`endif // !ETH_VIRTUAL_SILICON_RAM +`endif // !ETH_XILINX_RAMB4 + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_top.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_top.v new file mode 100644 index 000000000..17185b2c7 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_top.v @@ -0,0 +1,971 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_top.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is available in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_top.v,v $ +// Revision 1.52 2005/03/21 20:07:18 igorm +// Some small fixes + some troubles fixed. +// +// Revision 1.51 2005/02/21 11:13:17 igorm +// Defer indication fixed. +// +// Revision 1.50 2004/04/26 15:26:23 igorm +// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the +// previous update of the core. +// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. +// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER +// register. (thanks to Mathias and Torbjorn) +// - Multicast reception was fixed. Thanks to Ulrich Gries +// +// Revision 1.49 2003/11/12 18:24:59 tadejm +// WISHBONE slave changed and tested from only 32-bit accesss to byte access. +// +// Revision 1.48 2003/10/17 07:46:16 markom +// mbist signals updated according to newest convention +// +// Revision 1.47 2003/10/06 15:43:45 knguyen +// Update RxEnSync only when mrxdv_pad_i is inactive (LOW). +// +// Revision 1.46 2003/01/30 13:30:22 tadejm +// Defer indication changed. +// +// Revision 1.45 2003/01/22 13:49:26 tadejm +// When control packets were received, they were ignored in some cases. +// +// Revision 1.44 2003/01/21 12:09:40 mohor +// When receiving normal data frame and RxFlow control was switched on, RXB +// interrupt was not set. +// +// Revision 1.43 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.42 2002/11/21 00:09:19 mohor +// TPauseRq synchronized to tx_clk. +// +// Revision 1.41 2002/11/19 18:13:49 mohor +// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. +// +// Revision 1.40 2002/11/19 17:34:25 mohor +// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying +// that a frame was received because of the promiscous mode. +// +// Revision 1.39 2002/11/18 17:31:55 mohor +// wb_rst_i is used for MIIM reset. +// +// Revision 1.38 2002/11/14 18:37:20 mohor +// r_Rst signal does not reset any module any more and is removed from the design. +// +// Revision 1.37 2002/11/13 22:25:36 tadejm +// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. +// +// Revision 1.36 2002/10/18 17:04:20 tadejm +// Changed BIST scan signals. +// +// Revision 1.35 2002/10/11 13:36:58 mohor +// Typo error fixed. (When using Bist) +// +// Revision 1.34 2002/10/10 16:49:50 mohor +// Signals for WISHBONE B3 compliant interface added. +// +// Revision 1.33 2002/10/10 16:29:30 mohor +// BIST added. +// +// Revision 1.32 2002/09/20 17:12:58 mohor +// CsMiss added. When address between 0x800 and 0xfff is accessed within +// Ethernet Core, error acknowledge is generated. +// +// Revision 1.31 2002/09/12 14:50:17 mohor +// CarrierSenseLost bug fixed when operating in full duplex mode. +// +// Revision 1.30 2002/09/10 10:35:23 mohor +// Ethernet debug registers removed. +// +// Revision 1.29 2002/09/09 13:03:13 mohor +// Error acknowledge is generated when accessing BDs and RST bit in the +// MODER register (r_Rst) is set. +// +// Revision 1.28 2002/09/04 18:44:10 mohor +// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 +// connected. +// +// Revision 1.27 2002/07/25 18:15:37 mohor +// RxAbort changed. Packets received with MRxErr (from PHY) are also +// aborted. +// +// Revision 1.26 2002/07/17 18:51:50 mohor +// EXTERNAL_DMA removed. External DMA not supported. +// +// Revision 1.25 2002/05/03 10:15:50 mohor +// Outputs registered. Reset changed for eth_wishbone module. +// +// Revision 1.24 2002/04/22 14:15:42 mohor +// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is +// selected in eth_defines.v +// +// Revision 1.23 2002/03/25 13:33:53 mohor +// md_padoen_o changed to md_padoe_o. Signal was always active high, just +// name was incorrect. +// +// Revision 1.22 2002/02/26 16:59:54 mohor +// Small fixes for external/internal DMA missmatches. +// +// Revision 1.21 2002/02/26 16:21:00 mohor +// Interrupts changed in the top file +// +// Revision 1.20 2002/02/18 10:40:17 mohor +// Small fixes. +// +// Revision 1.19 2002/02/16 14:03:44 mohor +// Registered trimmed. Unused registers removed. +// +// Revision 1.18 2002/02/16 13:06:33 mohor +// EXTERNAL_DMA used instead of WISHBONE_DMA. +// +// Revision 1.17 2002/02/16 07:15:27 mohor +// Testbench fixed, code simplified, unused signals removed. +// +// Revision 1.16 2002/02/15 13:49:39 mohor +// RxAbort is connected differently. +// +// Revision 1.15 2002/02/15 11:38:26 mohor +// Changes that were lost when updating from 1.11 to 1.14 fixed. +// +// Revision 1.14 2002/02/14 20:19:11 billditt +// Modified for Address Checking, +// addition of eth_addrcheck.v +// +// Revision 1.13 2002/02/12 17:03:03 mohor +// HASH0 and HASH1 registers added. Registers address width was +// changed to 8 bits. +// +// Revision 1.12 2002/02/11 09:18:22 mohor +// Tx status is written back to the BD. +// +// Revision 1.11 2002/02/08 16:21:54 mohor +// Rx status is written back to the BD. +// +// Revision 1.10 2002/02/06 14:10:21 mohor +// non-DMA host interface added. Select the right configutation in eth_defines. +// +// Revision 1.9 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.8 2001/12/05 15:00:16 mohor +// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors +// instead of the number of RX descriptors). +// +// Revision 1.7 2001/12/05 10:45:59 mohor +// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. +// +// Revision 1.6 2001/10/19 11:24:29 mohor +// Number of addresses (wb_adr_i) minimized. +// +// Revision 1.5 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.4 2001/10/18 12:07:11 mohor +// Status signals changed, Adress decoding changed, interrupt controller +// added. +// +// Revision 1.3 2001/09/24 15:02:56 mohor +// Defines changed (All precede with ETH_). Small changes because some +// tools generate warnings when two operands are together. Synchronization +// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC +// demands). +// +// Revision 1.2 2001/08/15 14:03:59 mohor +// Signal names changed on the top level for easier pad insertion (ASIC). +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// +// +// + + +`include "eth_defines.v" +`include "timescale.v" + + +module eth_top +( + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, + + //RX + mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, + + // MIIM + mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, + + int_o + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +); + + +parameter Tp = 1; + + +// WISHBONE common +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [31:0] wb_dat_i; // WISHBONE data input +output [31:0] wb_dat_o; // WISHBONE data output +output wb_err_o; // WISHBONE error output + +// WISHBONE slave +input [11:2] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input +output wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +input m_wb_err_i; + +wire [29:0] m_wb_adr_tmp; + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +`endif + +// Tx +input mtx_clk_pad_i; // Transmit clock (from PHY) +output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) +output mtxen_pad_o; // Transmit enable (to PHY) +output mtxerr_pad_o; // Transmit error (to PHY) + +// Rx +input mrx_clk_pad_i; // Receive clock (from PHY) +input [3:0] mrxd_pad_i; // Receive nibble (from PHY) +input mrxdv_pad_i; // Receive data valid (from PHY) +input mrxerr_pad_i; // Receive data error (from PHY) + +// Common Tx and Rx +input mcoll_pad_i; // Collision (from PHY) +input mcrs_pad_i; // Carrier sense (from PHY) + +// MII Management interface +input md_pad_i; // MII data input (from I/O cell) +output mdc_pad_o; // MII Management data clock (to PHY) +output md_pad_o; // MII data output (to I/O cell) +output md_padoe_o; // MII data output enable (to I/O cell) + +output int_o; // Interrupt output + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +wire [7:0] r_ClkDiv; +wire r_MiiNoPre; +wire [15:0] r_CtrlData; +wire [4:0] r_FIAD; +wire [4:0] r_RGAD; +wire r_WCtrlData; +wire r_RStat; +wire r_ScanStat; +wire NValid_stat; +wire Busy_stat; +wire LinkFail; +wire [15:0] Prsd; // Read Status Data (data read from the PHY) +wire WCtrlDataStart; +wire RStatStart; +wire UpdateMIIRX_DATAReg; + +wire TxStartFrm; +wire TxEndFrm; +wire TxUsedData; +wire [7:0] TxData; +wire TxRetry; +wire TxAbort; +wire TxUnderRun; +wire TxDone; + + +reg WillSendControlFrame_sync1; +reg WillSendControlFrame_sync2; +reg WillSendControlFrame_sync3; +reg RstTxPauseRq; + +reg TxPauseRq_sync1; +reg TxPauseRq_sync2; +reg TxPauseRq_sync3; +reg TPauseRq; + + +// Connecting Miim module +eth_miim miim1 +( + .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv), + .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD), + .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat), + .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o), + .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat), + .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat), + .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) +); + + + + +wire [3:0] RegCs; // Connected to registers +wire [31:0] RegDataOut; // Multiplexed to wb_dat_o +wire r_RecSmall; // Receive small frames +wire r_LoopBck; // Loopback +wire r_TxEn; // Tx Enable +wire r_RxEn; // Rx Enable + +wire MRxDV_Lb; // Muxed MII receive data valid +wire MRxErr_Lb; // Muxed MII Receive Error +wire [3:0] MRxD_Lb; // Muxed MII Receive Data +wire Transmitting; // Indication that TxEthMAC is transmitting +wire r_HugEn; // Huge packet enable +wire r_DlyCrcEn; // Delayed CRC enabled +wire [15:0] r_MaxFL; // Maximum frame length + +wire [15:0] r_MinFL; // Minimum frame length +wire ShortFrame; +wire DribbleNibble; // Extra nibble received +wire ReceivedPacketTooBig; // Received packet is too big +wire [47:0] r_MAC; // MAC address +wire LoadRxStatus; // Rx status was loaded +wire [31:0] r_HASH0; // HASH table, lower 4 bytes +wire [31:0] r_HASH1; // HASH table, upper 4 bytes +wire [7:0] r_TxBDNum; // Receive buffer descriptor number +wire [6:0] r_IPGT; // +wire [6:0] r_IPGR1; // +wire [6:0] r_IPGR2; // +wire [5:0] r_CollValid; // +wire [15:0] r_TxPauseTV; // Transmit PAUSE value +wire r_TxPauseRq; // Transmit PAUSE request + +wire [3:0] r_MaxRet; // +wire r_NoBckof; // +wire r_ExDfrEn; // +wire r_TxFlow; // Tx flow control enable +wire r_IFG; // Minimum interframe gap for incoming packets + +wire TxB_IRQ; // Interrupt Tx Buffer +wire TxE_IRQ; // Interrupt Tx Error +wire RxB_IRQ; // Interrupt Rx Buffer +wire RxE_IRQ; // Interrupt Rx Error +wire Busy_IRQ; // Interrupt Busy (lack of buffers) + +//wire DWord; +wire ByteSelected; +wire BDAck; +wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write) +wire [3:0] BDCs; // Buffer descriptor CS +wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set + // but data is not valid. +wire r_Pad; +wire r_CrcEn; +wire r_FullD; +wire r_Pro; +wire r_Bro; +wire r_NoPre; +wire r_RxFlow; +wire r_PassAll; +wire TxCtrlEndFrm; +wire StartTxDone; +wire SetPauseTimer; +wire TxUsedDataIn; +wire TxDoneIn; +wire TxAbortIn; +wire PerPacketPad; +wire PadOut; +wire PerPacketCrcEn; +wire CrcEnOut; +wire TxStartFrmOut; +wire TxEndFrmOut; +wire ReceivedPauseFrm; +wire ControlFrmAddressOK; +wire RxStatusWriteLatched_sync2; +wire LateCollision; +wire DeferIndication; +wire LateCollLatched; +wire DeferLatched; +wire RstDeferLatched; +wire CarrierSenseLost; + +wire temp_wb_ack_o; +wire [31:0] temp_wb_dat_o; +wire temp_wb_err_o; + +`ifdef ETH_REGISTERED_OUTPUTS + reg temp_wb_ack_o_reg; + reg [31:0] temp_wb_dat_o_reg; + reg temp_wb_err_o_reg; +`endif + +//assign DWord = &wb_sel_i; +assign ByteSelected = |wb_sel_i; +assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF +assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF +assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF +assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF +assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF +assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF +assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF +assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF +assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF +assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O; +assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss); + +`ifdef ETH_REGISTERED_OUTPUTS + assign wb_ack_o = temp_wb_ack_o_reg; + assign wb_dat_o[31:0] = temp_wb_dat_o_reg; + assign wb_err_o = temp_wb_err_o_reg; +`else + assign wb_ack_o = temp_wb_ack_o; + assign wb_dat_o[31:0] = temp_wb_dat_o; + assign wb_err_o = temp_wb_err_o; +`endif + +`ifdef ETH_AVALON_BUS + // As Avalon has no corresponding "error" signal, I (erroneously) will + // send an ack to Avalon, even when accessing undefined memory. This + // is a grey area in Avalon vs. Wishbone specs: My understanding + // is that Avalon expects all memory addressable by the addr bus feeding + // a slave to be, at the very minimum, readable. + assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss; +`else // WISHBONE + assign temp_wb_ack_o = (|RegCs) | BDAck; +`endif + +`ifdef ETH_REGISTERED_OUTPUTS + always @ (posedge wb_clk_i or posedge wb_rst_i) + begin + if(wb_rst_i) + begin + temp_wb_ack_o_reg <=#Tp 1'b0; + temp_wb_dat_o_reg <=#Tp 32'h0; + temp_wb_err_o_reg <=#Tp 1'b0; + end + else + begin + temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg; + temp_wb_dat_o_reg <=#Tp temp_wb_dat_o; + temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg; + end + end +`endif + + +// Connecting Ethernet registers +eth_registers ethreg1 +( + .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i), + .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i), + .DataOut(RegDataOut), .r_RecSmall(r_RecSmall), + .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn), + .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD), + .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck), + .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(), + .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn), + .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), + .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), + .r_IPGT(r_IPGT), + .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL), + .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid), + .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll), + .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv), + .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat), + .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData), + .NValid_stat(NValid_stat), .Busy_stat(Busy_stat), + .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart), + .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd), + .r_TxBDNum(r_TxBDNum), .int_o(int_o), + .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq), + .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm), + .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i), + .SetPauseTimer(SetPauseTimer) + +); + + + +wire [7:0] RxData; +wire RxValid; +wire RxStartFrm; +wire RxEndFrm; +wire RxAbort; + +wire WillTransmit; // Will transmit (to RxEthMAC) +wire ResetCollision; // Reset Collision (for synchronizing collision) +wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) +wire WillSendControlFrame; +wire ReceiveEnd; +wire ReceivedPacketGood; +wire ReceivedLengthOK; +wire InvalidSymbol; +wire LatchedCrcError; +wire RxLateCollision; +wire [3:0] RetryCntLatched; +wire [3:0] RetryCnt; +wire StartTxAbort; +wire MaxCollisionOccured; +wire RetryLimit; +wire StatePreamble; +wire [1:0] StateData; + +// Connecting MACControl +eth_maccontrol maccontrol1 +( + .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq), + .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData), + .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm), + .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn), + .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i), + .RxData(RxData), .RxValid(RxValid), + .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), + .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), + .TxFlow(r_TxFlow), + .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn), + .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad), + .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn), + .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i), + .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK), + .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut), + .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData), + .TxDoneOut(TxDone), .TxAbortOut(TxAbort), + .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm), + .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK), + .SetPauseTimer(SetPauseTimer), + .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll) +); + + + +wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock) +wire Collision; // Synchronized Collision + +reg CarrierSense_Tx1; +reg CarrierSense_Tx2; +reg Collision_Tx1; +reg Collision_Tx2; + +reg RxEnSync; // Synchronized Receive Enable +reg WillTransmit_q; +reg WillTransmit_q2; + + + +// Muxed MII receive data valid +assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync; + +// Muxed MII Receive Error +assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync; + +// Muxed MII Receive Data +assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0]; + + + +// Connecting TxEthMAC +eth_txethmac txethmac1 +( + .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense), + .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut), + .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut), + .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD), + .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT), + .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid), + .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn), + .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o), + .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn), + .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit), + .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone), + .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision), + .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData) +); + + + + +wire [15:0] RxByteCnt; +wire RxByteCntEq0; +wire RxByteCntGreat2; +wire RxByteCntMaxFrame; +wire RxCrcError; +wire RxStateIdle; +wire RxStatePreamble; +wire RxStateSFD; +wire [1:0] RxStateData; +wire AddressMiss; + + + +// Connecting RxEthMAC +eth_rxethmac rxethmac1 +( + .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb), + .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), + .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i), + .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm), + .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt), + .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame), + .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble), + .StateSFD(RxStateSFD), .StateData(RxStateData), + .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro), + .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort), + .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK) +); + + +// MII Carrier Sense Synchronization +always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + CarrierSense_Tx1 <= #Tp 1'b0; + CarrierSense_Tx2 <= #Tp 1'b0; + end + else + begin + CarrierSense_Tx1 <= #Tp mcrs_pad_i; + CarrierSense_Tx2 <= #Tp CarrierSense_Tx1; + end +end + +assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2; + + +// MII Collision Synchronization +always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + Collision_Tx1 <= #Tp 1'b0; + Collision_Tx2 <= #Tp 1'b0; + end + else + begin + Collision_Tx1 <= #Tp mcoll_pad_i; + if(ResetCollision) + Collision_Tx2 <= #Tp 1'b0; + else + if(Collision_Tx1) + Collision_Tx2 <= #Tp 1'b1; + end +end + + +// Synchronized Collision +assign Collision = ~r_FullD & Collision_Tx2; + + + +// Delayed WillTransmit +always @ (posedge mrx_clk_pad_i) +begin + WillTransmit_q <= #Tp WillTransmit; + WillTransmit_q2 <= #Tp WillTransmit_q; +end + + +assign Transmitting = ~r_FullD & WillTransmit_q2; + + + +// Synchronized Receive Enable +always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + RxEnSync <= #Tp 1'b0; + else + if(~mrxdv_pad_i) + RxEnSync <= #Tp r_RxEn; +end + + + +// Synchronizing WillSendControlFrame to WB_CLK; +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + WillSendControlFrame_sync1 <= 1'b0; + else + WillSendControlFrame_sync1 <=#Tp WillSendControlFrame; +end + +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + WillSendControlFrame_sync2 <= 1'b0; + else + WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1; +end + +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + WillSendControlFrame_sync3 <= 1'b0; + else + WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2; +end + +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + RstTxPauseRq <= 1'b0; + else + RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3; +end + + + + +// TX Pause request Synchronization +always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + TxPauseRq_sync1 <= #Tp 1'b0; + TxPauseRq_sync2 <= #Tp 1'b0; + TxPauseRq_sync3 <= #Tp 1'b0; + end + else + begin + TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow); + TxPauseRq_sync2 <= #Tp TxPauseRq_sync1; + TxPauseRq_sync3 <= #Tp TxPauseRq_sync2; + end +end + + +always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + TPauseRq <= #Tp 1'b0; + else + TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3); +end + + +wire LatchedMRxErr; +reg RxAbort_latch; +reg RxAbort_sync1; +reg RxAbort_wb; +reg RxAbortRst_sync1; +reg RxAbortRst; + +// Synchronizing RxAbort to the WISHBONE clock +always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + RxAbort_latch <= #Tp 1'b0; + else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))) + RxAbort_latch <= #Tp 1'b1; + else if(RxAbortRst) + RxAbort_latch <= #Tp 1'b0; +end + +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + RxAbort_sync1 <= #Tp 1'b0; + RxAbort_wb <= #Tp 1'b0; + RxAbort_wb <= #Tp 1'b0; + end + else + begin + RxAbort_sync1 <= #Tp RxAbort_latch; + RxAbort_wb <= #Tp RxAbort_sync1; + end +end + +always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + RxAbortRst_sync1 <= #Tp 1'b0; + RxAbortRst <= #Tp 1'b0; + end + else + begin + RxAbortRst_sync1 <= #Tp RxAbort_wb; + RxAbortRst <= #Tp RxAbortRst_sync1; + end +end + + + +// Connecting Wishbone module +eth_wishbone wishbone +( + .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i), + .WB_DAT_O(BD_WB_DAT_O), + + // WISHBONE slave + .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i), + .BDCs(BDCs), .WB_ACK_O(BDAck), + + .Reset(wb_rst_i), + + // WISHBONE master + .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), + .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), + .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i), + +`ifdef ETH_WISHBONE_B3 + .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o), +`endif + + + //TX + .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), + .TxUsedData(TxUsedData), .TxData(TxData), + .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun), + .TxDone(TxDone), + .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), + + // Register + .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum), + .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll), + + //RX + .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid), + .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), + .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ), + .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ), + + .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), + + .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt), + .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble), + .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched), + .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched), + .RstDeferLatched(RstDeferLatched), + .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss), + .ReceivedPauseFrm(ReceivedPauseFrm) + +`ifdef ETH_BIST + , + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +); + +assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; + +// Connecting MacStatus module +eth_macstatus macstatus1 +( + .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i), + .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), + .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb), + .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble), + .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt), + .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame), + .InvalidSymbol(InvalidSymbol), + .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i), + .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall), + .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame), + .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn), + .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone), + .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i), + .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision), + .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched), + .RstDeferLatched(RstDeferLatched), + .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData), + .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn), + .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD) +); + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_transmitcontrol.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_transmitcontrol.v new file mode 100644 index 000000000..34984182a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_transmitcontrol.v @@ -0,0 +1,330 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_transmitcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_transmitcontrol.v,v $ +// Revision 1.6 2002/11/21 00:16:14 mohor +// When TxUsedData and CtrlMux occur at the same time, byte counter needs +// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason. +// +// Revision 1.5 2002/11/19 17:37:32 mohor +// When control frame (PAUSE) was sent, status was written in the +// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. +// Only TXC interrupt is set. +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.1 2001/07/03 12:51:54 mohor +// Initial release of the MAC Control module. +// +// +// +// +// +// + + +`include "timescale.v" + + +module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn, + TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn, + TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux, + ControlData, WillSendControlFrame, BlockTxDone + ); + +parameter Tp = 1; + + +input MTxClk; +input TxReset; +input TxUsedDataIn; +input TxUsedDataOut; +input TxDoneIn; +input TxAbortIn; +input TxStartFrmIn; +input TPauseRq; +input TxUsedDataOutDetected; +input TxFlow; +input DlyCrcEn; +input [15:0] TxPauseTV; +input [47:0] MAC; + +output TxCtrlStartFrm; +output TxCtrlEndFrm; +output SendingCtrlFrm; +output CtrlMux; +output [7:0] ControlData; +output WillSendControlFrame; +output BlockTxDone; + +reg SendingCtrlFrm; +reg CtrlMux; +reg WillSendControlFrame; +reg [3:0] DlyCrcCnt; +reg [5:0] ByteCnt; +reg ControlEnd_q; +reg [7:0] MuxedCtrlData; +reg TxCtrlStartFrm; +reg TxCtrlStartFrm_q; +reg TxCtrlEndFrm; +reg [7:0] ControlData; +reg TxUsedDataIn_q; +reg BlockTxDone; + +wire IncrementDlyCrcCnt; +wire ResetByteCnt; +wire IncrementByteCnt; +wire ControlEnd; +wire IncrementByteCntBy2; +wire EnableCnt; + + +// A command for Sending the control frame is active (latched) +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + WillSendControlFrame <= #Tp 1'b0; + else + if(TxCtrlEndFrm & CtrlMux) + WillSendControlFrame <= #Tp 1'b0; + else + if(TPauseRq & TxFlow) + WillSendControlFrame <= #Tp 1'b1; +end + + +// Generation of the transmit control packet start frame +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + TxCtrlStartFrm <= #Tp 1'b0; + else + if(TxUsedDataIn_q & CtrlMux) + TxCtrlStartFrm <= #Tp 1'b0; + else + if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected))) + TxCtrlStartFrm <= #Tp 1'b1; +end + + + +// Generation of the transmit control packet end frame +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + TxCtrlEndFrm <= #Tp 1'b0; + else + if(ControlEnd | ControlEnd_q) + TxCtrlEndFrm <= #Tp 1'b1; + else + TxCtrlEndFrm <= #Tp 1'b0; +end + + +// Generation of the multiplexer signal (controls muxes for switching between +// normal and control packets) +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + CtrlMux <= #Tp 1'b0; + else + if(WillSendControlFrame & ~TxUsedDataOut) + CtrlMux <= #Tp 1'b1; + else + if(TxDoneIn) + CtrlMux <= #Tp 1'b0; +end + + + +// Generation of the Sending Control Frame signal (enables padding and CRC) +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + SendingCtrlFrm <= #Tp 1'b0; + else + if(WillSendControlFrame & TxCtrlStartFrm) + SendingCtrlFrm <= #Tp 1'b1; + else + if(TxDoneIn) + SendingCtrlFrm <= #Tp 1'b0; +end + + +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + TxUsedDataIn_q <= #Tp 1'b0; + else + TxUsedDataIn_q <= #Tp TxUsedDataIn; +end + + + +// Generation of the signal that will block sending the Done signal to the eth_wishbone module +// While sending the control frame +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + BlockTxDone <= #Tp 1'b0; + else + if(TxCtrlStartFrm) + BlockTxDone <= #Tp 1'b1; + else + if(TxStartFrmIn) + BlockTxDone <= #Tp 1'b0; +end + + +always @ (posedge MTxClk) +begin + ControlEnd_q <= #Tp ControlEnd; + TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm; +end + + +assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2]; + + +// Delayed CRC counter +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + DlyCrcCnt <= #Tp 4'h0; + else + if(ResetByteCnt) + DlyCrcCnt <= #Tp 4'h0; + else + if(IncrementDlyCrcCnt) + DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; +end + + +assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn)); +assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd); +assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time + +assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])); +// Byte counter +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + ByteCnt <= #Tp 6'h0; + else + if(ResetByteCnt) + ByteCnt <= #Tp 6'h0; + else + if(IncrementByteCntBy2 & EnableCnt) + ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2; + else + if(IncrementByteCnt & EnableCnt) + ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1; +end + + +assign ControlEnd = ByteCnt[5:0] == 6'h22; + + +// Control data generation (goes to the TxEthMAC module) +always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt) +begin + case(ByteCnt) + 6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])) + MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address + else + MuxedCtrlData[7:0] = 8'h0; + 6'h2: MuxedCtrlData[7:0] = 8'h80; + 6'h4: MuxedCtrlData[7:0] = 8'hC2; + 6'h6: MuxedCtrlData[7:0] = 8'h00; + 6'h8: MuxedCtrlData[7:0] = 8'h00; + 6'hA: MuxedCtrlData[7:0] = 8'h01; + 6'hC: MuxedCtrlData[7:0] = MAC[47:40]; + 6'hE: MuxedCtrlData[7:0] = MAC[39:32]; + 6'h10: MuxedCtrlData[7:0] = MAC[31:24]; + 6'h12: MuxedCtrlData[7:0] = MAC[23:16]; + 6'h14: MuxedCtrlData[7:0] = MAC[15:8]; + 6'h16: MuxedCtrlData[7:0] = MAC[7:0]; + 6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length + 6'h1A: MuxedCtrlData[7:0] = 8'h08; + 6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode + 6'h1E: MuxedCtrlData[7:0] = 8'h01; + 6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value + 6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0]; + default: MuxedCtrlData[7:0] = 8'h0; + endcase +end + + +// Latched Control data +always @ (posedge MTxClk or posedge TxReset) +begin + if(TxReset) + ControlData[7:0] <= #Tp 8'h0; + else + if(~ByteCnt[0]) + ControlData[7:0] <= #Tp MuxedCtrlData[7:0]; +end + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txcounters.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txcounters.v new file mode 100644 index 000000000..ef2c20aa1 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txcounters.v @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_txcounters.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_txcounters.v,v $ +// Revision 1.6 2005/02/21 11:25:27 igorm +// Delayed CRC fixed. +// +// Revision 1.5 2002/04/22 14:54:14 mohor +// FCS should not be included in NibbleMinFl. +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.4 2001/06/27 21:27:45 mohor +// Few typos fixed. +// +// Revision 1.2 2001/06/19 10:38:07 mohor +// Minor changes in header. +// +// Revision 1.1 2001/06/19 10:27:57 mohor +// TxEthMAC initial release. +// +// +// + + +`include "timescale.v" + + +module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam, + StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS, + StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn, + ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt, + ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt + ); + +parameter Tp = 1; + +input MTxClk; // Tx clock +input Reset; // Reset +input StatePreamble; // Preamble state +input StateIPG; // IPG state +input [1:0] StateData; // Data state +input StatePAD; // PAD state +input StateFCS; // FCS state +input StateJam; // Jam state +input StateBackOff; // Backoff state +input StateDefer; // Defer state +input StateIdle; // Idle state +input StateSFD; // SFD state +input StartDefer; // Defer state will be activated in next clock +input StartIPG; // IPG state will be activated in next clock +input StartFCS; // FCS state will be activated in next clock +input StartJam; // Jam state will be activated in next clock +input StartBackoff; // Backoff state will be activated in next clock +input TxStartFrm; // Tx start frame +input [15:0] MinFL; // Minimum frame length (in bytes) +input [15:0] MaxFL; // Miximum frame length (in bytes) +input HugEn; // Pakets bigger then MaxFL enabled +input ExDfrEn; // Excessive deferral enabled +input PacketFinished_q; +input DlyCrcEn; // Delayed CRC enabled + +output [15:0] ByteCnt; // Byte counter +output [15:0] NibCnt; // Nibble counter +output ExcessiveDefer; // Excessive Deferral occuring +output NibCntEq7; // Nibble counter is equal to 7 +output NibCntEq15; // Nibble counter is equal to 15 +output MaxFrame; // Maximum frame occured +output NibbleMinFl; // Nibble counter is greater than the minimum frame length +output [2:0] DlyCrcCnt; // Delayed CRC Count + +wire ExcessiveDeferCnt; +wire ResetNibCnt; +wire IncrementNibCnt; +wire ResetByteCnt; +wire IncrementByteCnt; +wire ByteCntMax; + +reg [15:0] NibCnt; +reg [15:0] ByteCnt; +reg [2:0] DlyCrcCnt; + + + +assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD + | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm; + + +assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15 + | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam; + +// Nibble Counter +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + NibCnt <= #Tp 16'h0; + else + begin + if(ResetNibCnt) + NibCnt <= #Tp 16'h0; + else + if(IncrementNibCnt) + NibCnt <= #Tp NibCnt + 1'b1; + end +end + + +assign NibCntEq7 = &NibCnt[2:0]; +assign NibCntEq15 = &NibCnt[3:0]; + +assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl + +assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7; + +assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles + +assign IncrementByteCnt = StateData[1] & ~ByteCntMax + | StateBackOff & (&NibCnt[6:0]) + | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax; + +assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q; + + +// Transmit Byte Counter +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ByteCnt[15:0] <= #Tp 16'h0; + else + begin + if(ResetByteCnt) + ByteCnt[15:0] <= #Tp 16'h0; + else + if(IncrementByteCnt) + ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; + end +end + + +assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn; + +assign ByteCntMax = &ByteCnt[15:0]; + + +// Delayed CRC counter +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + DlyCrcCnt <= #Tp 3'h0; + else + begin + if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q) + DlyCrcCnt <= #Tp 3'h0; + else + if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0]))) + DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; + end +end + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txethmac.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txethmac.v new file mode 100644 index 000000000..eaa903741 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txethmac.v @@ -0,0 +1,495 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_txethmac.v //// +/// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_txethmac.v,v $ +// Revision 1.9 2005/02/21 11:25:28 igorm +// Delayed CRC fixed. +// +// Revision 1.8 2003/01/30 13:33:24 mohor +// When padding was enabled and crc disabled, frame was not ended correctly. +// +// Revision 1.7 2002/02/26 16:24:01 mohor +// RetryCntLatched was unused and removed from design +// +// Revision 1.6 2002/02/22 12:56:35 mohor +// Retry is not activated when a Tx Underrun occured +// +// Revision 1.5 2002/02/11 09:18:22 mohor +// Tx status is written back to the BD. +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/19 18:16:40 mohor +// TxClk changed to MTxClk (as discribed in the documentation). +// Crc changed so only one file can be used instead of two. +// +// Revision 1.2 2001/06/19 10:38:08 mohor +// Minor changes in header. +// +// Revision 1.1 2001/06/19 10:27:58 mohor +// TxEthMAC initial release. +// +// +// + +`include "timescale.v" + + +module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense, + Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT, + IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn, + MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit, + ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured, + LateCollision, DeferIndication, StatePreamble, StateData + + ); + +parameter Tp = 1; + + +input MTxClk; // Transmit clock (from PHY) +input Reset; // Reset +input TxStartFrm; // Transmit packet start frame +input TxEndFrm; // Transmit packet end frame +input TxUnderRun; // Transmit packet under-run +input [7:0] TxData; // Transmit packet data byte +input CarrierSense; // Carrier sense (synchronized) +input Collision; // Collision (synchronized) +input Pad; // Pad enable (from register) +input CrcEn; // Crc enable (from register) +input FullD; // Full duplex (from register) +input HugEn; // Huge packets enable (from register) +input DlyCrcEn; // Delayed Crc enabled (from register) +input [15:0] MinFL; // Minimum frame length (from register) +input [15:0] MaxFL; // Maximum frame length (from register) +input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register) +input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register) +input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register) +input [5:0] CollValid; // Valid collision window (from register) +input [3:0] MaxRet; // Maximum retry number (from register) +input NoBckof; // No backoff (from register) +input ExDfrEn; // Excessive defferal enable (from register) + +output [3:0] MTxD; // Transmit nibble (to PHY) +output MTxEn; // Transmit enable (to PHY) +output MTxErr; // Transmit error (to PHY) +output TxDone; // Transmit packet done (to RISC) +output TxRetry; // Transmit packet retry (to RISC) +output TxAbort; // Transmit packet abort (to RISC) +output TxUsedData; // Transmit packet used data (to RISC) +output WillTransmit; // Will transmit (to RxEthMAC) +output ResetCollision; // Reset Collision (for synchronizing collision) +output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes +output StartTxDone; +output StartTxAbort; +output MaxCollisionOccured; +output LateCollision; +output DeferIndication; +output StatePreamble; +output [1:0] StateData; + +reg [3:0] MTxD; +reg MTxEn; +reg MTxErr; +reg TxDone; +reg TxRetry; +reg TxAbort; +reg TxUsedData; +reg WillTransmit; +reg ColWindow; +reg StopExcessiveDeferOccured; +reg [3:0] RetryCnt; +reg [3:0] MTxD_d; +reg StatusLatch; +reg PacketFinished_q; +reg PacketFinished; + + +wire ExcessiveDeferOccured; +wire StartIPG; +wire StartPreamble; +wire [1:0] StartData; +wire StartFCS; +wire StartJam; +wire StartDefer; +wire StartBackoff; +wire StateDefer; +wire StateIPG; +wire StateIdle; +wire StatePAD; +wire StateFCS; +wire StateJam; +wire StateJam_q; +wire StateBackOff; +wire StateSFD; +wire StartTxRetry; +wire UnderRun; +wire TooBig; +wire [31:0] Crc; +wire CrcError; +wire [2:0] DlyCrcCnt; +wire [15:0] NibCnt; +wire NibCntEq7; +wire NibCntEq15; +wire NibbleMinFl; +wire ExcessiveDefer; +wire [15:0] ByteCnt; +wire MaxFrame; +wire RetryMax; +wire RandomEq0; +wire RandomEqByteCnt; +wire PacketFinished_d; + + + +assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS); + +assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured; + +assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn); + +assign UnderRun = StateData[0] & TxUnderRun & ~Collision; + +assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS); + +// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax); +assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun; + +assign LateCollision = StartJam & ~ColWindow & ~UnderRun; + +assign MaxCollisionOccured = StartJam & ColWindow & RetryMax; + +assign StateSFD = StatePreamble & NibCntEq15; + +assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured; + + +// StopExcessiveDeferOccured +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + StopExcessiveDeferOccured <= #Tp 1'b0; + else + begin + if(~TxStartFrm) + StopExcessiveDeferOccured <= #Tp 1'b0; + else + if(ExcessiveDeferOccured) + StopExcessiveDeferOccured <= #Tp 1'b1; + end +end + + +// Collision Window +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ColWindow <= #Tp 1'b1; + else + begin + if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0])) + ColWindow <= #Tp 1'b0; + else + if(StateIdle | StateIPG) + ColWindow <= #Tp 1'b1; + end +end + + +// Start Window +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + StatusLatch <= #Tp 1'b0; + else + begin + if(~TxStartFrm) + StatusLatch <= #Tp 1'b0; + else + if(ExcessiveDeferOccured | StateIdle) + StatusLatch <= #Tp 1'b1; + end +end + + +// Transmit packet used data +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxUsedData <= #Tp 1'b0; + else + TxUsedData <= #Tp |StartData; +end + + +// Transmit packet done +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxDone <= #Tp 1'b0; + else + begin + if(TxStartFrm & ~StatusLatch) + TxDone <= #Tp 1'b0; + else + if(StartTxDone) + TxDone <= #Tp 1'b1; + end +end + + +// Transmit packet retry +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxRetry <= #Tp 1'b0; + else + begin + if(TxStartFrm & ~StatusLatch) + TxRetry <= #Tp 1'b0; + else + if(StartTxRetry) + TxRetry <= #Tp 1'b1; + end +end + + +// Transmit packet abort +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxAbort <= #Tp 1'b0; + else + begin + if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured) + TxAbort <= #Tp 1'b0; + else + if(StartTxAbort) + TxAbort <= #Tp 1'b1; + end +end + + +// Retry counter +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + RetryCnt[3:0] <= #Tp 4'h0; + else + begin + if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun + | StateJam & NibCntEq7 & (~ColWindow | RetryMax)) + RetryCnt[3:0] <= #Tp 4'h0; + else + if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt) + RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1; + end +end + + +assign RetryMax = RetryCnt[3:0] == MaxRet[3:0]; + + +// Transmit nibble +always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or + Crc or NibCntEq15) +begin + if(StateData[0]) + MTxD_d[3:0] = TxData[3:0]; // Lower nibble + else + if(StateData[1]) + MTxD_d[3:0] = TxData[7:4]; // Higher nibble + else + if(StateFCS) + MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc + else + if(StateJam) + MTxD_d[3:0] = 4'h9; // Jam pattern + else + if(StatePreamble) + if(NibCntEq15) + MTxD_d[3:0] = 4'hd; // SFD + else + MTxD_d[3:0] = 4'h5; // Preamble + else + MTxD_d[3:0] = 4'h0; +end + + +// Transmit Enable +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + MTxEn <= #Tp 1'b0; + else + MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; +end + + +// Transmit nibble +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + MTxD[3:0] <= #Tp 4'h0; + else + MTxD[3:0] <= #Tp MTxD_d[3:0]; +end + + +// Transmit error +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + MTxErr <= #Tp 1'b0; + else + MTxErr <= #Tp TooBig | UnderRun; +end + + +// WillTransmit +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + WillTransmit <= #Tp 1'b0; + else + WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; +end + + +assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured; + + +// Packet finished +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + begin + PacketFinished <= #Tp 1'b0; + PacketFinished_q <= #Tp 1'b0; + end + else + begin + PacketFinished <= #Tp PacketFinished_d; + PacketFinished_q <= #Tp PacketFinished; + end +end + + +// Connecting module Counters +eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), + .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff), + .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG), + .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk), + .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn), + .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff), + .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer), + .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl), + .DlyCrcCnt(DlyCrcCnt) + ); + + +// Connecting module StateM +eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), + .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD), + .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision), + .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7), + .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn), + .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax), + .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle), + .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD), + .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff), + .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff), + .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG) + ); + + +wire Enable_Crc; +wire [3:0] Data_Crc; +wire Initialize_Crc; + +assign Enable_Crc = ~StateFCS; + +assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0; +assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0; +assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0; +assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0; + +assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt); + + +// Connecting module Crc +eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), + .Crc(Crc), .CrcError(CrcError) + ); + + +// Connecting module Random +eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), + .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt)); + + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txstatem.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txstatem.v new file mode 100644 index 000000000..17136a99e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_txstatem.v @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_txstatem.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// +//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_txstatem.v,v $ +// Revision 1.6 2003/01/30 13:29:08 tadejm +// Defer indication changed. +// +// Revision 1.5 2002/10/30 12:54:50 mohor +// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. +// +// Revision 1.4 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.3 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.2 2001/09/11 14:17:00 mohor +// Few little NCSIM warnings fixed. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/19 18:16:40 mohor +// TxClk changed to MTxClk (as discribed in the documentation). +// Crc changed so only one file can be used instead of two. +// +// Revision 1.2 2001/06/19 10:38:07 mohor +// Minor changes in header. +// +// Revision 1.1 2001/06/19 10:27:57 mohor +// TxEthMAC initial release. +// +// +// +// + + +`include "timescale.v" + + +module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1, + IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun, + StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn, + NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt, + StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS, + StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam, + StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG + ); + +parameter Tp = 1; + +input MTxClk; +input Reset; +input ExcessiveDefer; +input CarrierSense; +input [6:0] NibCnt; +input [6:0] IPGT; +input [6:0] IPGR1; +input [6:0] IPGR2; +input FullD; +input TxStartFrm; +input TxEndFrm; +input TxUnderRun; +input Collision; +input UnderRun; +input StartTxDone; +input TooBig; +input NibCntEq7; +input NibCntEq15; +input MaxFrame; +input Pad; +input CrcEn; +input NibbleMinFl; +input RandomEq0; +input ColWindow; +input RetryMax; +input NoBckof; +input RandomEqByteCnt; + + +output StateIdle; // Idle state +output StateIPG; // IPG state +output StatePreamble; // Preamble state +output [1:0] StateData; // Data state +output StatePAD; // PAD state +output StateFCS; // FCS state +output StateJam; // Jam state +output StateJam_q; // Delayed Jam state +output StateBackOff; // Backoff state +output StateDefer; // Defer state + +output StartFCS; // FCS state will be activated in next clock +output StartJam; // Jam state will be activated in next clock +output StartBackoff; // Backoff state will be activated in next clock +output StartDefer; // Defer state will be activated in next clock +output DeferIndication; +output StartPreamble; // Preamble state will be activated in next clock +output [1:0] StartData; // Data state will be activated in next clock +output StartIPG; // IPG state will be activated in next clock + +wire StartIdle; // Idle state will be activated in next clock +wire StartPAD; // PAD state will be activated in next clock + + +reg StateIdle; +reg StateIPG; +reg StatePreamble; +reg [1:0] StateData; +reg StatePAD; +reg StateFCS; +reg StateJam; +reg StateJam_q; +reg StateBackOff; +reg StateDefer; +reg Rule1; + + +// Defining the next state +assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense; + +assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2); + +assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense; + +assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm); + +assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame; + +assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl; + +assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn + | ~Collision & StatePAD & NibbleMinFl & CrcEn; + +assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS); + +assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof; + +assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2 + | StateIdle & CarrierSense + | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax) + | StateBackOff & (TxUnderRun | RandomEqByteCnt) + | StartTxDone | TooBig; + +assign DeferIndication = StateIdle & CarrierSense; + +// Tx State Machine +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + begin + StateIPG <= #Tp 1'b0; + StateIdle <= #Tp 1'b0; + StatePreamble <= #Tp 1'b0; + StateData[1:0] <= #Tp 2'b0; + StatePAD <= #Tp 1'b0; + StateFCS <= #Tp 1'b0; + StateJam <= #Tp 1'b0; + StateJam_q <= #Tp 1'b0; + StateBackOff <= #Tp 1'b0; + StateDefer <= #Tp 1'b1; + end + else + begin + StateData[1:0] <= #Tp StartData[1:0]; + StateJam_q <= #Tp StateJam; + + if(StartDefer | StartIdle) + StateIPG <= #Tp 1'b0; + else + if(StartIPG) + StateIPG <= #Tp 1'b1; + + if(StartDefer | StartPreamble) + StateIdle <= #Tp 1'b0; + else + if(StartIdle) + StateIdle <= #Tp 1'b1; + + if(StartData[0] | StartJam) + StatePreamble <= #Tp 1'b0; + else + if(StartPreamble) + StatePreamble <= #Tp 1'b1; + + if(StartFCS | StartJam) + StatePAD <= #Tp 1'b0; + else + if(StartPAD) + StatePAD <= #Tp 1'b1; + + if(StartJam | StartDefer) + StateFCS <= #Tp 1'b0; + else + if(StartFCS) + StateFCS <= #Tp 1'b1; + + if(StartBackoff | StartDefer) + StateJam <= #Tp 1'b0; + else + if(StartJam) + StateJam <= #Tp 1'b1; + + if(StartDefer) + StateBackOff <= #Tp 1'b0; + else + if(StartBackoff) + StateBackOff <= #Tp 1'b1; + + if(StartIPG) + StateDefer <= #Tp 1'b0; + else + if(StartDefer) + StateDefer <= #Tp 1'b1; + end +end + + +// This sections defines which interpack gap rule to use +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + Rule1 <= #Tp 1'b0; + else + begin + if(StateIdle | StateBackOff) + Rule1 <= #Tp 1'b0; + else + if(StatePreamble | FullD) + Rule1 <= #Tp 1'b1; + end +end + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_wishbone.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_wishbone.v new file mode 100644 index 000000000..d1a98ace5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/eth_wishbone.v @@ -0,0 +1,2559 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_wishbone.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is available in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_wishbone.v,v $ +// Revision 1.58 2005/03/21 20:07:18 igorm +// Some small fixes + some troubles fixed. +// +// Revision 1.57 2005/02/21 11:35:33 igorm +// Defer indication fixed. +// +// Revision 1.56 2004/04/30 10:30:00 igorm +// Accidently deleted line put back. +// +// Revision 1.55 2004/04/26 15:26:23 igorm +// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the +// previous update of the core. +// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. +// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER +// register. (thanks to Mathias and Torbjorn) +// - Multicast reception was fixed. Thanks to Ulrich Gries +// +// Revision 1.54 2003/11/12 18:24:59 tadejm +// WISHBONE slave changed and tested from only 32-bit accesss to byte access. +// +// Revision 1.53 2003/10/17 07:46:17 markom +// mbist signals updated according to newest convention +// +// Revision 1.52 2003/01/30 14:51:31 mohor +// Reset has priority in some flipflops. +// +// Revision 1.51 2003/01/30 13:36:22 mohor +// A new bug (entered with previous update) fixed. When abort occured sometimes +// data transmission was blocked. +// +// Revision 1.50 2003/01/22 13:49:26 tadejm +// When control packets were received, they were ignored in some cases. +// +// Revision 1.49 2003/01/21 12:09:40 mohor +// When receiving normal data frame and RxFlow control was switched on, RXB +// interrupt was not set. +// +// Revision 1.48 2003/01/20 12:05:26 mohor +// When in full duplex, transmit was sometimes blocked. Fixed. +// +// Revision 1.47 2002/11/22 13:26:21 mohor +// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used +// anywhere. Removed. +// +// Revision 1.46 2002/11/22 01:57:06 mohor +// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort +// synchronized. +// +// Revision 1.45 2002/11/19 17:33:34 mohor +// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying +// that a frame was received because of the promiscous mode. +// +// Revision 1.44 2002/11/13 22:21:40 tadejm +// RxError is not generated when small frame reception is enabled and small +// frames are received. +// +// Revision 1.43 2002/10/18 20:53:34 mohor +// case changed to casex. +// +// Revision 1.42 2002/10/18 17:04:20 tadejm +// Changed BIST scan signals. +// +// Revision 1.41 2002/10/18 15:42:09 tadejm +// Igor added WB burst support and repaired BUG when handling TX under-run and retry. +// +// Revision 1.40 2002/10/14 16:07:02 mohor +// TxStatus is written after last access to the TX fifo is finished (in case of abort +// or retry). TxDone is fixed. +// +// Revision 1.39 2002/10/11 15:35:20 mohor +// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, +// TxDone and TxRetry are generated after the current WISHBONE access is +// finished. +// +// Revision 1.38 2002/10/10 16:29:30 mohor +// BIST added. +// +// Revision 1.37 2002/09/11 14:18:46 mohor +// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. +// +// Revision 1.36 2002/09/10 13:48:46 mohor +// Reception is possible after RxPointer is read and not after BD is read. For +// that reason RxBDReady is changed to RxReady. +// Busy_IRQ interrupt connected. When there is no RxBD ready and frame +// comes, interrupt is generated. +// +// Revision 1.35 2002/09/10 10:35:23 mohor +// Ethernet debug registers removed. +// +// Revision 1.34 2002/09/08 16:31:49 mohor +// Async reset for WB_ACK_O removed (when core was in reset, it was +// impossible to access BDs). +// RxPointers and TxPointers names changed to be more descriptive. +// TxUnderRun synchronized. +// +// Revision 1.33 2002/09/04 18:47:57 mohor +// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals +// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal +// was not used OK. +// +// Revision 1.32 2002/08/14 19:31:48 mohor +// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No +// need to multiply or devide any more. +// +// Revision 1.31 2002/07/25 18:29:01 mohor +// WriteRxDataToMemory signal changed so end of frame (when last word is +// written to fifo) is changed. +// +// Revision 1.30 2002/07/23 15:28:31 mohor +// Ram , used for BDs changed from generic_spram to eth_spram_256x32. +// +// Revision 1.29 2002/07/20 00:41:32 mohor +// ShiftEnded synchronization changed. +// +// Revision 1.28 2002/07/18 16:11:46 mohor +// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. +// +// Revision 1.27 2002/07/11 02:53:20 mohor +// RxPointer bug fixed. +// +// Revision 1.26 2002/07/10 13:12:38 mohor +// Previous bug wasn't succesfully removed. Now fixed. +// +// Revision 1.25 2002/07/09 23:53:24 mohor +// Master state machine had a bug when switching from master write to +// master read. +// +// Revision 1.24 2002/07/09 20:44:41 mohor +// m_wb_cyc_o signal released after every single transfer. +// +// Revision 1.23 2002/05/03 10:15:50 mohor +// Outputs registered. Reset changed for eth_wishbone module. +// +// Revision 1.22 2002/04/24 08:52:19 mohor +// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" +// bug fixed. +// +// Revision 1.21 2002/03/29 16:18:11 lampret +// Small typo fixed. +// +// Revision 1.20 2002/03/25 16:19:12 mohor +// Any address can be used for Tx and Rx BD pointers. Address does not need +// to be aligned. +// +// Revision 1.19 2002/03/19 12:51:50 mohor +// Comments in Slovene language removed. +// +// Revision 1.18 2002/03/19 12:46:52 mohor +// casex changed with case, fifo reset changed. +// +// Revision 1.17 2002/03/09 16:08:45 mohor +// rx_fifo was not always cleared ok. Fixed. +// +// Revision 1.16 2002/03/09 13:51:20 mohor +// Status was not latched correctly sometimes. Fixed. +// +// Revision 1.15 2002/03/08 06:56:46 mohor +// Big Endian problem when sending frames fixed. +// +// Revision 1.14 2002/03/02 19:12:40 mohor +// Byte ordering changed (Big Endian used). casex changed with case because +// Xilinx Foundation had problems. Tested in HW. It WORKS. +// +// Revision 1.13 2002/02/26 16:59:55 mohor +// Small fixes for external/internal DMA missmatches. +// +// Revision 1.12 2002/02/26 16:22:07 mohor +// Interrupts changed +// +// Revision 1.11 2002/02/15 17:07:39 mohor +// Status was not written correctly when frames were discarted because of +// address mismatch. +// +// Revision 1.10 2002/02/15 12:17:39 mohor +// RxStartFrm cleared when abort or retry comes. +// +// Revision 1.9 2002/02/15 11:59:10 mohor +// Changes that were lost when updating from 1.5 to 1.8 fixed. +// +// Revision 1.8 2002/02/14 20:54:33 billditt +// Addition of new module eth_addrcheck.v +// +// Revision 1.7 2002/02/12 17:03:47 mohor +// RxOverRun added to statuses. +// +// Revision 1.6 2002/02/11 09:18:22 mohor +// Tx status is written back to the BD. +// +// Revision 1.5 2002/02/08 16:21:54 mohor +// Rx status is written back to the BD. +// +// Revision 1.4 2002/02/06 14:10:21 mohor +// non-DMA host interface added. Select the right configutation in eth_defines. +// +// Revision 1.3 2002/02/05 16:44:39 mohor +// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 +// MHz. Statuses, overrun, control frame transmission and reception still need +// to be fixed. +// +// Revision 1.2 2002/02/01 12:46:51 mohor +// Tx part finished. TxStatus needs to be fixed. Pause request needs to be +// added. +// +// Revision 1.1 2002/01/23 10:47:59 mohor +// Initial version. Equals to eth_wishbonedma.v at this moment. +// +// +// + +`include "eth_defines.v" +`include "timescale.v" + + +module eth_wishbone + ( + + // WISHBONE common + WB_CLK_I, WB_DAT_I, WB_DAT_O, + + // WISHBONE slave + WB_ADR_I, WB_WE_I, WB_ACK_O, + BDCs, + + Reset, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, + TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn, + PerPacketPad, + + //RX + MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2, + + // Register + r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll, + + // Interrupts + TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, + + // Rx Status + InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, + ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss, + ReceivedPauseFrm, + + // Tx Status + RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + + + + ); + + +parameter Tp = 1; + + +// WISHBONE common +input WB_CLK_I; // WISHBONE clock +input [31:0] WB_DAT_I; // WISHBONE data input +output [31:0] WB_DAT_O; // WISHBONE data output + +// WISHBONE slave +input [9:2] WB_ADR_I; // WISHBONE address input +input WB_WE_I; // WISHBONE write enable input +input [3:0] BDCs; // Buffer descriptors are selected +output WB_ACK_O; // WISHBONE acknowledge output + +// WISHBONE master +output [29:0] m_wb_adr_o; // +output [3:0] m_wb_sel_o; // +output m_wb_we_o; // +output [31:0] m_wb_dat_o; // +output m_wb_cyc_o; // +output m_wb_stb_o; // +input [31:0] m_wb_dat_i; // +input m_wb_ack_i; // +input m_wb_err_i; // + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +reg [2:0] m_wb_cti_o; // Cycle Type Identifier +`endif + +input Reset; // Reset signal + +// Rx Status signals +input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode +input LatchedCrcError; // CRC error +input RxLateCollision; // Late collision occured while receiving frame +input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall) +input DribbleNibble; // Extra nibble received +input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL +input [15:0] RxLength; // Length of the incoming frame +input LoadRxStatus; // Rx status was loaded +input ReceivedPacketGood;// Received packet's length and CRC are good +input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD +input r_RxFlow; +input r_PassAll; +input ReceivedPauseFrm; + +// Tx Status signals +input [3:0] RetryCntLatched; // Latched Retry Counter +input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made) +input LateCollLatched; // Late collision occured +input DeferLatched; // Defer indication (Frame was defered before sucessfully sent) +output RstDeferLatched; +input CarrierSenseLost; // Carrier Sense was lost during the frame transmission + +// Tx +input MTxClk; // Transmit clock (from PHY) +input TxUsedData; // Transmit packet used data +input TxRetry; // Transmit packet retry +input TxAbort; // Transmit packet abort +input TxDone; // Transmission ended +output TxStartFrm; // Transmit packet start frame +output TxEndFrm; // Transmit packet end frame +output [7:0] TxData; // Transmit packet data byte +output TxUnderRun; // Transmit packet under-run +output PerPacketCrcEn; // Per packet crc enable +output PerPacketPad; // Per packet pading + +// Rx +input MRxClk; // Receive clock (from PHY) +input [7:0] RxData; // Received data byte (from PHY) +input RxValid; // +input RxStartFrm; // +input RxEndFrm; // +input RxAbort; // This signal is set when address doesn't match. +output RxStatusWriteLatched_sync2; + +//Register +input r_TxEn; // Transmit enable +input r_RxEn; // Receive enable +input [7:0] r_TxBDNum; // Receive buffer descriptor number + +// Interrupts +output TxB_IRQ; +output TxE_IRQ; +output RxB_IRQ; +output RxE_IRQ; +output Busy_IRQ; + + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +reg TxB_IRQ; +reg TxE_IRQ; +reg RxB_IRQ; +reg RxE_IRQ; + +reg TxStartFrm; +reg TxEndFrm; +reg [7:0] TxData; + +reg TxUnderRun; +reg TxUnderRun_wb; + +reg TxBDRead; +wire TxStatusWrite; + +reg [1:0] TxValidBytesLatched; + +reg [15:0] TxLength; +reg [15:0] LatchedTxLength; +reg [14:11] TxStatus; + +reg [14:13] RxStatus; + +reg TxStartFrm_wb; +reg TxRetry_wb; +reg TxAbort_wb; +reg TxDone_wb; + +reg TxDone_wb_q; +reg TxAbort_wb_q; +reg TxRetry_wb_q; +reg TxRetryPacket; +reg TxRetryPacket_NotCleared; +reg TxDonePacket; +reg TxDonePacket_NotCleared; +reg TxAbortPacket; +reg TxAbortPacket_NotCleared; +reg RxBDReady; +reg RxReady; +reg TxBDReady; + +reg RxBDRead; + +reg [31:0] TxDataLatched; +reg [1:0] TxByteCnt; +reg LastWord; +reg ReadTxDataFromFifo_tck; + +reg BlockingTxStatusWrite; +reg BlockingTxBDRead; + +reg Flop; + +reg [7:1] TxBDAddress; +reg [7:1] RxBDAddress; + +reg TxRetrySync1; +reg TxAbortSync1; +reg TxDoneSync1; + +reg TxAbort_q; +reg TxRetry_q; +reg TxUsedData_q; + +reg [31:0] RxDataLatched2; + +reg [31:8] RxDataLatched1; // Big Endian Byte Ordering + +reg [1:0] RxValidBytes; +reg [1:0] RxByteCnt; +reg LastByteIn; +reg ShiftWillEnd; + +reg WriteRxDataToFifo; +reg [15:0] LatchedRxLength; +reg RxAbortLatched; + +reg ShiftEnded; +reg RxOverrun; + +reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side +reg BDRead; // BD Read access from WISHBONE side +wire [31:0] RxBDDataIn; // Rx BD data in +wire [31:0] TxBDDataIn; // Tx BD data in + +reg TxEndFrm_wb; + +wire TxRetryPulse; +wire TxDonePulse; +wire TxAbortPulse; + +wire StartRxBDRead; + +wire StartTxBDRead; + +wire TxIRQEn; +wire WrapTxStatusBit; + +wire RxIRQEn; +wire WrapRxStatusBit; + +wire [1:0] TxValidBytes; + +wire [7:1] TempTxBDAddress; +wire [7:1] TempRxBDAddress; + +wire RxStatusWrite; +wire RxBufferFull; +wire RxBufferAlmostEmpty; +wire RxBufferEmpty; + +reg WB_ACK_O; + +wire [8:0] RxStatusIn; +reg [8:0] RxStatusInLatched; + +reg WbEn, WbEn_q; +reg RxEn, RxEn_q; +reg TxEn, TxEn_q; +reg r_TxEn_q; +reg r_RxEn_q; + +wire ram_ce; +wire [3:0] ram_we; +wire ram_oe; +reg [7:0] ram_addr; +reg [31:0] ram_di; +wire [31:0] ram_do; + +wire StartTxPointerRead; +reg TxPointerRead; +reg TxEn_needed; +reg RxEn_needed; + +wire StartRxPointerRead; +reg RxPointerRead; + +`ifdef ETH_WISHBONE_B3 +assign m_wb_bte_o = 2'b00; // Linear burst +`endif + +assign m_wb_stb_o = m_wb_cyc_o; + +always @ (posedge WB_CLK_I) +begin + WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; +end + +assign WB_DAT_O = ram_do; + +// Generic synchronous single-port RAM interface +eth_spram_256x32 bd_ram ( + .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do) +`ifdef ETH_BIST + , + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +); + +assign ram_ce = 1'b1; +assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}}; +assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead); + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxEn_needed <=#Tp 1'b0; + else + if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q) + TxEn_needed <=#Tp 1'b1; + else + if(TxPointerRead & TxEn & TxEn_q) + TxEn_needed <=#Tp 1'b0; +end + +// Enabling access to the RAM for three devices. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + begin + WbEn <=#Tp 1'b1; + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b0; + ram_addr <=#Tp 8'h0; + ram_di <=#Tp 32'h0; + BDRead <=#Tp 1'b0; + BDWrite <=#Tp 1'b0; + end + else + begin + // Switching between three stages depends on enable signals + case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case + 5'b100_10, 5'b100_11 : + begin + WbEn <=#Tp 1'b0; + RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled + TxEn <=#Tp 1'b0; + ram_addr <=#Tp {RxBDAddress, RxPointerRead}; + ram_di <=#Tp RxBDDataIn; + end + 5'b100_01 : + begin + WbEn <=#Tp 1'b0; + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled + ram_addr <=#Tp {TxBDAddress, TxPointerRead}; + ram_di <=#Tp TxBDDataIn; + end + 5'b010_00, 5'b010_10 : + begin + WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b0; + ram_addr <=#Tp WB_ADR_I[9:2]; + ram_di <=#Tp WB_DAT_I; + BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; + BDRead <=#Tp (|BDCs) & ~WB_WE_I; + end + 5'b010_01, 5'b010_11 : + begin + WbEn <=#Tp 1'b0; + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled + ram_addr <=#Tp {TxBDAddress, TxPointerRead}; + ram_di <=#Tp TxBDDataIn; + end + 5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : + begin + WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage) + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b0; + ram_addr <=#Tp WB_ADR_I[9:2]; + ram_di <=#Tp WB_DAT_I; + BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; + BDRead <=#Tp (|BDCs) & ~WB_WE_I; + end + 5'b100_00 : + begin + WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit + end + 5'b000_00 : + begin + WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage. + RxEn <=#Tp 1'b0; + TxEn <=#Tp 1'b0; + ram_addr <=#Tp WB_ADR_I[9:2]; + ram_di <=#Tp WB_DAT_I; + BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; + BDRead <=#Tp (|BDCs) & ~WB_WE_I; + end + endcase + end +end + + +// Delayed stage signals +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + begin + WbEn_q <=#Tp 1'b0; + RxEn_q <=#Tp 1'b0; + TxEn_q <=#Tp 1'b0; + r_TxEn_q <=#Tp 1'b0; + r_RxEn_q <=#Tp 1'b0; + end + else + begin + WbEn_q <=#Tp WbEn; + RxEn_q <=#Tp RxEn; + TxEn_q <=#Tp TxEn; + r_TxEn_q <=#Tp r_TxEn; + r_RxEn_q <=#Tp r_RxEn; + end +end + +// Changes for tx occur every second clock. Flop is used for this manner. +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + Flop <=#Tp 1'b0; + else + if(TxDone | TxAbort | TxRetry_q) + Flop <=#Tp 1'b0; + else + if(TxUsedData) + Flop <=#Tp ~Flop; +end + +wire ResetTxBDReady; +assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse; + +// Latching READY status of the Tx buffer descriptor +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxBDReady <=#Tp 1'b0; + else + if(TxEn & TxEn_q & TxBDRead) + TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning. + else // Only packets larger then 4 bytes are transmitted. + if(ResetTxBDReady) + TxBDReady <=#Tp 1'b0; +end + + +// Reading the Tx buffer descriptor +assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady; + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxBDRead <=#Tp 1'b1; + else + if(StartTxBDRead) + TxBDRead <=#Tp 1'b1; + else + if(TxBDReady) + TxBDRead <=#Tp 1'b0; +end + + +// Reading Tx BD pointer +assign StartTxPointerRead = TxBDRead & TxBDReady; + +// Reading Tx BD Pointer +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxPointerRead <=#Tp 1'b0; + else + if(StartTxPointerRead) + TxPointerRead <=#Tp 1'b1; + else + if(TxEn_q) + TxPointerRead <=#Tp 1'b0; +end + + +// Writing status back to the Tx buffer descriptor +assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite; + + + +// Status writing must occur only once. Meanwhile it is blocked. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + BlockingTxStatusWrite <=#Tp 1'b0; + else + if(~TxDone_wb & ~TxAbort_wb) + BlockingTxStatusWrite <=#Tp 1'b0; + else + if(TxStatusWrite) + BlockingTxStatusWrite <=#Tp 1'b1; +end + + +reg BlockingTxStatusWrite_sync1; +reg BlockingTxStatusWrite_sync2; +reg BlockingTxStatusWrite_sync3; + +// Synchronizing BlockingTxStatusWrite to MTxClk +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + BlockingTxStatusWrite_sync1 <=#Tp 1'b0; + else + BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite; +end + +// Synchronizing BlockingTxStatusWrite to MTxClk +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + BlockingTxStatusWrite_sync2 <=#Tp 1'b0; + else + BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1; +end + +// Synchronizing BlockingTxStatusWrite to MTxClk +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + BlockingTxStatusWrite_sync3 <=#Tp 1'b0; + else + BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2; +end + +assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3; + +// TxBDRead state is activated only once. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + BlockingTxBDRead <=#Tp 1'b0; + else + if(StartTxBDRead) + BlockingTxBDRead <=#Tp 1'b1; + else + if(~StartTxBDRead & ~TxBDReady) + BlockingTxBDRead <=#Tp 1'b0; +end + + +// Latching status from the tx buffer descriptor +// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active) +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxStatus <=#Tp 4'h0; + else + if(TxEn & TxEn_q & TxBDRead) + TxStatus <=#Tp ram_do[14:11]; +end + +reg ReadTxDataFromMemory; +wire WriteRxDataToMemory; + +reg MasterWbTX; +reg MasterWbRX; + +reg [29:0] m_wb_adr_o; +reg m_wb_cyc_o; +reg [3:0] m_wb_sel_o; +reg m_wb_we_o; + +wire TxLengthEq0; +wire TxLengthLt4; + +reg BlockingIncrementTxPointer; +reg [31:2] TxPointerMSB; +reg [1:0] TxPointerLSB; +reg [1:0] TxPointerLSB_rst; +reg [31:2] RxPointerMSB; +reg [1:0] RxPointerLSB_rst; + +wire RxBurstAcc; +wire RxWordAcc; +wire RxHalfAcc; +wire RxByteAcc; + +//Latching length from the buffer descriptor; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxLength <=#Tp 16'h0; + else + if(TxEn & TxEn_q & TxBDRead) + TxLength <=#Tp ram_do[31:16]; + else + if(MasterWbTX & m_wb_ack_i) + begin + if(TxLengthLt4) + TxLength <=#Tp 16'h0; + else + if(TxPointerLSB_rst==2'h0) + TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request + else + if(TxPointerLSB_rst==2'h1) + TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request + else + if(TxPointerLSB_rst==2'h2) + TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request + else + if(TxPointerLSB_rst==2'h3) + TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request + end +end + + + +//Latching length from the buffer descriptor; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + LatchedTxLength <=#Tp 16'h0; + else + if(TxEn & TxEn_q & TxBDRead) + LatchedTxLength <=#Tp ram_do[31:16]; +end + +assign TxLengthEq0 = TxLength == 0; +assign TxLengthLt4 = TxLength < 4; + +reg cyc_cleared; +reg IncrTxPointer; + + +// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched +// because TxPointerMSB is only used for word-aligned accesses. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxPointerMSB <=#Tp 30'h0; + else + if(TxEn & TxEn_q & TxPointerRead) + TxPointerMSB <=#Tp ram_do[31:2]; + else + if(IncrTxPointer & ~BlockingIncrementTxPointer) + TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned +end + + +// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed, +// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This +// signals are used for proper selection of the start byte (TxData and TxByteCnt) are +// set by this two bits. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxPointerLSB[1:0] <=#Tp 0; + else + if(TxEn & TxEn_q & TxPointerRead) + TxPointerLSB[1:0] <=#Tp ram_do[1:0]; +end + + +// Latching 2 MSB bits of the buffer descriptor. +// After the read access, TxLength needs to be decremented for the number of the valid +// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are +// valid so this two bits are reset to zero. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxPointerLSB_rst[1:0] <=#Tp 0; + else + if(TxEn & TxEn_q & TxPointerRead) + TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; + else + if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned + TxPointerLSB_rst[1:0] <=#Tp 0; +end + + +reg [3:0] RxByteSel; +wire MasterAccessFinished; + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + BlockingIncrementTxPointer <=#Tp 0; + else + if(MasterAccessFinished) + BlockingIncrementTxPointer <=#Tp 0; + else + if(IncrTxPointer) + BlockingIncrementTxPointer <=#Tp 1'b1; +end + + +wire TxBufferAlmostFull; +wire TxBufferFull; +wire TxBufferEmpty; +wire TxBufferAlmostEmpty; +wire SetReadTxDataFromMemory; + +reg BlockReadTxDataFromMemory; + +assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead; + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ReadTxDataFromMemory <=#Tp 1'b0; + else + if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) + ReadTxDataFromMemory <=#Tp 1'b0; + else + if(SetReadTxDataFromMemory) + ReadTxDataFromMemory <=#Tp 1'b1; +end + +reg tx_burst_en; +reg rx_burst_en; + +wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory; +wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en; + +wire [31:0] TxData_wb; +wire ReadTxDataFromFifo_wb; + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + BlockReadTxDataFromMemory <=#Tp 1'b0; + else + if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))) + BlockReadTxDataFromMemory <=#Tp 1'b1; + else + if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) + BlockReadTxDataFromMemory <=#Tp 1'b0; +end + + +assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; +wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; +wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; +reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; +reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; + +wire rx_burst; +wire enough_data_in_rxfifo_for_burst; +wire enough_data_in_rxfifo_for_burst_plus1; + +// Enabling master wishbone access to the memory for two devices TX and RX. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + begin + MasterWbTX <=#Tp 1'b0; + MasterWbRX <=#Tp 1'b0; + m_wb_adr_o <=#Tp 30'h0; + m_wb_cyc_o <=#Tp 1'b0; + m_wb_we_o <=#Tp 1'b0; + m_wb_sel_o <=#Tp 4'h0; + cyc_cleared<=#Tp 1'b0; + tx_burst_cnt<=#Tp 0; + rx_burst_cnt<=#Tp 0; + IncrTxPointer<=#Tp 1'b0; + tx_burst_en<=#Tp 1'b1; + rx_burst_en<=#Tp 1'b0; + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b0; + `endif + end + else + begin + // Switching between two stages depends on enable signals + casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case + 8'b00_10_00_10, // Idle and MRB needed + 8'b10_1x_10_1x, // MRB continues + 8'b10_10_01_10, // Clear (previously MR) and MRB needed + 8'b01_1x_01_1x : // Clear (previously MW) and MRB needed + begin + MasterWbTX <=#Tp 1'b1; // tx burst + MasterWbRX <=#Tp 1'b0; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b0; + m_wb_sel_o <=#Tp 4'hf; + cyc_cleared<=#Tp 1'b0; + IncrTxPointer<=#Tp 1'b1; + tx_burst_cnt <=#Tp tx_burst_cnt+3'h1; + if(tx_burst_cnt==0) + m_wb_adr_o <=#Tp TxPointerMSB; + else + m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; + + if(tx_burst_cnt==(`ETH_BURST_LENGTH-1)) + begin + tx_burst_en<=#Tp 1'b0; + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b111; + `endif + end + else + begin + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b010; + `endif + end + end + 8'b00_x1_00_x1, // Idle and MWB needed + 8'b01_x1_10_x1, // MWB continues + 8'b01_01_01_01, // Clear (previously MW) and MWB needed + 8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed + begin + MasterWbTX <=#Tp 1'b0; // rx burst + MasterWbRX <=#Tp 1'b1; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b1; + m_wb_sel_o <=#Tp RxByteSel; + IncrTxPointer<=#Tp 1'b0; + cyc_cleared<=#Tp 1'b0; + rx_burst_cnt <=#Tp rx_burst_cnt+3'h1; + + if(rx_burst_cnt==0) + m_wb_adr_o <=#Tp RxPointerMSB; + else + m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; + + if(rx_burst_cnt==(`ETH_BURST_LENGTH-1)) + begin + rx_burst_en<=#Tp 1'b0; + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b111; + `endif + end + else + begin + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b010; + `endif + end + end + 8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer) + begin + MasterWbTX <=#Tp 1'b0; + MasterWbRX <=#Tp 1'b1; + m_wb_adr_o <=#Tp RxPointerMSB; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b1; + m_wb_sel_o <=#Tp RxByteSel; + IncrTxPointer<=#Tp 1'b0; + end + 8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer) + begin + MasterWbTX <=#Tp 1'b1; + MasterWbRX <=#Tp 1'b0; + m_wb_adr_o <=#Tp TxPointerMSB; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b0; + m_wb_sel_o <=#Tp 4'hf; + IncrTxPointer<=#Tp 1'b1; + end + 8'b10_10_01_00, // MR and MR is needed (data read from tx buffer) + 8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer) + begin + MasterWbTX <=#Tp 1'b1; + MasterWbRX <=#Tp 1'b0; + m_wb_adr_o <=#Tp TxPointerMSB; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b0; + m_wb_sel_o <=#Tp 4'hf; + cyc_cleared<=#Tp 1'b0; + IncrTxPointer<=#Tp 1'b1; + end + 8'b01_01_01_00, // MW and MW needed (data write to rx buffer) + 8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer) + begin + MasterWbTX <=#Tp 1'b0; + MasterWbRX <=#Tp 1'b1; + m_wb_adr_o <=#Tp RxPointerMSB; + m_wb_cyc_o <=#Tp 1'b1; + m_wb_we_o <=#Tp 1'b1; + m_wb_sel_o <=#Tp RxByteSel; + cyc_cleared<=#Tp 1'b0; + IncrTxPointer<=#Tp 1'b0; + end + 8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access) + 8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access) + 8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access) + 8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access) + begin + m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started + cyc_cleared<=#Tp 1'b1; + IncrTxPointer<=#Tp 1'b0; + tx_burst_cnt<=#Tp 0; + tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); + rx_burst_cnt<=#Tp 0; + rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b0; + `endif + end + 8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access) + 8'bxx_00_01_00 : // Between cyc_cleared request was cleared + begin + MasterWbTX <=#Tp 1'b0; + MasterWbRX <=#Tp 1'b0; + m_wb_cyc_o <=#Tp 1'b0; + cyc_cleared<=#Tp 1'b0; + IncrTxPointer<=#Tp 1'b0; + rx_burst_cnt<=#Tp 0; + rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. + `ifdef ETH_WISHBONE_B3 + m_wb_cti_o <=#Tp 3'b0; + `endif + end + 8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access) + begin + tx_burst_cnt<=#Tp 0; + tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); + end + default: // Don't touch + begin + MasterWbTX <=#Tp MasterWbTX; + MasterWbRX <=#Tp MasterWbRX; + m_wb_cyc_o <=#Tp m_wb_cyc_o; + m_wb_sel_o <=#Tp m_wb_sel_o; + IncrTxPointer<=#Tp IncrTxPointer; + end + endcase + end +end + + +wire TxFifoClear; + +assign TxFifoClear = (TxAbortPacket | TxRetryPacket); + +eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH) +tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb), + .clk(WB_CLK_I), .reset(Reset), + .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), + .clear(TxFifoClear), .full(TxBufferFull), + .almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty), + .empty(TxBufferEmpty), .cnt(txfifo_cnt) + ); + + +reg StartOccured; +reg TxStartFrm_sync1; +reg TxStartFrm_sync2; +reg TxStartFrm_syncb1; +reg TxStartFrm_syncb2; + + + +// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxStartFrm_wb <=#Tp 1'b0; + else + if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)) + TxStartFrm_wb <=#Tp 1'b1; + else + if(TxStartFrm_syncb2) + TxStartFrm_wb <=#Tp 1'b0; +end + +// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked. +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + StartOccured <=#Tp 1'b0; + else + if(TxStartFrm_wb) + StartOccured <=#Tp 1'b1; + else + if(ResetTxBDReady) + StartOccured <=#Tp 1'b0; +end + +// Synchronizing TxStartFrm_wb to MTxClk +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxStartFrm_sync1 <=#Tp 1'b0; + else + TxStartFrm_sync1 <=#Tp TxStartFrm_wb; +end + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxStartFrm_sync2 <=#Tp 1'b0; + else + TxStartFrm_sync2 <=#Tp TxStartFrm_sync1; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxStartFrm_syncb1 <=#Tp 1'b0; + else + TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxStartFrm_syncb2 <=#Tp 1'b0; + else + TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1; +end + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxStartFrm <=#Tp 1'b0; + else + if(TxStartFrm_sync2) + TxStartFrm <=#Tp 1'b1; + else + if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) + TxStartFrm <=#Tp 1'b0; +end +// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk + + +// TxEndFrm_wb: indicator of the end of frame +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxEndFrm_wb <=#Tp 1'b0; + else + if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) + TxEndFrm_wb <=#Tp 1'b1; + else + if(TxRetryPulse | TxDonePulse | TxAbortPulse) + TxEndFrm_wb <=#Tp 1'b0; +end + + +// Marks which bytes are valid within the word. +assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0; + +reg LatchValidBytes; +reg LatchValidBytes_q; + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + LatchValidBytes <=#Tp 1'b0; + else + if(TxLengthLt4 & TxBDReady) + LatchValidBytes <=#Tp 1'b1; + else + LatchValidBytes <=#Tp 1'b0; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + LatchValidBytes_q <=#Tp 1'b0; + else + LatchValidBytes_q <=#Tp LatchValidBytes; +end + + +// Latching valid bytes +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxValidBytesLatched <=#Tp 2'h0; + else + if(LatchValidBytes & ~LatchValidBytes_q) + TxValidBytesLatched <=#Tp TxValidBytes; + else + if(TxRetryPulse | TxDonePulse | TxAbortPulse) + TxValidBytesLatched <=#Tp 2'h0; +end + + +assign TxIRQEn = TxStatus[14]; +assign WrapTxStatusBit = TxStatus[13]; +assign PerPacketPad = TxStatus[12]; +assign PerPacketCrcEn = TxStatus[11]; + + +assign RxIRQEn = RxStatus[14]; +assign WrapRxStatusBit = RxStatus[13]; + + +// Temporary Tx and Rx buffer descriptor address +assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) +assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD + {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address) + + +// Latching Tx buffer descriptor address +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxBDAddress <=#Tp 7'h0; + else if (r_TxEn & (~r_TxEn_q)) + TxBDAddress <=#Tp 7'h0; + else if (TxStatusWrite) + TxBDAddress <=#Tp TempTxBDAddress; +end + + +// Latching Rx buffer descriptor address +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxBDAddress <=#Tp 7'h0; + else if(r_RxEn & (~r_RxEn_q)) + RxBDAddress <=#Tp r_TxBDNum[6:0]; + else if(RxStatusWrite) + RxBDAddress <=#Tp TempRxBDAddress; +end + +wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost}; + +assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched}; +assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched}; + + +// Signals used for various purposes +assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q; +assign TxDonePulse = TxDone_wb & ~TxDone_wb_q; +assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q; + + + +// Generating delayed signals +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + begin + TxAbort_q <=#Tp 1'b0; + TxRetry_q <=#Tp 1'b0; + TxUsedData_q <=#Tp 1'b0; + end + else + begin + TxAbort_q <=#Tp TxAbort; + TxRetry_q <=#Tp TxRetry; + TxUsedData_q <=#Tp TxUsedData; + end +end + +// Generating delayed signals +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + begin + TxDone_wb_q <=#Tp 1'b0; + TxAbort_wb_q <=#Tp 1'b0; + TxRetry_wb_q <=#Tp 1'b0; + end + else + begin + TxDone_wb_q <=#Tp TxDone_wb; + TxAbort_wb_q <=#Tp TxAbort_wb; + TxRetry_wb_q <=#Tp TxRetry_wb; + end +end + + +reg TxAbortPacketBlocked; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxAbortPacket <=#Tp 1'b0; + else + if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | + TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) + TxAbortPacket <=#Tp 1'b1; + else + TxAbortPacket <=#Tp 1'b0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxAbortPacket_NotCleared <=#Tp 1'b0; + else + if(TxEn & TxEn_q & TxAbortPacket_NotCleared) + TxAbortPacket_NotCleared <=#Tp 1'b0; + else + if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | + TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) + TxAbortPacket_NotCleared <=#Tp 1'b1; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxAbortPacketBlocked <=#Tp 1'b0; + else + if(!TxAbort_wb & TxAbort_wb_q) + TxAbortPacketBlocked <=#Tp 1'b0; + else + if(TxAbortPacket) + TxAbortPacketBlocked <=#Tp 1'b1; +end + + +reg TxRetryPacketBlocked; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxRetryPacket <=#Tp 1'b0; + else + if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | + TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) + TxRetryPacket <=#Tp 1'b1; + else + TxRetryPacket <=#Tp 1'b0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxRetryPacket_NotCleared <=#Tp 1'b0; + else + if(StartTxBDRead) + TxRetryPacket_NotCleared <=#Tp 1'b0; + else + if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | + TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) + TxRetryPacket_NotCleared <=#Tp 1'b1; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxRetryPacketBlocked <=#Tp 1'b0; + else + if(!TxRetry_wb & TxRetry_wb_q) + TxRetryPacketBlocked <=#Tp 1'b0; + else + if(TxRetryPacket) + TxRetryPacketBlocked <=#Tp 1'b1; +end + + +reg TxDonePacketBlocked; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxDonePacket <=#Tp 1'b0; + else + if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked | + TxDone_wb & !MasterWbTX & !TxDonePacketBlocked) + TxDonePacket <=#Tp 1'b1; + else + TxDonePacket <=#Tp 1'b0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxDonePacket_NotCleared <=#Tp 1'b0; + else + if(TxEn & TxEn_q & TxDonePacket_NotCleared) + TxDonePacket_NotCleared <=#Tp 1'b0; + else + if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) | + TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked)) + TxDonePacket_NotCleared <=#Tp 1'b1; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxDonePacketBlocked <=#Tp 1'b0; + else + if(!TxDone_wb & TxDone_wb_q) + TxDonePacketBlocked <=#Tp 1'b0; + else + if(TxDonePacket) + TxDonePacketBlocked <=#Tp 1'b1; +end + + +// Indication of the last word +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + LastWord <=#Tp 1'b0; + else + if((TxEndFrm | TxAbort | TxRetry) & Flop) + LastWord <=#Tp 1'b0; + else + if(TxUsedData & Flop & TxByteCnt == 2'h3) + LastWord <=#Tp TxEndFrm_wb; +end + + +// Tx end frame generation +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxEndFrm <=#Tp 1'b0; + else + if(Flop & TxEndFrm | TxAbort | TxRetry_q) + TxEndFrm <=#Tp 1'b0; + else + if(Flop & LastWord) + begin + case (TxValidBytesLatched) // synopsys parallel_case + 1 : TxEndFrm <=#Tp TxByteCnt == 2'h0; + 2 : TxEndFrm <=#Tp TxByteCnt == 2'h1; + 3 : TxEndFrm <=#Tp TxByteCnt == 2'h2; + 0 : TxEndFrm <=#Tp TxByteCnt == 2'h3; + default : TxEndFrm <=#Tp 1'b0; + endcase + end +end + + +// Tx data selection (latching) +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxData <=#Tp 0; + else + if(TxStartFrm_sync2 & ~TxStartFrm) + case(TxPointerLSB) // synopsys parallel_case + 2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering + 2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering + 2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering + 2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering + endcase + else + if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3) + TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering + else + if(TxUsedData & Flop) + begin + case(TxByteCnt) // synopsys parallel_case + 0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering + 1 : TxData <=#Tp TxDataLatched[23:16]; + 2 : TxData <=#Tp TxDataLatched[15:8]; + 3 : TxData <=#Tp TxDataLatched[7:0]; + endcase + end +end + + +// Latching tx data +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxDataLatched[31:0] <=#Tp 32'h0; + else + if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) + TxDataLatched[31:0] <=#Tp TxData_wb[31:0]; +end + + +// Tx under run +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxUnderRun_wb <=#Tp 1'b0; + else + if(TxAbortPulse) + TxUnderRun_wb <=#Tp 1'b0; + else + if(TxBufferEmpty & ReadTxDataFromFifo_wb) + TxUnderRun_wb <=#Tp 1'b1; +end + + +reg TxUnderRun_sync1; + +// Tx under run +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxUnderRun_sync1 <=#Tp 1'b0; + else + if(TxUnderRun_wb) + TxUnderRun_sync1 <=#Tp 1'b1; + else + if(BlockingTxStatusWrite_sync2) + TxUnderRun_sync1 <=#Tp 1'b0; +end + +// Tx under run +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxUnderRun <=#Tp 1'b0; + else + if(BlockingTxStatusWrite_sync2) + TxUnderRun <=#Tp 1'b0; + else + if(TxUnderRun_sync1) + TxUnderRun <=#Tp 1'b1; +end + + +// Tx Byte counter +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + TxByteCnt <=#Tp 2'h0; + else + if(TxAbort_q | TxRetry_q) + TxByteCnt <=#Tp 2'h0; + else + if(TxStartFrm & ~TxUsedData) + case(TxPointerLSB) // synopsys parallel_case + 2'h0 : TxByteCnt <=#Tp 2'h1; + 2'h1 : TxByteCnt <=#Tp 2'h2; + 2'h2 : TxByteCnt <=#Tp 2'h3; + 2'h3 : TxByteCnt <=#Tp 2'h0; + endcase + else + if(TxUsedData & Flop) + TxByteCnt <=#Tp TxByteCnt + 1'b1; +end + + +// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I +reg ReadTxDataFromFifo_sync1; +reg ReadTxDataFromFifo_sync2; +reg ReadTxDataFromFifo_sync3; +reg ReadTxDataFromFifo_syncb1; +reg ReadTxDataFromFifo_syncb2; +reg ReadTxDataFromFifo_syncb3; + + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_tck <=#Tp 1'b0; + else + if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) + ReadTxDataFromFifo_tck <=#Tp 1'b1; + else + if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3) + ReadTxDataFromFifo_tck <=#Tp 1'b0; +end + +// Synchronizing TxStartFrm_wb to MTxClk +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_sync1 <=#Tp 1'b0; + else + ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_sync2 <=#Tp 1'b0; + else + ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1; +end + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_syncb1 <=#Tp 1'b0; + else + ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2; +end + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_syncb2 <=#Tp 1'b0; + else + ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1; +end + +always @ (posedge MTxClk or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_syncb3 <=#Tp 1'b0; + else + ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ReadTxDataFromFifo_sync3 <=#Tp 1'b0; + else + ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2; +end + +assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3; +// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I + + +// Synchronizing TxRetry signal (synchronized to WISHBONE clock) +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxRetrySync1 <=#Tp 1'b0; + else + TxRetrySync1 <=#Tp TxRetry; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxRetry_wb <=#Tp 1'b0; + else + TxRetry_wb <=#Tp TxRetrySync1; +end + + +// Synchronized TxDone_wb signal (synchronized to WISHBONE clock) +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxDoneSync1 <=#Tp 1'b0; + else + TxDoneSync1 <=#Tp TxDone; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxDone_wb <=#Tp 1'b0; + else + TxDone_wb <=#Tp TxDoneSync1; +end + +// Synchronizing TxAbort signal (synchronized to WISHBONE clock) +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxAbortSync1 <=#Tp 1'b0; + else + TxAbortSync1 <=#Tp TxAbort; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxAbort_wb <=#Tp 1'b0; + else + TxAbort_wb <=#Tp TxAbortSync1; +end + + +reg RxAbortSync1; +reg RxAbortSync2; +reg RxAbortSync3; +reg RxAbortSync4; +reg RxAbortSyncb1; +reg RxAbortSyncb2; + +assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q; + +// Reading the Rx buffer descriptor +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxBDRead <=#Tp 1'b0; + else + if(StartRxBDRead & ~RxReady) + RxBDRead <=#Tp 1'b1; + else + if(RxBDReady) + RxBDRead <=#Tp 1'b0; +end + + +// Reading of the next receive buffer descriptor starts after reception status is +// written to the previous one. + +// Latching READY status of the Rx buffer descriptor +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxBDReady <=#Tp 1'b0; + else + if(RxPointerRead) + RxBDReady <=#Tp 1'b0; + else + if(RxEn & RxEn_q & RxBDRead) + RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning +end + +// Latching Rx buffer descriptor status +// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active) +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxStatus <=#Tp 2'h0; + else + if(RxEn & RxEn_q & RxBDRead) + RxStatus <=#Tp ram_do[14:13]; +end + + +// RxReady generation +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxReady <=#Tp 1'b0; + else + if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q) + RxReady <=#Tp 1'b0; + else + if(RxEn & RxEn_q & RxPointerRead) + RxReady <=#Tp 1'b1; +end + + +// Reading Rx BD pointer + + +assign StartRxPointerRead = RxBDRead & RxBDReady; + +// Reading Tx BD Pointer +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxPointerRead <=#Tp 1'b0; + else + if(StartRxPointerRead) + RxPointerRead <=#Tp 1'b1; + else + if(RxEn & RxEn_q) + RxPointerRead <=#Tp 1'b0; +end + + +//Latching Rx buffer pointer from buffer descriptor; +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxPointerMSB <=#Tp 30'h0; + else + if(RxEn & RxEn_q & RxPointerRead) + RxPointerMSB <=#Tp ram_do[31:2]; + else + if(MasterWbRX & m_wb_ack_i) + RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes) +end + + +//Latching last addresses from buffer descriptor (used as byte-half-word indicator); +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxPointerLSB_rst[1:0] <=#Tp 0; + else + if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active + RxPointerLSB_rst[1:0] <=#Tp 0; + else + if(RxEn & RxEn_q & RxPointerRead) + RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; +end + + +always @ (RxPointerLSB_rst) +begin + case(RxPointerLSB_rst[1:0]) // synopsys parallel_case + 2'h0 : RxByteSel[3:0] = 4'hf; + 2'h1 : RxByteSel[3:0] = 4'h7; + 2'h2 : RxByteSel[3:0] = 4'h3; + 2'h3 : RxByteSel[3:0] = 4'h1; + endcase +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxEn_needed <=#Tp 1'b0; + else + if(~RxReady & r_RxEn & WbEn & ~WbEn_q) + RxEn_needed <=#Tp 1'b1; + else + if(RxPointerRead & RxEn & RxEn_q) + RxEn_needed <=#Tp 1'b0; +end + + +// Reception status is written back to the buffer descriptor after the end of frame is detected. +assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q; + +reg RxEnableWindow; + +// Indicating that last byte is being reveived +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LastByteIn <=#Tp 1'b0; + else + if(ShiftWillEnd & (&RxByteCnt) | RxAbort) + LastByteIn <=#Tp 1'b0; + else + if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow) + LastByteIn <=#Tp 1'b1; +end + +reg ShiftEnded_rck; +reg ShiftEndedSync1; +reg ShiftEndedSync2; +reg ShiftEndedSync3; +reg ShiftEndedSync_c1; +reg ShiftEndedSync_c2; + +wire StartShiftWillEnd; +assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow; + +// Indicating that data reception will end +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ShiftWillEnd <=#Tp 1'b0; + else + if(ShiftEnded_rck | RxAbort) + ShiftWillEnd <=#Tp 1'b0; + else + if(StartShiftWillEnd) + ShiftWillEnd <=#Tp 1'b1; +end + + + +// Receive byte counter +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxByteCnt <=#Tp 2'h0; + else + if(ShiftEnded_rck | RxAbort) + RxByteCnt <=#Tp 2'h0; + else + if(RxValid & RxStartFrm & RxReady) + case(RxPointerLSB_rst) // synopsys parallel_case + 2'h0 : RxByteCnt <=#Tp 2'h1; + 2'h1 : RxByteCnt <=#Tp 2'h2; + 2'h2 : RxByteCnt <=#Tp 2'h3; + 2'h3 : RxByteCnt <=#Tp 2'h0; + endcase + else + if(RxValid & RxEnableWindow & RxReady | LastByteIn) + RxByteCnt <=#Tp RxByteCnt + 1'b1; +end + + +// Indicates how many bytes are valid within the last word +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxValidBytes <=#Tp 2'h1; + else + if(RxValid & RxStartFrm) + case(RxPointerLSB_rst) // synopsys parallel_case + 2'h0 : RxValidBytes <=#Tp 2'h1; + 2'h1 : RxValidBytes <=#Tp 2'h2; + 2'h2 : RxValidBytes <=#Tp 2'h3; + 2'h3 : RxValidBytes <=#Tp 2'h0; + endcase + else + if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow) + RxValidBytes <=#Tp RxValidBytes + 1'b1; +end + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxDataLatched1 <=#Tp 24'h0; + else + if(RxValid & RxReady & ~LastByteIn) + if(RxStartFrm) + begin + case(RxPointerLSB_rst) // synopsys parallel_case + 2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering + 2'h1: RxDataLatched1[23:16] <=#Tp RxData; + 2'h2: RxDataLatched1[15:8] <=#Tp RxData; + 2'h3: RxDataLatched1 <=#Tp RxDataLatched1; + endcase + end + else if (RxEnableWindow) + begin + case(RxByteCnt) // synopsys parallel_case + 2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering + 2'h1: RxDataLatched1[23:16] <=#Tp RxData; + 2'h2: RxDataLatched1[15:8] <=#Tp RxData; + 2'h3: RxDataLatched1 <=#Tp RxDataLatched1; + endcase + end +end + +wire SetWriteRxDataToFifo; + +// Assembling data that will be written to the rx_fifo +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxDataLatched2 <=#Tp 32'h0; + else + if(SetWriteRxDataToFifo & ~ShiftWillEnd) + RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering + else + if(SetWriteRxDataToFifo & ShiftWillEnd) + case(RxValidBytes) // synopsys parallel_case + 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering + 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0}; + 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0}; + 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0}; + endcase +end + + +reg WriteRxDataToFifoSync1; +reg WriteRxDataToFifoSync2; +reg WriteRxDataToFifoSync3; + + +// Indicating start of the reception process +assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | + (RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) | + (ShiftWillEnd & LastByteIn & (&RxByteCnt)); + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + WriteRxDataToFifo <=#Tp 1'b0; + else + if(SetWriteRxDataToFifo & ~RxAbort) + WriteRxDataToFifo <=#Tp 1'b1; + else + if(WriteRxDataToFifoSync2 | RxAbort) + WriteRxDataToFifo <=#Tp 1'b0; +end + + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + WriteRxDataToFifoSync1 <=#Tp 1'b0; + else + if(WriteRxDataToFifo) + WriteRxDataToFifoSync1 <=#Tp 1'b1; + else + WriteRxDataToFifoSync1 <=#Tp 1'b0; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + WriteRxDataToFifoSync2 <=#Tp 1'b0; + else + WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + WriteRxDataToFifoSync3 <=#Tp 1'b0; + else + WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2; +end + +wire WriteRxDataToFifo_wb; +assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3; + + +reg LatchedRxStartFrm; +reg SyncRxStartFrm; +reg SyncRxStartFrm_q; +reg SyncRxStartFrm_q2; +wire RxFifoReset; + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LatchedRxStartFrm <=#Tp 0; + else + if(RxStartFrm & ~SyncRxStartFrm_q) + LatchedRxStartFrm <=#Tp 1; + else + if(SyncRxStartFrm_q) + LatchedRxStartFrm <=#Tp 0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + SyncRxStartFrm <=#Tp 0; + else + if(LatchedRxStartFrm) + SyncRxStartFrm <=#Tp 1; + else + SyncRxStartFrm <=#Tp 0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + SyncRxStartFrm_q <=#Tp 0; + else + SyncRxStartFrm_q <=#Tp SyncRxStartFrm; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + SyncRxStartFrm_q2 <=#Tp 0; + else + SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q; +end + + +assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; + + +eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH) +rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), + .clk(WB_CLK_I), .reset(Reset), + .write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i), + .clear(RxFifoReset), .full(RxBufferFull), + .almost_full(), .almost_empty(RxBufferAlmostEmpty), + .empty(RxBufferEmpty), .cnt(rxfifo_cnt) + ); + +assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH; +assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH; +assign WriteRxDataToMemory = ~RxBufferEmpty; +assign rx_burst = rx_burst_en & WriteRxDataToMemory; + + +// Generation of the end-of-frame signal +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ShiftEnded_rck <=#Tp 1'b0; + else + if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) + ShiftEnded_rck <=#Tp 1'b1; + else + if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) + ShiftEnded_rck <=#Tp 1'b0; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ShiftEndedSync1 <=#Tp 1'b0; + else + ShiftEndedSync1 <=#Tp ShiftEnded_rck; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ShiftEndedSync2 <=#Tp 1'b0; + else + ShiftEndedSync2 <=#Tp ShiftEndedSync1; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ShiftEndedSync3 <=#Tp 1'b0; + else + if(ShiftEndedSync1 & ~ShiftEndedSync2) + ShiftEndedSync3 <=#Tp 1'b1; + else + if(ShiftEnded) + ShiftEndedSync3 <=#Tp 1'b0; +end + +// Generation of the end-of-frame signal +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + ShiftEnded <=#Tp 1'b0; + else + if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) + ShiftEnded <=#Tp 1'b1; + else + if(RxStatusWrite) + ShiftEnded <=#Tp 1'b0; +end + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ShiftEndedSync_c1 <=#Tp 1'b0; + else + ShiftEndedSync_c1 <=#Tp ShiftEndedSync2; +end + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + ShiftEndedSync_c2 <=#Tp 1'b0; + else + ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1; +end + +// Generation of the end-of-frame signal +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxEnableWindow <=#Tp 1'b0; + else + if(RxStartFrm) + RxEnableWindow <=#Tp 1'b1; + else + if(RxEndFrm | RxAbort) + RxEnableWindow <=#Tp 1'b0; +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxAbortSync1 <=#Tp 1'b0; + else + RxAbortSync1 <=#Tp RxAbortLatched; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxAbortSync2 <=#Tp 1'b0; + else + RxAbortSync2 <=#Tp RxAbortSync1; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxAbortSync3 <=#Tp 1'b0; + else + RxAbortSync3 <=#Tp RxAbortSync2; +end + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxAbortSync4 <=#Tp 1'b0; + else + RxAbortSync4 <=#Tp RxAbortSync3; +end + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxAbortSyncb1 <=#Tp 1'b0; + else + RxAbortSyncb1 <=#Tp RxAbortSync2; +end + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxAbortSyncb2 <=#Tp 1'b0; + else + RxAbortSyncb2 <=#Tp RxAbortSyncb1; +end + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxAbortLatched <=#Tp 1'b0; + else + if(RxAbortSyncb2) + RxAbortLatched <=#Tp 1'b0; + else + if(RxAbort) + RxAbortLatched <=#Tp 1'b1; +end + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + LatchedRxLength[15:0] <=#Tp 16'h0; + else + if(LoadRxStatus) + LatchedRxLength[15:0] <=#Tp RxLength[15:0]; +end + + +assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + RxStatusInLatched <=#Tp 'h0; + else + if(LoadRxStatus) + RxStatusInLatched <=#Tp RxStatusIn; +end + + +// Rx overrun +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxOverrun <=#Tp 1'b0; + else + if(RxStatusWrite) + RxOverrun <=#Tp 1'b0; + else + if(RxBufferFull & WriteRxDataToFifo_wb) + RxOverrun <=#Tp 1'b1; +end + + + +wire TxError; +assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost; + +wire RxError; + +// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames +// are aborted when signal r_RecSmall is set to 0 in MODER register. +// AddressMiss is identifying that a frame was received because of the promiscous +// mode and is not an error +assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]); + + + +reg RxStatusWriteLatched; +reg RxStatusWriteLatched_sync1; +reg RxStatusWriteLatched_sync2; +reg RxStatusWriteLatched_syncb1; +reg RxStatusWriteLatched_syncb2; + + +// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxStatusWriteLatched <=#Tp 1'b0; + else + if(RxStatusWriteLatched_syncb2) + RxStatusWriteLatched <=#Tp 1'b0; + else + if(RxStatusWrite) + RxStatusWriteLatched <=#Tp 1'b1; +end + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + begin + RxStatusWriteLatched_sync1 <=#Tp 1'b0; + RxStatusWriteLatched_sync2 <=#Tp 1'b0; + end + else + begin + RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched; + RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1; + end +end + + +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + begin + RxStatusWriteLatched_syncb1 <=#Tp 1'b0; + RxStatusWriteLatched_syncb2 <=#Tp 1'b0; + end + else + begin + RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2; + RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1; + end +end + + + +// Tx Done Interrupt +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxB_IRQ <=#Tp 1'b0; + else + if(TxStatusWrite & TxIRQEn) + TxB_IRQ <=#Tp ~TxError; + else + TxB_IRQ <=#Tp 1'b0; +end + + +// Tx Error Interrupt +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + TxE_IRQ <=#Tp 1'b0; + else + if(TxStatusWrite & TxIRQEn) + TxE_IRQ <=#Tp TxError; + else + TxE_IRQ <=#Tp 1'b0; +end + + +// Rx Done Interrupt +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxB_IRQ <=#Tp 1'b0; + else + if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) + RxB_IRQ <=#Tp (~RxError); + else + RxB_IRQ <=#Tp 1'b0; +end + + +// Rx Error Interrupt +always @ (posedge WB_CLK_I or posedge Reset) +begin + if(Reset) + RxE_IRQ <=#Tp 1'b0; + else + if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) + RxE_IRQ <=#Tp RxError; + else + RxE_IRQ <=#Tp 1'b0; +end + + +// Busy Interrupt + +reg Busy_IRQ_rck; +reg Busy_IRQ_sync1; +reg Busy_IRQ_sync2; +reg Busy_IRQ_sync3; +reg Busy_IRQ_syncb1; +reg Busy_IRQ_syncb2; + + +always @ (posedge MRxClk or posedge Reset) +begin + if(Reset) + Busy_IRQ_rck <=#Tp 1'b0; + else + if(RxValid & RxStartFrm & ~RxReady) + Busy_IRQ_rck <=#Tp 1'b1; + else + if(Busy_IRQ_syncb2) + Busy_IRQ_rck <=#Tp 1'b0; +end + +always @ (posedge WB_CLK_I) +begin + Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck; + Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1; + Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2; +end + +always @ (posedge MRxClk) +begin + Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2; + Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1; +end + +assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3; + + + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/timescale.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/timescale.v new file mode 100644 index 000000000..49516f072 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/timescale.v @@ -0,0 +1,53 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: timescale.v,v $ +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 11:36:31 mohor +// Log file added. +// +// +// + +`timescale 1ns / 1ns diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/xilinx_dist_ram_16x32.v b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/xilinx_dist_ram_16x32.v new file mode 100644 index 000000000..374357ce0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/xilinx_dist_ram_16x32.v @@ -0,0 +1,50 @@ +module xilinx_dist_ram_16x32 +( + data_out, + we, + data_in, + read_address, + write_address, + wclk +); + output [31:0] data_out; + input we, wclk; + input [31:0] data_in; + input [3:0] write_address, read_address; + + wire [3:0] waddr = write_address ; + wire [3:0] raddr = read_address ; + + RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); + RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/ethernet/testbench/eth_cop.v b/openfpga_flow/benchmarks/iwls2005/ethernet/testbench/eth_cop.v new file mode 100644 index 000000000..b2eff1b20 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/ethernet/testbench/eth_cop.v @@ -0,0 +1,392 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_cop.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_cop.v,v $ +// Revision 1.4 2003/06/13 11:55:37 mohor +// Define file in eth_cop.v is changed to eth_defines.v. Some defines were +// moved from tb_eth_defines.v to eth_defines.v. +// +// Revision 1.3 2002/10/10 16:43:59 mohor +// Minor $display change. +// +// Revision 1.2 2002/09/09 12:54:13 mohor +// error acknowledge cycle termination added to display. +// +// Revision 1.1 2002/08/14 17:16:07 mohor +// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave +// interfaces: +// - Host connects to the master interface +// - Ethernet master (DMA) connects to the second master interface +// - Memory interface connects to the slave interface +// - Ethernet slave interface (access to registers and BDs) connects to second +// slave interface +// +// +// +// +// + +`include "eth_defines.v" +`include "timescale.v" + +module eth_cop +( + // WISHBONE common + wb_clk_i, wb_rst_i, + + // WISHBONE MASTER 1 + m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o, + m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o, + m1_wb_err_o, + + // WISHBONE MASTER 2 + m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o, + m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o, + m2_wb_err_o, + + // WISHBONE slave 1 + s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o, + s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i, + s1_wb_dat_o, + + // WISHBONE slave 2 + s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o, + s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i, + s2_wb_dat_o +); + +parameter Tp=1; + +// WISHBONE common +input wb_clk_i, wb_rst_i; + +// WISHBONE MASTER 1 +input [31:0] m1_wb_adr_i, m1_wb_dat_i; +input [3:0] m1_wb_sel_i; +input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i; +output [31:0] m1_wb_dat_o; +output m1_wb_ack_o, m1_wb_err_o; + +// WISHBONE MASTER 2 +input [31:0] m2_wb_adr_i, m2_wb_dat_i; +input [3:0] m2_wb_sel_i; +input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i; +output [31:0] m2_wb_dat_o; +output m2_wb_ack_o, m2_wb_err_o; + +// WISHBONE slave 1 +input [31:0] s1_wb_dat_i; +input s1_wb_ack_i, s1_wb_err_i; +output [31:0] s1_wb_adr_o, s1_wb_dat_o; +output [3:0] s1_wb_sel_o; +output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o; + +// WISHBONE slave 2 +input [31:0] s2_wb_dat_i; +input s2_wb_ack_i, s2_wb_err_i; +output [31:0] s2_wb_adr_o, s2_wb_dat_o; +output [3:0] s2_wb_sel_o; +output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o; + +reg m1_in_progress; +reg m2_in_progress; +reg [31:0] s1_wb_adr_o; +reg [3:0] s1_wb_sel_o; +reg s1_wb_we_o; +reg [31:0] s1_wb_dat_o; +reg s1_wb_cyc_o; +reg s1_wb_stb_o; +reg [31:0] s2_wb_adr_o; +reg [3:0] s2_wb_sel_o; +reg s2_wb_we_o; +reg [31:0] s2_wb_dat_o; +reg s2_wb_cyc_o; +reg s2_wb_stb_o; + +reg m1_wb_ack_o; +reg [31:0] m1_wb_dat_o; +reg m2_wb_ack_o; +reg [31:0] m2_wb_dat_o; + +reg m1_wb_err_o; +reg m2_wb_err_o; + +wire m_wb_access_finished; +wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2); +wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2); + +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + begin + m1_in_progress <=#Tp 0; + m2_in_progress <=#Tp 0; + s1_wb_adr_o <=#Tp 0; + s1_wb_sel_o <=#Tp 0; + s1_wb_we_o <=#Tp 0; + s1_wb_dat_o <=#Tp 0; + s1_wb_cyc_o <=#Tp 0; + s1_wb_stb_o <=#Tp 0; + s2_wb_adr_o <=#Tp 0; + s2_wb_sel_o <=#Tp 0; + s2_wb_we_o <=#Tp 0; + s2_wb_dat_o <=#Tp 0; + s2_wb_cyc_o <=#Tp 0; + s2_wb_stb_o <=#Tp 0; + end + else + begin + case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case + 5'b00_10_0, 5'b00_11_0 : + begin + m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m + if(`M1_ADDRESSED_S1) + begin + s1_wb_adr_o <=#Tp m1_wb_adr_i; + s1_wb_sel_o <=#Tp m1_wb_sel_i; + s1_wb_we_o <=#Tp m1_wb_we_i; + s1_wb_dat_o <=#Tp m1_wb_dat_i; + s1_wb_cyc_o <=#Tp 1'b1; + s1_wb_stb_o <=#Tp 1'b1; + end + else if(`M1_ADDRESSED_S2) + begin + s2_wb_adr_o <=#Tp m1_wb_adr_i; + s2_wb_sel_o <=#Tp m1_wb_sel_i; + s2_wb_we_o <=#Tp m1_wb_we_i; + s2_wb_dat_o <=#Tp m1_wb_dat_i; + s2_wb_cyc_o <=#Tp 1'b1; + s2_wb_stb_o <=#Tp 1'b1; + end + else + $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); + end + 5'b00_01_0 : + begin + m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m + if(`M2_ADDRESSED_S1) + begin + s1_wb_adr_o <=#Tp m2_wb_adr_i; + s1_wb_sel_o <=#Tp m2_wb_sel_i; + s1_wb_we_o <=#Tp m2_wb_we_i; + s1_wb_dat_o <=#Tp m2_wb_dat_i; + s1_wb_cyc_o <=#Tp 1'b1; + s1_wb_stb_o <=#Tp 1'b1; + end + else if(`M2_ADDRESSED_S2) + begin + s2_wb_adr_o <=#Tp m2_wb_adr_i; + s2_wb_sel_o <=#Tp m2_wb_sel_i; + s2_wb_we_o <=#Tp m2_wb_we_i; + s2_wb_dat_o <=#Tp m2_wb_dat_i; + s2_wb_cyc_o <=#Tp 1'b1; + s2_wb_stb_o <=#Tp 1'b1; + end + else + $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); + end + 5'b10_10_1, 5'b10_11_1 : + begin + m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. + if(`M1_ADDRESSED_S1) + begin + s1_wb_cyc_o <=#Tp 1'b0; + s1_wb_stb_o <=#Tp 1'b0; + end + else if(`M1_ADDRESSED_S2) + begin + s2_wb_cyc_o <=#Tp 1'b0; + s2_wb_stb_o <=#Tp 1'b0; + end + end + 5'b01_01_1, 5'b01_11_1 : + begin + m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. + if(`M2_ADDRESSED_S1) + begin + s1_wb_cyc_o <=#Tp 1'b0; + s1_wb_stb_o <=#Tp 1'b0; + end + else if(`M2_ADDRESSED_S2) + begin + s2_wb_cyc_o <=#Tp 1'b0; + s2_wb_stb_o <=#Tp 1'b0; + end + end + endcase + end +end + +// Generating Ack for master 1 +always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2) +begin + if(m1_in_progress) + begin + if(`M1_ADDRESSED_S1) begin + m1_wb_ack_o <= s1_wb_ack_i; + m1_wb_dat_o <= s1_wb_dat_i; + end + else if(`M1_ADDRESSED_S2) begin + m1_wb_ack_o <= s2_wb_ack_i; + m1_wb_dat_o <= s2_wb_dat_i; + end + end + else + m1_wb_ack_o <= 0; +end + + +// Generating Ack for master 2 +always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2) +begin + if(m2_in_progress) + begin + if(`M2_ADDRESSED_S1) begin + m2_wb_ack_o <= s1_wb_ack_i; + m2_wb_dat_o <= s1_wb_dat_i; + end + else if(`M2_ADDRESSED_S2) begin + m2_wb_ack_o <= s2_wb_ack_i; + m2_wb_dat_o <= s2_wb_dat_i; + end + end + else + m2_wb_ack_o <= 0; +end + + +// Generating Err for master 1 +always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or + m1_wb_cyc_i or m1_wb_stb_i) +begin + if(m1_in_progress) begin + if(`M1_ADDRESSED_S1) + m1_wb_err_o <= s1_wb_err_i; + else if(`M1_ADDRESSED_S2) + m1_wb_err_o <= s2_wb_err_i; + end + else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2) + m1_wb_err_o <= 1'b1; + else + m1_wb_err_o <= 1'b0; +end + + +// Generating Err for master 2 +always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or + m2_wb_cyc_i or m2_wb_stb_i) +begin + if(m2_in_progress) begin + if(`M2_ADDRESSED_S1) + m2_wb_err_o <= s1_wb_err_i; + else if(`M2_ADDRESSED_S2) + m2_wb_err_o <= s2_wb_err_i; + end + else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2) + m2_wb_err_o <= 1'b1; + else + m2_wb_err_o <= 1'b0; +end + + +assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o; + + +// Activity monitor +integer cnt; +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if(wb_rst_i) + cnt <=#Tp 0; + else + if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i) + cnt <=#Tp 0; + else + if(s1_wb_cyc_o | s2_wb_cyc_o) + cnt <=#Tp cnt+1; +end + +always @ (posedge wb_clk_i) +begin + if(cnt==1000) begin + $display("(%0t)(%m) ERROR: WB activity ??? ", $time); + if(s1_wb_cyc_o) begin + $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); + $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); + $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); + $display("s1_wb_we_o = 0x%0x", s1_wb_we_o); + end + else if(s2_wb_cyc_o) begin + $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); + $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); + $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); + $display("s2_wb_we_o = 0x%0x", s2_wb_we_o); + end + + $stop; + end +end + + +always @ (posedge wb_clk_i) +begin + if(s1_wb_err_i & s1_wb_cyc_o) begin + $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); + $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); + $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); + $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); + $display("s1_wb_we_o = 0x%0x", s1_wb_we_o); + $stop; + end + if(s2_wb_err_i & s2_wb_cyc_o) begin + $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); + $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); + $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); + $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); + $display("s2_wb_we_o = 0x%0x", s2_wb_we_o); + $stop; + end +end + + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/fpu/rtl/except.v b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/except.v new file mode 100644 index 000000000..007099fe1 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/except.v @@ -0,0 +1,153 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// EXCEPT //// +//// Floating Point Exception/Special Numbers Unit //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 100ps + + +module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan, + opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn); +input clk; +input [31:0] opa, opb; +output inf, ind, qnan, snan, opa_nan, opb_nan; +output opa_00, opb_00; +output opa_inf, opb_inf; +output opa_dn; +output opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +reg expa_ff, infa_f_r, qnan_r_a, snan_r_a; +reg expb_ff, infb_f_r, qnan_r_b, snan_r_b; +reg inf, ind, qnan, snan; // Output registers +reg opa_nan, opb_nan; +reg expa_00, expb_00, fracta_00, fractb_00; +reg opa_00, opb_00; +reg opa_inf, opb_inf; +reg opa_dn, opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Determine if any of the input operators is a INF or NAN or any other special number +// + +always @(posedge clk) + expa_ff <= #1 &expa; + +always @(posedge clk) + expb_ff <= #1 &expb; + +always @(posedge clk) + infa_f_r <= #1 !(|fracta); + +always @(posedge clk) + infb_f_r <= #1 !(|fractb); + +always @(posedge clk) + qnan_r_a <= #1 fracta[22]; + +always @(posedge clk) + snan_r_a <= #1 !fracta[22] & |fracta[21:0]; + +always @(posedge clk) + qnan_r_b <= #1 fractb[22]; + +always @(posedge clk) + snan_r_b <= #1 !fractb[22] & |fractb[21:0]; + +always @(posedge clk) + ind <= #1 (expa_ff & infa_f_r) & (expb_ff & infb_f_r); + +always @(posedge clk) + inf <= #1 (expa_ff & infa_f_r) | (expb_ff & infb_f_r); + +always @(posedge clk) + qnan <= #1 (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b); + +always @(posedge clk) + snan <= #1 (expa_ff & snan_r_a) | (expb_ff & snan_r_b); + +always @(posedge clk) + opa_nan <= #1 &expa & (|fracta[22:0]); + +always @(posedge clk) + opb_nan <= #1 &expb & (|fractb[22:0]); + +always @(posedge clk) + opa_inf <= #1 (expa_ff & infa_f_r); + +always @(posedge clk) + opb_inf <= #1 (expb_ff & infb_f_r); + +always @(posedge clk) + expa_00 <= #1 !(|expa); + +always @(posedge clk) + expb_00 <= #1 !(|expb); + +always @(posedge clk) + fracta_00 <= #1 !(|fracta); + +always @(posedge clk) + fractb_00 <= #1 !(|fractb); + +always @(posedge clk) + opa_00 <= #1 expa_00 & fracta_00; + +always @(posedge clk) + opb_00 <= #1 expb_00 & fractb_00; + +always @(posedge clk) + opa_dn <= #1 expa_00; + +always @(posedge clk) + opb_dn <= #1 expb_00; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/fpu/rtl/fpu.v b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/fpu.v new file mode 100644 index 000000000..165a1d246 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/fpu.v @@ -0,0 +1,560 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FPU //// +//// Floating Point Unit (Single precision) //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + +/* + +FPU Operations (fpu_op): +======================== + +0 = add +1 = sub +2 = mul +3 = div +4 = +5 = +6 = +7 = + +Rounding Modes (rmode): +======================= + +0 = round_nearest_even +1 = round_to_zero +2 = round_up +3 = round_down + +*/ + + +module fpu( clk, rmode, fpu_op, opa, opb, out, inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero); +input clk; +input [1:0] rmode; +input [2:0] fpu_op; +input [31:0] opa, opb; +output [31:0] out; +output inf, snan, qnan; +output ine; +output overflow, underflow; +output zero; +output div_by_zero; + +parameter INF = 31'h7f800000, + QNAN = 31'h7fc00001, + SNAN = 31'h7f800001; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires +// +reg zero; +reg [31:0] opa_r, opb_r; // Input operand registers +reg [31:0] out; // Output register +reg div_by_zero; // Divide by zero output register +wire signa, signb; // alias to opX sign +wire sign_fasu; // sign output +wire [26:0] fracta, fractb; // Fraction Outputs from EQU block +wire [7:0] exp_fasu; // Exponent output from EQU block +reg [7:0] exp_r; // Exponent output (registerd) +wire [26:0] fract_out_d; // fraction output +wire co; // carry output +reg [27:0] fract_out_q; // fraction output (registerd) +wire [30:0] out_d; // Intermediate final result output +wire overflow_d, underflow_d;// Overflow/Underflow Indicators +reg overflow, underflow; // Output registers for Overflow & Underflow +reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN +reg ine; // Output Registers for INE +reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode + rmode_r3; +reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration + fpu_op_r3; +wire mul_inf, div_inf; +wire mul_00, div_00; + +//////////////////////////////////////////////////////////////////////// +// +// Input Registers +// + +always @(posedge clk) + opa_r <= #1 opa; + +always @(posedge clk) + opb_r <= #1 opb; + +always @(posedge clk) + rmode_r1 <= #1 rmode; + +always @(posedge clk) + rmode_r2 <= #1 rmode_r1; + +always @(posedge clk) + rmode_r3 <= #1 rmode_r2; + +always @(posedge clk) + fpu_op_r1 <= #1 fpu_op; + +always @(posedge clk) + fpu_op_r2 <= #1 fpu_op_r1; + +always @(posedge clk) + fpu_op_r3 <= #1 fpu_op_r2; + +//////////////////////////////////////////////////////////////////////// +// +// Exceptions block +// +wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; +wire opa_00, opb_00; +wire opa_inf, opb_inf; +wire opa_dn, opb_dn; + +except u0( .clk(clk), + .opa(opa_r), .opb(opb_r), + .inf(inf_d), .ind(ind_d), + .qnan(qnan_d), .snan(snan_d), + .opa_nan(opa_nan), .opb_nan(opb_nan), + .opa_00(opa_00), .opb_00(opb_00), + .opa_inf(opa_inf), .opb_inf(opb_inf), + .opa_dn(opa_dn), .opb_dn(opb_dn) + ); + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize block +// - Adjusts the numbers to equal exponents and sorts them +// - determine result sign +// - determine actual operation to perform (add or sub) +// + +wire nan_sign_d, result_zero_sign_d; +reg sign_fasu_r; +wire [7:0] exp_mul; +wire sign_mul; +reg sign_mul_r; +wire [23:0] fracta_mul, fractb_mul; +wire inf_mul; +reg inf_mul_r; +wire [1:0] exp_ovf; +reg [1:0] exp_ovf_r; +wire sign_exe; +reg sign_exe_r; +wire [2:0] underflow_fmul_d; + + +pre_norm u1(.clk(clk), // System Clock + .rmode(rmode_r2), // Roundin Mode + .add(!fpu_op_r1[0]), // Add/Sub Input + .opa(opa_r), .opb(opb_r), // Registered OP Inputs + .opa_nan(opa_nan), // OpA is a NAN indicator + .opb_nan(opb_nan), // OpB is a NAN indicator + .fracta_out(fracta), // Equalized and sorted fraction + .fractb_out(fractb), // outputs (Registered) + .exp_dn_out(exp_fasu), // Selected exponent output (registered); + .sign(sign_fasu), // Encoded output Sign (registered) + .nan_sign(nan_sign_d), // Output Sign for NANs (registered) + .result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered) + .fasu_op(fasu_op) // Actual fasu operation output (registered) + ); + +always @(posedge clk) + sign_fasu_r <= #1 sign_fasu; + +pre_norm_fmul u2( + .clk(clk), + .fpu_op(fpu_op_r1), + .opa(opa_r), .opb(opb_r), + .fracta(fracta_mul), + .fractb(fractb_mul), + .exp_out(exp_mul), // FMUL exponent output (registered) + .sign(sign_mul), // FMUL sign output (registered) + .sign_exe(sign_exe), // FMUL exception sign output (registered) + .inf(inf_mul), // FMUL inf output (registered) + .exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered) + .underflow(underflow_fmul_d) + ); + + +always @(posedge clk) + sign_mul_r <= #1 sign_mul; + +always @(posedge clk) + sign_exe_r <= #1 sign_exe; + +always @(posedge clk) + inf_mul_r <= #1 inf_mul; + +always @(posedge clk) + exp_ovf_r <= #1 exp_ovf; + + +//////////////////////////////////////////////////////////////////////// +// +// Add/Sub +// + +add_sub27 u3( + .add(fasu_op), // Add/Sub + .opa(fracta), // Fraction A input + .opb(fractb), // Fraction B Input + .sum(fract_out_d), // SUM output + .co(co_d) ); // Carry Output + +always @(posedge clk) + fract_out_q <= #1 {co_d, fract_out_d}; + +//////////////////////////////////////////////////////////////////////// +// +// Mul +// +wire [47:0] prod; + +mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod)); + +//////////////////////////////////////////////////////////////////////// +// +// Divide +// +wire [49:0] quo; +wire [49:0] fdiv_opa; +wire [49:0] remainder; +wire remainder_00; +reg [4:0] div_opa_ldz_d, div_opa_ldz_r1, div_opa_ldz_r2; + +always @(fracta_mul) + casex(fracta_mul[22:0]) + 23'b1??????????????????????: div_opa_ldz_d = 1; + 23'b01?????????????????????: div_opa_ldz_d = 2; + 23'b001????????????????????: div_opa_ldz_d = 3; + 23'b0001???????????????????: div_opa_ldz_d = 4; + 23'b00001??????????????????: div_opa_ldz_d = 5; + 23'b000001?????????????????: div_opa_ldz_d = 6; + 23'b0000001????????????????: div_opa_ldz_d = 7; + 23'b00000001???????????????: div_opa_ldz_d = 8; + 23'b000000001??????????????: div_opa_ldz_d = 9; + 23'b0000000001?????????????: div_opa_ldz_d = 10; + 23'b00000000001????????????: div_opa_ldz_d = 11; + 23'b000000000001???????????: div_opa_ldz_d = 12; + 23'b0000000000001??????????: div_opa_ldz_d = 13; + 23'b00000000000001?????????: div_opa_ldz_d = 14; + 23'b000000000000001????????: div_opa_ldz_d = 15; + 23'b0000000000000001???????: div_opa_ldz_d = 16; + 23'b00000000000000001??????: div_opa_ldz_d = 17; + 23'b000000000000000001?????: div_opa_ldz_d = 18; + 23'b0000000000000000001????: div_opa_ldz_d = 19; + 23'b00000000000000000001???: div_opa_ldz_d = 20; + 23'b000000000000000000001??: div_opa_ldz_d = 21; + 23'b0000000000000000000001?: div_opa_ldz_d = 22; + 23'b0000000000000000000000?: div_opa_ldz_d = 23; + endcase + +assign fdiv_opa = !(|opa_r[30:23]) ? {(fracta_mul<f2i_emax)) | (opas & (exp_inf2i_emax)) | (opas & (exp_in8'h16); + +assign f2i_shft = exp_in-8'h7d; + +// Select shifting direction +assign left_right = op_div ? lr_div : op_mul ? lr_mul : 1; + +assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1 : + (op_dn & exp_ovf[1]) ? 0 : + (op_dn & div_shft1_co) ? 0 : + (op_dn & exp_out_00) ? 1 : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? 1 : + exp_ovf[1] ? 0 : + 1; +assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1 : + ( exp_ovf[1] | exp_in_00 ) ? 0 : + 1; + +// Select Left and Right shift value +assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h2 : exp_in_pl1[7:0]) : {2'h0, fi_ldz}; +assign shift_right = op_div ? shftr_div : shftr_mul; + +assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz}; + +assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift; + +assign shftl_mul = (shft_co | + (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz}; + +assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] : + {2'h0, fi_ldz}; +assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 : + (op_dn & div_shft1_co) ? div_shft4 : + div_shft2; +// Do the actual shifting +assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0]; +assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<f2i_emax) ? 0 : opas) : + ((exp_inf2i_emax) ? 1 : opas); + +assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz); +assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<9'hfe) )) ? div_exp2 : + (opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 0 : + exp_out1_mi1; + +assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f); + +// --------------------------------------------------------------------- +// Round + +// Extract rounding (GRS) bits +assign grs_sel_div = op_div & (exp_ovf[1] | div_dn | exp_out1_co | exp_out_00); + +assign g = grs_sel_div ? fract_out[0] : fract_out[0]; +assign r = grs_sel_div ? (fract_trunc[24] & !div_nr) : fract_trunc[24]; +assign s = grs_sel_div ? |fract_trunc[24:0] : (|fract_trunc[23:0] | (fract_trunc[24] & op_div)); + +// Round to nearest even +assign round = (g & r) | (r & s) ; +assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out}; +assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out; +assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i; + +// round to zero +assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out; +assign exp_fix_div = (fi_ldz>22) ? exp_fix_diva : exp_fix_divb; +assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) : + (exp_out_ff & !op_f2i) ? exp_in : exp_out; +assign ovf1 = exp_out_ff & !dn; + +// round to +inf (UP) and -inf (DOWN) +assign r_sign = sign; + +assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff); +assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a)); + +assign round2_fmul = !r_sign & + ( + (exp_ovf[1] & !fract_in_00 & + ( ((!exp_out1_co | op_dn) & (r | s | (!rem_00 & op_div) )) | fract_out_00 | (!op_dn & !op_div)) + ) | + ( + (r | s | (!rem_00 & op_div)) & ( + (!exp_ovf[1] & (exp_in_80 | !exp_ovf[0])) | op_div | + ( exp_ovf[1] & !exp_ovf[0] & exp_out1_co) + ) + ) + ); + +assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc)); +assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu; + +assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out}; +assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out; + +assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a; +assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a; + + +// Choose rounding mode +always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2) + case(rmode) // synopsys full_case parallel_case + 0: exp_out_rnd = exp_out_rnd0; + 1: exp_out_rnd = exp_out_rnd1; + 2,3: exp_out_rnd = exp_out_rnd2; + endcase + +always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2) + case(rmode) // synopsys full_case parallel_case + 0: fract_out_rnd = fract_out_rnd0; + 1: fract_out_rnd = fract_out_rnd1; + 2,3: fract_out_rnd = fract_out_rnd2; + endcase + +// --------------------------------------------------------------------- +// Final Output Mux +// Fix Output for denormalized and special numbers +wire max_num, inf_out; + +assign max_num = ( !rmode_00 & (op_mul | op_div ) & ( + ( exp_ovf[1] & exp_ovf[0]) | + (!exp_ovf[1] & !exp_ovf[0] & exp_in_ff & (fi_ldz_2<24) & (exp_out!=8'hfe) ) + ) + ) | + + ( op_div & ( + ( rmode_01 & ( div_inf | + (exp_out_ff & !exp_ovf[1] ) | + (exp_ovf[1] & exp_ovf[0] ) + ) + ) | + + ( rmode[1] & !exp_ovf[1] & ( + ( exp_ovf[0] & exp_in_ff & r_sign & fract_in[47] + ) | + + ( r_sign & ( + (fract_in[47] & div_inf) | + (exp_in[7] & !exp_out_rnd[7] & !exp_in_80 & exp_out!=8'h7f ) | + (exp_in[7] & exp_out_rnd[7] & r_sign & exp_out_ff & op_dn & + div_exp1>9'h0fe ) + ) + ) | + + ( exp_in_00 & r_sign & ( + div_inf | + (r_sign & exp_out_ff & fi_ldz_2<24) + ) + ) + ) + ) + ) + ); + + +assign inf_out = (rmode[1] & (op_mul | op_div) & !r_sign & ( (exp_in_ff & !op_div) | + (exp_ovf[1] & exp_ovf[0] & (exp_in_00 | exp_in[7]) ) + ) + ) | (div_inf & op_div & ( + rmode_00 | + (rmode[1] & !exp_in_ff & !exp_ovf[1] & !exp_ovf[0] & !r_sign ) | + (rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign) + ) + ) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 24) & (exp_out_rnd!=8'hfe) ); + +assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h0 : + (max_num | (f2i_max & op_f2i) ) ? 23'h7fffff : + fract_out_rnd; + +assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 : + ((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff : + max_num ? 8'hfe : + exp_out_rnd; + + +// --------------------------------------------------------------------- +// Pack Result + +assign out = {exp_out_final, fract_out_final}; + +// --------------------------------------------------------------------- +// Exceptions +wire underflow_fmul; +wire overflow_fdiv; +wire undeflow_div; + +wire z = shft_co | ( exp_ovf[1] | exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00)); + +assign underflow_fmul = ( (|fract_trunc) & z & !exp_in_ff ) | + (fract_out_00 & !fract_in_00 & exp_ovf[1]); + +assign undeflow_div = !(exp_ovf[1] & exp_ovf[0] & rmode_00) & !inf_out & !max_num & exp_out_final!=8'hff & ( + + ((|fract_trunc) & !opb_dn & ( + ( op_dn & !exp_ovf[1] & exp_ovf[0]) | + ( op_dn & exp_ovf[1]) | + ( op_dn & div_shft1_co) | + exp_out_00 | + exp_ovf[1] + ) + + ) | + + ( exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & exp_in>8'h16 & fi_ldz<23) | + ( op_dn & exp_in<23 & fi_ldz<23 & !rem_00) | + ( !op_dn & (exp_in[7]==exp_div[7]) & !rem_00) | + ( !op_dn & exp_in_00 & (exp_div[7:1]==7'h7f) ) | + ( !op_dn & exp_in<8'h7f & exp_in>8'h20 ) + ) + ) | + + (!exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & fi_ldz<23 & exp_out_00) | + ( exp_in_00 & !rem_00) | + ( !op_dn & ldz_all<23 & exp_in==1 & exp_out_00 & !rem_00) + ) + ) + + ); + +assign underflow = op_div ? undeflow_div : op_mul ? underflow_fmul : (!fract_in[47] & exp_out1_co) & !dn; + +assign overflow_fdiv = inf_out | + (!rmode_00 & max_num) | + (exp_in[7] & op_dn & exp_out_ff) | + (exp_ovf[0] & (exp_ovf[1] | exp_out_ff) ); + +assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1); + +wire f2i_ine; + +assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) | + (|fract_trunc) | + (f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) | + (f2i_max & rmode_11 & (exp_in<8'h80)); + + + +assign ine = op_f2i ? f2i_ine : + op_i2f ? (|fract_trunc) : + ((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00)); + +// --------------------------------------------------------------------- +// Debugging Stuff + +// synopsys translate_off + +wire [26:0] fracta_del, fractb_del; +wire [2:0] grs_del; +wire dn_del; +wire [7:0] exp_in_del; +wire [7:0] exp_out_del; +wire [22:0] fract_out_del; +wire [47:0] fract_in_del; +wire overflow_del; +wire [1:0] exp_ovf_del; +wire [22:0] fract_out_x_del, fract_out_rnd2a_del; +wire [24:0] trunc_xx_del; +wire exp_rnd_adj2a_del; +wire [22:0] fract_dn_del; +wire [4:0] div_opa_ldz_del; +wire [23:0] fracta_div_del; +wire [23:0] fractb_div_del; +wire div_inf_del; +wire [7:0] fi_ldz_2_del; +wire inf_out_del, max_out_del; +wire [5:0] fi_ldz_del; +wire rx_del; +wire ez_del; +wire lr; +wire [7:0] shr, shl, exp_div_del; + +delay2 #26 ud000(clk, test.u0.fracta, fracta_del); +delay2 #26 ud001(clk, test.u0.fractb, fractb_del); +delay1 #2 ud002(clk, {g,r,s}, grs_del); +delay1 #0 ud004(clk, dn, dn_del); +delay1 #7 ud005(clk, exp_in, exp_in_del); +delay1 #7 ud007(clk, exp_out_rnd, exp_out_del); +delay1 #47 ud009(clk, fract_in, fract_in_del); +delay1 #0 ud010(clk, overflow, overflow_del); +delay1 #1 ud011(clk, exp_ovf, exp_ovf_del); +delay1 #22 ud014(clk, fract_out, fract_out_x_del); +delay1 #24 ud015(clk, fract_trunc, trunc_xx_del); +delay1 #0 ud017(clk, exp_rnd_adj2a, exp_rnd_adj2a_del); +delay1 #4 ud019(clk, div_opa_ldz, div_opa_ldz_del); +delay3 #23 ud020(clk, test.u0.fdiv_opa[49:26], fracta_div_del); +delay3 #23 ud021(clk, test.u0.fractb_mul, fractb_div_del); +delay1 #0 ud023(clk, div_inf, div_inf_del); +delay1 #7 ud024(clk, fi_ldz_2, fi_ldz_2_del); +delay1 #0 ud025(clk, inf_out, inf_out_del); +delay1 #0 ud026(clk, max_num, max_num_del); +delay1 #5 ud027(clk, fi_ldz, fi_ldz_del); +delay1 #0 ud028(clk, rem_00, rx_del); + +delay1 #0 ud029(clk, left_right, lr); +delay1 #7 ud030(clk, shift_right, shr); +delay1 #7 ud031(clk, shift_left, shl); +delay1 #22 ud032(clk, fract_out_rnd2a, fract_out_rnd2a_del); + +delay1 #7 ud033(clk, exp_div, exp_div_del); + +always @(test.error_event) + begin + + $display("\n----------------------------------------------"); + + $display("ERROR: GRS: %b exp_ovf: %b dn: %h exp_in: %h exp_out: %h, exp_rnd_adj2a: %b", + grs_del, exp_ovf_del, dn_del, exp_in_del, exp_out_del, exp_rnd_adj2a_del); + + $display(" div_opa: %b, div_opb: %b, rem_00: %b, exp_div: %h", + fracta_div_del, fractb_div_del, rx_del, exp_div_del); + + $display(" lr: %b, shl: %h, shr: %h", + lr, shl, shr); + + + $display(" overflow: %b, fract_in=%b fa:%h fb:%h", + overflow_del, fract_in_del, fracta_del, fractb_del); + + $display(" div_opa_ldz: %h, div_inf: %b, inf_out: %b, max_num: %b, fi_ldz: %h, fi_ldz_2: %h", + div_opa_ldz_del, div_inf_del, inf_out_del, max_num_del, fi_ldz_del, fi_ldz_2_del); + + $display(" fract_out_x: %b, fract_out_rnd2a_del: %h, fract_trunc: %b\n", + fract_out_x_del, fract_out_rnd2a_del, trunc_xx_del); + end + + +// synopsys translate_on + +endmodule + +// synopsys translate_off + +module delay1(clk, in, out); +parameter N = 1; +input [N:0] in; +output [N:0] out; +input clk; + +reg [N:0] out; + +always @(posedge clk) + out <= #1 in; + +endmodule + + +module delay2(clk, in, out); +parameter N = 1; +input [N:0] in; +output [N:0] out; +input clk; + +reg [N:0] out, r1; + +always @(posedge clk) + r1 <= #1 in; + +always @(posedge clk) + out <= #1 r1; + +endmodule + +module delay3(clk, in, out); +parameter N = 1; +input [N:0] in; +output [N:0] out; +input clk; + +reg [N:0] out, r1, r2; + +always @(posedge clk) + r1 <= #1 in; + +always @(posedge clk) + r2 <= #1 r1; + +always @(posedge clk) + out <= #1 r2; + +endmodule + +// synopsys translate_on \ No newline at end of file diff --git a/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm.v b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm.v new file mode 100644 index 000000000..c54c71fa2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm.v @@ -0,0 +1,270 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Pre Normalize //// +//// Pre Normalization Unit for Add/Sub Operations //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + + +module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out, + fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign, + fasu_op); +input clk; +input [1:0] rmode; +input add; +input [31:0] opa, opb; +input opa_nan, opb_nan; +output [26:0] fracta_out, fractb_out; +output [7:0] exp_dn_out; +output sign; +output nan_sign, result_zero_sign; +output fasu_op; // Operation Output + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire signa, signb; // alias to opX sign +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +wire expa_lt_expb; // expa is larger than expb indicator +wire fractb_lt_fracta; // fractb is larger than fracta indicator +reg [7:0] exp_dn_out; // de normalized exponent output +wire [7:0] exp_small, exp_large; +wire [7:0] exp_diff; // Numeric difference of the two exponents +wire [22:0] adj_op; // Fraction adjustment: input +wire [26:0] adj_op_tmp; +wire [26:0] adj_op_out; // Fraction adjustment: output +wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing +wire [26:0] fracta_s, fractb_s; // Fraction Sorting out +reg [26:0] fracta_out, fractb_out; // Fraction Output +reg sign, sign_d; // Sign Output +reg add_d; // operation (add/sub) +reg fasu_op; // operation (add/sub) register +wire expa_dn, expb_dn; +reg sticky; +reg result_zero_sign; +reg add_r, signa_r, signb_r; +wire [4:0] exp_diff_sft; +wire exp_lt_27; +wire op_dn; +wire [26:0] adj_op_out_sft; +reg fracta_lt_fractb, fracta_eq_fractb; +wire nan_sign1; +reg nan_sign; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize exponents (and fractions) +// + +assign expa_lt_expb = expa > expb; // expa is larger than expb + +// --------------------------------------------------------------------- +// Normalize + +assign expa_dn = !(|expa); // opa denormalized +assign expb_dn = !(|expb); // opb denormalized + +// --------------------------------------------------------------------- +// Calculate the difference between the smaller and larger exponent + +wire [7:0] exp_diff1, exp_diff1a, exp_diff2; + +assign exp_small = expa_lt_expb ? expb : expa; +assign exp_large = expa_lt_expb ? expa : expb; +assign exp_diff1 = exp_large - exp_small; +assign exp_diff1a = exp_diff1-1; +assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1; +assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2; + +always @(posedge clk) // If numbers are equal we should return zero + exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large; + +// --------------------------------------------------------------------- +// Adjust the smaller fraction + + +assign op_dn = expa_lt_expb ? expb_dn : expa_dn; +assign adj_op = expa_lt_expb ? fractb : fracta; +assign adj_op_tmp = { ~op_dn, adj_op, 3'b0 }; // recover hidden bit (op_dn) + +// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right +assign exp_lt_27 = exp_diff > 8'd27; +assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0]; +assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft; +assign adj_op_out = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky }; + +// --------------------------------------------------------------------- +// Get truncated portion (sticky bit) + +always @(exp_diff_sft or adj_op_tmp) + case(exp_diff_sft) // synopsys full_case parallel_case + 00: sticky = 1'h0; + 01: sticky = adj_op_tmp[0]; + 02: sticky = |adj_op_tmp[01:0]; + 03: sticky = |adj_op_tmp[02:0]; + 04: sticky = |adj_op_tmp[03:0]; + 05: sticky = |adj_op_tmp[04:0]; + 06: sticky = |adj_op_tmp[05:0]; + 07: sticky = |adj_op_tmp[06:0]; + 08: sticky = |adj_op_tmp[07:0]; + 09: sticky = |adj_op_tmp[08:0]; + 10: sticky = |adj_op_tmp[09:0]; + 11: sticky = |adj_op_tmp[10:0]; + 12: sticky = |adj_op_tmp[11:0]; + 13: sticky = |adj_op_tmp[12:0]; + 14: sticky = |adj_op_tmp[13:0]; + 15: sticky = |adj_op_tmp[14:0]; + 16: sticky = |adj_op_tmp[15:0]; + 17: sticky = |adj_op_tmp[16:0]; + 18: sticky = |adj_op_tmp[17:0]; + 19: sticky = |adj_op_tmp[18:0]; + 20: sticky = |adj_op_tmp[19:0]; + 21: sticky = |adj_op_tmp[20:0]; + 22: sticky = |adj_op_tmp[21:0]; + 23: sticky = |adj_op_tmp[22:0]; + 24: sticky = |adj_op_tmp[23:0]; + 25: sticky = |adj_op_tmp[24:0]; + 26: sticky = |adj_op_tmp[25:0]; + 27: sticky = |adj_op_tmp[26:0]; + endcase + +// --------------------------------------------------------------------- +// Select operands for add/sub (recover hidden bit) + +assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out; +assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0}; + +// --------------------------------------------------------------------- +// Sort operands (for sub only) + +assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta +assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n; +assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n; + +always @(posedge clk) + fracta_out <= #1 fracta_s; + +always @(posedge clk) + fractb_out <= #1 fractb_s; + +// --------------------------------------------------------------------- +// Determine sign for the output + +// sign: 0=Positive Number; 1=Negative Number +always @(signa or signb or add or fractb_lt_fracta) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b0_0_1: sign_d = 0; + 3'b0_1_1: sign_d = fractb_lt_fracta; + 3'b1_0_1: sign_d = !fractb_lt_fracta; + 3'b1_1_1: sign_d = 1; + + // Sub + 3'b0_0_0: sign_d = fractb_lt_fracta; + 3'b0_1_0: sign_d = 0; + 3'b1_0_0: sign_d = 1; + 3'b1_1_0: sign_d = !fractb_lt_fracta; + endcase + +always @(posedge clk) + sign <= #1 sign_d; + +// Fix sign for ZERO result +always @(posedge clk) + signa_r <= #1 signa; + +always @(posedge clk) + signb_r <= #1 signb; + +always @(posedge clk) + add_r <= #1 add; + +always @(posedge clk) + result_zero_sign <= #1 ( add_r & signa_r & signb_r) | + (!add_r & signa_r & !signb_r) | + ( add_r & (signa_r | signb_r) & (rmode==3)) | + (!add_r & (signa_r == signb_r) & (rmode==3)); + +// Fix sign for NAN result +always @(posedge clk) + fracta_lt_fractb <= #1 fracta < fractb; + +always @(posedge clk) + fracta_eq_fractb <= #1 fracta == fractb; + +assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r; + +always @(posedge clk) + nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r; + +//////////////////////////////////////////////////////////////////////// +// +// Decode Add/Sub operation +// + +// add: 1=Add; 0=Subtract +always @(signa or signb or add) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b0_0_1: add_d = 1; + 3'b0_1_1: add_d = 0; + 3'b1_0_1: add_d = 0; + 3'b1_1_1: add_d = 1; + + // Sub + 3'b0_0_0: add_d = 0; + 3'b0_1_0: add_d = 1; + 3'b1_0_0: add_d = 1; + 3'b1_1_0: add_d = 0; + endcase + +always @(posedge clk) + fasu_op <= #1 add_d; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm_fmul.v b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm_fmul.v new file mode 100644 index 000000000..26ddfeb75 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/pre_norm_fmul.v @@ -0,0 +1,150 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Pre Normalize //// +//// Floating Point Pre Normalization Unit for FMUL //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + +module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign, + sign_exe, inf, exp_ovf, underflow); +input clk; +input [2:0] fpu_op; +input [31:0] opa, opb; +output [23:0] fracta, fractb; +output [7:0] exp_out; +output sign, sign_exe; +output inf; +output [1:0] exp_ovf; +output [2:0] underflow; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +reg [7:0] exp_out; +wire signa, signb; +reg sign, sign_d; +reg sign_exe; +reg inf; +wire [1:0] exp_ovf_d; +reg [1:0] exp_ovf; +wire [7:0] expa, expb; +wire [7:0] exp_tmp1, exp_tmp2; +wire co1, co2; +wire expa_dn, expb_dn; +wire [7:0] exp_out_a; +wire opa_00, opb_00, fracta_00, fractb_00; +wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5; +wire [2:0] underflow_d; +reg [2:0] underflow; +wire op_div = (fpu_op == 3'b011); +wire [7:0] exp_out_mul, exp_out_div; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; + +//////////////////////////////////////////////////////////////////////// +// +// Calculate Exponenet +// + +assign expa_dn = !(|expa); +assign expb_dn = !(|expb); +assign opa_00 = !(|opa[30:0]); +assign opb_00 = !(|opb[30:0]); +assign fracta_00 = !(|opa[22:0]); +assign fractb_00 = !(|opb[22:0]); + +assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit +assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit + +assign {co1,exp_tmp1} = op_div ? (expa - expb) : (expa + expb); +assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 8'h7f) : ({co1,exp_tmp1} - 8'h7f); + +assign exp_tmp3 = exp_tmp2 + 1; +assign exp_tmp4 = 8'h7f - exp_tmp1; +assign exp_tmp5 = op_div ? (exp_tmp4+1) : (exp_tmp4-1); + + +always@(posedge clk) + exp_out <= #1 op_div ? exp_out_div : exp_out_mul; + +assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2; +assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2; +assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4; +assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]); +assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2); + +always @(posedge clk) + exp_ovf <= #1 exp_ovf_d; + +assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn); +assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) | + (expa_dn & !fracta_00) | (expb_dn & !fractb_00); +assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f); + +always @(posedge clk) + underflow <= #1 underflow_d; + +always @(posedge clk) + inf <= #1 op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ; + + +//////////////////////////////////////////////////////////////////////// +// +// Determine sign for the output +// + +// sign: 0=Posetive Number; 1=Negative Number +always @(signa or signb) + case({signa, signb}) // synopsys full_case parallel_case + 2'b0_0: sign_d = 0; + 2'b0_1: sign_d = 1; + 2'b1_0: sign_d = 1; + 2'b1_1: sign_d = 0; + endcase + +always @(posedge clk) + sign <= #1 sign_d; + +always @(posedge clk) + sign_exe <= #1 signa & signb; + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/iwls2005/fpu/rtl/primitives.v b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/primitives.v new file mode 100644 index 000000000..2e7f050e5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/fpu/rtl/primitives.v @@ -0,0 +1,103 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Primitives //// +//// FPU Primitives //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 100ps + + +//////////////////////////////////////////////////////////////////////// +// +// Add/Sub +// + +module add_sub27(add, opa, opb, sum, co); +input add; +input [26:0] opa, opb; +output [26:0] sum; +output co; + + + +assign {co, sum} = add ? (opa + opb) : (opa - opb); + +endmodule + +//////////////////////////////////////////////////////////////////////// +// +// Multiply +// + +module mul_r2(clk, opa, opb, prod); +input clk; +input [23:0] opa, opb; +output [47:0] prod; + +reg [47:0] prod1, prod; + +always @(posedge clk) + prod1 <= #1 opa * opb; + +always @(posedge clk) + prod <= #1 prod1; + +endmodule + +//////////////////////////////////////////////////////////////////////// +// +// Divide +// + +module div_r2(clk, opa, opb, quo, rem); +input clk; +input [49:0] opa; +input [23:0] opb; +output [49:0] quo, rem; + +reg [49:0] quo, rem, quo1, remainder; + +always @(posedge clk) + quo1 <= #1 opa / opb; + +always @(posedge clk) + quo <= #1 quo1; + +always @(posedge clk) + remainder <= #1 opa % opb; + +always @(posedge clk) + rem <= #1 remainder; + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_bit_ctrl.v b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_bit_ctrl.v new file mode 100644 index 000000000..17b2c8b1f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_bit_ctrl.v @@ -0,0 +1,535 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master bit-controller //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_bit_ctrl.v,v 1.11 2004/05/07 11:02:26 rherveille Exp $ +// +// $Date: 2004/05/07 11:02:26 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_bit_ctrl.v,v $ +// Revision 1.11 2004/05/07 11:02:26 rherveille +// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +// +// Revision 1.10 2003/08/09 07:01:33 rherveille +// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +// Fixed a potential bug in the byte controller's host-acknowledge generation. +// +// Revision 1.9 2003/03/10 14:26:37 rherveille +// Fixed cmd_ack generation item (no bug). +// +// Revision 1.8 2003/02/05 00:06:10 rherveille +// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +// +// Revision 1.7 2002/12/26 16:05:12 rherveille +// Small code simplifications +// +// Revision 1.6 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.5 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.4 2002/10/30 18:10:07 rherveille +// Fixed some reported minor start/stop generation timing issuess. +// +// Revision 1.3 2002/06/15 07:37:03 rherveille +// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +// +// Revision 1.2 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + +// +///////////////////////////////////// +// Bit controller section +///////////////////////////////////// +// +// Translate simple commands into SCL/SDA transitions +// Each command has 5 states, A/B/C/D/idle +// +// start: SCL ~~~~~~~~~~\____ +// SDA ~~~~~~~~\______ +// x | A | B | C | D | i +// +// repstart SCL ____/~~~~\___ +// SDA __/~~~\______ +// x | A | B | C | D | i +// +// stop SCL ____/~~~~~~~~ +// SDA ==\____/~~~~~ +// x | A | B | C | D | i +// +//- write SCL ____/~~~~\____ +// SDA ==X=========X= +// x | A | B | C | D | i +// +//- read SCL ____/~~~~\____ +// SDA XXXX=====XXXX +// x | A | B | C | D | i +// + +// Timing: Normal mode Fast mode +/////////////////////////////////////////////////////////////////////// +// Fscl 100KHz 400KHz +// Th_scl 4.0us 0.6us High period of SCL +// Tl_scl 4.7us 1.3us Low period of SCL +// Tsu:sta 4.7us 0.6us setup time for a repeated start condition +// Tsu:sto 4.0us 0.6us setup time for a stop conditon +// Tbuf 4.7us 1.3us Bus free time between a stop and start condition +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_bit_ctrl( + clk, rst, nReset, + clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout, + scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen + ); + + // + // inputs & outputs + // + input clk; + input rst; + input nReset; + input ena; // core enable signal + + input [15:0] clk_cnt; // clock prescale value + + input [3:0] cmd; + output cmd_ack; // command complete acknowledge + reg cmd_ack; + output busy; // i2c bus busy + reg busy; + output al; // i2c bus arbitration lost + reg al; + + input din; + output dout; + reg dout; + + // I2C lines + input scl_i; // i2c clock line input + output scl_o; // i2c clock line output + output scl_oen; // i2c clock line output enable (active low) + reg scl_oen; + input sda_i; // i2c data line input + output sda_o; // i2c data line output + output sda_oen; // i2c data line output enable (active low) + reg sda_oen; + + + // + // variable declarations + // + + reg sSCL, sSDA; // synchronized SCL and SDA inputs + reg dscl_oen; // delayed scl_oen + reg sda_chk; // check SDA output (Multi-master arbitration) + reg clk_en; // clock generation signals + wire slave_wait; +// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation) + reg [15:0] cnt; // clock divider counter (synthesis) + + // state machine variable + reg [16:0] c_state; // synopsys enum_state + + // + // module body + // + + // whenever the slave is not ready it can delay the cycle by pulling SCL low + // delay scl_oen + always @(posedge clk) + dscl_oen <= #1 scl_oen; + + assign slave_wait = dscl_oen && !sSCL; + + + // generate clk enable signal + always @(posedge clk or negedge nReset) + if(~nReset) + begin + cnt <= #1 16'h0; + clk_en <= #1 1'b1; + end + else if (rst) + begin + cnt <= #1 16'h0; + clk_en <= #1 1'b1; + end + else if ( ~|cnt || ~ena) + if (~slave_wait) + begin + cnt <= #1 clk_cnt; + clk_en <= #1 1'b1; + end + else + begin + cnt <= #1 cnt; + clk_en <= #1 1'b0; + end + else + begin + cnt <= #1 cnt - 16'h1; + clk_en <= #1 1'b0; + end + + + // generate bus status controller + reg dSCL, dSDA; + reg sta_condition; + reg sto_condition; + + // synchronize SCL and SDA inputs + // reduce metastability risc + always @(posedge clk or negedge nReset) + if (~nReset) + begin + sSCL <= #1 1'b1; + sSDA <= #1 1'b1; + + dSCL <= #1 1'b1; + dSDA <= #1 1'b1; + end + else if (rst) + begin + sSCL <= #1 1'b1; + sSDA <= #1 1'b1; + + dSCL <= #1 1'b1; + dSDA <= #1 1'b1; + end + else + begin + sSCL <= #1 scl_i; + sSDA <= #1 sda_i; + + dSCL <= #1 sSCL; + dSDA <= #1 sSDA; + end + + // detect start condition => detect falling edge on SDA while SCL is high + // detect stop condition => detect rising edge on SDA while SCL is high + always @(posedge clk or negedge nReset) + if (~nReset) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else if (rst) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else + begin + sta_condition <= #1 ~sSDA & dSDA & sSCL; + sto_condition <= #1 sSDA & ~dSDA & sSCL; + end + + // generate i2c bus busy signal + always @(posedge clk or negedge nReset) + if(!nReset) + busy <= #1 1'b0; + else if (rst) + busy <= #1 1'b0; + else + busy <= #1 (sta_condition | busy) & ~sto_condition; + + // generate arbitration lost signal + // aribitration lost when: + // 1) master drives SDA high, but the i2c bus is low + // 2) stop detected while not requested + reg cmd_stop; + always @(posedge clk or negedge nReset) + if (~nReset) + cmd_stop <= #1 1'b0; + else if (rst) + cmd_stop <= #1 1'b0; + else if (clk_en) + cmd_stop <= #1 cmd == `I2C_CMD_STOP; + + always @(posedge clk or negedge nReset) + if (~nReset) + al <= #1 1'b0; + else if (rst) + al <= #1 1'b0; + else + al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); + + + // generate dout signal (store SDA on rising edge of SCL) + always @(posedge clk) + if(sSCL & ~dSCL) + dout <= #1 sSDA; + + // generate statemachine + + // nxt_state decoder + parameter [16:0] idle = 17'b0_0000_0000_0000_0000; + parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; + parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; + parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; + parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; + parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; + parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; + parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; + parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; + parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; + parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; + parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; + parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; + parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; + parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; + parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; + parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; + parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else if (rst | al) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else + begin + cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle + + if (clk_en) + case (c_state) // synopsys full_case parallel_case + // idle state + idle: + begin + case (cmd) // synopsys full_case parallel_case + `I2C_CMD_START: + c_state <= #1 start_a; + + `I2C_CMD_STOP: + c_state <= #1 stop_a; + + `I2C_CMD_WRITE: + c_state <= #1 wr_a; + + `I2C_CMD_READ: + c_state <= #1 rd_a; + + default: + c_state <= #1 idle; + endcase + + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 sda_oen; // keep SDA in same state + sda_chk <= #1 1'b0; // don't check SDA output + end + + // start + start_a: + begin + c_state <= #1 start_b; + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_b: + begin + c_state <= #1 start_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_c: + begin + c_state <= #1 start_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_d: + begin + c_state <= #1 start_e; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_e: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + // stop + stop_a: + begin + c_state <= #1 stop_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_b: + begin + c_state <= #1 stop_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_c: + begin + c_state <= #1 stop_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + // read + rd_a: + begin + c_state <= #1 rd_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b1; // tri-state SDA + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_b: + begin + c_state <= #1 rd_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_c: + begin + c_state <= #1 rd_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + // write + wr_a: + begin + c_state <= #1 wr_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 din; // set SDA + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + wr_b: + begin + c_state <= #1 wr_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 din; // keep SDA + sda_chk <= #1 1'b1; // check SDA output + end + + wr_c: + begin + c_state <= #1 wr_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 din; + sda_chk <= #1 1'b1; // check SDA output + end + + wr_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 din; + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + endcase + end + + + // assign scl and sda output (always gnd) + assign scl_o = 1'b0; + assign sda_o = 1'b0; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_byte_ctrl.v b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_byte_ctrl.v new file mode 100644 index 000000000..d091d1e36 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_byte_ctrl.v @@ -0,0 +1,344 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master byte-controller //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $ +// +// $Date: 2004/02/18 11:40:46 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_byte_ctrl.v,v $ +// Revision 1.7 2004/02/18 11:40:46 rherveille +// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. +// +// Revision 1.6 2003/08/09 07:01:33 rherveille +// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +// Fixed a potential bug in the byte controller's host-acknowledge generation. +// +// Revision 1.5 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.4 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_byte_ctrl ( + clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, + cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); + + // + // inputs & outputs + // + input clk; // master clock + input rst; // synchronous active high reset + input nReset; // asynchronous active low reset + input ena; // core enable signal + + input [15:0] clk_cnt; // 4x SCL + + // control inputs + input start; + input stop; + input read; + input write; + input ack_in; + input [7:0] din; + + // status outputs + output cmd_ack; + reg cmd_ack; + output ack_out; + reg ack_out; + output i2c_busy; + output i2c_al; + output [7:0] dout; + + // I2C signals + input scl_i; + output scl_o; + output scl_oen; + input sda_i; + output sda_o; + output sda_oen; + + + // + // Variable declarations + // + + // statemachine + parameter [4:0] ST_IDLE = 5'b0_0000; + parameter [4:0] ST_START = 5'b0_0001; + parameter [4:0] ST_READ = 5'b0_0010; + parameter [4:0] ST_WRITE = 5'b0_0100; + parameter [4:0] ST_ACK = 5'b0_1000; + parameter [4:0] ST_STOP = 5'b1_0000; + + // signals for bit_controller + reg [3:0] core_cmd; + reg core_txd; + wire core_ack, core_rxd; + + // signals for shift register + reg [7:0] sr; //8bit shift register + reg shift, ld; + + // signals for state machine + wire go; + reg [2:0] dcnt; + wire cnt_done; + + // + // Module body + // + + // hookup bit_controller + i2c_master_bit_ctrl bit_controller ( + .clk ( clk ), + .rst ( rst ), + .nReset ( nReset ), + .ena ( ena ), + .clk_cnt ( clk_cnt ), + .cmd ( core_cmd ), + .cmd_ack ( core_ack ), + .busy ( i2c_busy ), + .al ( i2c_al ), + .din ( core_txd ), + .dout ( core_rxd ), + .scl_i ( scl_i ), + .scl_o ( scl_o ), + .scl_oen ( scl_oen ), + .sda_i ( sda_i ), + .sda_o ( sda_o ), + .sda_oen ( sda_oen ) + ); + + // generate go-signal + assign go = (read | write | stop) & ~cmd_ack; + + // assign dout output to shift-register + assign dout = sr; + + // generate shift register + always @(posedge clk or negedge nReset) + if (!nReset) + sr <= #1 8'h0; + else if (rst) + sr <= #1 8'h0; + else if (ld) + sr <= #1 din; + else if (shift) + sr <= #1 {sr[6:0], core_rxd}; + + // generate counter + always @(posedge clk or negedge nReset) + if (!nReset) + dcnt <= #1 3'h0; + else if (rst) + dcnt <= #1 3'h0; + else if (ld) + dcnt <= #1 3'h7; + else if (shift) + dcnt <= #1 dcnt - 3'h1; + + assign cnt_done = ~(|dcnt); + + // + // state machine + // + reg [4:0] c_state; // synopsis enum_state + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else if (rst | i2c_al) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else + begin + // initially reset all signals + core_txd <= #1 sr[7]; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + + case (c_state) // synopsys full_case parallel_case + ST_IDLE: + if (go) + begin + if (start) + begin + c_state <= #1 ST_START; + core_cmd <= #1 `I2C_CMD_START; + end + else if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else if (write) + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else // stop + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + + ld <= #1 1'b1; + end + + ST_START: + if (core_ack) + begin + if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + + ld <= #1 1'b1; + end + + ST_WRITE: + if (core_ack) + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; // stay in same state + core_cmd <= #1 `I2C_CMD_WRITE; // write next bit + shift <= #1 1'b1; + end + + ST_READ: + if (core_ack) + begin + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else + begin + c_state <= #1 ST_READ; // stay in same state + core_cmd <= #1 `I2C_CMD_READ; // read next bit + end + + shift <= #1 1'b1; + core_txd <= #1 ack_in; + end + + ST_ACK: + if (core_ack) + begin + if (stop) + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + else + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + // assign ack_out output to bit_controller_rxd (contains last received bit) + ack_out <= #1 core_rxd; + + core_txd <= #1 1'b1; + end + else + core_txd <= #1 ack_in; + + ST_STOP: + if (core_ack) + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + endcase + end +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_defines.v b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_defines.v new file mode 100644 index 000000000..ee3b694fa --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_defines.v @@ -0,0 +1,64 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master controller defines //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $ +// +// $Date: 2001/11/05 11:59:25 $ +// $Revision: 1.3 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_defines.v,v $ +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + + +// I2C registers wishbone addresses + +// bitcontroller states +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 diff --git a/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_top.v b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_top.v new file mode 100644 index 000000000..30689bd70 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/i2c_master_top.v @@ -0,0 +1,301 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE revB.2 compliant I2C Master controller Top-level //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $ +// +// $Date: 2005/02/27 09:26:24 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_top.v,v $ +// Revision 1.11 2005/02/27 09:26:24 rherveille +// Fixed register overwrite issue. +// Removed full_case pragma, replaced it by a default statement. +// +// Revision 1.10 2003/09/01 10:34:38 rherveille +// Fix a blocking vs. non-blocking error in the wb_dat output mux. +// +// Revision 1.9 2003/01/09 16:44:45 rherveille +// Fixed a bug in the Command Register declaration. +// +// Revision 1.8 2002/12/26 16:05:12 rherveille +// Small code simplifications +// +// Revision 1.7 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.6 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.5 2001/11/10 10:52:55 rherveille +// Changed PRER reset value from 0x0000 to 0xffff, conform specs. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_top( + wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, + scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); + + // parameters + parameter ARST_LVL = 1'b0; // asynchronous reset level + + // + // inputs & outputs + // + + // wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input arst_i; // asynchronous reset + input [2:0] wb_adr_i; // lower address bits + input [7:0] wb_dat_i; // databus input + output [7:0] wb_dat_o; // databus output + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + output wb_inta_o; // interrupt request signal output + + reg [7:0] wb_dat_o; + reg wb_ack_o; + reg wb_inta_o; + + // I2C signals + // i2c clock line + input scl_pad_i; // SCL-line input + output scl_pad_o; // SCL-line output (always 1'b0) + output scl_padoen_o; // SCL-line output enable (active low) + + // i2c data line + input sda_pad_i; // SDA-line input + output sda_pad_o; // SDA-line output (always 1'b0) + output sda_padoen_o; // SDA-line output enable (active low) + + + // + // variable declarations + // + + // registers + reg [15:0] prer; // clock prescale register + reg [ 7:0] ctr; // control register + reg [ 7:0] txr; // transmit register + wire [ 7:0] rxr; // receive register + reg [ 7:0] cr; // command register + wire [ 7:0] sr; // status register + + // done signal: command completed, clear command register + wire done; + + // core enable signal + wire core_en; + wire ien; + + // status register signals + wire irxack; + reg rxack; // received aknowledge from slave + reg tip; // transfer in progress + reg irq_flag; // interrupt pending flag + wire i2c_busy; // bus busy (start signal detected) + wire i2c_al; // i2c bus arbitration lost + reg al; // status register arbitration lost bit + + // + // module body + // + + // generate internal reset + wire rst_i = arst_i ^ ARST_LVL; + + // generate wishbone signals + wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i; + + // generate acknowledge output signal + always @(posedge wb_clk_i) + wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored + + // assign DAT_O + always @(posedge wb_clk_i) + begin + case (wb_adr_i) // synopsis parallel_case + 3'b000: wb_dat_o <= #1 prer[ 7:0]; + 3'b001: wb_dat_o <= #1 prer[15:8]; + 3'b010: wb_dat_o <= #1 ctr; + 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr) + 3'b100: wb_dat_o <= #1 sr; // write is command register (cr) + 3'b101: wb_dat_o <= #1 txr; + 3'b110: wb_dat_o <= #1 cr; + 3'b111: wb_dat_o <= #1 0; // reserved + endcase + end + + // generate registers + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else if (wb_rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else + if (wb_wacc) + case (wb_adr_i) // synopsis parallel_case + 3'b000 : prer [ 7:0] <= #1 wb_dat_i; + 3'b001 : prer [15:8] <= #1 wb_dat_i; + 3'b010 : ctr <= #1 wb_dat_i; + 3'b011 : txr <= #1 wb_dat_i; + default: ; + endcase + + // generate command register (special case) + always @(posedge wb_clk_i or negedge rst_i) + if (~rst_i) + cr <= #1 8'h0; + else if (wb_rst_i) + cr <= #1 8'h0; + else if (wb_wacc) + begin + if (core_en & (wb_adr_i == 3'b100) ) + cr <= #1 wb_dat_i; + end + else + begin + if (done | i2c_al) + cr[7:4] <= #1 4'h0; // clear command bits when done + // or when aribitration lost + cr[2:1] <= #1 2'b0; // reserved bits + cr[0] <= #1 2'b0; // clear IRQ_ACK bit + end + + + // decode command register + wire sta = cr[7]; + wire sto = cr[6]; + wire rd = cr[5]; + wire wr = cr[4]; + wire ack = cr[3]; + wire iack = cr[0]; + + // decode control register + assign core_en = ctr[7]; + assign ien = ctr[6]; + + // hookup byte controller block + i2c_master_byte_ctrl byte_controller ( + .clk ( wb_clk_i ), + .rst ( wb_rst_i ), + .nReset ( rst_i ), + .ena ( core_en ), + .clk_cnt ( prer ), + .start ( sta ), + .stop ( sto ), + .read ( rd ), + .write ( wr ), + .ack_in ( ack ), + .din ( txr ), + .cmd_ack ( done ), + .ack_out ( irxack ), + .dout ( rxr ), + .i2c_busy ( i2c_busy ), + .i2c_al ( i2c_al ), + .scl_i ( scl_pad_i ), + .scl_o ( scl_pad_o ), + .scl_oen ( scl_padoen_o ), + .sda_i ( sda_pad_i ), + .sda_o ( sda_pad_o ), + .sda_oen ( sda_padoen_o ) + ); + + // status register block + interrupt request signal + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else if (wb_rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else + begin + al <= #1 i2c_al | (al & ~sta); + rxack <= #1 irxack; + tip <= #1 (rd | wr); + irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated + end + + // generate interrupt request signals + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + wb_inta_o <= #1 1'b0; + else if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set) + + // assign status register bits + assign sr[7] = rxack; + assign sr[6] = i2c_busy; + assign sr[5] = al; + assign sr[4:2] = 3'h0; // reserved + assign sr[1] = tip; + assign sr[0] = irq_flag; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/i2c/rtl/timescale.v b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/timescale.v new file mode 100644 index 000000000..60d4ecbd1 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/i2c/rtl/timescale.v @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_adr_sel.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_adr_sel.v new file mode 100644 index 000000000..0408fa86f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_adr_sel.v @@ -0,0 +1,290 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Address Select Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_adr_sel.v,v 1.4 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_adr_sel.v,v $ +// Revision 1.4 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.3 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.2 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.1.1.1 2001/05/13 09:39:40 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i, + wb_write_go, wr_hold, cas_, + mc_addr, row_adr, bank_adr, rfr_ack, + cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle, + page_size); + +input clk; +input [31:0] csc; +input [31:0] tms; +input wb_ack_o, wb_stb_i; +input [31:0] wb_addr_i; +input wb_we_i; +input wb_write_go; +input wr_hold; +input cas_; +output [23:0] mc_addr; +output [12:0] row_adr; +output [1:0] bank_adr; +input rfr_ack; +input cs_le; +input cmd_a10; +input row_sel; +input lmr_sel; +input next_adr; +input wr_cycle; +output [10:0] page_size; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [23:0] mc_addr_d; +reg [23:0] acs_addr; +wire [23:0] acs_addr_pl1; +reg [23:0] sram_addr; +wire [14:0] sdram_adr; +reg [12:0] row_adr; +reg [9:0] col_adr; +reg [1:0] bank_adr; +reg [10:0] page_size; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire [1:0] mem_size; +wire bas; + +// Aliases +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign mem_size = csc[7:6]; +assign bas = csc[9]; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i) + if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr}; + else + if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr; + else + if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr; + else mc_addr_d = wb_addr_i[25:2]; + +assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d; + +//////////////////////////////////////////////////////////////////// +// +// Async Devices Address Latch & Counter +// + +mc_incn_r #(24) u0( .clk( clk ), + .inc_in( acs_addr ), + .inc_out( acs_addr_pl1 ) ); + +always @(posedge clk) + if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2]; + +always @(posedge clk) + if(cs_le | wb_we_i) + case(bus_width) // synopsys full_case parallel_case + `MC_BW_8: acs_addr <= #1 wb_addr_i[23:0]; + `MC_BW_16: acs_addr <= #1 wb_addr_i[24:1]; + `MC_BW_32: acs_addr <= #1 wb_addr_i[25:2]; + endcase + else + if(next_adr) acs_addr <= #1 acs_addr_pl1; + +//////////////////////////////////////////////////////////////////// +// +// SDRAM Address Mux +// + +assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] : + row_sel ? row_adr : + {2'h0, cmd_a10, col_adr}; + +assign sdram_adr[14:13] = bank_adr; + +always @(posedge clk) + if(wr_cycle ? wb_ack_o : wb_stb_i) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2]; + {`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]}; + + {`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]}; + endcase + +always @(posedge clk) + if(cs_le) + begin + if(!bas) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]}; + {`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12]; + endcase + else + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]}; + {`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]}; + {`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]}; + {`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]}; + {`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]}; + {`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]}; + {`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10]; + endcase + end + + +always @(posedge clk) + if(cs_le) + begin + if(!bas) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11]; + {`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12]; + {`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11]; + {`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10]; + {`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10]; + endcase + else + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23]; + {`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24]; + {`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25]; + + {`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22]; + {`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23]; + {`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24]; + + {`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21]; + {`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22]; + {`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23]; + endcase + end + +always @(bus_width or mem_size) + casex({bus_width, mem_size}) // synopsys full_case parallel_case + {`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512; + {`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024; + {`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024; + + {`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256; + {`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512; + {`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512; + + {`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256; + {`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256; + {`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256; + endcase + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v new file mode 100644 index 000000000..04c7ce7c8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_cs_rf.v @@ -0,0 +1,276 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Chip Select Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_cs_rf.v,v 1.6 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_cs_rf.v,v $ +// Revision 1.6 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:42 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs, + wp_err, lmr_req, lmr_ack, init_req, init_ack ); + +input clk, rst; +input wb_we_i; +input [31:0] din; +input rf_we; +input [31:0] addr; + +output [31:0] csc; +output [31:0] tms; +input [31:0] poc; +input [31:0] csc_mask; +output cs; +output wp_err; + +output lmr_req; +input lmr_ack; +output init_req; +input init_ack; + +parameter [2:0] this_cs = 0; +parameter [3:0] reg_select = this_cs + 2; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [31:0] csc; +reg [31:0] tms; +wire sel; +wire cs_d; +wire wp; +reg inited; +reg init_req; +reg init_req_we; +reg lmr_req; +reg lmr_req_we; + +//////////////////////////////////////////////////////////////////// +// +// A kludge for cases where there is no clock during reset ... +// + +reg rst_r1, rst_r2; + +always @(posedge clk or posedge rst) + if(rst) rst_r1 <= #1 1'b1; + else rst_r1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rst_r2 <= #1 1'b1; + else rst_r2 <= #1 rst_r1; + +//////////////////////////////////////////////////////////////////// +// +// Write Logic +// + +reg [6:0] addr_r; + +always @(posedge clk) + addr_r <= #1 addr[6:0]; + +assign sel = addr_r[6:3] == reg_select[3:0]; + +always @(posedge clk) + if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? + {26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0; + else + if(rf_we & sel & !addr_r[2]) csc <= #1 din; + +always @(posedge clk) + if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? + `MC_DEF_POR_TMS : 32'h0; + else + if(rf_we & sel & addr_r[2]) tms <= #1 din; + +//////////////////////////////////////////////////////////////////// +// +// Load Mode Register Request/Ack Logic +// +always @(posedge clk or posedge rst) + if(rst) lmr_req_we <= #1 1'b0; + else lmr_req_we <= #1 rf_we & sel & addr_r[2]; + +always @(posedge clk or posedge rst) + if(rst) lmr_req <= #1 1'b0; + else + if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM)) + lmr_req <= #1 inited; + else + if(lmr_ack) lmr_req <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Initialize SDRAM Request/Ack & tracking logic +// +always @(posedge clk or posedge rst) + if(rst) init_req_we <= #1 1'b0; + else init_req_we <= #1 rf_we & sel & !addr_r[2]; + +always @(posedge clk or posedge rst) + if(rst) init_req <= #1 1'b0; + else + if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited) + init_req <= #1 1'b1; + else + if(init_ack) init_req <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) inited <= #1 1'b0; + else + if(init_ack) inited <= #1 1'b1; + +//////////////////////////////////////////////////////////////////// +// +// Chip Select Generation Logic +// + +assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0]; + +assign wp = wb_we_i & csc[8]; + +assign wp_err = cs_d & wp; +assign cs = cs_d & !wp; + +endmodule + + + +// This dummy is used to terminate the outputs for non existing Chip Selects +module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs, + wp_err, lmr_req, lmr_ack, init_req, init_ack ); + +parameter [2:0] this_cs = 0; + +input clk, rst; +input wb_we_i; +input [31:0] din; +input rf_we; +input [31:0] addr; + +output [31:0] csc; +output [31:0] tms; +input [31:0] poc; +input [31:0] csc_mask; +output cs; +output wp_err; + +output lmr_req; +input lmr_ack; +output init_req; +input init_ack; + +assign csc = 32'h0; +assign tms = 32'h0; +assign cs = 1'b0; +assign wp_err = 1'b0; +assign lmr_req = 1'b0; +assign init_req = 1'b0; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_defines.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_defines.v new file mode 100644 index 000000000..62a1c6900 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_defines.v @@ -0,0 +1,232 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_defines.v,v 1.7 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_defines.v,v $ +// Revision 1.7 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.6 2001/12/12 06:35:15 rudi +// *** empty log message *** +// +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/10 13:44:17 rudi +// *** empty log message *** +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug +// fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:38 rudi +// Created Directory Structure +// +// +// +// + +`timescale 1ns / 10ps + +///////////////////////////////////////////////////////////////////// +// +// This define selects how the WISHBONE interface determines if +// the internal register file is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011) + +// This define selects how the WISHBONE interface determines if +// the memory is selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +`define MC_MEM_SEL (wb_addr_i[31:29] == 3'h0) + +///////////////////////////////////////////////////////////////////// +// +// This are the default Power-On Reset values for Chip Select +// + +// This will be defined by the run script for my test bench ... +// Alternatively force here for synthesis ... +//`define RUDIS_TB 1 + +// Defines which chip select is used for Power On booting + +// To run my default testbench default boot CS must be 3 !!! +`ifdef RUDIS_TB +`define MC_DEF_SEL 3'h3 +`else +`define MC_DEF_SEL 3'h0 +`endif + +// Defines the default (reset) TMS value for the DEF_SEL chip select +`define MC_DEF_POR_TMS 32'hffff_ffff + + +///////////////////////////////////////////////////////////////////// +// +// Define how many Chip Selects to Implement +// +`define MC_HAVE_CS1 1 +//`define MC_HAVE_CS2 1 +//`define MC_HAVE_CS3 1 +//`define MC_HAVE_CS4 1 +//`define MC_HAVE_CS5 1 +//`define MC_HAVE_CS6 1 +//`define MC_HAVE_CS7 1 + + +// To run my default testbench those need to there !!! +`ifdef RUDIS_TB +`define MC_HAVE_CS2 1 +`define MC_HAVE_CS3 1 +`define MC_HAVE_CS4 1 +`define MC_HAVE_CS5 1 +`endif + +///////////////////////////////////////////////////////////////////// +// +// Init Refresh +// +// Number of Refresh Cycles to perform during SDRAM initialization. +// This varies between SDRAM manufacturer. Typically this value is +// between 2 and 8. This number must be smaller than 16. +`define MC_INIT_RFRC_CNT 2 + +///////////////////////////////////////////////////////////////////// +// +// Power On Delay +// +// Most if SDRAMs require some time to initialize before they can be used +// after power on. If the Memory Controller shall stall after power on to +// allow SDRAMs to finish the initialization process uncomment the below +// define statement +`define MC_POR_DELAY 1 + +// This value defines how many MEM_CLK cycles the Memory Controller should +// stall. Default is 2.5uS. At a 10nS MEM_CLK cycle time, this would 250 +// cycles. +`define MC_POR_DELAY_VAL 8'd250 + + +// =============================================================== +// =============================================================== +// Various internal defines (DO NOT MODIFY !) +// =============================================================== +// =============================================================== + +// Register settings encodings +`define MC_BW_8 2'h0 +`define MC_BW_16 2'h1 +`define MC_BW_32 2'h2 + +`define MC_MEM_TYPE_SDRAM 3'h0 +`define MC_MEM_TYPE_SRAM 3'h1 +`define MC_MEM_TYPE_ACS 3'h2 +`define MC_MEM_TYPE_SCS 3'h3 + +`define MC_MEM_SIZE_64 2'h0 +`define MC_MEM_SIZE_128 2'h1 +`define MC_MEM_SIZE_256 2'h2 + +// Command Valid, Ras_, Cas_, We_ +`define MC_CMD_NOP 4'b0111 +`define MC_CMD_PC 4'b1010 +`define MC_CMD_ACT 4'b1011 +`define MC_CMD_WR 4'b1100 +`define MC_CMD_RD 4'b1101 +`define MC_CMD_BT 4'b1110 +`define MC_CMD_ARFR 4'b1001 +`define MC_CMD_LMR 4'b1000 +`define MC_CMD_XRD 4'b1111 +`define MC_CMD_XWR 4'b1110 + +`define MC_SINGLE_BANK 1'b0 +`define MC_ALL_BANKS 1'b1 + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_dp.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_dp.v new file mode 100644 index 000000000..f172db514 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_dp.v @@ -0,0 +1,244 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Data Path Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_dp.v,v 1.6 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_dp.v,v $ +// Revision 1.6 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_dp( clk, rst, csc, + wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o, + wb_read_go, wb_we_i, + mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o, + + dv, pack_le0, pack_le1, pack_le2, + byte_en, par_err + ); + +input clk, rst; +input [31:0] csc; + +input wb_cyc_i; +input wb_stb_i; +input mem_ack; +input wb_ack_o; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input wb_read_go; +input wb_we_i; + +input mc_clk; +input [35:0] mc_data_del; +input [3:0] mc_dp_i; +output [31:0] mc_data_o; +output [3:0] mc_dp_o; + +input dv; +input pack_le0, pack_le1, pack_le2; // Pack Latch Enable +input [3:0] byte_en; // High Active byte enables +output par_err; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [31:0] wb_data_o; +reg [31:0] mc_data_o; +wire [35:0] rd_fifo_out; +wire rd_fifo_clr; +reg [3:0] mc_dp_o; +reg par_err_r; + +reg [7:0] byte0, byte1, byte2; +reg [31:0] mc_data_d; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire pen; +wire re; + +// Aliases +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign pen = csc[11]; + +//////////////////////////////////////////////////////////////////// +// +// WB READ Data Path +// + +always @(mem_type or rd_fifo_out or mc_data_d) + if( (mem_type == `MC_MEM_TYPE_SDRAM) | + (mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0]; + else wb_data_o = mc_data_d; + +//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) ); +assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i); +assign re = wb_ack_o & wb_read_go; + +mc_rd_fifo u0( + .clk( clk ), + .rst( rst ), + .clr( rd_fifo_clr ), + .din( mc_data_del ), + .we( dv ), + .dout( rd_fifo_out ), + .re( re ) + ); + +//////////////////////////////////////////////////////////////////// +// +// WB WRITE Data Path +// + +always @(posedge clk) + if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) ) + mc_data_o <= #1 wb_data_i; + +//////////////////////////////////////////////////////////////////// +// +// Read Data Packing +// + +always @(posedge clk) + if(pack_le0) byte0 <= #1 mc_data_del[7:0]; + +always @(posedge clk) + if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0]; + else + if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8]; + +always @(posedge clk) + if(pack_le2) byte2 <= #1 mc_data_del[7:0]; + +always @(bus_width or mc_data_del or byte0 or byte1 or byte2) + if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0}; + else + if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0}; + else mc_data_d = mc_data_del[31:0]; + +//////////////////////////////////////////////////////////////////// +// +// Parity Generation +// + +always @(posedge clk) + if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) ) + mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16], + ^wb_data_i[15:08], ^wb_data_i[07:00] }; + +//////////////////////////////////////////////////////////////////// +// +// Parity Checking +// + +assign par_err = !wb_we_i & mem_ack & pen & ( + (( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) | + (( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) | + (( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) | + (( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] ) + ); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_incn_r.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_incn_r.v new file mode 100644 index 000000000..a058b0188 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_incn_r.v @@ -0,0 +1,102 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Parametarized, Pipelined Incrementer //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_incn_r.v,v 1.2 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_incn_r.v,v $ +// Revision 1.2 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1 2001/06/12 15:18:47 rudi +// +// +// This is a pipelined primitive incrementor. +// +// +// +// +// + +`include "mc_defines.v" + +// +// USAGE: incN_r #() uN(clk, input, output); +// +module mc_incn_r(clk, inc_in, inc_out); + +parameter incN_width = 32; + +input clk; +input [incN_width-1:0] inc_in; +output [incN_width-1:0] inc_out; + +parameter incN_center = incN_width / 2; + +reg [incN_center:0] out_r; +wire [31:0] tmp_zeros = 32'h0; +wire [incN_center-1:0] inc_next; + +always @(posedge clk) + out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1}; + +assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next; + +assign inc_next = out_r[incN_center] ? + {tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0]; + +assign inc_out[incN_center-1:0] = out_r; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_mem_if.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_mem_if.v new file mode 100644 index 000000000..1bb40ec41 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_mem_if.v @@ -0,0 +1,362 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Memory Bus Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_mem_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_mem_if.v,v $ +// Revision 1.6 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.5 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/14 01:57:37 rudi +// +// +// Fixed a potential bug in a corner case situation where the TMS register +// does not propegate properly during initialisation. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:48 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg, + mc_addr, mc_data_o, mc_dp_o, mc_data_oe, + mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_, + mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d, + mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r, + we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack, + cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel, + suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle, + wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i, + mc_zz_o + ); +// Memory Interface +input clk; +input rst; +input mc_clk; +input mc_br; +output mc_bg; +output [23:0] mc_addr; +output [31:0] mc_data_o; +output [3:0] mc_dp_o; +output mc_data_oe; +output [3:0] mc_dqm; +output mc_oe_; +output mc_we_; +output mc_cas_; +output mc_ras_; +output mc_cke_; +output [7:0] mc_cs_; +output mc_adsc_; +output mc_adv_; +input mc_ack; +output mc_rp; +output mc_c_oe; +output [35:0] mc_data_ir; +output mc_sts_ir; +output mc_zz_o; + +// Internal Interface +output mc_br_r; +input mc_bg_d; +input data_oe; +input susp_sel; +input suspended_o; +input [31:0] mc_data_od; +input [3:0] mc_dp_od; +input [23:0] mc_addr_d; +output mc_ack_r; +input wb_cyc_i; +input wb_stb_i; +input [3:0] wb_sel_i; +input wb_cycle; +input wr_cycle; +input oe_ ; +input we_; +input ras_; +input cas_; +input cke_; +input cs_en; +input rfr_ack; +input [7:0] cs_need_rfr; +input lmr_sel; +input [7:0] spec_req_cs; +input [7:0] cs; +input fs; +input mc_adsc_d; +input mc_adv_d; +input mc_c_oe_d; +input [31:0] mc_data_i; +input [3:0] mc_dp_i; +input mc_sts_i; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg mc_data_oe; +reg [31:0] mc_data_o; +reg [3:0] mc_dp_o; +reg [3:0] mc_dqm; +reg [3:0] mc_dqm_r; +reg [23:0] mc_addr; +reg mc_oe_; +reg mc_we_; +reg mc_cas_; +reg mc_ras_; +wire mc_cke_; +reg [7:0] mc_cs_; +reg mc_bg; +reg mc_adsc_; +reg mc_adv_; +reg mc_br_r; +reg mc_ack_r; +reg mc_rp; +reg mc_c_oe; +reg mc_zz_o; + +reg [35:0] mc_data_ir; +reg mc_sts_ir; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge mc_clk) + mc_zz_o <= #1 suspended_o; + +always @(posedge mc_clk) + mc_sts_ir <= #1 mc_sts_i; + +always @(posedge mc_clk) + mc_data_ir <= #1 {mc_dp_i, mc_data_i}; + +always @(posedge mc_clk) + mc_c_oe <= #1 mc_c_oe_d; + +always @(posedge mc_clk) + mc_rp <= #1 !suspended_o & !fs; + +always @(posedge mc_clk) + mc_br_r <= #1 mc_br; + +always @(posedge mc_clk) + mc_ack_r <= #1 mc_ack; + +always @(posedge mc_clk) + mc_bg <= #1 mc_bg_d; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_data_oe <= #1 1'b0; + else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d; + +always @(posedge mc_clk) + mc_data_o <= #1 mc_data_od; + +always @(posedge mc_clk) + mc_dp_o <= #1 mc_dp_od; + +always @(posedge mc_clk) + mc_addr <= #1 mc_addr_d; + +always @(posedge clk) + if(wb_cyc_i & wb_stb_i) + mc_dqm_r <= #1 wb_sel_i; + +reg [3:0] mc_dqm_r2; +always @(posedge clk) + mc_dqm_r2 <= #1 mc_dqm_r; + +always @(posedge mc_clk) + mc_dqm <= #1 susp_sel ? 4'hf : + data_oe ? ~mc_dqm_r2 : + (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_oe_ <= #1 1'b1; + else mc_oe_ <= #1 oe_ | susp_sel; + +always @(posedge mc_clk) + mc_we_ <= #1 we_; + +always @(posedge mc_clk) + mc_cas_ <= #1 cas_; + +always @(posedge mc_clk) + mc_ras_ <= #1 ras_; + +assign mc_cke_ = cke_; + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[0] <= #1 1'b1; + else + mc_cs_[0] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[0] : + lmr_sel ? spec_req_cs[0] : + cs[0] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[1] <= #1 1'b1; + else + mc_cs_[1] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[1] : + lmr_sel ? spec_req_cs[1] : + cs[1] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[2] <= #1 1'b1; + else + mc_cs_[2] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[2] : + lmr_sel ? spec_req_cs[2] : + cs[2] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[3] <= #1 1'b1; + else + mc_cs_[3] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[3] : + lmr_sel ? spec_req_cs[3] : + cs[3] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[4] <= #1 1'b1; + else + mc_cs_[4] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[4] : + lmr_sel ? spec_req_cs[4] : + cs[4] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[5] <= #1 1'b1; + else + mc_cs_[5] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[5] : + lmr_sel ? spec_req_cs[5] : + cs[5] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[6] <= #1 1'b1; + else + mc_cs_[6] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[6] : + lmr_sel ? spec_req_cs[6] : + cs[6] + )); + +always @(posedge mc_clk or posedge rst) + if(rst) mc_cs_[7] <= #1 1'b1; + else + mc_cs_[7] <= #1 ~(cs_en & ( + (rfr_ack | susp_sel) ? cs_need_rfr[7] : + lmr_sel ? spec_req_cs[7] : + cs[7] + )); + +always @(posedge mc_clk) + mc_adsc_ <= #1 ~mc_adsc_d; + +always @(posedge mc_clk) + mc_adv_ <= #1 ~mc_adv_d; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct.v new file mode 100644 index 000000000..5890d7fb3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct.v @@ -0,0 +1,236 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Open Bank & Row Tracking Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_obct.v,v 1.4 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_obct.v,v $ +// Revision 1.4 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.3 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.2 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:45 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same); +input clk, rst; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg bank0_open, bank1_open, bank2_open, bank3_open; +reg bank_open; +reg [12:0] b0_last_row; +reg [12:0] b1_last_row; +reg [12:0] b2_last_row; +reg [12:0] b3_last_row; +wire row0_same, row1_same, row2_same, row3_same; +reg row_same; + +//////////////////////////////////////////////////////////////////// +// +// Bank Open/Closed Tracking +// + +always @(posedge clk or posedge rst) + if(rst) bank0_open <= #1 1'b0; + else + if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1; + else + if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0; + else + if(bank_clr_all) bank0_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank1_open <= #1 1'b0; + else + if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1; + else + if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0; + else + if(bank_clr_all) bank1_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank2_open <= #1 1'b0; + else + if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1; + else + if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0; + else + if(bank_clr_all) bank2_open <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) bank3_open <= #1 1'b0; + else + if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1; + else + if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0; + else + if(bank_clr_all) bank3_open <= #1 1'b0; + +always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open) + case(bank_adr) // synopsys full_case parallel_case + 2'h0: bank_open = bank0_open; + 2'h1: bank_open = bank1_open; + 2'h2: bank_open = bank2_open; + 2'h3: bank_open = bank3_open; + endcase + +assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open; + +//////////////////////////////////////////////////////////////////// +// +// Raw Address Tracking +// + +always @(posedge clk) + if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr; + +always @(posedge clk) + if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr; + +//////////////////////////////////////////////////////////////////// +// +// Raw address checking +// + +assign row0_same = (b0_last_row == row_adr); +assign row1_same = (b1_last_row == row_adr); +assign row2_same = (b2_last_row == row_adr); +assign row3_same = (b3_last_row == row_adr); + +always @(bank_adr or row0_same or row1_same or row2_same or row3_same) + case(bank_adr) // synopsys full_case parallel_case + 2'h0: row_same = row0_same; + 2'h1: row_same = row1_same; + 2'h2: row_same = row2_same; + 2'h3: row_same = row3_same; + endcase + +endmodule + + +// This is used for unused Chip Selects +module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same); +input clk, rst; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; + +assign bank_open = 1'b0; +assign any_bank_open = 1'b0; +assign row_same = 1'b0; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct_top.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct_top.v new file mode 100644 index 000000000..26d230190 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_obct_top.v @@ -0,0 +1,426 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Open Bank & Row Tracking Block Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_obct_top.v,v 1.4 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_obct_top.v,v $ +// Revision 1.4 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.3 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all, + bank_open, any_bank_open, row_same, rfr_ack); +input clk, rst; +input [7:0] cs; +input [12:0] row_adr; +input [1:0] bank_adr; +input bank_set; +input bank_clr; +input bank_clr_all; +output bank_open; +output any_bank_open; +output row_same; +input rfr_ack; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg bank_open; +reg row_same; +reg any_bank_open; + +wire bank_set_0; +wire bank_clr_0; +wire bank_clr_all_0; +wire bank_open_0; +wire row_same_0; +wire any_bank_open_0; + +wire bank_set_1; +wire bank_clr_1; +wire bank_clr_all_1; +wire bank_open_1; +wire row_same_1; +wire any_bank_open_1; + +wire bank_set_2; +wire bank_clr_2; +wire bank_clr_all_2; +wire bank_open_2; +wire row_same_2; +wire any_bank_open_2; + +wire bank_set_3; +wire bank_clr_3; +wire bank_clr_all_3; +wire bank_open_3; +wire row_same_3; +wire any_bank_open_3; + +wire bank_set_4; +wire bank_clr_4; +wire bank_clr_all_4; +wire bank_open_4; +wire row_same_4; +wire any_bank_open_4; + +wire bank_set_5; +wire bank_clr_5; +wire bank_clr_all_5; +wire bank_open_5; +wire row_same_5; +wire any_bank_open_5; + +wire bank_set_6; +wire bank_clr_6; +wire bank_clr_all_6; +wire bank_open_6; +wire row_same_6; +wire any_bank_open_6; + +wire bank_set_7; +wire bank_clr_7; +wire bank_clr_all_7; +wire bank_open_7; +wire row_same_7; +wire any_bank_open_7; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign bank_set_0 = cs[0] & bank_set; +assign bank_set_1 = cs[1] & bank_set; +assign bank_set_2 = cs[2] & bank_set; +assign bank_set_3 = cs[3] & bank_set; +assign bank_set_4 = cs[4] & bank_set; +assign bank_set_5 = cs[5] & bank_set; +assign bank_set_6 = cs[6] & bank_set; +assign bank_set_7 = cs[7] & bank_set; + +assign bank_clr_0 = cs[0] & bank_clr; +assign bank_clr_1 = cs[1] & bank_clr; +assign bank_clr_2 = cs[2] & bank_clr; +assign bank_clr_3 = cs[3] & bank_clr; +assign bank_clr_4 = cs[4] & bank_clr; +assign bank_clr_5 = cs[5] & bank_clr; +assign bank_clr_6 = cs[6] & bank_clr; +assign bank_clr_7 = cs[7] & bank_clr; + +assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack; +assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack; +assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack; +assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack; +assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack; +assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack; +assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack; +assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack; + +always @(posedge clk) + bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) | + (cs[2] & bank_open_2) | (cs[3] & bank_open_3) | + (cs[4] & bank_open_4) | (cs[5] & bank_open_5) | + (cs[6] & bank_open_6) | (cs[7] & bank_open_7); + +always @(posedge clk) + row_same <= #1 (cs[0] & row_same_0) | (cs[1] & row_same_1) | + (cs[2] & row_same_2) | (cs[3] & row_same_3) | + (cs[4] & row_same_4) | (cs[5] & row_same_5) | + (cs[6] & row_same_6) | (cs[7] & row_same_7); + +always @(posedge clk) + any_bank_open <= #1 (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) | + (cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) | + (cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) | + (cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7); + + +//////////////////////////////////////////////////////////////////// +// +// OBCT Modules for each Chip Select +// + +mc_obct u0( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_0 ), + .bank_clr( bank_clr_0 ), + .bank_clr_all( bank_clr_all_0 ), + .bank_open( bank_open_0 ), + .any_bank_open( any_bank_open_0 ), + .row_same( row_same_0 ) + ); + +`ifdef MC_HAVE_CS1 +mc_obct u1( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_1 ), + .bank_clr( bank_clr_1 ), + .bank_clr_all( bank_clr_all_1 ), + .bank_open( bank_open_1 ), + .any_bank_open( any_bank_open_1 ), + .row_same( row_same_1 ) + ); +`else +mc_obct_dummy u1( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_1 ), + .bank_clr( bank_clr_1 ), + .bank_clr_all( bank_clr_all_1 ), + .bank_open( bank_open_1 ), + .any_bank_open( any_bank_open_1 ), + .row_same( row_same_1 ) + ); +`endif + +`ifdef MC_HAVE_CS2 +mc_obct u2( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_2 ), + .bank_clr( bank_clr_2 ), + .bank_clr_all( bank_clr_all_2 ), + .bank_open( bank_open_2 ), + .any_bank_open( any_bank_open_2 ), + .row_same( row_same_2 ) + ); +`else +mc_obct_dummy u2( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_2 ), + .bank_clr( bank_clr_2 ), + .bank_clr_all( bank_clr_all_2 ), + .bank_open( bank_open_2 ), + .any_bank_open( any_bank_open_2 ), + .row_same( row_same_2 ) + ); +`endif + +`ifdef MC_HAVE_CS3 +mc_obct u3( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_3 ), + .bank_clr( bank_clr_3 ), + .bank_clr_all( bank_clr_all_3 ), + .bank_open( bank_open_3 ), + .any_bank_open( any_bank_open_3 ), + .row_same( row_same_3 ) + ); +`else +mc_obct_dummy u3( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_3 ), + .bank_clr( bank_clr_3 ), + .bank_clr_all( bank_clr_all_3 ), + .bank_open( bank_open_3 ), + .any_bank_open( any_bank_open_3 ), + .row_same( row_same_3 ) + ); +`endif + +`ifdef MC_HAVE_CS4 +mc_obct u4( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_4 ), + .bank_clr( bank_clr_4 ), + .bank_clr_all( bank_clr_all_4 ), + .bank_open( bank_open_4 ), + .any_bank_open( any_bank_open_4 ), + .row_same( row_same_4 ) + ); +`else +mc_obct_dummy u4( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_4 ), + .bank_clr( bank_clr_4 ), + .bank_clr_all( bank_clr_all_4 ), + .bank_open( bank_open_4 ), + .any_bank_open( any_bank_open_4 ), + .row_same( row_same_4 ) + ); +`endif + +`ifdef MC_HAVE_CS5 +mc_obct u5( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_5 ), + .bank_clr( bank_clr_5 ), + .bank_clr_all( bank_clr_all_5 ), + .bank_open( bank_open_5 ), + .any_bank_open( any_bank_open_5 ), + .row_same( row_same_5 ) + ); +`else +mc_obct_dummy u5( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_5 ), + .bank_clr( bank_clr_5 ), + .bank_clr_all( bank_clr_all_5 ), + .bank_open( bank_open_5 ), + .any_bank_open( any_bank_open_5 ), + .row_same( row_same_5 ) + ); +`endif + +`ifdef MC_HAVE_CS6 +mc_obct u6( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_6 ), + .bank_clr( bank_clr_6 ), + .bank_clr_all( bank_clr_all_6 ), + .bank_open( bank_open_6 ), + .any_bank_open( any_bank_open_6 ), + .row_same( row_same_6 ) + ); +`else +mc_obct_dummy u6( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_6 ), + .bank_clr( bank_clr_6 ), + .bank_clr_all( bank_clr_all_6 ), + .bank_open( bank_open_6 ), + .any_bank_open( any_bank_open_6 ), + .row_same( row_same_6 ) + ); +`endif + +`ifdef MC_HAVE_CS7 +mc_obct u7( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_7 ), + .bank_clr( bank_clr_7 ), + .bank_clr_all( bank_clr_all_7 ), + .bank_open( bank_open_7 ), + .any_bank_open( any_bank_open_7 ), + .row_same( row_same_7 ) + ); +`else +mc_obct_dummy u7( + .clk( clk ), + .rst( rst ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set_7 ), + .bank_clr( bank_clr_7 ), + .bank_clr_all( bank_clr_all_7 ), + .bank_open( bank_open_7 ), + .any_bank_open( any_bank_open_7 ), + .row_same( row_same_7 ) + ); +`endif + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rd_fifo.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rd_fifo.v new file mode 100644 index 000000000..55de0c0f4 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rd_fifo.v @@ -0,0 +1,130 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Read FIFO //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_rd_fifo.v,v 1.4 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_rd_fifo.v,v $ +// Revision 1.4 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.3 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.2 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.1.1.1 2001/05/13 09:39:44 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_rd_fifo(clk, rst, clr, din, we, dout, re); + +input clk, rst, clr; +input [35:0] din; +input we; +output [35:0] dout; +input re; + +reg [3:0] rd_adr, wr_adr; +reg [35:0] r0, r1, r2, r3; +reg [35:0] dout; + +always @(posedge clk or posedge rst) + if(rst) rd_adr <= #1 4'h1; + else + if(clr) rd_adr <= #1 4'h1; + else + if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]}; + +always @(posedge clk or posedge rst) + if(rst) wr_adr <= #1 4'h1; + else + if(clr) wr_adr <= #1 4'h1; + else + if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]}; + +always @(posedge clk) + if(we & wr_adr[0]) r0 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[1]) r1 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[2]) r2 <= #1 din; + +always @(posedge clk) + if(we & wr_adr[3]) r3 <= #1 din; + +always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din) + case(rd_adr) // synopsys full_case parallel_case + 4'h1: dout = r0; + 4'h2: dout = r1; + 4'h4: dout = r2; + 4'h8: dout = r3; + endcase + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_refresh.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_refresh.v new file mode 100644 index 000000000..b824fa4f7 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_refresh.v @@ -0,0 +1,210 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// Refresh Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_refresh.v,v 1.4 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_refresh.v,v $ +// Revision 1.4 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.3 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.2 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_refresh(clk, rst, + cs_need_rfr, ref_int, rfr_req, rfr_ack, + rfr_ps_val + ); + +input clk, rst; +input [7:0] cs_need_rfr; +input [2:0] ref_int; +output rfr_req; +input rfr_ack; +input [7:0] rfr_ps_val; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg rfr_en; +reg [7:0] ps_cnt; +wire ps_cnt_clr; +reg rfr_ce; +reg [7:0] rfr_cnt; +reg rfr_clr; +reg rfr_req; +reg rfr_early; + +/* +Refresh generation + +The prescaler generates a 0.48828 uS clock enable + +The refresh counter generates the following refresh rates: +(Actual values are about 0.63% below the desired values). +This is for a 200 Mhz WISHBONE Bus. +0.970 uS, +1.940 +3.880 +7.760 +15.520 +32.040 +62.080 +124.160 uS + +(desired values) +0.976 uS +1.953 +3.906 +7.812 +15.625 +31.250 +62.500 +125.000 uS +*/ + +//////////////////////////////////////////////////////////////////// +// +// Prescaler +// + +always @(posedge clk or posedge rst) + if(rst) rfr_en <= #1 1'b0; + else rfr_en <= #1 |cs_need_rfr; + +always @(posedge clk or posedge rst) + if(rst) ps_cnt <= #1 8'h0; + else + if(ps_cnt_clr) ps_cnt <= #1 8'h0; + else + if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1; + +assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0); + +always @(posedge clk or posedge rst) + if(rst) rfr_early <= #1 1'b0; + else rfr_early <= #1 (ps_cnt == rfr_ps_val); + +//////////////////////////////////////////////////////////////////// +// +// Refresh Counter +// + +always @(posedge clk or posedge rst) + if(rst) rfr_ce <= #1 1'b0; + else rfr_ce <= #1 ps_cnt_clr; + +always @(posedge clk or posedge rst) + if(rst) rfr_cnt <= #1 8'h0; + else + if(rfr_ack) rfr_cnt <= #1 8'h0; + else + if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1; + +always @(posedge clk) + case(ref_int) // synopsys full_case parallel_case + 3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early; + 3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early; + 3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early; + 3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early; + 3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early; + 3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early; + 3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early; + 3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early; + endcase + +always @(posedge clk or posedge rst) + if(rst) rfr_req <= #1 1'b0; + else + if(rfr_ack) rfr_req <= #1 1'b0; + else + if(rfr_clr) rfr_req <= #1 1'b1; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rf.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rf.v new file mode 100644 index 000000000..8a1d3da9f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_rf.v @@ -0,0 +1,836 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_rf.v,v 1.8 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_rf.v,v $ +// Revision 1.8 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.7 2001/12/21 05:09:29 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.6 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/10/04 03:19:37 rudi +// +// Fixed Register reads +// Tightened up timing for register rd/wr +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:42 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_rf(clk, rst, + + wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wp_err, + + csc, tms, poc, + sp_csc, sp_tms, cs, + mc_data_i, mc_sts, mc_vpen, fs, + + cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req, + init_ack, lmr_req, lmr_ack, + spec_req_cs + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +// Slave Interface +input [31:0] wb_data_i; +output [31:0] rf_dout; +input [31:0] wb_addr_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wp_err; + +// -------------------------------------- +// Misc Signals +output [31:0] csc; +output [31:0] tms; +output [31:0] poc; +output [31:0] sp_csc; +output [31:0] sp_tms; +output [7:0] cs; + +input [31:0] mc_data_i; +input mc_sts; +output mc_vpen; +output fs; + +input cs_le_d; +input cs_le; + +output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM + // attached and need to be refreshed +output [2:0] ref_int; // Refresh Interval +output [7:0] rfr_ps_val; + +output init_req; +input init_ack; +output lmr_req; +input lmr_ack; + +output [7:0] spec_req_cs; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg wb_ack_o; + +reg [31:0] csc; +reg [31:0] tms; +reg [31:0] sp_csc; +reg [31:0] sp_tms; +reg [31:0] rf_dout; +reg [7:0] cs; + +reg rf_we; +wire [31:0] csr; +reg [10:0] csr_r; +reg [7:0] csr_r2; +reg [31:0] poc; + +wire [31:0] csc_mask; +reg [10:0] csc_mask_r; + +wire [31:0] csc0, tms0; +wire [31:0] csc1, tms1; +wire [31:0] csc2, tms2; +wire [31:0] csc3, tms3; +wire [31:0] csc4, tms4; +wire [31:0] csc5, tms5; +wire [31:0] csc6, tms6; +wire [31:0] csc7, tms7; + +wire cs0, cs1, cs2, cs3; +wire cs4, cs5, cs6, cs7; +wire wp_err0, wp_err1, wp_err2, wp_err3; +wire wp_err4, wp_err5, wp_err6, wp_err7; +reg wp_err; + +wire lmr_req7, lmr_req6, lmr_req5, lmr_req4; +wire lmr_req3, lmr_req2, lmr_req1, lmr_req0; +wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4; +wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0; + +wire init_req7, init_req6, init_req5, init_req4; +wire init_req3, init_req2, init_req1, init_req0; +wire init_ack7, init_ack6, init_ack5, init_ack4; +wire init_ack3, init_ack2, init_ack1, init_ack0; + +reg init_ack_r; +wire init_ack_fe; +reg lmr_ack_r; +wire lmr_ack_fe; +wire [7:0] spec_req_cs_t; +wire [7:0] spec_req_cs_d; +reg [7:0] spec_req_cs; +reg init_req, lmr_req; +reg sreq_cs_le; + +// Aliases +assign csr = {csr_r2, 8'h0, 5'h0, csr_r}; +assign csc_mask = {21'h0, csc_mask_r}; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Read logic +// + +always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or + tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or + tms5 or csc6 or tms6 or csc7 or tms7) + case(wb_addr_i[6:2]) // synopsys full_case parallel_case + 5'h00: rf_dout <= #1 csr; + 5'h01: rf_dout <= #1 poc; + 5'h02: rf_dout <= #1 csc_mask; + + 5'h04: rf_dout <= #1 csc0; + 5'h05: rf_dout <= #1 tms0; + 5'h06: rf_dout <= #1 csc1; + 5'h07: rf_dout <= #1 tms1; + 5'h08: rf_dout <= #1 csc2; + 5'h09: rf_dout <= #1 tms2; + 5'h0a: rf_dout <= #1 csc3; + 5'h0b: rf_dout <= #1 tms3; + 5'h0c: rf_dout <= #1 csc4; + 5'h0d: rf_dout <= #1 tms4; + 5'h0e: rf_dout <= #1 csc5; + 5'h0f: rf_dout <= #1 tms5; + 5'h10: rf_dout <= #1 csc6; + 5'h11: rf_dout <= #1 tms6; + 5'h12: rf_dout <= #1 csc7; + 5'h13: rf_dout <= #1 tms7; + endcase + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Write logic +// + +reg [6:0] wb_addr_r; + +always @(posedge clk) + wb_addr_r <= #1 wb_addr_i[6:0]; + +always @(posedge clk or posedge rst) + if(rst) rf_we <= #1 1'b0; + else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we; + +always @(posedge clk or posedge rst) + if(rst) csr_r2 <= #1 8'h0; + else + if(rf_we & (wb_addr_r[6:2] == 5'h0) ) + csr_r2 <= #1 wb_data_i[31:24]; + +always @(posedge clk or posedge rst) + if(rst) csr_r[10:1] <= #1 10'h0; + else + if(rf_we & (wb_addr_r[6:2] == 5'h0) ) + csr_r[10:1] <= #1 wb_data_i[10:1]; + +always @(posedge clk) + csr_r[0] <= #1 mc_sts; + +assign mc_vpen = csr_r[1]; +assign fs = csr_r[2]; +assign rfr_ps_val = csr_r2[7:0]; + +always @(posedge clk or posedge rst) + if(rst) csc_mask_r <= #1 11'h7ff; + else + if(rf_we & (wb_addr_r[6:2] == 5'h2) ) + csc_mask_r <= #1 wb_data_i[10:0]; + +//////////////////////////////////////////////////////////////////// +// +// A kludge for cases where there is no clock during reset ... +// + +reg rst_r1, rst_r2, rst_r3; + +always @(posedge clk or posedge rst) + if(rst) rst_r1 <= #1 1'b1; + else rst_r1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rst_r2 <= #1 1'b1; + else rst_r2 <= #1 rst_r1; + +always @(posedge clk or posedge rst) + if(rst) rst_r3 <= #1 1'b1; + else rst_r3 <= #1 rst_r2; + +always @(posedge clk) + if(rst_r3) poc <= #1 mc_data_i; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Ack logic +// + +always @(posedge clk) + wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; + +//////////////////////////////////////////////////////////////////// +// +// Select CSC and TMS Registers +// + +always @(posedge clk or posedge rst) + if(rst) cs <= #1 8'h0; + else + if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0}; + +always @(posedge clk or posedge rst) + if(rst) wp_err <= #1 1'b0; + else + if(cs_le & wb_cyc_i & wb_stb_i) + wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 | + wp_err3 | wp_err2 | wp_err1 | wp_err0; + else + if(!wb_cyc_i) wp_err <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) csc <= #1 32'h0; + else + if(cs_le_d & wb_cyc_i & wb_stb_i) + begin + if(cs0) csc <= #1 csc0; + else + if(cs1) csc <= #1 csc1; + else + if(cs2) csc <= #1 csc2; + else + if(cs3) csc <= #1 csc3; + else + if(cs4) csc <= #1 csc4; + else + if(cs5) csc <= #1 csc5; + else + if(cs6) csc <= #1 csc6; + else csc <= #1 csc7; + end + +always @(posedge clk or posedge rst) + if(rst) tms <= #1 32'hffff_ffff; + else + if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i) + begin + if(cs0) tms <= #1 tms0; + else + if(cs1) tms <= #1 tms1; + else + if(cs2) tms <= #1 tms2; + else + if(cs3) tms <= #1 tms3; + else + if(cs4) tms <= #1 tms4; + else + if(cs5) tms <= #1 tms5; + else + if(cs6) tms <= #1 tms6; + else tms <= #1 tms7; + end + +always @(posedge clk or posedge rst) + if(rst) sp_csc <= #1 32'h0; + else + if(cs_le_d & wb_cyc_i & wb_stb_i) + begin + if(spec_req_cs[0]) sp_csc <= #1 csc0; + else + if(spec_req_cs[1]) sp_csc <= #1 csc1; + else + if(spec_req_cs[2]) sp_csc <= #1 csc2; + else + if(spec_req_cs[3]) sp_csc <= #1 csc3; + else + if(spec_req_cs[4]) sp_csc <= #1 csc4; + else + if(spec_req_cs[5]) sp_csc <= #1 csc5; + else + if(spec_req_cs[6]) sp_csc <= #1 csc6; + else sp_csc <= #1 csc7; + end + +always @(posedge clk or posedge rst) + if(rst) sp_tms <= #1 32'hffff_ffff; + else + if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i) + begin + if(spec_req_cs[0]) sp_tms <= #1 tms0; + else + if(spec_req_cs[1]) sp_tms <= #1 tms1; + else + if(spec_req_cs[2]) sp_tms <= #1 tms2; + else + if(spec_req_cs[3]) sp_tms <= #1 tms3; + else + if(spec_req_cs[4]) sp_tms <= #1 tms4; + else + if(spec_req_cs[5]) sp_tms <= #1 tms5; + else + if(spec_req_cs[6]) sp_tms <= #1 tms6; + else sp_tms <= #1 tms7; + end + +assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM); +assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM); + +assign ref_int = csr_r[10:8]; + +//////////////////////////////////////////////////////////////////// +// +// Init & Lmr Logic +// + +// Init Ack falling edge detector +always @(posedge clk) + init_ack_r <= #1 init_ack; + +assign init_ack_fe = init_ack_r & !init_ack; + +// LMR Ack falling edge detector +always @(posedge clk) + lmr_ack_r <= #1 lmr_ack; + +assign lmr_ack_fe = lmr_ack_r & !lmr_ack; + +// Chip Select Output +always @(posedge clk or posedge rst) + if(rst) spec_req_cs <= #1 8'h0; + else + if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d; + +always @(posedge clk or posedge rst) + if(rst) sreq_cs_le <= #1 1'b0; + else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe; + +// Make sure only one is serviced at a time +assign spec_req_cs_d[0] = spec_req_cs_t[0]; +assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0]; +assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] ); +assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] ); +assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] ); +assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] ); +assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] ); +assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] ); + +// Request Tracking +always @(posedge clk or posedge rst) + if(rst) init_req <= #1 1'b0; + else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 | + init_req4 | init_req5 | init_req6 | init_req7; + +always @(posedge clk or posedge rst) + if(rst) lmr_req <= #1 1'b0; + else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 | + lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7; + +assign spec_req_cs_t = !init_req ? // Load Mode Register Requests + {lmr_req7, lmr_req6, lmr_req5, lmr_req4, + lmr_req3, lmr_req2, lmr_req1, lmr_req0 } : + // Initialize SDRAM Requests + {init_req7, init_req6, init_req5, init_req4, + init_req3, init_req2, init_req1, init_req0 }; + +// Ack distribution +assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe; +assign lmr_ack1 = spec_req_cs[1] & lmr_ack_fe; +assign lmr_ack2 = spec_req_cs[2] & lmr_ack_fe; +assign lmr_ack3 = spec_req_cs[3] & lmr_ack_fe; +assign lmr_ack4 = spec_req_cs[4] & lmr_ack_fe; +assign lmr_ack5 = spec_req_cs[5] & lmr_ack_fe; +assign lmr_ack6 = spec_req_cs[6] & lmr_ack_fe; +assign lmr_ack7 = spec_req_cs[7] & lmr_ack_fe; + +assign init_ack0 = spec_req_cs[0] & init_ack_fe; +assign init_ack1 = spec_req_cs[1] & init_ack_fe; +assign init_ack2 = spec_req_cs[2] & init_ack_fe; +assign init_ack3 = spec_req_cs[3] & init_ack_fe; +assign init_ack4 = spec_req_cs[4] & init_ack_fe; +assign init_ack5 = spec_req_cs[5] & init_ack_fe; +assign init_ack6 = spec_req_cs[6] & init_ack_fe; +assign init_ack7 = spec_req_cs[7] & init_ack_fe; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +mc_cs_rf #(3'h0) u0( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc0 ), + .tms( tms0 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs0 ), + .wp_err( wp_err0 ), + .lmr_req( lmr_req0 ), + .lmr_ack( lmr_ack0 ), + .init_req( init_req0 ), + .init_ack( init_ack0 ) + ); + +`ifdef MC_HAVE_CS1 +mc_cs_rf #(3'h1) u1( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc1 ), + .tms( tms1 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs1 ), + .wp_err( wp_err1 ), + .lmr_req( lmr_req1 ), + .lmr_ack( lmr_ack1 ), + .init_req( init_req1 ), + .init_ack( init_ack1 ) + ); +`else +mc_cs_rf_dummy #(3'h1) u1( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc1 ), + .tms( tms1 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs1 ), + .wp_err( wp_err1 ), + .lmr_req( lmr_req1 ), + .lmr_ack( lmr_ack1 ), + .init_req( init_req1 ), + .init_ack( init_ack1 ) + ); +`endif + +`ifdef MC_HAVE_CS2 +mc_cs_rf #(3'h2) u2( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc2 ), + .tms( tms2 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs2 ), + .wp_err( wp_err2 ), + .lmr_req( lmr_req2 ), + .lmr_ack( lmr_ack2 ), + .init_req( init_req2 ), + .init_ack( init_ack2 ) + ); +`else +mc_cs_rf_dummy #(3'h2) u2( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc2 ), + .tms( tms2 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs2 ), + .wp_err( wp_err2 ), + .lmr_req( lmr_req2 ), + .lmr_ack( lmr_ack2 ), + .init_req( init_req2 ), + .init_ack( init_ack2 ) + ); +`endif + +`ifdef MC_HAVE_CS3 +mc_cs_rf #(3'h3) u3( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc3 ), + .tms( tms3 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs3 ), + .wp_err( wp_err3 ), + .lmr_req( lmr_req3 ), + .lmr_ack( lmr_ack3 ), + .init_req( init_req3 ), + .init_ack( init_ack3 ) + ); +`else +mc_cs_rf_dummy #(3'h3) u3( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc3 ), + .tms( tms3 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs3 ), + .wp_err( wp_err3 ), + .lmr_req( lmr_req3 ), + .lmr_ack( lmr_ack3 ), + .init_req( init_req3 ), + .init_ack( init_ack3 ) + ); +`endif + +`ifdef MC_HAVE_CS4 +mc_cs_rf #(3'h4) u4( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc4 ), + .tms( tms4 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs4 ), + .wp_err( wp_err4 ), + .lmr_req( lmr_req4 ), + .lmr_ack( lmr_ack4 ), + .init_req( init_req4 ), + .init_ack( init_ack4 ) + ); +`else +mc_cs_rf_dummy #(3'h4) u4( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc4 ), + .tms( tms4 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs4 ), + .wp_err( wp_err4 ), + .lmr_req( lmr_req4 ), + .lmr_ack( lmr_ack4 ), + .init_req( init_req4 ), + .init_ack( init_ack4 ) + ); +`endif + +`ifdef MC_HAVE_CS5 +mc_cs_rf #(3'h5) u5( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc5 ), + .tms( tms5 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs5 ), + .wp_err( wp_err5 ), + .lmr_req( lmr_req5 ), + .lmr_ack( lmr_ack5 ), + .init_req( init_req5 ), + .init_ack( init_ack5 ) + ); +`else +mc_cs_rf_dummy #(3'h5) u5( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc5 ), + .tms( tms5 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs5 ), + .wp_err( wp_err5 ), + .lmr_req( lmr_req5 ), + .lmr_ack( lmr_ack5 ), + .init_req( init_req5 ), + .init_ack( init_ack5 ) + ); +`endif + +`ifdef MC_HAVE_CS6 +mc_cs_rf #(3'h6) u6( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc6 ), + .tms( tms6 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs6 ), + .wp_err( wp_err6 ), + .lmr_req( lmr_req6 ), + .lmr_ack( lmr_ack6 ), + .init_req( init_req6 ), + .init_ack( init_ack6 ) + ); +`else +mc_cs_rf_dummy #(3'h6) u6( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc6 ), + .tms( tms6 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs6 ), + .wp_err( wp_err6 ), + .lmr_req( lmr_req6 ), + .lmr_ack( lmr_ack6 ), + .init_req( init_req6 ), + .init_ack( init_ack6 ) + ); +`endif + +`ifdef MC_HAVE_CS7 +mc_cs_rf #(3'h7) u7( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc7 ), + .tms( tms7 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs7 ), + .wp_err( wp_err7 ), + .lmr_req( lmr_req7 ), + .lmr_ack( lmr_ack7 ), + .init_req( init_req7 ), + .init_ack( init_ack7 ) + ); +`else +mc_cs_rf_dummy #(3'h7) u7( + .clk( clk ), + .rst( rst ), + .wb_we_i( wb_we_i ), + .din( wb_data_i ), + .rf_we( rf_we ), + .addr( wb_addr_i ), + .csc( csc7 ), + .tms( tms7 ), + .poc( poc ), + .csc_mask( csc_mask ), + .cs( cs7 ), + .wp_err( wp_err7 ), + .lmr_req( lmr_req7 ), + .lmr_ack( lmr_ack7 ), + .init_req( init_req7 ), + .init_ack( init_ack7 ) + ); +`endif + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_timing.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_timing.v new file mode 100644 index 000000000..e3a61c42f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_timing.v @@ -0,0 +1,1735 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Main Timing Block //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_timing.v,v 1.8 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_timing.v,v $ +// Revision 1.8 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.7 2001/12/21 05:09:30 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.6 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.3 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.4 2001/06/14 01:57:37 rudi +// +// +// Fixed a potential bug in a corner case situation where the TMS register +// does not propegate properly during initialisation. +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:44 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_timing(clk, rst, + + // Wishbone Interface + wb_cyc_i, wb_stb_i, wb_we_i, + wb_read_go, wb_write_go, wb_first, wb_wait, mem_ack, + err, + + // Suspend/Resume Interface + susp_req, resume_req, suspended, susp_sel, + + // Memory Interface + mc_clk, data_oe, oe_, we_, cas_, ras_, cke_, + cs_en, wb_cycle, wr_cycle, + mc_br, mc_bg, mc_adsc, mc_adv, + mc_c_oe, mc_ack, + not_mem_cyc, + + // Register File Interface + csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le, + + // Address Select Signals + cmd_a10, row_sel, next_adr, page_size, + + // OBCT Signals + bank_set, bank_clr, bank_clr_all, bank_open, any_bank_open, row_same, + + // Data path Controller Signals + dv, pack_le0, pack_le1, pack_le2, par_err, + + // Refresh Counter Signals + rfr_req, rfr_ack, + + // Initialize Request & Ack + init_req, init_ack + ); + +input clk; +input rst; + +// Wishbone Interface +input wb_cyc_i, wb_stb_i, wb_we_i; +input wb_read_go; +input wb_write_go; +input wb_first; +input wb_wait; +output mem_ack; +output err; + +// Suspend/Resume Interface +input susp_req; +input resume_req; +output suspended; +output susp_sel; + +// Memory Interface +input mc_clk; +output data_oe; +output oe_; +output we_; +output cas_; +output ras_; +output cke_; +output cs_en; +output wb_cycle; +output wr_cycle; +input mc_br; +output mc_bg; +output mc_adsc; +output mc_adv; +output mc_c_oe; +input mc_ack; +input not_mem_cyc; + +// Register File Interface +input [31:0] csc; +input [31:0] tms; +input [7:0] cs; +input lmr_req; +output lmr_ack; +output cs_le; +output cs_le_d; + +// Address Select Signals +input [10:0] page_size; +output cmd_a10; +output row_sel; +output next_adr; + +// OBCT Signals +output bank_set; +output bank_clr; +output bank_clr_all; +input bank_open; +input any_bank_open; +input row_same; + +// Data path Controller Signals +output dv; +output pack_le0, pack_le1, pack_le2; // Pack Latch Enable +input par_err; + +// Refresh Counter Signals +input rfr_req; +output rfr_ack; + +// Initialize Request & Ack +input init_req; +output init_ack; + +//////////////////////////////////////////////////////////////////// +// +// Defines & Parameters +// + +// Number of states: 66 +parameter [65:0] // synopsys enum state +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +POR = 66'b000000000000000000000000000000000000000000000000000000000000000001, +IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010, +IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100, +IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000, +PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000, +PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000, +ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000, +ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000, +SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000, +SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000, +SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000, +SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000, +SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000, +SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000, +SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000, +BT = 66'b000000000000000000000000000000000000000000000000001000000000000000, +BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000, +REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000, +LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000, +LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000, +LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000, +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000, +INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000, +INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000, +INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000, +INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000, +// 6666666555555555544444444443333333333222222222211111111110000000000 +// 6543210987654321098765432109876543210987654321098765432109876543210 +INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000, +SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000, +SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000, +SUSP3 = 66'b000000000000000000000000000000000000100000000000000000000000000000, +SUSP4 = 66'b000000000000000000000000000000000001000000000000000000000000000000, +RESUME1 = 66'b000000000000000000000000000000000010000000000000000000000000000000, +RESUME2 = 66'b000000000000000000000000000000000100000000000000000000000000000000, +BG0 = 66'b000000000000000000000000000000001000000000000000000000000000000000, +BG1 = 66'b000000000000000000000000000000010000000000000000000000000000000000, +BG2 = 66'b000000000000000000000000000000100000000000000000000000000000000000, +ACS_RD = 66'b000000000000000000000000000001000000000000000000000000000000000000, +ACS_RD1 = 66'b000000000000000000000000000010000000000000000000000000000000000000, +ACS_RD2A = 66'b000000000000000000000000000100000000000000000000000000000000000000, +ACS_RD2 = 66'b000000000000000000000000001000000000000000000000000000000000000000, +ACS_RD3 = 66'b000000000000000000000000010000000000000000000000000000000000000000, +ACS_RD_8_1 = 66'b000000000000000000000000100000000000000000000000000000000000000000, +ACS_RD_8_2 = 66'b000000000000000000000001000000000000000000000000000000000000000000, +ACS_RD_8_3 = 66'b000000000000000000000010000000000000000000000000000000000000000000, +ACS_RD_8_4 = 66'b000000000000000000000100000000000000000000000000000000000000000000, +ACS_RD_8_5 = 66'b000000000000000000001000000000000000000000000000000000000000000000, +ACS_RD_8_6 = 66'b000000000000000000010000000000000000000000000000000000000000000000, +ACS_WR = 66'b000000000000000000100000000000000000000000000000000000000000000000, +ACS_WR1 = 66'b000000000000000001000000000000000000000000000000000000000000000000, +ACS_WR2 = 66'b000000000000000010000000000000000000000000000000000000000000000000, +ACS_WR3 = 66'b000000000000000100000000000000000000000000000000000000000000000000, +ACS_WR4 = 66'b000000000000001000000000000000000000000000000000000000000000000000, +SRAM_RD = 66'b000000000000010000000000000000000000000000000000000000000000000000, +SRAM_RD0 = 66'b000000000000100000000000000000000000000000000000000000000000000000, +SRAM_RD1 = 66'b000000000001000000000000000000000000000000000000000000000000000000, +SRAM_RD2 = 66'b000000000010000000000000000000000000000000000000000000000000000000, +SRAM_RD3 = 66'b000000000100000000000000000000000000000000000000000000000000000000, +SRAM_RD4 = 66'b000000001000000000000000000000000000000000000000000000000000000000, +SRAM_WR = 66'b000000010000000000000000000000000000000000000000000000000000000000, +SRAM_WR0 = 66'b000000100000000000000000000000000000000000000000000000000000000000, +SCS_RD = 66'b000001000000000000000000000000000000000000000000000000000000000000, +SCS_RD1 = 66'b000010000000000000000000000000000000000000000000000000000000000000, +SCS_RD2 = 66'b000100000000000000000000000000000000000000000000000000000000000000, +SCS_WR = 66'b001000000000000000000000000000000000000000000000000000000000000000, +SCS_WR1 = 66'b010000000000000000000000000000000000000000000000000000000000000000, +SCS_ERR = 66'b100000000000000000000000000000000000000000000000000000000000000000; + +//////////////////////////////////////////////////////////////////// +// +// Local Registers & Wires +// + +reg [65:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg mc_bg; + +wire [2:0] mem_type; +wire [1:0] bus_width; +wire kro; + +wire cs_a; +reg [3:0] cmd; + +wire mem_ack; +wire mem_ack_s; +reg mem_ack_d; +reg err_d; +wire err; +reg cmd_a10; +reg lmr_ack; +reg lmr_ack_d; +reg row_sel; +reg oe_; +reg oe_d; +reg data_oe; +reg data_oe_d; +reg cke_d; +reg cke_; +reg init_ack; +reg dv; +reg rfr_ack_d; +reg mc_adsc; +reg mc_adv; + +reg bank_set; +reg bank_clr; +reg bank_clr_all; + +reg wr_set, wr_clr; +reg wr_cycle; + +reg cmd_asserted; +reg cmd_asserted2; + +reg [10:0] burst_val; +reg [10:0] burst_cnt; +wire burst_act; +reg burst_act_rd; +wire single_write; + +reg cs_le_d; +reg cs_le; +reg cs_le_r; + +reg susp_req_r; +reg resume_req_r; +reg suspended; +reg suspended_d; +reg susp_sel_set, susp_sel_clr, susp_sel_r; + +reg [3:0] cmd_del; +reg [3:0] cmd_r; +reg data_oe_r; +reg data_oe_r2; +reg cke_r; +reg cke_rd; +reg cke_o_del; +reg cke_o_r1; +reg cke_o_r2; +reg wb_cycle_set, wb_cycle; +reg [3:0] ack_cnt; +wire ack_cnt_is_0; +reg cnt, cnt_next; +reg [7:0] timer; +reg tmr_ld_trp, tmr_ld_trcd, tmr_ld_tcl, tmr_ld_trfc; +reg tmr_ld_twr, tmr_ld_txsr; +reg tmr2_ld_tscsto; +reg tmr_ld_trdv; +reg tmr_ld_trdz; +reg tmr_ld_twr2; +wire timer_is_zero; +reg tmr_done; +reg tmr2_ld_trdv, tmr2_ld_trdz; +reg tmr2_ld_twpw, tmr2_ld_twd, tmr2_ld_twwd; +reg tmr2_ld_tsrdv; +reg [8:0] timer2; +reg tmr2_done; +wire timer2_is_zero; +reg [3:0] ir_cnt; +reg ir_cnt_ld; +reg ir_cnt_dec; +reg ir_cnt_done; +reg rfr_ack_r; +reg burst_cnt_ld; +reg burst_fp; +reg wb_wait_r, wb_wait_r2; +reg lookup_ready1, lookup_ready2; +reg burst_cnt_ld_4; +reg dv_r; +reg mc_adv_r1, mc_adv_r; + +reg next_adr; +reg pack_le0, pack_le1, pack_le2; +reg pack_le0_d, pack_le1_d, pack_le2_d; +wire bw8, bw16; + +reg mc_c_oe_d; +reg mc_c_oe; + +reg mc_le; +reg mem_ack_r; + +reg rsts, rsts1; +reg no_wb_cycle; + +wire bc_dec; +reg ap_en; // Auto Precharge Enable +reg cmd_a10_r; +reg wb_stb_first; +reg tmr_ld_tavav; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// +assign mem_type = csc[3:1]; +assign bus_width = csc[5:4]; +assign kro = csc[10]; +assign single_write = tms[9] | (tms[2:0] == 3'h0); + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// +reg cs_le_r1; + +always @(posedge clk) + lmr_ack <= #1 lmr_ack_d; + +assign rfr_ack = rfr_ack_r; + +always @(posedge clk) + cs_le_r <= #1 cs_le_r1; + +always @(posedge clk) + cs_le_r1 <= #1 cs_le; + +always @(posedge clk) + cs_le <= #1 cs_le_d; + +always @(posedge mc_clk or posedge rst) + if(rst) rsts1 <= #1 1'b1; + else rsts1 <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rsts <= #1 1'b1; + else rsts <= #1 rsts1; + +// Control Signals Output Enable +always @(posedge clk or posedge rst) + if(rst) mc_c_oe <= #1 1'b0; + else mc_c_oe <= #1 mc_c_oe_d; + +always @(posedge clk or posedge rsts) + if(rsts) mc_le <= #1 1'b0; + else mc_le <= #1 ~mc_le; + +always @(posedge clk) + pack_le0 <= #1 pack_le0_d; + +always @(posedge clk) + pack_le1 <= #1 pack_le1_d; + +always @(posedge clk) + pack_le2 <= #1 pack_le2_d; + +always @(posedge clk or posedge rst) + if(rst) mc_adv_r1 <= #1 1'b0; + else + if(!mc_le) mc_adv_r1 <= #1 mc_adv; + +always @(posedge clk or posedge rst) + if(rst) mc_adv_r <= #1 1'b0; + else + if(!mc_le) mc_adv_r <= #1 mc_adv_r1; + +// Bus Width decoder +assign bw8 = (bus_width == `MC_BW_8); +assign bw16 = (bus_width == `MC_BW_16); + +// Any Chip Select +assign cs_a = |cs; + +// Memory to Wishbone Ack +assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go); + +always @(posedge clk or posedge rst) + if(rst) mem_ack_r <= #1 1'b0; + else mem_ack_r <= #1 mem_ack; + +assign err = err_d; + +// SDRAM Command, either delayed (for writes) or straight through +always @(posedge clk or posedge rst) + if(rst) cmd_r <= #1 `MC_CMD_NOP; + else cmd_r <= #1 cmd; + +always @(posedge clk or posedge rst) + if(rst) cmd_del <= #1 `MC_CMD_NOP; + else cmd_del <= #1 cmd_r; + +assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd; + +// Track Timing of Asserting a command +always @(posedge clk or posedge rst) + if(rst) cmd_asserted <= #1 1'b0; + else + if(!mc_le) cmd_asserted <= #1 cmd[3]; + +always @(posedge clk or posedge rst) + if(rst) cmd_asserted2 <= #1 1'b0; + else + if(!mc_le) cmd_asserted2 <= #1 cmd_asserted; + +// Output Enable +always @(posedge clk or posedge rst) + if(rst) oe_ <= #1 1'b1; + else oe_ <= #1 ~oe_d; + +// Memory Bus Data lines Output Enable +always @(posedge clk or posedge rst) + if(rst) data_oe_r <= #1 1'b0; + else data_oe_r <= #1 data_oe_d; + +always @(posedge clk or posedge rst) + if(rst) data_oe_r2 <= #1 1'b0; + else data_oe_r2 <= #1 data_oe_r; + +always @(posedge clk or posedge rst) + if(rst) data_oe <= #1 1'b0; + else data_oe <= #1 wr_cycle ? data_oe_r2 : data_oe_d; + +// Clock Enable +always @(posedge clk) + cke_r <= #1 cke_d; + +always @(posedge clk) + cke_ <= #1 cke_r & cke_rd; + +// CKE output delay line to time DV for reads +always @(posedge clk) + cke_o_r1 <= #1 cke_; + +always @(posedge clk) + cke_o_r2 <= #1 cke_o_r1; + +always @(posedge clk) + cke_o_del <= #1 cke_o_r2; + +// Delayed version of the wb_wait input +always @(posedge clk) + wb_wait_r2 <= #1 wb_wait; + +always @(posedge clk) + wb_wait_r <= #1 wb_wait_r2; + +// Indicates when the row_same and bank_open lookups are done +reg lookup_ready1a; + +always @(posedge clk or posedge rst) + if(rst) lookup_ready1 <= #1 1'b0; + else lookup_ready1 <= #1 cs_le & wb_cyc_i & wb_stb_i; + +always @(posedge clk or posedge rst) + if(rst) lookup_ready2 <= #1 1'b0; + else lookup_ready2 <= #1 lookup_ready1 & wb_cyc_i & wb_stb_i; + +// Keep Track if it is a SDRAM write cycle +always @(posedge clk or posedge rst) + if(rst) wr_cycle <= #1 1'b0; + else + if(wr_set) wr_cycle <= #1 1'b1; + else + if(wr_clr) wr_cycle <= #1 1'b0; + +// Track when a cycle is *still* active +always @(posedge clk or posedge rst) + if(rst) wb_cycle <= #1 1'b0; + else + if(wb_cycle_set) wb_cycle <= #1 1'b1; + else + if(!wb_cyc_i | not_mem_cyc) wb_cycle <= #1 1'b0; + +// Thses two signals are used to signal that no wishbone cycle is in +// progress. Need to register them to avoid a very long combinatorial +// path .... +always @(posedge clk or posedge rst) + if(rst) no_wb_cycle <= #1 1'b0; + else no_wb_cycle <= #1 !wb_read_go & !wb_write_go; + +// Track ack's for read cycles +always @(posedge clk or posedge rst) + if(rst) ack_cnt <= #1 4'h0; + else + if(no_wb_cycle) ack_cnt <= #1 4'h0; + else + if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1; + else + if(!dv & mem_ack_s) ack_cnt <= #1 ack_cnt - 4'h1; + +assign ack_cnt_is_0 = (ack_cnt==4'h0); + +assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack_r & wb_read_go & !(wb_we_i & wb_stb_i); + +// Internal Cycle Tracker +always @(posedge clk) + cnt <= #1 cnt_next; + +// Suspend/resume Logic +always @(posedge clk or posedge rst) + if(rst) susp_req_r <= #1 1'b0; + else susp_req_r <= #1 susp_req; + +always @(posedge clk or posedge rst) + if(rst) resume_req_r <= #1 1'b0; + else resume_req_r <= #1 resume_req; + +always @(posedge clk or posedge rst) + if(rst) suspended <= #1 1'b0; + else suspended <= #1 suspended_d; + +always @(posedge clk or posedge rst) + if(rst) rfr_ack_r <= #1 1'b0; + else rfr_ack_r <= #1 rfr_ack_d; + +// Suspend Select Logic +assign susp_sel = susp_sel_r; + +always @(posedge clk or posedge rst) + if(rst) susp_sel_r <= #1 1'b0; + else + if(susp_sel_set) susp_sel_r <= #1 1'b1; + else + if(susp_sel_clr) susp_sel_r <= #1 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Timing Logic +// +wire [3:0] twrp; +wire twd_is_zero; +wire [31:0] tms_x; + +// FIX_ME +// Hard wire worst case or make it programmable ??? +assign tms_x = (rfr_ack_d | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms; + +always @(posedge clk) + if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16]; + else + if(tmr2_ld_tsrdv) timer2 <= #1 9'd4; // SSRAM RD->1st DATA VALID + else + if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]}; + else + if(tmr2_ld_twd) timer2 <= #1 { 4'h0, tms_x[19:16],1'b0}; + else + if(tmr2_ld_twwd) timer2 <= #1 { 3'h0, tms_x[25:20]}; + else + if(tmr2_ld_trdz) timer2 <= #1 { 4'h0, tms_x[11:8], 1'b1}; + else + if(tmr2_ld_trdv) timer2 <= #1 { tms_x[7:0], 1'b1}; + else + if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1; + +assign twd_is_zero = (tms_x[19:16] == 4'h0); + +assign timer2_is_zero = (timer2 == 9'h0); + +always @(posedge clk or posedge rst) + if(rst) tmr2_done <= #1 1'b0; + else tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz & + !tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto; + +assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20]; + +// SDRAM Memories timing tracker +always @(posedge clk or posedge rst) +`ifdef MC_POR_DELAY + if(rst) timer <= #1 `MC_POR_DELAY_VAL ; + else +`endif + if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] }; + else + if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] }; + else + if(tmr_ld_trdv) timer <= #1 tms_x[7:0]; + else + if(tmr_ld_twr) timer <= #1 { 4'h0, twrp}; + else + if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]}; + else + if(tmr_ld_trcd) timer <= #1 { 5'h0, tms_x[19:17]}; + else + if(tmr_ld_tcl) timer <= #1 { 6'h0, tms_x[05:04]}; + else + if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]}; + else + if(tmr_ld_tavav) timer <= #1 8'h3; + else + if(tmr_ld_txsr) timer <= #1 8'h7; + else + if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1; + +assign timer_is_zero = (timer == 8'h0); + +always @(posedge clk or posedge rst) + if(rst) tmr_done <= #1 1'b0; + else tmr_done <= #1 timer_is_zero; + +// Init Refresh Cycles Counter +always @(posedge clk) + if(ir_cnt_ld) ir_cnt <= #1 `MC_INIT_RFRC_CNT; + else + if(ir_cnt_dec) ir_cnt <= #1 ir_cnt - 4'b1; + +always @(posedge clk) + ir_cnt_done <= #1 (ir_cnt == 4'h0); + +// Burst Counter +always @(tms_x or page_size) + case(tms_x[2:0]) // synopsys full_case parallel_case + 3'h0: burst_val = 11'h1; + 3'h1: burst_val = 11'h2; + 3'h2: burst_val = 11'h4; + 3'h3: burst_val = 11'h8; + 3'h7: burst_val = page_size; + endcase + +assign bc_dec = wr_cycle ? mem_ack_d : dv; + +always @(posedge clk) + if(burst_cnt_ld_4) burst_cnt <= #1 11'h4; // for SSRAM only + else + if(burst_cnt_ld) burst_cnt <= #1 burst_val; + else + if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1; + +always @(posedge clk or posedge rst) + if(rst) burst_fp <= #1 1'b0; + else + if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7); + +// Auto Precharge Enable +always @(posedge clk or posedge rst) + if(rst) ap_en <= #1 1'b0; + else + if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro; + +assign burst_act = |burst_cnt & ( |tms_x[2:0] ); + +always @(posedge clk) + burst_act_rd <= #1 |burst_cnt; + +always @(posedge clk or posedge rst) + if(rst) dv_r <= #1 1'b0; + else dv_r <= #1 dv; + +always @(posedge clk) // Auto Precharge Holding Register + cmd_a10_r <= #1 cmd_a10; + +//////////////////////////////////////////////////////////////////// +// +// Main State Machine +// +reg wb_write_go_r; + +always @(posedge clk) + wb_write_go_r <= #1 wb_write_go; + +always @(posedge clk or posedge rst) + if(rst) wb_stb_first <= #1 1'b0; + else + if(mem_ack) wb_stb_first <= #1 1'b0; + else + if(wb_first & wb_stb_i) wb_stb_first <= #1 1'b1; + +always @(posedge clk or posedge rst) +`ifdef MC_POR_DELAY + if(rst) state <= #1 POR; +`else + if(rst) state <= #1 IDLE; +`endif + else state <= #1 next_state; + +always @(state or cs_a or cs_le or cs_le_r or + twd_is_zero or wb_stb_i or wb_write_go_r or + wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack_r or wb_we_i or + ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or wr_cycle or + mem_type or kro or lookup_ready2 or row_same or cmd_a10_r or + bank_open or single_write or + cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or + burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or + rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or + mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack or wb_stb_first or ap_en + ) + begin + next_state = state; // Default keep current state + cnt_next = 1'b0; + + cmd = `MC_CMD_NOP; + cmd_a10 = ap_en; + oe_d = 1'b0; + data_oe_d = 1'b0; + cke_d = 1'b1; + cke_rd = 1'b1; + mc_adsc = 1'b0; + mc_adv = 1'b0; + + bank_set = 1'b0; + bank_clr = 1'b0; + bank_clr_all = 1'b0; + + burst_cnt_ld = 1'b0; + burst_cnt_ld_4 = 1'b0; + tmr_ld_trp = 1'b0; + tmr_ld_trcd = 1'b0; + tmr_ld_tcl = 1'b0; + tmr_ld_trfc = 1'b0; + tmr_ld_twr = 1'b0; + tmr_ld_txsr = 1'b0; + tmr_ld_trdv = 1'b0; + tmr_ld_trdz = 1'b0; + tmr_ld_twr2 = 1'b0; + tmr_ld_tavav = 1'b0; + + tmr2_ld_trdv = 1'b0; + tmr2_ld_trdz = 1'b0; + + tmr2_ld_twpw = 1'b0; + tmr2_ld_twd = 1'b0; + tmr2_ld_twwd = 1'b0; + tmr2_ld_tsrdv = 1'b0; + tmr2_ld_tscsto = 1'b0; + + mem_ack_d = 1'b0; + err_d = 1'b0; + rfr_ack_d = 1'b0; + lmr_ack_d = 1'b0; + init_ack = 1'b0; + + ir_cnt_dec = 1'b0; + ir_cnt_ld = 1'b0; + + row_sel = 1'b0; + cs_le_d = 1'b0; + wr_clr = 1'b0; + wr_set = 1'b0; + wb_cycle_set = 1'b0; + dv = 1'b0; + + suspended_d = 1'b0; + susp_sel_set = 1'b0; + susp_sel_clr = 1'b0; + mc_bg = 1'b0; + + next_adr = 1'b0; + pack_le0_d = 1'b0; + pack_le1_d = 1'b0; + pack_le2_d = 1'b0; + + mc_c_oe_d = 1'b1; + + case(state) // synopsys full_case parallel_case +`ifdef MC_POR_DELAY + POR: + begin + if(tmr_done) next_state = IDLE; + end +`endif + IDLE: + begin + //cs_le_d = wb_stb_first | lmr_req; + cs_le_d = wb_stb_first; + + burst_cnt_ld = 1'b1; + wr_clr = 1'b1; + + if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1; + if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1; + + if(rfr_req) + begin + rfr_ack_d = 1'b1; + next_state = PRECHARGE; + end + else + if(init_req) + begin + cs_le_d = 1'b1; + next_state = INIT0; + end + else + if(lmr_req & lookup_ready2) + begin + lmr_ack_d = 1'b1; + cs_le_d = 1'b1; + next_state = LMR0; + end + else + if(susp_req_r & !wb_cycle) + begin + cs_le_d = 1'b1; + susp_sel_set = 1'b1; + next_state = SUSP1; + end + else + if(cs_a & (wb_read_go | wb_write_go) & lookup_ready2) + begin + wb_cycle_set = 1'b1; + case(mem_type) // synopsys full_case parallel_case + `MC_MEM_TYPE_SDRAM: // SDRAM + if((lookup_ready2) & !wb_wait) + begin + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + if(kro & bank_open & row_same) next_state = SD_RD_WR; + else + if(kro & bank_open) next_state = PRECHARGE; + else next_state = ACTIVATE; + end + `MC_MEM_TYPE_ACS: + begin // Async Chip Select + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + data_oe_d = 1'b1; + next_state = ACS_WR; + end + else next_state = ACS_RD; + end + end + `MC_MEM_TYPE_SCS: + begin // Sync Chip Select + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + tmr_ld_twr2 = 1'b1; + next_state = SCS_WR; + end + else + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr_ld_trdv = 1'b1; + next_state = SCS_RD; + end + end + end + `MC_MEM_TYPE_SRAM: + begin // SRAM + if(!wb_wait) + begin + cs_le_d = 1'b1; + if(wb_write_go) + begin + data_oe_d = 1'b1; + mem_ack_d = 1'b1; + next_state = SRAM_WR; + end + else + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + mc_adsc = 1'b1; + next_state = SRAM_RD; + end + end + end + endcase + end + else + if(mc_br) + begin + if(!cmd_asserted2) + begin + next_state = BG0; + mc_c_oe_d = 1'b0; + end + end + end + + IDLE_T: + begin + cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes + if(tmr_done & wb_cycle & !wb_wait) cs_le_d = 1'b1; + if(tmr_done) next_state = IDLE; + end + + IDLE_T2: + begin + if(tmr2_done & (!wb_wait | !wb_cycle) ) + begin + cs_le_d = wb_cycle; + if(cs_le_r | !wb_cycle) next_state = IDLE; + end + end + + ///////////////////////////////////////// + // SCS STATES .... + ///////////////////////////////////////// + SCS_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr_ld_trdv = 1'b1; + if(mc_ack) next_state = SCS_RD1; + else + if(tmr2_done) next_state = SCS_ERR; + end + + SCS_RD1: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr_done) + begin + mem_ack_d = 1'b1; + tmr_ld_trdz = 1'b1; + next_state = SCS_RD2; + end + end + + SCS_RD2: + begin + tmr_ld_trdz = 1'b1; + next_state = IDLE_T; + end + + SCS_WR: + begin + tmr_ld_twr2 = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + if(mc_ack) next_state = SCS_WR1; + else + if(tmr2_done) next_state = SCS_ERR; + end + + SCS_WR1: + begin + data_oe_d = 1'b1; + if(tmr_done) + begin + mem_ack_d = 1'b1; + next_state = IDLE_T; + end + else cmd = `MC_CMD_XWR; + end + + SCS_ERR: + begin + mem_ack_d = 1'b1; + err_d = 1'b1; + next_state = IDLE_T2; + end + + ///////////////////////////////////////// + // SSRAM STATES .... + ///////////////////////////////////////// + SRAM_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + mc_adsc = 1'b1; + tmr2_ld_tsrdv = 1'b1; + burst_cnt_ld_4 = 1'b1; + if(cmd_asserted) next_state = SRAM_RD0; + end + + SRAM_RD0: + begin + mc_adv = 1'b1; + oe_d = 1'b1; + if(tmr2_done) + begin + mc_adv = !wb_wait; + next_state = SRAM_RD1; + end + end + + SRAM_RD1: + begin + if(mc_adv_r) dv = ~dv_r; + mc_adv = !wb_wait; + + if(!burst_act | !wb_read_go) next_state = SRAM_RD2; + else oe_d = 1'b1; + end + + SRAM_RD2: + begin + if(ack_cnt_is_0 & wb_read_go) next_state = SRAM_RD3; + else + if(!wb_read_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + end + + SRAM_RD3: + begin + if(!wb_read_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + if(!wb_wait) + begin + cs_le_d = 1'b1; + next_state = SRAM_RD; + end + end + + SRAM_RD4: // DESELECT + begin + if(wb_cycle) cs_le_d = 1'b1; // For RMW + mc_adsc = 1'b1; + next_state = IDLE; + end + + SRAM_WR: + begin + cmd = `MC_CMD_XWR; + mc_adsc = 1'b1; + data_oe_d = 1'b1; + if(cmd_asserted) + begin + if(wb_wait) next_state = SRAM_WR0; + else + if(!wb_write_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + begin + data_oe_d = 1'b1; + mem_ack_d = ~mem_ack_r; + end + end + end + + SRAM_WR0: + begin + if(wb_wait) next_state = SRAM_WR0; + else + if(!wb_write_go) + begin + mc_adsc = 1'b1; + next_state = SRAM_RD4; + end + else + begin + data_oe_d = 1'b1; + next_state = SRAM_WR; + end + end + + ///////////////////////////////////////// + // Async Devices STATES .... + ///////////////////////////////////////// + ACS_RD: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD1; + end + + ACS_RD1: + begin // 32 bit, 8 bit - first; 16 bit - first + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + if(bw8 | bw16) next_adr = 1'b1; + if(bw8) next_state = ACS_RD_8_1; + else + if(bw16) next_state = ACS_RD_8_5; + else next_state = ACS_RD2A; + end + end + + ACS_RD_8_1: + begin // 8 bit 2nd byte + pack_le0_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_2; + end + + ACS_RD_8_2: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_adr = 1'b1; + next_state = ACS_RD_8_3; + end + end + + ACS_RD_8_3: + begin // 8 bit 3rd byte + pack_le1_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_4; + end + + ACS_RD_8_4: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_adr = 1'b1; + next_state = ACS_RD_8_5; + end + end + + ACS_RD_8_5: + begin // 8 bit 4th byte; 16 bit 2nd word + if(bw8) pack_le2_d = 1'b1; + if(bw16) pack_le0_d = 1'b1; + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + tmr2_ld_trdv = 1'b1; + next_state = ACS_RD_8_6; + end + + ACS_RD_8_6: + begin + cmd = `MC_CMD_XRD; + oe_d = 1'b1; + if(tmr2_done) + begin + next_state = ACS_RD2; + end + end + + ACS_RD2A: + begin + oe_d = 1'b1; + cmd = `MC_CMD_XRD; + next_state = ACS_RD2; + end + + ACS_RD2: + begin + cmd = `MC_CMD_XRD; + next_state = ACS_RD3; + end + + ACS_RD3: + begin + mem_ack_d = 1'b1; + tmr2_ld_trdz = 1'b1; + next_state = IDLE_T2; + end + + ACS_WR: + begin + tmr2_ld_twpw = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + next_state = ACS_WR1; + end + + ACS_WR1: + begin + if(!cmd_asserted) tmr2_ld_twpw = 1'b1; + cmd = `MC_CMD_XWR; + data_oe_d = 1'b1; + if(tmr2_done) + begin + tmr2_ld_twd = 1'b1; + next_state = ACS_WR2; + end + end + + ACS_WR2: + begin + if(twd_is_zero) next_state = ACS_WR3; + else + begin + cmd = `MC_CMD_XRD; + data_oe_d = 1'b1; + next_state = ACS_WR3; + end + end + + ACS_WR3: + begin + if(tmr2_done) next_state = ACS_WR4; + else cmd = `MC_CMD_XRD; + end + + ACS_WR4: + begin + tmr2_ld_twwd = 1'b1; + mem_ack_d = 1'b1; + next_state = IDLE_T2; + end + + ///////////////////////////////////////// + // SDRAM STATES .... + ///////////////////////////////////////// + + PRECHARGE: + begin + cmd = `MC_CMD_PC; + if(rfr_ack_r) + begin + rfr_ack_d = 1'b1; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + end + else + begin + bank_clr = 1'b1; + cmd_a10 = `MC_SINGLE_BANK; + end + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = PRECHARGE_W; + end + + PRECHARGE_W: + begin + rfr_ack_d = rfr_ack_r; + if(tmr_done) + begin + if(rfr_ack_r) next_state = REFR; + else next_state = ACTIVATE; + end + end + + ACTIVATE: + begin + if(!wb_wait_r) + begin + row_sel = 1'b1; + tmr_ld_trcd = 1'b1; + cmd = `MC_CMD_ACT; + end + if(cmd_asserted) next_state = ACTIVATE_W; + end + + ACTIVATE_W: + begin + row_sel = 1'b1; + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + + if(kro) bank_set = 1'b1; + + if(tmr_done) + begin + if(wb_write_go) + begin + mem_ack_d = ~mem_ack_r; + cmd_a10 = ap_en | (single_write & !kro); + next_state = SD_WR; + end + else + if(!wb_wait_r) next_state = SD_RD; + end + end + + SD_RD_WR: + begin + if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1; + + if(wb_write_go & !wb_wait) + begin // Write + data_oe_d = 1'b1; + mem_ack_d = ~mem_ack_r; + cmd_a10 = ap_en | (single_write & !kro); + next_state = SD_WR; + end + else + if(!wb_wait) + begin // Read + if(kro) + begin + if(!wb_wait_r) next_state = SD_RD; + end + else next_state = SD_RD; + end + end + + SD_WR: // Write Command + begin // Does the first single write + data_oe_d = 1'b1; + tmr_ld_twr = 1'b1; + cnt_next = ~cnt; + cmd = `MC_CMD_WR; + + cmd_a10 = ap_en | (single_write & !kro); + + if(!cnt & wb_cycle & burst_act) cke_d = ~wb_wait; + else cke_d = cke_r; + + if(cmd_asserted) + begin + mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wb_cycle & burst_act; + + if(wb_cycle & !burst_act) next_state = IDLE_T; + else + if(wb_write_go) next_state = SD_WR_W; + else + if(burst_act & !single_write) next_state = BT; + else + if(!ap_en) next_state = BT_W; + else next_state = IDLE_T; + end + + end + + SD_WR_W: + begin // Does additional Writes or Times them + tmr_ld_twr = 1'b1; + cnt_next = ~cnt; + + if(single_write & wb_cycle) + begin + cmd = `MC_CMD_WR; + end + cmd_a10 = ap_en | (single_write & !kro); + + data_oe_d = 1'b1; + mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wr_cycle & burst_act; + + if(!cnt) cke_d = ~wb_wait; + else cke_d = cke_r; + + if( (single_write & cke_r) | (!single_write & !cnt & !wb_wait) | (!single_write & cnt & cke_r) ) + begin + if(single_write & !wb_cycle) next_state = IDLE_T; + else + if(burst_act & !single_write & !wb_write_go_r) + begin + cmd = `MC_CMD_BT; + next_state = BT; + end + else + if(!burst_act & !ap_en) next_state = BT_W; + else + if(!burst_act) next_state = IDLE_T; + else + if(!wb_write_go_r & wb_read_go) next_state = IDLE_T; // Added for WMR + end + end + + SD_RD: // Read Command + begin + cmd = `MC_CMD_RD; + cmd_a10 = ap_en; + tmr_ld_tcl = 1'b1; + if(cmd_asserted) next_state = SD_RD_W; + end + + SD_RD_W: + begin + if(tmr_done) next_state = SD_RD_LOOP; + end + + SD_RD_LOOP: + begin + cnt_next = ~cnt; + + if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait; + else cke_rd = cke_; + + if(wb_cycle & !cnt & burst_act_rd & cke_o_del) dv = 1'b1; + + if(wb_cycle & wb_write_go) next_state = BT; + else + if(burst_act & !wb_cycle) next_state = BT; + else + if(!burst_act) next_state = SD_RD_W2; + end + + SD_RD_W2: + begin + if(wb_write_go | ack_cnt_is_0) + begin + if(!ap_en & !kro) next_state = BT_W; + else + if(!wb_wait & !mem_ack_r) next_state = IDLE_T; + end + end + + BT: + begin + cmd = `MC_CMD_BT; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = BT_W; + end + + BT_W: + begin + cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes + + if(kro & tmr_done) + begin + if(kro & !wb_wait & (wb_read_go | wb_write_go) ) cs_le_d = 1'b1; + next_state = IDLE; + end + else + if(!kro & tmr_done) // Must do a PRECHARGE after Burst Terminate + begin + bank_clr = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_SINGLE_BANK; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + end + + REFR: // Refresh Cycle + begin + cs_le_d = 1'b1; + cmd = `MC_CMD_ARFR; + tmr_ld_trfc = 1'b1; + rfr_ack_d = 1'b1; + if(cmd_asserted) + begin + susp_sel_clr = 1'b1; + next_state = IDLE_T; + end + end + + LMR0: + begin + lmr_ack_d = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = LMR1; + end + + LMR1: + begin + lmr_ack_d = 1'b1; + if(tmr_done) next_state = LMR2; + end + + LMR2: + begin + bank_clr_all = 1'b1; + cmd = `MC_CMD_LMR; + tmr_ld_trfc = 1'b1; + lmr_ack_d = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + + INIT0: + begin + cs_le_d = 1'b1; + next_state = INIT; + end + + INIT: // Initialize SDRAMS + begin // PRECHARGE + init_ack = 1'b1; + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + ir_cnt_ld = 1'b1; + if(cmd_asserted) next_state = INIT_W; + end + + INIT_W: + begin + init_ack = 1'b1; + if(tmr_done) next_state = INIT_REFR1; + end + + INIT_REFR1: // Init Refresh Cycle 1 + begin + init_ack = 1'b1; + cmd = `MC_CMD_ARFR; + tmr_ld_trfc = 1'b1; + if(cmd_asserted) + begin + ir_cnt_dec = 1'b1; + next_state = INIT_REFR1_W; + end + end + + INIT_REFR1_W: + begin + init_ack = 1'b1; + if(tmr_done) + begin + if(ir_cnt_done) next_state = INIT_LMR; + else next_state = INIT_REFR1; + end + end + + INIT_LMR: + begin + init_ack = 1'b1; + cmd = `MC_CMD_LMR; + bank_clr_all = 1'b1; + tmr_ld_trfc = 1'b1; + if(cmd_asserted) next_state = IDLE_T; + end + + ///////////////////////////////////////// + // Bus Arbitration STATES .... + ///////////////////////////////////////// + BG0: + begin // Bus Grant + mc_bg = 1'b1; + mc_c_oe_d = 1'b0; + next_state = BG1; + end + BG1: + begin // Bus Grant + mc_bg = 1'b1; + cs_le_d = 1'b1; + mc_c_oe_d = 1'b0; + next_state = BG2; + end + BG2: + begin // Bus Grant + cs_le_d = 1'b1; + mc_bg = !wb_read_go & !wb_write_go & + !rfr_req & !init_req & !lmr_req & + !susp_req_r; + tmr_ld_tavav = 1'b1; + mc_c_oe_d = mc_br; + if(!mc_br) next_state = IDLE_T; + end + + ///////////////////////////////////////// + // SUSPEND/RESUME STATES .... + ///////////////////////////////////////// + SUSP1: + begin // Precharge All + cmd = `MC_CMD_PC; + cmd_a10 = `MC_ALL_BANKS; + bank_clr_all = 1'b1; + tmr_ld_trp = 1'b1; + if(cmd_asserted) next_state = SUSP2; + end + + SUSP2: + begin + if(tmr_done) next_state = SUSP3; + end + + SUSP3: + begin // Enter Self refresh Mode + cke_d = 1'b0; + cmd = `MC_CMD_ARFR; + rfr_ack_d = 1'b1; + if(cmd_asserted) + begin + next_state = SUSP4; + end + end + + SUSP4: + begin // Now we are suspended + cke_rd = 1'b0; + suspended_d = 1'b1; + tmr_ld_txsr = 1'b1; + if(resume_req_r) next_state = RESUME1; + end + + RESUME1: + begin + suspended_d = 1'b1; + tmr_ld_txsr = 1'b1; + next_state = RESUME2; + end + + RESUME2: + begin + suspended_d = 1'b1; + if(tmr_done) next_state = REFR; + end + +// synopsys translate_off + default: + $display("MC_TIMING SM: Entered non existing state ... (%t)",$time); +// synopsys translate_on + + endcase + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_top.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_top.v new file mode 100644 index 000000000..3058e287a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_top.v @@ -0,0 +1,549 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_top.v,v 1.7 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_top.v,v $ +// Revision 1.7 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.6 2001/12/21 05:09:30 rudi +// +// - Fixed combinatorial loops in synthesis +// - Fixed byte select bug +// +// Revision 1.5 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.4 2001/09/10 13:44:17 rudi +// *** empty log message *** +// +// Revision 1.3 2001/09/02 02:28:28 rudi +// +// Many fixes for minor bugs that showed up in gate level simulations. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:39 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_top(clk_i, rst_i, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, + + susp_req_i, resume_req_i, suspended_o, poc_o, + + mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i, + mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i, + mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_, + mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_, + mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o, + mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o + ); + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE SLAVE INTERFACE +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// -------------------------------------- +// Suspend Resume Interface +input susp_req_i; +input resume_req_i; +output suspended_o; + +// POC +output [31:0] poc_o; + +// -------------------------------------- +// Memory Bus Signals +input mc_clk_i; +input mc_br_pad_i; +output mc_bg_pad_o; +input mc_ack_pad_i; +output [23:0] mc_addr_pad_o; +input [31:0] mc_data_pad_i; +output [31:0] mc_data_pad_o; +input [3:0] mc_dp_pad_i; +output [3:0] mc_dp_pad_o; +output mc_doe_pad_doe_o; +output [3:0] mc_dqm_pad_o; +output mc_oe_pad_o_; +output mc_we_pad_o_; +output mc_cas_pad_o_; +output mc_ras_pad_o_; +output mc_cke_pad_o_; +output [7:0] mc_cs_pad_o_; +input mc_sts_pad_i; +output mc_rp_pad_o_; +output mc_vpen_pad_o; +output mc_adsc_pad_o_; +output mc_adv_pad_o_; +output mc_zz_pad_o; +output mc_coe_pad_coe_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +// WISHBONE Interface Interconnects +wire wb_read_go; +wire wb_write_go; +wire wb_first; +wire wb_wait; +wire mem_ack; + +// Suspend Resume Interface +wire susp_sel; + +// Register File Interconnects +wire [31:0] rf_dout; +wire [31:0] csc; +wire [31:0] tms; +wire [31:0] sp_csc; +wire [31:0] sp_tms; +wire [7:0] cs; +wire fs; +wire cs_le; +wire [7:0] cs_need_rfr; +wire [2:0] ref_int; +wire [31:0] mem_dout; +wire wp_err; + +// Address Select Signals +wire [12:0] row_adr; +wire [1:0] bank_adr; +wire cmd_a10; +wire row_sel; +wire next_adr; +wire [10:0] page_size; +wire lmr_sel; +wire wr_hold; + +// OBCT Signals +wire bank_set; +wire bank_clr; +wire bank_clr_all; +wire bank_open; +wire row_same; +wire [7:0] obct_cs; +wire any_bank_open; + +// Data path Controller Signals +wire dv; +wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable +wire par_err; +wire [31:0] mc_data_od; +wire [3:0] mc_dp_od; +wire [23:0] mc_addr_d; +wire [35:0] mc_data_ir; + +// Refresh Counter Signals +wire rfr_req; +wire rfr_ack; +wire [7:0] rfr_ps_val; + +// Memory Timing Block Signals +wire data_oe; +wire oe_; +wire we_; +wire cas_; +wire ras_; +wire cke_; +wire lmr_req; +wire lmr_ack; +wire init_req; +wire init_ack; +wire [7:0] spec_req_cs; +wire cs_en; +wire wb_cycle, wr_cycle; +wire [31:0] tms_s; +wire [31:0] csc_s; +wire mc_c_oe_d; +wire mc_br_r; +wire mc_bg_d; +wire mc_adsc_d; +wire mc_adv_d; +wire mc_ack_r; +wire err; +wire mc_sts_i; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr : + (lmr_ack | init_ack) ? spec_req_cs : cs; + +assign lmr_sel = lmr_ack | init_ack; + +assign tms_s = lmr_sel ? sp_tms : tms; +assign csc_s = lmr_sel ? sp_csc : csc; + + +wire not_mem_cyc; + +assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL ); + +reg mem_ack_r; + +always @(posedge clk_i) + mem_ack_r <= #1 mem_ack; + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +mc_rf u0( + .clk( clk_i ), + .rst( rst_i ), + .wb_data_i( wb_data_i ), + .rf_dout( rf_dout ), + .wb_addr_i( wb_addr_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( ), + .wp_err( wp_err ), + .csc( csc ), + .tms( tms ), + .poc( poc_o ), + .sp_csc( sp_csc ), + .sp_tms( sp_tms ), + .cs( cs ), + .mc_data_i( mc_data_ir[31:0]), + .mc_sts( mc_sts_ir ), + .mc_vpen( mc_vpen_pad_o ), + .fs( fs ), + .cs_le( cs_le ), + .cs_le_d( cs_le_d ), + .cs_need_rfr( cs_need_rfr ), + .ref_int( ref_int ), + .rfr_ps_val( rfr_ps_val ), + .spec_req_cs( spec_req_cs ), + .init_req( init_req ), + .init_ack( init_ack ), + .lmr_req( lmr_req ), + .lmr_ack( lmr_ack ) + ); + +mc_adr_sel u1( + .clk( clk_i ), + .csc( csc_s ), + .tms( tms_s ), + .wb_stb_i( wb_stb_i ), + //.wb_ack_o( wb_ack_o ), + .wb_ack_o( mem_ack_r ), + .wb_addr_i( wb_addr_i ), + .wb_we_i( wb_we_i ), + .wb_write_go( wb_write_go ), + .wr_hold( wr_hold ), + .cas_( cas_ ), + .mc_addr( mc_addr_d ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .rfr_ack( rfr_ack ), + .cs_le( cs_le ), + .cmd_a10( cmd_a10 ), + .row_sel( row_sel ), + .lmr_sel( lmr_sel ), + .next_adr( next_adr ), + .wr_cycle( wr_cycle ), + .page_size( page_size ) + ); + +mc_obct_top u2( + .clk( clk_i ), + .rst( rst_i ), + .cs( obct_cs ), + .row_adr( row_adr ), + .bank_adr( bank_adr ), + .bank_set( bank_set ), + .bank_clr( bank_clr ), + .bank_clr_all( bank_clr_all ), + .bank_open( bank_open ), + .any_bank_open( any_bank_open ), + .row_same( row_same ), + .rfr_ack( rfr_ack ) + ); + +mc_dp u3( + .clk( clk_i ), + .rst( rst_i ), + .csc( csc ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .mem_ack( mem_ack ), + //.wb_ack_o( wb_ack_o ), + .wb_ack_o( mem_ack_r ), + .wb_we_i( wb_we_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( mem_dout ), + .wb_read_go( wb_read_go ), + .mc_clk( mc_clk_i ), + .mc_data_del( mc_data_ir ), + .mc_dp_i( mc_dp_pad_i ), + .mc_data_o( mc_data_od ), + .mc_dp_o( mc_dp_od ), + .dv( dv ), + .pack_le0( pack_le0 ), + .pack_le1( pack_le1 ), + .pack_le2( pack_le2 ), + .byte_en( wb_sel_i ), + .par_err( par_err ) + ); + +mc_refresh u4( + .clk( clk_i ), + .rst( rst_i ), + .cs_need_rfr( cs_need_rfr ), + .ref_int( ref_int ), + .rfr_req( rfr_req ), + .rfr_ack( rfr_ack ), + .rfr_ps_val( rfr_ps_val ) + ); + +mc_timing u5( + .clk( clk_i ), + .mc_clk( mc_clk_i ), + .rst( rst_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_we_i( wb_we_i ), + .wb_read_go( wb_read_go ), + .wb_write_go( wb_write_go ), + .wb_first( wb_first ), + .wb_wait( wb_wait ), + .mem_ack( mem_ack ), + .err( err ), + .susp_req( susp_req_i ), + .resume_req( resume_req_i ), + .suspended( suspended_o ), + .susp_sel( susp_sel ), + .mc_br( mc_br_r ), + .mc_bg( mc_bg_d ), + .mc_ack( mc_ack_r ), + .not_mem_cyc( not_mem_cyc ), + .data_oe( data_oe ), + .oe_( oe_ ), + .we_( we_ ), + .cas_( cas_ ), + .ras_( ras_ ), + .cke_( cke_ ), + .cs_en( cs_en ), + .mc_adsc( mc_adsc_d ), + .mc_adv( mc_adv_d ), + .mc_c_oe( mc_c_oe_d ), + .wb_cycle( wb_cycle ), + .wr_cycle( wr_cycle ), + .csc( csc_s ), + .tms( tms_s ), + .cs( obct_cs ), + .lmr_req( lmr_req ), + .lmr_ack( lmr_ack ), + .cs_le( cs_le ), + .cs_le_d( cs_le_d ), + .cmd_a10( cmd_a10 ), + .row_sel( row_sel ), + .next_adr( next_adr ), + .page_size( page_size ), + .bank_set( bank_set ), + .bank_clr( bank_clr ), + .bank_clr_all( bank_clr_all ), + .bank_open( bank_open ), + .any_bank_open( any_bank_open ), + .row_same( row_same ), + .dv( dv ), + .pack_le0( pack_le0 ), + .pack_le1( pack_le1 ), + .pack_le2( pack_le2 ), + .par_err( par_err ), + .rfr_req( rfr_req ), + .rfr_ack( rfr_ack ), + .init_req( init_req ), + .init_ack( init_ack ) + ); + +mc_wb_if u6( + .clk( clk_i ), + .rst( rst_i ), + .wb_addr_i( wb_addr_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_we_i( wb_we_i ), + .wb_ack_o( wb_ack_o ), + .wb_err( wb_err_o ), + .wb_read_go( wb_read_go ), + .wb_write_go( wb_write_go ), + .wb_first( wb_first ), + .wb_wait( wb_wait ), + .mem_ack( mem_ack ), + .wr_hold( wr_hold ), + .err( err ), + .par_err( par_err ), + .wp_err( wp_err ), + .wb_data_o( wb_data_o ), + .mem_dout( mem_dout ), + .rf_dout( rf_dout ) + ); + +mc_mem_if u7( + .clk( clk_i ), + .rst( rst_i ), + .mc_rp( mc_rp_pad_o_ ), + .mc_clk( mc_clk_i ), + .mc_br( mc_br_pad_i ), + .mc_bg( mc_bg_pad_o ), + .mc_addr( mc_addr_pad_o ), + .mc_data_o( mc_data_pad_o ), + .mc_dp_o( mc_dp_pad_o ), + .mc_data_oe( mc_doe_pad_doe_o), + .mc_dqm( mc_dqm_pad_o ), + .mc_oe_( mc_oe_pad_o_ ), + .mc_we_( mc_we_pad_o_ ), + .mc_cas_( mc_cas_pad_o_ ), + .mc_ras_( mc_ras_pad_o_ ), + .mc_cke_( mc_cke_pad_o_ ), + .mc_cs_( mc_cs_pad_o_ ), + .mc_adsc_( mc_adsc_pad_o_ ), + .mc_adv_( mc_adv_pad_o_ ), + .mc_br_r( mc_br_r ), + .mc_bg_d( mc_bg_d ), + .mc_data_od( mc_data_od ), + .mc_dp_od( mc_dp_od ), + .mc_addr_d( mc_addr_d ), + .mc_ack( mc_ack_pad_i ), + .mc_zz_o( mc_zz_pad_o ), + .we_( we_ ), + .ras_( ras_ ), + .cas_( cas_ ), + .cke_( cke_ ), + .mc_adsc_d( mc_adsc_d ), + .mc_adv_d( mc_adv_d ), + .cs_en( cs_en ), + .rfr_ack( rfr_ack ), + .cs_need_rfr( cs_need_rfr ), + .lmr_sel( lmr_sel ), + .spec_req_cs( spec_req_cs ), + .cs( cs ), + .fs( fs ), + .data_oe( data_oe ), + .susp_sel( susp_sel ), + .suspended_o( suspended_o ), + .mc_c_oe( mc_coe_pad_coe_o), + .mc_c_oe_d( mc_c_oe_d ), + .mc_ack_r( mc_ack_r ), + .oe_( oe_ ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_sel_i( wb_sel_i ), + .wb_cycle( wb_cycle ), + .wr_cycle( wr_cycle ), + .mc_data_i( mc_data_pad_i ), + .mc_dp_i( mc_dp_pad_i ), + .mc_data_ir( mc_data_ir ), + .mc_sts_i( mc_sts_pad_i ), + .mc_sts_ir( mc_sts_ir ) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_wb_if.v b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_wb_if.v new file mode 100644 index 000000000..3d58f3a89 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/mc_wb_if.v @@ -0,0 +1,252 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Memory Controller //// +//// WISHBONE Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: mc_wb_if.v,v 1.6 2002/01/21 13:08:52 rudi Exp $ +// +// $Date: 2002/01/21 13:08:52 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: mc_wb_if.v,v $ +// Revision 1.6 2002/01/21 13:08:52 rudi +// +// Fixed several minor bugs, cleaned up the code further ... +// +// Revision 1.5 2001/12/11 02:47:19 rudi +// +// - Made some changes not to expect clock during reset ... +// +// Revision 1.4 2001/11/29 02:16:28 rudi +// +// +// - More Synthesis cleanup, mostly for speed +// - Several bug fixes +// - Changed code to avoid auto-precharge and +// burst-terminate combinations (apparently illegal ?) +// Now we will do a manual precharge ... +// +// Revision 1.3 2001/09/24 00:38:21 rudi +// +// Changed Reset to be active high and async. +// +// Revision 1.2 2001/08/10 08:16:21 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Removed "Refresh Early" configuration +// +// Revision 1.1 2001/07/29 07:34:41 rudi +// +// +// 1) Changed Directory Structure +// 2) Fixed several minor bugs +// +// Revision 1.3 2001/06/12 15:19:49 rudi +// +// +// Minor changes after running lint, and a small bug +// fix reading csr and ba_mask registers. +// +// Revision 1.2 2001/06/03 11:37:17 rudi +// +// +// 1) Fixed Chip Select Mask Register +// - Power On Value is now all ones +// - Comparison Logic is now correct +// +// 2) All resets are now asynchronous +// +// 3) Converted Power On Delay to an configurable item +// +// 4) Added reset to Chip Select Output Registers +// +// 5) Forcing all outputs to Hi-Z state during reset +// +// Revision 1.1.1.1 2001/05/13 09:39:47 rudi +// Created Directory Structure +// +// +// +// + +`include "mc_defines.v" + +module mc_wb_if(clk, rst, + wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o, + wb_read_go, wb_write_go, + wb_first, wb_wait, mem_ack, wr_hold, + err, par_err, wp_err, + wb_data_o, mem_dout, rf_dout); + +input clk, rst; +input [31:0] wb_addr_i; +input wb_cyc_i; +input wb_stb_i; +input wb_we_i; +output wb_err; +output wb_ack_o; +output wb_read_go; +output wb_write_go; +output wb_first; +output wb_wait; +input mem_ack; +output wr_hold; +input err, par_err, wp_err; +output [31:0] wb_data_o; +input [31:0] mem_dout, rf_dout; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire mem_sel; +reg read_go_r; +reg read_go_r1; +reg write_go_r; +reg write_go_r1; +reg wb_first_r; +wire wb_first_set; +reg wr_hold; +wire rmw; +reg rmw_r; +reg rmw_en; +reg wb_ack_o; +reg wb_err; +reg [31:0] wb_data_o; + +//////////////////////////////////////////////////////////////////// +// +// Memory Go Logic +// + +assign mem_sel = `MC_MEM_SEL; + +always @(posedge clk or posedge rst) + if(rst) rmw_en <= #1 1'b0; + else + if(wb_ack_o) rmw_en <= #1 1'b1; + else + if(!wb_cyc_i) rmw_en <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) rmw_r <= #1 1'b0; + else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en; + +assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en); + +always @(posedge clk or posedge rst) + if(rst) read_go_r1 <= #1 1'b0; + else read_go_r1 <= #1 !rmw & wb_cyc_i & + ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r); + +always @(posedge clk or posedge rst) + if(rst) read_go_r <= #1 1'b0; + else read_go_r <= #1 read_go_r1 & wb_cyc_i; + +assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i; + +always @(posedge clk or posedge rst) + if(rst) write_go_r1 <= #1 1'b0; + else write_go_r1 <= #1 wb_cyc_i & + ((wb_stb_i & mem_sel & wb_we_i) | write_go_r); + +always @(posedge clk or posedge rst) + if(rst) write_go_r <= #1 1'b0; + else write_go_r <= #1 write_go_r1 & wb_cyc_i & + ((wb_we_i & wb_stb_i) | !wb_stb_i); + +assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i & + ((wb_we_i & wb_stb_i) | !wb_stb_i); + +assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r); +assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err); + +always @(posedge clk or posedge rst) + if(rst) wb_first_r <= #1 1'b0; + else + if(wb_first_set) wb_first_r <= #1 1'b1; + else + if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0; + +always @(posedge clk or posedge rst) + if(rst) wr_hold <= #1 1'b0; + else + if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i; + +//////////////////////////////////////////////////////////////////// +// +// WB Ack +// + +wire wb_err_d; + +// Ack no longer asserted when wb_err is asserted +always @(posedge clk or posedge rst) + if(rst) wb_ack_o <= #1 1'b0; + else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d : + `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; + +assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err); + +always @(posedge clk or posedge rst) + if(rst) wb_err <= #1 1'b0; + else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err; + +//////////////////////////////////////////////////////////////////// +// +// Memory Wait Logic +// + +assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go); + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Data Output +// + +always @(posedge clk) + wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/bus_commands.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/bus_commands.v new file mode 100644 index 000000000..b96ac9178 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/bus_commands.v @@ -0,0 +1,80 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "bus_commands.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README.pdf //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: bus_commands.v,v $ +// Revision 1.4 2002/08/22 13:28:05 mihad +// Updated for synthesis purposes. Gate level simulation was failing in some configurations +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// definitions of PCI bus commands | used by PCI Master | used by PCI Target +`define BC_IACK 4'h0 // yes no +`define BC_SPECIAL 4'h1 // no no +`define BC_IO_READ 4'h2 // yes yes +`define BC_IO_WRITE 4'h3 // yes yes +`define BC_RESERVED0 4'h4 // no no +`define BC_RESERVED1 4'h5 // no no +`define BC_MEM_READ 4'h6 // yes yes +`define BC_MEM_WRITE 4'h7 // yes yes +`define BC_RESERVED2 4'h8 // no no +`define BC_RESERVED3 4'h9 // no no +`define BC_CONF_READ 4'hA // yes yes +`define BC_CONF_WRITE 4'hB // yes yes +`define BC_MEM_READ_MUL 4'hC // yes yes +`define BC_DUAL_ADDR_CYC 4'hD // no no +`define BC_MEM_READ_LN 4'hE // yes yes +`define BC_MEM_WRITE_INVAL 4'hF // no yes + +// common bits for configuration cycle commands +`define BC_CONF_RW 3'b101 +// common bits for io cycle commands +`define BC_IO_RW 3'b001 diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_async_reset_flop.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_async_reset_flop.v new file mode 100644 index 000000000..86027e62f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_async_reset_flop.v @@ -0,0 +1,102 @@ +//=========================================================================== +// $Id: pci_async_reset_flop.v,v 1.1 2003/01/27 16:49:31 mihad Exp $ +// +////////////////////////////////////////////////////////////////////// +//// //// +//// async_reset_flop //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// Make a rising-edge triggered flop with async reset with a //// +//// distinguished name so that it's output can be easily //// +//// traced, because it is used for asynchronous reset of some //// +//// flip-flops. //// +//// //// +//// This flop should be used instead of a regular flop for ALL //// +//// asynchronous-reset generator flops. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_async_reset_flop.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/08/14 16:44:19 mihad +// Include statement was enclosed in synosys translate off/on directive - repaired +// +// Revision 1.2 2002/02/25 15:15:43 mihad +// Added include statement that was missing and causing errors +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "pci_constants.v" + +module pci_async_reset_flop ( + data_in, clk_in, async_reset_data_out, reset_in +); + +input data_in; +input clk_in; +output async_reset_data_out; +input reset_in; + +reg async_reset_data_out; + +always @(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + async_reset_data_out <= #`FF_DELAY 1'b0; + end + else + begin + async_reset_data_out <= #`FF_DELAY data_in; + end +end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_bridge32.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_bridge32.v new file mode 100644 index 000000000..bba700a8e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_bridge32.v @@ -0,0 +1,1653 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_bridge32.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// - Tadej Markovic (tadej@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_bridge32.v,v $ +// Revision 1.19 2004/09/23 13:48:53 mihad +// The control inputs from PCI are now muxed with control outputs +// using output enable state for given signal. +// +// Revision 1.18 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.17 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.16 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.15 2003/12/10 12:02:54 mihad +// The wbs B3 to B2 translation logic had wrong reset wire connected! +// +// Revision 1.14 2003/12/09 09:33:57 simons +// Some warning cleanup. +// +// Revision 1.13 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.12 2003/08/21 20:49:03 tadejm +// Added signals for WB Master B3. +// +// Revision 1.11 2003/08/08 16:36:33 tadejm +// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. +// +// Revision 1.10 2003/08/03 18:05:06 mihad +// Added limited WISHBONE B3 support for WISHBONE Slave Unit. +// Doesn't support full speed bursts yet. +// +// Revision 1.9 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.8 2002/10/21 13:04:33 mihad +// Changed BIST signal names etc.. +// +// Revision 1.7 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.6 2002/10/17 22:51:50 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.5 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.4 2002/10/08 17:17:05 mihad +// Added BIST signals for RAMs. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// this is top level module of pci bridge core +// it instantiates and connects other lower level modules +// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification + +module pci_bridge32 +( + // WISHBONE system signals + wb_clk_i, + wb_rst_i, + wb_rst_o, + wb_int_i, + wb_int_o, + + // WISHBONE slave interface + wbs_adr_i, + wbs_dat_i, + wbs_dat_o, + wbs_sel_i, + wbs_cyc_i, + wbs_stb_i, + wbs_we_i, + +`ifdef PCI_WB_REV_B3 + + wbs_cti_i, + wbs_bte_i, + +`else + + wbs_cab_i, + +`endif + + wbs_ack_o, + wbs_rty_o, + wbs_err_o, + + // WISHBONE master interface + wbm_adr_o, + wbm_dat_i, + wbm_dat_o, + wbm_sel_o, + wbm_cyc_o, + wbm_stb_o, + wbm_we_o, + wbm_cti_o, + wbm_bte_o, + wbm_ack_i, + wbm_rty_i, + wbm_err_i, + + // pci interface - system pins + pci_clk_i, + pci_rst_i, + pci_rst_o, + pci_inta_i, + pci_inta_o, + pci_rst_oe_o, + pci_inta_oe_o, + + // arbitration pins + pci_req_o, + pci_req_oe_o, + + pci_gnt_i, + + // protocol pins + pci_frame_i, + pci_frame_o, + + pci_frame_oe_o, + pci_irdy_oe_o, + pci_devsel_oe_o, + pci_trdy_oe_o, + pci_stop_oe_o, + pci_ad_oe_o, + pci_cbe_oe_o, + + pci_irdy_i, + pci_irdy_o, + + pci_idsel_i, + + pci_devsel_i, + pci_devsel_o, + + pci_trdy_i, + pci_trdy_o, + + pci_stop_i, + pci_stop_o , + + // data transfer pins + pci_ad_i, + pci_ad_o, + + pci_cbe_i, + pci_cbe_o, + + // parity generation and checking pins + pci_par_i, + pci_par_o, + pci_par_oe_o, + + pci_perr_i, + pci_perr_o, + pci_perr_oe_o, + + // system error pin + pci_serr_o, + pci_serr_oe_o + +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +`ifdef PCI_CPCI_HS_IMPLEMENT + , + // Compact PCI Hot Swap signals + pci_cpci_hs_enum_o , // ENUM# output with output enable (open drain) + pci_cpci_hs_enum_oe_o , // ENUM# enum output enable + pci_cpci_hs_led_o , // LED output with output enable (open drain) + pci_cpci_hs_led_oe_o , // LED output enable + pci_cpci_hs_es_i // ejector switch state indicator input +`endif + +`ifdef PCI_SPOCI + , + // Serial power on configuration interface + spoci_scl_o , + spoci_scl_oe_o , + spoci_sda_i , + spoci_sda_o , + spoci_sda_oe_o +`endif + +); + +`ifdef HOST + `ifdef NO_CNF_IMAGE + parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + `else + parameter pci_ba0_width = 20 ; + `endif +`endif + +`ifdef GUEST + parameter pci_ba0_width = 20 ; +`endif + +parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + +// WISHBONE system signals +input wb_clk_i ; +input wb_rst_i ; +output wb_rst_o ; +input wb_int_i ; +output wb_int_o ; + +// WISHBONE slave interface +input [31:0] wbs_adr_i ; +input [31:0] wbs_dat_i ; +output [31:0] wbs_dat_o ; +input [3:0] wbs_sel_i ; +input wbs_cyc_i ; +input wbs_stb_i ; +input wbs_we_i ; + +`ifdef PCI_WB_REV_B3 + +input [2:0] wbs_cti_i ; +input [1:0] wbs_bte_i ; + +`else + +input wbs_cab_i ; + +`endif + +output wbs_ack_o ; +output wbs_rty_o ; +output wbs_err_o ; + +// WISHBONE master interface +output [31:0] wbm_adr_o ; +input [31:0] wbm_dat_i ; +output [31:0] wbm_dat_o ; +output [3:0] wbm_sel_o ; +output wbm_cyc_o ; +output wbm_stb_o ; +output wbm_we_o ; +output [2:0] wbm_cti_o ; +output [1:0] wbm_bte_o ; +input wbm_ack_i ; +input wbm_rty_i ; +input wbm_err_i ; + +// pci interface - system pins +input pci_clk_i ; +input pci_rst_i ; +output pci_rst_o ; +output pci_rst_oe_o ; + +input pci_inta_i ; +output pci_inta_o ; +output pci_inta_oe_o ; + +// arbitration pins +output pci_req_o ; +output pci_req_oe_o ; + +input pci_gnt_i ; + +// protocol pins +input pci_frame_i ; +output pci_frame_o ; +output pci_frame_oe_o ; +output pci_irdy_oe_o ; +output pci_devsel_oe_o ; +output pci_trdy_oe_o ; +output pci_stop_oe_o ; +output [31:0] pci_ad_oe_o ; +output [3:0] pci_cbe_oe_o ; + +input pci_irdy_i ; +output pci_irdy_o ; + +input pci_idsel_i ; + +input pci_devsel_i ; +output pci_devsel_o ; + +input pci_trdy_i ; +output pci_trdy_o ; + +input pci_stop_i ; +output pci_stop_o ; + +// data transfer pins +input [31:0] pci_ad_i ; +output [31:0] pci_ad_o ; + +input [3:0] pci_cbe_i ; +output [3:0] pci_cbe_o ; + +// parity generation and checking pins +input pci_par_i ; +output pci_par_o ; +output pci_par_oe_o ; + +input pci_perr_i ; +output pci_perr_o ; +output pci_perr_oe_o ; + +// system error pin +output pci_serr_o ; +output pci_serr_oe_o ; + +`ifdef PCI_BIST +/*----------------------------------------------------- +BIST debug chain port signals +-----------------------------------------------------*/ +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +`ifdef PCI_CPCI_HS_IMPLEMENT + // Compact PCI Hot Swap signals +output pci_cpci_hs_enum_o ; // ENUM# output with output enable (open drain) +output pci_cpci_hs_enum_oe_o ; // ENUM# enum output enable +output pci_cpci_hs_led_o ; // LED output with output enable (open drain) +output pci_cpci_hs_led_oe_o ; // LED output enable +input pci_cpci_hs_es_i ; // ejector switch state indicator input + +assign pci_cpci_hs_enum_o = 1'b0 ; +assign pci_cpci_hs_led_o = 1'b0 ; +`endif + +`ifdef PCI_SPOCI +output spoci_scl_o ; +output spoci_scl_oe_o ; +input spoci_sda_i ; +output spoci_sda_o ; +output spoci_sda_oe_o ; + +assign spoci_scl_o = 1'b0 ; +assign spoci_sda_o = 1'b0 ; +`endif + +// declare clock and reset wires +wire pci_clk = pci_clk_i ; +wire wb_clk = wb_clk_i ; +wire reset ; // assigned at pci bridge reset and interrupt logic + +/*========================================================================================================= +First comes definition of all modules' outputs, so they can be assigned to any other module's input later + in the file, when module is instantiated +=========================================================================================================*/ +// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS +wire pci_reso_reset ; +wire pci_reso_pci_rstn_out ; +wire pci_reso_pci_rstn_en_out ; +wire pci_reso_rst_o ; +wire pci_into_pci_intan_out ; +wire pci_into_pci_intan_en_out ; +wire pci_into_int_o ; +wire pci_into_conf_isr_int_prop_out ; + +// assign pci bridge reset interrupt logic outputs to top outputs where possible +assign reset = pci_reso_reset ; +assign pci_rst_o = pci_reso_pci_rstn_out ; +assign pci_rst_oe_o = pci_reso_pci_rstn_en_out ; +assign wb_rst_o = pci_reso_rst_o ; +assign pci_inta_o = pci_into_pci_intan_out ; +assign pci_inta_oe_o = pci_into_pci_intan_en_out ; +assign wb_int_o = pci_into_int_o ; + +// WISHBONE SLAVE UNIT OUTPUTS +wire [31:0] wbu_sdata_out ; +wire wbu_ack_out ; +wire wbu_rty_out ; +wire wbu_err_out ; +wire wbu_pciif_req_out ; +wire wbu_pciif_frame_out ; +wire wbu_pciif_frame_en_out ; +wire wbu_pciif_irdy_out ; +wire wbu_pciif_irdy_en_out ; +wire [31:0] wbu_pciif_ad_out ; +wire wbu_pciif_ad_en_out ; +wire [3:0] wbu_pciif_cbe_out ; +wire wbu_pciif_cbe_en_out ; +wire [31:0] wbu_err_addr_out ; +wire [3:0] wbu_err_bc_out ; +wire wbu_err_signal_out ; +wire wbu_err_source_out ; +wire wbu_err_rty_exp_out ; +wire wbu_tabort_rec_out ; +wire wbu_mabort_rec_out ; +wire [11:0] wbu_conf_offset_out ; +wire wbu_conf_renable_out ; +wire wbu_conf_wenable_out ; +wire [3:0] wbu_conf_be_out ; +wire [31:0] wbu_conf_data_out ; +wire wbu_del_read_comp_pending_out ; +wire wbu_wbw_fifo_empty_out ; +wire wbu_ad_load_out ; +wire wbu_ad_load_on_transfer_out ; +wire wbu_pciif_frame_load_out ; + +// PCI TARGET UNIT OUTPUTS +wire [31:0] pciu_adr_out ; +wire [31:0] pciu_mdata_out ; +wire pciu_cyc_out ; +wire pciu_stb_out ; +wire pciu_we_out ; +wire [2:0] pciu_cti_out ; +wire [1:0] pciu_bte_out ; +wire [3:0] pciu_sel_out ; +wire pciu_pciif_trdy_out ; +wire pciu_pciif_stop_out ; +wire pciu_pciif_devsel_out ; +wire pciu_pciif_trdy_en_out ; +wire pciu_pciif_stop_en_out ; +wire pciu_pciif_devsel_en_out ; +wire pciu_ad_load_out ; +wire pciu_ad_load_on_transfer_out ; +wire [31:0] pciu_pciif_ad_out ; +wire pciu_pciif_ad_en_out ; +wire pciu_pciif_tabort_set_out ; +wire [31:0] pciu_err_addr_out ; +wire [3:0] pciu_err_bc_out ; +wire [31:0] pciu_err_data_out ; +wire [3:0] pciu_err_be_out ; +wire pciu_err_signal_out ; +wire pciu_err_source_out ; +wire pciu_err_rty_exp_out ; +wire [11:0] pciu_conf_offset_out ; +wire pciu_conf_renable_out ; +wire pciu_conf_wenable_out ; +wire [3:0] pciu_conf_be_out ; +wire [31:0] pciu_conf_data_out ; +wire pciu_pci_drcomp_pending_out ; +wire pciu_pciw_fifo_empty_out ; + +// assign pci target unit's outputs to top outputs where possible +assign wbm_adr_o = pciu_adr_out ; +assign wbm_dat_o = pciu_mdata_out ; +assign wbm_cyc_o = pciu_cyc_out ; +assign wbm_stb_o = pciu_stb_out ; +assign wbm_we_o = pciu_we_out ; +assign wbm_cti_o = pciu_cti_out ; +assign wbm_bte_o = pciu_bte_out ; +assign wbm_sel_o = pciu_sel_out ; + +// CONFIGURATION SPACE OUTPUTS +wire [31:0] conf_w_data_out ; +wire [31:0] conf_r_data_out ; +wire conf_serr_enable_out ; +wire conf_perr_response_out ; +wire conf_pci_master_enable_out ; +wire conf_mem_space_enable_out ; +wire conf_io_space_enable_out ; +wire [7:0] conf_cache_line_size_to_pci_out ; +wire [7:0] conf_cache_line_size_to_wb_out ; +wire conf_cache_lsize_not_zero_to_wb_out ; +wire [7:0] conf_latency_tim_out ; + +wire [pci_ba0_width - 1:0] conf_pci_ba0_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ba1_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ba2_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ba3_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ba4_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ba5_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta0_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta1_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta2_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta3_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta4_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_ta5_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am0_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am1_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am2_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am3_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am4_out ; +wire [pci_ba1_5_width - 1:0] conf_pci_am5_out ; + +wire conf_pci_mem_io0_out ; +wire conf_pci_mem_io1_out ; +wire conf_pci_mem_io2_out ; +wire conf_pci_mem_io3_out ; +wire conf_pci_mem_io4_out ; +wire conf_pci_mem_io5_out ; + +wire [1:0] conf_pci_img_ctrl0_out ; +wire [1:0] conf_pci_img_ctrl1_out ; +wire [1:0] conf_pci_img_ctrl2_out ; +wire [1:0] conf_pci_img_ctrl3_out ; +wire [1:0] conf_pci_img_ctrl4_out ; +wire [1:0] conf_pci_img_ctrl5_out ; + +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba0_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba1_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba2_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba3_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba4_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba5_out ; + +wire conf_wb_mem_io0_out ; +wire conf_wb_mem_io1_out ; +wire conf_wb_mem_io2_out ; +wire conf_wb_mem_io3_out ; +wire conf_wb_mem_io4_out ; +wire conf_wb_mem_io5_out ; + +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am0_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am1_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am2_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am3_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am4_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am5_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta0_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta1_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta2_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta3_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta4_out ; +wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta5_out ; +wire [2:0] conf_wb_img_ctrl0_out ; +wire [2:0] conf_wb_img_ctrl1_out ; +wire [2:0] conf_wb_img_ctrl2_out ; +wire [2:0] conf_wb_img_ctrl3_out ; +wire [2:0] conf_wb_img_ctrl4_out ; +wire [2:0] conf_wb_img_ctrl5_out ; +wire [23:0] conf_ccyc_addr_out ; +wire conf_soft_res_out ; +wire conf_int_out ; +wire conf_wb_init_complete_out ; +wire conf_pci_init_complete_out ; + +// PCI IO MUX OUTPUTS +wire pci_mux_frame_out ; +wire pci_mux_irdy_out ; +wire pci_mux_devsel_out ; +wire pci_mux_trdy_out ; +wire pci_mux_stop_out ; +wire [3:0] pci_mux_cbe_out ; +wire [31:0] pci_mux_ad_out ; +wire pci_mux_ad_load_out ; + +wire [31:0] pci_mux_ad_en_out ; +wire pci_mux_ad_en_unregistered_out ; +wire pci_mux_frame_en_out ; +wire pci_mux_irdy_en_out ; +wire pci_mux_devsel_en_out ; +wire pci_mux_trdy_en_out ; +wire pci_mux_stop_en_out ; +wire [3:0] pci_mux_cbe_en_out ; + +wire pci_mux_par_out ; +wire pci_mux_par_en_out ; +wire pci_mux_perr_out ; +wire pci_mux_perr_en_out ; +wire pci_mux_serr_out ; +wire pci_mux_serr_en_out ; + +wire pci_mux_req_out ; +wire pci_mux_req_en_out ; + +// assign outputs to top level outputs + +assign pci_ad_oe_o = pci_mux_ad_en_out ; +assign pci_frame_oe_o = pci_mux_frame_en_out ; +assign pci_irdy_oe_o = pci_mux_irdy_en_out ; +assign pci_cbe_oe_o = pci_mux_cbe_en_out ; + +assign pci_par_o = pci_mux_par_out ; +assign pci_par_oe_o = pci_mux_par_en_out ; +assign pci_perr_o = pci_mux_perr_out ; +assign pci_perr_oe_o = pci_mux_perr_en_out ; +assign pci_serr_o = pci_mux_serr_out ; +assign pci_serr_oe_o = pci_mux_serr_en_out ; + +assign pci_req_o = pci_mux_req_out ; +assign pci_req_oe_o = pci_mux_req_en_out ; + +assign pci_trdy_oe_o = pci_mux_trdy_en_out ; +assign pci_devsel_oe_o = pci_mux_devsel_en_out ; +assign pci_stop_oe_o = pci_mux_stop_en_out ; +assign pci_trdy_o = pci_mux_trdy_out ; +assign pci_devsel_o = pci_mux_devsel_out ; +assign pci_stop_o = pci_mux_stop_out ; + +assign pci_ad_o = pci_mux_ad_out ; +assign pci_frame_o = pci_mux_frame_out ; +assign pci_irdy_o = pci_mux_irdy_out ; +assign pci_cbe_o = pci_mux_cbe_out ; + +// duplicate output register's outputs +wire out_bckp_frame_out ; +wire out_bckp_irdy_out ; +wire out_bckp_devsel_out ; +wire out_bckp_trdy_out ; +wire out_bckp_stop_out ; +wire [3:0] out_bckp_cbe_out ; +wire out_bckp_cbe_en_out ; +wire [31:0] out_bckp_ad_out ; +wire out_bckp_ad_en_out ; +wire out_bckp_irdy_en_out ; +wire out_bckp_frame_en_out ; +wire out_bckp_tar_ad_en_out ; +wire out_bckp_mas_ad_en_out ; +wire out_bckp_trdy_en_out ; + +wire out_bckp_par_out ; +wire out_bckp_par_en_out ; +wire out_bckp_perr_out ; +wire out_bckp_perr_en_out ; +wire out_bckp_serr_out ; +wire out_bckp_serr_en_out ; + +wire int_pci_frame = out_bckp_frame_en_out ? out_bckp_frame_out : pci_frame_i ; +wire int_pci_irdy = out_bckp_irdy_en_out ? out_bckp_irdy_out : pci_irdy_i ; +wire int_pci_devsel = out_bckp_trdy_en_out ? out_bckp_devsel_out : pci_devsel_i ; +wire int_pci_trdy = out_bckp_trdy_en_out ? out_bckp_trdy_out : pci_trdy_i ; +wire int_pci_stop = out_bckp_trdy_en_out ? out_bckp_stop_out : pci_stop_i ; +wire [ 3: 0] int_pci_cbe = out_bckp_cbe_en_out ? out_bckp_cbe_out : pci_cbe_i ; +wire int_pci_par = out_bckp_par_en_out ? out_bckp_par_out : pci_par_i ; +wire int_pci_perr = out_bckp_perr_en_out ? out_bckp_perr_out : pci_perr_i ; +// PARITY CHECKER OUTPUTS +wire parchk_pci_par_out ; +wire parchk_pci_par_en_out ; +wire parchk_pci_perr_out ; +wire parchk_pci_perr_en_out ; +wire parchk_pci_serr_out ; +wire parchk_pci_serr_en_out ; +wire parchk_par_err_detect_out ; +wire parchk_perr_mas_detect_out ; +wire parchk_sig_serr_out ; + +// input register outputs +wire in_reg_gnt_out ; +wire in_reg_frame_out ; +wire in_reg_irdy_out ; +wire in_reg_trdy_out ; +wire in_reg_stop_out ; +wire in_reg_devsel_out ; +wire in_reg_idsel_out ; +wire [31:0] in_reg_ad_out ; +wire [3:0] in_reg_cbe_out ; + +/*========================================================================================================= +Now comes definition of all modules' and their appropriate inputs +=========================================================================================================*/ +// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS +wire pci_resi_rst_i = wb_rst_i ; +wire pci_resi_pci_rstn_in = pci_rst_i ; +wire pci_resi_conf_soft_res_in = conf_soft_res_out ; +wire pci_inti_pci_intan_in = pci_inta_i ; +wire pci_inti_conf_int_in = conf_int_out ; +wire pci_inti_int_i = wb_int_i ; +wire pci_into_init_complete_in = conf_pci_init_complete_out ; + +pci_rst_int pci_resets_and_interrupts +( + .clk_in (pci_clk), + .rst_i (pci_resi_rst_i), + .pci_rstn_in (pci_resi_pci_rstn_in), + .conf_soft_res_in (pci_resi_conf_soft_res_in), + .reset (pci_reso_reset), + .pci_rstn_out (pci_reso_pci_rstn_out), + .pci_rstn_en_out (pci_reso_pci_rstn_en_out), + .rst_o (pci_reso_rst_o), + .pci_intan_in (pci_inti_pci_intan_in), + .conf_int_in (pci_inti_conf_int_in), + .int_i (pci_inti_int_i), + .pci_intan_out (pci_into_pci_intan_out), + .pci_intan_en_out (pci_into_pci_intan_en_out), + .int_o (pci_into_int_o), + .conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out), + .init_complete_in (pci_into_init_complete_in) +); + + +`ifdef PCI_WB_REV_B3 + +wire wbs_wbb3_2_wbb2_cyc_o ; +wire wbs_wbb3_2_wbb2_stb_o ; +wire [31:0] wbs_wbb3_2_wbb2_adr_o ; +wire [31:0] wbs_wbb3_2_wbb2_dat_i_o ; +wire [31:0] wbs_wbb3_2_wbb2_dat_o_o ; +wire wbs_wbb3_2_wbb2_we_o ; +wire [ 3:0] wbs_wbb3_2_wbb2_sel_o ; +wire wbs_wbb3_2_wbb2_ack_o ; +wire wbs_wbb3_2_wbb2_err_o ; +wire wbs_wbb3_2_wbb2_rty_o ; +wire wbs_wbb3_2_wbb2_cab_o ; + +// assign wishbone slave unit's outputs to top outputs where possible +assign wbs_dat_o = wbs_wbb3_2_wbb2_dat_o_o ; +assign wbs_ack_o = wbs_wbb3_2_wbb2_ack_o ; +assign wbs_rty_o = wbs_wbb3_2_wbb2_rty_o ; +assign wbs_err_o = wbs_wbb3_2_wbb2_err_o ; + +wire wbs_wbb3_2_wbb2_cyc_i = wbs_cyc_i ; +wire wbs_wbb3_2_wbb2_stb_i = wbs_stb_i ; +wire wbs_wbb3_2_wbb2_we_i = wbs_we_i ; +wire wbs_wbb3_2_wbb2_ack_i = wbu_ack_out ; +wire wbs_wbb3_2_wbb2_err_i = wbu_err_out ; +wire wbs_wbb3_2_wbb2_rty_i = wbu_rty_out ; +wire [31:0] wbs_wbb3_2_wbb2_adr_i = wbs_adr_i ; +wire [ 3:0] wbs_wbb3_2_wbb2_sel_i = wbs_sel_i ; +wire [31:0] wbs_wbb3_2_wbb2_dat_i_i = wbs_dat_i ; +wire [31:0] wbs_wbb3_2_wbb2_dat_o_i = wbu_sdata_out ; +wire [ 2:0] wbs_wbb3_2_wbb2_cti_i = wbs_cti_i ; +wire [ 1:0] wbs_wbb3_2_wbb2_bte_i = wbs_bte_i ; + +pci_wbs_wbb3_2_wbb2 i_pci_wbs_wbb3_2_wbb2 +( + .wb_clk_i ( wb_clk_i ) , + .wb_rst_i ( reset ) , + + .wbs_cyc_i ( wbs_wbb3_2_wbb2_cyc_i ) , + .wbs_cyc_o ( wbs_wbb3_2_wbb2_cyc_o ) , + .wbs_stb_i ( wbs_wbb3_2_wbb2_stb_i ) , + .wbs_stb_o ( wbs_wbb3_2_wbb2_stb_o ) , + .wbs_adr_i ( wbs_wbb3_2_wbb2_adr_i ) , + .wbs_adr_o ( wbs_wbb3_2_wbb2_adr_o ) , + .wbs_dat_i_i ( wbs_wbb3_2_wbb2_dat_i_i ) , + .wbs_dat_i_o ( wbs_wbb3_2_wbb2_dat_i_o ) , + .wbs_dat_o_i ( wbs_wbb3_2_wbb2_dat_o_i ) , + .wbs_dat_o_o ( wbs_wbb3_2_wbb2_dat_o_o ) , + .wbs_we_i ( wbs_wbb3_2_wbb2_we_i ) , + .wbs_we_o ( wbs_wbb3_2_wbb2_we_o ) , + .wbs_sel_i ( wbs_wbb3_2_wbb2_sel_i ) , + .wbs_sel_o ( wbs_wbb3_2_wbb2_sel_o ) , + .wbs_ack_i ( wbs_wbb3_2_wbb2_ack_i ) , + .wbs_ack_o ( wbs_wbb3_2_wbb2_ack_o ) , + .wbs_err_i ( wbs_wbb3_2_wbb2_err_i ) , + .wbs_err_o ( wbs_wbb3_2_wbb2_err_o ) , + .wbs_rty_i ( wbs_wbb3_2_wbb2_rty_i ) , + .wbs_rty_o ( wbs_wbb3_2_wbb2_rty_o ) , + .wbs_cti_i ( wbs_wbb3_2_wbb2_cti_i ) , + .wbs_bte_i ( wbs_wbb3_2_wbb2_bte_i ) , + .wbs_cab_o ( wbs_wbb3_2_wbb2_cab_o ) , + .wb_init_complete_i ( conf_wb_init_complete_out ) +) ; + +// WISHBONE SLAVE UNIT INPUTS +wire [31:0] wbu_addr_in = wbs_wbb3_2_wbb2_adr_o ; +wire [31:0] wbu_sdata_in = wbs_wbb3_2_wbb2_dat_i_o ; +wire wbu_cyc_in = wbs_wbb3_2_wbb2_cyc_o ; +wire wbu_stb_in = wbs_wbb3_2_wbb2_stb_o ; +wire wbu_we_in = wbs_wbb3_2_wbb2_we_o ; +wire [3:0] wbu_sel_in = wbs_wbb3_2_wbb2_sel_o ; +wire wbu_cab_in = wbs_wbb3_2_wbb2_cab_o ; + +`else + +// WISHBONE SLAVE UNIT INPUTS +wire [31:0] wbu_addr_in = wbs_adr_i ; +wire [31:0] wbu_sdata_in = wbs_dat_i ; +wire wbu_cyc_in = wbs_cyc_i ; +wire wbu_stb_in = wbs_stb_i ; +wire wbu_we_in = wbs_we_i ; +wire [3:0] wbu_sel_in = wbs_sel_i ; +wire wbu_cab_in = wbs_cab_i ; + +// assign wishbone slave unit's outputs to top outputs where possible +assign wbs_dat_o = wbu_sdata_out ; +assign wbs_ack_o = wbu_ack_out ; +assign wbs_rty_o = wbu_rty_out ; +assign wbs_err_o = wbu_err_out ; + +`endif + +wire [5:0] wbu_map_in = { + conf_wb_mem_io5_out, + conf_wb_mem_io4_out, + conf_wb_mem_io3_out, + conf_wb_mem_io2_out, + conf_wb_mem_io1_out, + conf_wb_mem_io0_out + } ; + +wire [5:0] wbu_pref_en_in = { + conf_wb_img_ctrl5_out[1], + conf_wb_img_ctrl4_out[1], + conf_wb_img_ctrl3_out[1], + conf_wb_img_ctrl2_out[1], + conf_wb_img_ctrl1_out[1], + conf_wb_img_ctrl0_out[1] + }; +wire [5:0] wbu_mrl_en_in = { + conf_wb_img_ctrl5_out[0], + conf_wb_img_ctrl4_out[0], + conf_wb_img_ctrl3_out[0], + conf_wb_img_ctrl2_out[0], + conf_wb_img_ctrl1_out[0], + conf_wb_img_ctrl0_out[0] + }; + +wire [5:0] wbu_at_en_in = { + conf_wb_img_ctrl5_out[2], + conf_wb_img_ctrl4_out[2], + conf_wb_img_ctrl3_out[2], + conf_wb_img_ctrl2_out[2], + conf_wb_img_ctrl1_out[2], + conf_wb_img_ctrl0_out[2] + } ; + +wire wbu_pci_drcomp_pending_in = pciu_pci_drcomp_pending_out ; +wire wbu_pciw_empty_in = pciu_pciw_fifo_empty_out ; + +`ifdef HOST + wire [31:0] wbu_conf_data_in = conf_w_data_out ; +`else +`ifdef GUEST + wire [31:0] wbu_conf_data_in = conf_r_data_out ; +`endif +`endif + +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in = conf_wb_ba0_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in = conf_wb_ba1_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in = conf_wb_ba2_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in = conf_wb_ba3_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in = conf_wb_ba4_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in = conf_wb_ba5_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in = conf_wb_am0_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in = conf_wb_am1_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in = conf_wb_am2_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in = conf_wb_am3_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in = conf_wb_am4_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in = conf_wb_am5_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in = conf_wb_ta0_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in = conf_wb_ta1_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in = conf_wb_ta2_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in = conf_wb_ta3_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in = conf_wb_ta4_out ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in = conf_wb_ta5_out ; + +wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ; +wire wbu_master_enable_in = conf_pci_master_enable_out ; +wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ; +wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ; + +wire wbu_pciif_gnt_in = pci_gnt_i ; +wire wbu_pciif_frame_in = in_reg_frame_out ; +wire wbu_pciif_irdy_in = in_reg_irdy_out ; +wire wbu_pciif_trdy_in = int_pci_trdy ; +wire wbu_pciif_stop_in = int_pci_stop ; +wire wbu_pciif_devsel_in = int_pci_devsel ; +wire [31:0] wbu_pciif_ad_reg_in = in_reg_ad_out ; +wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ; +wire wbu_pciif_stop_reg_in = in_reg_stop_out ; +wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ; + + +wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ; + +wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ; +wire wbu_pciif_frame_out_in = out_bckp_frame_out ; +wire wbu_wb_init_complete_in = conf_wb_init_complete_out ; + +pci_wb_slave_unit wishbone_slave_unit +( + .reset_in (reset), + .wb_clock_in (wb_clk), + .pci_clock_in (pci_clk), + .ADDR_I (wbu_addr_in), + .SDATA_I (wbu_sdata_in), + .SDATA_O (wbu_sdata_out), + .CYC_I (wbu_cyc_in), + .STB_I (wbu_stb_in), + .WE_I (wbu_we_in), + .SEL_I (wbu_sel_in), + .ACK_O (wbu_ack_out), + .RTY_O (wbu_rty_out), + .ERR_O (wbu_err_out), + .CAB_I (wbu_cab_in), + .wbu_map_in (wbu_map_in), + .wbu_pref_en_in (wbu_pref_en_in), + .wbu_mrl_en_in (wbu_mrl_en_in), + .wbu_pci_drcomp_pending_in (wbu_pci_drcomp_pending_in), + .wbu_conf_data_in (wbu_conf_data_in), + .wbu_pciw_empty_in (wbu_pciw_empty_in), + .wbu_bar0_in (wbu_bar0_in), + .wbu_bar1_in (wbu_bar1_in), + .wbu_bar2_in (wbu_bar2_in), + .wbu_bar3_in (wbu_bar3_in), + .wbu_bar4_in (wbu_bar4_in), + .wbu_bar5_in (wbu_bar5_in), + .wbu_am0_in (wbu_am0_in), + .wbu_am1_in (wbu_am1_in), + .wbu_am2_in (wbu_am2_in), + .wbu_am3_in (wbu_am3_in), + .wbu_am4_in (wbu_am4_in), + .wbu_am5_in (wbu_am5_in), + .wbu_ta0_in (wbu_ta0_in), + .wbu_ta1_in (wbu_ta1_in), + .wbu_ta2_in (wbu_ta2_in), + .wbu_ta3_in (wbu_ta3_in), + .wbu_ta4_in (wbu_ta4_in), + .wbu_ta5_in (wbu_ta5_in), + .wbu_at_en_in (wbu_at_en_in), + .wbu_ccyc_addr_in (wbu_ccyc_addr_in), + .wbu_master_enable_in (wbu_master_enable_in), + .wb_init_complete_in (wbu_wb_init_complete_in), + .wbu_cache_line_size_not_zero (wbu_cache_line_size_not_zero), + .wbu_cache_line_size_in (wbu_cache_line_size_in), + .wbu_pciif_gnt_in (wbu_pciif_gnt_in), + .wbu_pciif_frame_in (wbu_pciif_frame_in), + .wbu_pciif_frame_en_in (wbu_pciif_frame_en_in), + .wbu_pciif_frame_out_in (wbu_pciif_frame_out_in), + .wbu_pciif_irdy_in (wbu_pciif_irdy_in), + .wbu_pciif_trdy_in (wbu_pciif_trdy_in), + .wbu_pciif_stop_in (wbu_pciif_stop_in), + .wbu_pciif_devsel_in (wbu_pciif_devsel_in), + .wbu_pciif_ad_reg_in (wbu_pciif_ad_reg_in), + .wbu_pciif_req_out (wbu_pciif_req_out), + .wbu_pciif_frame_out (wbu_pciif_frame_out), + .wbu_pciif_frame_en_out (wbu_pciif_frame_en_out), + .wbu_pciif_frame_load_out (wbu_pciif_frame_load_out), + .wbu_pciif_irdy_out (wbu_pciif_irdy_out), + .wbu_pciif_irdy_en_out (wbu_pciif_irdy_en_out), + .wbu_pciif_ad_out (wbu_pciif_ad_out), + .wbu_pciif_ad_en_out (wbu_pciif_ad_en_out), + .wbu_pciif_cbe_out (wbu_pciif_cbe_out), + .wbu_pciif_cbe_en_out (wbu_pciif_cbe_en_out), + .wbu_err_addr_out (wbu_err_addr_out), + .wbu_err_bc_out (wbu_err_bc_out), + .wbu_err_signal_out (wbu_err_signal_out), + .wbu_err_source_out (wbu_err_source_out), + .wbu_err_rty_exp_out (wbu_err_rty_exp_out), + .wbu_tabort_rec_out (wbu_tabort_rec_out), + .wbu_mabort_rec_out (wbu_mabort_rec_out), + .wbu_conf_offset_out (wbu_conf_offset_out), + .wbu_conf_renable_out (wbu_conf_renable_out), + .wbu_conf_wenable_out (wbu_conf_wenable_out), + .wbu_conf_be_out (wbu_conf_be_out), + .wbu_conf_data_out (wbu_conf_data_out), + .wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out), + .wbu_wbw_fifo_empty_out (wbu_wbw_fifo_empty_out), + .wbu_latency_tim_val_in (wbu_latency_tim_val_in), + .wbu_ad_load_out (wbu_ad_load_out), + .wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out), + .wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in), + .wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in), + .wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in) + +`ifdef PCI_BIST + , + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o_internal), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +); + +// PCI TARGET UNIT INPUTS +wire [31:0] pciu_mdata_in = wbm_dat_i ; +wire pciu_ack_in = wbm_ack_i ; +wire pciu_rty_in = wbm_rty_i ; +wire pciu_err_in = wbm_err_i ; + +wire [5:0] pciu_map_in = { + conf_pci_mem_io5_out, + conf_pci_mem_io4_out, + conf_pci_mem_io3_out, + conf_pci_mem_io2_out, + conf_pci_mem_io1_out, + conf_pci_mem_io0_out + } ; + +wire [5:0] pciu_pref_en_in = { + conf_pci_img_ctrl5_out[0], + conf_pci_img_ctrl4_out[0], + conf_pci_img_ctrl3_out[0], + conf_pci_img_ctrl2_out[0], + conf_pci_img_ctrl1_out[0], + conf_pci_img_ctrl0_out[0] + }; + +wire [5:0] pciu_at_en_in = { + conf_pci_img_ctrl5_out[1], + conf_pci_img_ctrl4_out[1], + conf_pci_img_ctrl3_out[1], + conf_pci_img_ctrl2_out[1], + conf_pci_img_ctrl1_out[1], + conf_pci_img_ctrl0_out[1] + } ; + +wire pciu_mem_enable_in = conf_mem_space_enable_out ; +wire pciu_io_enable_in = conf_io_space_enable_out ; + +wire pciu_wbw_fifo_empty_in = wbu_wbw_fifo_empty_out ; +wire pciu_wbu_del_read_comp_pending_in = wbu_del_read_comp_pending_out ; +wire pciu_wbu_frame_en_in = out_bckp_frame_en_out ; + +`ifdef HOST + wire [31:0] pciu_conf_data_in = conf_r_data_out ; +`else +`ifdef GUEST + wire [31:0] pciu_conf_data_in = conf_w_data_out ; +`endif +`endif + +wire [pci_ba0_width - 1:0] pciu_bar0_in = conf_pci_ba0_out ; +wire [pci_ba1_5_width - 1:0] pciu_bar1_in = conf_pci_ba1_out ; +wire [pci_ba1_5_width - 1:0] pciu_bar2_in = conf_pci_ba2_out ; +wire [pci_ba1_5_width - 1:0] pciu_bar3_in = conf_pci_ba3_out ; +wire [pci_ba1_5_width - 1:0] pciu_bar4_in = conf_pci_ba4_out ; +wire [pci_ba1_5_width - 1:0] pciu_bar5_in = conf_pci_ba5_out ; +wire [pci_ba1_5_width - 1:0] pciu_am0_in = conf_pci_am0_out ; +wire [pci_ba1_5_width - 1:0] pciu_am1_in = conf_pci_am1_out ; +wire [pci_ba1_5_width - 1:0] pciu_am2_in = conf_pci_am2_out ; +wire [pci_ba1_5_width - 1:0] pciu_am3_in = conf_pci_am3_out ; +wire [pci_ba1_5_width - 1:0] pciu_am4_in = conf_pci_am4_out ; +wire [pci_ba1_5_width - 1:0] pciu_am5_in = conf_pci_am5_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta0_in = conf_pci_ta0_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta1_in = conf_pci_ta1_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta2_in = conf_pci_ta2_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta3_in = conf_pci_ta3_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta4_in = conf_pci_ta4_out ; +wire [pci_ba1_5_width - 1:0] pciu_ta5_in = conf_pci_ta5_out ; + +wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ; +wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ; + +wire pciu_pciif_frame_in = int_pci_frame ; +wire pciu_pciif_irdy_in = int_pci_irdy ; +wire pciu_pciif_idsel_in = pci_idsel_i ; +wire pciu_pciif_frame_reg_in = in_reg_frame_out ; +wire pciu_pciif_irdy_reg_in = in_reg_irdy_out ; +wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ; +wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ; +wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ; +wire [3:0] pciu_pciif_cbe_in = int_pci_cbe ; + +wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ; +wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ; +wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ; +wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ; +wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ; +wire pciu_pciif_stop_reg_in = in_reg_stop_out ; + +pci_target_unit pci_target_unit +( + .reset_in (reset), + .wb_clock_in (wb_clk), + .pci_clock_in (pci_clk), + .pciu_wbm_adr_o (pciu_adr_out), + .pciu_wbm_dat_o (pciu_mdata_out), + .pciu_wbm_dat_i (pciu_mdata_in), + .pciu_wbm_cyc_o (pciu_cyc_out), + .pciu_wbm_stb_o (pciu_stb_out), + .pciu_wbm_we_o (pciu_we_out), + .pciu_wbm_cti_o (pciu_cti_out), + .pciu_wbm_bte_o (pciu_bte_out), + .pciu_wbm_sel_o (pciu_sel_out), + .pciu_wbm_ack_i (pciu_ack_in), + .pciu_wbm_rty_i (pciu_rty_in), + .pciu_wbm_err_i (pciu_err_in), + .pciu_mem_enable_in (pciu_mem_enable_in), + .pciu_io_enable_in (pciu_io_enable_in), + .pciu_map_in (pciu_map_in), + .pciu_pref_en_in (pciu_pref_en_in), + .pciu_conf_data_in (pciu_conf_data_in), + .pciu_wbw_fifo_empty_in (pciu_wbw_fifo_empty_in), + .pciu_wbu_del_read_comp_pending_in (pciu_wbu_del_read_comp_pending_in), + .pciu_wbu_frame_en_in (pciu_wbu_frame_en_in), + .pciu_bar0_in (pciu_bar0_in), + .pciu_bar1_in (pciu_bar1_in), + .pciu_bar2_in (pciu_bar2_in), + .pciu_bar3_in (pciu_bar3_in), + .pciu_bar4_in (pciu_bar4_in), + .pciu_bar5_in (pciu_bar5_in), + .pciu_am0_in (pciu_am0_in), + .pciu_am1_in (pciu_am1_in), + .pciu_am2_in (pciu_am2_in), + .pciu_am3_in (pciu_am3_in), + .pciu_am4_in (pciu_am4_in), + .pciu_am5_in (pciu_am5_in), + .pciu_ta0_in (pciu_ta0_in), + .pciu_ta1_in (pciu_ta1_in), + .pciu_ta2_in (pciu_ta2_in), + .pciu_ta3_in (pciu_ta3_in), + .pciu_ta4_in (pciu_ta4_in), + .pciu_ta5_in (pciu_ta5_in), + .pciu_at_en_in (pciu_at_en_in), + .pciu_cache_line_size_in (pciu_cache_line_size_in), + .pciu_cache_lsize_not_zero_in (pciu_cache_lsize_not_zero_in), + .pciu_pciif_frame_in (pciu_pciif_frame_in), + .pciu_pciif_irdy_in (pciu_pciif_irdy_in), + .pciu_pciif_idsel_in (pciu_pciif_idsel_in), + .pciu_pciif_frame_reg_in (pciu_pciif_frame_reg_in), + .pciu_pciif_irdy_reg_in (pciu_pciif_irdy_reg_in), + .pciu_pciif_idsel_reg_in (pciu_pciif_idsel_reg_in), + .pciu_pciif_ad_reg_in (pciu_pciif_ad_reg_in), + .pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in), + .pciu_pciif_cbe_in (pciu_pciif_cbe_in), + .pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in), + .pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in), + .pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in), + .pciu_pciif_bckp_stop_in (pciu_pciif_bckp_stop_in), + .pciu_pciif_trdy_reg_in (pciu_pciif_trdy_reg_in), + .pciu_pciif_stop_reg_in (pciu_pciif_stop_reg_in), + .pciu_pciif_trdy_out (pciu_pciif_trdy_out), + .pciu_pciif_stop_out (pciu_pciif_stop_out), + .pciu_pciif_devsel_out (pciu_pciif_devsel_out), + .pciu_pciif_trdy_en_out (pciu_pciif_trdy_en_out), + .pciu_pciif_stop_en_out (pciu_pciif_stop_en_out), + .pciu_pciif_devsel_en_out (pciu_pciif_devsel_en_out), + .pciu_ad_load_out (pciu_ad_load_out), + .pciu_ad_load_on_transfer_out (pciu_ad_load_on_transfer_out), + .pciu_pciif_ad_out (pciu_pciif_ad_out), + .pciu_pciif_ad_en_out (pciu_pciif_ad_en_out), + .pciu_pciif_tabort_set_out (pciu_pciif_tabort_set_out), + .pciu_err_addr_out (pciu_err_addr_out), + .pciu_err_bc_out (pciu_err_bc_out), + .pciu_err_data_out (pciu_err_data_out), + .pciu_err_be_out (pciu_err_be_out), + .pciu_err_signal_out (pciu_err_signal_out), + .pciu_err_source_out (pciu_err_source_out), + .pciu_err_rty_exp_out (pciu_err_rty_exp_out), + .pciu_conf_offset_out (pciu_conf_offset_out), + .pciu_conf_renable_out (pciu_conf_renable_out), + .pciu_conf_wenable_out (pciu_conf_wenable_out), + .pciu_conf_be_out (pciu_conf_be_out), + .pciu_conf_data_out (pciu_conf_data_out), + .pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out), + .pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out) + +`ifdef PCI_BIST + , + .mbist_si_i (mbist_so_o_internal), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +); + + +// CONFIGURATION SPACE INPUTS +`ifdef HOST + + wire [11:0] conf_w_addr_in = wbu_conf_offset_out ; + wire [31:0] conf_w_data_in = wbu_conf_data_out ; + wire conf_w_we_in = wbu_conf_wenable_out ; + wire conf_w_re_in = wbu_conf_renable_out ; + wire [3:0] conf_w_be_in = wbu_conf_be_out ; + wire conf_w_clock = wb_clk ; + wire [11:0] conf_r_addr_in = pciu_conf_offset_out ; + wire conf_r_re_in = pciu_conf_renable_out ; + +`else +`ifdef GUEST + + wire [11:0] conf_r_addr_in = wbu_conf_offset_out ; + wire conf_r_re_in = wbu_conf_renable_out ; + wire conf_w_clock = pci_clk ; + wire [11:0] conf_w_addr_in = pciu_conf_offset_out ; + wire [31:0] conf_w_data_in = pciu_conf_data_out ; + wire conf_w_we_in = pciu_conf_wenable_out ; + wire conf_w_re_in = pciu_conf_renable_out ; + wire [3:0] conf_w_be_in = pciu_conf_be_out ; + +`endif +`endif + + +wire conf_perr_in = parchk_par_err_detect_out ; +wire conf_serr_in = parchk_sig_serr_out ; +wire conf_master_abort_recv_in = wbu_mabort_rec_out ; +wire conf_target_abort_recv_in = wbu_tabort_rec_out ; +wire conf_target_abort_set_in = pciu_pciif_tabort_set_out ; + +wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ; + +wire [3:0] conf_pci_err_be_in = pciu_err_be_out ; +wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out; +wire conf_pci_err_es_in = pciu_err_source_out ; +wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ; +wire conf_pci_err_sig_in = pciu_err_signal_out ; +wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ; +wire [31:0] conf_pci_err_data_in = pciu_err_data_out ; + +wire [3:0] conf_wb_err_be_in = out_bckp_cbe_out ; +wire [3:0] conf_wb_err_bc_in = wbu_err_bc_out ; +wire conf_wb_err_rty_exp_in = wbu_err_rty_exp_out ; +wire conf_wb_err_es_in = wbu_err_source_out ; +wire conf_wb_err_sig_in = wbu_err_signal_out ; +wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ; +wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ; + +wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ; +wire conf_par_err_int_in = parchk_perr_mas_detect_out ; +wire conf_sys_err_int_in = parchk_sig_serr_out ; + +pci_conf_space configuration( + .reset (reset), + .pci_clk (pci_clk), + .wb_clk (wb_clk), + .w_conf_address_in (conf_w_addr_in), + .w_conf_data_in (conf_w_data_in), + .w_conf_data_out (conf_w_data_out), + .r_conf_address_in (conf_r_addr_in), + .r_conf_data_out (conf_r_data_out), + .w_we_i (conf_w_we_in), + .w_re (conf_w_re_in), + .r_re (conf_r_re_in), + .w_byte_en_in (conf_w_be_in), + .w_clock (conf_w_clock), + .serr_enable (conf_serr_enable_out), + .perr_response (conf_perr_response_out), + .pci_master_enable (conf_pci_master_enable_out), + .memory_space_enable (conf_mem_space_enable_out), + .io_space_enable (conf_io_space_enable_out), + .perr_in (conf_perr_in), + .serr_in (conf_serr_in), + .master_abort_recv (conf_master_abort_recv_in), + .target_abort_recv (conf_target_abort_recv_in), + .target_abort_set (conf_target_abort_set_in), + .master_data_par_err (conf_master_data_par_err_in), + .cache_line_size_to_pci (conf_cache_line_size_to_pci_out), + .cache_line_size_to_wb (conf_cache_line_size_to_wb_out), + .cache_lsize_not_zero_to_wb (conf_cache_lsize_not_zero_to_wb_out), + .latency_tim (conf_latency_tim_out), + .pci_base_addr0 (conf_pci_ba0_out), + .pci_base_addr1 (conf_pci_ba1_out), + .pci_base_addr2 (conf_pci_ba2_out), + .pci_base_addr3 (conf_pci_ba3_out), + .pci_base_addr4 (conf_pci_ba4_out), + .pci_base_addr5 (conf_pci_ba5_out), + .pci_memory_io0 (conf_pci_mem_io0_out), + .pci_memory_io1 (conf_pci_mem_io1_out), + .pci_memory_io2 (conf_pci_mem_io2_out), + .pci_memory_io3 (conf_pci_mem_io3_out), + .pci_memory_io4 (conf_pci_mem_io4_out), + .pci_memory_io5 (conf_pci_mem_io5_out), + .pci_addr_mask0 (conf_pci_am0_out), + .pci_addr_mask1 (conf_pci_am1_out), + .pci_addr_mask2 (conf_pci_am2_out), + .pci_addr_mask3 (conf_pci_am3_out), + .pci_addr_mask4 (conf_pci_am4_out), + .pci_addr_mask5 (conf_pci_am5_out), + .pci_tran_addr0 (conf_pci_ta0_out), + .pci_tran_addr1 (conf_pci_ta1_out), + .pci_tran_addr2 (conf_pci_ta2_out), + .pci_tran_addr3 (conf_pci_ta3_out), + .pci_tran_addr4 (conf_pci_ta4_out), + .pci_tran_addr5 (conf_pci_ta5_out), + .pci_img_ctrl0 (conf_pci_img_ctrl0_out), + .pci_img_ctrl1 (conf_pci_img_ctrl1_out), + .pci_img_ctrl2 (conf_pci_img_ctrl2_out), + .pci_img_ctrl3 (conf_pci_img_ctrl3_out), + .pci_img_ctrl4 (conf_pci_img_ctrl4_out), + .pci_img_ctrl5 (conf_pci_img_ctrl5_out), + .pci_error_be (conf_pci_err_be_in), + .pci_error_bc (conf_pci_err_bc_in), + .pci_error_rty_exp (conf_pci_err_rty_exp_in), + .pci_error_es (conf_pci_err_es_in), + .pci_error_sig (conf_pci_err_sig_in), + .pci_error_addr (conf_pci_err_addr_in), + .pci_error_data (conf_pci_err_data_in), + .wb_base_addr0 (conf_wb_ba0_out), + .wb_base_addr1 (conf_wb_ba1_out), + .wb_base_addr2 (conf_wb_ba2_out), + .wb_base_addr3 (conf_wb_ba3_out), + .wb_base_addr4 (conf_wb_ba4_out), + .wb_base_addr5 (conf_wb_ba5_out), + .wb_memory_io0 (conf_wb_mem_io0_out), + .wb_memory_io1 (conf_wb_mem_io1_out), + .wb_memory_io2 (conf_wb_mem_io2_out), + .wb_memory_io3 (conf_wb_mem_io3_out), + .wb_memory_io4 (conf_wb_mem_io4_out), + .wb_memory_io5 (conf_wb_mem_io5_out), + .wb_addr_mask0 (conf_wb_am0_out), + .wb_addr_mask1 (conf_wb_am1_out), + .wb_addr_mask2 (conf_wb_am2_out), + .wb_addr_mask3 (conf_wb_am3_out), + .wb_addr_mask4 (conf_wb_am4_out), + .wb_addr_mask5 (conf_wb_am5_out), + .wb_tran_addr0 (conf_wb_ta0_out), + .wb_tran_addr1 (conf_wb_ta1_out), + .wb_tran_addr2 (conf_wb_ta2_out), + .wb_tran_addr3 (conf_wb_ta3_out), + .wb_tran_addr4 (conf_wb_ta4_out), + .wb_tran_addr5 (conf_wb_ta5_out), + .wb_img_ctrl0 (conf_wb_img_ctrl0_out), + .wb_img_ctrl1 (conf_wb_img_ctrl1_out), + .wb_img_ctrl2 (conf_wb_img_ctrl2_out), + .wb_img_ctrl3 (conf_wb_img_ctrl3_out), + .wb_img_ctrl4 (conf_wb_img_ctrl4_out), + .wb_img_ctrl5 (conf_wb_img_ctrl5_out), + .wb_error_be (conf_wb_err_be_in), + .wb_error_bc (conf_wb_err_bc_in), + .wb_error_rty_exp (conf_wb_err_rty_exp_in), + .wb_error_es (conf_wb_err_es_in), + .wb_error_sig (conf_wb_err_sig_in), + .wb_error_addr (conf_wb_err_addr_in), + .wb_error_data (conf_wb_err_data_in), + .config_addr (conf_ccyc_addr_out), + .icr_soft_res (conf_soft_res_out), + .int_out (conf_int_out), + .isr_int_prop (conf_isr_int_prop_in), + .isr_par_err_int (conf_par_err_int_in), + .isr_sys_err_int (conf_sys_err_int_in), + + .pci_init_complete_out (conf_pci_init_complete_out), + .wb_init_complete_out (conf_wb_init_complete_out) + + `ifdef PCI_CPCI_HS_IMPLEMENT + , + .pci_cpci_hs_enum_oe_o (pci_cpci_hs_enum_oe_o) , + .pci_cpci_hs_led_oe_o (pci_cpci_hs_led_oe_o ) , + .pci_cpci_hs_es_i (pci_cpci_hs_es_i) + `endif + + `ifdef PCI_SPOCI + , + // Serial power on configuration interface + .spoci_scl_oe_o (spoci_scl_oe_o ) , + .spoci_sda_i (spoci_sda_i ) , + .spoci_sda_oe_o (spoci_sda_oe_o ) + `endif + ) ; + +// pci data io multiplexer inputs +wire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ; +wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ; +wire [31:0] pci_mux_tar_ad_in = pciu_pciif_ad_out ; +wire pci_mux_devsel_in = pciu_pciif_devsel_out ; +wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ; +wire pci_mux_trdy_in = pciu_pciif_trdy_out ; +wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ; +wire pci_mux_stop_in = pciu_pciif_stop_out ; +wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ; +wire pci_mux_tar_load_in = pciu_ad_load_out ; +wire pci_mux_tar_load_on_transfer_in = pciu_ad_load_on_transfer_out ; + +wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ; +wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ; + +wire pci_mux_frame_in = wbu_pciif_frame_out ; +wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ; +wire pci_mux_irdy_in = wbu_pciif_irdy_out; +wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out; +wire pci_mux_mas_load_in = wbu_ad_load_out ; +wire pci_mux_mas_load_on_transfer_in = wbu_ad_load_on_transfer_out ; +wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ; +wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ; + +wire pci_mux_par_in = parchk_pci_par_out ; +wire pci_mux_par_en_in = parchk_pci_par_en_out ; +wire pci_mux_perr_in = parchk_pci_perr_out ; +wire pci_mux_perr_en_in = parchk_pci_perr_en_out ; +wire pci_mux_serr_in = parchk_pci_serr_out ; +wire pci_mux_serr_en_in = parchk_pci_serr_en_out; + +wire pci_mux_req_in = wbu_pciif_req_out ; +wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ; + +wire pci_mux_pci_irdy_in = int_pci_irdy ; +wire pci_mux_pci_trdy_in = int_pci_trdy ; +wire pci_mux_pci_frame_in = int_pci_frame ; +wire pci_mux_pci_stop_in = int_pci_stop ; + +wire pci_mux_init_complete_in = conf_pci_init_complete_out ; + +pci_io_mux pci_io_mux +( + .reset_in (reset), + .clk_in (pci_clk), + .frame_in (pci_mux_frame_in), + .frame_en_in (pci_mux_frame_en_in), + .frame_load_in (pci_mux_frame_load_in), + .irdy_in (pci_mux_irdy_in), + .irdy_en_in (pci_mux_irdy_en_in), + .devsel_in (pci_mux_devsel_in), + .devsel_en_in (pci_mux_devsel_en_in), + .trdy_in (pci_mux_trdy_in), + .trdy_en_in (pci_mux_trdy_en_in), + .stop_in (pci_mux_stop_in), + .stop_en_in (pci_mux_stop_en_in), + .master_load_in (pci_mux_mas_load_in), + .master_load_on_transfer_in (pci_mux_mas_load_on_transfer_in), + .target_load_in (pci_mux_tar_load_in), + .target_load_on_transfer_in (pci_mux_tar_load_on_transfer_in), + .cbe_in (pci_mux_cbe_in), + .cbe_en_in (pci_mux_cbe_en_in), + .mas_ad_in (pci_mux_mas_ad_in), + .tar_ad_in (pci_mux_tar_ad_in), + + .mas_ad_en_in (pci_mux_mas_ad_en_in), + .tar_ad_en_in (pci_mux_tar_ad_en_in), + .tar_ad_en_reg_in (pci_mux_tar_ad_en_reg_in), + + .par_in (pci_mux_par_in), + .par_en_in (pci_mux_par_en_in), + .perr_in (pci_mux_perr_in), + .perr_en_in (pci_mux_perr_en_in), + .serr_in (pci_mux_serr_in), + .serr_en_in (pci_mux_serr_en_in), + + .frame_en_out (pci_mux_frame_en_out), + .irdy_en_out (pci_mux_irdy_en_out), + .devsel_en_out (pci_mux_devsel_en_out), + .trdy_en_out (pci_mux_trdy_en_out), + .stop_en_out (pci_mux_stop_en_out), + .cbe_en_out (pci_mux_cbe_en_out), + .ad_en_out (pci_mux_ad_en_out), + + .frame_out (pci_mux_frame_out), + .irdy_out (pci_mux_irdy_out), + .devsel_out (pci_mux_devsel_out), + .trdy_out (pci_mux_trdy_out), + .stop_out (pci_mux_stop_out), + .cbe_out (pci_mux_cbe_out), + .ad_out (pci_mux_ad_out), + .ad_load_out (pci_mux_ad_load_out), + + .par_out (pci_mux_par_out), + .par_en_out (pci_mux_par_en_out), + .perr_out (pci_mux_perr_out), + .perr_en_out (pci_mux_perr_en_out), + .serr_out (pci_mux_serr_out), + .serr_en_out (pci_mux_serr_en_out), + .req_in (pci_mux_req_in), + .req_out (pci_mux_req_out), + .req_en_out (pci_mux_req_en_out), + .pci_irdy_in (pci_mux_pci_irdy_in), + .pci_trdy_in (pci_mux_pci_trdy_in), + .pci_frame_in (pci_mux_pci_frame_in), + .pci_stop_in (pci_mux_pci_stop_in), + .ad_en_unregistered_out (pci_mux_ad_en_unregistered_out), + + .init_complete_in (pci_mux_init_complete_in) +); + +pci_cur_out_reg output_backup +( + .reset_in (reset), + .clk_in (pci_clk), + .frame_in (pci_mux_frame_in), + .frame_en_in (pci_mux_frame_en_in), + .frame_load_in (pci_mux_frame_load_in), + .irdy_in (pci_mux_irdy_in), + .irdy_en_in (pci_mux_irdy_en_in), + .devsel_in (pci_mux_devsel_in), + .trdy_in (pci_mux_trdy_in), + .trdy_en_in (pci_mux_trdy_en_in), + .stop_in (pci_mux_stop_in), + .ad_load_in (pci_mux_ad_load_out), + .cbe_in (pci_mux_cbe_in), + .cbe_en_in (pci_mux_cbe_en_in), + .mas_ad_in (pci_mux_mas_ad_in), + .tar_ad_in (pci_mux_tar_ad_in), + + .mas_ad_en_in (pci_mux_mas_ad_en_in), + .tar_ad_en_in (pci_mux_tar_ad_en_in), + .ad_en_unregistered_in (pci_mux_ad_en_unregistered_out), + + .par_in (pci_mux_par_in), + .par_en_in (pci_mux_par_en_in), + .perr_in (pci_mux_perr_in), + .perr_en_in (pci_mux_perr_en_in), + .serr_in (pci_mux_serr_in), + .serr_en_in (pci_mux_serr_en_in), + + .frame_out (out_bckp_frame_out), + .frame_en_out (out_bckp_frame_en_out), + .irdy_out (out_bckp_irdy_out), + .irdy_en_out (out_bckp_irdy_en_out), + .devsel_out (out_bckp_devsel_out), + .trdy_out (out_bckp_trdy_out), + .trdy_en_out (out_bckp_trdy_en_out), + .stop_out (out_bckp_stop_out), + .cbe_out (out_bckp_cbe_out), + .ad_out (out_bckp_ad_out), + .ad_en_out (out_bckp_ad_en_out), + .cbe_en_out (out_bckp_cbe_en_out), + .tar_ad_en_out (out_bckp_tar_ad_en_out), + .mas_ad_en_out (out_bckp_mas_ad_en_out), + + .par_out (out_bckp_par_out), + .par_en_out (out_bckp_par_en_out), + .perr_out (out_bckp_perr_out), + .perr_en_out (out_bckp_perr_en_out), + .serr_out (out_bckp_serr_out), + .serr_en_out (out_bckp_serr_en_out) +) ; + +// PARITY CHECKER INPUTS +wire parchk_pci_par_in = int_pci_par ; +wire parchk_pci_perr_in = int_pci_perr ; +wire parchk_pci_frame_reg_in = in_reg_frame_out ; +wire parchk_pci_frame_en_in = out_bckp_frame_en_out ; +wire parchk_pci_irdy_en_in = out_bckp_irdy_en_out ; +wire parchk_pci_irdy_reg_in = in_reg_irdy_out ; +wire parchk_pci_trdy_reg_in = in_reg_trdy_out ; + + +wire parchk_pci_trdy_en_in = out_bckp_trdy_en_out ; + + +wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ; +wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ; +wire [3:0] parchk_pci_cbe_in_in = int_pci_cbe ; +wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ; +wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ; +wire parchk_pci_ad_en_in = out_bckp_ad_en_out ; +wire parchk_par_err_response_in = conf_perr_response_out ; +wire parchk_serr_enable_in = conf_serr_enable_out ; + +wire parchk_pci_perr_out_in = out_bckp_perr_out ; +wire parchk_pci_serr_en_in = out_bckp_serr_en_out ; +wire parchk_pci_serr_out_in = out_bckp_serr_out ; +wire parchk_pci_cbe_en_in = out_bckp_cbe_en_out ; + +wire parchk_pci_par_en_in = out_bckp_par_en_out ; + +pci_parity_check parity_checker +( + .reset_in (reset), + .clk_in (pci_clk), + .pci_par_in (parchk_pci_par_in), + .pci_par_out (parchk_pci_par_out), + .pci_par_en_out (parchk_pci_par_en_out), + .pci_par_en_in (parchk_pci_par_en_in), + .pci_perr_in (parchk_pci_perr_in), + .pci_perr_out (parchk_pci_perr_out), + .pci_perr_en_out (parchk_pci_perr_en_out), + .pci_perr_out_in (parchk_pci_perr_out_in), + .pci_serr_out (parchk_pci_serr_out), + .pci_serr_out_in (parchk_pci_serr_out_in), + .pci_serr_en_out (parchk_pci_serr_en_out), + .pci_serr_en_in (parchk_pci_serr_en_in), + .pci_frame_reg_in (parchk_pci_frame_reg_in), + .pci_frame_en_in (parchk_pci_frame_en_in), + .pci_irdy_en_in (parchk_pci_irdy_en_in), + .pci_irdy_reg_in (parchk_pci_irdy_reg_in), + .pci_trdy_reg_in (parchk_pci_trdy_reg_in), + .pci_trdy_en_in (parchk_pci_trdy_en_in), + .pci_ad_out_in (parchk_pci_ad_out_in), + .pci_ad_reg_in (parchk_pci_ad_reg_in), + .pci_cbe_in_in (parchk_pci_cbe_in_in), + .pci_cbe_reg_in (parchk_pci_cbe_reg_in), + .pci_cbe_en_in (parchk_pci_cbe_en_in), + .pci_cbe_out_in (parchk_pci_cbe_out_in), + .pci_ad_en_in (parchk_pci_ad_en_in), + .par_err_response_in (parchk_par_err_response_in), + .par_err_detect_out (parchk_par_err_detect_out), + .perr_mas_detect_out (parchk_perr_mas_detect_out), + .serr_enable_in (parchk_serr_enable_in), + .sig_serr_out (parchk_sig_serr_out) +); + +wire in_reg_gnt_in = pci_gnt_i ; +wire in_reg_frame_in = int_pci_frame ; +wire in_reg_irdy_in = int_pci_irdy ; +wire in_reg_trdy_in = int_pci_trdy ; +wire in_reg_stop_in = int_pci_stop ; +wire in_reg_devsel_in = int_pci_devsel ; +wire in_reg_idsel_in = pci_idsel_i ; +wire [31:0] in_reg_ad_in = pci_ad_i ; +wire [3:0] in_reg_cbe_in = int_pci_cbe ; + +pci_in_reg input_register +( + .reset_in (reset), + .clk_in (pci_clk), + .init_complete_in (conf_pci_init_complete_out), + + .pci_gnt_in (in_reg_gnt_in), + .pci_frame_in (in_reg_frame_in), + .pci_irdy_in (in_reg_irdy_in), + .pci_trdy_in (in_reg_trdy_in), + .pci_stop_in (in_reg_stop_in), + .pci_devsel_in (in_reg_devsel_in), + .pci_idsel_in (in_reg_idsel_in), + .pci_ad_in (in_reg_ad_in), + .pci_cbe_in (in_reg_cbe_in), + + .pci_gnt_reg_out (in_reg_gnt_out), + .pci_frame_reg_out (in_reg_frame_out), + .pci_irdy_reg_out (in_reg_irdy_out), + .pci_trdy_reg_out (in_reg_trdy_out), + .pci_stop_reg_out (in_reg_stop_out), + .pci_devsel_reg_out (in_reg_devsel_out), + .pci_idsel_reg_out (in_reg_idsel_out), + .pci_ad_reg_out (in_reg_ad_out), + .pci_cbe_reg_out (in_reg_cbe_out) +); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cbe_en_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cbe_en_crit.v new file mode 100644 index 000000000..2041b046d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cbe_en_crit.v @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "cbe_en_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_cbe_en_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// this one is included in master state machine for CBE output enable driving + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_cbe_en_crit +( + pci_cbe_en_out, + cbe_en_slow_in, + cbe_en_keep_in, + pci_stop_in, + pci_trdy_in +) ; + +output pci_cbe_en_out ; +input cbe_en_slow_in, + cbe_en_keep_in, + pci_stop_in, + pci_trdy_in ; + +assign pci_cbe_en_out = cbe_en_slow_in || cbe_en_keep_in && pci_stop_in && pci_trdy_in ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_cyc_addr_dec.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_cyc_addr_dec.v new file mode 100644 index 000000000..96ef75556 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_cyc_addr_dec.v @@ -0,0 +1,119 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "conf_cyc_addr_dec.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_conf_cyc_addr_dec.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + + +// module is a simple decoder which decodes device num field of configuration address +// for type0 configuration cycles. If type 1 configuration cycle is +// initiated then address goes through unchanged + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_conf_cyc_addr_dec +( + ccyc_addr_in, + ccyc_addr_out +) ; + +input [31:0] ccyc_addr_in ; +output [31:0] ccyc_addr_out ; +reg [31:11] ccyc_addr_31_11 ; + +// lower 11 address lines are alweys going through unchanged +assign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ; + +// configuration cycle type indicator +wire ccyc_type = ccyc_addr_in[0] ; + +always@(ccyc_addr_in or ccyc_type) +begin + if (ccyc_type) + // type 1 cycle - address goes through unchanged + ccyc_addr_31_11 = ccyc_addr_in[31:11] ; + else + begin + // type 0 conf. cycle - decode device number field to appropriate value + case (ccyc_addr_in[15:11]) + 5'h00:ccyc_addr_31_11 = 21'h00_0001 ; + 5'h01:ccyc_addr_31_11 = 21'h00_0002 ; + 5'h02:ccyc_addr_31_11 = 21'h00_0004 ; + 5'h03:ccyc_addr_31_11 = 21'h00_0008 ; + 5'h04:ccyc_addr_31_11 = 21'h00_0010 ; + 5'h05:ccyc_addr_31_11 = 21'h00_0020 ; + 5'h06:ccyc_addr_31_11 = 21'h00_0040 ; + 5'h07:ccyc_addr_31_11 = 21'h00_0080 ; + 5'h08:ccyc_addr_31_11 = 21'h00_0100 ; + 5'h09:ccyc_addr_31_11 = 21'h00_0200 ; + 5'h0A:ccyc_addr_31_11 = 21'h00_0400 ; + 5'h0B:ccyc_addr_31_11 = 21'h00_0800 ; + 5'h0C:ccyc_addr_31_11 = 21'h00_1000 ; + 5'h0D:ccyc_addr_31_11 = 21'h00_2000 ; + 5'h0E:ccyc_addr_31_11 = 21'h00_4000 ; + 5'h0F:ccyc_addr_31_11 = 21'h00_8000 ; + 5'h10:ccyc_addr_31_11 = 21'h01_0000 ; + 5'h11:ccyc_addr_31_11 = 21'h02_0000 ; + 5'h12:ccyc_addr_31_11 = 21'h04_0000 ; + 5'h13:ccyc_addr_31_11 = 21'h08_0000 ; + 5'h14:ccyc_addr_31_11 = 21'h10_0000 ; + default: ccyc_addr_31_11 = 21'h00_0000 ; + endcase + end +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_space.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_space.v new file mode 100644 index 000000000..4c806ee8a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_conf_space.v @@ -0,0 +1,3932 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_conf_space.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org //// +//// - Tadej Markovic //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_conf_space.v,v $ +// Revision 1.10 2004/08/19 16:04:53 mihad +// Removed some unused signals. +// +// Revision 1.9 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.8 2004/07/07 12:45:01 mihad +// Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. +// Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers. +// +// Revision 1.7 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.6 2003/12/28 09:54:48 fr2201 +// def_wb_imagex_addr_map defined correctly +// +// Revision 1.5 2003/12/28 09:20:00 fr2201 +// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) +// +// Revision 1.4 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.3 2003/08/14 13:06:02 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.2 2003/03/26 13:16:18 mihad +// Added the reset value parameter to the synchronizer flop module. +// Added resets to all synchronizer flop instances. +// Repaired initial sync value in fifos. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.4 2002/08/13 11:03:53 mihad +// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +/*----------------------------------------------------------------------------------------------------------- + w_ prefix is a sign for Write (and read) side of Dual-Port registers + r_ prefix is a sign for Read only side of Dual-Port registers +In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read +enable signals with chip-select (conf_hit) for config. space. +In the third line there are output signlas from Command register of the PCI configuration header !!! +In the fourth line there are input signals to Status register of the PCI configuration header !!! +In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!! +Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address +registers from the PCI conf. header !!! +-----------------------------------------------------------------------------------------------------------*/ + // normal R/W address, data and control +module pci_conf_space + ( w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out, + w_we_i, w_re, r_re, w_byte_en_in, w_clock, reset, pci_clk, wb_clk, + // outputs from command register of the PCI header + serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable, + // inputs to status register of the PCI header + perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err, + // output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header + cache_line_size_to_pci, cache_line_size_to_wb, cache_lsize_not_zero_to_wb, + latency_tim, + // output from all pci IMAGE registers + pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5, + pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5, + pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5, + pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5, + pci_img_ctrl0, pci_img_ctrl1, pci_img_ctrl2, pci_img_ctrl3, pci_img_ctrl4, pci_img_ctrl5, + // input to pci error control and status register, error address and error data registers + pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_es, pci_error_sig, pci_error_addr, + pci_error_data, + // output from all wishbone IMAGE registers + wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5, + wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5, + wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5, + wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5, + wb_img_ctrl0, wb_img_ctrl1, wb_img_ctrl2, wb_img_ctrl3, wb_img_ctrl4, wb_img_ctrl5, + // input to wb error control and status register, error address and error data registers + wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data, + // output from conf. cycle generation register (sddress), int. control register & interrupt output + config_addr, icr_soft_res, int_out, + // input to interrupt status register + isr_sys_err_int, isr_par_err_int, isr_int_prop, + + pci_init_complete_out, wb_init_complete_out + + `ifdef PCI_CPCI_HS_IMPLEMENT + , + pci_cpci_hs_enum_oe_o, pci_cpci_hs_led_oe_o, pci_cpci_hs_es_i + `endif + + `ifdef PCI_SPOCI + , + spoci_scl_oe_o, spoci_sda_i, spoci_sda_oe_o + `endif + ) ; + + +/*########################################################################################################### +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + Input and output ports + ====================== +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +###########################################################################################################*/ + +// output data +output [31 : 0] w_conf_data_out ; +output [31 : 0] r_conf_data_out ; +reg [31 : 0] w_conf_data_out ; + +`ifdef NO_CNF_IMAGE +`else +reg [31 : 0] r_conf_data_out ; +`endif + +// input data +input [31 : 0] w_conf_data_in ; +wire [31 : 0] w_conf_pdata_reduced ; // reduced data written into PCI image registers +wire [31 : 0] w_conf_wdata_reduced ; // reduced data written into WB image registers +// input address +input [11 : 0] w_conf_address_in ; +input [11 : 0] r_conf_address_in ; +// input control signals +input w_we_i ; +input w_re ; +input r_re ; +input [3 : 0] w_byte_en_in ; +input w_clock ; +input reset ; +input pci_clk ; +input wb_clk ; +// PCI header outputs from command register +output serr_enable ; +output perr_response ; +output pci_master_enable ; +output memory_space_enable ; +output io_space_enable ; +// PCI header inputs to status register +input perr_in ; +input serr_in ; +input master_abort_recv ; +input target_abort_recv ; +input target_abort_set ; +input master_data_par_err ; +// PCI header output from cache_line_size, latency timer and interrupt pin +output [7 : 0] cache_line_size_to_pci ; // sinchronized to PCI clock +output [7 : 0] cache_line_size_to_wb ; // sinchronized to WB clock +output cache_lsize_not_zero_to_wb ; // used in WBU and PCIU +output [7 : 0] latency_tim ; +//output [2 : 0] int_pin ; // only 3 LSbits are important! +// PCI output from image registers +`ifdef GUEST + output [31:12] pci_base_addr0 ; +`endif + +`ifdef HOST + `ifdef NO_CNF_IMAGE + output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0 ; + `else + output [31:12] pci_base_addr0 ; + `endif +`endif + +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5 ; +output pci_memory_io0 ; +output pci_memory_io1 ; +output pci_memory_io2 ; +output pci_memory_io3 ; +output pci_memory_io4 ; +output pci_memory_io5 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4 ; +output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5 ; +output [2 : 1] pci_img_ctrl0 ; +output [2 : 1] pci_img_ctrl1 ; +output [2 : 1] pci_img_ctrl2 ; +output [2 : 1] pci_img_ctrl3 ; +output [2 : 1] pci_img_ctrl4 ; +output [2 : 1] pci_img_ctrl5 ; +// PCI input to pci error control and status register, error address and error data registers +input [3 : 0] pci_error_be ; +input [3 : 0] pci_error_bc ; +input pci_error_rty_exp ; +input pci_error_es ; +input pci_error_sig ; +input [31 : 0] pci_error_addr ; +input [31 : 0] pci_error_data ; +// WISHBONE output from image registers +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr0 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr1 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr2 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr3 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr4 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr5 ; +output wb_memory_io0 ; +output wb_memory_io1 ; +output wb_memory_io2 ; +output wb_memory_io3 ; +output wb_memory_io4 ; +output wb_memory_io5 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask0 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask1 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask2 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask3 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask4 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask5 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr0 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr1 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr2 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr3 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr4 ; +output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr5 ; +output [2 : 0] wb_img_ctrl0 ; +output [2 : 0] wb_img_ctrl1 ; +output [2 : 0] wb_img_ctrl2 ; +output [2 : 0] wb_img_ctrl3 ; +output [2 : 0] wb_img_ctrl4 ; +output [2 : 0] wb_img_ctrl5 ; +// WISHBONE input to wb error control and status register, error address and error data registers +input [3 : 0] wb_error_be ; +input [3 : 0] wb_error_bc ; +input wb_error_rty_exp ; +input wb_error_es ; +input wb_error_sig ; +input [31 : 0] wb_error_addr ; +input [31 : 0] wb_error_data ; +// GENERAL output from conf. cycle generation register & int. control register +output [23 : 0] config_addr ; +output icr_soft_res ; +output int_out ; +// GENERAL input to interrupt status register +input isr_sys_err_int ; +input isr_par_err_int ; +input isr_int_prop ; + +output pci_init_complete_out ; +output wb_init_complete_out ; + +`ifdef PCI_CPCI_HS_IMPLEMENT +output pci_cpci_hs_enum_oe_o ; +output pci_cpci_hs_led_oe_o ; +input pci_cpci_hs_es_i ; + +reg pci_cpci_hs_enum_oe_o ; +reg pci_cpci_hs_led_oe_o ; + +// set the hot swap ejector switch debounce counter width +// it is only 4 for simulation purposes +`ifdef PCI_CPCI_SIM + + parameter hs_es_cnt_width = 4 ; + +`else + + `ifdef PCI33 + + parameter hs_es_cnt_width = 16 ; + + `endif + + `ifdef PCI66 + + parameter hs_es_cnt_width = 17 ; + + `endif +`endif + +`endif + +`ifdef PCI_SPOCI +output spoci_scl_oe_o ; +input spoci_sda_i ; +output spoci_sda_oe_o ; + +reg spoci_cs_nack, + spoci_cs_write, + spoci_cs_read; + +reg [10: 0] spoci_cs_adr ; +reg [ 7: 0] spoci_cs_dat ; +`endif + +/*########################################################################################################### +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + REGISTERS definition + ==================== +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +###########################################################################################################*/ + +// Decoded Register Select signals for writting (only one address decoder) +reg [56 : 0] w_reg_select_dec ; + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +PCI CONFIGURATION SPACE HEADER (type 00h) registers + + BIST and some other registers are not implemented and therefor written in correct + place with comment line. There are also some registers with NOT all bits implemented and therefor uses + _bitX or _bitX2_X1 to sign which bit or range of bits are implemented. + Some special cases and examples are described below! +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +/*----------------------------------------------------------------------------------------------------------- +[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type ! + r_ prefix is a sign for read only registers + Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. + Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used + together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class + (00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal). +-----------------------------------------------------------------------------------------------------------*/ + reg [15: 0] r_vendor_id ; + reg [15: 0] r_device_id ; + reg [15: 0] r_subsys_vendor_id ; + reg [15: 0] r_subsys_id ; + + reg command_bit8 ; + reg command_bit6 ; + reg [2 : 0] command_bit2_0 ; + reg [15 : 11] status_bit15_11 ; + parameter r_status_bit10_9 = 2'b01 ; // 2'b01 means MEDIUM devsel timing !!! + reg status_bit8 ; + parameter r_status_bit7 = 1'b1 ; // xfast back-to-back capable response !!! + parameter r_status_bit5 = `HEADER_66MHz ; // 1'b0 indicates 33 MHz capable !!! + +`ifdef PCI_CPCI_HS_IMPLEMENT + wire r_status_bit4 = 1 ; + reg hs_ins ; + reg hs_ext ; + wire [ 1: 0] hs_pi = 2'b00 ; + reg hs_loo ; + reg hs_eim ; + wire [ 7: 0] hs_cap_id = 8'h06 ; + reg hs_ins_armed ; + reg hs_ext_armed ; +`else + wire r_status_bit4 = 0 ; +`endif + + reg [ 7: 0] r_revision_id ; + +`ifdef HOST + parameter r_class_code = 24'h06_00_00 ; +`else + parameter r_class_code = 24'h06_80_00 ; +`endif + reg [7 : 0] cache_line_size_reg ; + reg [7 : 0] latency_timer ; + parameter r_header_type = 8'h00 ; + // REG bist NOT implemented !!! + +/*----------------------------------------------------------------------------------------------------------- +[010h-03Ch] all other DWORDs (32-bit) of PCI configuration header - only for HEADER type 00h ! + r_ prefix is a sign for read only registers + BASE_ADDRESS_REGISTERS are the same as ones in the PCI Target configuration registers section. They + are duplicated and therefor defined just ones and used with the same name as written below. If + IMAGEx is NOT defined there is only parameter image_X assigned to '0' and this parameter is used + elsewhere in the code. This parameter is defined in the INTERNAL SIGNALS part !!! + Interrupt_Pin value 8'h01 is used for INT_A pin used. + MIN_GNT and MAX_LAT are used for device's desired values for Latency Timer value. The value in boath + registers specifies a period of time in units of 1/4 microsecond. ZERO indicates that there are no + major requirements for the settings of Latency Timer. + MIN_GNT specifieshow how long a burst period the device needs at 33MHz. MAX_LAT specifies how often + the device needs to gain access to the PCI bus. Values are choosen assuming that the target does not + insert any wait states. Follow the expamle of settings for simple display card. + If we use 64 (32-bit) FIFO locations for one burst then we need 8 x 1/4 microsecond periods at 33MHz + clock rate => MIN_GNT = 08h ! Resolution is 1024 x 768 (= 786432 pixels for one frame) with 16-bit + color mode. We can transfere 2 16-bit pixels in one FIFO location. From that we calculate, that for + one frame we need 6144 burst transferes in 1/25 second. So we need one burst every 6,51 microsecond + and that is 26 x 1/4 microsecond or 1Ah x 1/4 microsecond => MAX_LAT = 1Ah ! +-----------------------------------------------------------------------------------------------------------*/ + // REG x 6 base_address_register_X IMPLEMENTED as pci_ba_X !!! + // REG r_cardbus_cis_pointer NOT implemented !!! + // REG r_subsystem_vendor_id NOT implemented !!! + // REG r_subsystem_id NOT implemented !!! + // REG r_expansion_rom_base_address NOT implemented !!! + // REG r_cap_list_pointer NOT implemented !!! + reg [7 : 0] interrupt_line ; + parameter r_interrupt_pin = 8'h01 ; + reg [7 : 0] r_min_gnt ; + reg [7 : 0] r_max_lat ; + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +PCI Target configuration registers + There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to + sign which bit or range of bits are implemented. Some special cases and examples are described below! +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +/*----------------------------------------------------------------------------------------------------------- +[100h-168h] + Depending on defines (PCI_IMAGE1 or .. or PCI_IMAGE5 or (PCI_IMAGE0 and HOST)) in constants.v file, + there are registers corresponding to each IMAGE defined to REG and parameter pci_image_X assigned to '1'. + The maximum number of images is "6". By default there are first two images used and the first (PCI_IMAGE0) + is assigned to Configuration space! With a 'define' PCI_IMAGEx you choose the number of used PCI IMAGES + in a bridge without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and PCI_IMAGE3 are + used for mapping the space from WB to PCI. Offcourse, PCI_IMAGE0 is assigned to Configuration space). + That leave us PCI_IMAGE5 as the maximum number of images. + There is one exeption, when the core is implemented as HOST. If so, then the PCI specification allowes + the Configuration space NOT to be visible on the PCI bus. With `define PCI_IMAGE0 (and `define HOST), we + assign PCI_IMAGE0 to normal WB to PCI image and not to configuration space! + + When error occurs, PCI ERR_ADDR and ERR_DATA registers stores address and data on the bus that + caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10 + and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error + Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting + mechanism. +-----------------------------------------------------------------------------------------------------------*/ +`ifdef HOST + `ifdef NO_CNF_IMAGE + `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space + reg [31 : 8] pci_ba0_bit31_8 ; + reg [2 : 1] pci_img_ctrl0_bit2_1 ; + reg pci_ba0_bit0 ; + reg [31 : 8] pci_am0 ; + reg [31 : 8] pci_ta0 ; + `else // if PCI bridge is HOST and IMAGE0 is not used + wire [31 : 8] pci_ba0_bit31_8 = 24'h0000_00 ; // NO base address needed + wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch + wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space + wire [31 : 8] pci_am0 = 24'h0000_00 ; // NO address mask needed + wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed + `endif + `else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space + reg [31 : 8] pci_ba0_bit31_8 ; + wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support + wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space + wire [31 : 8] pci_am0 = 24'hFFFF_F0 ; // address mask for configuration image always 20'hffff_f + wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed + `endif +`endif + +`ifdef GUEST // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space + reg [31 : 8] pci_ba0_bit31_8 ; + wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch + wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space + wire [31 : 8] pci_am0 = 24'hffff_f0 ; // address mask for configuration image always 24'hffff_f0 - 4KB mem image + wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed +`endif + +// IMAGE1 is included by default, meanwhile other IMAGEs are optional !!! + reg [2 : 1] pci_img_ctrl1_bit2_1 ; + reg [31 : 8] pci_ba1_bit31_8 ; + `ifdef HOST + reg pci_ba1_bit0 ; + `else + wire pci_ba1_bit0 = `PCI_BA1_MEM_IO ; + `endif + reg [31 : 8] pci_am1 ; + reg [31 : 8] pci_ta1 ; +`ifdef PCI_IMAGE2 + reg [2 : 1] pci_img_ctrl2_bit2_1 ; + reg [31 : 8] pci_ba2_bit31_8 ; + `ifdef HOST + reg pci_ba2_bit0 ; + `else + wire pci_ba2_bit0 = `PCI_BA2_MEM_IO ; + `endif + reg [31 : 8] pci_am2 ; + reg [31 : 8] pci_ta2 ; +`else + wire [2 : 1] pci_img_ctrl2_bit2_1 = 2'b00 ; + wire [31 : 8] pci_ba2_bit31_8 = 24'h0000_00 ; + wire pci_ba2_bit0 = 1'b0 ; + wire [31 : 8] pci_am2 = 24'h0000_00 ; + wire [31 : 8] pci_ta2 = 24'h0000_00 ; +`endif +`ifdef PCI_IMAGE3 + reg [2 : 1] pci_img_ctrl3_bit2_1 ; + reg [31 : 8] pci_ba3_bit31_8 ; + `ifdef HOST + reg pci_ba3_bit0 ; + `else + wire pci_ba3_bit0 = `PCI_BA3_MEM_IO ; + `endif + reg [31 : 8] pci_am3 ; + reg [31 : 8] pci_ta3 ; +`else + wire [2 : 1] pci_img_ctrl3_bit2_1 = 2'b00 ; + wire [31 : 8] pci_ba3_bit31_8 = 24'h0000_00 ; + wire pci_ba3_bit0 = 1'b0 ; + wire [31 : 8] pci_am3 = 24'h0000_00 ; + wire [31 : 8] pci_ta3 = 24'h0000_00 ; +`endif +`ifdef PCI_IMAGE4 + reg [2 : 1] pci_img_ctrl4_bit2_1 ; + reg [31 : 8] pci_ba4_bit31_8 ; + `ifdef HOST + reg pci_ba4_bit0 ; + `else + wire pci_ba4_bit0 = `PCI_BA4_MEM_IO ; + `endif + reg [31 : 8] pci_am4 ; + reg [31 : 8] pci_ta4 ; +`else + wire [2 : 1] pci_img_ctrl4_bit2_1 = 2'b00 ; + wire [31 : 8] pci_ba4_bit31_8 = 24'h0000_00 ; + wire pci_ba4_bit0 = 1'b0 ; + wire [31 : 8] pci_am4 = 24'h0000_00 ; + wire [31 : 8] pci_ta4 = 24'h0000_00 ; +`endif +`ifdef PCI_IMAGE5 + reg [2 : 1] pci_img_ctrl5_bit2_1 ; + reg [31 : 8] pci_ba5_bit31_8 ; + `ifdef HOST + reg pci_ba5_bit0 ; + `else + wire pci_ba5_bit0 = `PCI_BA5_MEM_IO ; + `endif + reg [31 : 8] pci_am5 ; + reg [31 : 8] pci_ta5 ; +`else + wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ; + wire [31 : 8] pci_ba5_bit31_8 = 24'h0000_00 ; + wire pci_ba5_bit0 = 1'b0 ; + wire [31 : 8] pci_am5 = 24'h0000_00 ; + wire [31 : 8] pci_ta5 = 24'h0000_00 ; +`endif + reg [31 : 24] pci_err_cs_bit31_24 ; + reg pci_err_cs_bit10 ; + reg pci_err_cs_bit9 ; + reg pci_err_cs_bit8 ; + reg pci_err_cs_bit0 ; + reg [31 : 0] pci_err_addr ; + reg [31 : 0] pci_err_data ; + + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +WISHBONE Slave configuration registers + There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to + sign which bit or range of bits are implemented. Some special cases and examples are described below! +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +/*----------------------------------------------------------------------------------------------------------- +[800h-85Ch] + Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are + registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'. + The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0) + is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in + a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for + mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave + us WB_IMAGE5 as the maximum number of images. + + When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that + caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9 + and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error + Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting + mechanism. +-----------------------------------------------------------------------------------------------------------*/ +// WB_IMAGE0 is always assigned to config. space or is not used + wire [2 : 0] wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line + wire [31 : 12] wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ; + wire wb_ba0_bit0 = 0 ; // config. space is MEMORY space + wire [31 : 12] wb_am0 = `WB_AM0 ; // 4KBytes of configuration space is minimum + wire [31 : 12] wb_ta0 = 20'h0000_0 ; // NO address translation needed +// WB_IMAGE1 is included by default meanwhile others are optional ! + reg [2 : 0] wb_img_ctrl1_bit2_0 ; + reg [31 : 12] wb_ba1_bit31_12 ; + reg wb_ba1_bit0 ; + reg [31 : 12] wb_am1 ; + reg [31 : 12] wb_ta1 ; +`ifdef WB_IMAGE2 + reg [2 : 0] wb_img_ctrl2_bit2_0 ; + reg [31 : 12] wb_ba2_bit31_12 ; + reg wb_ba2_bit0 ; + reg [31 : 12] wb_am2 ; + reg [31 : 12] wb_ta2 ; +`else + wire [2 : 0] wb_img_ctrl2_bit2_0 = 3'b000 ; + wire [31 : 12] wb_ba2_bit31_12 = 20'h0000_0 ; + wire wb_ba2_bit0 = 1'b0 ; + wire [31 : 12] wb_am2 = 20'h0000_0 ; + wire [31 : 12] wb_ta2 = 20'h0000_0 ; +`endif +`ifdef WB_IMAGE3 + reg [2 : 0] wb_img_ctrl3_bit2_0 ; + reg [31 : 12] wb_ba3_bit31_12 ; + reg wb_ba3_bit0 ; + reg [31 : 12] wb_am3 ; + reg [31 : 12] wb_ta3 ; +`else + wire [2 : 0] wb_img_ctrl3_bit2_0 = 3'b000 ; + wire [31 : 12] wb_ba3_bit31_12 = 20'h0000_0 ; + wire wb_ba3_bit0 = 1'b0 ; + wire [31 : 12] wb_am3 = 20'h0000_0 ; + wire [31 : 12] wb_ta3 = 20'h0000_0 ; +`endif +`ifdef WB_IMAGE4 + reg [2 : 0] wb_img_ctrl4_bit2_0 ; + reg [31 : 12] wb_ba4_bit31_12 ; + reg wb_ba4_bit0 ; + reg [31 : 12] wb_am4 ; + reg [31 : 12] wb_ta4 ; +`else + wire [2 : 0] wb_img_ctrl4_bit2_0 = 3'b000 ; + wire [31 : 12] wb_ba4_bit31_12 = 20'h0000_0 ; + wire wb_ba4_bit0 = 1'b0 ; + wire [31 : 12] wb_am4 = 20'h0000_0 ; + wire [31 : 12] wb_ta4 = 20'h0000_0 ; +`endif +`ifdef WB_IMAGE5 + reg [2 : 0] wb_img_ctrl5_bit2_0 ; + reg [31 : 12] wb_ba5_bit31_12 ; + reg wb_ba5_bit0 ; + reg [31 : 12] wb_am5 ; + reg [31 : 12] wb_ta5 ; +`else + wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ; + wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ; + wire wb_ba5_bit0 = 1'b0 ; + wire [31 : 12] wb_am5 = 20'h0000_0 ; + wire [31 : 12] wb_ta5 = 20'h0000_0 ; +`endif + reg [31 : 24] wb_err_cs_bit31_24 ; +/* reg wb_err_cs_bit10 ;*/ + reg wb_err_cs_bit9 ; + reg wb_err_cs_bit8 ; + reg wb_err_cs_bit0 ; + reg [31 : 0] wb_err_addr ; + reg [31 : 0] wb_err_data ; + + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +Configuration Cycle address register + There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to + sign which bit or range of bits are implemented. +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +/*----------------------------------------------------------------------------------------------------------- +[860h-868h] + PCI bridge must ignore Type 1 configuration cycles (Master Abort) since they are used for PCI to PCI + bridges. This is single function device, that means responding on configuration cycles to all functions + (or responding only to function 0). Configuration address register for generating configuration cycles + is prepared for all options (it includes Bus Number, Device, Function, Offset and Type). + Interrupt acknowledge register stores interrupt vector data returned during Interrupt Acknowledge cycle. +-----------------------------------------------------------------------------------------------------------*/ +`ifdef HOST + reg [23 : 2] cnf_addr_bit23_2 ; + reg cnf_addr_bit0 ; +`else // GUEST + wire [23 : 2] cnf_addr_bit23_2 = 22'h0 ; + wire cnf_addr_bit0 = 1'b0 ; +`endif + // reg [31 : 0] cnf_data ; IMPLEMENTED elsewhere !!!!! + // reg [31 : 0] int_ack ; IMPLEMENTED elsewhere !!!!! + + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +General Interrupt registers + There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to + sign which bit or range of bits are implemented. +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +/*----------------------------------------------------------------------------------------------------------- +[FF8h-FFCh] + Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4 + bits are used to enable interrupt generations. + 5 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, PCI & WB + Error Int and Inerrupt respecively. System and Parity errors are implented only in HOST bridge + implementations! +-----------------------------------------------------------------------------------------------------------*/ + reg icr_bit31 ; +`ifdef HOST + reg [4 : 3] icr_bit4_3 ; + reg [4 : 3] isr_bit4_3 ; + reg [2 : 0] icr_bit2_0 ; + reg [2 : 0] isr_bit2_0 ; +`else // GUEST + wire [4 : 3] icr_bit4_3 = 2'h0 ; + wire [4 : 3] isr_bit4_3 = 2'h0 ; + reg [2 : 0] icr_bit2_0 ; + reg [2 : 0] isr_bit2_0 ; +`endif + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- +Initialization complete identifier + When using I2C or similar initialisation mechanism, + the bridge must not respond to transaction requests on PCI bus, + not even to configuration cycles. + Therefore, only when init_complete is set, the bridge starts + participating on the PCI bus as an active device. + Two additional flip flops are also provided for GUEST implementation, + to synchronize to the pci clock after PCI reset is asynchronously de-asserted. +------------------------------------------------------------------------------------------------------------- +###########################################################################################################*/ + +`ifdef GUEST + +reg rst_inactive_sync ; +reg rst_inactive ; + +`else + +wire rst_inactive = 1'b1 ; + +`endif + +reg init_complete ; + +wire sync_init_complete ; + +`ifdef HOST +assign wb_init_complete_out = init_complete ; + +pci_synchronizer_flop #(1, 0) i_pci_init_complete_sync +( + .data_in ( init_complete ), + .clk_out ( pci_clk ), + .sync_data_out ( sync_init_complete ), + .async_reset ( reset ) +); + +reg pci_init_complete_out ; + +always@(posedge pci_clk or posedge reset) +begin + if (reset) + pci_init_complete_out <= 1'b0 ; + else + pci_init_complete_out <= sync_init_complete ; +end + +`endif + +`ifdef GUEST + +assign pci_init_complete_out = init_complete ; + +pci_synchronizer_flop #(1, 0) i_wb_init_complete_sync +( + .data_in ( init_complete ), + .clk_out ( wb_clk ), + .sync_data_out ( sync_init_complete ), + .async_reset ( reset ) +); + +reg wb_init_complete_out ; + +always@(posedge wb_clk or posedge reset) +begin + if (reset) + wb_init_complete_out <= 1'b0 ; + else + wb_init_complete_out <= sync_init_complete ; +end + +`endif + +/*########################################################################################################### +------------------------------------------------------------------------------------------------------------- + + +-----------------------------------------------------------------------------------------------------------*/ + +`ifdef NO_CNF_IMAGE // if IMAGE0 is assigned as general image space + + assign r_conf_data_out = 32'h0000_0000 ; + +`else + + always@(r_conf_address_in or + status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or + latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or + r_subsys_vendor_id or r_subsys_id or r_max_lat or r_min_gnt or + pci_ba0_bit31_8 or + pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or + pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8 or pci_ba1_bit0 or + pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or + pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or + pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or + pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or + interrupt_line or + pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or + pci_err_addr or pci_err_data or + wb_ba0_bit31_12 or wb_ba0_bit0 or + wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or + wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or + wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or + wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or + wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or + wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or + wb_err_addr or wb_err_data or + cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0 + + `ifdef PCI_CPCI_HS_IMPLEMENT + or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id + `endif + + `ifdef PCI_SPOCI + or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat + `endif + ) + begin + case (r_conf_address_in[9:2]) + // PCI header - configuration space + 8'h0: r_conf_data_out = { r_device_id, r_vendor_id } ; + 8'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, + 4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ; + 8'h2: r_conf_data_out = { r_class_code, r_revision_id } ; + 8'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ; + 8'h4: + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; + `else + r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + end + 8'h5: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; + end + 8'h6: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; + end + 8'h7: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; + end + 8'h8: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; + end + 8'h9: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; + end + 8'hB: + begin + r_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ; + end + `ifdef PCI_CPCI_HS_IMPLEMENT + 8'hD: + begin + r_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ; + end + `endif + 8'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ; + `ifdef PCI_CPCI_HS_IMPLEMENT + (`PCI_CAP_PTR_VAL >> 2): + begin + r_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ; + end + `endif + // PCI target - configuration space + {2'b01, `P_IMG_CTRL0_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ; + {2'b01, `P_BA0_ADDR} : + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; + `else + r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + end + {2'b01, `P_AM0_ADDR}: + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + `else + r_conf_data_out[31:12] = pci_am0[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + r_conf_data_out[31:12] = pci_am0[31:12] ; + r_conf_data_out[11: 0] = 12'h000 ; + `endif + end + {2'b01, `P_TA0_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ; + {2'b01, `P_BA1_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; + end + {2'b01, `P_AM1_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_TA1_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ; + {2'b01, `P_BA2_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; + end + {2'b01, `P_AM2_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_TA2_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ; + {2'b01, `P_BA3_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; + end + {2'b01, `P_AM3_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_TA3_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ; + {2'b01, `P_BA4_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; + end + {2'b01, `P_AM4_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_TA4_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ; + {2'b01, `P_BA5_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; + end + {2'b01, `P_AM5_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_TA5_ADDR}: + begin + r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `P_ERR_CS_ADDR}: r_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9, + pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ; + {2'b01, `P_ERR_ADDR_ADDR}: r_conf_data_out = pci_err_addr ; + {2'b01, `P_ERR_DATA_ADDR}: r_conf_data_out = pci_err_data ; + // WB slave - configuration space + {2'b01, `WB_CONF_SPC_BAR_ADDR}: r_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ; + {2'b01, `W_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ; + {2'b01, `W_BA1_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = wb_ba1_bit0 ; + end + {2'b01, `W_AM1_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_TA1_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ; + `W_BA2_ADDR : + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = wb_ba2_bit0 ; + end + {2'b01, `W_AM2_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_TA2_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ; + {2'b01, `W_BA3_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = wb_ba3_bit0 ; + end + {2'b01, `W_AM3_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_TA3_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ; + {2'b01, `W_BA4_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = wb_ba4_bit0 ; + end + {2'b01, `W_AM4_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_TA4_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ; + {2'b01, `W_BA5_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + r_conf_data_out[0] = wb_ba5_bit0 ; + end + {2'b01, `W_AM5_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_TA5_ADDR}: + begin + r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + end + {2'b01, `W_ERR_CS_ADDR}: r_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/ + wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ; + {2'b01, `W_ERR_ADDR_ADDR}: r_conf_data_out = wb_err_addr ; + {2'b01, `W_ERR_DATA_ADDR}: r_conf_data_out = wb_err_data ; + + {2'b01, `CNF_ADDR_ADDR}: r_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ; + // `CNF_DATA_ADDR: implemented elsewhere !!! + // `INT_ACK_ADDR : implemented elsewhere !!! + {2'b01, `ICR_ADDR}: r_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ; + {2'b01, `ISR_ADDR}: r_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ; + + `ifdef PCI_SPOCI + 8'hff: r_conf_data_out = {spoci_cs_nack, 5'h0, spoci_cs_write, spoci_cs_read, + 5'h0, spoci_cs_adr[10:8], + spoci_cs_adr[7:0], + spoci_cs_dat[7:0]} ; + `endif + default : r_conf_data_out = 32'h0000_0000 ; + endcase + end + +`endif + +`ifdef PCI_SPOCI +reg [ 7: 0] spoci_reg_num ; +wire [11: 0] w_conf_address = init_complete ? w_conf_address_in : {2'b00, spoci_reg_num, 2'b00} ; +`else +wire [11: 0] w_conf_address = w_conf_address_in ; +wire [ 7: 0] spoci_reg_num = 'hff ; +`endif + +always@(w_conf_address or + status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or + latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or + r_subsys_id or r_subsys_vendor_id or r_max_lat or r_min_gnt or + pci_ba0_bit31_8 or + pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or + pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8 or pci_ba1_bit0 or + pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or + pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or + pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or + pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or + interrupt_line or + pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or + pci_err_addr or pci_err_data or + wb_ba0_bit31_12 or wb_ba0_bit0 or + wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or + wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or + wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or + wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or + wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or + wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or + wb_err_addr or wb_err_data or + cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0 + + `ifdef PCI_CPCI_HS_IMPLEMENT + or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id + `endif + + `ifdef PCI_SPOCI + or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat + `endif + ) +begin + case (w_conf_address[9:2]) + 8'h0: + begin + w_conf_data_out = { r_device_id, r_vendor_id } ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register + end + 8'h1: // w_reg_select_dec bit 0 + begin + w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, + 4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ; + w_reg_select_dec = 57'h000_0000_0000_0001 ; + end + 8'h2: + begin + w_conf_data_out = { r_class_code, r_revision_id } ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register + end + 8'h3: // w_reg_select_dec bit 1 + begin + w_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ; + w_reg_select_dec = 57'h000_0000_0000_0002 ; + end + 8'h4: // w_reg_select_dec bit 4 + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; + `else + w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address + end + 8'h5: // w_reg_select_dec bit 8 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; + w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address + end + 8'h6: // w_reg_select_dec bit 12 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; + w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address + end + 8'h7: // w_reg_select_dec bit 16 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; + w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address + end + 8'h8: // w_reg_select_dec bit 20 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; + w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address + end + 8'h9: // w_reg_select_dec bit 24 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; + w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address + end + 8'hB: + begin + w_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; + end + +`ifdef PCI_CPCI_HS_IMPLEMENT + 8'hD: + begin + w_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register + end +`endif + 8'hf: // w_reg_select_dec bit 2 + begin + w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ; + w_reg_select_dec = 57'h000_0000_0000_0004 ; + end +`ifdef PCI_CPCI_HS_IMPLEMENT + (`PCI_CAP_PTR_VAL >> 2): + begin + w_reg_select_dec = 57'h100_0000_0000_0000 ; + w_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ; + end +`endif + {2'b01, `P_IMG_CTRL0_ADDR}: // w_reg_select_dec bit 3 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0000_0008 ; + end + {2'b01, `P_BA0_ADDR}: // w_reg_select_dec bit 4 + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; + `else + w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address + end + {2'b01, `P_AM0_ADDR}: // w_reg_select_dec bit 5 + begin + `ifdef HOST + `ifdef NO_CNF_IMAGE + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + `else + w_conf_data_out[31:12] = pci_am0[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + `endif + + `ifdef GUEST + w_conf_data_out[31:12] = pci_am0[31:12] ; + w_conf_data_out[11: 0] = 12'h000 ; + `endif + w_reg_select_dec = 57'h000_0000_0000_0020 ; + end + {2'b01, `P_TA0_ADDR}: // w_reg_select_dec bit 6 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0000_0040 ; + end + {2'b01, `P_IMG_CTRL1_ADDR}: // w_reg_select_dec bit 7 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0000_0080 ; + end + {2'b01, `P_BA1_ADDR}: // w_reg_select_dec bit 8 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; + w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address + end + {2'b01, `P_AM1_ADDR}: // w_reg_select_dec bit 9 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0000_0200 ; + end + {2'b01, `P_TA1_ADDR}: // w_reg_select_dec bit 10 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0000_0400 ; + end + {2'b01, `P_IMG_CTRL2_ADDR}: // w_reg_select_dec bit 11 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0000_0800 ; + end + {2'b01, `P_BA2_ADDR}: // w_reg_select_dec bit 12 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; + w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address + end + {2'b01, `P_AM2_ADDR}: // w_reg_select_dec bit 13 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0000_2000 ; + end + {2'b01, `P_TA2_ADDR}: // w_reg_select_dec bit 14 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0000_4000 ; + end + {2'b01, `P_IMG_CTRL3_ADDR}: // w_reg_select_dec bit 15 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0000_8000 ; + end + {2'b01, `P_BA3_ADDR}: // w_reg_select_dec bit 16 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; + w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address + end + {2'b01, `P_AM3_ADDR}: // w_reg_select_dec bit 17 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0002_0000 ; + end + {2'b01, `P_TA3_ADDR}: // w_reg_select_dec bit 18 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0004_0000 ; + end + {2'b01, `P_IMG_CTRL4_ADDR}: // w_reg_select_dec bit 19 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0008_0000 ; + end + {2'b01, `P_BA4_ADDR}: // w_reg_select_dec bit 20 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; + w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address + end + {2'b01, `P_AM4_ADDR}: // w_reg_select_dec bit 21 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0020_0000 ; + end + {2'b01, `P_TA4_ADDR}: // w_reg_select_dec bit 22 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0040_0000 ; + end + {2'b01, `P_IMG_CTRL5_ADDR}: // w_reg_select_dec bit 23 + begin + w_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ; + w_reg_select_dec = 57'h000_0000_0080_0000 ; + end + {2'b01, `P_BA5_ADDR}: // w_reg_select_dec bit 24 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & + pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; + w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address + end + {2'b01, `P_AM5_ADDR}: // w_reg_select_dec bit 25 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0200_0000 ; + end + {2'b01, `P_TA5_ADDR}: // w_reg_select_dec bit 26 + begin + w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0000_0400_0000 ; + end + {2'b01, `P_ERR_CS_ADDR}: // w_reg_select_dec bit 27 + begin + w_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9, + pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ; + w_reg_select_dec = 57'h000_0000_0800_0000 ; + end + {2'b01, `P_ERR_ADDR_ADDR}: // w_reg_select_dec bit 28 + begin + w_conf_data_out = pci_err_addr ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_1000_0000 ; + end + {2'b01, `P_ERR_DATA_ADDR}: // w_reg_select_dec bit 29 + begin + w_conf_data_out = pci_err_data ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_2000_0000 ; + end + // WB slave - configuration space + {2'b01, `WB_CONF_SPC_BAR_ADDR}: + begin + w_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register + end + {2'b01, `W_IMG_CTRL1_ADDR}: // w_reg_select_dec bit 30 + begin + w_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ; + w_reg_select_dec = 57'h000_0000_4000_0000 ; + end + {2'b01, `W_BA1_ADDR}: // w_reg_select_dec bit 31 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = wb_ba1_bit0 ; + w_reg_select_dec = 57'h000_0000_8000_0000 ; + end + {2'b01, `W_AM1_ADDR}: // w_reg_select_dec bit 32 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0001_0000_0000 ; + end + {2'b01, `W_TA1_ADDR}: // w_reg_select_dec bit 33 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0002_0000_0000 ; + end + {2'b01, `W_IMG_CTRL2_ADDR}: // w_reg_select_dec bit 34 + begin + w_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ; + w_reg_select_dec = 57'h000_0004_0000_0000 ; + end + {2'b01, `W_BA2_ADDR}: // w_reg_select_dec bit 35 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = wb_ba2_bit0 ; + w_reg_select_dec = 57'h000_0008_0000_0000 ; + end + {2'b01, `W_AM2_ADDR}: // w_reg_select_dec bit 36 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0010_0000_0000 ; + end + {2'b01, `W_TA2_ADDR}: // w_reg_select_dec bit 37 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0020_0000_0000 ; + end + {2'b01, `W_IMG_CTRL3_ADDR}: // w_reg_select_dec bit 38 + begin + w_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ; + w_reg_select_dec = 57'h000_0040_0000_0000 ; + end + {2'b01, `W_BA3_ADDR}: // w_reg_select_dec bit 39 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = wb_ba3_bit0 ; + w_reg_select_dec = 57'h000_0080_0000_0000 ; + end + {2'b01, `W_AM3_ADDR}: // w_reg_select_dec bit 40 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0100_0000_0000 ; + end + {2'b01, `W_TA3_ADDR}: // w_reg_select_dec bit 41 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_0200_0000_0000 ; + end + {2'b01, `W_IMG_CTRL4_ADDR}: // w_reg_select_dec bit 42 + begin + w_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ; + w_reg_select_dec = 57'h000_0400_0000_0000 ; + end + {2'b01, `W_BA4_ADDR}: // w_reg_select_dec bit 43 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = wb_ba4_bit0 ; + w_reg_select_dec = 57'h000_0800_0000_0000 ; + end + {2'b01, `W_AM4_ADDR}: // w_reg_select_dec bit 44 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_1000_0000_0000 ; + end + {2'b01, `W_TA4_ADDR}: // w_reg_select_dec bit 45 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h000_2000_0000_0000 ; + end + {2'b01, `W_IMG_CTRL5_ADDR}: // w_reg_select_dec bit 46 + begin + w_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ; + w_reg_select_dec = 57'h000_4000_0000_0000 ; + end + {2'b01, `W_BA5_ADDR}: // w_reg_select_dec bit 47 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & + wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; + w_conf_data_out[0] = wb_ba5_bit0 ; + w_reg_select_dec = 57'h000_8000_0000_0000 ; + end + {2'b01, `W_AM5_ADDR}: // w_reg_select_dec bit 48 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h001_0000_0000_0000 ; + end + {2'b01, `W_TA5_ADDR}: // w_reg_select_dec bit 49 + begin + w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; + w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; + w_reg_select_dec = 57'h002_0000_0000_0000 ; + end + {2'b01, `W_ERR_CS_ADDR}: // w_reg_select_dec bit 50 + begin + w_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/ + wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ; + w_reg_select_dec = 57'h004_0000_0000_0000 ; + end + {2'b01, `W_ERR_ADDR_ADDR}: // w_reg_select_dec bit 51 + begin + w_conf_data_out = wb_err_addr ; + w_reg_select_dec = 57'h008_0000_0000_0000 ; + end + {2'b01, `W_ERR_DATA_ADDR}: // w_reg_select_dec bit 52 + begin + w_conf_data_out = wb_err_data ; + w_reg_select_dec = 57'h010_0000_0000_0000 ; + end + {2'b01, `CNF_ADDR_ADDR}: // w_reg_select_dec bit 53 + begin + w_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ; + w_reg_select_dec = 57'h020_0000_0000_0000 ; + end + // `CNF_DATA_ADDR: implemented elsewhere !!! + // `INT_ACK_ADDR: implemented elsewhere !!! + {2'b01, `ICR_ADDR}: // w_reg_select_dec bit 54 + begin + w_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ; + w_reg_select_dec = 57'h040_0000_0000_0000 ; + end + {2'b01, `ISR_ADDR}: // w_reg_select_dec bit 55 + begin + w_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ; + w_reg_select_dec = 57'h080_0000_0000_0000 ; + end + +`ifdef PCI_SPOCI + 8'hff: + begin + w_conf_data_out = {spoci_cs_nack, 5'h0, spoci_cs_write, spoci_cs_read, + 5'h0, spoci_cs_adr[10:8], + spoci_cs_adr[7:0], + spoci_cs_dat[7:0]} ; + + // this register is implemented separate from other registers, because + // it has special features implemented + w_reg_select_dec = 57'h000_0000_0000_0000 ; + end +`endif + + default: + begin + w_conf_data_out = 32'h0000_0000 ; + w_reg_select_dec = 57'h000_0000_0000_0000 ; + end + endcase +end + +`ifdef PCI_SPOCI +reg init_we ; +reg init_cfg_done ; +reg [31: 0] spoci_dat ; +wire [31: 0] w_conf_data = init_cfg_done ? w_conf_data_in : spoci_dat ; +wire [ 3: 0] w_byte_en = init_cfg_done ? w_byte_en_in : 4'b0000 ; +`else +wire init_we = 1'b0 ; +wire init_cfg_done = 1'b1 ; +wire [31: 0] w_conf_data = w_conf_data_in ; +wire [ 3: 0] w_byte_en = w_byte_en_in ; +wire [31: 0] spoci_dat = 'h0000_0000 ; +`endif + +// Reduced write data for BASE, MASK and TRANSLATION registers of PCI and WB images +assign w_conf_pdata_reduced[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = w_conf_data[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign w_conf_pdata_reduced[(31-`PCI_NUM_OF_DEC_ADDR_LINES): 0] = 0 ; +assign w_conf_wdata_reduced[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = w_conf_data[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign w_conf_wdata_reduced[(31-`WB_NUM_OF_DEC_ADDR_LINES): 0] = 0 ; + +wire w_we = w_we_i | init_we ; + +always@(posedge w_clock or posedge reset) +begin + // Here are implemented all registers that are reset with RESET signal otherwise they can be normaly written!!! + // Registers that are commented are implemented after this alwasy statement, because they are e.g. reset with + // RESET signal, set with some status signal and they are erased with writting '1' into them !!! + if (reset) + begin + /*status_bit15_11 ; status_bit8 ;*/ command_bit8 <= 1'h0 ; command_bit6 <= 1'h0 ; command_bit2_0 <= 3'h0 ; + latency_timer <= 8'h00 ; cache_line_size_reg <= 8'h00 ; + // ALL pci_base address registers are the same as pci_baX registers ! + interrupt_line <= 8'h00 ; + + `ifdef HOST + `ifdef NO_CNF_IMAGE // if PCI bridge is HOST and IMAGE0 is assigned as general image space + `ifdef PCI_IMAGE0 + pci_img_ctrl0_bit2_1 <= {`PCI_AT_EN0, 1'b0} ; + pci_ba0_bit31_8 <= 24'h0000_00 ; + pci_ba0_bit0 <= `PCI_BA0_MEM_IO ; + pci_am0 <= `PCI_AM0 ; + pci_ta0 <= `PCI_TA0 ;//fr2201 translation address + `endif + `else + pci_ba0_bit31_8 <= 24'h0000_00 ; + `endif + `endif + + `ifdef GUEST + pci_ba0_bit31_8 <= 24'h0000_00 ; + `endif + + pci_img_ctrl1_bit2_1 <= {`PCI_AT_EN1, 1'b0} ; + + pci_ba1_bit31_8 <= 24'h0000_00 ; + `ifdef HOST + pci_ba1_bit0 <= `PCI_BA1_MEM_IO ; + `endif + pci_am1 <= `PCI_AM1; + pci_ta1 <= `PCI_TA1 ;//FR2201 translation address ; + `ifdef PCI_IMAGE2 + + pci_img_ctrl2_bit2_1 <= {`PCI_AT_EN2, 1'b0} ; + + pci_ba2_bit31_8 <= 24'h0000_00 ; + `ifdef HOST + pci_ba2_bit0 <= `PCI_BA2_MEM_IO ; + `endif + pci_am2 <= `PCI_AM2; + pci_ta2 <= `PCI_TA2 ;//FR2201 translation address ; + `endif + `ifdef PCI_IMAGE3 + + pci_img_ctrl3_bit2_1 <= {`PCI_AT_EN3, 1'b0} ; //FR2201 when defined enabled + + pci_ba3_bit31_8 <= 24'h0000_00 ; + `ifdef HOST + pci_ba3_bit0 <= `PCI_BA3_MEM_IO ; + `endif + pci_am3 <= `PCI_AM3; + pci_ta3 <= `PCI_TA3 ;//FR2201 translation address ; + `endif + `ifdef PCI_IMAGE4 + + pci_img_ctrl4_bit2_1 <= {`PCI_AT_EN4, 1'b0} ; //FR2201 when defined enabled + + pci_ba4_bit31_8 <= 24'h0000_00 ; + `ifdef HOST + pci_ba4_bit0 <= `PCI_BA4_MEM_IO ; + `endif + pci_am4 <= `PCI_AM4; + pci_ta4 <= `PCI_TA4 ;//FR2201 translation address ; + `endif + `ifdef PCI_IMAGE5 + + pci_img_ctrl5_bit2_1 <= {`PCI_AT_EN5, 1'b0} ; //FR2201 when defined enabled + + pci_ba5_bit31_8 <= 24'h0000_00 ; + `ifdef HOST + pci_ba5_bit0 <= `PCI_BA5_MEM_IO ; + `endif + pci_am5 <= `PCI_AM5; //FR2201 pci_am0 + pci_ta5 <= `PCI_TA5 ;//FR2201 translation address ; + `endif + /*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ; + /*pci_err_addr ;*/ + /*pci_err_data ;*/ + // + wb_img_ctrl1_bit2_0 <= {`WB_AT_EN1, 2'b00} ; + + wb_ba1_bit31_12 <=`WB_BA1; //FR2201 Address bar + wb_ba1_bit0 <=`WB_BA1_MEM_IO;// + wb_am1 <= `WB_AM1 ;//FR2201 Address mask + wb_ta1 <= `WB_TA1 ;//FR2201 20'h0000_0 ; + `ifdef WB_IMAGE2 + wb_img_ctrl2_bit2_0 <= {`WB_AT_EN2, 2'b00} ; + + wb_ba2_bit31_12 <=`WB_BA2; //FR2201 Address bar + wb_ba2_bit0 <=`WB_BA2_MEM_IO;// + wb_am2 <=`WB_AM2 ;//FR2201 Address mask + wb_ta2 <=`WB_TA2 ;//FR2201 translation address ; + `endif + `ifdef WB_IMAGE3 + wb_img_ctrl3_bit2_0 <= {`WB_AT_EN3, 2'b00} ; + + wb_ba3_bit31_12 <=`WB_BA3; //FR2201 Address bar + wb_ba3_bit0 <=`WB_BA3_MEM_IO;// + wb_am3 <=`WB_AM3 ;//FR2201 Address mask + wb_ta3 <=`WB_TA3 ;//FR2201 translation address ; + `endif + `ifdef WB_IMAGE4 + wb_img_ctrl4_bit2_0 <= {`WB_AT_EN4, 2'b00} ; + + wb_ba4_bit31_12 <=`WB_BA4; //FR2201 Address bar + wb_ba4_bit0 <=`WB_BA4_MEM_IO;// + wb_am4 <=`WB_AM4 ;//FR2201 Address mask + wb_ta4 <=`WB_TA4 ;//FR2201 translation address ; + `endif + `ifdef WB_IMAGE5 + wb_img_ctrl5_bit2_0 <= {`WB_AT_EN5, 2'b00} ; + + wb_ba5_bit31_12 <=`WB_BA5; //FR2201 Address bar ; + wb_ba5_bit0 <=`WB_BA5_MEM_IO;//FR2201 1'h0 ; + wb_am5 <=`WB_AM5 ;//FR2201 Address mask + wb_ta5 <=`WB_TA5 ;//FR2201 translation address ; + `endif + /*wb_err_cs_bit31_24 ; wb_err_cs_bit10 ; wb_err_cs_bit9 ; wb_err_cs_bit8 ;*/ wb_err_cs_bit0 <= 1'h0 ; + /*wb_err_addr ;*/ + /*wb_err_data ;*/ + + `ifdef HOST + cnf_addr_bit23_2 <= 22'h0000_00 ; cnf_addr_bit0 <= 1'h0 ; + `endif + + icr_bit31 <= 1'h0 ; + `ifdef HOST + icr_bit2_0 <= 3'h0 ; + icr_bit4_3 <= 2'h0 ; + `else + icr_bit2_0[2:0] <= 3'h0 ; + `endif + /*isr_bit4_3 ; isr_bit2_0 ;*/ + + // Not register bit; used only internally after reset! + init_complete <= 1'b0 ; + + `ifdef GUEST + rst_inactive_sync <= 1'b0 ; + rst_inactive <= 1'b0 ; + `endif + + `ifdef PCI_CPCI_HS_IMPLEMENT + /*hs_ins hs_ext*/ hs_loo <= 1'b0; hs_eim <= 1'b0; + // Not register bits; used only internally after reset! + /*hs_ins_armed hs_ext_armed*/ + `endif + end +/* ----------------------------------------------------------------------------------------------------------- +Following register bits should have asynchronous RESET & SET! That is why they are IMPLEMENTED separately +after this ALWAYS block!!! (for every register bit, there are two D-FF implemented) + status_bit15_11[15] <= 1'b1 ; + status_bit15_11[14] <= 1'b1 ; + status_bit15_11[13] <= 1'b1 ; + status_bit15_11[12] <= 1'b1 ; + status_bit15_11[11] <= 1'b1 ; + status_bit8 <= 1'b1 ; + pci_err_cs_bit10 <= 1'b1 ; + pci_err_cs_bit9 <= 1'b1 ; + pci_err_cs_bit8 <= 1'b1 ; + pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ; + pci_err_addr <= pci_error_addr ; + pci_err_data <= pci_error_data ; + wb_err_cs_bit10 <= 1'b1 ; + wb_err_cs_bit9 <= 1'b1 ; + wb_err_cs_bit8 <= 1'b1 ; + wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ; + wb_err_addr <= wb_error_addr ; + wb_err_data <= wb_error_data ; + isr_bit4_0[4] <= 1'b1 & icr_bit4_0[4] ; + isr_bit4_0[3] <= 1'b1 & icr_bit4_0[3] ; + isr_bit4_0[2] <= 1'b1 & icr_bit4_0[2] ; + isr_bit4_0[1] <= 1'b1 & icr_bit4_0[1] ; + isr_bit4_0[0] <= 1'b1 & icr_bit4_0[0] ; + + hs_ins; hs_ext; +-----------------------------------------------------------------------------------------------------------*/ + // Here follows normal writting to registers (only to their valid bits) ! + else + begin + if (w_we) + begin + // PCI header - configuration space + if (w_reg_select_dec[0]) // w_conf_address[5:2] = 4'h1: + begin + if (~w_byte_en[1]) + command_bit8 <= w_conf_data[8] ; + if (~w_byte_en[0]) + begin + command_bit6 <= w_conf_data[6] ; + command_bit2_0 <= w_conf_data[2:0] ; + end + end + if (w_reg_select_dec[1]) // w_conf_address[5:2] = 4'h3: + begin + if (~w_byte_en[1]) + latency_timer <= w_conf_data[15:8] ; + if (~w_byte_en[0]) + cache_line_size_reg <= w_conf_data[7:0] ; + end +// if (w_reg_select_dec[4]) // w_conf_address[5:2] = 4'h4: +// Also used with IMAGE0 + +// if (w_reg_select_dec[8]) // w_conf_address[5:2] = 4'h5: +// Also used with IMAGE1 + +// if (w_reg_select_dec[12]) // w_conf_address[5:2] = 4'h6: +// Also used with IMAGE2 + +// if (w_reg_select_dec[16]) // w_conf_address[5:2] = 4'h7: +// Also used with IMAGE3 + +// if (w_reg_select_dec[20]) // w_conf_address[5:2] = 4'h8: +// Also used with IMAGE4 + +// if (w_reg_select_dec[24]) // w_conf_address[5:2] = 4'h9: +// Also used with IMAGE5 and IMAGE6 + if (w_reg_select_dec[2]) // w_conf_address[5:2] = 4'hf: + begin + if (~w_byte_en[0]) + interrupt_line <= w_conf_data[7:0] ; + end + // PCI target - configuration space +`ifdef HOST + `ifdef NO_CNF_IMAGE + `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space + if (w_reg_select_dec[3]) // case (w_conf_address[7:2]) = `P_IMG_CTRL0_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl0_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: + begin + if (~w_byte_en[3]) + pci_ba0_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba0_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba0_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + if (~w_byte_en[0]) + pci_ba0_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[5]) // case (w_conf_address[7:2]) = `P_AM0_ADDR: + begin + if (~w_byte_en[3]) + pci_am0[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am0[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am0[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[6]) // case (w_conf_address[7:2]) = `P_TA0_ADDR: + begin + if (~w_byte_en[3]) + pci_ta0[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta0[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta0[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + `endif + `else + if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: + begin + if (~w_byte_en[3]) + pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ; + if (~w_byte_en[2]) + pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ; + if (~w_byte_en[1]) + pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ; + end + `endif +`endif + +`ifdef GUEST + if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: + begin + if (~w_byte_en[3]) + pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ; + if (~w_byte_en[2]) + pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ; + if (~w_byte_en[1]) + pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ; + end +`endif + if (w_reg_select_dec[7]) // case (w_conf_address[7:2]) = `P_IMG_CTRL1_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl1_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[8]) // case (w_conf_address[7:2]) = `P_BA1_ADDR: + begin + if (~w_byte_en[3]) + pci_ba1_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba1_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba1_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + `ifdef HOST + if (~w_byte_en[0]) + pci_ba1_bit0 <= w_conf_data[0] ; + `endif + end + if (w_reg_select_dec[9]) // case (w_conf_address[7:2]) = `P_AM1_ADDR: + begin + if (~w_byte_en[3]) + pci_am1[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am1[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am1[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[10]) // case (w_conf_address[7:2]) = `P_TA1_ADDR: + begin + if (~w_byte_en[3]) + pci_ta1[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta1[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta1[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end +`ifdef PCI_IMAGE2 + if (w_reg_select_dec[11]) // case (w_conf_address[7:2]) = `P_IMG_CTRL2_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl2_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[12]) // case (w_conf_address[7:2]) = `P_BA2_ADDR: + begin + if (~w_byte_en[3]) + pci_ba2_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba2_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba2_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + `ifdef HOST + if (~w_byte_en[0]) + pci_ba2_bit0 <= w_conf_data[0] ; + `endif + end + if (w_reg_select_dec[13]) // case (w_conf_address[7:2]) = `P_AM2_ADDR: + begin + if (~w_byte_en[3]) + pci_am2[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am2[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am2[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[14]) // case (w_conf_address[7:2]) = `P_TA2_ADDR: + begin + if (~w_byte_en[3]) + pci_ta2[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta2[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta2[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end +`endif +`ifdef PCI_IMAGE3 + if (w_reg_select_dec[15]) // case (w_conf_address[7:2]) = `P_IMG_CTRL3_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl3_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[16]) // case (w_conf_address[7:2]) = `P_BA3_ADDR: + begin + if (~w_byte_en[3]) + pci_ba3_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba3_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba3_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + `ifdef HOST + if (~w_byte_en[0]) + pci_ba3_bit0 <= w_conf_data[0] ; + `endif + end + if (w_reg_select_dec[17]) // case (w_conf_address[7:2]) = `P_AM3_ADDR: + begin + if (~w_byte_en[3]) + pci_am3[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am3[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am3[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[18]) // case (w_conf_address[7:2]) = `P_TA3_ADDR: + begin + if (~w_byte_en[3]) + pci_ta3[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta3[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta3[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end +`endif +`ifdef PCI_IMAGE4 + if (w_reg_select_dec[19]) // case (w_conf_address[7:2]) = `P_IMG_CTRL4_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl4_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[20]) // case (w_conf_address[7:2]) = `P_BA4_ADDR: + begin + if (~w_byte_en[3]) + pci_ba4_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba4_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba4_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + `ifdef HOST + if (~w_byte_en[0]) + pci_ba4_bit0 <= w_conf_data[0] ; + `endif + end + if (w_reg_select_dec[21]) // case (w_conf_address[7:2]) = `P_AM4_ADDR: + begin + if (~w_byte_en[3]) + pci_am4[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am4[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am4[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[22]) // case (w_conf_address[7:2]) = `P_TA4_ADDR: + begin + if (~w_byte_en[3]) + pci_ta4[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta4[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta4[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end +`endif +`ifdef PCI_IMAGE5 + if (w_reg_select_dec[23]) // case (w_conf_address[7:2]) = `P_IMG_CTRL5_ADDR: + begin + if (~w_byte_en[0]) + pci_img_ctrl5_bit2_1 <= w_conf_data[2:1] ; + end + if (w_reg_select_dec[24]) // case (w_conf_address[7:2]) = `P_BA5_ADDR: + begin + if (~w_byte_en[3]) + pci_ba5_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ba5_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ba5_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; + `ifdef HOST + if (~w_byte_en[0]) + pci_ba5_bit0 <= w_conf_data[0] ; + `endif + end + if (w_reg_select_dec[25]) // case (w_conf_address[7:2]) = `P_AM5_ADDR: + begin + if (~w_byte_en[3]) + pci_am5[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_am5[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_am5[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end + if (w_reg_select_dec[26]) // case (w_conf_address[7:2]) = `P_TA5_ADDR: + begin + if (~w_byte_en[3]) + pci_ta5[31:24] <= w_conf_pdata_reduced[31:24] ; + if (~w_byte_en[2]) + pci_ta5[23:16] <= w_conf_pdata_reduced[23:16] ; + if (~w_byte_en[1]) + pci_ta5[15: 8] <= w_conf_pdata_reduced[15: 8] ; + end +`endif + if (w_reg_select_dec[27]) // case (w_conf_address[7:2]) = `P_ERR_CS_ADDR: + begin + if (~w_byte_en[0]) + pci_err_cs_bit0 <= w_conf_data[0] ; + end + // WB slave - configuration space + if (w_reg_select_dec[30]) // case (w_conf_address[7:2]) = `W_IMG_CTRL1_ADDR: + begin + if (~w_byte_en[0]) + wb_img_ctrl1_bit2_0 <= w_conf_data[2:0] ; + end + if (w_reg_select_dec[31]) // case (w_conf_address[7:2]) = `W_BA1_ADDR: + begin + if (~w_byte_en[3]) + wb_ba1_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ba1_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ba1_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; + if (~w_byte_en[0]) + wb_ba1_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[32]) // case (w_conf_address[7:2]) = `W_AM1_ADDR: + begin + if (~w_byte_en[3]) + wb_am1[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_am1[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_am1[15:12] <= w_conf_wdata_reduced[15:12] ; + end + if (w_reg_select_dec[33]) // case (w_conf_address[7:2]) = `W_TA1_ADDR: + begin + if (~w_byte_en[3]) + wb_ta1[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ta1[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ta1[15:12] <= w_conf_wdata_reduced[15:12] ; + end +`ifdef WB_IMAGE2 + if (w_reg_select_dec[34]) // case (w_conf_address[7:2]) = `W_IMG_CTRL2_ADDR: + begin + if (~w_byte_en[0]) + wb_img_ctrl2_bit2_0 <= w_conf_data[2:0] ; + end + if (w_reg_select_dec[35]) // case (w_conf_address[7:2]) = `W_BA2_ADDR: + begin + if (~w_byte_en[3]) + wb_ba2_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ba2_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ba2_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; + if (~w_byte_en[0]) + wb_ba2_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[36]) // case (w_conf_address[7:2]) = `W_AM2_ADDR: + begin + if (~w_byte_en[3]) + wb_am2[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_am2[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_am2[15:12] <= w_conf_wdata_reduced[15:12] ; + end + if (w_reg_select_dec[37]) // case (w_conf_address[7:2]) = `W_TA2_ADDR: + begin + if (~w_byte_en[3]) + wb_ta2[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ta2[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ta2[15:12] <= w_conf_wdata_reduced[15:12] ; + end +`endif +`ifdef WB_IMAGE3 + if (w_reg_select_dec[38]) // case (w_conf_address[7:2]) = `W_IMG_CTRL3_ADDR: + begin + if (~w_byte_en[0]) + wb_img_ctrl3_bit2_0 <= w_conf_data[2:0] ; + end + if (w_reg_select_dec[39]) // case (w_conf_address[7:2]) = `W_BA3_ADDR: + begin + if (~w_byte_en[3]) + wb_ba3_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ba3_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ba3_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; + if (~w_byte_en[0]) + wb_ba3_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[40]) // case (w_conf_address[7:2]) = `W_AM3_ADDR: + begin + if (~w_byte_en[3]) + wb_am3[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_am3[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_am3[15:12] <= w_conf_wdata_reduced[15:12] ; + end + if (w_reg_select_dec[41]) // case (w_conf_address[7:2]) = `W_TA3_ADDR: + begin + if (~w_byte_en[3]) + wb_ta3[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ta3[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ta3[15:12] <= w_conf_wdata_reduced[15:12] ; + end +`endif +`ifdef WB_IMAGE4 + if (w_reg_select_dec[42]) // case (w_conf_address[7:2]) = `W_IMG_CTRL4_ADDR: + begin + if (~w_byte_en[0]) + wb_img_ctrl4_bit2_0 <= w_conf_data[2:0] ; + end + if (w_reg_select_dec[43]) // case (w_conf_address[7:2]) = `W_BA4_ADDR: + begin + if (~w_byte_en[3]) + wb_ba4_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ba4_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ba4_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; + if (~w_byte_en[0]) + wb_ba4_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[44]) // case (w_conf_address[7:2]) = `W_AM4_ADDR: + begin + if (~w_byte_en[3]) + wb_am4[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_am4[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_am4[15:12] <= w_conf_wdata_reduced[15:12] ; + end + if (w_reg_select_dec[45]) // case (w_conf_address[7:2]) = `W_TA4_ADDR: + begin + if (~w_byte_en[3]) + wb_ta4[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ta4[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ta4[15:12] <= w_conf_wdata_reduced[15:12] ; + end +`endif +`ifdef WB_IMAGE5 + if (w_reg_select_dec[46]) // case (w_conf_address[7:2]) = `W_IMG_CTRL5_ADDR: + begin + if (~w_byte_en[0]) + wb_img_ctrl5_bit2_0 <= w_conf_data[2:0] ; + end + if (w_reg_select_dec[47]) // case (w_conf_address[7:2]) = `W_BA5_ADDR: + begin + if (~w_byte_en[3]) + wb_ba5_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ba5_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ba5_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; + if (~w_byte_en[0]) + wb_ba5_bit0 <= w_conf_data[0] ; + end + if (w_reg_select_dec[48]) // case (w_conf_address[7:2]) = `W_AM5_ADDR: + begin + if (~w_byte_en[3]) + wb_am5[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_am5[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_am5[15:12] <= w_conf_wdata_reduced[15:12] ; + end + if (w_reg_select_dec[49]) // case (w_conf_address[7:2]) = `W_TA5_ADDR: + begin + if (~w_byte_en[3]) + wb_ta5[31:24] <= w_conf_wdata_reduced[31:24] ; + if (~w_byte_en[2]) + wb_ta5[23:16] <= w_conf_wdata_reduced[23:16] ; + if (~w_byte_en[1]) + wb_ta5[15:12] <= w_conf_wdata_reduced[15:12] ; + end +`endif + if (w_reg_select_dec[50]) // case (w_conf_address[7:2]) = `W_ERR_CS_ADDR: + begin + if (~w_byte_en[0]) + wb_err_cs_bit0 <= w_conf_data[0] ; + end + +`ifdef HOST + if (w_reg_select_dec[53]) // case (w_conf_address[7:2]) = `CNF_ADDR_ADDR: + begin + if (~w_byte_en[2]) + cnf_addr_bit23_2[23:16] <= w_conf_data[23:16] ; + if (~w_byte_en[1]) + cnf_addr_bit23_2[15:8] <= w_conf_data[15:8] ; + if (~w_byte_en[0]) + begin + cnf_addr_bit23_2[7:2] <= w_conf_data[7:2] ; + cnf_addr_bit0 <= w_conf_data[0] ; + end + end +`endif + // `CNF_DATA_ADDR: implemented elsewhere !!! + // `INT_ACK_ADDR : implemented elsewhere !!! + if (w_reg_select_dec[54]) // case (w_conf_address[7:2]) = `ICR_ADDR: + begin + if (~w_byte_en[3]) + icr_bit31 <= w_conf_data[31] ; + + if (~w_byte_en[0]) + begin +`ifdef HOST + icr_bit4_3 <= w_conf_data[4:3] ; + icr_bit2_0 <= w_conf_data[2:0] ; +`else + icr_bit2_0[2:0] <= w_conf_data[2:0] ; +`endif + end + end + +`ifdef PCI_CPCI_HS_IMPLEMENT + if (w_reg_select_dec[56]) + begin + if (~w_byte_en[2]) + begin + hs_loo <= w_conf_data[19]; + hs_eim <= w_conf_data[17]; + end + end +`endif + end // end of we + + // Not register bits; used only internally after reset! + `ifdef GUEST + rst_inactive_sync <= 1'b1 ; + rst_inactive <= rst_inactive_sync ; + `endif + + if (rst_inactive & ~init_complete & init_cfg_done) + init_complete <= 1'b1 ; + end +end + +// implementation of read only device identification registers +always@(posedge w_clock or posedge reset) +begin + if (reset) + begin + r_vendor_id <= `HEADER_VENDOR_ID ; + r_device_id <= `HEADER_DEVICE_ID ; + r_revision_id <= `HEADER_REVISION_ID ; + r_subsys_vendor_id <= `HEADER_SUBSYS_VENDOR_ID ; + r_subsys_id <= `HEADER_SUBSYS_ID ; + r_max_lat <= `HEADER_MAX_LAT ; + r_min_gnt <= `HEADER_MIN_GNT ; + end else + begin + if (init_we) + begin + if (spoci_reg_num == 'h0) + begin + r_vendor_id <= spoci_dat[15: 0] ; + r_device_id <= spoci_dat[31:16] ; + end + + if (spoci_reg_num == 'hB) + begin + r_subsys_vendor_id <= spoci_dat[15: 0] ; + r_subsys_id <= spoci_dat[31:16] ; + end + + if (spoci_reg_num == 'h2) + begin + r_revision_id <= spoci_dat[ 7: 0] ; + end + + if (spoci_reg_num == 'hF) + begin + r_max_lat <= spoci_dat[31:24] ; + r_min_gnt <= spoci_dat[23:16] ; + end + end + end +end + +// This signals are synchronous resets for registers, whic occures when asynchronous RESET is '1' or +// data '1' is synchronously written into them! +reg delete_status_bit15 ; +reg delete_status_bit14 ; +reg delete_status_bit13 ; +reg delete_status_bit12 ; +reg delete_status_bit11 ; +reg delete_status_bit8 ; +reg delete_pci_err_cs_bit8 ; +reg delete_wb_err_cs_bit8 ; +reg delete_isr_bit4 ; +reg delete_isr_bit3 ; +reg delete_isr_bit2 ; +reg delete_isr_bit1 ; + +// This are aditional register bits, which are resets when their value is '1' !!! +always@(w_we or w_reg_select_dec or w_conf_data or w_byte_en) +begin +// I' is written into, then it also sets signals to '1' + delete_status_bit15 = w_conf_data[31] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_status_bit14 = w_conf_data[30] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_status_bit13 = w_conf_data[29] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_status_bit12 = w_conf_data[28] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_status_bit11 = w_conf_data[27] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_status_bit8 = w_conf_data[24] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; + delete_pci_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[27] ; + delete_wb_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[50] ; + delete_isr_bit4 = w_conf_data[4] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; + delete_isr_bit3 = w_conf_data[3] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; + delete_isr_bit2 = w_conf_data[2] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; + delete_isr_bit1 = w_conf_data[1] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; +end + +// STATUS BITS of PCI Header status register +`ifdef SYNCHRONEOUS_CLOCK_DOMAINS + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[15] <= 1'b0 ; + else + begin + if (perr_in) // Synchronous set + status_bit15_11[15] <= 1'b1 ; + else if (delete_status_bit15) // Synchronous reset + status_bit15_11[15] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[14] <= 1'b0 ; + else + begin + if (serr_in) // Synchronous set + status_bit15_11[14] <= 1'b1 ; + else if (delete_status_bit14) // Synchronous reset + status_bit15_11[14] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[13] <= 1'b0 ; + else + begin + if (master_abort_recv) // Synchronous set + status_bit15_11[13] <= 1'b1 ; + else if (delete_status_bit13) // Synchronous reset + status_bit15_11[13] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[12] <= 1'b0 ; + else + begin + if (target_abort_recv) // Synchronous set + status_bit15_11[12] <= 1'b1 ; + else if (delete_status_bit12) // Synchronous reset + status_bit15_11[12] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[11] <= 1'b0 ; + else + begin + if (target_abort_set) // Synchronous set + status_bit15_11[11] <= 1'b1 ; + else if (delete_status_bit11) // Synchronous reset + status_bit15_11[11] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit8 <= 1'b0 ; + else + begin + if (master_data_par_err) // Synchronous set + status_bit8 <= 1'b1 ; + else if (delete_status_bit8) // Synchronous reset + status_bit8 <= 1'b0 ; + end + end +`else // not SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + reg [15:11] set_status_bit15_11; + reg set_status_bit8; + wire delete_set_status_bit15; + wire delete_set_status_bit14; + wire delete_set_status_bit13; + wire delete_set_status_bit12; + wire delete_set_status_bit11; + wire delete_set_status_bit8; + wire block_set_status_bit15; + wire block_set_status_bit14; + wire block_set_status_bit13; + wire block_set_status_bit12; + wire block_set_status_bit11; + wire block_set_status_bit8; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_15 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit15), + .block_set_out (block_set_status_bit15), + .delete_in (delete_status_bit15) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit15_11[15] <= 1'b0 ; + else + begin + if (perr_in) // Synchronous set + set_status_bit15_11[15] <= 1'b1 ; + else if (delete_set_status_bit15) // Synchronous reset + set_status_bit15_11[15] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_14 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit14), + .block_set_out (block_set_status_bit14), + .delete_in (delete_status_bit14) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit15_11[14] <= 1'b0 ; + else + begin + if (serr_in) // Synchronous set + set_status_bit15_11[14] <= 1'b1 ; + else if (delete_set_status_bit14) // Synchronous reset + set_status_bit15_11[14] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_13 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit13), + .block_set_out (block_set_status_bit13), + .delete_in (delete_status_bit13) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit15_11[13] <= 1'b0 ; + else + begin + if (master_abort_recv) // Synchronous set + set_status_bit15_11[13] <= 1'b1 ; + else if (delete_set_status_bit13) // Synchronous reset + set_status_bit15_11[13] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_12 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit12), + .block_set_out (block_set_status_bit12), + .delete_in (delete_status_bit12) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit15_11[12] <= 1'b0 ; + else + begin + if (target_abort_recv) // Synchronous set + set_status_bit15_11[12] <= 1'b1 ; + else if (delete_set_status_bit12) // Synchronous reset + set_status_bit15_11[12] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_11 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit11), + .block_set_out (block_set_status_bit11), + .delete_in (delete_status_bit11) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit15_11[11] <= 1'b0 ; + else + begin + if (target_abort_set) // Synchronous set + set_status_bit15_11[11] <= 1'b1 ; + else if (delete_set_status_bit11) // Synchronous reset + set_status_bit15_11[11] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_status_8 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_status_bit8), + .block_set_out (block_set_status_bit8), + .delete_in (delete_status_bit8) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_status_bit8 <= 1'b0 ; + else + begin + if (master_data_par_err) // Synchronous set + set_status_bit8 <= 1'b1 ; + else if (delete_set_status_bit8) // Synchronous reset + set_status_bit8 <= 1'b0 ; + end + end + wire [5:0] status_bits = {set_status_bit15_11[15] && !block_set_status_bit15, + set_status_bit15_11[14] && !block_set_status_bit14, + set_status_bit15_11[13] && !block_set_status_bit13, + set_status_bit15_11[12] && !block_set_status_bit12, + set_status_bit15_11[11] && !block_set_status_bit11, + set_status_bit8 && !block_set_status_bit8 } ; + wire [5:0] meta_status_bits ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(6, 0) status_bits_sync + ( + .data_in (status_bits), + .clk_out (wb_clk), + .sync_data_out (meta_status_bits), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + begin + status_bit15_11[15:11] <= 5'b0 ; + status_bit8 <= 1'b0 ; + end + else + begin + status_bit15_11[15:11] <= meta_status_bits[5:1] ; + status_bit8 <= meta_status_bits[0] ; + end + end + `else // GUEST + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[15] <= 1'b0 ; + else + begin + if (perr_in) // Synchronous set + status_bit15_11[15] <= 1'b1 ; + else if (delete_status_bit15) // Synchronous reset + status_bit15_11[15] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[14] <= 1'b0 ; + else + begin + if (serr_in) // Synchronous set + status_bit15_11[14] <= 1'b1 ; + else if (delete_status_bit14) // Synchronous reset + status_bit15_11[14] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[13] <= 1'b0 ; + else + begin + if (master_abort_recv) // Synchronous set + status_bit15_11[13] <= 1'b1 ; + else if (delete_status_bit13) // Synchronous reset + status_bit15_11[13] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[12] <= 1'b0 ; + else + begin + if (target_abort_recv) // Synchronous set + status_bit15_11[12] <= 1'b1 ; + else if (delete_status_bit12) // Synchronous reset + status_bit15_11[12] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit15_11[11] <= 1'b0 ; + else + begin + if (target_abort_set) // Synchronous set + status_bit15_11[11] <= 1'b1 ; + else if (delete_status_bit11) // Synchronous reset + status_bit15_11[11] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + status_bit8 <= 1'b0 ; + else + begin + if (master_data_par_err) // Synchronous set + status_bit8 <= 1'b1 ; + else if (delete_status_bit8) // Synchronous reset + status_bit8 <= 1'b0 ; + end + end + `endif +`endif + +// STATUS BITS of P_ERR_CS - PCI error control and status register +`ifdef SYNCHRONEOUS_CLOCK_DOMAINS + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + pci_err_cs_bit8 <= 1'b0 ; + else + begin + if (pci_error_sig && pci_err_cs_bit0) // Synchronous set + pci_err_cs_bit8 <= 1'b1 ; + else if (delete_pci_err_cs_bit8) // Synchronous reset + pci_err_cs_bit8 <= 1'b0 ; + end + end +`else // not SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + // Set and clear FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + pci_err_cs_bit8 <= 1'b0 ; + else + begin + if (pci_error_sig && pci_err_cs_bit0) // Synchronous set + pci_err_cs_bit8 <= 1'b1 ; + else if (delete_pci_err_cs_bit8) // Synchronous reset + pci_err_cs_bit8 <= 1'b0 ; + end + end + `else // GUEST + reg set_pci_err_cs_bit8; + wire delete_set_pci_err_cs_bit8; + wire block_set_pci_err_cs_bit8; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_pci_err_cs_8 + ( + .set_clk_in (wb_clk), + .delete_clk_in (pci_clk), + .reset_in (reset), + .delete_set_out (delete_set_pci_err_cs_bit8), + .block_set_out (block_set_pci_err_cs_bit8), + .delete_in (delete_pci_err_cs_bit8) + ); + // Setting FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_pci_err_cs_bit8 <= 1'b0 ; + else + begin + if (pci_error_sig && pci_err_cs_bit0) // Synchronous set + set_pci_err_cs_bit8 <= 1'b1 ; + else if (delete_set_pci_err_cs_bit8) // Synchronous reset + set_pci_err_cs_bit8 <= 1'b0 ; + end + end + wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ; + wire meta_pci_err_cs_bits ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1,0) pci_err_cs_bits_sync + ( + .data_in (pci_err_cs_bits), + .clk_out (pci_clk), + .sync_data_out (meta_pci_err_cs_bits), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + pci_err_cs_bit8 <= 1'b0 ; + else + pci_err_cs_bit8 <= meta_pci_err_cs_bits ; + end + `endif +`endif + // Set and clear FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + pci_err_cs_bit10 <= 1'b0 ; + else + begin + if (pci_error_sig) // Synchronous report + pci_err_cs_bit10 <= pci_error_rty_exp ; + end + end + // Set and clear FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + pci_err_cs_bit9 <= 1'b0 ; + else + begin + if (pci_error_sig) // Synchronous report + pci_err_cs_bit9 <= pci_error_es ; + end + end + // Set and clear FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + begin + pci_err_cs_bit31_24 <= 8'h00 ; + pci_err_addr <= 32'h0000_0000 ; + pci_err_data <= 32'h0000_0000 ; + end + else + if (pci_error_sig) // Synchronous report + begin + pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ; + pci_err_addr <= pci_error_addr ; + pci_err_data <= pci_error_data ; + end + end + +// STATUS BITS of W_ERR_CS - WB error control and status register +`ifdef SYNCHRONEOUS_CLOCK_DOMAINS + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + wb_err_cs_bit8 <= 1'b0 ; + else + begin + if (wb_error_sig && wb_err_cs_bit0) // Synchronous set + wb_err_cs_bit8 <= 1'b1 ; + else if (delete_wb_err_cs_bit8) // Synchronous reset + wb_err_cs_bit8 <= 1'b0 ; + end + end +`else // not SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + reg set_wb_err_cs_bit8; + wire delete_set_wb_err_cs_bit8; + wire block_set_wb_err_cs_bit8; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_wb_err_cs_8 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_wb_err_cs_bit8), + .block_set_out (block_set_wb_err_cs_bit8), + .delete_in (delete_wb_err_cs_bit8) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_wb_err_cs_bit8 <= 1'b0 ; + else + begin + if (wb_error_sig && wb_err_cs_bit0) // Synchronous set + set_wb_err_cs_bit8 <= 1'b1 ; + else if (delete_set_wb_err_cs_bit8) // Synchronous reset + set_wb_err_cs_bit8 <= 1'b0 ; + end + end + wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ; + wire meta_wb_err_cs_bits ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1,0) wb_err_cs_bits_sync + ( + .data_in (wb_err_cs_bits), + .clk_out (wb_clk), + .sync_data_out (meta_wb_err_cs_bits), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + wb_err_cs_bit8 <= 1'b0 ; + else + wb_err_cs_bit8 <= meta_wb_err_cs_bits ; + end + `else // GUEST + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + wb_err_cs_bit8 <= 1'b0 ; + else + begin + if (wb_error_sig && wb_err_cs_bit0) // Synchronous set + wb_err_cs_bit8 <= 1'b1 ; + else if (delete_wb_err_cs_bit8) // Synchronous reset + wb_err_cs_bit8 <= 1'b0 ; + end + end + `endif +`endif +/* // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + wb_err_cs_bit10 <= 1'b0 ; + else + begin + if (wb_error_sig) // Synchronous report + wb_err_cs_bit10 <= wb_error_rty_exp ; + end + end */ + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + wb_err_cs_bit9 <= 1'b0 ; + else + begin + if (wb_error_sig) // Synchronous report + wb_err_cs_bit9 <= wb_error_es ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + begin + wb_err_cs_bit31_24 <= 8'h00 ; + wb_err_addr <= 32'h0000_0000 ; + wb_err_data <= 32'h0000_0000 ; + end + else + if (wb_error_sig) + begin + wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ; + wb_err_addr <= wb_error_addr ; + wb_err_data <= wb_error_data ; + end + end + +// SERR_INT and PERR_INT STATUS BITS of ISR - interrupt status register +`ifdef SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit4_3[4] <= 1'b0 ; + else + begin + if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set + isr_bit4_3[4] <= 1'b1 ; + else if (delete_isr_bit4) // Synchronous reset + isr_bit4_3[4] <= 1'b0 ; + end + end + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit4_3[3] <= 1'b0 ; + else + begin + if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set + isr_bit4_3[3] <= 1'b1 ; + else if (delete_isr_bit3) // Synchronous reset + isr_bit4_3[3] <= 1'b0 ; + end + end + `endif +`else // not SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + reg [4:3] set_isr_bit4_3; + wire delete_set_isr_bit4; + wire delete_set_isr_bit3; + wire block_set_isr_bit4; + wire block_set_isr_bit3; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_isr_4 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_isr_bit4), + .block_set_out (block_set_isr_bit4), + .delete_in (delete_isr_bit4) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_isr_bit4_3[4] <= 1'b0 ; + else + begin + if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set + set_isr_bit4_3[4] <= 1'b1 ; + else if (delete_set_isr_bit4) // Synchronous reset + set_isr_bit4_3[4] <= 1'b0 ; + end + end + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_isr_3 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_isr_bit3), + .block_set_out (block_set_isr_bit3), + .delete_in (delete_isr_bit3) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_isr_bit4_3[3] <= 1'b0 ; + else + begin + if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set + set_isr_bit4_3[3] <= 1'b1 ; + else if (delete_set_isr_bit3) // Synchronous reset + set_isr_bit4_3[3] <= 1'b0 ; + end + end + wire [4:3] isr_bits4_3 = {set_isr_bit4_3[4] && !block_set_isr_bit4, + set_isr_bit4_3[3] && !block_set_isr_bit3 } ; + wire [4:3] meta_isr_bits4_3 ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(2, 0) isr_bits_sync + ( + .data_in (isr_bits4_3), + .clk_out (wb_clk), + .sync_data_out (meta_isr_bits4_3), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + isr_bit4_3[4:3] <= 2'b0 ; + else + isr_bit4_3[4:3] <= meta_isr_bits4_3[4:3] ; + end + `endif +`endif + +// PCI_EINT and WB_EINT STATUS BITS of ISR - interrupt status register +`ifdef SYNCHRONEOUS_CLOCK_DOMAINS + // WB_EINT STATUS BIT + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit2_0[1] <= 1'b0 ; + else + begin + if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set + isr_bit2_0[1] <= 1'b1 ; + else if (delete_isr_bit1) // Synchronous reset + isr_bit2_0[1] <= 1'b0 ; + end + end + // PCI_EINT STATUS BIT + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit2_0[2] <= 1'b0 ; + else + begin + if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set + isr_bit2_0[2] <= 1'b1 ; + else if (delete_isr_bit2) // Synchronous reset + isr_bit2_0[2] <= 1'b0 ; + end + end +`else // not SYNCHRONEOUS_CLOCK_DOMAINS + `ifdef HOST + // WB_EINT STATUS BIT + reg set_isr_bit1; + wire delete_set_isr_bit1; + wire block_set_isr_bit1; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_isr_1 + ( + .set_clk_in (pci_clk), + .delete_clk_in (wb_clk), + .reset_in (reset), + .delete_set_out (delete_set_isr_bit1), + .block_set_out (block_set_isr_bit1), + .delete_in (delete_isr_bit1) + ); + // Setting FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_isr_bit1 <= 1'b0 ; + else + begin + if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set + set_isr_bit1 <= 1'b1 ; + else if (delete_set_isr_bit1) // Synchronous reset + set_isr_bit1 <= 1'b0 ; + end + end + wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ; + wire meta_isr_bit1 ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) isr_bit1_sync + ( + .data_in (isr_bit1), + .clk_out (wb_clk), + .sync_data_out (meta_isr_bit1), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + isr_bit2_0[1] <= 1'b0 ; + else + isr_bit2_0[1] <= meta_isr_bit1 ; + end + // PCI_EINT STATUS BIT + // Set and clear FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit2_0[2] <= 1'b0 ; + else + begin + if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set + isr_bit2_0[2] <= 1'b1 ; + else if (delete_isr_bit2) // Synchronous reset + isr_bit2_0[2] <= 1'b0 ; + end + end + `else // GUEST + // WB_EINT STATUS BIT + // Set and clear FF + always@(posedge pci_clk or posedge reset) + begin + if (reset) // Asynchronous reset + isr_bit2_0[1] <= 1'b0 ; + else + begin + if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set + isr_bit2_0[1] <= 1'b1 ; + else if (delete_isr_bit1) // Synchronous reset + isr_bit2_0[1] <= 1'b0 ; + end + end + // PCI_EINT STATUS BIT + reg set_isr_bit2; + wire delete_set_isr_bit2; + wire block_set_isr_bit2; + // Synchronization module for clearing FF between two clock domains + pci_sync_module sync_isr_2 + ( + .set_clk_in (wb_clk), + .delete_clk_in (pci_clk), + .reset_in (reset), + .delete_set_out (delete_set_isr_bit2), + .block_set_out (block_set_isr_bit2), + .delete_in (delete_isr_bit2) + ); + // Setting FF + always@(posedge wb_clk or posedge reset) + begin + if (reset) // Asynchronous reset + set_isr_bit2 <= 1'b0 ; + else + begin + if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set + set_isr_bit2 <= 1'b1 ; + else if (delete_set_isr_bit2) // Synchronous reset + set_isr_bit2 <= 1'b0 ; + end + end + wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ; + wire meta_isr_bit2 ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) isr_bit2_sync + ( + .data_in (isr_bit2), + .clk_out (pci_clk), + .sync_data_out (meta_isr_bit2), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + isr_bit2_0[2] <= 1'b0 ; + else + isr_bit2_0[2] <= meta_isr_bit2 ; + end + `endif +`endif + +// INT BIT of ISR - interrupt status register +`ifdef HOST + wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; + wire meta_isr_int_prop_bit ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) isr_bit0_sync + ( + .data_in (isr_int_prop_bit), + .clk_out (wb_clk), + .sync_data_out (meta_isr_int_prop_bit), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + isr_bit2_0[0] <= 1'b0 ; + else + isr_bit2_0[0] <= meta_isr_int_prop_bit ; + end +`else // GUEST + `ifdef SYNCHRONEOUS_CLOCK_DOMAINS + wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + isr_bit2_0[0] <= 1'b0 ; + else + isr_bit2_0[0] <= isr_int_prop_bit ; + end + `else // not SYNCHRONEOUS_CLOCK_DOMAINS + wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; + wire meta_isr_int_prop_bit ; + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) isr_bit0_sync + ( + .data_in (isr_int_prop_bit), + .clk_out (pci_clk), + .sync_data_out (meta_isr_int_prop_bit), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + isr_bit2_0[0] <= 1'b0 ; + else + isr_bit2_0[0] <= meta_isr_int_prop_bit ; + end + `endif +`endif + +// INT PIN +wire int_in; +wire int_meta; +reg interrupt_out; +`ifdef HOST + `ifdef SYNCHRONEOUS_CLOCK_DOMAINS + assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2] || isr_bit4_3[3] || isr_bit4_3[4]; + `else // not SYNCHRONEOUS_CLOCK_DOMAINS + assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4]; + `endif + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) int_pin_sync + ( + .data_in (int_in), + .clk_out (wb_clk), + .sync_data_out (int_meta), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + interrupt_out <= 1'b0 ; + else + interrupt_out <= int_meta ; + end +`else // GUEST + `ifdef SYNCHRONEOUS_CLOCK_DOMAINS + assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2]; + `else // not SYNCHRONEOUS_CLOCK_DOMAINS + assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2; + `endif + // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability + pci_synchronizer_flop #(1, 0) int_pin_sync + ( + .data_in (int_in), + .clk_out (pci_clk), + .sync_data_out (int_meta), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + interrupt_out <= 1'b0 ; + else + interrupt_out <= int_meta ; + end +`endif + + +`ifdef PCI_CPCI_HS_IMPLEMENT + reg [hs_es_cnt_width - 1:0] hs_es_cnt ; // debounce counter + reg hs_es_in_state, // current state of ejector switch input - synchronized + hs_es_sync, // synchronization flop for ejector switch input + hs_es_cur_state ; // current valid state of ejector switch + +`ifdef ACTIVE_HIGH_OE + wire oe_active_val = 1'b1 ; +`endif + +`ifdef ACTIVE_LOW_OE + wire oe_active_val = 1'b0 ; +`endif + + always@(posedge pci_clk or posedge reset) + begin + if (reset) + begin + hs_ins <= 1'b0 ; + hs_ins_armed <= 1'b1 ; + hs_ext <= 1'b0 ; + hs_ext_armed <= 1'b0 ; + hs_es_in_state <= 1'b0 ; + hs_es_sync <= 1'b0 ; + hs_es_cur_state <= 1'b0 ; + hs_es_cnt <= 'h0 ; + + `ifdef ACTIVE_LOW_OE + pci_cpci_hs_enum_oe_o <= 1'b1 ; + pci_cpci_hs_led_oe_o <= 1'b0 ; + `endif + + `ifdef ACTIVE_HIGH_OE + pci_cpci_hs_enum_oe_o <= 1'b0 ; + pci_cpci_hs_led_oe_o <= 1'b1 ; + `endif + + end + else + begin + // INS + if (hs_ins) + begin + if (w_conf_data[23] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) // clear + hs_ins <= 1'b0 ; + end + else if (hs_ins_armed) // set + hs_ins <= init_complete & (hs_es_cur_state == 1'b1) ; + + // INS armed + if (~hs_ins & hs_ins_armed & init_complete & (hs_es_cur_state == 1'b1)) // clear + hs_ins_armed <= 1'b0 ; + else if (hs_ext) // set + hs_ins_armed <= w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56] ; + + // EXT + if (hs_ext) // clear + begin + if (w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) + hs_ext <= 1'b0 ; + end + else if (hs_ext_armed) // set + hs_ext <= (hs_es_cur_state == 1'b0) ; + + // EXT armed + if (~hs_ext & hs_ext_armed & (hs_es_cur_state == 1'b0)) // clear + hs_ext_armed <= 1'b0 ; + else if (hs_ins) // set + hs_ext_armed <= w_conf_data[23] & !w_byte_en[2] & w_we & w_reg_select_dec[56] ; + + // ejector switch debounce counter logic + hs_es_sync <= pci_cpci_hs_es_i ; + hs_es_in_state <= hs_es_sync ; + + if (hs_es_in_state == hs_es_cur_state) + hs_es_cnt <= 'h0 ; + else + hs_es_cnt <= hs_es_cnt + 1'b1 ; + + if (hs_es_cnt == {hs_es_cnt_width{1'b1}}) + hs_es_cur_state <= hs_es_in_state ; + + if ((hs_ins | hs_ext) & ~hs_eim) + pci_cpci_hs_enum_oe_o <= oe_active_val ; + else + pci_cpci_hs_enum_oe_o <= ~oe_active_val ; + + if (~init_complete | hs_loo) + pci_cpci_hs_led_oe_o <= oe_active_val ; + else + pci_cpci_hs_led_oe_o <= ~oe_active_val ; + end + end +`endif + +`ifdef PCI_SPOCI + + wire spoci_write_done, + spoci_dat_rdy , + spoci_no_ack ; + + wire [ 7: 0] spoci_wdat ; + wire [ 7: 0] spoci_rdat ; + + // power on configuration control and status register + always@(posedge pci_clk or posedge reset) + begin + if (reset) + begin + spoci_cs_nack <= 1'b0 ; + spoci_cs_write <= 1'b0 ; + spoci_cs_read <= 1'b0 ; + spoci_cs_adr <= 'h0 ; + spoci_cs_dat <= 'h0 ; + end + else + begin + if (spoci_cs_write) + begin + if (spoci_write_done | spoci_no_ack) + spoci_cs_write <= 1'b0 ; + end + else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3]) + spoci_cs_write <= w_conf_data[25] ; + + if (spoci_cs_read) + begin + if (spoci_dat_rdy | spoci_no_ack) + spoci_cs_read <= 1'b0 ; + end + else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] ) + spoci_cs_read <= w_conf_data[24] ; + + if (spoci_cs_nack) + begin + if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] & w_conf_data[31] ) + spoci_cs_nack <= 1'b0 ; + end + else if (spoci_cs_write | spoci_cs_read | ~init_cfg_done) + begin + spoci_cs_nack <= spoci_no_ack ; + end + + if ( w_we & (w_conf_address[9:2] == 8'hFF) ) + begin + if (~w_byte_en[2]) + spoci_cs_adr[10: 8] <= w_conf_data[18:16] ; + + if (~w_byte_en[1]) + spoci_cs_adr[ 7: 0] <= w_conf_data[15: 8] ; + end + + if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[0] ) + spoci_cs_dat <= w_conf_data[ 7: 0] ; + else if (spoci_cs_read & spoci_dat_rdy) + spoci_cs_dat <= spoci_rdat ; + + end + end + + reg [ 2 : 0] bytes_received ; + + always@(posedge pci_clk or posedge reset) + begin + if (reset) + begin + init_we <= 1'b0 ; + init_cfg_done <= 1'b0 ; + bytes_received <= 1'b0 ; + spoci_dat <= 'h0 ; + spoci_reg_num <= 'h0 ; + end + else if (~init_cfg_done) + begin + if (spoci_dat_rdy) + begin + case (bytes_received) + 'h0:spoci_reg_num <= spoci_rdat ; + 'h1:spoci_dat[ 7: 0] <= spoci_rdat ; + 'h2:spoci_dat[15: 8] <= spoci_rdat ; + 'h3:spoci_dat[23:16] <= spoci_rdat ; + 'h4:spoci_dat[31:24] <= spoci_rdat ; + default: + begin + spoci_dat <= 32'hxxxx_xxxx ; + spoci_reg_num <= 'hxx ; + end + endcase + end + + if (init_we) + bytes_received <= 'h0 ; + else if (spoci_dat_rdy) + bytes_received <= bytes_received + 1'b1 ; + + if (init_we) + init_we <= 1'b0 ; + else if (bytes_received == 'h5) + init_we <= 1'b1 ; + + if (spoci_no_ack | ((bytes_received == 'h1) & (spoci_reg_num == 'hff)) ) + init_cfg_done <= 1'b1 ; + end + end + + assign spoci_wdat = spoci_cs_dat ; + + pci_spoci_ctrl i_pci_spoci_ctrl + ( + .reset_i (reset ), + .clk_i (pci_clk ), + + .do_rnd_read_i (spoci_cs_read ), + .do_seq_read_i (rst_inactive & ~init_cfg_done ), + .do_write_i (spoci_cs_write ), + + .write_done_o (spoci_write_done ), + .dat_rdy_o (spoci_dat_rdy ), + .no_ack_o (spoci_no_ack ), + + .adr_i (spoci_cs_adr ), + .dat_i (spoci_wdat ), + .dat_o (spoci_rdat ), + + .pci_spoci_sda_i (spoci_sda_i ), + .pci_spoci_sda_oe_o (spoci_sda_oe_o ), + .pci_spoci_scl_oe_o (spoci_scl_oe_o ) + ); +`endif + +/*----------------------------------------------------------------------------------------------------------- + OUTPUTs from registers !!! +-----------------------------------------------------------------------------------------------------------*/ + +// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done +`ifdef HOST + wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ; + wire [3:0] meta_command_bits ; + reg [3:0] sync_command_bits ; + pci_synchronizer_flop #(4, 0) command_bits_sync + ( + .data_in (command_bits), + .clk_out (pci_clk), + .sync_data_out (meta_command_bits), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + sync_command_bits <= 4'b0 ; + else + sync_command_bits <= meta_command_bits ; + end + wire sync_command_bit8 = sync_command_bits[3] ; + wire sync_command_bit6 = sync_command_bits[2] ; + wire sync_command_bit1 = sync_command_bits[1] ; + wire sync_command_bit0 = sync_command_bits[0] ; + wire sync_command_bit2 = command_bit2_0[2] ; +`else // GUEST + wire command_bit = command_bit2_0[2] ; + wire meta_command_bit ; + reg sync_command_bit ; + pci_synchronizer_flop #(1, 0) command_bit_sync + ( + .data_in (command_bit), + .clk_out (pci_clk), + .sync_data_out (meta_command_bit), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + sync_command_bit <= 1'b0 ; + else + sync_command_bit <= meta_command_bit ; + end + wire sync_command_bit8 = command_bit8 ; + wire sync_command_bit6 = command_bit6 ; + wire sync_command_bit1 = command_bit2_0[1] ; + wire sync_command_bit0 = command_bit2_0[0] ; + wire sync_command_bit2 = sync_command_bit ; +`endif +// PCI header outputs from command register +assign serr_enable = sync_command_bit8 & pci_init_complete_out ; // to PCI clock +assign perr_response = sync_command_bit6 & pci_init_complete_out ; // to PCI clock +assign pci_master_enable = sync_command_bit2 & wb_init_complete_out ; // to WB clock +assign memory_space_enable = sync_command_bit1 & pci_init_complete_out ; // to PCI clock +assign io_space_enable = sync_command_bit0 & pci_init_complete_out ; // to PCI clock + +// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done + // We don't support cache line sizes smaller that 4 and it must have last two bits zero!!! +wire cache_lsize_not_zero = ((cache_line_size_reg[7] || cache_line_size_reg[6] || cache_line_size_reg[5] || + cache_line_size_reg[4] || cache_line_size_reg[3] || cache_line_size_reg[2]) && + (!cache_line_size_reg[1] && !cache_line_size_reg[0]) ); +`ifdef HOST + wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ; + wire [7:2] meta_cache_lsize_to_pci_bits ; + reg [7:2] sync_cache_lsize_to_pci_bits ; + pci_synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync + ( + .data_in (cache_lsize_to_pci_bits), + .clk_out (pci_clk), + .sync_data_out (meta_cache_lsize_to_pci_bits), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + sync_cache_lsize_to_pci_bits <= 6'b0 ; + else + sync_cache_lsize_to_pci_bits <= meta_cache_lsize_to_pci_bits ; + end + wire [7:2] sync_cache_line_size_to_pci_reg = sync_cache_lsize_to_pci_bits[7:2] ; + wire [7:2] sync_cache_line_size_to_wb_reg = cache_line_size_reg[7:2] ; + wire sync_cache_lsize_not_zero_to_wb = cache_lsize_not_zero ; +// Latency timer is sinchronized only to PCI clock when bridge implementation is HOST + wire [7:0] latency_timer_bits = latency_timer ; + wire [7:0] meta_latency_timer_bits ; + reg [7:0] sync_latency_timer_bits ; + pci_synchronizer_flop #(8, 0) latency_timer_bits_sync + ( + .data_in (latency_timer_bits), + .clk_out (pci_clk), + .sync_data_out (meta_latency_timer_bits), + .async_reset (reset) + ) ; + always@(posedge pci_clk or posedge reset) + begin + if (reset) + sync_latency_timer_bits <= 8'b0 ; + else + sync_latency_timer_bits <= meta_latency_timer_bits ; + end + wire [7:0] sync_latency_timer = sync_latency_timer_bits ; +`else // GUEST + wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ; + wire [8:2] meta_cache_lsize_to_wb_bits ; + reg [8:2] sync_cache_lsize_to_wb_bits ; + pci_synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync + ( + .data_in (cache_lsize_to_wb_bits), + .clk_out (wb_clk), + .sync_data_out (meta_cache_lsize_to_wb_bits), + .async_reset (reset) + ) ; + always@(posedge wb_clk or posedge reset) + begin + if (reset) + sync_cache_lsize_to_wb_bits <= 7'b0 ; + else + sync_cache_lsize_to_wb_bits <= meta_cache_lsize_to_wb_bits ; + end + wire [7:2] sync_cache_line_size_to_pci_reg = cache_line_size_reg[7:2] ; + wire [7:2] sync_cache_line_size_to_wb_reg = sync_cache_lsize_to_wb_bits[7:2] ; + wire sync_cache_lsize_not_zero_to_wb = sync_cache_lsize_to_wb_bits[8] ; +// Latency timer + wire [7:0] sync_latency_timer = latency_timer ; +`endif +// PCI header output from cache_line_size, latency timer and interrupt pin +assign cache_line_size_to_pci = {sync_cache_line_size_to_pci_reg, 2'h0} ; // [7 : 0] to PCI clock +assign cache_line_size_to_wb = {sync_cache_line_size_to_wb_reg, 2'h0} ; // [7 : 0] to WB clock +assign cache_lsize_not_zero_to_wb = sync_cache_lsize_not_zero_to_wb ; + +assign latency_tim[7 : 0] = sync_latency_timer ; // to PCI clock +//assign int_pin[2 : 0] = r_interrupt_pin ; +assign int_out = interrupt_out ; +// PCI output from image registers +// base address, address mask, translation address and control registers are sinchronized in PCI_DECODER.V module +`ifdef HOST + `ifdef NO_CNF_IMAGE + assign pci_base_addr0 = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; + `else + assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ; + `endif +`endif + +`ifdef GUEST + assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ; +`endif + +assign pci_base_addr1 = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_base_addr2 = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_base_addr3 = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_base_addr4 = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_base_addr5 = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_memory_io0 = pci_ba0_bit0 ; +assign pci_memory_io1 = pci_ba1_bit0 ; +assign pci_memory_io2 = pci_ba2_bit0 ; +assign pci_memory_io3 = pci_ba3_bit0 ; +assign pci_memory_io4 = pci_ba4_bit0 ; +assign pci_memory_io5 = pci_ba5_bit0 ; + +assign pci_addr_mask0 = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_addr_mask1 = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_addr_mask2 = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_addr_mask3 = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_addr_mask4 = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_addr_mask5 = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr0 = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr1 = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr2 = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr3 = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr4 = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_tran_addr5 = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; +assign pci_img_ctrl0[2 : 1] = pci_img_ctrl0_bit2_1 ; +assign pci_img_ctrl1[2 : 1] = pci_img_ctrl1_bit2_1 ; +assign pci_img_ctrl2[2 : 1] = pci_img_ctrl2_bit2_1 ; +assign pci_img_ctrl3[2 : 1] = pci_img_ctrl3_bit2_1 ; +assign pci_img_ctrl4[2 : 1] = pci_img_ctrl4_bit2_1 ; +assign pci_img_ctrl5[2 : 1] = pci_img_ctrl5_bit2_1 ; +// WISHBONE output from image registers +// base address, address mask, translation address and control registers are sinchronized in DECODER.V module +assign wb_base_addr0 = wb_ba0_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_base_addr1 = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_base_addr2 = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_base_addr3 = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_base_addr4 = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_base_addr5 = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_memory_io0 = wb_ba0_bit0 ; +assign wb_memory_io1 = wb_ba1_bit0 ; +assign wb_memory_io2 = wb_ba2_bit0 ; +assign wb_memory_io3 = wb_ba3_bit0 ; +assign wb_memory_io4 = wb_ba4_bit0 ; +assign wb_memory_io5 = wb_ba5_bit0 ; +assign wb_addr_mask0 = wb_am0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_addr_mask1 = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_addr_mask2 = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_addr_mask3 = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_addr_mask4 = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_addr_mask5 = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr0 = wb_ta0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr1 = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr2 = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr3 = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr4 = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_tran_addr5 = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; +assign wb_img_ctrl0[2 : 0] = wb_img_ctrl0_bit2_0 ; +assign wb_img_ctrl1[2 : 0] = wb_img_ctrl1_bit2_0 ; +assign wb_img_ctrl2[2 : 0] = wb_img_ctrl2_bit2_0 ; +assign wb_img_ctrl3[2 : 0] = wb_img_ctrl3_bit2_0 ; +assign wb_img_ctrl4[2 : 0] = wb_img_ctrl4_bit2_0 ; +assign wb_img_ctrl5[2 : 0] = wb_img_ctrl5_bit2_0 ; +// GENERAL output from conf. cycle generation register & int. control register +assign config_addr[23 : 0] = { cnf_addr_bit23_2, 1'b0, cnf_addr_bit0 } ; +assign icr_soft_res = icr_bit31 ; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_constants.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_constants.v new file mode 100644 index 000000000..c29391971 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_constants.v @@ -0,0 +1,170 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_constants.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// - Tadej Markovic (tadej@opencores.org) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_constants.v,v $ +// Revision 1.2 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// + +// first include user definable parameters +`ifdef REGRESSION // Used only for regression testing purposes!!! + `include "pci_regression_constants.v" +`else + `include "pci_user_constants.v" +`endif + +//////////////////////////////////////////////////////////////////////// +//// //// +//// FIFO parameters define behaviour of FIFO control logic and //// +//// FIFO depths. //// +//// //// +//////////////////////////////////////////////////////////////////////// +`define WBW_DEPTH (1 << `WBW_ADDR_LENGTH) +`define WBR_DEPTH (1 << `WBR_ADDR_LENGTH) +`define PCIW_DEPTH (1 << `PCIW_ADDR_LENGTH) +`define PCIR_DEPTH (1 << `PCIR_ADDR_LENGTH) + +// defines on which bit in control bus means what +`define ADDR_CTRL_BIT 3 +`define LAST_CTRL_BIT 0 +`define DATA_ERROR_CTRL_BIT 1 +`define UNUSED_CTRL_BIT 2 +`define BURST_BIT 2 + +// MAX Retry counter value for PCI Master state-machine +// This value is 8-bit because of 8-bit retry counter !!! +//`define PCI_RTY_CNT_MAX 8'h08 + +// Value of address mask for WB configuration image. This has to be defined always, since it is a value, that is not changable in runtime. +// !!!!!!!!!!!!!!!!!!!!!!!If this is not defined, WB configuration access will not be possible!!!!!!!!!!!!!!!!!!!!!1 +`define WB_AM0 20'hffff_f + +// PCI target & WB slave ADDRESS names for configuration space !!! +// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.) +// ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while +// accessing this registers, otherwise the configuration header will be accessed !!! +`define PCI_CAP_PTR_VAL 8'h80 +`define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100 +`define P_BA0_ADDR 6'h01 // Address offset = h 104 +`define P_AM0_ADDR 6'h02 // Address offset = h 108 +`define P_TA0_ADDR 6'h03 // Address offset = h 10c +`define P_IMG_CTRL1_ADDR 6'h04 // Address offset = h 110 +`define P_BA1_ADDR 6'h05 // Address offset = h 114 +`define P_AM1_ADDR 6'h06 // Address offset = h 118 +`define P_TA1_ADDR 6'h07 // Address offset = h 11c +`define P_IMG_CTRL2_ADDR 6'h08 // Address offset = h 120 +`define P_BA2_ADDR 6'h09 // Address offset = h 124 +`define P_AM2_ADDR 6'h0a // Address offset = h 128 +`define P_TA2_ADDR 6'h0b // Address offset = h 12c +`define P_IMG_CTRL3_ADDR 6'h0c // Address offset = h 130 +`define P_BA3_ADDR 6'h0d // Address offset = h 134 +`define P_AM3_ADDR 6'h0e // Address offset = h 138 +`define P_TA3_ADDR 6'h0f // Address offset = h 13c +`define P_IMG_CTRL4_ADDR 6'h10 // Address offset = h 140 +`define P_BA4_ADDR 6'h11 // Address offset = h 144 +`define P_AM4_ADDR 6'h12 // Address offset = h 148 +`define P_TA4_ADDR 6'h13 // Address offset = h 14c +`define P_IMG_CTRL5_ADDR 6'h14 // Address offset = h 150 +`define P_BA5_ADDR 6'h15 // Address offset = h 154 +`define P_AM5_ADDR 6'h16 // Address offset = h 158 +`define P_TA5_ADDR 6'h17 // Address offset = h 15c +`define P_ERR_CS_ADDR 6'h18 // Address offset = h 160 +`define P_ERR_ADDR_ADDR 6'h19 // Address offset = h 164 +`define P_ERR_DATA_ADDR 6'h1a // Address offset = h 168 + +`define WB_CONF_SPC_BAR_ADDR 6'h20 // Address offset = h 180 +`define W_IMG_CTRL1_ADDR 6'h21 // Address offset = h 184 +`define W_BA1_ADDR 6'h22 // Address offset = h 188 +`define W_AM1_ADDR 6'h23 // Address offset = h 18c +`define W_TA1_ADDR 6'h24 // Address offset = h 190 +`define W_IMG_CTRL2_ADDR 6'h25 // Address offset = h 194 +`define W_BA2_ADDR 6'h26 // Address offset = h 198 +`define W_AM2_ADDR 6'h27 // Address offset = h 19c +`define W_TA2_ADDR 6'h28 // Address offset = h 1a0 +`define W_IMG_CTRL3_ADDR 6'h29 // Address offset = h 1a4 +`define W_BA3_ADDR 6'h2a // Address offset = h 1a8 +`define W_AM3_ADDR 6'h2b // Address offset = h 1ac +`define W_TA3_ADDR 6'h2c // Address offset = h 1b0 +`define W_IMG_CTRL4_ADDR 6'h2d // Address offset = h 1b4 +`define W_BA4_ADDR 6'h2e // Address offset = h 1b8 +`define W_AM4_ADDR 6'h2f // Address offset = h 1bc +`define W_TA4_ADDR 6'h30 // Address offset = h 1c0 +`define W_IMG_CTRL5_ADDR 6'h31 // Address offset = h 1c4 +`define W_BA5_ADDR 6'h32 // Address offset = h 1c8 +`define W_AM5_ADDR 6'h33 // Address offset = h 1cc +`define W_TA5_ADDR 6'h34 // Address offset = h 1d0 +`define W_ERR_CS_ADDR 6'h35 // Address offset = h 1d4 +`define W_ERR_ADDR_ADDR 6'h36 // Address offset = h 1d8 +`define W_ERR_DATA_ADDR 6'h37 // Address offset = h 1dc +`define CNF_ADDR_ADDR 6'h38 // Address offset = h 1e0 +// Following two registers are not implemented in a configuration space but in a WishBone unit! +`define CNF_DATA_ADDR 6'h39 // Address offset = h 1e4 +`define INT_ACK_ADDR 6'h3a // Address offset = h 1e8 +// ------------------------------------- +`define ICR_ADDR 6'h3b // Address offset = h 1ec +`define ISR_ADDR 6'h3c // Address offset = h 1f0 + +`ifdef PCI33 + `define HEADER_66MHz 1'b0 +`else +`ifdef PCI66 + `define HEADER_66MHz 1'b1 +`endif +`endif + +// all flip-flops in the design have this inter-assignment delay +`define FF_DELAY 1 + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cur_out_reg.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cur_out_reg.v new file mode 100644 index 000000000..ea8f287b9 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_cur_out_reg.v @@ -0,0 +1,271 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "cur_out_reg.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_cur_out_reg.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" + +// module is only a backup copy of relevant output registers +// used in some arhitectures that support IOB registers, which have to have a +// fanout of 1 +// Otherwise nothing special in this module +module pci_cur_out_reg +( + reset_in, + clk_in, + frame_in, + frame_load_in, + irdy_in, + devsel_in, + trdy_in, + trdy_en_in, + stop_in, + ad_load_in, + cbe_in, + cbe_en_in, + mas_ad_in, + tar_ad_in, + frame_en_in, + irdy_en_in, + + mas_ad_en_in, + tar_ad_en_in, + ad_en_unregistered_in, + + par_in, + par_en_in, + perr_in, + perr_en_in, + serr_in, + serr_en_in, + + frame_out, + irdy_out, + devsel_out, + trdy_out, + stop_out, + cbe_out, + cbe_en_out, + ad_out, + frame_en_out, + irdy_en_out, + ad_en_out, + mas_ad_en_out, + tar_ad_en_out, + trdy_en_out, + + par_out, + par_en_out, + perr_out, + perr_en_out, + serr_out, + serr_en_out +) ; + +input reset_in, clk_in ; + +input frame_in ; +input frame_load_in ; +input irdy_in ; +input devsel_in ; +input trdy_in ; +input stop_in ; +input ad_load_in ; + +input [3:0] cbe_in ; +input cbe_en_in ; +input [31:0] mas_ad_in ; +input [31:0] tar_ad_in ; + +input mas_ad_en_in ; +input tar_ad_en_in ; +input ad_en_unregistered_in ; + +input frame_en_in, + irdy_en_in ; + +input trdy_en_in ; + +input par_in ; +input par_en_in ; +input perr_in ; +input perr_en_in ; +input serr_in ; +input serr_en_in ; + +output frame_out ; +reg frame_out ; +output irdy_out ; +reg irdy_out ; +output devsel_out ; +reg devsel_out ; +output trdy_out ; +reg trdy_out ; +output stop_out ; +reg stop_out ; +output [3:0] cbe_out ; +reg [3:0] cbe_out ; +output [31:0] ad_out ; +reg [31:0] ad_out ; + +output frame_en_out, + irdy_en_out, + ad_en_out, + cbe_en_out, + mas_ad_en_out, + tar_ad_en_out, + trdy_en_out ; + +reg frame_en_out, + irdy_en_out, + cbe_en_out, + mas_ad_en_out, + tar_ad_en_out, + trdy_en_out; + +output par_out ; +output par_en_out ; +output perr_out ; +output perr_en_out ; +output serr_out ; +output serr_en_out ; + +reg par_out ; +reg par_en_out ; +reg perr_out ; +reg perr_en_out ; +reg serr_out ; +reg serr_en_out ; + +assign ad_en_out = mas_ad_en_out || tar_ad_en_out ; + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + begin + irdy_out <= #`FF_DELAY 1'b1 ; + devsel_out <= #`FF_DELAY 1'b1 ; + trdy_out <= #`FF_DELAY 1'b1 ; + stop_out <= #`FF_DELAY 1'b1 ; + frame_en_out <= #`FF_DELAY 1'b0 ; + irdy_en_out <= #`FF_DELAY 1'b0 ; + mas_ad_en_out<= #`FF_DELAY 1'b0 ; + tar_ad_en_out<= #`FF_DELAY 1'b0 ; + trdy_en_out <= #`FF_DELAY 1'b0 ; + par_out <= #`FF_DELAY 1'b0 ; + par_en_out <= #`FF_DELAY 1'b0 ; + perr_out <= #`FF_DELAY 1'b1 ; + perr_en_out <= #`FF_DELAY 1'b0 ; + serr_out <= #`FF_DELAY 1'b1 ; + serr_en_out <= #`FF_DELAY 1'b0 ; + cbe_en_out <= #`FF_DELAY 1'b0 ; + + end + else + begin + irdy_out <= #`FF_DELAY irdy_in ; + devsel_out <= #`FF_DELAY devsel_in ; + trdy_out <= #`FF_DELAY trdy_in ; + stop_out <= #`FF_DELAY stop_in ; + frame_en_out <= #`FF_DELAY frame_en_in ; + irdy_en_out <= #`FF_DELAY irdy_en_in ; + mas_ad_en_out<= #`FF_DELAY mas_ad_en_in && ad_en_unregistered_in ; + tar_ad_en_out<= #`FF_DELAY tar_ad_en_in && ad_en_unregistered_in ; + trdy_en_out <= #`FF_DELAY trdy_en_in ; + + par_out <= #`FF_DELAY par_in ; + par_en_out <= #`FF_DELAY par_en_in ; + perr_out <= #`FF_DELAY perr_in ; + perr_en_out <= #`FF_DELAY perr_en_in ; + serr_out <= #`FF_DELAY serr_in ; + serr_en_out <= #`FF_DELAY serr_en_in ; + cbe_en_out <= #`FF_DELAY cbe_en_in ; + end +end + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + cbe_out <= #`FF_DELAY 4'hF ; + else if ( ad_load_in ) + cbe_out <= #`FF_DELAY cbe_in ; + +end + +wire [31:0] ad_source = tar_ad_en_out ? tar_ad_in : mas_ad_in ; + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + ad_out <= #`FF_DELAY 32'h0000_0000 ; + else if ( ad_load_in ) + ad_out <= #`FF_DELAY ad_source ; + +end + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + frame_out <= #`FF_DELAY 1'b1 ; + else if ( frame_load_in ) + frame_out <= #`FF_DELAY frame_in ; + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v new file mode 100644 index 000000000..b87244abb --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_sync.v @@ -0,0 +1,469 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "delayed_sync.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_delayed_sync.v,v $ +// Revision 1.3 2003/08/14 13:06:02 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.2 2003/03/26 13:16:18 mihad +// Added the reset value parameter to the synchronizer flop module. +// Added resets to all synchronizer flop instances. +// Repaired initial sync value in fifos. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.5 2002/09/25 09:54:50 mihad +// Added completion expiration test for WB Slave unit. Changed expiration signalling +// +// Revision 1.4 2002/03/05 11:53:47 mihad +// Added some testcases, removed un-needed fifo signals +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module provides synchronization mechanism between requesting and completing side of the bridge +`include "pci_constants.v" +`include "bus_commands.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_delayed_sync +( + reset_in, + req_clk_in, + comp_clk_in, + req_in, + comp_in, + done_in, + in_progress_in, + comp_req_pending_out, + req_req_pending_out, + req_comp_pending_out, + comp_comp_pending_out, + addr_in, + be_in, + addr_out, + be_out, + we_in, + we_out, + bc_in, + bc_out, + status_in, + status_out, + comp_flush_out, + burst_in, + burst_out, + retry_expired_in +); + +// system inputs +input reset_in, // reset input + req_clk_in, // requesting clock input + comp_clk_in ; // completing clock input + +// request, completion, done and in progress indication inputs +input req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs + comp_in, // completion qualifier - when 1, completing side indicates that request has completed + done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus + in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge + +// pending indication outputs +output comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock + req_req_pending_out, // request pending output for requesting side + req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus + comp_comp_pending_out ; // completion pending output for completing side of the bridge + +// additional signals and wires for clock domain passage of signals +reg comp_req_pending, + req_req_pending, + req_comp_pending, + req_comp_pending_sample, + comp_comp_pending, + req_done_reg, + comp_done_reg_main, + comp_done_reg_clr, + req_rty_exp_reg, + req_rty_exp_clr, + comp_rty_exp_reg, + comp_rty_exp_clr ; + +wire sync_comp_req_pending, + sync_req_comp_pending, + sync_comp_done, + sync_req_rty_exp, + sync_comp_rty_exp_clr ; + +// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides +// all signals that identify requests are stored in this module + +input [31:0] addr_in ; // address bus input +input [3:0] be_in ; // byte enable input +input we_in ; // write enable input - read/write request indication 1 = write request / 0 = read request +input [3:0] bc_in ; // bus command input +input burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer + +// common request outputs used both by completing and requesting sides +// this outputs are not resynchronized, since flags determine the request status +output [31:0] addr_out ; +output [3:0] be_out ; +output we_out ; +output [3:0] bc_out ; +output burst_out ; + +// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion +input status_in ; +output status_out ; + +// input signals that delayed transaction has been retried for max number of times +// on this signal request is ditched, otherwise it would cause a deadlock +// requestor can issue another request and procedure will be repeated +input retry_expired_in ; + +// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data +output comp_flush_out ; + +// output registers for common signals +reg [31:0] addr_out ; +reg [3:0] be_out ; +reg we_out ; +reg [3:0] bc_out ; +reg burst_out ; + +// delayed transaction information is stored only when request is issued and request nor completion are pending +wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ; +always@(posedge req_clk_in or posedge reset_in) +begin + if (reset_in) + begin + addr_out <= #`FF_DELAY 32'h0000_0000 ; + be_out <= #`FF_DELAY 4'h0 ; + we_out <= #`FF_DELAY 1'b0 ; + bc_out <= #`FF_DELAY `BC_RESERVED0 ; + burst_out <= #`FF_DELAY 1'b0 ; + end + else + if (new_request) + begin + addr_out <= #`FF_DELAY addr_in ; + be_out <= #`FF_DELAY be_in ; + we_out <= #`FF_DELAY we_in ; + bc_out <= #`FF_DELAY bc_in ; + burst_out <= #`FF_DELAY burst_in ; + end +end + +// completion pending cycle counter +reg [16:0] comp_cycle_count ; + +/*================================================================================================================================= +Passing of requests between clock domains: +request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain +=================================================================================================================================*/ +// main request flip-flop triggered on requesting side's clock +// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge +wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ; +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_req_pending <= #`FF_DELAY 1'b0 ; + else + if ( req_req_clear ) + req_req_pending <= #`FF_DELAY 1'b0 ; + else + if ( req_in ) + req_req_pending <= #`FF_DELAY 1'b1 ; +end + +// interemediate stage request synchronization flip - flop - this one is prone to metastability +// and should have setup and hold times disabled during simulation +pci_synchronizer_flop #(1, 0) req_sync +( + .data_in (req_req_pending), + .clk_out (comp_clk_in), + .sync_data_out (sync_comp_req_pending), + .async_reset (reset_in) +) ; + +// wire for clearing completion side request flag - whenever completion or retry expired are signalled +wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ; + +// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active +wire comp_req_pending_ena = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ; + +// completion side request flip flop - gets a value from intermediate stage sync flip flop +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_req_pending <= #`FF_DELAY 1'b0 ; + else + if ( comp_req_pending_clear ) + comp_req_pending <= #`FF_DELAY 1'b0 ; + else + if ( comp_req_pending_ena ) + comp_req_pending <= #`FF_DELAY sync_comp_req_pending ; +end + +// completion side request output assignment - when request ff is set and completion ff is not set +assign comp_req_pending_out = comp_req_pending ; + +// requesting side request pending output +assign req_req_pending_out = req_req_pending ; +/*================================================================================================================================= +Passing of completions between clock domains: +completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain +=================================================================================================================================*/ +// main completion Flip - Flop - triggered by completing side's clock +// completion side completion pending flag is cleared when done flag propagates through clock domains +wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ; +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_comp_pending <= #`FF_DELAY 1'b0 ; + else + if ( comp_comp_clear ) + comp_comp_pending <= #`FF_DELAY 1'b0 ; + else + if ( comp_in && comp_req_pending ) + comp_comp_pending <= #`FF_DELAY 1'b1 ; +end + +assign comp_comp_pending_out = comp_comp_pending ; + +// interemediate stage completion synchronization flip - flop - this one is prone to metastability +pci_synchronizer_flop #(1, 0) comp_sync +( + .data_in (comp_comp_pending), + .clk_out (req_clk_in), + .sync_data_out (sync_req_comp_pending), + .async_reset (reset_in) +) ; + +// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles +wire req_comp_pending_clear = done_in || comp_cycle_count[16]; + +// request side completion pending flip flop is disabled while done flag is set +wire req_comp_pending_ena = ~req_done_reg ; + +// request side completion flip flop - gets a value from intermediate stage sync flip flop +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_comp_pending <= #`FF_DELAY 1'b0 ; + else + if ( req_comp_pending_clear ) + req_comp_pending <= #`FF_DELAY 1'b0 ; + else + if ( req_comp_pending_ena ) + req_comp_pending <= #`FF_DELAY sync_req_comp_pending ; +end + +// sampling FF - used for sampling incoming completion flag from completing side +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_comp_pending_sample <= #`FF_DELAY 1'b0 ; + else + req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ; +end + +// requesting side completion pending output assignment +assign req_comp_pending_out = req_comp_pending && ~req_req_pending ; + +/*================================================================================================================================== +Passing of delayed transaction done signal between clock domains. +Done is signalled by requesting side of the bridge and is passed to completing side of the bridge +==================================================================================================================================*/ +// main done flip-flop triggered on requesting side's clock +// when completing side removes completion flag, done flag is also removed, so requests can proceede +wire req_done_clear = ~req_comp_pending_sample ; +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_done_reg <= #`FF_DELAY 1'b0 ; + else + if ( req_done_clear ) + req_done_reg <= #`FF_DELAY 1'b0 ; + else + if ( done_in || comp_cycle_count[16] ) + req_done_reg <= #`FF_DELAY 1'b1 ; +end + +pci_synchronizer_flop #(1, 0) done_sync +( + .data_in (req_done_reg), + .clk_out (comp_clk_in), + .sync_data_out (sync_comp_done), + .async_reset (reset_in) +) ; + +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_done_reg_main <= #`FF_DELAY 1'b0 ; + else + comp_done_reg_main <= #`FF_DELAY sync_comp_done ; +end + +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_done_reg_clr <= #`FF_DELAY 1'b0 ; + else + comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ; +end + +/*================================================================================================================================= +Passing of retry expired signal between clock domains +Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain +=================================================================================================================================*/ +// main retry expired Flip - Flop - triggered by completing side's clock +wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ; + +// retry expired is a special case of transaction removal - retry expired propagates from completing +// clock domain to requesting clock domain to remove all pending requests and than propagates back +// to completing side to qualify valid new requests + +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_rty_exp_reg <= #`FF_DELAY 1'b0 ; + else + if ( comp_rty_exp_clear ) + comp_rty_exp_reg <= #`FF_DELAY 1'b0 ; + else + if ( retry_expired_in && comp_req_pending) + comp_rty_exp_reg <= #`FF_DELAY 1'b1 ; +end + +// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability +pci_synchronizer_flop #(1, 0) rty_exp_sync +( + .data_in (comp_rty_exp_reg), + .clk_out (req_clk_in), + .sync_data_out (sync_req_rty_exp), + .async_reset (reset_in) +) ; + +// request retry expired flip flop - gets a value from intermediate stage sync flip flop +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_rty_exp_reg <= #`FF_DELAY 1'b0 ; + else + req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ; +end + +always@(posedge req_clk_in or posedge reset_in) +begin + if ( reset_in ) + req_rty_exp_clr <= #`FF_DELAY 1'b0 ; + else + req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ; +end + +pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync +( + .data_in (req_rty_exp_reg && req_rty_exp_clr), + .clk_out (comp_clk_in), + .sync_data_out (sync_comp_rty_exp_clr), + .async_reset (reset_in) +) ; + +always@(posedge comp_clk_in or posedge reset_in) +begin + if ( reset_in ) + comp_rty_exp_clr <= #`FF_DELAY 1'b0 ; + else + comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ; +end + +// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error +reg status_out ; +always@(posedge comp_clk_in or posedge reset_in) +begin + if (reset_in) + status_out <= #`FF_DELAY 1'b0 ; + else + if (comp_in && comp_req_pending) + status_out <= #`FF_DELAY status_in ; +end + +// clocks counter - it counts how many clock cycles completion is present without beeing repeated +// if it counts to 2^^16 cycles the completion must be ditched + +// wire for clearing this counter +wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ; +always@(posedge req_clk_in or posedge reset_in) +begin + if (reset_in) + comp_cycle_count <= #`FF_DELAY 17'h0_0000 ; + else + if (clear_count) + comp_cycle_count <= #`FF_DELAY 17'h0_0000 ; + else + comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ; +end + +// completion flush output - used for flushing fifos when counter expires +// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines +reg comp_flush_out ; +always@(posedge req_clk_in or posedge reset_in) +begin + if (reset_in) + comp_flush_out <= #`FF_DELAY 1'b0 ; + else + comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ; +end + +endmodule //delayed_sync diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_write_reg.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_write_reg.v new file mode 100644 index 000000000..42f871ad5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_delayed_write_reg.v @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "delayed_write_reg.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_delayed_write_reg.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_delayed_write_reg +( + reset_in, + req_clk_in, + comp_wdata_out, + req_we_in, + req_wdata_in +); + +// system inputs +input reset_in, + req_clk_in ; // request clock input + +output [31:0] comp_wdata_out ; // data output + +input req_we_in ; // write enable input +input [31:0] req_wdata_in ; // data input - latched with posedge of req_clk_in when req_we_in is high + +reg [31:0] comp_wdata_out ; + +// write request operation +always@(posedge req_clk_in or posedge reset_in) +begin + if (reset_in) + comp_wdata_out <= #`FF_DELAY 32'h0000_0000 ; + else + if (req_we_in) + comp_wdata_out <= #`FF_DELAY req_wdata_in ; +end + +endmodule // DELAYED_WRITE_REG diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_crit.v new file mode 100644 index 000000000..6de6fa586 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_crit.v @@ -0,0 +1,83 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "frame_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_frame_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// this one is used in master state machine for driving correct value of frame output + +module pci_frame_crit +( + pci_frame_out, + force_frame_in, + slow_frame_in, + pci_stop_in +) ; + +output pci_frame_out ; +input force_frame_in, + slow_frame_in, + pci_stop_in ; + +assign pci_frame_out = force_frame_in && (slow_frame_in || ~pci_stop_in) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_en_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_en_crit.v new file mode 100644 index 000000000..2dcfffc02 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_en_crit.v @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "frame_en_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_frame_en_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// This one is used in master state machine for frame output enable driving + +module pci_frame_en_crit +( + pci_frame_en_out, + frame_en_slow_in, + frame_en_keep_in, + pci_stop_in, + pci_trdy_in +) ; + +output pci_frame_en_out ; +input frame_en_slow_in, + frame_en_keep_in, + pci_stop_in, + pci_trdy_in ; + +assign pci_frame_en_out = frame_en_slow_in || frame_en_keep_in && pci_stop_in && pci_trdy_in ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_load_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_load_crit.v new file mode 100644 index 000000000..2ad22ae32 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_frame_load_crit.v @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "frame_load_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_frame_load_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// This one is used in master state machine for frame output flip flop clock enable driving +module pci_frame_load_crit +( + pci_frame_load_out, + sm_data_phases_in, + frame_load_slow_in, + pci_trdy_in, + pci_stop_in +) ; + +output pci_frame_load_out ; +input sm_data_phases_in, + frame_load_slow_in, + pci_trdy_in, + pci_stop_in ; + +assign pci_frame_load_out = frame_load_slow_in || sm_data_phases_in && (~(pci_trdy_in && pci_stop_in)) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v new file mode 100644 index 000000000..53a2c79fd --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_in_reg.v @@ -0,0 +1,160 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_in_reg.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_in_reg.v,v $ +// Revision 1.5 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:29 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" +// Module is used for registering PCI input signals +// It provides data flip flops with reset +module pci_in_reg +( + reset_in, + clk_in, + init_complete_in, + + pci_gnt_in, + pci_frame_in, + pci_irdy_in, + pci_trdy_in, + pci_stop_in, + pci_devsel_in, + pci_idsel_in, + pci_ad_in, + pci_cbe_in, + + pci_gnt_reg_out, + pci_frame_reg_out, + pci_irdy_reg_out, + pci_trdy_reg_out, + pci_stop_reg_out, + pci_devsel_reg_out, + pci_idsel_reg_out, + pci_ad_reg_out, + pci_cbe_reg_out + +); + +input reset_in, clk_in, init_complete_in ; + +input pci_gnt_in ; +input pci_frame_in ; +input pci_irdy_in ; +input pci_trdy_in ; +input pci_stop_in ; +input pci_devsel_in ; +input pci_idsel_in ; +input [31:0] pci_ad_in ; +input [3:0] pci_cbe_in ; + +output pci_gnt_reg_out ; +output pci_frame_reg_out ; +output pci_irdy_reg_out ; +output pci_trdy_reg_out ; +output pci_stop_reg_out ; +output pci_devsel_reg_out ; +output pci_idsel_reg_out ; +output [31:0] pci_ad_reg_out ; +output [3:0] pci_cbe_reg_out ; + + +reg pci_gnt_reg_out ; +reg pci_frame_reg_out ; +reg pci_irdy_reg_out ; +reg pci_trdy_reg_out ; +reg pci_stop_reg_out ; +reg pci_devsel_reg_out ; +reg pci_idsel_reg_out ; +reg [31:0] pci_ad_reg_out ; +reg [3:0] pci_cbe_reg_out ; + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + begin + pci_gnt_reg_out <= #`FF_DELAY 1'b1 ; + pci_frame_reg_out <= #`FF_DELAY 1'b0 ; + pci_irdy_reg_out <= #`FF_DELAY 1'b1 ; + pci_trdy_reg_out <= #`FF_DELAY 1'b1 ; + pci_stop_reg_out <= #`FF_DELAY 1'b1 ; + pci_devsel_reg_out <= #`FF_DELAY 1'b1 ; + pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high! + pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ; + pci_cbe_reg_out <= #`FF_DELAY 4'h0 ; + end + else if (init_complete_in) + begin + pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ; + pci_frame_reg_out <= #`FF_DELAY pci_frame_in ; + pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ; + pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ; + pci_stop_reg_out <= #`FF_DELAY pci_stop_in ; + pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ; + pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ; + pci_ad_reg_out <= #`FF_DELAY pci_ad_in ; + pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ; + end +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux.v new file mode 100644 index 000000000..f0882dfe8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux.v @@ -0,0 +1,855 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_io_mux.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_io_mux.v,v $ +// Revision 1.5 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:29 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// this module instantiates output flip flops for PCI interface and +// some fanout downsizing logic because of heavily constrained PCI signals + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_io_mux +( + reset_in, + clk_in, + frame_in, + frame_en_in, + frame_load_in, + irdy_in, + irdy_en_in, + devsel_in, + devsel_en_in, + trdy_in, + trdy_en_in, + stop_in, + stop_en_in, + master_load_in, + master_load_on_transfer_in, + target_load_in, + target_load_on_transfer_in, + cbe_in, + cbe_en_in, + mas_ad_in, + tar_ad_in, + + par_in, + par_en_in, + perr_in, + perr_en_in, + serr_in, + serr_en_in, + + req_in, + + mas_ad_en_in, + tar_ad_en_in, + tar_ad_en_reg_in, + + ad_en_out, + frame_en_out, + irdy_en_out, + devsel_en_out, + trdy_en_out, + stop_en_out, + cbe_en_out, + + frame_out, + irdy_out, + devsel_out, + trdy_out, + stop_out, + cbe_out, + ad_out, + ad_load_out, + ad_en_unregistered_out, + + par_out, + par_en_out, + perr_out, + perr_en_out, + serr_out, + serr_en_out, + + req_out, + req_en_out, + pci_trdy_in, + pci_irdy_in, + pci_frame_in, + pci_stop_in, + + init_complete_in +); + +input reset_in, clk_in ; + +input frame_in ; +input frame_en_in ; +input frame_load_in ; +input irdy_in ; +input irdy_en_in ; +input devsel_in ; +input devsel_en_in ; +input trdy_in ; +input trdy_en_in ; +input stop_in ; +input stop_en_in ; +input master_load_in ; +input target_load_in ; + +input [3:0] cbe_in ; +input cbe_en_in ; +input [31:0] mas_ad_in ; +input [31:0] tar_ad_in ; + +input mas_ad_en_in ; +input tar_ad_en_in ; +input tar_ad_en_reg_in ; + +input par_in ; +input par_en_in ; +input perr_in ; +input perr_en_in ; +input serr_in ; +input serr_en_in ; + +output frame_en_out ; +output irdy_en_out ; +output devsel_en_out ; +output trdy_en_out ; +output stop_en_out ; +output [31:0] ad_en_out ; +output [3:0] cbe_en_out ; + +output frame_out ; +output irdy_out ; +output devsel_out ; +output trdy_out ; +output stop_out ; +output [3:0] cbe_out ; +output [31:0] ad_out ; +output ad_load_out ; +output ad_en_unregistered_out ; + +output par_out ; +output par_en_out ; +output perr_out ; +output perr_en_out ; +output serr_out ; +output serr_en_out ; + +input req_in ; + +output req_out ; +output req_en_out ; + +input pci_trdy_in, + pci_irdy_in, + pci_frame_in, + pci_stop_in ; + +input master_load_on_transfer_in ; +input target_load_on_transfer_in ; + +input init_complete_in ; + +wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ; + +wire ad_en_ctrl_low ; + +wire ad_en_ctrl_mlow ; + +wire ad_en_ctrl_mhigh ; + +wire ad_en_ctrl_high ; + +wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ; + +pci_io_mux_ad_en_crit ad_en_low_gen +( + .ad_en_in (ad_enable_internal), + .pci_frame_in (pci_frame_in), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in), + .ad_en_out (ad_en_ctrl_low) +); + +pci_io_mux_ad_en_crit ad_en_mlow_gen +( + .ad_en_in (ad_enable_internal), + .pci_frame_in (pci_frame_in), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in), + .ad_en_out (ad_en_ctrl_mlow) +); + +pci_io_mux_ad_en_crit ad_en_mhigh_gen +( + .ad_en_in (ad_enable_internal), + .pci_frame_in (pci_frame_in), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in), + .ad_en_out (ad_en_ctrl_mhigh) +); + +pci_io_mux_ad_en_crit ad_en_high_gen +( + .ad_en_in (ad_enable_internal), + .pci_frame_in (pci_frame_in), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in), + .ad_en_out (ad_en_ctrl_high) +); + +assign ad_en_unregistered_out = ad_en_ctrl_high ; + +wire load = master_load_in || target_load_in ; +wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ; + +wire ad_load_ctrl_low ; +wire ad_load_ctrl_mlow ; +wire ad_load_ctrl_mhigh ; +wire ad_load_ctrl_high ; + +assign ad_load_out = ad_load_ctrl_high ; + +pci_io_mux_ad_load_crit ad_load_low_gen +( + .load_in(load), + .load_on_transfer_in(load_on_transfer), + .pci_irdy_in(pci_irdy_in), + .pci_trdy_in(pci_trdy_in), + .load_out(ad_load_ctrl_low) +); + +pci_io_mux_ad_load_crit ad_load_mlow_gen +( + .load_in(load), + .load_on_transfer_in(load_on_transfer), + .pci_irdy_in(pci_irdy_in), + .pci_trdy_in(pci_trdy_in), + .load_out(ad_load_ctrl_mlow) +); + +pci_io_mux_ad_load_crit ad_load_mhigh_gen +( + .load_in(load), + .load_on_transfer_in(load_on_transfer), + .pci_irdy_in(pci_irdy_in), + .pci_trdy_in(pci_trdy_in), + .load_out(ad_load_ctrl_mhigh) +); + +pci_io_mux_ad_load_crit ad_load_high_gen +( + .load_in(load), + .load_on_transfer_in(load_on_transfer), + .pci_irdy_in(pci_irdy_in), + .pci_trdy_in(pci_trdy_in), + .load_out(ad_load_ctrl_high) +); + +pci_out_reg ad_iob0 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[0] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[0] ), + .dat_out ( ad_out[0] ) +); + +pci_out_reg ad_iob1 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[1] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[1] ), + .dat_out ( ad_out[1] ) +); + +pci_out_reg ad_iob2 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[2] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[2] ), + .dat_out ( ad_out[2] ) +); + +pci_out_reg ad_iob3 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[3] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[3] ), + .dat_out ( ad_out[3] ) +); + +pci_out_reg ad_iob4 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[4] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[4] ), + .dat_out ( ad_out[4] ) +); + +pci_out_reg ad_iob5 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[5] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[5] ), + .dat_out ( ad_out[5] ) +); + +pci_out_reg ad_iob6 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[6] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[6] ), + .dat_out ( ad_out[6] ) +); + +pci_out_reg ad_iob7 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_low ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[7] ) , + .en_in ( ad_en_ctrl_low ) , + .en_out ( ad_en_out[7] ), + .dat_out ( ad_out[7] ) +); + +pci_out_reg ad_iob8 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[8] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[8] ), + .dat_out ( ad_out[8] ) +); + +pci_out_reg ad_iob9 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[9] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[9] ), + .dat_out ( ad_out[9] ) +); + +pci_out_reg ad_iob10 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[10] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[10] ), + .dat_out ( ad_out[10] ) +); + +pci_out_reg ad_iob11 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[11] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[11] ), + .dat_out ( ad_out[11] ) +); + +pci_out_reg ad_iob12 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[12] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[12] ), + .dat_out ( ad_out[12] ) +); + +pci_out_reg ad_iob13 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[13] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[13] ), + .dat_out ( ad_out[13] ) +); + +pci_out_reg ad_iob14 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[14] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[14] ), + .dat_out ( ad_out[14] ) +); + +pci_out_reg ad_iob15 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mlow ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[15] ) , + .en_in ( ad_en_ctrl_mlow ) , + .en_out ( ad_en_out[15] ), + .dat_out ( ad_out[15] ) +); + +pci_out_reg ad_iob16 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[16] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[16] ), + .dat_out ( ad_out[16] ) +); + +pci_out_reg ad_iob17 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[17] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[17] ), + .dat_out ( ad_out[17] ) +); + +pci_out_reg ad_iob18 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[18] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[18] ), + .dat_out ( ad_out[18] ) +); + +pci_out_reg ad_iob19 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[19] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[19] ), + .dat_out ( ad_out[19] ) +); + +pci_out_reg ad_iob20 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[20] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[20] ), + .dat_out ( ad_out[20] ) +); + +pci_out_reg ad_iob21 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[21] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[21] ), + .dat_out ( ad_out[21] ) +); + +pci_out_reg ad_iob22 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[22] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[22] ), + .dat_out ( ad_out[22] ) +); + +pci_out_reg ad_iob23 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_mhigh ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[23] ) , + .en_in ( ad_en_ctrl_mhigh ) , + .en_out ( ad_en_out[23] ), + .dat_out ( ad_out[23] ) +); + +pci_out_reg ad_iob24 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[24] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[24] ), + .dat_out ( ad_out[24] ) +); + +pci_out_reg ad_iob25 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[25] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[25] ), + .dat_out ( ad_out[25] ) +); + +pci_out_reg ad_iob26 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[26] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[26] ), + .dat_out ( ad_out[26] ) +); + +pci_out_reg ad_iob27 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[27] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[27] ), + .dat_out ( ad_out[27] ) +); + +pci_out_reg ad_iob28 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[28] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[28] ), + .dat_out ( ad_out[28] ) +); + +pci_out_reg ad_iob29 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[29] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[29] ), + .dat_out ( ad_out[29] ) +); + +pci_out_reg ad_iob30 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[30] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[30] ), + .dat_out ( ad_out[30] ) +); + +pci_out_reg ad_iob31 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( ad_load_ctrl_high ), + .en_en_in ( 1'b1 ), + .dat_in ( temp_ad[31] ) , + .en_in ( ad_en_ctrl_high ) , + .en_out ( ad_en_out[31] ), + .dat_out ( ad_out[31] ) +); + +wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ; +wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ; + +pci_out_reg cbe_iob0 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( cbe_load_ctrl[0] ), + .en_en_in ( 1'b1 ), + .dat_in ( cbe_in[0] ) , + .en_in ( cbe_en_ctrl[0] ) , + .en_out ( cbe_en_out[0] ), + .dat_out ( cbe_out[0] ) +); + +pci_out_reg cbe_iob1 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( cbe_load_ctrl[1] ), + .en_en_in ( 1'b1 ), + .dat_in ( cbe_in[1] ) , + .en_in ( cbe_en_ctrl[1] ) , + .en_out ( cbe_en_out[1] ), + .dat_out ( cbe_out[1] ) +); + +pci_out_reg cbe_iob2 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( cbe_load_ctrl[2] ), + .en_en_in ( 1'b1 ), + .dat_in ( cbe_in[2] ) , + .en_in ( cbe_en_ctrl[2] ) , + .en_out ( cbe_en_out[2] ), + .dat_out ( cbe_out[2] ) +); + +pci_out_reg cbe_iob3 +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( cbe_load_ctrl[3] ), + .en_en_in ( 1'b1 ), + .dat_in ( cbe_in[3] ) , + .en_in ( cbe_en_ctrl[3] ) , + .en_out ( cbe_en_out[3] ), + .dat_out ( cbe_out[3] ) +); + +pci_out_reg frame_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( frame_load_in ), + .en_en_in ( 1'b1 ), + .dat_in ( frame_in ) , + .en_in ( frame_en_in ) , + .en_out ( frame_en_out ), + .dat_out ( frame_out ) +); + +pci_out_reg irdy_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( irdy_in ) , + .en_in ( irdy_en_in ) , + .en_out ( irdy_en_out ), + .dat_out ( irdy_out ) +); + +pci_out_reg trdy_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( trdy_in ) , + .en_in ( trdy_en_in ) , + .en_out ( trdy_en_out ), + .dat_out ( trdy_out ) +); + +pci_out_reg stop_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( stop_in ) , + .en_in ( stop_en_in ) , + .en_out ( stop_en_out ), + .dat_out ( stop_out ) +); + +pci_out_reg devsel_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( devsel_in ) , + .en_in ( devsel_en_in ) , + .en_out ( devsel_en_out ), + .dat_out ( devsel_out ) +); + +pci_out_reg par_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( par_in ) , + .en_in ( par_en_in ) , + .en_out ( par_en_out ), + .dat_out ( par_out ) +); + +pci_out_reg perr_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( perr_in ) , + .en_in ( perr_en_in ) , + .en_out ( perr_en_out ), + .dat_out ( perr_out ) +); + +pci_out_reg serr_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( serr_in ) , + .en_in ( serr_en_in ) , + .en_out ( serr_en_out ), + .dat_out ( serr_out ) +); + +pci_out_reg req_iob +( + .reset_in ( reset_in ), + .clk_in ( clk_in) , + .dat_en_in ( 1'b1 ), + .en_en_in ( 1'b1 ), + .dat_in ( req_in ) , + .en_in ( init_complete_in ) , + .en_out ( req_en_out ), + .dat_out ( req_out ) +); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_en_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_en_crit.v new file mode 100644 index 000000000..788077dc9 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_en_crit.v @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_io_mux_ad_en_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_io_mux_ad_en_crit.v,v $ +// Revision 1.2 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// module provides equation for ad output enables, which uses critical pci bus inputs + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// module is provided for ad bus output enable Flip-Flops values +module pci_io_mux_ad_en_crit +( + ad_en_in, + pci_frame_in, + pci_trdy_in, + pci_stop_in, + ad_en_out +); +input ad_en_in, + pci_frame_in, + pci_trdy_in, + pci_stop_in ; +output ad_en_out ; + +assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ; +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_load_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_load_crit.v new file mode 100644 index 000000000..4fd91e69e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_io_mux_ad_load_crit.v @@ -0,0 +1,77 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_io_mux_ad_load_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_io_mux_ad_load_crit.v,v $ +// Revision 1.2 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// module is provided for last level of logic for loading AD output flip-flops +// and output backup flip - flops +module pci_io_mux_ad_load_crit +( + load_in, + load_on_transfer_in, + pci_irdy_in, + pci_trdy_in, + load_out +); + +input load_in, + load_on_transfer_in, + pci_irdy_in, + pci_trdy_in ; + +output load_out ; + +assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_irdy_out_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_irdy_out_crit.v new file mode 100644 index 000000000..d097b9e67 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_irdy_out_crit.v @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "irdy_out_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_irdy_out_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// This module is used in master state machine for IRDY output driving + +module pci_irdy_out_crit +( + pci_irdy_out, + irdy_slow_in, + pci_frame_out_in, + pci_trdy_in, + pci_stop_in +) ; + +output pci_irdy_out ; +input irdy_slow_in, + pci_frame_out_in, + pci_trdy_in, + pci_stop_in ; + +assign pci_irdy_out = irdy_slow_in || (pci_frame_out_in && ~(pci_trdy_in && pci_stop_in)) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_en_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_en_crit.v new file mode 100644 index 000000000..cc4a169a2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_en_crit.v @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "mas_ad_en_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_mas_ad_en_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// This module is used in master state machine for AD lines output enable driving +module pci_mas_ad_en_crit +( + pci_ad_en_out, + ad_en_slow_in, + ad_en_on_grant_in, + pci_gnt_in +) ; + +output pci_ad_en_out ; +input ad_en_slow_in, + ad_en_on_grant_in, + pci_gnt_in ; + +assign pci_ad_en_out = ad_en_slow_in || (ad_en_on_grant_in && !pci_gnt_in) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_load_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_load_crit.v new file mode 100644 index 000000000..6ec59a0c3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ad_load_crit.v @@ -0,0 +1,70 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "mas_ad_load_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_mas_ad_load_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// module is included for loading output flip - flops by monitoring timing critical GNT pci input +module pci_mas_ad_load_crit +( + ad_load_out, + ad_load_in, + ad_load_on_grant_in, + pci_gnt_in +); +output ad_load_out ; +input ad_load_in, + ad_load_on_grant_in, + pci_gnt_in ; + +assign ad_load_out = ad_load_in || ( ad_load_on_grant_in && !pci_gnt_in ) ; +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ch_state_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ch_state_crit.v new file mode 100644 index 000000000..d05779aa3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_mas_ch_state_crit.v @@ -0,0 +1,85 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "mas_ch_state_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_mas_ch_state_crit.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// Module is used in master state machine for state machine clock enable driving + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_mas_ch_state_crit +( + change_state_out, + ch_state_med_in, + sm_data_phases_in, + pci_trdy_in, + pci_stop_in +) ; + +output change_state_out ; +input ch_state_med_in, + sm_data_phases_in, + pci_trdy_in, + pci_stop_in ; + +assign change_state_out = ch_state_med_in || sm_data_phases_in && (~(pci_trdy_in && pci_stop_in)) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm.v new file mode 100644 index 000000000..4787f4bdb --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm.v @@ -0,0 +1,615 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_master32_sm.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_master32_sm.v,v $ +// Revision 1.5 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.4 2003/01/21 16:06:56 mihad +// Bug fixes, testcases added. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:29 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module includes pci master state machine and surrounding logic + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" + +module pci_master32_sm +( + // system inputs + clk_in, + reset_in, + // arbitration + pci_req_out, + pci_gnt_in, + // master in/outs + pci_frame_in, + pci_frame_out, + pci_frame_out_in, + pci_frame_load_out, + pci_frame_en_in, + pci_frame_en_out, + pci_irdy_in, + pci_irdy_out, + pci_irdy_en_out, + + // target response inputs + pci_trdy_in, + pci_trdy_reg_in, + pci_stop_in, + pci_stop_reg_in, + pci_devsel_in, + pci_devsel_reg_in, + + // address, data, bus command, byte enable in/outs + pci_ad_reg_in, + pci_ad_out, + pci_ad_en_out, + pci_cbe_out, + pci_cbe_en_out, + + // other side of state machine + address_in, + bc_in, + data_in, + data_out, + be_in, + req_in, + rdy_in, + last_in, + next_data_in, + next_be_in, + next_last_in, + ad_load_out, + ad_load_on_transfer_out, + wait_out, + wtransfer_out, + rtransfer_out, + retry_out, + rerror_out, + first_out, + mabort_out, + latency_tim_val_in +) ; + +// system inputs +input clk_in, + reset_in ; + +/*================================================================================================================== +PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation +module. Enables are separate signals. +==================================================================================================================*/ +// arbitration +output pci_req_out ; + +input pci_gnt_in ; + +// master in/outs +input pci_frame_in ; +input pci_frame_en_in ; +input pci_frame_out_in ; + +output pci_frame_out, + pci_frame_en_out ; + +output pci_frame_load_out ; + +input pci_irdy_in ; +output pci_irdy_out, + pci_irdy_en_out; + +// target response inputs +input pci_trdy_in, + pci_trdy_reg_in, + pci_stop_in, + pci_stop_reg_in, + pci_devsel_in, + pci_devsel_reg_in ; + +// address, data, bus command, byte enable in/outs +input [31:0] pci_ad_reg_in ; +output [31:0] pci_ad_out ; + +reg [31:0] pci_ad_out ; + +output pci_ad_en_out ; + +output [3:0] pci_cbe_out ; + +reg [3:0] pci_cbe_out ; + +output pci_cbe_en_out ; + +input [31:0] address_in ; // current request address input + +input [3:0] bc_in ; // current request bus command input + +input [31:0] data_in ; // current dataphase data input + +output [31:0] data_out ; // for read operations - current request data output + +reg [31:0] data_out ; + +input [3:0] be_in ; // current dataphase byte enable inputs + +input req_in ; // initiator cycle is requested +input rdy_in ; // requestor indicates that data is ready to be sent for write transaction and ready to + // be received on read transaction +input last_in ; // last dataphase in current transaction indicator + +// status outputs +output wait_out, // wait indicates to the backend that dataphases are not in progress on PCI bus + wtransfer_out, // on any rising clock edge that this status is 1, data is transferred - heavy constraints here + rtransfer_out, // registered transfer indicator - when 1 indicates that data was transfered on previous clock cycle + retry_out, // retry status output - when target signals a retry + rerror_out, // registered error output - when 1 indicates that error was signalled by a target on previous clock cycle + first_out , // indicates whether or not any data was transfered in current transaction + mabort_out; // master abort indicator + +reg wait_out ; + +// latency timer value input - state machine starts latency timer whenever it starts a transaction and last is not +// asserted ( meaning burst transfer ). +input [7:0] latency_tim_val_in ; + +// next data, byte enable and last inputs +input [31:0] next_data_in ; +input [3:0] next_be_in ; +input next_last_in ; + +// clock enable for data output flip-flops - whenever data is transfered, sm loads next data to those flip flops +output ad_load_out, + ad_load_on_transfer_out ; + +// parameters - states - one hot +// idle state +parameter S_IDLE = 4'h1 ; + +// address state +parameter S_ADDRESS = 4'h2 ; + +// transfer state - dataphases +parameter S_TRANSFER = 4'h4 ; + +// turn arround state +parameter S_TA_END = 4'h8 ; + +// change state - clock enable for sm state register +wire change_state ; +// next state for state machine +reg [3:0] next_state ; +// SM state register +reg [3:0] cur_state ; + +// variables for indicating which state state machine is in +// this variables are used to reduce logic levels in case of heavily constrained PCI signals +reg sm_idle ; +reg sm_address ; +reg sm_data_phases ; +reg sm_turn_arround ; + +// state machine register control logic with clock enable +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + cur_state <= #`FF_DELAY S_IDLE ; + else + if ( change_state ) + cur_state <= #`FF_DELAY next_state ; +end + +// parameters - data selector - ad and bc lines switch between address/data and bus command/byte enable respectively +parameter SEL_ADDR_BC = 2'b01 ; +parameter SEL_DATA_BE = 2'b00 ; +parameter SEL_NEXT_DATA_BE = 2'b11 ; + +reg [1:0] wdata_selector ; + +wire u_dont_have_pci_bus = pci_gnt_in || ~pci_frame_in || ~pci_irdy_in ; // pci master can't start a transaction when GNT is deasserted ( 1 ) or + // bus is not in idle state ( FRAME and IRDY both 1 ) +wire u_have_pci_bus = ~pci_gnt_in && pci_frame_in && pci_irdy_in ; + +// decode count enable - counter that counts cycles passed since address phase +wire sm_decode_count_enable = sm_data_phases ; // counter is enabled when master wants to transfer +wire decode_count_enable = sm_decode_count_enable && pci_trdy_in && pci_stop_in && pci_devsel_in ; // and target is not responding +wire decode_count_load = ~decode_count_enable ; +reg [2:0] decode_count ; + +wire decode_to = ~( decode_count[2] || decode_count[1]) ; + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + // initial value of counter is 4 + decode_count <= #`FF_DELAY 3'h4 ; + else + if ( decode_count_load ) + decode_count <= #`FF_DELAY 3'h4 ; + else + if ( decode_count_enable ) + decode_count <= #`FF_DELAY decode_count - 1'b1 ; +end + +// Bus commands LSbit indicates whether operation is a read or a write +wire do_write = bc_in[0] ; + +// latency timer +reg [7:0] latency_timer ; + +wire latency_time_out = ~( + (latency_timer[7] || latency_timer[6] || latency_timer[5] || latency_timer[4]) || + (latency_timer[3] || latency_timer[2] || latency_timer[1] ) + ) ; + +wire latency_timer_enable = (sm_address || sm_data_phases) && ~latency_time_out ; +wire latency_timer_load = ~sm_address && ~sm_data_phases ; + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + latency_timer <= #`FF_DELAY 8'h00 ; + else + if ( latency_timer_load ) + latency_timer <= #`FF_DELAY latency_tim_val_in ; + else + if ( latency_timer_enable) // latency timer counts down until it expires - then it stops + latency_timer <= #`FF_DELAY latency_timer - 1'b1 ; +end + +// master abort indicators - when decode time out occurres and still no target response is received +wire do_master_abort = decode_to && pci_trdy_in && pci_stop_in && pci_devsel_in ; +reg mabort1 ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + mabort1 <= #`FF_DELAY 1'b0 ; + else + mabort1 <= #`FF_DELAY do_master_abort ; +end + +reg mabort2 ; +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + mabort2 <= #`FF_DELAY 1'b0 ; + else + mabort2 <= #`FF_DELAY mabort1 ; +end + +// master abort is only asserted for one clock cycle +assign mabort_out = mabort1 && ~mabort2 ; + +// register indicating when master should do timeout termination (latency timer expires) +reg timeout ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + timeout <= #`FF_DELAY 1'b0 ; + else + timeout <= #`FF_DELAY (latency_time_out && ~pci_frame_out_in && pci_gnt_in || timeout ) && ~wait_out ; +end + +wire timeout_termination = sm_turn_arround && timeout && pci_stop_reg_in ; + +// frame control logic +// frame is forced to 0 (active) when state machine is in idle state, since only possible next state is address state which always drives frame active +wire force_frame = ~sm_idle ; +// slow signal for frame calculated from various registers in the core +wire slow_frame = last_in || (latency_time_out && pci_gnt_in) || (next_last_in && sm_data_phases) || mabort1 ; +// critical timing frame logic in separate module - some combinations of target signals force frame to inactive state immediately after sampled asserted +// (STOP) +pci_frame_crit frame_iob_feed +( + .pci_frame_out (pci_frame_out), + .force_frame_in (force_frame), + .slow_frame_in (slow_frame), + .pci_stop_in (pci_stop_in) +) ; + +// frame IOB flip flop's clock enable signal +// slow clock enable - calculated from internal - non critical paths +wire frame_load_slow = sm_idle || sm_address || mabort1 ; + +// critical clock enable for frame IOB in separate module - target response signals actually allow frame value change - critical timing +pci_frame_load_crit frame_iob_ce +( + .pci_frame_load_out (pci_frame_load_out), + .sm_data_phases_in (sm_data_phases), + .frame_load_slow_in (frame_load_slow), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in) +) ; + +// IRDY driving +// non critical path for IRDY calculation +wire irdy_slow = pci_frame_out_in && mabort1 || mabort2 ; + +// critical path in separate module +pci_irdy_out_crit irdy_iob_feed +( + .pci_irdy_out (pci_irdy_out), + .irdy_slow_in (irdy_slow), + .pci_frame_out_in (pci_frame_out_in), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in) +) ; + +// transfer FF indicator - when first transfer occurs it is set to 1 so backend can distinguish between disconnects and retries. +wire sm_transfer = sm_data_phases ; +reg transfer ; + +wire transfer_input = sm_transfer && (~(pci_trdy_in || pci_devsel_in) || transfer) ; + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + transfer <= #`FF_DELAY 1'b0 ; + else + transfer <= #`FF_DELAY transfer_input ; +end + +assign first_out = ~transfer ; + +// xfast transfer status output - it's only negated target ready, since wait indicator qualifies valid transfer +assign wtransfer_out = ~pci_trdy_in ; + +// registered transfer status output - calculated from registered target response inputs +assign rtransfer_out = ~(pci_trdy_reg_in || pci_devsel_reg_in) ; + +// registered error status - calculated from registered target response inputs +assign rerror_out = (~pci_stop_reg_in && pci_devsel_reg_in) ; + +// retry is signalled to backend depending on registered target response or when latency timer expires +assign retry_out = timeout_termination || (~pci_stop_reg_in && ~pci_devsel_reg_in) ; + +// AD output flip flops' clock enable +// new data is loaded to AD outputs whenever state machine is idle, bus was granted and bus is in idle state or +// when address phase is about to be finished +wire ad_load_slow = sm_address ; +wire ad_load_on_grant = sm_idle && pci_frame_in && pci_irdy_in ; + +pci_mas_ad_load_crit mas_ad_load_feed +( + .ad_load_out (ad_load_out), + .ad_load_in (ad_load_slow), + .ad_load_on_grant_in (ad_load_on_grant), + .pci_gnt_in (pci_gnt_in) +); + +// next data loading is allowed when state machine is in transfer state and operation is a write +assign ad_load_on_transfer_out = sm_data_phases && do_write ; + +// request for a bus is issued anytime when backend is requesting a transaction and state machine is in idle state +assign pci_req_out = ~(req_in && sm_idle) ; + +// change state signal is actually clock enable for state register +// Non critical path for state change enable: +// state is always changed when: +// - address phase is finishing +// - state machine is in turn arround state +// - state machine is in transfer state and master abort termination is in progress + +wire ch_state_slow = sm_address || sm_turn_arround || sm_data_phases && ( pci_frame_out_in && mabort1 || mabort2 ) ; + +// a bit more critical change state enable is calculated with GNT signal +wire ch_state_med = ch_state_slow || sm_idle && u_have_pci_bus && req_in && rdy_in ; + +// most critical change state enable - calculated from target response signals +pci_mas_ch_state_crit state_machine_ce +( + .change_state_out (change_state), + .ch_state_med_in (ch_state_med), + .sm_data_phases_in (sm_data_phases), + .pci_trdy_in (pci_trdy_in), + .pci_stop_in (pci_stop_in) +) ; + +// ad enable driving +// also divided in several categories - from less critical to most critical in separate module +//wire ad_en_slowest = do_write && (sm_address || sm_data_phases && ~pci_frame_out_in) ; +//wire ad_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ; +//wire ad_en_slow = ad_en_on_grant && ~pci_gnt_in || ad_en_slowest ; +//wire ad_en_keep = sm_data_phases && do_write && (pci_frame_out_in && ~mabort1 && ~mabort2) ; + +wire ad_en_slow = do_write && ( sm_address || ( sm_data_phases && !( ( pci_frame_out_in && mabort1 ) || mabort2 ) ) ) ; +wire ad_en_on_grant = ( sm_idle && pci_frame_in && pci_irdy_in ) || sm_turn_arround ; + +// critical timing ad enable - calculated from grant input +pci_mas_ad_en_crit ad_iob_oe_feed +( + .pci_ad_en_out (pci_ad_en_out), + .ad_en_slow_in (ad_en_slow), + .ad_en_on_grant_in (ad_en_on_grant), + .pci_gnt_in (pci_gnt_in) +) ; + +// cbe enable driving +wire cbe_en_on_grant = sm_idle && pci_frame_in && pci_irdy_in || sm_turn_arround ; +wire cbe_en_slow = cbe_en_on_grant && ~pci_gnt_in || sm_address || sm_data_phases && ~pci_frame_out_in ; +wire cbe_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ; + +// most critical cbe enable in separate module - calculated with most critical target inputs +pci_cbe_en_crit cbe_iob_feed +( + .pci_cbe_en_out (pci_cbe_en_out), + .cbe_en_slow_in (cbe_en_slow), + .cbe_en_keep_in (cbe_en_keep), + .pci_stop_in (pci_stop_in), + .pci_trdy_in (pci_trdy_in) + +) ; + +// IRDY enable is equal to FRAME enable delayed for one clock +assign pci_irdy_en_out = pci_frame_en_in ; + +// frame enable driving - sometimes it's calculated from non critical paths +wire frame_en_slow = (sm_idle && u_have_pci_bus && req_in && rdy_in) || sm_address || (sm_data_phases && ~pci_frame_out_in) ; +wire frame_en_keep = sm_data_phases && pci_frame_out_in && ~mabort1 && ~mabort2 ; + +// most critical frame enable - calculated from heavily constrained target inputs in separate module +pci_frame_en_crit frame_iob_en_feed +( + .pci_frame_en_out (pci_frame_en_out), + .frame_en_slow_in (frame_en_slow), + .frame_en_keep_in (frame_en_keep), + .pci_stop_in (pci_stop_in), + .pci_trdy_in (pci_trdy_in) +) ; + +// state machine next state definitions +always@( + cur_state or + do_write or + pci_frame_out_in +) +begin + // default values for state machine outputs + wait_out = 1'b1 ; + wdata_selector = SEL_ADDR_BC ; + sm_idle = 1'b0 ; + sm_address = 1'b0 ; + sm_data_phases = 1'b0 ; + sm_turn_arround = 1'b0 ; + + case ( cur_state ) + + S_IDLE: begin + // indicate the state + sm_idle = 1'b1 ; + // assign next state - only possible is address - if state machine is supposed to stay in idle state + // outside signals disable the clock + next_state = S_ADDRESS ; + wdata_selector = SEL_DATA_BE ; + end + + S_ADDRESS: begin + // indicate the state + sm_address = 1'b1 ; + // select appropriate data/be for outputs + wdata_selector = SEL_NEXT_DATA_BE ; + // only possible next state is transfer state + next_state = S_TRANSFER ; + end + + S_TRANSFER: begin + // during transfers wait indicator is inactive - all status signals are now valid + wait_out = 1'b0 ; + // indicate the state + sm_data_phases = 1'b1 ; + // select appropriate data/be for outputs + wdata_selector = SEL_NEXT_DATA_BE ; + if ( pci_frame_out_in ) + begin + // when frame is inactive next state will be turn arround + next_state = S_TA_END ; + end + else + // while frame is active state cannot be anything else then transfer + next_state = S_TRANSFER ; + end + + S_TA_END: begin + // wait is still inactive because of registered statuses + wait_out = 1'b0 ; + // indicate the state + sm_turn_arround = 1'b1 ; + // next state is always idle + next_state = S_IDLE ; + end + default: next_state = S_IDLE ; + endcase +end + +// ad and cbe lines multiplexer for write data +reg [1:0] rdata_selector ; +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + rdata_selector <= #`FF_DELAY SEL_ADDR_BC ; + else + if ( change_state ) + rdata_selector <= #`FF_DELAY wdata_selector ; +end + +always@(rdata_selector or address_in or bc_in or data_in or be_in or next_data_in or next_be_in) +begin + case ( rdata_selector ) + SEL_ADDR_BC: begin + pci_ad_out = address_in ; + pci_cbe_out = bc_in ; + end + + SEL_DATA_BE: begin + pci_ad_out = data_in ; + pci_cbe_out = be_in ; + end + SEL_NEXT_DATA_BE, + 2'b10: begin + pci_ad_out = next_data_in ; + pci_cbe_out = next_be_in ; + end + endcase +end + +// data output mux for reads +always@(mabort_out or pci_ad_reg_in) +begin + if ( mabort_out ) + data_out = 32'hFFFF_FFFF ; + else + data_out = pci_ad_reg_in ; +end +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm_if.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm_if.v new file mode 100644 index 000000000..0be11ac4b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_master32_sm_if.v @@ -0,0 +1,846 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_master32_sm_if.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_master32_sm_if.v,v $ +// Revision 1.7 2004/03/19 16:36:55 mihad +// Single PCI Master write fix. +// +// Revision 1.6 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.5 2003/06/12 10:12:22 mihad +// Changed one critical PCI bus signal logic. +// +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:29 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" +`include "bus_commands.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +/*==================================================================== +Module provides interface between PCI bridge internals and PCI master +state machine +====================================================================*/ +module pci_master32_sm_if +( + clk_in, + reset_in, + + // interconnect to pci master state machine + address_out, + bc_out, + data_out, + data_in, + be_out, + req_out, + rdy_out, + last_out, + + next_data_out, + next_be_out, + next_last_out, + + // status inputs from master SM + wait_in, + wtransfer_in, + rtransfer_in, + retry_in, + rerror_in, + first_in , + mabort_in, + + + // WISHBONE WRITE fifo inputs and outputs + wbw_renable_out, + wbw_fifo_addr_data_in, + wbw_fifo_cbe_in, + wbw_fifo_control_in, + wbw_fifo_empty_in, + wbw_fifo_transaction_ready_in, + + // WISHBONE READ fifo inputs and outputs + wbr_fifo_wenable_out, + wbr_fifo_data_out, + wbr_fifo_be_out, + wbr_fifo_control_out, + + // delayed transaction control logic inputs and outputs + del_wdata_in, + del_complete_out, + del_req_in, + del_addr_in, + del_bc_in, + del_be_in, + del_burst_in, + del_error_out, + del_rty_exp_out, + del_we_in, + + // configuration space interconnect + // error reporting + err_addr_out, + err_bc_out, + err_signal_out, + err_source_out, + err_rty_exp_out, + + cache_line_size_in, + + // two signals for pci control and status + mabort_received_out, + tabort_received_out, + + posted_write_not_present_out +); + +// system inputs +input clk_in ; +input reset_in ; + +// PCI master state machine interconnect +output [31:0] address_out ; // address output + +output [3:0] bc_out ; // bus command output +reg [3:0] bc_out ; + +output [31:0] data_out ; // data output for writes +reg [31:0] data_out ; + +input [31:0] data_in ; // data input for reads +output [3:0] be_out ; // byte enable output +reg [3:0] be_out ; + +output req_out ; // request output + +output rdy_out ; // ready output +reg rdy_out ; + +output last_out ; // last data indicator output + +output [31:0] next_data_out ; // next data output +output [3:0] next_be_out ; // next byte enable output +output next_last_out ; // next transfer last indicator + +input wait_in, + wtransfer_in, + rtransfer_in, + retry_in, + rerror_in, + first_in , + mabort_in ; + +// WISHBONE write fifo interconnect +output wbw_renable_out ; // WBW_FIFO read enable signal + +input [31:0] wbw_fifo_addr_data_in ; // WBW_FIFO address/data bus +input [3:0] wbw_fifo_cbe_in ; // WBW_FIFO command/byte enable bus +input [3:0] wbw_fifo_control_in ; // WBW_FIFO control bus +input wbw_fifo_empty_in ; // WBW_FIFO's empty status indicator +input wbw_fifo_transaction_ready_in ; // WBW_FIFO transaction ready indicator + +// WISHBONE read FIFO interconnect +output wbr_fifo_wenable_out ; // write enable for WBR_FIFO + +output [31:0] wbr_fifo_data_out ; // data output to WBR_FIFO + +output [3:0] wbr_fifo_be_out ; // byte enable output for WBR_FIFO + +output [3:0] wbr_fifo_control_out ; // WBR_FIFO control output + +// delayed transaction control logic inputs and outputs +input [31:0] del_wdata_in ; // delayed write data input +output del_complete_out ; // delayed transaction completed output + +input del_req_in ; // delayed transaction request +input [31:0] del_addr_in ; // delayed transaction address +input [3:0] del_bc_in ; // delayed transaction bus command input +input [3:0] del_be_in ; // delayed transaction byte enables input +input del_burst_in ; // delayed transaction burst req. indicator +output del_error_out ; // delayed transation error termination signal + +output del_rty_exp_out ; // retry expired output for delayed transactions + +input del_we_in ; // delayed write request indicator + +output [31:0] err_addr_out ; // erroneous address output +output [3:0] err_bc_out ; // erroneous bus command output + +output err_signal_out ; // error signalization + +output err_source_out ; // error source indicator + +input [7:0] cache_line_size_in ; // cache line size value input + +output err_rty_exp_out ; // retry expired error output + +output mabort_received_out ; // master abort signaled to status register +output tabort_received_out ; // target abort signaled to status register + +output posted_write_not_present_out ; // used in target state machine - must deny read completions when this signal is 0 + + +assign err_bc_out = bc_out ; + +// assign read outputs +/*================================================================================================================== +WISHBONE read FIFO data outputs - just link them to SM data outputs and delayed BE input +==================================================================================================================*/ +assign wbr_fifo_data_out = data_in ; +assign wbr_fifo_be_out = del_be_in ; + +// decode if current bus command is configuration command +wire conf_cyc_bc = ( bc_out[3:1] == `BC_CONF_RW ) ; + +// register for indicating that current data is also last in transfer +reg current_last ; + +// register indicating that last data was transfered OK +reg last_transfered ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + last_transfered <= #`FF_DELAY 1'b0 ; + else + last_transfered <= #`FF_DELAY ~wait_in && last_out && wtransfer_in ; +end + +// status signals output assignement +assign mabort_received_out = mabort_in ; + +wire tabort_ff_in = ~wait_in && rerror_in ; + +reg tabort_received_out ; +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + tabort_received_out <= #`FF_DELAY 1'b0 ; + else + tabort_received_out <= #`FF_DELAY tabort_ff_in ; +end + +// error recovery indicator +reg err_recovery ; + +// operation is locked until error recovery is in progress or error bit is not cleared in configuration space +wire err_lock = err_recovery ; + +// three requests are possible - posted write, delayed write and delayed read +reg del_write_req ; +reg posted_write_req ; +reg del_read_req ; + +// assign request output +assign req_out = del_write_req || posted_write_req || del_read_req ; + +// posted write is not present, when WB Write Fifo is empty and posted write transaction is not beeing requested at present time +assign posted_write_not_present_out = !posted_write_req && wbw_fifo_empty_in ; + +// write requests are staged, so data is read from source into current data register and next data register +reg write_req_int ; +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + write_req_int <= #`FF_DELAY 1'b0 ; + else + write_req_int <= #`FF_DELAY posted_write_req || del_write_req ; + +end + +// ready output is generated one clock after request for reads and two after for writes +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + rdy_out <= #`FF_DELAY 1'b0 ; + else + rdy_out <= #`FF_DELAY del_read_req || ( (posted_write_req || del_write_req) && write_req_int) ; +end + +// wires with logic used as inputs to request FFs +wire do_posted_write = ( wbw_fifo_transaction_ready_in && ~wbw_fifo_empty_in && ~err_lock ) ; +wire do_del = ( del_req_in && ~err_lock && wbw_fifo_empty_in ) ; +wire do_del_write = do_del && del_we_in ; +wire do_del_read = do_del && ~del_we_in ; + +// register for indicating current operation's data source +parameter DELAYED_WRITE = 1'b1 ; +parameter POSTED_WRITE = 1'b0 ; + +// new data source - depending on which transaction will be processed next - delayed read is here because source of byte enables must +// be specified for delayed reads also - data source is not relevant for delayed reads, so value is don't care anyway +wire new_data_source = (do_del_write || do_del_read) ? DELAYED_WRITE : POSTED_WRITE ; // input to data source register +wire data_source_change = ~req_out ; // change (enable) for data source register - when no requests are in progress + +reg data_source ; // data source value +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + // default value is posted write source - wbw_fifo + data_source <= #`FF_DELAY POSTED_WRITE ; + else + if (data_source_change) + // change data source on rising clock edge + data_source <= #`FF_DELAY new_data_source ; +end + +// multiplexer for data output to PCI MASTER state machine +reg [31:0] source_data ; +reg [3:0] source_be ; +always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in or del_burst_in) +begin + case (data_source) + POSTED_WRITE: begin + source_data = wbw_fifo_addr_data_in ; + source_be = wbw_fifo_cbe_in ; + end + DELAYED_WRITE: begin + source_data = del_wdata_in ; + // read all bytes during delayed burst read! + source_be = ~( del_be_in | {4{del_burst_in}} ) ; + end + endcase +end + +wire waddr = wbw_fifo_control_in[`ADDR_CTRL_BIT] ; + +// address change indicator - address is allowed to be loaded only when no transaction is in progress! +wire address_change = ~req_out ; // address change - whenever there is no request in progress + +// new address - input to register storing address of current request - if posted write request will be next, +// load address and bus command from wbw_fifo, else load data from delayed transaction logic +wire [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ; +wire [3:0] new_bc = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ; + +// address counter enable - only for posted writes when data is actually transfered +wire addr_count_en = !wait_in && posted_write_req && rtransfer_in ; + +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + bc_out <= #`FF_DELAY `BC_RESERVED0 ; + else + if (address_change) + bc_out <= #`FF_DELAY new_bc ; +end + +reg [29:0] current_dword_address ; + +// DWORD address counter with load +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + current_dword_address <= #`FF_DELAY 30'h0000_0000 ; + else + if (address_change) + current_dword_address <= #`FF_DELAY new_address[31:2] ; + else + if (addr_count_en) + current_dword_address <= #`FF_DELAY current_dword_address + 1'b1 ; +end + +reg [1:0] current_byte_address ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + current_byte_address <= #`FF_DELAY 2'b00 ; + else + if (address_change) + current_byte_address <= #`FF_DELAY new_address[1:0] ; +end + +// byte address generation logic +reg [ 1: 0] generated_byte_adr ; +reg [ 1: 0] pci_byte_adr ; + +always@(be_out) +begin + casex(be_out) + 4'bxxx0:generated_byte_adr = 2'b00 ; + 4'bxx01:generated_byte_adr = 2'b01 ; + 4'bx011:generated_byte_adr = 2'b10 ; + 4'b0111:generated_byte_adr = 2'b11 ; + 4'b1111:generated_byte_adr = 2'b00 ; + endcase +end + +always@(generated_byte_adr or bc_out or current_byte_address) +begin + // for memory access commands, set lower 2 address bits to 0 + if ((bc_out == `BC_MEM_READ) | (bc_out == `BC_MEM_WRITE) | + (bc_out == `BC_MEM_READ_MUL) | (bc_out == `BC_MEM_READ_LN) | + (bc_out == `BC_MEM_WRITE_INVAL)) + begin + pci_byte_adr = 2'b00 ; + end + else if ((bc_out == `BC_IO_WRITE) | (bc_out == `BC_IO_READ)) + begin + pci_byte_adr = generated_byte_adr ; + end + else + begin + pci_byte_adr = current_byte_address ; + end +end + +// address output to PCI master state machine assignment +assign address_out = { current_dword_address, pci_byte_adr } ; + +// the same for erroneous address assignement +assign err_addr_out = { current_dword_address, pci_byte_adr } ; + +// cacheline size counter - for read transaction length control +// cache line count is enabled during burst reads when data is actually transfered +wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in ; + +// cache line counter is loaded when del read request is not in progress +wire read_count_load = ~del_read_req ; + +reg [(`WBR_ADDR_LENGTH - 1):0] max_read_count ; +always@(cache_line_size_in or del_bc_in) +begin + if ( (cache_line_size_in >= `WBR_DEPTH) || (~del_bc_in[1] && ~del_bc_in[0]) ) + max_read_count = `WBR_DEPTH - 1'b1; + else + max_read_count = cache_line_size_in ; +end + +reg [(`WBR_ADDR_LENGTH - 1):0] read_count ; + +// cache line bound indicator - it signals when data for one complete cacheline was read +wire read_bound_comb = ~|(read_count[(`WBR_ADDR_LENGTH - 1):2]) ; +reg read_bound ; +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + read_bound <= #`FF_DELAY 1'b0 ; + else if (read_count_load) + read_bound <= #`FF_DELAY 1'b0 ; + else if ( read_count_enable ) + read_bound <= #`FF_DELAY read_bound_comb ; +end + +wire read_count_change_val = read_count_load | read_count_enable ; + +wire [(`WBR_ADDR_LENGTH - 1):0] read_count_next = read_count_load ? max_read_count : (read_count - 1'b1) ; + +// down counter with load +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + read_count <= #`FF_DELAY 0 ; + else +/* if (read_count_load) + read_count <= #`FF_DELAY max_read_count ; + else + if (read_count_enable) + read_count <= #`FF_DELAY read_count - 1'b1 ; +*/ if (read_count_change_val) + read_count <= #`FF_DELAY read_count_next ; +end + +// flip flop indicating error recovery is in progress +reg err_recovery_in ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + err_recovery <= #`FF_DELAY 1'b0 ; + else + err_recovery <= #`FF_DELAY err_recovery_in ; +end + +/*// retry counter implementation +reg [7:0] retry_count ; + +wire retry_expired = ~|(retry_count[7:1]) ; + +// loading of retry counter - whenever no request is present or other termination than retry or wait is signalled +wire retry_load = ~req_out || (~wait_in && rtransfer_in) ; + +// retry DOWN counter with load +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + retry_count <= #`FF_DELAY 8'hFF ; + else + if ( retry_load ) + retry_count <= #`FF_DELAY `PCI_RTY_CNT_MAX ; + else + if (retry_in) + retry_count <= #`FF_DELAY retry_count - 1'b1 ; +end*/ + +/*================================================================================================================== +Delayed write requests are always single transfers! +Delayed write request starts, when no request is currently beeing processed and it is signaled from other side +of the bridge. +==================================================================================================================*/ +// delayed write request FF input control +reg del_write_req_input ; + +always@( + do_del_write or + del_write_req or + posted_write_req or + del_read_req or + wait_in or + //retry_in or + //retry_expired or + rtransfer_in or + rerror_in or + mabort_in +) +begin + if (~del_write_req) + begin + // delayed write is not in progress and is requested + // delayed write can be requested when no other request is in progress + del_write_req_input = ~posted_write_req && ~del_read_req && do_del_write ; + end + else + begin + // delayed write request is in progress - assign input + del_write_req_input = wait_in || + ( /*~( retry_in && retry_expired) &&*/ + ~rtransfer_in && ~rerror_in && ~mabort_in + ); + end +end + +// delayed write request FLIP-FLOP +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + del_write_req <= #`FF_DELAY 1'b0 ; + else + del_write_req <= #`FF_DELAY del_write_req_input ; +end + +/*================================================================================================ +Posted write request indicator. +Posted write starts whenever no request is in progress and one whole posted write is +stored in WBW_FIFO. It ends on error terminations ( master, target abort, retry expired) or +data transfer terminations if last data is on top of FIFO. +Continues on wait, retry, and disconnect without data. +================================================================================================*/ +// posted write request FF input control +reg posted_write_req_input ; +always@( + do_posted_write or + del_write_req or + posted_write_req or + del_read_req or + wait_in or + //retry_in or + rerror_in or + mabort_in or + //retry_expired or + rtransfer_in or + last_transfered +) +begin + if (~posted_write_req) + begin + // posted write is not in progress + posted_write_req_input = ~del_write_req && ~del_read_req && do_posted_write ; + end + else + begin + posted_write_req_input = wait_in || + (/*~(retry_in && retry_expired && ~rtransfer_in) &&*/ + ~rerror_in && ~mabort_in && + ~(last_transfered) + ) ; + + end +end + +// posted write request flip flop +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + posted_write_req <= #`FF_DELAY 1'b0 ; + else + posted_write_req <= #`FF_DELAY posted_write_req_input ; + +end + +/*================================================================================================ +Delayed read request indicator. +Delayed read starts whenever no request is in progress and delayed read request is signaled from +other side of bridge. It ends on error terminations ( master, target abort, retry expired) or +data transfer terminations if it is not burst transfer or on cache line bounds on burst transfer. +It also ends on disconnects. +Continues on wait and retry. +================================================================================================*/ +// delayed read FF input control +reg del_read_req_input ; +always@( + do_del_read or + del_write_req or + posted_write_req or + del_read_req or + last_transfered or + wait_in or + retry_in or + //retry_expired or + mabort_in or + rtransfer_in or + rerror_in or + first_in or + del_complete_out +) +begin + if (~del_read_req) + begin + del_read_req_input = ~del_write_req && ~posted_write_req && ~del_complete_out && do_del_read ; + end + else + begin + del_read_req_input = wait_in || + ( ~(retry_in && (~first_in /*|| retry_expired */)) && + ~mabort_in && ~rerror_in && + ~(last_transfered) + ) ; + end +end + +// delayed read request FF +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + del_read_req <= #`FF_DELAY 1'b0 ; + else + del_read_req <= #`FF_DELAY del_read_req_input ; +end + +// wire indicating last entry of transaction on top of fifo +wire wlast = wbw_fifo_control_in[`LAST_CTRL_BIT] ; + +wire last_int = posted_write_req && wlast || del_write_req ; + +// intermidiate data, byte enable and last registers +reg [31:0] intermediate_data ; +reg [3:0] intermediate_be ; +reg intermediate_last ; + +wire intermediate_enable = ( posted_write_req || del_write_req ) && ( ~write_req_int || (( ~rdy_out || ~wait_in && rtransfer_in ) && ~intermediate_last)) ; + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + begin + intermediate_data <= #`FF_DELAY 32'h0000_0000 ; + intermediate_be <= #`FF_DELAY 4'h0 ; + intermediate_last <= #`FF_DELAY 1'b0 ; + end + else + if ( intermediate_enable ) + begin + intermediate_data <= #`FF_DELAY source_data ; + intermediate_be <= #`FF_DELAY source_be ; + intermediate_last <= #`FF_DELAY last_int ; + end +end + +// multiplexer for next data +reg [31:0] next_data_out ; +reg [3:0] next_be_out ; +reg write_next_last ; +reg [3:0] write_next_be ; + +always@ +( + rtransfer_in or + intermediate_data or + intermediate_be or + intermediate_last or + wbw_fifo_addr_data_in or + wbw_fifo_cbe_in or + wlast or + wait_in +) +begin + if( rtransfer_in & ~wait_in ) + begin + next_data_out = wbw_fifo_addr_data_in ; + write_next_last = wlast ; + write_next_be = wbw_fifo_cbe_in ; + end + else + begin + next_data_out = intermediate_data ; + write_next_last = intermediate_last ; + write_next_be = intermediate_be ; + end +end + +always@(del_read_req or source_be or write_next_be) +begin + if (del_read_req) + next_be_out = source_be ; + else + next_be_out = write_next_be ; +end +/*================================================================================================ +WBW_FIFO read enable - read from WBW_FIFO is performed on posted writes, when data transfer +termination is received - transfer or disconnect with data. Reads are enabled during error +recovery also, since erroneous transaction must be pulled out of FIFO! +================================================================================================*/ +// wbw_fifo read enable input control + +assign wbw_renable_out = ~req_out && (do_posted_write || err_recovery) || + posted_write_req && ( ~write_req_int || (~rdy_out && ~intermediate_last) || (~wait_in && rtransfer_in && ~intermediate_last)) ; + +/*================================================================================================ +WBR_FIFO write enable control - +writes to FIFO are possible only when delayed read request is in progress and data transfer +or error termination is signalled. It is not enabled on retry or disconnect without data. +================================================================================================*/ +// wbr_fifo write enable control - enabled when transfer is in progress and data is transfered or error is signalled +assign wbr_fifo_wenable_out = del_read_req && ~wait_in && ( rtransfer_in || mabort_in || rerror_in ) ; + +/*================================================================================================ +WBR_FIFO control output for identifying data entries. +This is necesary because of prefetched reads, which partially succeed. On error, error entry +gets in to signal it on WISHBONE bus if WISHBONE master reads up to this entry. +================================================================================================*/ +assign wbr_fifo_control_out[`ADDR_CTRL_BIT] = 1'b0 ; +assign wbr_fifo_control_out[`LAST_CTRL_BIT] = last_transfered ; +assign wbr_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rerror_in || (mabort_in && ~conf_cyc_bc) ; +assign wbr_fifo_control_out[`UNUSED_CTRL_BIT] = 1'b0 ; + +// retry expired error for posted writes control +//assign err_rty_exp_out = posted_write_req && ~wait_in && retry_in && retry_expired && ~rtransfer_in; +assign err_rty_exp_out = 1'b0 ; + +// error source and error signal output control logic - only for posted writes +assign err_source_out = mabort_in /*|| err_rty_exp_out*/ ; + +assign err_signal_out = /*err_rty_exp_out || */ posted_write_req && ~wait_in && (mabort_in || rerror_in) ; + +//assign del_rty_exp_out = (~wait_in && (del_read_req || del_write_req)) && (retry_in && retry_expired && ~rtransfer_in) ; +assign del_rty_exp_out = 1'b0 ; + +assign del_error_out = ~wait_in && (del_write_req || del_read_req) && ( (mabort_in && ~conf_cyc_bc) || rerror_in ) ; + +wire del_write_complete = del_write_req && ~wait_in && ( rtransfer_in || rerror_in || mabort_in ) ; +wire del_read_complete = del_read_req && ~wait_in && ( rerror_in || mabort_in || last_transfered || ( retry_in && ~first_in ) ) ; + +assign del_complete_out = ~wait_in && ( del_write_complete || del_read_complete ) ; + +// next last output generation +assign next_last_out = del_write_req || del_read_req && ( ~del_burst_in || read_bound ) || posted_write_req && ( write_next_last ) ; +/*================================================================================================================== +Error recovery FF gets a value of one, when during posted write error occurs. It is cleared when all the data provided +for erroneous transaction is pulled out of WBW_FIFO +==================================================================================================================*/ + +// error recovery flip flop input - used when posted write is terminated with an error +always@( + err_recovery or + last_out or + wlast or + err_signal_out or + intermediate_last +) +begin + // when error recovery is not set - drive its input so it gets set + if ( ~err_recovery ) + err_recovery_in = ~last_out && ~intermediate_last && err_signal_out ; + else + // when error recovery is set, wbw_fifo is enabled - clear err_recovery when last data entry of erroneous transaction is pulled out of fifo + err_recovery_in = ~wlast ; +end + +wire data_out_load = (posted_write_req || del_write_req) && ( !rdy_out || ( !wait_in && rtransfer_in ) ) ; + +wire be_out_load = (req_out && !rdy_out) || ( posted_write_req && !wait_in && rtransfer_in ) ; + +wire last_load = req_out && ( ~rdy_out || ~wait_in && wtransfer_in ) ; + +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + data_out <= #`FF_DELAY 32'h0000_0000 ; + else + if ( data_out_load ) + data_out <= #`FF_DELAY intermediate_data ; +end + +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + be_out <= #`FF_DELAY 4'hF ; + else + if ( be_out_load ) + be_out <= #`FF_DELAY posted_write_req ? intermediate_be : source_be ; +end + +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + current_last <= #`FF_DELAY 1'b0 ; + else + if ( last_load ) + current_last <= #`FF_DELAY next_last_out ; +end + +assign last_out = current_last ; +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_out_reg.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_out_reg.v new file mode 100644 index 000000000..81a5ff200 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_out_reg.v @@ -0,0 +1,124 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "out_reg.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_out_reg.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// module inferes a single IOB output block as known in FPGA architectures +// It provides data flip flop with clock enable and output enable flip flop with clock enable +// This is tested in Xilinx FPGA - active low output enable +// Check polarity of output enable flip flop for specific architecure. +module pci_out_reg +( + reset_in, + clk_in, + dat_en_in, + en_en_in, + dat_in, + en_in, + en_out, + dat_out +); + +input reset_in, + clk_in, + dat_en_in, + en_en_in, + dat_in, + en_in ; + +output dat_out ; +output en_out ; + +reg dat_out, + en_out ; + +`ifdef ACTIVE_LOW_OE +wire en = ~en_in ; +`else +`ifdef ACTIVE_HIGH_OE +wire en = en_in ; +`endif +`endif + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + dat_out <= #`FF_DELAY 1'b0 ; + else if ( dat_en_in ) + dat_out <= #`FF_DELAY dat_in ; +end + +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + `ifdef ACTIVE_LOW_OE + en_out <= #`FF_DELAY 1'b1 ; + `else + `ifdef ACTIVE_HIGH_OE + en_out <= #`FF_DELAY 1'b0 ; + `endif + `endif + else if ( en_en_in ) + en_out <= #`FF_DELAY en ; +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_par_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_par_crit.v new file mode 100644 index 000000000..c55966c28 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_par_crit.v @@ -0,0 +1,90 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "par_crit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_par_crit.v,v $ +// Revision 1.2 2003/02/13 18:26:33 mihad +// Cleaned up the code. No functional changes. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// this one is used in parity generator/checker for calculating parity signal + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_par_crit +( + par_out, + par_out_in, + pci_cbe_en_in, + data_par_in, + pci_cbe_in +) ; + +output par_out ; + +input par_out_in, + pci_cbe_en_in, + data_par_in ; + +input [3:0] pci_cbe_in ; + +assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^ pci_cbe_in[2] ^ pci_cbe_in[1] ^ pci_cbe_in[0] ^ data_par_in) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_parity_check.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_parity_check.v new file mode 100644 index 000000000..529c3f311 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_parity_check.v @@ -0,0 +1,336 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_parity_check.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_parity_check.v,v $ +// Revision 1.6 2003/02/13 18:26:33 mihad +// Cleaned up the code. No functional changes. +// +// Revision 1.5 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.4 2002/08/13 11:03:53 mihad +// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" +`include "bus_commands.v" + +module pci_parity_check +( + reset_in, + clk_in, + pci_par_in, + pci_par_out, + pci_par_en_out, + pci_perr_in, + pci_perr_out, + pci_perr_out_in, + pci_perr_en_out, + pci_serr_en_in, + pci_serr_out, + pci_serr_out_in, + pci_serr_en_out, + pci_frame_reg_in, + pci_frame_en_in, + pci_irdy_en_in, + pci_irdy_reg_in, + pci_trdy_reg_in, + pci_trdy_en_in, + pci_par_en_in, + pci_ad_out_in, + pci_ad_reg_in, + pci_cbe_in_in, + pci_cbe_reg_in, + pci_cbe_out_in, + pci_cbe_en_in, + pci_ad_en_in, + par_err_response_in, + par_err_detect_out, + perr_mas_detect_out, + + serr_enable_in, + sig_serr_out + +); + +// system inputs +input reset_in ; +input clk_in ; + +// pci signals that are monitored or generated by parity error checker +input pci_par_in ; // pci PAR input +output pci_par_out ; // pci_PAR output +output pci_par_en_out ; // pci PAR enable output +input pci_perr_in ; // PERR# input +output pci_perr_out ; // PERR# output +output pci_perr_en_out ; // PERR# buffer enable output +input pci_serr_en_in ; // SERR enable input +output pci_serr_out ; // SERR# output +input pci_serr_out_in ; // SERR# output value input +input pci_perr_out_in ; // PERR# output value input +output pci_serr_en_out ; // SERR# buffer enable output +input pci_frame_reg_in ; // frame from pci bus input +input pci_frame_en_in ; // frame enable driven by master state machine +input pci_irdy_en_in ; // irdy enable input from PCI master +input pci_irdy_reg_in ; // irdy from PCI bus +input pci_trdy_reg_in ; // target ready from PCI bus +input pci_trdy_en_in ; // target ready output enable +input pci_par_en_in ; // par enable input +input [31:0] pci_ad_out_in ; // data driven by bridge to PCI +input [31:0] pci_ad_reg_in ; // data driven by other agents on PCI +input [3:0] pci_cbe_in_in ; // cbe driven by outside agents +input [3:0] pci_cbe_reg_in ; // registered cbe driven by outside agents +input [3:0] pci_cbe_out_in ; // cbe driven by pci master state machine +input pci_ad_en_in ; // ad enable input +input par_err_response_in ; // parity error response bit from conf.space +output par_err_detect_out ; // parity error detected signal out +output perr_mas_detect_out ; // master asserted PERR or sampled PERR asserted +input serr_enable_in ; // system error enable bit from conf.space +output sig_serr_out ; // signalled system error output for configuration space +input pci_cbe_en_in ; + +// FFs for frame input - used for determining whether PAR is sampled for address phase or for data phase +reg frame_dec2 ; +reg check_perr ; + +/*======================================================================================================================= +CBE lines' parity is needed for overall parity calculation +=======================================================================================================================*/ +wire par_cbe_out = pci_cbe_out_in[3] ^ pci_cbe_out_in[2] ^ pci_cbe_out_in[1] ^ pci_cbe_out_in[0] ; +wire par_cbe_in = pci_cbe_reg_in[3] ^ pci_cbe_reg_in[2] ^ pci_cbe_reg_in[1] ^ pci_cbe_reg_in[0] ; + +/*======================================================================================================================= +Parity generator - parity is generated and assigned to output on every clock edge. PAR output enable is active +one clock cycle after data output enable. Depending on whether master is performing access or target is responding, +apropriate cbe data is included in parity generation. Non - registered CBE is used during reads through target SM +=======================================================================================================================*/ + +// generate appropriate par signal +wire data_par = (pci_ad_out_in[31] ^ pci_ad_out_in[30] ^ pci_ad_out_in[29] ^ pci_ad_out_in[28]) ^ + (pci_ad_out_in[27] ^ pci_ad_out_in[26] ^ pci_ad_out_in[25] ^ pci_ad_out_in[24]) ^ + (pci_ad_out_in[23] ^ pci_ad_out_in[22] ^ pci_ad_out_in[21] ^ pci_ad_out_in[20]) ^ + (pci_ad_out_in[19] ^ pci_ad_out_in[18] ^ pci_ad_out_in[17] ^ pci_ad_out_in[16]) ^ + (pci_ad_out_in[15] ^ pci_ad_out_in[14] ^ pci_ad_out_in[13] ^ pci_ad_out_in[12]) ^ + (pci_ad_out_in[11] ^ pci_ad_out_in[10] ^ pci_ad_out_in[9] ^ pci_ad_out_in[8]) ^ + (pci_ad_out_in[7] ^ pci_ad_out_in[6] ^ pci_ad_out_in[5] ^ pci_ad_out_in[4]) ^ + (pci_ad_out_in[3] ^ pci_ad_out_in[2] ^ pci_ad_out_in[1] ^ pci_ad_out_in[0]) ; + +wire par_out_only = data_par ^ par_cbe_out ; + +pci_par_crit par_gen +( + .par_out (pci_par_out), + .par_out_in (par_out_only), + .pci_cbe_en_in (pci_cbe_en_in), + .data_par_in (data_par), + .pci_cbe_in (pci_cbe_in_in) +) ; + +// PAR enable = ad output enable delayed by one clock +assign pci_par_en_out = pci_ad_en_in ; + +/*======================================================================================================================= +Parity checker - parity is checked on every clock cycle. When parity error is detected, appropriate action is taken +to signal address parity errors on SERR if enabled and data parity errors on PERR# if enabled. Logic also drives +outputs to configuration space to set appropriate status bits if parity error is detected. PAR signal is checked on +master read operations or writes through pci target. Master read is performed when master drives irdy output and +doesn't drive ad lines. Writes through target are performed when target is driving trdy and doesn't drive ad lines. +=======================================================================================================================*/ + +// equation indicating whether to check and generate or not PERR# signal on next cycle +wire perr_generate = ~pci_par_en_in && ~pci_ad_en_in // par was not generated on this cycle, so it should be checked + && ((pci_irdy_en_in && ~pci_trdy_reg_in) || // and master is driving irdy and target is signaling ready + (pci_trdy_en_in && ~pci_irdy_reg_in)) ; // or target is driving trdy and master is signaling ready + +wire data_in_par = (pci_ad_reg_in[31] ^ pci_ad_reg_in[30] ^ pci_ad_reg_in[29] ^ pci_ad_reg_in[28]) ^ + (pci_ad_reg_in[27] ^ pci_ad_reg_in[26] ^ pci_ad_reg_in[25] ^ pci_ad_reg_in[24]) ^ + (pci_ad_reg_in[23] ^ pci_ad_reg_in[22] ^ pci_ad_reg_in[21] ^ pci_ad_reg_in[20]) ^ + (pci_ad_reg_in[19] ^ pci_ad_reg_in[18] ^ pci_ad_reg_in[17] ^ pci_ad_reg_in[16]) ^ + (pci_ad_reg_in[15] ^ pci_ad_reg_in[14] ^ pci_ad_reg_in[13] ^ pci_ad_reg_in[12]) ^ + (pci_ad_reg_in[11] ^ pci_ad_reg_in[10] ^ pci_ad_reg_in[9] ^ pci_ad_reg_in[8]) ^ + (pci_ad_reg_in[7] ^ pci_ad_reg_in[6] ^ pci_ad_reg_in[5] ^ pci_ad_reg_in[4]) ^ + (pci_ad_reg_in[3] ^ pci_ad_reg_in[2] ^ pci_ad_reg_in[1] ^ pci_ad_reg_in[0]) ; + +//wire perr = (cbe_par_reg ^ pci_par_in ^ data_in_par) ; +wire perr ; +wire perr_n ; +wire perr_en ; + +assign pci_perr_out = perr_n ; + +// parity error output assignment +//assign pci_perr_out = ~(perr && perr_generate) ; + +wire non_critical_par = par_cbe_in ^ data_in_par ; + +pci_perr_crit perr_crit_gen +( + .perr_out (perr), + .perr_n_out (perr_n), + .non_critical_par_in(non_critical_par), + .pci_par_in (pci_par_in), + .perr_generate_in (perr_generate) +) ; + +// PERR# enable +wire pci_perr_en_reg ; +pci_perr_en_crit perr_en_crit_gen +( + .reset_in (reset_in), + .clk_in (clk_in), + .perr_en_out (pci_perr_en_out), + .perr_en_reg_out (pci_perr_en_reg), + .non_critical_par_in (non_critical_par), + .pci_par_in (pci_par_in), + .perr_generate_in (perr_generate), + .par_err_response_in (par_err_response_in) +) ; + +// address phase decoding +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + frame_dec2 <= #`FF_DELAY 1'b0 ; + else + frame_dec2 <= #`FF_DELAY pci_frame_reg_in ; +end + +// address phase parity error checking - done after address phase is detected - which is - when bridge's master is not driving frame, +// frame was asserted on previous cycle and was not asserted two cycles before. +wire check_for_serr_on_first = ~pci_frame_reg_in && frame_dec2 && ~pci_frame_en_in ; + +reg check_for_serr_on_second ; +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + check_for_serr_on_second <= #`FF_DELAY 1'b0 ; + else + check_for_serr_on_second <= #`FF_DELAY check_for_serr_on_first && ( pci_cbe_reg_in == `BC_DUAL_ADDR_CYC ) ; +end + +wire check_for_serr = check_for_serr_on_first || check_for_serr_on_second ; + +wire serr_generate = check_for_serr && serr_enable_in && par_err_response_in ; + +pci_serr_en_crit serr_en_crit_gen +( + .serr_en_out (pci_serr_en_out), + .pci_par_in (pci_par_in), + .non_critical_par_in(non_critical_par), + .serr_generate_in (serr_generate) +); + + +// serr is enabled only for reporting errors - route this signal to configuration space +assign sig_serr_out = pci_serr_en_in ; + +// SERR# output is always 0, just enable is driven apropriately +pci_serr_crit serr_crit_gen +( + .serr_out (pci_serr_out), + .non_critical_par_in (non_critical_par), + .pci_par_in (pci_par_in), + .serr_check_in (check_for_serr) +); + +/*======================================================================================================================================= + Synchronizing mechanism detecting what is supposed to be done - PERR# generation or PERR# checking +=======================================================================================================================================*/ +// perr should be checked one clock after PAR is generated +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + check_perr <= #`FF_DELAY 1'b0 ; + else + check_perr <= #`FF_DELAY pci_par_en_in ; +end + +wire perr_sampled_in = ~pci_perr_in && check_perr ; +reg perr_sampled ; +always@(posedge reset_in or posedge clk_in) +begin + if (reset_in) + perr_sampled <= #`FF_DELAY 1'b0 ; + else + perr_sampled <= #`FF_DELAY perr_sampled_in ; +end + +// assign output for parity error detected bit +assign par_err_detect_out = ~pci_serr_out_in || ~pci_perr_out_in ;//|| perr_sampled ; MihaD - removed - detected parity error is set only during Master Reads or Target Writes + +// FF indicating that that last operation was done as bus master +reg frame_and_irdy_en_prev ; +reg frame_and_irdy_en_prev_prev ; +reg master_perr_report ; +always@(posedge reset_in or posedge clk_in) +begin + if ( reset_in ) + begin + master_perr_report <= #`FF_DELAY 1'b0 ; + frame_and_irdy_en_prev <= #`FF_DELAY 1'b0 ; + frame_and_irdy_en_prev_prev <= #`FF_DELAY 1'b0 ; + end + else + begin + master_perr_report <= #`FF_DELAY frame_and_irdy_en_prev_prev ; + frame_and_irdy_en_prev <= #`FF_DELAY pci_irdy_en_in && pci_frame_en_in ; + frame_and_irdy_en_prev_prev <= #`FF_DELAY frame_and_irdy_en_prev ; + end +end + +assign perr_mas_detect_out = master_perr_report && ( (par_err_response_in && perr_sampled) || pci_perr_en_reg ) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v new file mode 100644 index 000000000..b60573f5d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_decoder.v @@ -0,0 +1,201 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_decoder.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_pci_decoder.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_pci_decoder (hit, addr_out, + addr_in, bc_in, + base_addr, mask_addr, tran_addr, at_en, + mem_io_space, mem_en, io_en) ; + +// Decoding address size parameter - for FPGAs 1MegByte is recommended +// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!! +parameter decode_len = 12 ; + +//########################################################################################################### +// ALL COMMENTS are written as there were decode_len 20. This number and 12 (32 - 20) are assigning the +// numbers of decoded and compared bits, etc. +//########################################################################################################### + +/*----------------------------------------------------------------------------------------------------------- +DECODER interface decodes input address (ADDR_IN); what means that it validates (HIT), if input address +falls within the defined image space boundaries. Image space boundarie is defined with image base address +register (BASE_ADDR) and address mask register (MASK_ADDR). +Beside that, it also translates (maps) the input address to the output address (ADDR_OUT), regarding the +translation address register (TRAN_ADDR) and the address mask register. +-----------------------------------------------------------------------------------------------------------*/ + +// output control +output hit ; +// output address +output [31:0] addr_out ; +// input address and bus command +input [31:0] addr_in ; +input [3:0] bc_in ; + +// input registers - 12 LSbits are not valid since the smallest possible size is 4KB ! +input [31:(32-decode_len)] base_addr ; +input [31:(32-decode_len)] mask_addr ; +input [31:(32-decode_len)] tran_addr ; + +// input bit[2] of the Image Control register used to enable the address translation ! +input at_en ; + +// memory or io space selection and its enable signals ! +input mem_io_space ; +input mem_en ; +input io_en ; + +/*----------------------------------------------------------------------------------------------------------- +Internal signals ! +-----------------------------------------------------------------------------------------------------------*/ + +// bit[31] if address mask register is IMAGE ENABLE bit (img_en) +wire img_en ; + +// addr_in_compare are masked input address bits that are compared with masked base_addr +wire [31:(32-decode_len)] addr_in_compare ; +// base_addr_compare are masked base address bits that are compared with masked addr_in +wire [31:(32-decode_len)] base_addr_compare ; + +/*----------------------------------------------------------------------------------------------------------- +Decoding the input address! +This logic produces the loghest path in this module! + +20 MSbits of input addres are as well as base address (20 bits) masked with corrected address mask. Only +masked bits of each vector are actually logically compared. +Bit[31] of address mask register is used to enable the image space ! +Because of PCI bus specifications, there is also the comparison of memory/io selection (mem_io_space) and +its appropriate enable bit (mem_en / io_en). +-----------------------------------------------------------------------------------------------------------*/ + +assign addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ; + +assign base_addr_compare = (base_addr & mask_addr) ; + +assign img_en = mask_addr[31] ; + +wire addr_hit = (addr_in_compare == base_addr_compare) ; + +wire space_hit = (!mem_io_space && mem_en && img_en) || (mem_io_space && io_en && img_en) ; + +reg bc_hit ; +always@(bc_in or mem_io_space) +begin // Allowed bus commands for accesses through IMAGEs to WB bus - BC_CONF_WRITE/READ are not used with address claim!!! + case ( {bc_in[3:1], mem_io_space} ) + 4'b001_1, // BC_IO_READ or BC_IO_WRITE and IO space + 4'b011_0, // BC_MEM_READ or BC_MEM_WRITE and MEM space + 4'b110_0, // BC_MEM_READ_MUL and MEM space - BC_DUAL_ADDR_CYC must NOT be allowed! + 4'b111_0: // BC_MEM_READ_LN or BC_MEM_WRITE_INVAL and MEM space + bc_hit <= 1'b1 ; + default: + bc_hit <= 1'b0 ; + endcase +end + +wire bc_forbid = bc_in[3] && bc_in[2] && !bc_in[1] && bc_in[0] ; // BC_DUAL_ADDR_CYC must NOT be allowed! + + +assign hit = (addr_hit && space_hit && bc_hit && !bc_forbid) ; + +/*----------------------------------------------------------------------------------------------------------- +Translating the input address! + +Translation of input address is not implemented if ADDR_TRAN_IMPL is not defined + +20 MSbits of input address are masked with negated value of the corrected address mask in order to get +address bits of the input address which won't be replaced with translation address bits. +Translation address bits (20 bits) are masked with corrected address mask. Only masked bits of vector are +actually valid, all others are zero. +Boath vectors are bit-wise ORed in order to get the valid translation address with an offset of an input +address. +12 LSbits of an input address are assigned to 12 LSbits of an output addres. +-----------------------------------------------------------------------------------------------------------*/ + +`ifdef ADDR_TRAN_IMPL + // if Address Translation Enable bit is set, then translation address is used othervise input address is used! + // addr_in_combine input address bits are not replaced with translation address! + wire [31:(32-decode_len)] addr_in_combine ; + // tran_addr_combine are masked and combined with addr_in_combine! + reg [31:(32-decode_len)] tran_addr_combine ; + + assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ; + always@(at_en or tran_addr or mask_addr or addr_in) + begin + if (at_en) + begin + tran_addr_combine <= (tran_addr & mask_addr) ; + end + else + begin + tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ; + end + end + + assign addr_out[31:(32-decode_len)] = (addr_in_combine | tran_addr_combine) ; + assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ; +`else + assign addr_out = addr_in ; +`endif + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_tpram.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_tpram.v new file mode 100644 index 000000000..5bc4ca987 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_pci_tpram.v @@ -0,0 +1,464 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Two-Port Synchronous RAM //// +//// //// +//// This file is part of pci bridge project //// +//// http://www.opencores.org/cvsweb.shtml/pci/ //// +//// //// +//// Description //// +//// This block is a wrapper with common two-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// two-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Double-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB4_S16_S16 //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - xilinx rams need external tri-state logic //// +//// - add additional RAMs (Altera, VS etc) //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// - Miha Dolenc, mihad@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_pci_tpram.v,v $ +// Revision 1.4 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.3 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.2 2003/08/14 13:06:03 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.7 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.6 2002/10/17 22:51:08 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.5 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.4 2002/10/08 17:17:06 mihad +// Added BIST signals for RAMs. +// +// Revision 1.3 2002/09/30 17:22:27 mihad +// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! +// +// Revision 1.2 2002/08/19 16:51:36 mihad +// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" + +module pci_pci_tpram +( + // Generic synchronous two-port RAM interface + clk_a, + rst_a, + ce_a, + we_a, + oe_a, + addr_a, + di_a, + do_a, + clk_b, + rst_b, + ce_b, + we_b, + oe_b, + addr_b, + di_b, + do_b +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif +); + +// +// Default address and data buses width +// +parameter aw = 8; +parameter dw = 40; + +// +// Generic synchronous two-port RAM interface +// +input clk_a; // Clock +input rst_a; // Reset +input ce_a; // Chip enable input +input we_a; // Write enable input +input oe_a; // Output enable input +input [aw-1:0] addr_a; // address bus inputs +input [dw-1:0] di_a; // input data bus +output [dw-1:0] do_a; // output data bus +input clk_b; // Clock +input rst_b; // Reset +input ce_b; // Chip enable input +input we_b; // Write enable input +input oe_b; // Output enable input +input [aw-1:0] addr_b; // address bus inputs +input [dw-1:0] di_b; // input data bus +output [dw-1:0] do_b; // output data bus + +`ifdef PCI_BIST +// debug chain signals +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +// +// Internal wires and registers +// + +`ifdef PCI_VS_STP + `define PCI_PCI_RAM_SELECTED + `ifdef PCI_BIST + vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist + `else + vs_hdtp_64x40 i_vs_hdtp_64x40 + `endif + ( + .RCK (clk_b), + .WCK (clk_a), + .RADR (addr_b), + .WADR (addr_a), + .DI (di_a), + .DOUT (do_b), + .REN (1'b0), + .WEN (!we_a) + `ifdef PCI_BIST + , + // debug chain signals + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) + `endif + ); + + assign do_a = 0 ; +`endif + +`ifdef PCI_ARTISAN_SDP + `define PCI_PCI_RAM_SELECTED + // + // Instantiation of ASIC memory: + // + // Artisan Synchronous Double-Port RAM (ra2sh) + // + `ifdef PCI_BIST + art_hsdp_64x40_bist /*#(dw, 1<> 1)) + begin + start_sent = 1'b1 ; + sda_oe_en = 1'b1 ; + end + + // after half clock period of driving the sda low, the only possible + // transition is to send state. + // if send bit is not active, stop the procedure - undrive sda + if (clk_gen_cnt == period_cnt) + begin + clk_gen_cnt_clr = 1'b1 ; + if (send_bit) + begin + tx_rx_next_state = tx_rx_send_bits ; + end + else + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + tx_rx_next_state = tx_rx_idle ; + end + end + end + + tx_rx_send_bits: + begin + clk_gen_cnt_en = 1'b1 ; + + // generate high to low transition on the scl line immediately + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, load new value for sda oe, depending on the + // msb bit in the shift register + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = ~tx_shift_reg[7] ; + sda_oe_en = 1'b1 ; + bit_sent = 1'b1 ; + end + + // after clock low time, generate low to high transition on the scl line + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after clock high time, check what to do next + if (clk_gen_cnt == (period_cnt)) + begin + clk_gen_cnt_clr = 1'b1 ; + + if (~send_bit) + begin + // after transmiting all the bits, the only possible transition is to the state + // that checks the eprom acknowledge + if (rec_ack) + tx_rx_next_state = tx_rx_rec_ack ; + else + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + tx_rx_next_state = tx_rx_idle ; + end + end + end + end + + tx_rx_rec_bits: + begin + clk_gen_cnt_en = 1'b1 ; + sda_i_reg_en = 1'b1 ; + + // generate high to low transition on the scl line immediately + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, disable sda driver + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + end + + // after clock low time, generate low to high transition on the scl line + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock high time, report received bit + if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) ) + begin + bit_rec = 1'b1 ; + end + + // after clock period is finished, check the next operation + if (clk_gen_cnt == (period_cnt)) + begin + clk_gen_cnt_clr = 1'b1 ; + + if (~rec_bit) + begin + // when all bits are received, only nack or ack next states are possible + if (send_ack) + tx_rx_next_state = tx_rx_send_ack ; + else if (send_nack) + tx_rx_next_state = tx_rx_send_nack ; + else + begin + tx_rx_next_state = tx_rx_idle ; + end + end + end + end + + tx_rx_send_ack: + begin + clk_gen_cnt_en = 1'b1 ; + + // generate high to low transition on the scl line + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, enable the sda driver + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b1 ; + sda_oe_en = 1'b1 ; + ack_sent = 1'b1 ; + end + + // after clock low time, disable the scl driver - generate low to high transition on the scl line + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after clock period time expires, check what to do next + if (clk_gen_cnt == period_cnt) + begin + clk_gen_cnt_clr = 1'b1 ; + + // after the byte is acknowledged, the only possible next state is receive bits + // state + if (rec_bit) + tx_rx_next_state = tx_rx_rec_bits ; + else + begin + // this should never happen + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + + tx_rx_next_state = tx_rx_idle ; + end + end + end + + tx_rx_rec_ack: + begin + + clk_gen_cnt_en = 1'b1 ; + sda_i_reg_en = 1'b1 ; + + // generate high to low transition on the scl line + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, disable the sda driver + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + end + + // after clock low time, disable the scl driver - generate low to high transition on the scl line + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after 1/2 clock high time, report ack or nack condition, depending on the sda input state + if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) ) + begin + ack_rec = ~sda_i_reg ; + nack_rec = sda_i_reg ; + end + + // after clock period time expires, check what to do next + if (clk_gen_cnt == period_cnt) + begin + clk_gen_cnt_clr = 1'b1 ; + + if (send_bit) + tx_rx_next_state = tx_rx_send_bits ; + else if (rec_bit) + tx_rx_next_state = tx_rx_rec_bits ; + else if (send_stop) + tx_rx_next_state = tx_rx_stop ; + else if (send_start) + tx_rx_next_state = tx_rx_restart ; + else + begin + // this should never happen + tx_rx_next_state = tx_rx_idle ; + end + end + end + + tx_rx_send_nack: + begin + clk_gen_cnt_en = 1'b1 ; + + // generate high to low transition on the scl line + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, disable the sda driver + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + nack_sent = 1'b1 ; + end + + // after clock low time, disable the scl driver - generate low to high transition on the scl line + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after clock period time expires, check what to do next + if (clk_gen_cnt == period_cnt) + begin + clk_gen_cnt_clr = 1'b1 ; + + // after the no acknowledge is sent, the only possible next state is stop + // state + if (send_stop) + tx_rx_next_state = tx_rx_stop ; + else + begin + // this should never happen + tx_rx_next_state = tx_rx_idle ; + end + end + end + + tx_rx_restart: + begin + clk_gen_cnt_en = 1'b1 ; + + // generate high to low transition + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, release sda line + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + end + + // generate low to high transition + if (clk_gen_cnt == (period_cnt >> 1)) + begin + clk_gen_cnt_clr = 1'b1 ; + + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + + if (send_start) + tx_rx_next_state = tx_rx_start ; + else + tx_rx_next_state = tx_rx_idle ; + end + end + + tx_rx_stop: + begin + clk_gen_cnt_en = 1'b1 ; + + // generate high to low transition + if (clk_gen_cnt == 'h0) + begin + scl_oe = 1'b1 ; + scl_oe_en = 1'b1 ; + end + + // after half of clock low time, drive sda line low + if (clk_gen_cnt == (period_cnt >> 2)) + begin + sda_oe = 1'b1 ; + sda_oe_en = 1'b1 ; + end + + // generate low to high transition + if (clk_gen_cnt == (period_cnt >> 1)) + begin + scl_oe = 1'b0 ; + scl_oe_en = 1'b1 ; + end + + // after full clock period, release the sda line + if (clk_gen_cnt == period_cnt) + begin + sda_oe = 1'b0 ; + sda_oe_en = 1'b1 ; + stop_sent = 1'b1 ; + + tx_rx_next_state = tx_rx_idle ; + end + end + + endcase +end + +reg [rw_seq_state_width - 1:0] rw_seq_state ; + +reg doing_read , + doing_write , + doing_seq_read , + adr_set ; + +reg [ 3: 0] bits_transfered ; + +always@(posedge clk_i or posedge reset_i) +begin + if (reset_i) + begin + rw_seq_state <= rw_seq_idle ; + adr_set <= 1'b0 ; + doing_read <= 1'b0 ; + doing_write <= 1'b0 ; + doing_seq_read <= 1'b0 ; + dat_o <= 'h0 ; + tx_shift_reg <= 'h0 ; + send_start <= 'h0 ; + send_stop <= 'h0 ; + send_bit <= 'h0 ; + send_nack <= 'h0 ; + rec_ack <= 'h0 ; + no_ack_o <= 'h0 ; + bits_transfered <= 'h0 ; + write_done_o <= 'h0 ; + dat_rdy_o <= 'h0 ; + send_ack <= 'h0 ; + rec_bit <= 'h0 ; + end + else + begin + + case (rw_seq_state) + + rw_seq_idle: + begin + tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ; + adr_set <= 1'b0 ; + + if ( tx_rx_sm_idle & ~(doing_write | doing_read | doing_seq_read) ) + begin + if (do_write_i | do_rnd_read_i | do_seq_read_i) + begin + rw_seq_state <= rw_seq_tx_ctrl ; + send_start <= 1'b1 ; + end + + if (do_write_i) + doing_write <= 1'b1 ; + else if (do_rnd_read_i) + doing_read <= 1'b1 ; + else if (do_seq_read_i) + doing_seq_read <= 1'b1 ; + end + else + begin + doing_write <= 1'b0 ; + doing_read <= 1'b0 ; + doing_seq_read <= 1'b0 ; + end + end + + rw_seq_tx_ctrl: + begin + if (send_start) + begin + bits_transfered <= 'h0 ; + + if (start_sent) + begin + send_start <= 1'b0 ; + send_bit <= 1'b1 ; + end + end + else if (send_bit) + begin + if (bit_sent) + begin + bits_transfered <= bits_transfered + 1'b1 ; + tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ; + end + + if (bits_transfered == 'h8) + begin + send_bit <= 1'b0 ; + rec_ack <= 1'b1 ; + end + end + else if (rec_ack) + begin + bits_transfered <= 'h0 ; + + if (ack_rec | nack_rec) + rec_ack <= 1'b0 ; + + if (ack_rec) + begin + if (doing_write | ~adr_set) + begin + rw_seq_state <= rw_seq_tx_adr ; + tx_shift_reg <= adr_i[ 7: 0] ; + send_bit <= 1'b1 ; + end + else + begin + rw_seq_state <= rw_seq_rx_byte ; + rec_bit <= 1'b1 ; + end + end + else if (nack_rec) + begin + no_ack_o <= 1'b1 ; + send_stop <= 1'b1 ; + end + end + else if (send_stop) + begin + no_ack_o <= 1'b0 ; + + if (stop_sent) + begin + send_stop <= 1'b0 ; + rw_seq_state <= rw_seq_idle ; + end + end + end + + rw_seq_tx_adr: + begin + if (send_bit) + begin + if (bit_sent) + begin + bits_transfered <= bits_transfered + 1'b1 ; + tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ; + end + + if (bits_transfered == 'h8) + begin + send_bit <= 1'b0 ; + rec_ack <= 1'b1 ; + end + end + else if (rec_ack) + begin + bits_transfered <= 'h0 ; + + if (ack_rec | nack_rec) + rec_ack <= 1'b0 ; + + if (ack_rec) + begin + + adr_set <= 1'b1 ; + + if (doing_write) + begin + send_bit <= 1'b1 ; + rw_seq_state <= rw_seq_tx_byte ; + tx_shift_reg <= dat_i ; + end + else if (doing_read | doing_seq_read) + begin + send_start <= 1'b1 ; + rw_seq_state <= rw_seq_tx_ctrl ; + tx_shift_reg <= 8'b10100001 ; + end + end + else if (nack_rec) + begin + no_ack_o <= 1'b1 ; + send_stop <= 1'b1 ; + end + end + else if (send_stop) + begin + no_ack_o <= 1'b0 ; + + if (stop_sent) + begin + send_stop <= 1'b0 ; + rw_seq_state <= rw_seq_idle ; + end + end + end + + rw_seq_tx_byte: + begin + if (send_bit) + begin + if (bit_sent) + begin + bits_transfered <= bits_transfered + 1'b1 ; + tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ; + end + + if (bits_transfered == 'h8) + begin + send_bit <= 1'b0 ; + rec_ack <= 1'b1 ; + end + end + else if (rec_ack) + begin + bits_transfered <= 'h0 ; + + if (ack_rec | nack_rec) + begin + rec_ack <= 1'b0 ; + send_stop <= 1'b1 ; + end + + if (nack_rec) + no_ack_o <= 1'b1 ; + + if (ack_rec) + write_done_o <= 1'b1 ; + end + else if (send_stop) + begin + no_ack_o <= 1'b0 ; + write_done_o <= 1'b0 ; + + if (stop_sent) + begin + send_stop <= 1'b0 ; + rw_seq_state <= rw_seq_idle ; + end + end + end + + rw_seq_rx_byte: + begin + if (rec_bit) + begin + if (bit_rec) + begin + bits_transfered <= bits_transfered + 1'b1 ; + dat_o <= {dat_o[6:0], sda_i_reg} ; + end + + if (bits_transfered == 'h8) + begin + rec_bit <= 1'b0 ; + dat_rdy_o <= 1'b1 ; + if (doing_read) + send_nack <= 1'b1 ; + else + send_ack <= 1'b1 ; + end + end + else if (send_nack) + begin + dat_rdy_o <= 1'b0 ; + bits_transfered <= 'h0 ; + + if (nack_sent) + begin + send_stop <= 1'b1 ; + send_nack <= 1'b0 ; + end + end + else if (send_ack) + begin + dat_rdy_o <= 1'b0 ; + bits_transfered <= 'h0 ; + + if (~do_seq_read_i) + begin + send_ack <= 1'b0 ; + send_nack <= 1'b1 ; + end + else if (ack_sent) + begin + send_ack <= 1'b0 ; + rec_bit <= 1'b1 ; + end + end + else if (send_stop) + begin + if (stop_sent) + begin + send_stop <= 1'b0 ; + rw_seq_state <= rw_seq_idle ; + end + end + end + endcase + end +end + +endmodule // pci_spoci_ctrl \ No newline at end of file diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_sync_module.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_sync_module.v new file mode 100644 index 000000000..e3f1059f4 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_sync_module.v @@ -0,0 +1,167 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "sync_module.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_sync_module.v,v $ +// Revision 1.3 2003/08/14 13:06:03 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.2 2003/03/26 13:16:18 mihad +// Added the reset value parameter to the synchronizer flop module. +// Added resets to all synchronizer flop instances. +// Repaired initial sync value in fifos. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_sync_module +( + set_clk_in, + delete_clk_in, + reset_in, + delete_set_out, + block_set_out, + delete_in +); + +// system inputs from two clock domains +input set_clk_in; +input delete_clk_in; +input reset_in; +// control outputs +output delete_set_out; +output block_set_out; +// control input +input delete_in; + +// internal signals +reg del_bit; +wire meta_del_bit; +reg sync_del_bit; +reg delayed_del_bit; +wire meta_bckp_bit; +reg sync_bckp_bit; +reg delayed_bckp_bit; + + +// DELETE_IN input FF - when set must be active, until it is sinchronously cleared +always@(posedge delete_clk_in or posedge reset_in) +begin + if (reset_in) + del_bit <= 1'b0; + else + begin + if (!delayed_bckp_bit && sync_bckp_bit) + del_bit <= 1'b0; + else if (delete_in) + del_bit <= 1'b1; + end +end +assign block_set_out = del_bit; + +// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability +pci_synchronizer_flop #(1, 0) delete_sync +( + .data_in (del_bit), + .clk_out (set_clk_in), + .sync_data_out (meta_del_bit), + .async_reset (reset_in) +) ; + +// Final synchronization of del_bit signal to the set clock domain +always@(posedge set_clk_in or posedge reset_in) +begin + if (reset_in) + sync_del_bit <= 1'b0; + else + sync_del_bit <= meta_del_bit; +end + +// Delayed sync_del_bit signal for one clock period pulse generation +always@(posedge set_clk_in or posedge reset_in) +begin + if (reset_in) + delayed_del_bit <= 1'b0; + else + delayed_del_bit <= sync_del_bit; +end + +assign delete_set_out = !delayed_del_bit && sync_del_bit; + +// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability +pci_synchronizer_flop #(1, 0) clear_delete_sync +( + .data_in (sync_del_bit), + .clk_out (delete_clk_in), + .sync_data_out (meta_bckp_bit), + .async_reset (reset_in) +) ; + +// Final synchronization of sync_del_bit signal to the delete clock domain +always@(posedge delete_clk_in or posedge reset_in) +begin + if (reset_in) + sync_bckp_bit <= 1'b0; + else + sync_bckp_bit <= meta_bckp_bit; +end + +// Delayed sync_bckp_bit signal for one clock period pulse generation +always@(posedge delete_clk_in or posedge reset_in) +begin + if (reset_in) + delayed_bckp_bit <= 1'b0; + else + delayed_bckp_bit <= sync_bckp_bit; +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_synchronizer_flop.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_synchronizer_flop.v new file mode 100644 index 000000000..b1a05e06c --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_synchronizer_flop.v @@ -0,0 +1,103 @@ +//=========================================================================== +// $Id: pci_synchronizer_flop.v,v 1.1 2003/08/14 13:08:58 simons Exp $ +// +////////////////////////////////////////////////////////////////////// +//// //// +//// pci_synchronizer_flop //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// Make a rising-edge triggered flop with async reset with a //// +//// distinguished name so that it can be replaced with a flop //// +//// which does not make X's during simulation. //// +//// //// +//// This flop should be used instead of a regular flop for ALL //// +//// cross-clock-domain flops. Manually instantiating this //// +//// flop for all signals which must NEVER go to 1'bX during //// +//// simulation will make it possible for the user to //// +//// substitute a simulation model which does NOT have setup //// +//// and hold checks. //// +//// //// +//// If a target device library has a component which is //// +//// especially well suited to perform this function, it should //// +//// be instantiated by name in this file. Otherwise, the //// +//// behaviorial version of this module will be used. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - anynomous //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_synchronizer_flop.v,v $ +// Revision 1.1 2003/08/14 13:08:58 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// If the vendor has a flop which is particularly good at settling out of +// metastability, it should be used here. +module pci_synchronizer_flop ( + data_in, clk_out, sync_data_out, async_reset +); +parameter width = 1 ; +parameter reset_val = 0 ; + + input [width-1:0] data_in; + input clk_out; + output [width-1:0] sync_data_out; + input async_reset; + + reg [width-1:0] sync_data_out; + + always @(posedge clk_out or posedge async_reset) + begin + if (async_reset == 1'b1) + begin + sync_data_out <= reset_val; + end + else + begin +// In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ. +// This should NEVER go to 1'bX due to setup or hold violations. + sync_data_out <= data_in; + end + end +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_clk_en.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_clk_en.v new file mode 100644 index 000000000..eabcf7811 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_clk_en.v @@ -0,0 +1,104 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_clk_en.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_clk_en.v,v $ +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_clk_en +( + addr_phase, + config_access, + addr_claim_in, + pci_frame_in, + state_wait, + state_transfere, + state_default, + clk_enable +); + +input addr_phase ; // indicates registered address phase on PCI bus +input config_access ; // indicates configuration access +input addr_claim_in ; // indicates claimed input PCI address +input pci_frame_in ; // critical constrained input signal +input state_wait ; // indicates WAIT state of FSM +input state_transfere ; // indicates TRANSFERE state of FSM +input state_default ; // indicates DEFAULT state of FSM + +output clk_enable ; // FSM clock enable output + + +// clock enable signal when FSM is in IDLE state +wire s_idle_clk_en = ((addr_phase && config_access) || + (addr_phase && ~config_access && addr_claim_in)) ; + +// clock enable signal when FSM is in WAIT state or in DEFAULT state +wire s_wait_clk_en = (state_wait || state_default) ; + +// clock enable signal when FSM is in TRANSFERE state +wire s_tran_clk_en = (state_transfere && pci_frame_in) ; + + +// Clock enable signal for FSM with preserved hierarchy for minimum delay! +assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_devs_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_devs_crit.v new file mode 100644 index 000000000..c2d18fb7e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_devs_crit.v @@ -0,0 +1,89 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_devs_crit.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_devs_crit.v,v $ +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_devs_crit +( + devs_w, + devs_w_frm, + devs_w_frm_irdy, + pci_frame_in, + pci_irdy_in, + pci_devsel_out +); + +input devs_w ; // devsel signal (composed without critical signals) that do not need critical inputs +input devs_w_frm ; // devsel signal (composed without critical signals) that needs AND with critical FRAME input +input devs_w_frm_irdy ; // devsel signal (composed without critical signals) that needs AND with critical FRAME and + // IRDY inputs +input pci_frame_in ; // critical constrained input signal +input pci_irdy_in ; // critical constrained input signal + +output pci_devsel_out ; // PCI devsel output + +// PCI devsel output with preserved hierarchy for minimum delay! +assign pci_devsel_out = ~(devs_w || (devs_w_frm && ~pci_frame_in) || (devs_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_interface.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_interface.v new file mode 100644 index 000000000..a3ddbe1a3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_interface.v @@ -0,0 +1,962 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_interface.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_interface.v,v $ +// Revision 1.11 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.10 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.9 2003/08/21 20:55:14 tadejm +// Corrected bug when writing to FIFO (now it is registered). +// +// Revision 1.8 2003/08/08 16:36:33 tadejm +// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. +// +// Revision 1.7 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.6 2003/01/21 16:06:56 mihad +// Bug fixes, testcases added. +// +// Revision 1.5 2002/08/22 13:28:04 mihad +// Updated for synthesis purposes. Gate level simulation was failing in some configurations +// +// Revision 1.4 2002/02/19 16:32:37 mihad +// Modified testbench and fixed some bugs +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +`include "bus_commands.v" +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_interface +( + // system inputs + clk_in, + reset_in, + + // PCI Target side of INTERFACE + address_in, + addr_claim_out, + bc_in, + bc0_in, + data_in, + data_out, + be_in, + next_be_in, + req_in, + rdy_in, + addr_phase_in, + bckp_devsel_in, + bckp_trdy_in, + bckp_stop_in, + last_reg_in, + frame_reg_in, + fetch_pcir_fifo_in, + load_medium_reg_in, + sel_fifo_mreg_in, + sel_conf_fifo_in, + load_to_pciw_fifo_in, + load_to_conf_in, + same_read_out, + + norm_access_to_config_out, + read_completed_out, + read_processing_out, + target_abort_out, + disconect_wo_data_out, + disconect_w_data_out, + pciw_fifo_full_out, + pcir_fifo_data_err_out, + wbw_fifo_empty_out, + wbu_del_read_comp_pending_out, + + // Delayed synchronizacion module signals + req_out, + done_out, + in_progress_out, + req_req_pending_in, + req_comp_pending_in, + addr_out, + be_out, + we_out, + bc_out, + burst_ok_out, + strd_addr_in, + strd_bc_in, + status_in, + comp_flush_in, + + // FIFO signals + pcir_fifo_renable_out, + pcir_fifo_data_in, + pcir_fifo_be_in, + pcir_fifo_control_in, + pcir_fifo_flush_out, + pcir_fifo_almost_empty_in, + pcir_fifo_empty_in, + pciw_fifo_wenable_out, + pciw_fifo_addr_data_out, + pciw_fifo_cbe_out, + pciw_fifo_control_out, + pciw_fifo_three_left_in, + pciw_fifo_two_left_in, + pciw_fifo_almost_full_in, + pciw_fifo_full_in, + wbw_fifo_empty_in, + wbu_del_read_comp_pending_in, + + // Configuration space signals + conf_addr_out, + conf_data_out, + conf_data_in, + conf_be_out, + conf_we_out, + conf_re_out, + mem_enable_in, + io_enable_in, + mem_io_addr_space0_in, + mem_io_addr_space1_in, + mem_io_addr_space2_in, + mem_io_addr_space3_in, + mem_io_addr_space4_in, + mem_io_addr_space5_in, + pre_fetch_en0_in, + pre_fetch_en1_in, + pre_fetch_en2_in, + pre_fetch_en3_in, + pre_fetch_en4_in, + pre_fetch_en5_in, + pci_base_addr0_in, + pci_base_addr1_in, + pci_base_addr2_in, + pci_base_addr3_in, + pci_base_addr4_in, + pci_base_addr5_in, + pci_addr_mask0_in, + pci_addr_mask1_in, + pci_addr_mask2_in, + pci_addr_mask3_in, + pci_addr_mask4_in, + pci_addr_mask5_in, + pci_tran_addr0_in, + pci_tran_addr1_in, + pci_tran_addr2_in, + pci_tran_addr3_in, + pci_tran_addr4_in, + pci_tran_addr5_in, + addr_tran_en0_in, + addr_tran_en1_in, + addr_tran_en2_in, + addr_tran_en3_in, + addr_tran_en4_in, + addr_tran_en5_in +) ; + +`ifdef HOST + `ifdef NO_CNF_IMAGE + parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + `else + parameter pci_ba0_width = 20 ; + `endif +`endif + +`ifdef GUEST + parameter pci_ba0_width = 20 ; +`endif + +parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + +/*================================================================================================================== +System inputs. +==================================================================================================================*/ +// PCI side clock and reset +input clk_in, + reset_in ; + + +/*================================================================================================================== +Side of the PCI Target state machine +==================================================================================================================*/ +// Data, byte enables, bus commands and address ports +input [31:0] address_in ; // current request address input - registered +output addr_claim_out ; // current request address claim output +input [3:0] bc_in ; // current request bus command input - registered +input bc0_in ; // current cycle RW signal +output [31:0] data_out ; // for read operations - current dataphase data output +input [31:0] data_in ; // for write operations - current request data input - registered +input [3:0] be_in ; // current dataphase byte enable inputs - registered +input [3:0] next_be_in ; // next dataphase byte enable inputs - NOT registered +// Port connection control signals from PCI FSM +input req_in ; // Read is requested to WB master from PCI side +input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered +input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered +input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent +input bckp_trdy_in ; // TRDY input (which is registered) equivalent +input bckp_stop_in ; // STOP input (which is registered) equivalent +input last_reg_in ; // Indicates last data phase - registered +input frame_reg_in ; // FRAME input signal - registered +input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side +input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time) +input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register +input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO" +input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO +input load_to_conf_in ; // Write enable to Configuration space registers + + +/*================================================================================================================== +Status outputs to PCI side (FSM) +==================================================================================================================*/ +output same_read_out ; // Indicates the same read request (important when read is finished on WB side) +output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands +output read_completed_out ; // Indicates that read request is completed on WB side +output read_processing_out ; // Indicates that read request is processing on WB side +output target_abort_out ; // Indicates target abort termination +output disconect_wo_data_out ; // Indicates disconnect without data termination +output disconect_w_data_out ; // Indicates disconnect with data termination +output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full +output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO +output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus +output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending! + +/*================================================================================================================== +Read request interface through Delayed sinchronization module to WB Master +==================================================================================================================*/ +// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized +output req_out, // request qualifier - when 1 it indicates that valid data is provided on outputs + done_out, // done output - when 1 indicates that PCI Target has completed a cycle on its bus + in_progress_out ; // out progress indicator - indicates that current completion is in progress on + // PCI Target side +// pending indication inputs - PCI Target side must know about requests and completions +input req_req_pending_in ; // request pending input for PCI Target side +input req_comp_pending_in ; // completion pending input for PCI Target side - it indicates when completion + // is ready for completing on PCI Target bus +// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst +output [31:0] addr_out ; // address bus output +output [3:0] be_out ; // byte enable output +output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request +output [3:0] bc_out ; // bus command output +output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space + +// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion +input [31:0] strd_addr_in ; // Stored requested read access address +input [3:0] strd_bc_in ; // Stored requested read access bus command +input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status +input comp_flush_in ; // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data + + +/*================================================================================================================== +PCIR_PCIW_FIFO signals from pci side +==================================================================================================================*/ +// PCIR_FIFO control signals used for fetching data from PCIR_FIFO +output pcir_fifo_renable_out ; // read enable output to PCIR_FIFO +input [31:0] pcir_fifo_data_in ; // data input from PCIR_FIFO +input [3:0] pcir_fifo_be_in ; // byte enable input from PCIR_FIFO +input [3:0] pcir_fifo_control_in ; // control signals input from PCIR_FIFO +output pcir_fifo_flush_out ; // flush PCIR_FIFO +input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO +input pcir_fifo_empty_in ; // empty indicator + +// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring +output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO +wire pciw_fifo_wenable ; // not registered we +output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO +output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO +output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO +input pciw_fifo_three_left_in ; // three data spaces left in PCIW_FIFO +input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO +input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO +input pciw_fifo_full_in ; // full indicator from PCIW_FIFO + +// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO +input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO +input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit + + +/*================================================================================================================== +Configuration space signals - from and to registers +==================================================================================================================*/ +// BUS for reading and writing to configuration space registers +output [11:0] conf_addr_out ; // address to configuration space when there is access to it +output [31:0] conf_data_out ; // data to configuration space - for writing to registers +input [31:0] conf_data_in ; // data from configuration space - for reading from registers +output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space +output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing +output conf_re_out ; // read enable control signal - 1 for reading / 0 for nothing + +// Inputs for image control registers +input mem_enable_in ; // allowed access to memory mapped image +input io_enable_in ; // allowed access to io mapped image + +// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation +input mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register +input mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register +input mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register +input mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register +input mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register +input mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register +input pre_fetch_en0_in ; // bit-1 in pci_image_ctr0 register +input pre_fetch_en1_in ; // bit-1 in pci_image_ctr1 register +input pre_fetch_en2_in ; // bit-1 in pci_image_ctr2 register +input pre_fetch_en3_in ; // bit-1 in pci_image_ctr3 register +input pre_fetch_en4_in ; // bit-1 in pci_image_ctr4 register +input pre_fetch_en5_in ; // bit-1 in pci_image_ctr5 register + +// Input from image registers - register values needed for decoder to work properly +input [pci_ba0_width - 1:0] pci_base_addr0_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_base_addr1_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_base_addr2_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_base_addr3_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_base_addr4_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_base_addr5_in ; // base address from base address register +input [pci_ba1_5_width - 1:0] pci_addr_mask0_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_addr_mask1_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_addr_mask2_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_addr_mask3_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_addr_mask4_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_addr_mask5_in ; // masking of base address from address mask register +input [pci_ba1_5_width - 1:0] pci_tran_addr0_in ; // translation address from address translation register +input [pci_ba1_5_width - 1:0] pci_tran_addr1_in ; // translation address from address translation register +input [pci_ba1_5_width - 1:0] pci_tran_addr2_in ; // translation address from address translation register +input [pci_ba1_5_width - 1:0] pci_tran_addr3_in ; // translation address from address translation register +input [pci_ba1_5_width - 1:0] pci_tran_addr4_in ; // translation address from address translation register +input [pci_ba1_5_width - 1:0] pci_tran_addr5_in ; // translation address from address translation register + +input addr_tran_en0_in ; // address translation enable bit +input addr_tran_en1_in ; // address translation enable bit +input addr_tran_en2_in ; // address translation enable bit +input addr_tran_en3_in ; // address translation enable bit +input addr_tran_en4_in ; // address translation enable bit +input addr_tran_en5_in ; // address translation enable bit + +/*================================================================================================================== +END of input / output PORT DEFINITONS !!! +==================================================================================================================*/ + +// address output from address multiplexer +reg [31:0] address ; +// prefetch enable for access to selected image space +reg pre_fetch_en ; + +// Input addresses and image hits from address decoders - addresses are multiplexed to address +`ifdef HOST + `ifdef NO_CNF_IMAGE + `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space +wire hit0_in ; +wire [31:0] address0_in ; +wire pre_fetch_en0 = pre_fetch_en0_in ; + `else +wire hit0_in = 1'b0 ; +wire [31:0] address0_in = 32'h0 ; +wire pre_fetch_en0 = 1'b0 ; + `endif + `else +wire hit0_in ; +wire [31:0] address0_in ; +wire pre_fetch_en0 = pre_fetch_en0_in ; + `endif +`else // GUEST +wire hit0_in ; +wire [31:0] address0_in ; +wire pre_fetch_en0 = pre_fetch_en0_in ; +`endif + +wire hit1_in ; +wire [31:0] address1_in ; +wire pre_fetch_en1 = pre_fetch_en1_in ; + +`ifdef PCI_IMAGE2 +wire hit2_in ; +wire [31:0] address2_in ; +wire pre_fetch_en2 = pre_fetch_en2_in ; +`else +wire hit2_in = 1'b0 ; +wire [31:0] address2_in = 32'h0 ; +wire pre_fetch_en2 = 1'b0 ; +`endif + +`ifdef PCI_IMAGE3 +wire hit3_in ; +wire [31:0] address3_in ; +wire pre_fetch_en3 = pre_fetch_en3_in ; +`else +wire hit3_in = 1'b0 ; +wire [31:0] address3_in = 32'h0 ; +wire pre_fetch_en3 = 1'b0 ; +`endif + +`ifdef PCI_IMAGE4 +wire hit4_in ; +wire [31:0] address4_in ; +wire pre_fetch_en4 = pre_fetch_en4_in ; +`else +wire hit4_in = 1'b0 ; +wire [31:0] address4_in = 32'h0 ; +wire pre_fetch_en4 = 1'b0 ; +`endif + +`ifdef PCI_IMAGE5 +wire hit5_in ; +wire [31:0] address5_in ; +wire pre_fetch_en5 = pre_fetch_en5_in ; +`else +wire hit5_in = 1'b0 ; +wire [31:0] address5_in = 32'h0 ; +wire pre_fetch_en5 = 1'b0 ; +`endif + +// Include address decoders +`ifdef HOST + `ifdef NO_CNF_IMAGE + `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space + pci_pci_decoder #(pci_ba0_width) decoder0 + (.hit (hit0_in), + .addr_out (address0_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr0_in), + .mask_addr (pci_addr_mask0_in), + .tran_addr (pci_tran_addr0_in), + .at_en (addr_tran_en0_in), + .mem_io_space (mem_io_addr_space0_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; + `endif + `else + pci_pci_decoder #(pci_ba0_width) decoder0 + (.hit (hit0_in), + .addr_out (address0_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr0_in), + .mask_addr ({pci_ba0_width{1'b1}}), + .tran_addr ({pci_ba0_width{1'b0}}), + .at_en (1'b0), + .mem_io_space (1'b0), + .mem_en (mem_enable_in), + .io_en (1'b0) + ) ; + `endif +`else // GUEST + pci_pci_decoder #(pci_ba0_width) decoder0 + (.hit (hit0_in), + .addr_out (address0_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr0_in), + .mask_addr ({pci_ba0_width{1'b1}}), + .tran_addr ({pci_ba0_width{1'b0}}), + .at_en (1'b0), + .mem_io_space (1'b0), + .mem_en (mem_enable_in), + .io_en (1'b0) + ) ; +`endif + pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1 + (.hit (hit1_in), + .addr_out (address1_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr1_in), + .mask_addr (pci_addr_mask1_in), + .tran_addr (pci_tran_addr1_in), + .at_en (addr_tran_en1_in), + .mem_io_space (mem_io_addr_space1_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; +`ifdef PCI_IMAGE2 + pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2 + (.hit (hit2_in), + .addr_out (address2_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr2_in), + .mask_addr (pci_addr_mask2_in), + .tran_addr (pci_tran_addr2_in), + .at_en (addr_tran_en2_in), + .mem_io_space (mem_io_addr_space2_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; +`endif +`ifdef PCI_IMAGE3 + pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3 + (.hit (hit3_in), + .addr_out (address3_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr3_in), + .mask_addr (pci_addr_mask3_in), + .tran_addr (pci_tran_addr3_in), + .at_en (addr_tran_en3_in), + .mem_io_space (mem_io_addr_space3_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; +`endif +`ifdef PCI_IMAGE4 + pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4 + (.hit (hit4_in), + .addr_out (address4_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr4_in), + .mask_addr (pci_addr_mask4_in), + .tran_addr (pci_tran_addr4_in), + .at_en (addr_tran_en4_in), + .mem_io_space (mem_io_addr_space4_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; +`endif +`ifdef PCI_IMAGE5 + pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5 + (.hit (hit5_in), + .addr_out (address5_in), + .addr_in (address_in), + .bc_in (bc_in), + .base_addr (pci_base_addr5_in), + .mask_addr (pci_addr_mask5_in), + .tran_addr (pci_tran_addr5_in), + .at_en (addr_tran_en5_in), + .mem_io_space (mem_io_addr_space5_in), + .mem_en (mem_enable_in), + .io_en (io_enable_in) + ) ; +`endif + +// Internal signals for image hit determination +reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM + +// Determining if image 0 is assigned to configuration space or as normal pci to wb access! +// if normal access is allowed to configuration space, then hit0 is hit0_conf +`ifdef HOST + `ifdef NO_CNF_IMAGE + parameter hit0_conf = 1'b0 ; + `else + parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf + `endif +`else // GUEST + parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf +`endif + +// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not +always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or + address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or + pre_fetch_en5 or + pre_fetch_en4 or + pre_fetch_en3 or + pre_fetch_en2 or + pre_fetch_en1 or + pre_fetch_en0 + ) +begin + addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ; + case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in}) + 5'b10000 : + begin + address <= address5_in ; + pre_fetch_en <= pre_fetch_en5 ; + end + 5'b01000 : + begin + address <= address4_in ; + pre_fetch_en <= pre_fetch_en4 ; + end + 5'b00100 : + begin + address <= address3_in ; + pre_fetch_en <= pre_fetch_en3 ; + end + 5'b00010 : + begin + address <= address2_in ; + pre_fetch_en <= pre_fetch_en2 ; + end + 5'b00001 : + begin + address <= address0_in ; + pre_fetch_en <= pre_fetch_en0 ; + end + default : // IMAGE 1 is always included into PCI bridge + begin + address <= address1_in ; + pre_fetch_en <= pre_fetch_en1 ; + end + endcase +end + +// Address claim output to PCI Target SM +assign addr_claim_out = addr_claim ; + +reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB +reg norm_prf_en ; // stored pre-fetch enable +reg [3:0] norm_bc ; // stored bus-command +reg same_read_reg ; // stored SAME_READ information +reg target_rd ; // delayed registered TRDY output equivalent signal + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + norm_address <= #`FF_DELAY 32'h0000_0000 ; + norm_prf_en <= #`FF_DELAY 1'b0 ; + norm_bc <= #`FF_DELAY 4'h0 ; + same_read_reg <= #`FF_DELAY 1'b0 ; + end + else + begin + if (addr_phase_in) + begin + norm_address <= #`FF_DELAY address ; + norm_prf_en <= #`FF_DELAY pre_fetch_en ; + norm_bc <= #`FF_DELAY bc_in ; + same_read_reg <= #`FF_DELAY same_read_out ; + end + end +end + +`ifdef HOST + `ifdef NO_CNF_IMAGE + reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers + `else + reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers + `endif +`else + reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers +`endif +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + strd_address <= #`FF_DELAY 0 ; + end + else + begin + if (addr_phase_in) + begin +`ifdef HOST + `ifdef NO_CNF_IMAGE + strd_address <= #`FF_DELAY address_in[1:0] ; + `else + strd_address <= #`FF_DELAY address_in[11:0] ; + `endif +`else + strd_address <= #`FF_DELAY address_in[11:0] ; +`endif + end + end +end + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + target_rd <= #`FF_DELAY 1'b0 ; + end + else + begin + if (same_read_reg && !bckp_trdy_in) + target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus + else if (same_read_reg && bckp_devsel_in && !bckp_stop_in) + target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus + else if ((!same_read_reg) || (last_reg_in && target_rd)) + target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus + end +end +// '1' indicates asserted TRDY signal when same read operation is performed +wire target_rd_completed = target_rd ; + +reg same_read_request ; + +// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request +always@(address or strd_addr_in or bc_in or strd_bc_in) +begin + if ((address == strd_addr_in) & (bc_in == strd_bc_in)) + same_read_request <= 1'b1 ; + else + same_read_request <= 1'b0 ; +end + +assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ; + +// Signals for byte enable checking +reg addr_burst_ok ; +reg io_be_ok ; + +// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low! +always@(strd_address or be_in) +begin + case (strd_address[1:0]) + 2'b11 : + begin + addr_burst_ok <= 1'b0 ; + io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active + end + 2'b10 : + begin + addr_burst_ok <= 1'b0 ; + io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ; + end + 2'b01 : + begin + addr_burst_ok <= 1'b0 ; + io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ; + end + default : // 2'b00 + begin + addr_burst_ok <= 1'b1 ; + io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ; + end + endcase +end + +wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ; + +wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ; + +// Medium registers for data and control busses from PCIR_FIFO +reg [31:0] pcir_fifo_data_reg ; +reg [3:0] pcir_fifo_ctrl_reg ; + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ; + pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ; + end + else + begin + if (load_medium_reg_in) + begin + pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ; + pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ; + end + end +end + +// when disconnect is signalled, the next data written to fifo will be the last +// also when this happens, disconnect must stay asserted until last data is written to the fifo +reg keep_desconnect_wo_data_set ; + +// selecting "fifo data" from medium registers or from PCIR_FIFO +wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ; +wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ; + +// signal assignments to PCI Target FSM +assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge +assign read_processing_out = req_req_pending_in ; // request pending input for requesting side + // when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules + wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ; +assign disconect_wo_data_out = ( + ((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) && + ~bc0_in && ~frame_reg_in) || + ((pciw_fifo_full_in || pciw_fifo_almost_full_in || keep_desconnect_wo_data_set || pciw_fifo_two_left_in || + (pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) && + bc0_in && ~frame_reg_in) + ) ; +assign disconect_w_data_out = ( + ( burst_ok_out && !io_memory_bus_command && ~bc0_in ) || + ( addr_burst_ok && !io_memory_bus_command && bc0_in ) + ) ; +assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ; + +`ifdef HOST + `ifdef NO_CNF_IMAGE + // signal assignments to PCI Target FSM + assign norm_access_to_config_out = 1'b0 ; + // control signal assignments to read request sinchronization module + assign done_out = (target_rd_completed && last_reg_in) ; + assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ; + // signal used for PCIR_FIFO flush (with comp_flush_in signal) + wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ; + `else + // signal assignments to PCI Target FSM + assign norm_access_to_config_out = (hit0_in && hit0_conf) ; + // control signal assignments to read request sinchronization module + assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ; + assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ; + // signal used for PCIR_FIFO flush (with comp_flush_in signal) + wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ; + `endif +`else + // signal assignments to PCI Target FSM + assign norm_access_to_config_out = (hit0_in && hit0_conf) ; + // control signal assignments to read request sinchronization module + assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ; + assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ; + // signal used for PCIR_FIFO flush (with comp_flush_in signal) + wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ; +`endif + +// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers +wire pcir_fifo_flush_reg ; +pci_async_reset_flop async_reset_as_pcir_flush +( + .data_in (comp_flush_in || pcir_fifo_flush), + .clk_in (clk_in), + .async_reset_data_out (pcir_fifo_flush_reg), + .reset_in (reset_in) +) ; + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + keep_desconnect_wo_data_set <= #1 1'b0 ; + else if (keep_desconnect_wo_data_set && pciw_fifo_wenable) + keep_desconnect_wo_data_set <= #1 1'b0 ; + else if (pciw_fifo_wenable && disconect_wo_data_out) + keep_desconnect_wo_data_set <= #1 1'b1 ; +end + + +// signal assignments from fifo to PCI Target FSM +assign wbw_fifo_empty_out = wbw_fifo_empty_in ; +assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ; +assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || pciw_fifo_three_left_in) ; +assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ; +// signal assignments to PCIR FIFO fifo +assign pcir_fifo_flush_out = pcir_fifo_flush_reg ; +assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ; + +// signal assignments to PCIW FIFO +reg pciw_fifo_wenable_out; +assign pciw_fifo_wenable = load_to_pciw_fifo_in ; +reg [3:0] pciw_fifo_control_out; +reg [31:0] pciw_fifo_addr_data_out; +reg [3:0] pciw_fifo_cbe_out; +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + pciw_fifo_wenable_out <= #1 1'b0; + pciw_fifo_control_out <= #1 4'h0; + // data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits + pciw_fifo_addr_data_out <= #1 32'h0; + pciw_fifo_cbe_out <= #1 4'h0; + end + else + begin + pciw_fifo_wenable_out <= #1 load_to_pciw_fifo_in ; + pciw_fifo_control_out[`ADDR_CTRL_BIT] <= #1 ~rdy_in ; + pciw_fifo_control_out[`BURST_BIT] <= #1 rdy_in ? ~frame_reg_in : 1'b0 ; + // if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers + pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] <= #1 rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp. + pciw_fifo_control_out[`LAST_CTRL_BIT] <= #1 rdy_in && (frame_reg_in || (bckp_trdy_in && ~bckp_stop_in)); + // data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits + pciw_fifo_addr_data_out <= #1 rdy_in ? data_in : {norm_address[31:2], + norm_address[1] && io_memory_bus_command, + norm_address[0] && io_memory_bus_command} ; + pciw_fifo_cbe_out <= #1 rdy_in ? be_in : norm_bc ; + end +end + +`ifdef HOST + `ifdef NO_CNF_IMAGE + // data and address outputs assignments to PCI Target FSM + assign data_out = pcir_fifo_data ; + `else + // data and address outputs assignments to PCI Target FSM + assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ; + `endif +`else + // data and address outputs assignments to PCI Target FSM + assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ; +`endif + +// data and address outputs assignments to read request sinchronization module +assign req_out = req_in ; + // this address is stored in delayed_sync module and is connected back as strd_addr_in +assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved +assign be_out = be_in ; +assign we_out = 1'b0 ; +assign bc_out = norm_bc ; +// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR +// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) +assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ; +// data and address outputs assignments to Configuration space +`ifdef HOST + `ifdef NO_CNF_IMAGE + assign conf_data_out = 32'h0 ; + assign conf_addr_out = 12'h0 ; + assign conf_be_out = 4'b0 ; + assign conf_we_out = 1'h0 ; + `else + assign conf_data_out = data_in ; + assign conf_addr_out = strd_address[11:0] ; + assign conf_be_out = be_in ; + assign conf_we_out = load_to_conf_in ; + `endif +`else + assign conf_data_out = data_in ; + assign conf_addr_out = strd_address[11:0] ; + assign conf_be_out = be_in ; + assign conf_we_out = load_to_conf_in ; +`endif +// NOT USED NOW, SONCE READ IS ASYNCHRONOUS +//assign conf_re_out = fetch_conf_in ; +assign conf_re_out = 1'b0 ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_sm.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_sm.v new file mode 100644 index 000000000..5d7746bbb --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_sm.v @@ -0,0 +1,758 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_sm.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_sm.v,v $ +// Revision 1.11 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.10 2003/08/08 16:36:33 tadejm +// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. +// +// Revision 1.9 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.8 2003/01/21 16:06:56 mihad +// Bug fixes, testcases added. +// +// Revision 1.7 2002/09/24 19:09:17 mihad +// Number of state bits define was removed +// +// Revision 1.6 2002/09/24 18:30:00 mihad +// Changed state machine encoding to true one-hot +// +// Revision 1.5 2002/08/22 09:07:06 mihad +// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. +// +// Revision 1.4 2002/02/19 16:32:37 mihad +// Modified testbench and fixed some bugs +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_sm +( + // system inputs + clk_in, + reset_in, + // master inputs + pci_frame_in, + pci_irdy_in, + pci_idsel_in, + pci_frame_reg_in, + pci_irdy_reg_in, + pci_idsel_reg_in, + // target response outputs + pci_trdy_out, + pci_stop_out, + pci_devsel_out, + pci_trdy_en_out, + pci_stop_en_out, + pci_devsel_en_out, + ad_load_out, + ad_load_on_transfer_out, + // address, data, bus command, byte enable in/outs + pci_ad_reg_in, + pci_ad_out, + pci_ad_en_out, + pci_cbe_reg_in, + pci_cbe_in, + bckp_trdy_en_in, + bckp_devsel_in, + bckp_trdy_in, + bckp_stop_in, + pci_trdy_reg_in, + pci_stop_reg_in, + + // backend side of state machine with control signals to pci_io_mux ... + address_out, + addr_claim_in, + bc_out, + bc0_out, + data_out, + data_in, + be_out, + next_be_out, + req_out, + rdy_out, + addr_phase_out, + bckp_devsel_out, + bckp_trdy_out, + bckp_stop_out, + last_reg_out, + frame_reg_out, + fetch_pcir_fifo_out, + load_medium_reg_out, + sel_fifo_mreg_out, + sel_conf_fifo_out, + load_to_pciw_fifo_out, + load_to_conf_out, + same_read_in, + norm_access_to_config_in, + read_completed_in, + read_processing_in, + target_abort_in, + disconect_wo_data_in, + disconect_w_data_in, + target_abort_set_out, + pciw_fifo_full_in, + pcir_fifo_data_err_in, + wbw_fifo_empty_in, + wbu_del_read_comp_pending_in, + wbu_frame_en_in + +) ; + +/*---------------------------------------------------------------------------------------------------------------------- +Various parameters needed for state machine and other stuff +----------------------------------------------------------------------------------------------------------------------*/ +parameter S_IDLE = 3'b001 ; +parameter S_WAIT = 3'b010 ; +parameter S_TRANSFERE = 3'b100 ; + + +/*================================================================================================================== +System inputs. +==================================================================================================================*/ +// PCI side clock and reset +input clk_in, + reset_in ; + + +/*================================================================================================================== +PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation +module. Enables are separate signals. +==================================================================================================================*/ +// master inputs +input pci_frame_in, + pci_irdy_in, + pci_idsel_in ; +input pci_frame_reg_in, + pci_irdy_reg_in, + pci_idsel_reg_in ; + +// target response outputs +output pci_trdy_out, + pci_stop_out, + pci_devsel_out ; +output pci_trdy_en_out, + pci_stop_en_out, + pci_devsel_en_out ; +output ad_load_out ; +output ad_load_on_transfer_out ; +// address, data, bus command, byte enable in/outs +input [31:0] pci_ad_reg_in ; +output [31:0] pci_ad_out ; +output pci_ad_en_out ; +input [3:0] pci_cbe_reg_in ; +input [3:0] pci_cbe_in ; +input bckp_trdy_en_in ; +input bckp_devsel_in ; +input bckp_trdy_in ; +input bckp_stop_in ; +input pci_trdy_reg_in ; +input pci_stop_reg_in ; + + +/*================================================================================================================== +Other side of PCI Target state machine +==================================================================================================================*/ +// Data, byte enables, bus commands and address ports +output [31:0] address_out ; // current request address output - registered +input addr_claim_in ; // current request address claim input +output [3:0] bc_out ; // current request bus command output - registered +output bc0_out ; // current cycle RW signal output +input [31:0] data_in ; // for read operations - current dataphase data input +output [31:0] data_out ; // for write operations - current request data output - registered +output [3:0] be_out ; // current dataphase byte enable outputs - registered +output [3:0] next_be_out ; // next dataphase byte enable outputs - NOT registered +// Port connection control signals from PCI FSM +output req_out ; // Read is requested to WB master +output rdy_out ; // DATA / ADDRESS selection when read or write - registered +output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered +output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent +output bckp_trdy_out ; // TRDY output (which is registered) equivalent +output bckp_stop_out ; // STOP output (which is registered) equivalent +output last_reg_out ; // Indicates last data phase - registered +output frame_reg_out ; // FRAME output signal - registered +output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side +output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time) +output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register +output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO" +output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO +output load_to_conf_out ; // Write enable to Configuration space registers + + +/*================================================================================================================== +Status +==================================================================================================================*/ +input same_read_in ; // Indicates the same read request (important when read is finished on WB side) +input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands +input read_completed_in ; // Indicates that read request is completed on WB side +input read_processing_in ; // Indicates that read request is processing on WB side +input target_abort_in ; // Indicates target abort termination +input disconect_wo_data_in ; // Indicates disconnect without data termination +input disconect_w_data_in ; // Indicates disconnect with data termination +input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full +input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO +input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus +input wbu_del_read_comp_pending_in ; // Indicates that WB SAVE UNIT has a delayed read pending +input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if + // address on PCI bus is also claimed by decoder in this PCI TARGET UNIT +output target_abort_set_out ; // Signal used to be set in configuration space registers + +/*================================================================================================================== +END of input / output PORT DEFINITONS !!! +==================================================================================================================*/ + +// Delayed frame signal for determining the address phase +reg previous_frame ; +// Delayed read completed signal for preparing the data from pcir fifo +reg read_completed_reg ; +// Delayed disconnect with/without data for stop loading data to PCIW_FIFO +//reg disconect_wo_data_reg ; + +wire config_disconnect ; +wire disconect_wo_data = disconect_wo_data_in || config_disconnect ; +wire disconect_w_data = disconect_w_data_in ; +// Delayed frame signal for determining the address phase! +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + previous_frame <= #`FF_DELAY 1'b0 ; + read_completed_reg <= #`FF_DELAY 1'b0 ; + end + else + begin + previous_frame <= #`FF_DELAY pci_frame_reg_in ; + read_completed_reg <= #`FF_DELAY read_completed_in ; + end +end + +// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU) +wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ; + +`ifdef HOST + `ifdef NO_CNF_IMAGE + // Wire tells when there is configuration (read or write) command with IDSEL signal active + wire config_access = 1'b0 ; + // Write and read progresses are used for determining next state + wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) || + (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ; + wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ; + `else + // Wire tells when there is configuration (read or write) command with IDSEL signal active + wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x) + (pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle + + // Write and read progresses are used for determining next state + wire write_progress = ( (norm_access_to_config_in) || + (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) || + (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ; + wire read_progress = ( (~read_completed_in && norm_access_to_config_in) || + (read_completed_in && wbw_fifo_empty_in) ) ; + `endif +`else + // Wire tells when there is configuration (read or write) command with IDSEL signal active + wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x) + (pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle + + // Write and read progresses are used for determining next state + wire write_progress = ( (norm_access_to_config_in) || + (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) || + (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ; + wire read_progress = ( (~read_completed_in && norm_access_to_config_in) || + (read_completed_in && wbw_fifo_empty_in) ) ; +`endif + +// Signal for loading data to medium register from pcir fifo when read completed from WB side! +wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ; + +// Write allowed to PCIW_FIFO +wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) || + (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in)) ; +// Read allowed from PCIR_FIFO +wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ; +`ifdef HOST + `ifdef NO_CNF_IMAGE + // Read request is allowed to be proceed regarding the WB side + wire read_request = (~read_completed_in && ~read_processing_in) ; + `else + // Read request is allowed to be proceed regarding the WB side + wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ; + `endif +`else + // Read request is allowed to be proceed regarding the WB side + wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ; +`endif + +// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period +reg rw_cbe0 ; +reg wr_progress ; +reg rd_progress ; +reg rd_from_fifo ; +reg rd_request ; +reg wr_to_fifo ; +reg same_read_reg ; + +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + rw_cbe0 <= #`FF_DELAY 1'b0 ; + wr_progress <= #`FF_DELAY 1'b0 ; + rd_progress <= #`FF_DELAY 1'b0 ; + rd_from_fifo <= #`FF_DELAY 1'b0 ; + rd_request <= #`FF_DELAY 1'b0 ; + wr_to_fifo <= #`FF_DELAY 1'b0 ; + same_read_reg <= #`FF_DELAY 1'b0 ; + end + else + begin + if (addr_phase) + begin + rw_cbe0 <= #`FF_DELAY pci_cbe_reg_in[0] ; + wr_progress <= #`FF_DELAY write_progress ; + rd_progress <= #`FF_DELAY read_progress ; + rd_from_fifo <= #`FF_DELAY read_from_fifo ; + rd_request <= #`FF_DELAY read_request ; + wr_to_fifo <= #`FF_DELAY write_to_fifo ; + same_read_reg <= #`FF_DELAY same_read_in ; + end + end +end + +`ifdef HOST + `ifdef NO_CNF_IMAGE + wire norm_access_to_conf_reg = 1'b0 ; + wire cnf_progress = 1'b0 ; + `else + reg norm_access_to_conf_reg ; + reg cnf_progress ; + always@(posedge clk_in or posedge reset_in) + begin + if (reset_in) + begin + norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ; + cnf_progress <= #`FF_DELAY 1'b0 ; + end + else + begin + if (addr_phase) + begin + norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ; + cnf_progress <= #`FF_DELAY config_access ; + end + end + end + `endif +`else + reg norm_access_to_conf_reg ; + reg cnf_progress ; + always@(posedge clk_in or posedge reset_in) + begin + if (reset_in) + begin + norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ; + cnf_progress <= #`FF_DELAY 1'b0 ; + end + else + begin + if (addr_phase) + begin + norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ; + cnf_progress <= #`FF_DELAY config_access ; + end + end + end +`endif + +// Signal used in S_WAIT state to determin next state +wire s_wait_progress = ( + (~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) || + (~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && ~pcir_fifo_data_err_in) || + (~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) || + (cnf_progress && ~target_abort_in) + ) ; + +// Signal used in S_TRANSFERE state to determin next state +wire s_tran_progress = ( + (rw_cbe0 && !disconect_wo_data) || + (~rw_cbe0 && !disconect_wo_data && !target_abort_in && !pcir_fifo_data_err_in) + ) ; + +// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY +wire pcit_sm_clk_en ; +// FSM states signals indicating the current state +reg state_idle ; +reg state_wait ; +reg sm_transfere ; +reg backoff ; +reg state_default ; +wire state_backoff = sm_transfere && backoff ; +wire state_transfere = sm_transfere && !backoff ; + +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + backoff <= #`FF_DELAY 1'b0 ; + else if ( state_idle ) + backoff <= #`FF_DELAY 1'b0 ; + else + backoff <= #`FF_DELAY (state_wait && !s_wait_progress) || + (sm_transfere && !s_tran_progress && !pci_frame_in && !pci_irdy_in) || + backoff ; +end +assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ; + +// Clock enable module used for preserving the architecture because of minimum delay for critical inputs +pci_target32_clk_en pci_target_clock_en +( + .addr_phase (addr_phase), + .config_access (config_access), + .addr_claim_in (addr_claim_in), + .pci_frame_in (pci_frame_in), + .state_wait (state_wait), + .state_transfere (sm_transfere), + .state_default (state_default), + .clk_enable (pcit_sm_clk_en) +); + +reg [2:0] c_state ; //current state register +reg [2:0] n_state ; //next state input to current state register + +// state machine register control +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) // reset state machine to S_IDLE state + c_state <= #`FF_DELAY S_IDLE ; + else + if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state! + c_state <= #`FF_DELAY n_state ; +end + +// state machine logic +always@(c_state) +begin + case (c_state) + S_IDLE : + begin + state_idle <= 1'b1 ; + state_wait <= 1'b0 ; + sm_transfere <= 1'b0 ; + state_default <= 1'b0 ; + n_state <= S_WAIT ; + end + S_WAIT : + begin + state_idle <= 1'b0 ; + state_wait <= 1'b1 ; + sm_transfere <= 1'b0 ; + state_default <= 1'b0 ; + n_state <= S_TRANSFERE ; + end + S_TRANSFERE : + begin + state_idle <= 1'b0 ; + state_wait <= 1'b0 ; + sm_transfere <= 1'b1 ; + state_default <= 1'b0 ; + n_state <= S_IDLE ; + end + default : + begin + state_idle <= 1'b0 ; + state_wait <= 1'b0 ; + sm_transfere <= 1'b0 ; + state_default <= 1'b1 ; + n_state <= S_IDLE ; + end + endcase +end + + // if not retry and not target abort + // NO CRITICAL SIGNALS +wire trdy_w = ( + (state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) || + (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && !pcir_fifo_data_err_in) || + (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) || + (state_wait && cnf_progress && ~target_abort_in) + ) ; + // if not disconnect without data and not target abort (only during reads) + // MUST BE ANDED WITH CRITICAL ~FRAME +wire trdy_w_frm = ( + (state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) || + (state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) || + (state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && + ((~rw_cbe0 && ~pcir_fifo_data_err_in) || rw_cbe0)) + ) ; + // if not disconnect without data and not target abort (only during reads) + // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY +wire trdy_w_frm_irdy = ( ~bckp_trdy_in ) ; +// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs +pci_target32_trdy_crit pci_target_trdy_critical +( + .trdy_w (trdy_w), + .trdy_w_frm (trdy_w_frm), + .trdy_w_frm_irdy (trdy_w_frm_irdy), + .pci_frame_in (pci_frame_in), + .pci_irdy_in (pci_irdy_in), + .pci_trdy_out (pci_trdy_out) +); + + // if target abort or retry + // NO CRITICAL SIGNALS +wire stop_w = ( + (state_wait && target_abort_in) || + (state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) || + (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) || + (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) || + (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg) + ) ; + // if asserted, wait for deactivating the frame + // MUST BE ANDED WITH CRITICAL ~FRAME +wire stop_w_frm = ( + (state_backoff && ~bckp_stop_in) + ) ; + // if target abort or if disconnect without data (after data transfere) + // MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY +wire stop_w_frm_irdy = ( + (state_transfere && (disconect_wo_data)) || + (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in) + ) ; +// STOP critical module used for preserving the architecture because of minimum delay for critical inputs +pci_target32_stop_crit pci_target_stop_critical +( + .stop_w (stop_w), + .stop_w_frm (stop_w_frm), + .stop_w_frm_irdy (stop_w_frm_irdy), + .pci_frame_in (pci_frame_in), + .pci_irdy_in (pci_irdy_in), + .pci_stop_out (pci_stop_out) +); + + // if OK to respond and not target abort + // NO CRITICAL SIGNALS +wire devs_w = ( + (addr_phase && config_access) || + (addr_phase && ~config_access && addr_claim_in) || + (state_wait && ~target_abort_in && !(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) ) + ) ; + + // if not target abort (only during reads) or if asserted, wait for deactivating the frame + // MUST BE ANDED WITH CRITICAL ~FRAME +wire devs_w_frm = ( + (state_transfere && rw_cbe0) || + (state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) || + (state_backoff && ~bckp_devsel_in) + ) ; + // if not target abort (only during reads) + // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY +wire devs_w_frm_irdy = ( + (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in) + ) ; +// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs +pci_target32_devs_crit pci_target_devsel_critical +( + .devs_w (devs_w), + .devs_w_frm (devs_w_frm), + .devs_w_frm_irdy (devs_w_frm_irdy), + .pci_frame_in (pci_frame_in), + .pci_irdy_in (pci_irdy_in), + .pci_devsel_out (pci_devsel_out) +); + +// signal used in AD enable module with preserving the hierarchy because of minimum delay for critical inputs +assign pci_ad_en_out = ( + (addr_phase && config_access && ~pci_cbe_reg_in[0]) || + (addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) || + (state_wait && ~rw_cbe0) || + (state_transfere && ~rw_cbe0) || + (state_backoff && ~rw_cbe0 && ~pci_frame_reg_in) + ) ; + +wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ; + + // if cycle will progress or will not be stopped + // NO CRITICAL SIGNALS +wire ctrl_en = + /*(~wbu_frame_en_in && fast_back_to_back) ||*/ + (addr_phase && config_access) || + (addr_phase && ~config_access && addr_claim_in) || + (state_wait) || + (state_transfere && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) || + (state_backoff && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ; + +assign pci_trdy_en_out = ctrl_en ; +assign pci_stop_en_out = ctrl_en ; +assign pci_devsel_en_out = ctrl_en ; + +// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which +// data are registered in io mux module - from fifo or medoum register +reg bckp_trdy_reg ; +// delayed indicators for states transfere and backoff +reg state_transfere_reg ; +reg state_backoff_reg ; +always@(posedge clk_in or posedge reset_in) +begin + if (reset_in) + begin + bckp_trdy_reg <= #`FF_DELAY 1'b1 ; + state_transfere_reg <= #`FF_DELAY 1'b0 ; + state_backoff_reg <= #`FF_DELAY 1'b0 ; + end + else + begin + bckp_trdy_reg <= #`FF_DELAY bckp_trdy_in ; + state_transfere_reg <= #`FF_DELAY state_transfere ; + state_backoff_reg <= #`FF_DELAY state_backoff ; + end +end + +// Read control signals assignments +assign + fetch_pcir_fifo_out = ( + (prepare_rd_fifo_data) || + (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) || + (bckp_trdy_en_in && ~pci_trdy_reg_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in) + ) ; + +assign ad_load_out = (state_wait) ; + +assign ad_load_on_transfer_out = (bckp_trdy_en_in && ~rw_cbe0) ; + +assign load_medium_reg_out = ( + (prepare_rd_fifo_data) || + (state_wait && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~target_abort_in) || + (~pci_irdy_reg_in && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~pci_trdy_reg_in && bckp_trdy_en_in) + ) ; + +assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ; + +`ifdef HOST + `ifdef NO_CNF_IMAGE + assign sel_conf_fifo_out = 1'b0 ; + `else + assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ; + `endif +`else + assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ; +`endif + +// Write control signals assignments +assign + load_to_pciw_fifo_out = ( + (state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) || + (state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo /*&& ~disconect_wo_data_reg*/ && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) || + ((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) + ) ; + +`ifdef HOST + `ifdef NO_CNF_IMAGE + assign load_to_conf_out = 1'b0 ; + `else + assign load_to_conf_out = ( + (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) || + (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) + ) ; + `endif +`else + assign load_to_conf_out = ( + (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) || + (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) + ) ; +`endif + +// General control sigal assignments +assign addr_phase_out = addr_phase ; +assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ; +assign frame_reg_out = pci_frame_reg_in ; +assign bckp_devsel_out = bckp_devsel_in ; +assign bckp_trdy_out = bckp_trdy_in ; +assign bckp_stop_out = bckp_stop_in ; +assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in && bckp_trdy_en_in) ; +// request signal for delayed sinc. module +reg master_will_request_read ; +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + master_will_request_read <= #`FF_DELAY 1'b0 ; + else + master_will_request_read <= #`FF_DELAY ((state_wait && ~target_abort_in) || (state_backoff && ~target_abort_set_out)) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request ; +end +// MORE OPTIMIZED READS, but not easy to control in a testbench! +//assign req_out = master_will_request_read ; +assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ; + +// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS +assign rdy_out = ~bckp_trdy_reg ; + +// data and address outputs assignments! +assign pci_ad_out = data_in ; + +assign data_out = pci_ad_reg_in ; +assign be_out = pci_cbe_reg_in ; +assign next_be_out = pci_cbe_in ; +assign address_out = pci_ad_reg_in ; +assign bc_out = pci_cbe_reg_in ; +assign bc0_out = rw_cbe0 ; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_stop_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_stop_crit.v new file mode 100644 index 000000000..22ef867e2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_stop_crit.v @@ -0,0 +1,89 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_stop_crit.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_stop_crit.v,v $ +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_stop_crit +( + stop_w, + stop_w_frm, + stop_w_frm_irdy, + pci_frame_in, + pci_irdy_in, + pci_stop_out +); + +input stop_w ; // stop signal (composed without critical signals) that do not need critical inputs +input stop_w_frm ; // stop signal (composed without critical signals) that needs AND with critical FRAME input +input stop_w_frm_irdy ; // stop signal (composed without critical signals) that needs AND with critical FRAME and + // IRDY inputs +input pci_frame_in ; // critical constrained input signal +input pci_irdy_in ; // critical constrained input signal + +output pci_stop_out ; // PCI stop output + +// PCI stop output with preserved hierarchy for minimum delay! +assign pci_stop_out = ~(stop_w || (stop_w_frm && ~pci_frame_in) || (stop_w_frm_irdy && ~pci_frame_in && ~pci_irdy_in)) ; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_trdy_crit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_trdy_crit.v new file mode 100644 index 000000000..ab96c0357 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target32_trdy_crit.v @@ -0,0 +1,89 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target32_trdy_crit.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target32_trdy_crit.v,v $ +// Revision 1.4 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// module is used to separate logic which uses criticaly constrained inputs from slower logic. +// It is used to synthesize critical timing logic separately with faster cells or without optimization + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target32_trdy_crit +( + trdy_w, + trdy_w_frm, + trdy_w_frm_irdy, + pci_frame_in, + pci_irdy_in, + pci_trdy_out +); + +input trdy_w ; // trdy signal (composed without critical signals) that do not need critical inputs +input trdy_w_frm ; // trdy signal (composed without critical signals) that needs AND with critical FRAME input +input trdy_w_frm_irdy ; // trdy signal (composed without critical signals) that needs AND with critical FRAME and + // IRDY inputs +input pci_frame_in ; // critical constrained input signal +input pci_irdy_in ; // critical constrained input signal + +output pci_trdy_out ; // PCI trdy output + +// PCI trdy output with preserved hierarchy for minimum delay! +assign pci_trdy_out = ~(trdy_w || (trdy_w_frm && ~pci_frame_in) || (trdy_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ; + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target_unit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target_unit.v new file mode 100644 index 000000000..27cc6ef7c --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_target_unit.v @@ -0,0 +1,946 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: pci_target_unit.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_target_unit.v,v $ +// Revision 1.16 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.15 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.14 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.13 2003/08/21 20:55:14 tadejm +// Corrected bug when writing to FIFO (now it is registered). +// +// Revision 1.12 2003/08/08 16:36:33 tadejm +// Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. +// +// Revision 1.11 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.10 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.9 2002/10/17 22:51:08 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.8 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.7 2002/10/08 17:17:05 mihad +// Added BIST signals for RAMs. +// +// Revision 1.6 2002/09/25 15:53:52 mihad +// Removed all logic from asynchronous reset network +// +// Revision 1.5 2002/03/05 11:53:47 mihad +// Added some testcases, removed un-needed fifo signals +// +// Revision 1.4 2002/02/19 16:32:37 mihad +// Modified testbench and fixed some bugs +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// Module instantiates and connects other modules lower in hierarcy +// PCI target unit consists of modules that together form datapath +// between external WISHBONE slaves and external PCI initiators +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_target_unit +( + reset_in, + wb_clock_in, + pci_clock_in, + + pciu_wbm_adr_o, + pciu_wbm_dat_o, + pciu_wbm_dat_i, + pciu_wbm_cyc_o, + pciu_wbm_stb_o, + pciu_wbm_we_o, + pciu_wbm_cti_o, + pciu_wbm_bte_o, + pciu_wbm_sel_o, + pciu_wbm_ack_i, + pciu_wbm_rty_i, + pciu_wbm_err_i, + pciu_mem_enable_in, + pciu_io_enable_in, + pciu_map_in, + pciu_pref_en_in, + pciu_conf_data_in, + pciu_wbw_fifo_empty_in, + pciu_wbu_del_read_comp_pending_in, + pciu_wbu_frame_en_in, + pciu_bar0_in, + pciu_bar1_in, + pciu_bar2_in, + pciu_bar3_in, + pciu_bar4_in, + pciu_bar5_in, + pciu_am0_in, + pciu_am1_in, + pciu_am2_in, + pciu_am3_in, + pciu_am4_in, + pciu_am5_in, + pciu_ta0_in, + pciu_ta1_in, + pciu_ta2_in, + pciu_ta3_in, + pciu_ta4_in, + pciu_ta5_in, + pciu_at_en_in, + pciu_cache_line_size_in, + pciu_cache_lsize_not_zero_in, + pciu_pciif_frame_in, + pciu_pciif_irdy_in, + pciu_pciif_idsel_in, + pciu_pciif_frame_reg_in, + pciu_pciif_irdy_reg_in, + pciu_pciif_idsel_reg_in, + pciu_pciif_ad_reg_in, + pciu_pciif_cbe_reg_in, + pciu_pciif_cbe_in, + pciu_pciif_bckp_trdy_en_in, + pciu_pciif_bckp_devsel_in, + pciu_pciif_bckp_trdy_in, + pciu_pciif_bckp_stop_in, + pciu_pciif_trdy_reg_in, + pciu_pciif_stop_reg_in, + pciu_pciif_trdy_out, + pciu_pciif_stop_out, + pciu_pciif_devsel_out, + pciu_pciif_trdy_en_out, + pciu_pciif_stop_en_out, + pciu_pciif_devsel_en_out, + pciu_ad_load_out, + pciu_ad_load_on_transfer_out, + pciu_pciif_ad_out, + pciu_pciif_ad_en_out, + pciu_pciif_tabort_set_out, + pciu_err_addr_out, + pciu_err_bc_out, + pciu_err_data_out, + pciu_err_be_out, + pciu_err_signal_out, + pciu_err_source_out, + pciu_err_rty_exp_out, + pciu_conf_offset_out, + pciu_conf_renable_out, + pciu_conf_wenable_out, + pciu_conf_be_out, + pciu_conf_data_out, + pciu_pci_drcomp_pending_out, + pciu_pciw_fifo_empty_out + +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif +); + +`ifdef HOST + `ifdef NO_CNF_IMAGE + parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + `else + parameter pci_ba0_width = 20 ; + `endif +`endif + +`ifdef GUEST + parameter pci_ba0_width = 20 ; +`endif + +parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ; + +input reset_in, + wb_clock_in, + pci_clock_in ; + +output [31:0] pciu_wbm_adr_o ; +output [31:0] pciu_wbm_dat_o ; +input [31:0] pciu_wbm_dat_i ; +output pciu_wbm_cyc_o ; +output pciu_wbm_stb_o ; +output pciu_wbm_we_o ; +output [2:0] pciu_wbm_cti_o ; +output [1:0] pciu_wbm_bte_o ; +output [3:0] pciu_wbm_sel_o ; +input pciu_wbm_ack_i ; +input pciu_wbm_rty_i ; +input pciu_wbm_err_i ; + +input pciu_wbw_fifo_empty_in ; +input pciu_wbu_del_read_comp_pending_in ; +input pciu_wbu_frame_en_in ; + +input pciu_mem_enable_in ; +input pciu_io_enable_in ; +input [5:0] pciu_map_in ; +input [5:0] pciu_pref_en_in ; +input [31:0] pciu_conf_data_in ; + +input [pci_ba0_width - 1:0] pciu_bar0_in ; +input [pci_ba1_5_width - 1:0] pciu_bar1_in ; +input [pci_ba1_5_width - 1:0] pciu_bar2_in ; +input [pci_ba1_5_width - 1:0] pciu_bar3_in ; +input [pci_ba1_5_width - 1:0] pciu_bar4_in ; +input [pci_ba1_5_width - 1:0] pciu_bar5_in ; +input [pci_ba1_5_width - 1:0] pciu_am0_in ; +input [pci_ba1_5_width - 1:0] pciu_am1_in ; +input [pci_ba1_5_width - 1:0] pciu_am2_in ; +input [pci_ba1_5_width - 1:0] pciu_am3_in ; +input [pci_ba1_5_width - 1:0] pciu_am4_in ; +input [pci_ba1_5_width - 1:0] pciu_am5_in ; +input [pci_ba1_5_width - 1:0] pciu_ta0_in ; +input [pci_ba1_5_width - 1:0] pciu_ta1_in ; +input [pci_ba1_5_width - 1:0] pciu_ta2_in ; +input [pci_ba1_5_width - 1:0] pciu_ta3_in ; +input [pci_ba1_5_width - 1:0] pciu_ta4_in ; +input [pci_ba1_5_width - 1:0] pciu_ta5_in ; +input [5:0] pciu_at_en_in ; + +input [7:0] pciu_cache_line_size_in ; +input pciu_cache_lsize_not_zero_in ; + +input pciu_pciif_frame_in ; +input pciu_pciif_irdy_in ; +input pciu_pciif_idsel_in ; +input pciu_pciif_frame_reg_in ; +input pciu_pciif_irdy_reg_in ; +input pciu_pciif_idsel_reg_in ; +input [31:0] pciu_pciif_ad_reg_in ; +input [3:0] pciu_pciif_cbe_reg_in ; +input [3:0] pciu_pciif_cbe_in; +input pciu_pciif_bckp_trdy_en_in ; +input pciu_pciif_bckp_devsel_in ; +input pciu_pciif_bckp_trdy_in ; +input pciu_pciif_bckp_stop_in ; +input pciu_pciif_trdy_reg_in ; +input pciu_pciif_stop_reg_in ; + + +output pciu_pciif_trdy_out ; +output pciu_pciif_stop_out ; +output pciu_pciif_devsel_out ; +output pciu_pciif_trdy_en_out ; +output pciu_pciif_stop_en_out ; +output pciu_pciif_devsel_en_out ; +output pciu_ad_load_out ; +output pciu_ad_load_on_transfer_out ; +output [31:0] pciu_pciif_ad_out ; +output pciu_pciif_ad_en_out ; +output pciu_pciif_tabort_set_out ; + +output [31:0] pciu_err_addr_out ; +output [3:0] pciu_err_bc_out ; +output [31:0] pciu_err_data_out ; +output [3:0] pciu_err_be_out ; +output pciu_err_signal_out ; +output pciu_err_source_out ; +output pciu_err_rty_exp_out ; + +output [11:0] pciu_conf_offset_out ; +output pciu_conf_renable_out ; +output pciu_conf_wenable_out ; +output [3:0] pciu_conf_be_out ; +output [31:0] pciu_conf_data_out ; + +output pciu_pci_drcomp_pending_out ; +output pciu_pciw_fifo_empty_out ; + +`ifdef PCI_BIST +/*----------------------------------------------------- +BIST debug chain port signals +-----------------------------------------------------*/ +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + + +// pci target state machine and interface outputs +wire pcit_sm_trdy_out ; +wire pcit_sm_stop_out ; +wire pcit_sm_devsel_out ; +wire pcit_sm_trdy_en_out ; +wire pcit_sm_stop_en_out ; +wire pcit_sm_devsel_en_out ; +wire pcit_sm_ad_load_out ; +wire pcit_sm_ad_load_on_transfer_out ; +wire [31:0] pcit_sm_ad_out ; +wire pcit_sm_ad_en_out ; +wire [31:0] pcit_sm_address_out ; +wire [3:0] pcit_sm_bc_out ; +wire pcit_sm_bc0_out ; +wire [31:0] pcit_sm_data_out ; +wire [3:0] pcit_sm_be_out ; +wire [3:0] pcit_sm_next_be_out ; +wire pcit_sm_req_out ; +wire pcit_sm_rdy_out ; +wire pcit_sm_addr_phase_out ; +wire pcit_sm_bckp_devsel_out ; +wire pcit_sm_bckp_trdy_out ; +wire pcit_sm_bckp_stop_out ; +wire pcit_sm_last_reg_out ; +wire pcit_sm_frame_reg_out ; +wire pcit_sm_fetch_pcir_fifo_out ; +wire pcit_sm_load_medium_reg_out ; +wire pcit_sm_sel_fifo_mreg_out ; +wire pcit_sm_sel_conf_fifo_out ; +wire pcit_sm_load_to_pciw_fifo_out ; +wire pcit_sm_load_to_conf_out ; + +wire pcit_sm_target_abort_set_out ; // to conf space + +assign pciu_pciif_trdy_out = pcit_sm_trdy_out ; +assign pciu_pciif_stop_out = pcit_sm_stop_out ; +assign pciu_pciif_devsel_out = pcit_sm_devsel_out ; +assign pciu_pciif_trdy_en_out = pcit_sm_trdy_en_out ; +assign pciu_pciif_stop_en_out = pcit_sm_stop_en_out ; +assign pciu_pciif_devsel_en_out = pcit_sm_devsel_en_out ; +assign pciu_ad_load_out = pcit_sm_ad_load_out ; +assign pciu_ad_load_on_transfer_out = pcit_sm_ad_load_on_transfer_out ; +assign pciu_pciif_ad_out = pcit_sm_ad_out ; +assign pciu_pciif_ad_en_out = pcit_sm_ad_en_out ; +assign pciu_pciif_tabort_set_out = pcit_sm_target_abort_set_out ; + +wire pcit_if_addr_claim_out ; +wire [31:0] pcit_if_data_out ; +wire pcit_if_same_read_out ; +wire pcit_if_norm_access_to_config_out ; +wire pcit_if_read_completed_out ; +wire pcit_if_read_processing_out ; +wire pcit_if_target_abort_out ; +wire pcit_if_disconect_wo_data_out ; +wire pcit_if_disconect_w_data_out ; +wire pcit_if_pciw_fifo_full_out ; +wire pcit_if_pcir_fifo_data_err_out ; +wire pcit_if_wbw_fifo_empty_out ; +wire pcit_if_wbu_del_read_comp_pending_out ; +wire pcit_if_req_out ; +wire pcit_if_done_out ; +wire pcit_if_in_progress_out ; +wire [31:0] pcit_if_addr_out ; +wire [3:0] pcit_if_be_out ; +wire pcit_if_we_out ; +wire [3:0] pcit_if_bc_out ; +wire pcit_if_burst_ok_out ; +wire pcit_if_pcir_fifo_renable_out ; +wire pcit_if_pcir_fifo_flush_out ; +wire pcit_if_pciw_fifo_wenable_out ; +wire [31:0] pcit_if_pciw_fifo_addr_data_out ; +wire [3:0] pcit_if_pciw_fifo_cbe_out ; +wire [3:0] pcit_if_pciw_fifo_control_out ; +wire [11:0] pcit_if_conf_addr_out ; +wire [31:0] pcit_if_conf_data_out ; +wire [3:0] pcit_if_conf_be_out ; +wire pcit_if_conf_we_out ; +wire pcit_if_conf_re_out ; + +// pci target state machine outputs +// pci interface signals +assign pciu_conf_offset_out = pcit_if_conf_addr_out ; +assign pciu_conf_renable_out = pcit_if_conf_re_out ; +assign pciu_conf_wenable_out = pcit_if_conf_we_out ; +assign pciu_conf_be_out = pcit_if_conf_be_out ; +assign pciu_conf_data_out = pcit_if_conf_data_out ; + +// wishbone master state machine outputs +wire wbm_sm_wb_read_done ; +wire wbm_sm_write_attempt ; +wire wbm_sm_pcir_fifo_wenable_out ; +wire [31:0] wbm_sm_pcir_fifo_data_out ; +wire [3:0] wbm_sm_pcir_fifo_be_out ; +wire [3:0] wbm_sm_pcir_fifo_control_out ; +wire wbm_sm_pciw_fifo_renable_out ; +wire wbm_sm_pci_error_sig_out ; +wire [3:0] wbm_sm_pci_error_bc ; +wire wbm_sm_write_rty_cnt_exp_out ; +wire wbm_sm_error_source_out ; +wire wbm_sm_read_rty_cnt_exp_out ; +wire wbm_sm_cyc_out ; +wire wbm_sm_stb_out ; +wire wbm_sm_we_out ; +wire [2:0] wbm_sm_cti_out ; +wire [1:0] wbm_sm_bte_out ; +wire [3:0] wbm_sm_sel_out ; +wire [31:0] wbm_sm_adr_out ; +wire [31:0] wbm_sm_mdata_out ; + +assign pciu_err_addr_out = wbm_sm_adr_out ; +assign pciu_err_bc_out = wbm_sm_pci_error_bc ; +assign pciu_err_data_out = wbm_sm_mdata_out ; +assign pciu_err_be_out = ~wbm_sm_sel_out ; +assign pciu_err_signal_out = wbm_sm_pci_error_sig_out ; +assign pciu_err_source_out = wbm_sm_error_source_out ; +assign pciu_err_rty_exp_out = wbm_sm_write_rty_cnt_exp_out ; + +assign pciu_wbm_adr_o = wbm_sm_adr_out ; +assign pciu_wbm_dat_o = wbm_sm_mdata_out ; +assign pciu_wbm_cyc_o = wbm_sm_cyc_out ; +assign pciu_wbm_stb_o = wbm_sm_stb_out ; +assign pciu_wbm_we_o = wbm_sm_we_out ; +assign pciu_wbm_cti_o = wbm_sm_cti_out ; +assign pciu_wbm_bte_o = wbm_sm_bte_out ; +assign pciu_wbm_sel_o = wbm_sm_sel_out ; + +// pciw_pcir fifo outputs + +// pciw_fifo_outputs: +wire [31:0] fifos_pciw_addr_data_out ; +wire [3:0] fifos_pciw_cbe_out ; +wire [3:0] fifos_pciw_control_out ; +wire fifos_pciw_three_left_out ; +wire fifos_pciw_two_left_out ; +wire fifos_pciw_almost_full_out ; +wire fifos_pciw_full_out ; +wire fifos_pciw_almost_empty_out ; +wire fifos_pciw_empty_out ; +wire fifos_pciw_transaction_ready_out ; + +assign pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt; + +// pcir_fifo_outputs +wire [31:0] fifos_pcir_data_out ; +wire [3:0] fifos_pcir_be_out ; +wire [3:0] fifos_pcir_control_out ; +wire fifos_pcir_almost_empty_out ; +wire fifos_pcir_empty_out ; + +// delayed transaction logic outputs +wire [31:0] del_sync_addr_out ; +wire [3:0] del_sync_be_out ; +wire del_sync_we_out ; +wire del_sync_comp_req_pending_out ; +wire del_sync_comp_comp_pending_out ; +wire del_sync_req_req_pending_out ; +wire del_sync_req_comp_pending_out ; +wire [3:0] del_sync_bc_out ; +wire del_sync_status_out ; +wire del_sync_comp_flush_out ; +wire del_sync_burst_out ; + +assign pciu_pci_drcomp_pending_out = del_sync_comp_comp_pending_out ; + +// WISHBONE master interface inputs +wire wbm_sm_pci_tar_read_request = del_sync_comp_req_pending_out ; +wire [31:0] wbm_sm_pci_tar_address = del_sync_addr_out ; +wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ; +wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ; +wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ; +wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ; +wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ; +wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ; +wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ; +wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ; +wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ; +wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ; +wire wbm_sm_pciw_fifo_transaction_ready_in = fifos_pciw_transaction_ready_out ; +wire [31:0] wbm_sm_mdata_in = pciu_wbm_dat_i ; +wire wbm_sm_ack_in = pciu_wbm_ack_i ; +wire wbm_sm_rty_in = pciu_wbm_rty_i ; +wire wbm_sm_err_in = pciu_wbm_err_i ; + +// WISHBONE master interface instantiation +pci_wb_master wishbone_master +( + .wb_clock_in (wb_clock_in), + .reset_in (reset_in), + .pci_tar_read_request (wbm_sm_pci_tar_read_request), //in + .pci_tar_address (wbm_sm_pci_tar_address), //in + .pci_tar_cmd (wbm_sm_pci_tar_cmd), //in + .pci_tar_be (wbm_sm_pci_tar_be), //in + .pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in + .pci_cache_line_size (wbm_sm_pci_cache_line_size), //in + .cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in), + .wb_read_done_out (wbm_sm_wb_read_done), //out + .w_attempt (wbm_sm_write_attempt), //out + .pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out), + .pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out), + .pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out), + .pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out), + .pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out), + .pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in), + .pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in), + .pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in), + .pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in), + .pciw_fifo_empty_in (wbm_sm_pciw_fifo_empty_in), + .pciw_fifo_transaction_ready_in (wbm_sm_pciw_fifo_transaction_ready_in), + .pci_error_sig_out (wbm_sm_pci_error_sig_out), + .pci_error_bc (wbm_sm_pci_error_bc), + .write_rty_cnt_exp_out (wbm_sm_write_rty_cnt_exp_out), + .error_source_out (wbm_sm_error_source_out), + .read_rty_cnt_exp_out (wbm_sm_read_rty_cnt_exp_out), + .wb_cyc_o (wbm_sm_cyc_out), + .wb_stb_o (wbm_sm_stb_out), + .wb_we_o (wbm_sm_we_out), + .wb_cti_o (wbm_sm_cti_out), + .wb_bte_o (wbm_sm_bte_out), + .wb_sel_o (wbm_sm_sel_out), + .wb_adr_o (wbm_sm_adr_out), + .wb_dat_i (wbm_sm_mdata_in), + .wb_dat_o (wbm_sm_mdata_out), + .wb_ack_i (wbm_sm_ack_in), + .wb_rty_i (wbm_sm_rty_in), + .wb_err_i (wbm_sm_err_in) +); + +// pciw_pcir_fifos inputs +// PCIW_FIFO inputs +wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ; +wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ; +wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ; +wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ; +wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ; +//wire fifos_pciw_flush_in = 1'b0 ; // flush not used for write fifo + +// PCIR_FIFO inputs +wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ; +wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ; +wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ; +wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ; +wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ; +wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ; + +// PCIW_FIFO and PCIR_FIFO instantiation +pci_pciw_pcir_fifos fifos +( + .wb_clock_in (wb_clock_in), + .pci_clock_in (pci_clock_in), + .reset_in (reset_in), + .pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!! + .pciw_addr_data_in (fifos_pciw_addr_data_in), //for PCI Target !!! + .pciw_cbe_in (fifos_pciw_cbe_in), //for PCI Target !!! + .pciw_control_in (fifos_pciw_control_in), //for PCI Target !!! + .pciw_renable_in (fifos_pciw_renable_in), + .pciw_addr_data_out (fifos_pciw_addr_data_out), + .pciw_cbe_out (fifos_pciw_cbe_out), + .pciw_control_out (fifos_pciw_control_out), +// .pciw_flush_in (fifos_pciw_flush_in), // flush not used for write fifo + .pciw_three_left_out (fifos_pciw_three_left_out), //for PCI Target !!! + .pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!! + .pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!! + .pciw_full_out (fifos_pciw_full_out), //for PCI Target !!! + .pciw_almost_empty_out (fifos_pciw_almost_empty_out), + .pciw_empty_out (fifos_pciw_empty_out), + .pciw_transaction_ready_out (fifos_pciw_transaction_ready_out), + .pcir_wenable_in (fifos_pcir_wenable_in), + .pcir_data_in (fifos_pcir_data_in), + .pcir_be_in (fifos_pcir_be_in), + .pcir_control_in (fifos_pcir_control_in), + .pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!! + .pcir_data_out (fifos_pcir_data_out), //for PCI Target !!! + .pcir_be_out (fifos_pcir_be_out), //for PCI Target !!! + .pcir_control_out (fifos_pcir_control_out), //for PCI Target !!! + .pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!! + .pcir_full_out (), + .pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!! + .pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!! + .pcir_transaction_ready_out () + +`ifdef PCI_BIST + , + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +) ; + +// delayed transaction logic inputs +wire del_sync_req_in = pcit_if_req_out ; +wire del_sync_comp_in = wbm_sm_wb_read_done ; +wire del_sync_done_in = pcit_if_done_out ; +wire del_sync_in_progress_in = pcit_if_in_progress_out ; +wire [31:0] del_sync_addr_in = pcit_if_addr_out ; +wire [3:0] del_sync_be_in = pcit_if_be_out ; +wire del_sync_we_in = pcit_if_we_out ; +wire [3:0] del_sync_bc_in = pcit_if_bc_out ; +wire del_sync_status_in = 1'b0 ; +wire del_sync_burst_in = pcit_if_burst_ok_out ; +wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ; + +// delayed transaction logic instantiation +pci_delayed_sync del_sync +( + .reset_in (reset_in), + .req_clk_in (pci_clock_in), + .comp_clk_in (wb_clock_in), + .req_in (del_sync_req_in), + .comp_in (del_sync_comp_in), + .done_in (del_sync_done_in), + .in_progress_in (del_sync_in_progress_in), + .comp_req_pending_out (del_sync_comp_req_pending_out), + .comp_comp_pending_out (del_sync_comp_comp_pending_out), + .req_req_pending_out (del_sync_req_req_pending_out), + .req_comp_pending_out (del_sync_req_comp_pending_out), + .addr_in (del_sync_addr_in), + .be_in (del_sync_be_in), + .addr_out (del_sync_addr_out), + .be_out (del_sync_be_out), + .we_in (del_sync_we_in), + .we_out (del_sync_we_out), + .bc_in (del_sync_bc_in), + .bc_out (del_sync_bc_out), + .status_in (del_sync_status_in), + .status_out (del_sync_status_out), + .comp_flush_out (del_sync_comp_flush_out), + .burst_in (del_sync_burst_in), + .burst_out (del_sync_burst_out), + .retry_expired_in (del_sync_retry_expired_in) +); + +// pci target interface inputs +wire [31:0] pcit_if_address_in = pcit_sm_address_out ; +wire [3:0] pcit_if_bc_in = pcit_sm_bc_out ; +wire pcit_if_bc0_in = pcit_sm_bc0_out ; +wire [31:0] pcit_if_data_in = pcit_sm_data_out ; +wire [3:0] pcit_if_be_in = pcit_sm_be_out ; +wire [3:0] pcit_if_next_be_in = pcit_sm_next_be_out ; +wire pcit_if_req_in = pcit_sm_req_out ; +wire pcit_if_rdy_in = pcit_sm_rdy_out ; +wire pcit_if_addr_phase_in = pcit_sm_addr_phase_out ; +wire pcit_if_bckp_devsel_in = pcit_sm_bckp_devsel_out ; +wire pcit_if_bckp_trdy_in = pcit_sm_bckp_trdy_out ; +wire pcit_if_bckp_stop_in = pcit_sm_bckp_stop_out ; +wire pcit_if_last_reg_in = pcit_sm_last_reg_out ; +wire pcit_if_frame_reg_in = pcit_sm_frame_reg_out ; +wire pcit_if_fetch_pcir_fifo_in = pcit_sm_fetch_pcir_fifo_out ; +wire pcit_if_load_medium_reg_in = pcit_sm_load_medium_reg_out ; +wire pcit_if_sel_fifo_mreg_in = pcit_sm_sel_fifo_mreg_out ; +wire pcit_if_sel_conf_fifo_in = pcit_sm_sel_conf_fifo_out ; +wire pcit_if_load_to_pciw_fifo_in = pcit_sm_load_to_pciw_fifo_out ; +wire pcit_if_load_to_conf_in = pcit_sm_load_to_conf_out ; +wire pcit_if_req_req_pending_in = del_sync_req_req_pending_out ; +wire pcit_if_req_comp_pending_in = del_sync_req_comp_pending_out ; +wire pcit_if_status_in = del_sync_status_out ; +wire [31:0] pcit_if_strd_addr_in = del_sync_addr_out ; +wire [3:0] pcit_if_strd_bc_in = del_sync_bc_out ; +wire pcit_if_comp_flush_in = del_sync_comp_flush_out ; +wire [31:0] pcit_if_pcir_fifo_data_in = fifos_pcir_data_out ; +wire [3:0] pcit_if_pcir_fifo_be_in = fifos_pcir_be_out ; +wire [3:0] pcit_if_pcir_fifo_control_in = fifos_pcir_control_out ; +wire pcit_if_pcir_fifo_almost_empty_in = fifos_pcir_almost_empty_out ; +wire pcit_if_pcir_fifo_empty_in = fifos_pcir_empty_out ; +wire pcit_if_pciw_fifo_three_left_in = fifos_pciw_three_left_out ; +wire pcit_if_pciw_fifo_two_left_in = fifos_pciw_two_left_out ; +wire pcit_if_pciw_fifo_almost_full_in = fifos_pciw_almost_full_out ; +wire pcit_if_pciw_fifo_full_in = fifos_pciw_full_out ; +wire pcit_if_wbw_fifo_empty_in = pciu_wbw_fifo_empty_in ; +wire pcit_if_wbu_del_read_comp_pending_in = pciu_wbu_del_read_comp_pending_in ; +wire [31:0] pcit_if_conf_data_in = pciu_conf_data_in ; +wire pcit_if_mem_enable_in = pciu_mem_enable_in ; +wire pcit_if_io_enable_in = pciu_io_enable_in ; +wire pcit_if_mem_io_addr_space0_in = pciu_map_in[0] ; +wire pcit_if_mem_io_addr_space1_in = pciu_map_in[1] ; +wire pcit_if_mem_io_addr_space2_in = pciu_map_in[2] ; +wire pcit_if_mem_io_addr_space3_in = pciu_map_in[3] ; +wire pcit_if_mem_io_addr_space4_in = pciu_map_in[4] ; +wire pcit_if_mem_io_addr_space5_in = pciu_map_in[5] ; +wire pcit_if_pre_fetch_en0_in = pciu_pref_en_in[0] ; +wire pcit_if_pre_fetch_en1_in = pciu_pref_en_in[1] ; +wire pcit_if_pre_fetch_en2_in = pciu_pref_en_in[2] ; +wire pcit_if_pre_fetch_en3_in = pciu_pref_en_in[3] ; +wire pcit_if_pre_fetch_en4_in = pciu_pref_en_in[4] ; +wire pcit_if_pre_fetch_en5_in = pciu_pref_en_in[5] ; +wire [(pci_ba0_width - 1):0] pcit_if_pci_base_addr0_in = pciu_bar0_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr1_in = pciu_bar1_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr2_in = pciu_bar2_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr3_in = pciu_bar3_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr4_in = pciu_bar4_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr5_in = pciu_bar5_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask0_in = pciu_am0_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask1_in = pciu_am1_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask2_in = pciu_am2_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask3_in = pciu_am3_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask4_in = pciu_am4_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask5_in = pciu_am5_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr0_in = pciu_ta0_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr1_in = pciu_ta1_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr2_in = pciu_ta2_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr3_in = pciu_ta3_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr4_in = pciu_ta4_in ; +wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr5_in = pciu_ta5_in ; +wire pcit_if_addr_tran_en0_in = pciu_at_en_in[0] ; +wire pcit_if_addr_tran_en1_in = pciu_at_en_in[1] ; +wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ; +wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ; +wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ; +wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ; + +pci_target32_interface pci_target_if +( + .clk_in (pci_clock_in), + .reset_in (reset_in), + .address_in (pcit_if_address_in), + .addr_claim_out (pcit_if_addr_claim_out), + .bc_in (pcit_if_bc_in), + .bc0_in (pcit_if_bc0_in), + .data_in (pcit_if_data_in), + .data_out (pcit_if_data_out), + .be_in (pcit_if_be_in), + .next_be_in (pcit_if_next_be_in), + .req_in (pcit_if_req_in), + .rdy_in (pcit_if_rdy_in), + .addr_phase_in (pcit_if_addr_phase_in), + .bckp_devsel_in (pcit_if_bckp_devsel_in), + .bckp_trdy_in (pcit_if_bckp_trdy_in), + .bckp_stop_in (pcit_if_bckp_stop_in), + .last_reg_in (pcit_if_last_reg_in), + .frame_reg_in (pcit_if_frame_reg_in), + .fetch_pcir_fifo_in (pcit_if_fetch_pcir_fifo_in), + .load_medium_reg_in (pcit_if_load_medium_reg_in), + .sel_fifo_mreg_in (pcit_if_sel_fifo_mreg_in), + .sel_conf_fifo_in (pcit_if_sel_conf_fifo_in), + .load_to_pciw_fifo_in (pcit_if_load_to_pciw_fifo_in), + .load_to_conf_in (pcit_if_load_to_conf_in), + .same_read_out (pcit_if_same_read_out), + .norm_access_to_config_out (pcit_if_norm_access_to_config_out), + .read_completed_out (pcit_if_read_completed_out), + .read_processing_out (pcit_if_read_processing_out), + .target_abort_out (pcit_if_target_abort_out), + .disconect_wo_data_out (pcit_if_disconect_wo_data_out), + .disconect_w_data_out (pcit_if_disconect_w_data_out), + .pciw_fifo_full_out (pcit_if_pciw_fifo_full_out), + .pcir_fifo_data_err_out (pcit_if_pcir_fifo_data_err_out), + .wbw_fifo_empty_out (pcit_if_wbw_fifo_empty_out), + .wbu_del_read_comp_pending_out (pcit_if_wbu_del_read_comp_pending_out), + .req_out (pcit_if_req_out), + .done_out (pcit_if_done_out), + .in_progress_out (pcit_if_in_progress_out), + .req_req_pending_in (pcit_if_req_req_pending_in), + .req_comp_pending_in (pcit_if_req_comp_pending_in), + .addr_out (pcit_if_addr_out), + .be_out (pcit_if_be_out), + .we_out (pcit_if_we_out), + .bc_out (pcit_if_bc_out), + .burst_ok_out (pcit_if_burst_ok_out), + .strd_addr_in (pcit_if_strd_addr_in), + .strd_bc_in (pcit_if_strd_bc_in), + .status_in (pcit_if_status_in), + .comp_flush_in (pcit_if_comp_flush_in), + .pcir_fifo_renable_out (pcit_if_pcir_fifo_renable_out), + .pcir_fifo_data_in (pcit_if_pcir_fifo_data_in), + .pcir_fifo_be_in (pcit_if_pcir_fifo_be_in), + .pcir_fifo_control_in (pcit_if_pcir_fifo_control_in), + .pcir_fifo_flush_out (pcit_if_pcir_fifo_flush_out), + .pcir_fifo_almost_empty_in (pcit_if_pcir_fifo_almost_empty_in), + .pcir_fifo_empty_in (pcit_if_pcir_fifo_empty_in), + .pciw_fifo_wenable_out (pcit_if_pciw_fifo_wenable_out), + .pciw_fifo_addr_data_out (pcit_if_pciw_fifo_addr_data_out), + .pciw_fifo_cbe_out (pcit_if_pciw_fifo_cbe_out), + .pciw_fifo_control_out (pcit_if_pciw_fifo_control_out), + .pciw_fifo_three_left_in (pcit_if_pciw_fifo_three_left_in), + .pciw_fifo_two_left_in (pcit_if_pciw_fifo_two_left_in), + .pciw_fifo_almost_full_in (pcit_if_pciw_fifo_almost_full_in), + .pciw_fifo_full_in (pcit_if_pciw_fifo_full_in), + .wbw_fifo_empty_in (pcit_if_wbw_fifo_empty_in), + .wbu_del_read_comp_pending_in (pcit_if_wbu_del_read_comp_pending_in), + .conf_addr_out (pcit_if_conf_addr_out), + .conf_data_out (pcit_if_conf_data_out), + .conf_data_in (pcit_if_conf_data_in), + .conf_be_out (pcit_if_conf_be_out), + .conf_we_out (pcit_if_conf_we_out), + .conf_re_out (pcit_if_conf_re_out), + .mem_enable_in (pcit_if_mem_enable_in), + .io_enable_in (pcit_if_io_enable_in), + .mem_io_addr_space0_in (pcit_if_mem_io_addr_space0_in), + .mem_io_addr_space1_in (pcit_if_mem_io_addr_space1_in), + .mem_io_addr_space2_in (pcit_if_mem_io_addr_space2_in), + .mem_io_addr_space3_in (pcit_if_mem_io_addr_space3_in), + .mem_io_addr_space4_in (pcit_if_mem_io_addr_space4_in), + .mem_io_addr_space5_in (pcit_if_mem_io_addr_space5_in), + .pre_fetch_en0_in (pcit_if_pre_fetch_en0_in), + .pre_fetch_en1_in (pcit_if_pre_fetch_en1_in), + .pre_fetch_en2_in (pcit_if_pre_fetch_en2_in), + .pre_fetch_en3_in (pcit_if_pre_fetch_en3_in), + .pre_fetch_en4_in (pcit_if_pre_fetch_en4_in), + .pre_fetch_en5_in (pcit_if_pre_fetch_en5_in), + .pci_base_addr0_in (pcit_if_pci_base_addr0_in), + .pci_base_addr1_in (pcit_if_pci_base_addr1_in), + .pci_base_addr2_in (pcit_if_pci_base_addr2_in), + .pci_base_addr3_in (pcit_if_pci_base_addr3_in), + .pci_base_addr4_in (pcit_if_pci_base_addr4_in), + .pci_base_addr5_in (pcit_if_pci_base_addr5_in), + .pci_addr_mask0_in (pcit_if_pci_addr_mask0_in), + .pci_addr_mask1_in (pcit_if_pci_addr_mask1_in), + .pci_addr_mask2_in (pcit_if_pci_addr_mask2_in), + .pci_addr_mask3_in (pcit_if_pci_addr_mask3_in), + .pci_addr_mask4_in (pcit_if_pci_addr_mask4_in), + .pci_addr_mask5_in (pcit_if_pci_addr_mask5_in), + .pci_tran_addr0_in (pcit_if_pci_tran_addr0_in), + .pci_tran_addr1_in (pcit_if_pci_tran_addr1_in), + .pci_tran_addr2_in (pcit_if_pci_tran_addr2_in), + .pci_tran_addr3_in (pcit_if_pci_tran_addr3_in), + .pci_tran_addr4_in (pcit_if_pci_tran_addr4_in), + .pci_tran_addr5_in (pcit_if_pci_tran_addr5_in), + .addr_tran_en0_in (pcit_if_addr_tran_en0_in), + .addr_tran_en1_in (pcit_if_addr_tran_en1_in), + .addr_tran_en2_in (pcit_if_addr_tran_en2_in), + .addr_tran_en3_in (pcit_if_addr_tran_en3_in), + .addr_tran_en4_in (pcit_if_addr_tran_en4_in), + .addr_tran_en5_in (pcit_if_addr_tran_en5_in) +) ; + +// pci target state machine inputs +wire pcit_sm_frame_in = pciu_pciif_frame_in ; +wire pcit_sm_irdy_in = pciu_pciif_irdy_in ; +wire pcit_sm_idsel_in = pciu_pciif_idsel_in ; +wire pcit_sm_frame_reg_in = pciu_pciif_frame_reg_in ; +wire pcit_sm_irdy_reg_in = pciu_pciif_irdy_reg_in ; +wire pcit_sm_idsel_reg_in = pciu_pciif_idsel_reg_in ; +wire [31:0] pcit_sm_ad_reg_in = pciu_pciif_ad_reg_in ; +wire [3:0] pcit_sm_cbe_reg_in = pciu_pciif_cbe_reg_in ; +wire [3:0] pcit_sm_cbe_in = pciu_pciif_cbe_in ; +wire pcit_sm_bckp_trdy_en_in = pciu_pciif_bckp_trdy_en_in ; +wire pcit_sm_bckp_devsel_in = pciu_pciif_bckp_devsel_in ; +wire pcit_sm_bckp_trdy_in = pciu_pciif_bckp_trdy_in ; +wire pcit_sm_bckp_stop_in = pciu_pciif_bckp_stop_in ; +wire pcit_sm_addr_claim_in = pcit_if_addr_claim_out ; +wire [31:0] pcit_sm_data_in = pcit_if_data_out ; +wire pcit_sm_same_read_in = pcit_if_same_read_out ; +wire pcit_sm_norm_access_to_config_in = pcit_if_norm_access_to_config_out ; +wire pcit_sm_read_completed_in = pcit_if_read_completed_out ; +wire pcit_sm_read_processing_in = pcit_if_read_processing_out ; +wire pcit_sm_target_abort_in = pcit_if_target_abort_out ; +wire pcit_sm_disconect_wo_data_in = pcit_if_disconect_wo_data_out ; +wire pcit_sm_disconect_w_data_in = pcit_if_disconect_w_data_out ; +wire pcit_sm_pciw_fifo_full_in = pcit_if_pciw_fifo_full_out ; +wire pcit_sm_pcir_fifo_data_err_in = pcit_if_pcir_fifo_data_err_out ; +wire pcit_sm_wbw_fifo_empty_in = pcit_if_wbw_fifo_empty_out ; +wire pcit_sm_wbu_del_read_comp_pending_in = pcit_if_wbu_del_read_comp_pending_out ; +wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ; +wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ; +wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ; + + +pci_target32_sm pci_target_sm +( + .clk_in (pci_clock_in), + .reset_in (reset_in), + .pci_frame_in (pcit_sm_frame_in), + .pci_irdy_in (pcit_sm_irdy_in), + .pci_idsel_in (pcit_sm_idsel_in), + .pci_frame_reg_in (pcit_sm_frame_reg_in), + .pci_irdy_reg_in (pcit_sm_irdy_reg_in), + .pci_idsel_reg_in (pcit_sm_idsel_reg_in), + .pci_trdy_out (pcit_sm_trdy_out), + .pci_stop_out (pcit_sm_stop_out), + .pci_devsel_out (pcit_sm_devsel_out), + .pci_trdy_en_out (pcit_sm_trdy_en_out), + .pci_stop_en_out (pcit_sm_stop_en_out), + .pci_devsel_en_out (pcit_sm_devsel_en_out), + .ad_load_out (pcit_sm_ad_load_out), + .ad_load_on_transfer_out (pcit_sm_ad_load_on_transfer_out), + .pci_ad_reg_in (pcit_sm_ad_reg_in), + .pci_ad_out (pcit_sm_ad_out), + .pci_ad_en_out (pcit_sm_ad_en_out), + .pci_cbe_reg_in (pcit_sm_cbe_reg_in), + .pci_cbe_in (pcit_sm_cbe_in), + .bckp_trdy_en_in (pcit_sm_bckp_trdy_en_in), + .bckp_devsel_in (pcit_sm_bckp_devsel_in), + .bckp_trdy_in (pcit_sm_bckp_trdy_in), + .bckp_stop_in (pcit_sm_bckp_stop_in), + .pci_trdy_reg_in (pcit_sm_trdy_reg_in), + .pci_stop_reg_in (pcit_sm_stop_reg_in), + .address_out (pcit_sm_address_out), + .addr_claim_in (pcit_sm_addr_claim_in), + .bc_out (pcit_sm_bc_out), + .bc0_out (pcit_sm_bc0_out), + .data_out (pcit_sm_data_out), + .data_in (pcit_sm_data_in), + .be_out (pcit_sm_be_out), + .next_be_out (pcit_sm_next_be_out), + .req_out (pcit_sm_req_out), + .rdy_out (pcit_sm_rdy_out), + .addr_phase_out (pcit_sm_addr_phase_out), + .bckp_devsel_out (pcit_sm_bckp_devsel_out), + .bckp_trdy_out (pcit_sm_bckp_trdy_out), + .bckp_stop_out (pcit_sm_bckp_stop_out), + .last_reg_out (pcit_sm_last_reg_out), + .frame_reg_out (pcit_sm_frame_reg_out), + .fetch_pcir_fifo_out (pcit_sm_fetch_pcir_fifo_out), + .load_medium_reg_out (pcit_sm_load_medium_reg_out), + .sel_fifo_mreg_out (pcit_sm_sel_fifo_mreg_out), + .sel_conf_fifo_out (pcit_sm_sel_conf_fifo_out), + .load_to_pciw_fifo_out (pcit_sm_load_to_pciw_fifo_out), + .load_to_conf_out (pcit_sm_load_to_conf_out), + .same_read_in (pcit_sm_same_read_in), + .norm_access_to_config_in (pcit_sm_norm_access_to_config_in), + .read_completed_in (pcit_sm_read_completed_in), + .read_processing_in (pcit_sm_read_processing_in), + .target_abort_in (pcit_sm_target_abort_in), + .disconect_wo_data_in (pcit_sm_disconect_wo_data_in), + .disconect_w_data_in (pcit_sm_disconect_w_data_in), + .target_abort_set_out (pcit_sm_target_abort_set_out), + .pciw_fifo_full_in (pcit_sm_pciw_fifo_full_in), + .pcir_fifo_data_err_in (pcit_sm_pcir_fifo_data_err_in), + .wbw_fifo_empty_in (pcit_sm_wbw_fifo_empty_in), + .wbu_del_read_comp_pending_in (pcit_sm_wbu_del_read_comp_pending_in), + .wbu_frame_en_in (pcit_sm_wbu_frame_en_in) +) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_user_constants.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_user_constants.v new file mode 100644 index 000000000..f65ffec42 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_user_constants.v @@ -0,0 +1,330 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "pci_user_constants.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// - Tadej Markovic (tadej@opencores.org) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_user_constants.v,v $ +// Revision 1.15 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.14 2004/07/07 12:45:01 mihad +// Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. +// Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers. +// +// Revision 1.13 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.12 2003/12/28 09:54:48 fr2201 +// def_wb_imagex_addr_map defined correctly +// +// Revision 1.11 2003/12/28 09:20:00 fr2201 +// Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) +// +// Revision 1.10 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.9 2003/08/03 18:05:06 mihad +// Added limited WISHBONE B3 support for WISHBONE Slave Unit. +// Doesn't support full speed bursts yet. +// +// Revision 1.8 2003/03/14 15:31:57 mihad +// Entered the option to disable no response counter in wb master. +// +// Revision 1.7 2003/01/27 17:05:50 mihad +// Updated. +// +// Revision 1.6 2003/01/27 16:51:19 mihad +// Old files with wrong names removed. +// +// Revision 1.5 2003/01/21 16:06:56 mihad +// Bug fixes, testcases added. +// +// Revision 1.4 2002/09/30 17:22:45 mihad +// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! +// +// Revision 1.3 2002/08/13 11:03:53 mihad +// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image +// +// Revision 1.2 2002/03/05 11:53:47 mihad +// Added some testcases, removed un-needed fifo signals +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// Fifo implementation defines: +// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage. +// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out), +// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used +// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations ) +// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with +// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port +// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ). +// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and +// WB_FIFO_RAM_ADDR_LENGTH. + +`define WBW_ADDR_LENGTH 4 +`define WBR_ADDR_LENGTH 4 +`define PCIW_ADDR_LENGTH 3 +`define PCIR_ADDR_LENGTH 3 + +//`define FPGA +//`define XILINX + +`define WB_RAM_DONT_SHARE +`define PCI_RAM_DONT_SHARE + +`ifdef FPGA + `ifdef XILINX + `define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition + `define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition + `define PCI_XILINX_RAMB4 + `define WB_XILINX_RAMB4 + //`define PCI_XILINX_DIST_RAM + //`define WB_XILINX_DIST_RAM + `endif +`else + `define PCI_FIFO_RAM_ADDR_LENGTH 3 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) + `define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) +// `define WB_ARTISAN_SDP +// `define PCI_ARTISAN_SDP +// `define PCI_VS_STP +// `define WB_VS_STP +`endif + +// these two defines allow user to select active high or low output enables on PCI bus signals, depending on +// output buffers instantiated. Xilinx FPGAs use active low output enables. +`define ACTIVE_LOW_OE +//`define ACTIVE_HIGH_OE + +// HOST/GUEST implementation selection - see design document and specification for description of each implementation +// only one can be defined at same time +//`define HOST +`define GUEST + +// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED: +// - ENABLED Read-Only access from WISHBONE for GUEST bridges +// - ENABLED Read-Only access from PCI for HOST bridges +// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved +`define NO_CNF_IMAGE + +// number defined here specifies how many MS bits in PCI address are compared with base address, to decode +// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number +// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images, +// you have to define a number of minimum sized image and enlarge others by specifying different address mask. +// smaller the number here, faster the decoder operation +`define PCI_NUM_OF_DEC_ADDR_LINES 24 + +// no. of PCI Target IMAGES +// - PCI provides 6 base address registers for image implementation. +// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented +// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space +// access. +// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration +// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there +// is no access to Configuration space possible from PCI bus. +// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST +// or GUEST implementation. +`ifdef HOST + `ifdef NO_CNF_IMAGE + //`define PCI_IMAGE0 + `endif +`endif + +//`define PCI_IMAGE2 +//`define PCI_IMAGE3 +//`define PCI_IMAGE4 +//`define PCI_IMAGE5 + +// initial value for PCI image address masks. Address masks can be defined in enabled state, +// to allow device independent software to detect size of image and map base addresses to +// memory space. If initial mask for an image is defined as 0, then device independent software +// won't detect base address implemented and device dependent software will have to configure +// address masks as well as base addresses! +// Don't define PCI_AMx to 24'hffff_ff for memory images! Use that just for I/O images. +`define PCI_AM0 24'hffff_f0 +`define PCI_AM1 24'hffff_ff +`define PCI_AM2 24'hffff_f0 +`define PCI_AM3 24'hffff_f0 +`define PCI_AM4 24'hffff_f0 +`define PCI_AM5 24'hffff_f0 + +// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0, +// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D +// Device independent software sets the base addresses acording to MEMORY or IO maping! +`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image! +`define PCI_BA1_MEM_IO 1'b1 +`define PCI_BA2_MEM_IO 1'b0 +`define PCI_BA3_MEM_IO 1'b0 +`define PCI_BA4_MEM_IO 1'b0 +`define PCI_BA5_MEM_IO 1'b0 + +// initial value for PCI translation addresses. The initial values +// are set after reset. When ADDR_TRAN_IMPL is defined then then Images +// are transleted to this adresses whithout access to pci_ta registers. +`define PCI_TA0 24'h0000_0 +`define PCI_TA1 24'h0000_0 +`define PCI_TA2 24'h0000_0 +`define PCI_TA3 24'h0000_0 +`define PCI_TA4 24'h0000_0 +`define PCI_TA5 24'h0000_0 + +`define PCI_AT_EN0 1'b0 +`define PCI_AT_EN1 1'b0 +`define PCI_AT_EN2 1'b0 +`define PCI_AT_EN3 1'b0 +`define PCI_AT_EN4 1'b0 +`define PCI_AT_EN5 1'b0 + +// number defined here specifies how many MS bits in WB address are compared with base address, to decode +// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number +// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images, +// you have to define a number of minimum sized image and enlarge others by specifying different address mask. +// smaller the number here, faster the decoder operation +`define WB_NUM_OF_DEC_ADDR_LINES 1 + +// no. of WISHBONE Slave IMAGES +// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented, +// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0. +// WB Image 1 is always implemented and user doesnt need to specify its definition +// WB images' 2 through 5 implementation by defining each one. +`define WB_IMAGE2 +//`define WB_IMAGE3 +//`define WB_IMAGE4 +//`define WB_IMAGE5 + +//Address bar register defines the base address for each image. +//To asccess bus without Software configuration. +`define WB_BA1 20'h0000_0 +`define WB_BA2 20'h8000_0 +`define WB_BA3 20'h0000_0 +`define WB_BA4 20'h0000_0 +`define WB_BA5 20'h0000_0 + +// initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0, +// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. +`define WB_BA1_MEM_IO 1'b0 +`define WB_BA2_MEM_IO 1'b0 +`define WB_BA3_MEM_IO 1'b0 +`define WB_BA4_MEM_IO 1'b0 +`define WB_BA5_MEM_IO 1'b0 + +// initial value for WB image address masks. +`define WB_AM1 20'h8000_0 +`define WB_AM2 20'h8000_0 +`define WB_AM3 20'h0000_0 +`define WB_AM4 20'h0000_0 +`define WB_AM5 20'h0000_0 + +// initial value for WB translation addresses. The initial values +// are set after reset. When ADDR_TRAN_IMPL is defined then then Images +// are transleted to this adresses whithout access to pci_ta registers. +`define WB_TA1 20'h0000_0 +`define WB_TA2 20'h0000_0 +`define WB_TA3 20'h0000_0 +`define WB_TA4 20'h0000_0 +`define WB_TA5 20'h0000_0 + +`define WB_AT_EN1 1'b0 +`define WB_AT_EN2 1'b0 +`define WB_AT_EN3 1'b0 +`define WB_AT_EN4 1'b0 +`define WB_AT_EN5 1'b0 + +// If this define is commented out, then address translation will not be implemented. +// addresses will pass through bridge unchanged, regardles of address translation enable bits. +// Address translation also slows down the decoding +//When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset. +//`define ADDR_TRAN_IMPL + +// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow. +// slower decode speed can be used, to provide enough time for address to be decoded. +`define WB_DECODE_FAST +//`define WB_DECODE_MEDIUM +//`define WB_DECODE_SLOW + +// Base address for Configuration space access from WB bus. This value cannot be changed during runtime +`define WB_CONFIGURATION_BASE 20'h0000_0 + +// Turn registered WISHBONE slave outputs on or off +// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as +// outputs to internals of the core. +//`define REGISTER_WBS_OUTPUTS + +/*----------------------------------------------------------------------------------------------------------- +Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz +capable device +-----------------------------------------------------------------------------------------------------------*/ +`define PCI33 +//`define PCI66 + +/*----------------------------------------------------------------------------------------------------------- +[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type ! + Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. + Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used + together by application. +-----------------------------------------------------------------------------------------------------------*/ +`define HEADER_VENDOR_ID 16'h1895 +`define HEADER_DEVICE_ID 16'h0001 +`define HEADER_REVISION_ID 8'h01 +`define HEADER_SUBSYS_VENDOR_ID 16'h1895 +`define HEADER_SUBSYS_ID 16'h0001 +`define HEADER_MAX_LAT 8'h1a +`define HEADER_MIN_GNT 8'h08 + +// MAX Retry counter value for WISHBONE Master state-machine +// This value is 8-bit because of 8-bit retry counter !!! +`define WB_RTY_CNT_MAX 8'hff + +// define the macro below to disable internal retry generation in the wishbone master interface +// used when wb master accesses extremly slow devices. +`define PCI_WBM_NO_RESPONSE_CNT_DISABLE + +`define PCI_WB_REV_B3 +//`define PCI_WBS_B3_RTY_DISABLE + +`ifdef GUEST +// `define PCI_CPCI_HS_IMPLEMENT +// `define PCI_SPOCI +`endif + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v new file mode 100644 index 000000000..b35ee37f3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_addr_mux.v @@ -0,0 +1,279 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "wb_addr_mux.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_addr_mux.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.4 2002/08/19 16:54:25 mihad +// Got rid of undef directives +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images +`include "pci_constants.v" +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_wb_addr_mux +( + `ifdef REGISTER_WBS_OUTPUTS + clk_in, + reset_in, + sample_address_in, + `endif + address_in, + bar0_in, + bar1_in, + bar2_in, + bar3_in, + bar4_in, + bar5_in, + am0_in, + am1_in, + am2_in, + am3_in, + am4_in, + am5_in, + ta0_in, + ta1_in, + ta2_in, + ta3_in, + ta4_in, + ta5_in, + at_en_in, + hit_out, + address_out +); + +input [31:0] address_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ; +input [5:0] at_en_in ; +output [5:0] hit_out ; +output [31:0] address_out ; +reg [31:0] address_out ; + +wire [31:0] addr0 ; +wire [31:0] addr1 ; +wire [31:0] addr2 ; +wire [31:0] addr3 ; +wire [31:0] addr4 ; +wire [31:0] addr5 ; + +wire [5:0] hit ; +assign hit_out = hit ; + +`ifdef REGISTER_WBS_OUTPUTS + input clk_in, reset_in, sample_address_in ; + + reg [31:0] address ; + always@(posedge clk_in or posedge reset_in) + begin + if ( reset_in ) + address <= #`FF_DELAY 0 ; + else + if ( sample_address_in ) + address <= #`FF_DELAY address_in ; + end +`else + wire [31:0] address = address_in ; +`endif + +`ifdef GUEST + `ifdef NO_CNF_IMAGE + `else + `define PCI_WB_ADDR_MUX_DEC0_INCLUDE + `endif +`else +`ifdef HOST + `define PCI_WB_ADDR_MUX_DEC0_INCLUDE +`endif +`endif + +`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE + pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0 + ( + .hit (hit[0]), + .addr_out (addr0), + .addr_in (address), + .base_addr (bar0_in), + .mask_addr (am0_in), + .tran_addr (ta0_in), + .at_en (1'b0) + ) ; +`else + // configuration image not implemented + assign hit[0] = 1'b0 ; + assign addr0 = 32'h0000_0000 ; +`endif + +// one image is always implemented +pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1 +( + .hit (hit[1]), + .addr_out (addr1), + .addr_in (address), + .base_addr (bar1_in), + .mask_addr (am1_in), + .tran_addr (ta1_in), + .at_en (at_en_in[1]) +) ; + +`ifdef WB_IMAGE2 + pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2 + ( + .hit (hit[2]), + .addr_out (addr2), + .addr_in (address), + .base_addr (bar2_in), + .mask_addr (am2_in), + .tran_addr (ta2_in), + .at_en (at_en_in[2]) + ) ; + +`else + assign hit[2] = 1'b0 ; + assign addr2 = 0 ; +`endif + +`ifdef WB_IMAGE3 + pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3 + ( + .hit (hit[3]), + .addr_out (addr3), + .addr_in (address), + .base_addr (bar3_in), + .mask_addr (am3_in), + .tran_addr (ta3_in), + .at_en (at_en_in[3]) + ) ; +`else + assign hit[3] = 1'b0 ; + assign addr3 = 0 ; +`endif + +`ifdef WB_IMAGE4 + pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4 + ( + .hit (hit[4]), + .addr_out (addr4), + .addr_in (address), + .base_addr (bar4_in), + .mask_addr (am4_in), + .tran_addr (ta4_in), + .at_en (at_en_in[4]) + ) ; +`else + assign hit[4] = 1'b0 ; + assign addr4 = 0 ; +`endif + +`ifdef WB_IMAGE5 + pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5 + ( + .hit (hit[5]), + .addr_out (addr5), + .addr_in (address), + .base_addr (bar5_in), + .mask_addr (am5_in), + .tran_addr (ta5_in), + .at_en (at_en_in[5]) + ) ; +`else + assign hit[5] = 1'b0 ; + assign addr5 = 0 ; +`endif + +// address multiplexer +always@ +( + hit or + addr0 or + addr1 or + addr2 or + addr3 or + addr4 or + addr5 +) +begin + case ( {hit[5:2], hit[0]} ) + 5'b0_0_0_0_1: address_out = addr0 ; + 5'b0_0_0_1_0: address_out = addr2 ; + 5'b0_0_1_0_0: address_out = addr3 ; + 5'b0_1_0_0_0: address_out = addr4 ; + 5'b1_0_0_0_0: address_out = addr5 ; + + // default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image + // this multiplexer can be completely removed during synthesys + default: address_out = addr1 ; + endcase +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_decoder.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_decoder.v new file mode 100644 index 000000000..3f84a804f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_decoder.v @@ -0,0 +1,170 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: decoder.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// - Tilen Novak, tilen@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// Tilen Novak, tilen@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_decoder.v,v $ +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.3 2002/02/01 15:25:12 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:28 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_wb_decoder (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en) ; + +// Decoding address size parameter - for FPGAs 1MegByte is recommended +// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!! +parameter decode_len = 12 ; + +//########################################################################################################### +// ALL COMMENTS are written as there were decode_len 20. This number and 12 (32 - 20) are assigning the +// numbers of decoded and compared bits, etc. +//########################################################################################################### + +/*----------------------------------------------------------------------------------------------------------- +DECODER interface decodes input address (ADDR_IN); what means that it validates (HIT), if input address +falls within the defined image space boundaries. Image space boundarie is defined with image base address +register (BASE_ADDR) and address mask register (MASK_ADDR). +Beside that, it also translates (maps) the input address to the output address (ADDR_OUT), regarding the +translation address register (TRAN_ADDR) and the address mask register. +-----------------------------------------------------------------------------------------------------------*/ + +// output control +output hit ; +// output address +output [31:0] addr_out ; +// input address +input [31:0] addr_in ; + +// input registers - 12 LSbits are not valid since the smallest possible size is 4KB ! +input [31:(32-decode_len)] base_addr ; +input [31:(32-decode_len)] mask_addr ; +input [31:(32-decode_len)] tran_addr ; + +// input bit[2] of the Image Control register used to enable the address translation ! +input at_en ; +/*----------------------------------------------------------------------------------------------------------- +Internal signals ! +-----------------------------------------------------------------------------------------------------------*/ + +// bit[31] if address mask register is IMAGE ENABLE bit (img_en) +wire img_en ; + +// addr_in_compare are masked input address bits that are compared with masked base_addr +wire [31:(32-decode_len)] addr_in_compare ; +// base_addr_compare are masked base address bits that are compared with masked addr_in +wire [31:(32-decode_len)] base_addr_compare ; + +/*----------------------------------------------------------------------------------------------------------- +Decoding the input address! +This logic produces the loghest path in this module! + +20 MSbits of input addres are as well as base address (20 bits) masked with corrected address mask. Only +masked bits of each vector are actually logically compared. +Bit[31] of address mask register is used to enable the image space ! +-----------------------------------------------------------------------------------------------------------*/ + +assign addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ; + +assign base_addr_compare = (base_addr & mask_addr) ; + +assign img_en = mask_addr[31] ; + +assign hit = { 1'b1, addr_in_compare } == { img_en, base_addr_compare } ; + +/*----------------------------------------------------------------------------------------------------------- +Translating the input address! + +Translation of input address is not implemented if ADDR_TRAN_IMPL is not defined + +20 MSbits of input address are masked with negated value of the corrected address mask in order to get +address bits of the input address which won't be replaced with translation address bits. +Translation address bits (20 bits) are masked with corrected address mask. Only masked bits of vector are +actually valid, all others are zero. +Boath vectors are bit-wise ORed in order to get the valid translation address with an offset of an input +address. +12 LSbits of an input address are assigned to 12 LSbits of an output addres. +-----------------------------------------------------------------------------------------------------------*/ + +`ifdef ADDR_TRAN_IMPL + // if Address Translation Enable bit is set, then translation address is used othervise input address is used! + // addr_in_combine input address bits are not replaced with translation address! + wire [31:(32-decode_len)] addr_in_combine ; + // tran_addr_combine are masked and combined with addr_in_combine! + reg [31:(32-decode_len)] tran_addr_combine ; + + assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ; + always@(at_en or tran_addr or mask_addr or addr_in) + begin + if (at_en) + begin + tran_addr_combine <= (tran_addr & mask_addr) ; + end + else + begin + tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ; + end + end + + assign addr_out[31:(32-decode_len)] = addr_in_combine | tran_addr_combine ; + assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ; +`else + assign addr_out = addr_in ; +`endif + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v new file mode 100644 index 000000000..591e2206f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_master.v @@ -0,0 +1,1173 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name: wb_master.v //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Tadej Markovic, tadej@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_master.v,v $ +// Revision 1.6 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.5 2003/10/24 09:35:40 tadejm +// Added missing signals to 2 sensitivity lists. Everything works the same as before. +// +// Revision 1.4 2003/08/21 20:56:40 tadejm +// WB Master is now WISHBONE B3 compatible. +// +// Revision 1.3 2003/03/14 15:31:57 mihad +// Entered the option to disable no response counter in wb master. +// +// Revision 1.2 2003/01/30 22:01:09 mihad +// Updated synchronization in top level fifo modules. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.7 2002/12/05 12:19:23 mihad +// *** empty log message *** +// +// Revision 1.6 2002/10/11 14:15:29 mihad +// Cleaned up non-blocking assignments in combinatinal logic statements +// +// Revision 1.5 2002/03/05 11:53:47 mihad +// Added some testcases, removed un-needed fifo signals +// +// Revision 1.4 2002/02/19 16:32:37 mihad +// Modified testbench and fixed some bugs +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +`define WB_FSM_BITS 3 // number of bits needed for FSM states + + +`include "bus_commands.v" +`include "pci_constants.v" +//synopsys translate_off +`include "timescale.v" +//synopsys translate_on + +module pci_wb_master + ( wb_clock_in, // CLK_I + reset_in, // RST_I + + pci_tar_read_request, + pci_tar_address, + pci_tar_cmd, + pci_tar_be, + pci_tar_burst_ok, + pci_cache_line_size, + cache_lsize_not_zero, + wb_read_done_out, + w_attempt, + + pcir_fifo_wenable_out, + pcir_fifo_data_out, + pcir_fifo_be_out, + pcir_fifo_control_out, + //pcir_fifo_renable_out, for PCI Target !!! + //pcir_fifo_data_in, for PCI Target !!! + //pcir_fifo_be_in, for PCI Target !!! + //pcir_fifo_control_in, for PCI Target !!! + //pcir_fifo_flush_out, for PCI Target !!! + //pcir_fifo_almost_empty_in, for PCI Target !!! + //pcir_fifo_empty_in, NOT used + //pcir_fifo_transaction_ready_in, NOT used + //pciw_fifo_wenable_out, for PCI Target !!! + //pciw_fifo_addr_data_out, for PCI Target !!! + //pciw_fifo_cbe_out, for PCI Target !!! + //pciw_fifo_control_out, for PCI Target !!! + pciw_fifo_renable_out, + pciw_fifo_addr_data_in, + pciw_fifo_cbe_in, + pciw_fifo_control_in, + //pciw_fifo_flush_out, NOT used + //pciw_fifo_almost_full_in, for PCI Target !!! + //pciw_fifo_full_in, for PCI Target !!! + pciw_fifo_almost_empty_in, + pciw_fifo_empty_in, + pciw_fifo_transaction_ready_in, + + pci_error_sig_out, + pci_error_bc, + write_rty_cnt_exp_out, + error_source_out, + read_rty_cnt_exp_out, + + wb_cyc_o, + wb_stb_o, + wb_we_o, + wb_cti_o, + wb_bte_o, + wb_sel_o, + wb_adr_o, + wb_dat_i, + wb_dat_o, + wb_ack_i, + wb_rty_i, + wb_err_i +// CYC_O, +// STB_O, +// WE_O, +// SEL_O, +// ADR_O, +// MDATA_I, +// MDATA_O, +// ACK_I, +// RTY_I, +// ERR_I, + ); + +/*---------------------------------------------------------------------------------------------------------------------- +Various parameters needed for state machine and other stuff +----------------------------------------------------------------------------------------------------------------------*/ +parameter S_IDLE = `WB_FSM_BITS'h0 ; +parameter S_WRITE = `WB_FSM_BITS'h1 ; +parameter S_WRITE_ERR_RTY = `WB_FSM_BITS'h2 ; +parameter S_READ = `WB_FSM_BITS'h3 ; +parameter S_READ_RTY = `WB_FSM_BITS'h4 ; +parameter S_TURN_ARROUND = `WB_FSM_BITS'h5 ; + +/*---------------------------------------------------------------------------------------------------------------------- +System signals inputs +wb_clock_in - WISHBONE bus clock input +reset_in - system reset input controlled by bridge's reset logic +----------------------------------------------------------------------------------------------------------------------*/ +input wb_clock_in ; +input reset_in ; + +/*---------------------------------------------------------------------------------------------------------------------- +Control signals from PCI Target for READS to PCIR_FIFO +---------------------------------------------------------------------------------------------------------------------*/ +input pci_tar_read_request ; // read request from PCI Target +input [31:0] pci_tar_address ; // address for requested read from PCI Target +input [3:0] pci_tar_cmd ; // command for requested read from PCI Target +input [3:0] pci_tar_be ; // byte enables for requested read from PCI Target +input pci_tar_burst_ok ; +input [7:0] pci_cache_line_size ; // CACHE line size register value for burst length +input cache_lsize_not_zero ; +output wb_read_done_out ; // read done and PCIR_FIFO has data ready +output w_attempt ; + +reg wb_read_done_out ; +reg wb_read_done ; + +/*---------------------------------------------------------------------------------------------------------------------- +PCIR_FIFO control signals used for sinking data into PCIR_FIFO and status monitoring +---------------------------------------------------------------------------------------------------------------------*/ +output pcir_fifo_wenable_out ; // PCIR_FIFO write enable output +output [31:0] pcir_fifo_data_out ; // data output to PCIR_FIFO +output [3:0] pcir_fifo_be_out ; // byte enable output to PCIR_FIFO +output [3:0] pcir_fifo_control_out ; // control bus output to PCIR_FIFO + +reg [31:0] pcir_fifo_data_out ; +reg pcir_fifo_wenable_out ; +reg pcir_fifo_wenable ; +reg [3:0] pcir_fifo_control_out ; +reg [3:0] pcir_fifo_control ; + +/*---------------------------------------------------------------------------------------------------------------------- +PCIW_FIFO control signals used for fetching data from PCIW_FIFO and status monitoring +---------------------------------------------------------------------------------------------------------------------*/ +output pciw_fifo_renable_out ; // read enable for PCIW_FIFO output +input [31:0] pciw_fifo_addr_data_in ; // address and data input from PCIW_FIFO +input [3:0] pciw_fifo_cbe_in ; // command and byte_enables from PCIW_FIFO +input [3:0] pciw_fifo_control_in ; // control bus input from PCIW_FIFO +input pciw_fifo_almost_empty_in ; // almost empty status indicator from PCIW_FIFO +input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO +input pciw_fifo_transaction_ready_in ; // write transaction is ready in PCIW_FIFO + +reg pciw_fifo_renable_out ; +reg pciw_fifo_renable ; + +/*---------------------------------------------------------------------------------------------------------------------- +Control INPUT / OUTPUT signals for configuration space reporting registers !!! +---------------------------------------------------------------------------------------------------------------------*/ +output pci_error_sig_out ; // When error occures (on WB bus, retry counter, etc.) +output [3:0] pci_error_bc ; // bus command at which error occured ! +output write_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during write transaction! +output read_rty_cnt_exp_out ; // Signaling that RETRY counter has expired during read transaction! + // if error_source is '0' other side didn't respond + // if error_source is '1' other side RETRIED for max retry counter value +output error_source_out ; // Signaling error source - '0' other WB side signaled error OR didn't respond + // if '1' wridge counted max value in retry counter because of RTY responds +reg pci_error_sig_out ; +reg write_rty_cnt_exp_out ; +reg read_rty_cnt_exp_out ; +reg error_source_out ; + +/*---------------------------------------------------------------------------------------------------------------------- +WISHBONE bus interface signals - can be connected directly to WISHBONE bus +---------------------------------------------------------------------------------------------------------------------*/ +output wb_cyc_o; // cycle indicator output +output wb_stb_o; // strobe output - data is valid when strobe and cycle indicator are high +output wb_we_o; // write enable output - 1 - write operation, 0 - read operation +output [2:0] wb_cti_o; // WB B3 - cycle type identifier +output [1:0] wb_bte_o; // WB B3 - burst type +output [3:0] wb_sel_o; // Byte select outputs +output [31:0] wb_adr_o; // WISHBONE address output +input [31:0] wb_dat_i; // WISHBONE interface input data bus +output [31:0] wb_dat_o; // WISHBONE interface output data bus +input wb_ack_i; // Acknowledge input - qualifies valid data on data output bus or received data on data input bus +input wb_rty_i; // retry input - signals from WISHBONE slave that cycle should be terminated and retried later +input wb_err_i; // Signals from WISHBONE slave that access resulted in an error + +reg wb_cyc_o; +reg wb_stb_o; +reg wb_we_o; +reg [2:0] wb_cti_o; +reg [1:0] wb_bte_o; +reg [3:0] wb_sel_o; +reg [31:0] wb_dat_o; + + + +/*########################################################################################################### +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + LOGIC, COUNTERS, STATE MACHINE and some control register bits + ============================================================= +///////////////////////////////////////////////////////////////////////////////////////////////////////////// +###########################################################################################################*/ + +reg last_data_transferred ; // signal is set by STATE MACHINE after each complete transfere ! + +// wire for write attempt - 1 when PCI Target attempt to write and PCIW_FIFO has a write transaction ready +reg w_attempt; +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + w_attempt <= #`FF_DELAY 1'b0; + else + begin + if (pciw_fifo_transaction_ready_in && ~pciw_fifo_empty_in) + w_attempt <= #`FF_DELAY 1'b1; + else + if (last_data_transferred) + w_attempt <= #`FF_DELAY 1'b0; + end +end + +// wire for read attempt - 1 when PCI Target is attempting a read and PCIR_FIFO is not full ! +// because of transaction ordering, PCI Master must not start read untill all writes are done -> at that +// moment PCIW_FIFO is empty !!! (when read is pending PCI Target will block new reads and writes) +wire r_attempt = ( pci_tar_read_request && !w_attempt && pciw_fifo_empty_in ) ; + +// Signal is used for reads on WB, when there is retry! +reg first_wb_data_access ; + +reg last_data_from_pciw_fifo ; // signal tells when there is last data in pciw_fifo +reg last_data_from_pciw_fifo_reg ; +reg last_data_to_pcir_fifo ; // signal tells when there will be last data for pcir_fifo + +// Logic used in State Machine logic implemented out of State Machine because of less delay! +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ; + else + begin + if ((pciw_fifo_renable_out) && + (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in)) // if last data is going to be transfered + last_data_from_pciw_fifo <= #`FF_DELAY 1'b1 ; // signal for last data from PCIW_FIFO + else + last_data_from_pciw_fifo <= #`FF_DELAY 1'b0 ; + end +end + + reg read_count_load; + reg read_count_enable; + + reg [(`PCIR_ADDR_LENGTH - 1):0] max_read_count ; + always@(pci_cache_line_size or cache_lsize_not_zero or pci_tar_cmd) + begin + if (cache_lsize_not_zero) + if ( (pci_cache_line_size >= `PCIR_DEPTH) || (~pci_tar_cmd[1] && ~pci_tar_cmd[0]) ) + // If cache line size is larger than FIFO or BC_MEM_READ_MUL command is performed! + max_read_count = `PCIR_DEPTH - 1'b1; + else + max_read_count = pci_cache_line_size ; + else + max_read_count = 1'b1; + end + + reg [(`PCIR_ADDR_LENGTH - 1):0] read_count ; + + // cache line bound indicator - it signals when data for one complete cacheline was read + wire read_bound_comb = ~|( { read_count[(`PCIR_ADDR_LENGTH - 1):2], read_count[0] } ) ; + + reg read_bound ; + always@(posedge wb_clock_in or posedge reset_in) + begin + if ( reset_in ) + read_bound <= #`FF_DELAY 1'b0 ; + else if (read_count_load) + read_bound <= #`FF_DELAY 1'b0 ; + else if ( read_count_enable ) + read_bound <= #`FF_DELAY read_bound_comb ; + end + + // down counter with load + always@(posedge reset_in or posedge wb_clock_in) + begin + if (reset_in) + read_count <= #`FF_DELAY 0 ; + else + if (read_count_load) + read_count <= #`FF_DELAY max_read_count ; + else + if (read_count_enable) + read_count <= #`FF_DELAY read_count - 1'b1 ; + end + +// Logic used in State Machine logic implemented out of State Machine because of less delay! +// definition of signal telling, when there is last data written into FIFO +always@(pci_tar_cmd or pci_tar_burst_ok or read_bound) +begin + // burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR + // (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok + case ({pci_tar_cmd, pci_tar_burst_ok}) + {`BC_MEM_READ, 1'b1}, + {`BC_MEM_READ_LN, 1'b1} : + begin // when burst cycle + if (read_bound) + last_data_to_pcir_fifo = 1'b1 ; + else + last_data_to_pcir_fifo = 1'b0 ; + end + {`BC_MEM_READ_MUL, 1'b1} : + begin // when burst cycle + if (read_bound) + last_data_to_pcir_fifo = 1'b1 ; + else + last_data_to_pcir_fifo = 1'b0 ; + end + default : + // {`BC_IO_READ, 1'b0}, + // {`BC_IO_READ, 1'b1}, + // {`BC_MEM_READ, 1'b0}, + // {`BC_MEM_READ_LN, 1'b0}, + // {`BC_MEM_READ_MUL, 1'b0}: + begin // when single cycle + last_data_to_pcir_fifo = 1'b1 ; + end + endcase +end + +reg wait_for_wb_response ; + +`ifdef PCI_WBM_NO_RESPONSE_CNT_DISABLE +wire set_retry = 1'b0 ; + +`else +reg [3:0] wb_no_response_cnt ; +reg [3:0] wb_response_value ; +reg set_retry ; // + +// internal WB no response retry generator counter! +always@(posedge reset_in or posedge wb_clock_in) +begin + if (reset_in) + wb_no_response_cnt <= #`FF_DELAY 4'h0 ; + else + wb_no_response_cnt <= #`FF_DELAY wb_response_value ; +end +// internal WB no response retry generator logic +always@(wait_for_wb_response or wb_no_response_cnt) +begin + if (wb_no_response_cnt == 4'h8) // when there isn't response for 8 clocks, set internal retry + begin + wb_response_value = 4'h0 ; + set_retry = 1'b1 ; + end + else + begin + if (wait_for_wb_response) + wb_response_value = wb_no_response_cnt + 1'h1 ; // count clocks when no response + else + wb_response_value = 4'h0 ; + set_retry = 1'b0 ; + end +end +`endif + +wire retry = wb_rty_i || set_retry ; // retry signal - logic OR function between wb_rty_i and internal WB no response retry! +reg [7:0] rty_counter ; // output from retry counter +reg [7:0] rty_counter_in ; // input value - output value + 1 OR output value +reg rty_counter_almost_max_value ; // signal tells when retry counter riches maximum value - 1! +reg reset_rty_cnt ; // signal for asynchronous reset of retry counter after each complete transfere + +// sinchronous signal after each transfere and asynchronous signal 'reset_rty_cnt' after reset +// for reseting the retry counter +always@(posedge reset_in or posedge wb_clock_in) +begin + if (reset_in) + reset_rty_cnt <= #`FF_DELAY 1'b1 ; // asynchronous set when reset signal is active + else + reset_rty_cnt <= #`FF_DELAY wb_ack_i || wb_err_i || last_data_transferred ; // synchronous set after completed transfere +end + +// Retry counter register control +always@(posedge reset_in or posedge wb_clock_in) +begin + if (reset_in) + rty_counter <= #`FF_DELAY 8'h00 ; + else + begin + if (reset_rty_cnt) + rty_counter <= #`FF_DELAY 8'h00 ; + else if (retry) + rty_counter <= #`FF_DELAY rty_counter_in ; + end +end +// Retry counter logic +always@(rty_counter) +begin + if(rty_counter == `WB_RTY_CNT_MAX - 1'b1) // stop counting + begin + rty_counter_in = rty_counter ; + rty_counter_almost_max_value = 1'b1 ; + end + else + begin + rty_counter_in = rty_counter + 1'b1 ; // count up + rty_counter_almost_max_value = 1'b0 ; + end +end + +reg [31:0] addr_cnt_out ; // output value from address counter to WB ADDRESS output +reg [31:0] addr_cnt_in ; // input address value to address counter +reg addr_into_cnt ; // control signal for loading starting address into counter +reg addr_into_cnt_reg ; +reg addr_count ; // control signal for count enable +reg [3:0] bc_register ; // used when error occures during writes! + +// wb address counter register control +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) // reset counter + begin + addr_cnt_out <= #`FF_DELAY 32'h0000_0000 ; + bc_register <= #`FF_DELAY 4'h0 ; + addr_into_cnt_reg <= #`FF_DELAY 1'b0; + end + else + begin + addr_cnt_out <= #`FF_DELAY addr_cnt_in ; // count up or hold value depending on cache line counter logic + addr_into_cnt_reg <= #`FF_DELAY addr_into_cnt; + if (addr_into_cnt) + bc_register <= #`FF_DELAY pciw_fifo_cbe_in ; + end +end + +// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules +wire io_memory_bus_command = !pci_tar_cmd[3] && !pci_tar_cmd[2] ; + +// wb address counter logic +always@(addr_into_cnt or r_attempt or addr_count or pciw_fifo_addr_data_in or pci_tar_address or addr_cnt_out or + io_memory_bus_command) +begin + if (addr_into_cnt) // load starting address into counter + begin + if (r_attempt) + begin // if read request, then load read addresss from PCI Target + addr_cnt_in = {pci_tar_address[31:2], pci_tar_address[1] && io_memory_bus_command, + pci_tar_address[0] && io_memory_bus_command} ; + end + else + begin // if not read request, then load write address from PCIW_FIFO + addr_cnt_in = pciw_fifo_addr_data_in[31:0] ; + end + end + else + if (addr_count) + begin + addr_cnt_in = addr_cnt_out + 3'h4 ; // count up for 32-bit alligned address + end + else + begin + addr_cnt_in = addr_cnt_out ; + end +end + +reg retried ; // Signal is output value from FF and is set for one clock period after retried_d is set +reg retried_d ; // Signal is set whenever cycle is retried and is input to FF for delaying -> used in S_IDLE state +reg retried_write; +reg rty_i_delayed; // Dignal used for determinig the source of retry! + +reg first_data_is_burst ; // Signal is set in S_WRITE or S_READ states, when data transfere is burst! +reg first_data_is_burst_reg ; +wire burst_transfer ; // This signal is set when data transfere is burst and is reset with RESET or last data transfered +reg burst_chopped; // This signal is set when WB_SEL_O is changed during burst write transaction +reg burst_chopped_delayed; + +// FFs output signals tell, when there is first data out from FIFO (for BURST checking) +// and for delaying retried signal +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) // reset signals + begin + retried <= #`FF_DELAY 1'b0 ; + retried_write <= #`FF_DELAY 1'b0 ; + rty_i_delayed <= #`FF_DELAY 1'B0 ; + end + else + begin + retried <= #`FF_DELAY retried_d ; // delaying retried signal + retried_write <= #`FF_DELAY retried ; + rty_i_delayed <= #`FF_DELAY wb_rty_i ; + end +end + +// Determinig if first data is a part of BURST or just a single transfere! +always@(addr_into_cnt or r_attempt or pci_tar_burst_ok or max_read_count or + pciw_fifo_control_in or pciw_fifo_empty_in) +begin + if (addr_into_cnt) + begin + if (r_attempt) + begin + // burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR + // (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00) -> pci_tar_burst_ok + if (pci_tar_burst_ok && (max_read_count != 8'h1)) + first_data_is_burst = 1'b1 ; + else + first_data_is_burst = 1'b0 ; + end + else + begin + first_data_is_burst = 1'b0 ; + end + end + else + first_data_is_burst = pciw_fifo_control_in[`BURST_BIT] && ~pciw_fifo_empty_in && + ~pciw_fifo_control_in[`LAST_CTRL_BIT] /*&& ~pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT]*/; +end + +// FF for seting and reseting burst_transfer signal +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + begin + burst_chopped <= #`FF_DELAY 1'b0; + burst_chopped_delayed <= #`FF_DELAY 1'b0; + first_data_is_burst_reg <= #`FF_DELAY 1'b0 ; + end + else + begin + if (pciw_fifo_transaction_ready_in) + begin + if (pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT]) + burst_chopped <= #`FF_DELAY 1'b1; + else if (wb_ack_i || wb_err_i || wb_rty_i) + burst_chopped <= #`FF_DELAY 1'b0; + end + else + burst_chopped <= #`FF_DELAY 1'b0; + burst_chopped_delayed <= #`FF_DELAY burst_chopped; + if (last_data_transferred || first_data_is_burst) + first_data_is_burst_reg <= #`FF_DELAY ~last_data_transferred ; + end +end +assign burst_transfer = first_data_is_burst || first_data_is_burst_reg ; + +reg [(`WB_FSM_BITS - 1):0] c_state ; //current state register +reg [(`WB_FSM_BITS - 1):0] n_state ; //next state input to current state register + +//################################## +// WISHBONE B3 master state machine +//################################## + +// state machine register control and registered outputs (without wb_adr_o counter) +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) // reset state machine to S_IDLE state + begin + c_state <= #`FF_DELAY S_IDLE; + wb_cyc_o <= #`FF_DELAY 1'b0; + wb_stb_o <= #`FF_DELAY 1'b0; + wb_we_o <= #`FF_DELAY 1'b0; + wb_cti_o <= #`FF_DELAY 3'h2; + wb_bte_o <= #`FF_DELAY 2'h0; + wb_sel_o <= #`FF_DELAY 4'h0; + wb_dat_o <= #`FF_DELAY 32'h0; + pcir_fifo_data_out <= #`FF_DELAY 32'h0; + pcir_fifo_control_out <= #`FF_DELAY 4'h0; + pcir_fifo_wenable_out <= #`FF_DELAY 1'b0; + end + else + begin + c_state <= #`FF_DELAY n_state; + wb_bte_o <= #`FF_DELAY 2'h0; + case (n_state) // synthesis parallel_case full_case + S_WRITE: + begin + wb_cyc_o <= #`FF_DELAY ~addr_into_cnt; + wb_stb_o <= #`FF_DELAY ~addr_into_cnt; + wb_we_o <= #`FF_DELAY ~addr_into_cnt; + // if '1' then next burst BE is not equat to current one => burst is chopped into singles + // OR if last data is going to be transfered + if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && (retried || burst_chopped_delayed))) + begin + if (burst_transfer && ~pciw_fifo_control_in[`DATA_ERROR_CTRL_BIT] && + ~(pciw_fifo_renable_out && (pciw_fifo_control_in[`LAST_CTRL_BIT] || pciw_fifo_almost_empty_in))) + wb_cti_o <= #`FF_DELAY 3'h2; + else + wb_cti_o <= #`FF_DELAY 3'h7; + end + if ((pciw_fifo_renable_out && ~addr_into_cnt) || addr_into_cnt_reg) + begin + wb_sel_o <= #`FF_DELAY ~pciw_fifo_cbe_in; + wb_dat_o <= #`FF_DELAY pciw_fifo_addr_data_in; + end + end + S_WRITE_ERR_RTY: + begin + wb_cyc_o <= #`FF_DELAY 1'b0; + wb_stb_o <= #`FF_DELAY 1'b0; + wb_we_o <= #`FF_DELAY 1'b0; + wb_cti_o <= #`FF_DELAY 3'h2; + // stay the same as previous + //wb_sel_o <= #`FF_DELAY 4'h0; + //wb_dat_o <= #`FF_DELAY 32'h0; + end + S_READ: + begin + wb_cyc_o <= #`FF_DELAY ~addr_into_cnt; + wb_stb_o <= #`FF_DELAY ~addr_into_cnt; + wb_we_o <= #`FF_DELAY 1'b0; + if ((wb_stb_o && wb_ack_i) || addr_into_cnt_reg || (~wb_cyc_o && retried)) + begin + if (burst_transfer && ~read_bound_comb) + wb_cti_o <= #`FF_DELAY 3'h2; + else + wb_cti_o <= #`FF_DELAY 3'h7; + end + if (burst_transfer) + wb_sel_o <= #`FF_DELAY 4'hF; + else + wb_sel_o <= #`FF_DELAY ~pci_tar_be; + // no need to change att all + //wb_dat_o <= #`FF_DELAY 32'h0; + end + S_READ_RTY: + begin + wb_cyc_o <= #`FF_DELAY 1'b0; + wb_stb_o <= #`FF_DELAY 1'b0; + wb_we_o <= #`FF_DELAY 1'b0; + wb_cti_o <= #`FF_DELAY 3'h2; + // no need to change att all + //wb_sel_o <= #`FF_DELAY 4'h0; + //wb_dat_o <= #`FF_DELAY 32'h0; + end + S_TURN_ARROUND: + begin + wb_cyc_o <= #`FF_DELAY 1'b0; + wb_stb_o <= #`FF_DELAY 1'b0; + wb_we_o <= #`FF_DELAY 1'b0; + wb_cti_o <= #`FF_DELAY 3'h2; + // no need to change att all + //wb_sel_o <= #`FF_DELAY 4'h0; + //wb_dat_o <= #`FF_DELAY 32'h0; + end + default: // S_IDLE: + begin + wb_cyc_o <= #`FF_DELAY 1'b0; + wb_stb_o <= #`FF_DELAY 1'b0; + wb_we_o <= #`FF_DELAY 1'b0; + wb_cti_o <= #`FF_DELAY 3'h2; + // no need to change att all + //wb_sel_o <= #`FF_DELAY 4'h0; + //wb_dat_o <= #`FF_DELAY 32'h0; + end + endcase + pcir_fifo_data_out <= #`FF_DELAY wb_dat_i; + pcir_fifo_control_out <= #`FF_DELAY pcir_fifo_control ; + pcir_fifo_wenable_out <= #`FF_DELAY pcir_fifo_wenable ; + end +end + +assign wb_adr_o = addr_cnt_out ; + +// state machine logic +always@(c_state or + wb_ack_i or + wb_rty_i or + wb_err_i or + w_attempt or + r_attempt or + retried or + burst_chopped or + burst_chopped_delayed or + rty_i_delayed or + pci_tar_read_request or + rty_counter_almost_max_value or + set_retry or + last_data_to_pcir_fifo or + first_wb_data_access or + pciw_fifo_control_in or + pciw_fifo_empty_in or + burst_transfer or + last_data_from_pciw_fifo_reg + ) +begin + case (c_state) + S_IDLE: + begin + // Default values for signals not used in this state + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_count = 1'b0 ; + read_count_enable = 1'b0 ; + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + retried_d = 1'b0 ; + last_data_transferred = 1'b0 ; + wb_read_done = 1'b0 ; + wait_for_wb_response = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; + pci_error_sig_out = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + case ({w_attempt, r_attempt, retried}) + 3'b101 : // Write request for PCIW_FIFO to WB bus transaction + begin // If there was retry, the same transaction must be initiated + pciw_fifo_renable = 1'b0 ; // the same data + addr_into_cnt = 1'b0 ; // the same address + read_count_load = 1'b0 ; // no need for cache line when there is write + n_state = S_WRITE ; + end + 3'b100 : // Write request for PCIW_FIFO to WB bus transaction + begin // If there is new transaction + if (burst_chopped_delayed) + begin + addr_into_cnt = 1'b0 ; // address must not be latched into address counter + pciw_fifo_renable = 1'b1 ; // first location is address (in FIFO), next will be data + end + else + begin + if (pciw_fifo_control_in[`ADDR_CTRL_BIT]) + addr_into_cnt = 1'b1 ; // address must be latched into address counter + else + addr_into_cnt = 1'b0 ; + pciw_fifo_renable = 1'b1 ; // first location is address (in FIFO), next will be data + end + read_count_load = 1'b0 ; // no need for cache line when there is write + n_state = S_WRITE ; + end + 3'b011 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction + begin // If there was retry, the same transaction must be initiated + addr_into_cnt = 1'b0 ; // the same address + read_count_load = 1'b0 ; // cache line counter must not be changed for retried read + pciw_fifo_renable = 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO + n_state = S_READ ; + end + 3'b010 : // Read request from PCI Target for WB bus to PCIR_FIFO transaction + begin // If there is new transaction + addr_into_cnt = 1'b1 ; // address must be latched into counter from separate request bus + read_count_load = 1'b1 ; // cache line size must be latched into its counter + pciw_fifo_renable = 1'b0 ; // don't read from FIFO, when read transaction from WB to FIFO + n_state = S_READ ; + end + default : // stay in IDLE state + begin + pciw_fifo_renable = 1'b0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + n_state = S_IDLE ; + end + endcase + end + S_WRITE: // WRITE from PCIW_FIFO to WB bus + begin + // Default values for signals not used in this state + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + read_count_enable = 1'b0 ; + wb_read_done = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + case ({wb_ack_i, wb_err_i, wb_rty_i}) + 3'b100 : // If writting of one data is acknowledged + begin + addr_count = 1'b1 ; // prepare next address if there will be burst + retried_d = 1'b0 ; // there was no retry + pci_error_sig_out = 1'b0 ; // there was no error + error_source_out = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; // there was no retry + wait_for_wb_response = 1'b0 ; + // if last data was transfered ! + if (last_data_from_pciw_fifo_reg) + begin + n_state = S_TURN_ARROUND; + if (~pciw_fifo_empty_in) + pciw_fifo_renable = 1'b0 ; // prepare next value (address when new trans., data when burst tran.) + else + pciw_fifo_renable = 1'b0 ; + last_data_transferred = 1'b1 ; // signal for last data transfered + end + // next burst data has different byte enables ! + else if (burst_transfer && burst_chopped) + begin + n_state = S_IDLE ; + pciw_fifo_renable = 1'b0 ; // next value (address when new trans., data when burst tran.) + last_data_transferred = 1'b0 ; + end + else + begin + n_state = S_WRITE ; + pciw_fifo_renable = 1'b1 ; // prepare next value (address when new trans., data when burst tran.) + last_data_transferred = 1'b0 ; + end + end + 3'b010 : // If writting of one data is terminated with ERROR + begin + if (~pciw_fifo_empty_in) + pciw_fifo_renable = 1'b1 ; // prepare next value (address when new trans., data when cleaning FIFO) + else + pciw_fifo_renable = 1'b0 ; + addr_count = 1'b0 ; // no need for new address + retried_d = 1'b0 ; // there was no retry + last_data_transferred = 1'b1 ; // signal for last data transfered + pci_error_sig_out = 1'b1 ; // segnal for error reporting + error_source_out = 1'b0 ; // error source from other side of WB bus + write_rty_cnt_exp_out = 1'b0 ; // there was no retry + wait_for_wb_response = 1'b0 ; + if (last_data_from_pciw_fifo_reg) // if last data was transfered + n_state = S_TURN_ARROUND ; // go to S_TURN_ARROUND for new transfere + else // if there wasn't last data of transfere + n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO + end + 3'b001 : // If writting of one data is retried + begin + addr_count = 1'b0 ; + last_data_transferred = 1'b0 ; + retried_d = 1'b1 ; // there was a retry + wait_for_wb_response = 1'b0 ; + if(rty_counter_almost_max_value) // If retry counter reached maximum allowed value + begin + if (last_data_from_pciw_fifo_reg) // if last data was transfered + pciw_fifo_renable = 1'b0 ; + else // if there wasn't last data of transfere + pciw_fifo_renable = 1'b1 ; + n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO + write_rty_cnt_exp_out = 1'b1 ; // signal for reporting write counter expired + pci_error_sig_out = 1'b1 ; + error_source_out = 1'b1 ; // error ocuerd because of retry counter + end + else + begin + pciw_fifo_renable = 1'b0 ; + n_state = S_IDLE ; // go to S_IDLE state for retrying the transaction + write_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + end + end + default : + begin + addr_count = 1'b0 ; + last_data_transferred = 1'b0 ; + wait_for_wb_response = 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented) + error_source_out = 1'b0 ; // if error ocures, error source is from other WB bus side + if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value + begin + retried_d = 1'b1 ; + if (last_data_from_pciw_fifo_reg) // if last data was transfered + pciw_fifo_renable = 1'b0 ; + else // if there wasn't last data of transfere + pciw_fifo_renable = 1'b1 ; + n_state = S_WRITE_ERR_RTY ; // go here to clean this write transaction from PCIW_FIFO + write_rty_cnt_exp_out = 1'b1 ; // signal for reporting write counter expired + pci_error_sig_out = 1'b1 ; // signal for error reporting + end + else + begin + pciw_fifo_renable = 1'b0 ; + retried_d = 1'b0 ; + n_state = S_WRITE ; // stay in S_WRITE state to wait WB to response + write_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet + pci_error_sig_out = 1'b0 ; + end + end + endcase + end + S_WRITE_ERR_RTY: // Clean current write transaction from PCIW_FIFO if ERROR or Retry counter expired occures + begin + pciw_fifo_renable = !last_data_from_pciw_fifo_reg ; // put out next data (untill last data or FIFO empty) + last_data_transferred = 1'b1 ; // after exiting this state, negedge of this signal is used + // Default values for signals not used in this state + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + read_count_enable = 1'b0 ; + addr_count = 1'b0 ; + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + retried_d = 1'b0 ; + wb_read_done = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + wait_for_wb_response = 1'b0 ; + // If last data is cleaned out from PCIW_FIFO + if (last_data_from_pciw_fifo_reg) + n_state = S_IDLE ; + else + n_state = S_WRITE_ERR_RTY ; // Clean until last data is cleaned out from FIFO + end + S_READ: // READ from WB bus to PCIR_FIFO + begin + // Default values for signals not used in this state + pciw_fifo_renable = 1'b0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; + case ({wb_ack_i, wb_err_i, wb_rty_i}) + 3'b100 : // If reading of one data is acknowledged + begin + pcir_fifo_wenable = 1'b1 ; // enable writting data into PCIR_FIFO + addr_count = 1'b1 ; // prepare next address if there will be burst + read_count_enable = 1'b1 ; // decrease counter value for cache line size + retried_d = 1'b0 ; // there was no retry + read_rty_cnt_exp_out = 1'b0 ; // there was no retry + wait_for_wb_response = 1'b0 ; + // if last data was transfered + if (last_data_to_pcir_fifo) + begin + pcir_fifo_control[`LAST_CTRL_BIT] = 1'b1 ; // FIFO must indicate LAST data transfered + pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ; + last_data_transferred = 1'b1 ; // signal for last data transfered + wb_read_done = 1'b1 ; // signal last data of read transaction for PCI Target + n_state = S_TURN_ARROUND ; + end + else // if not last data transfered + begin + pcir_fifo_control = 4'h0 ; // ZERO for control code + last_data_transferred = 1'b0 ; // not last data transfered + wb_read_done = 1'b0 ; // read is not done yet + n_state = S_READ ; + end + end + 3'b010 : // If reading of one data is terminated with ERROR + begin + pcir_fifo_wenable = 1'b1 ; // enable for writting to FIFO data with ERROR + addr_count = 1'b0 ; // no need for new address + pcir_fifo_control[`LAST_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ; // FIFO must indicate the DATA with ERROR + pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ; + last_data_transferred = 1'b1 ; // signal for last data transfered + wb_read_done = 1'b1 ; // signal last data of read transaction for PCI Target + read_count_enable = 1'b0 ; // no need for cache line, when error occures + n_state = S_TURN_ARROUND ; + retried_d = 1'b0 ; // there was no retry + wait_for_wb_response = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; // there was no retry + end + 3'b001 : // If reading of one data is retried + begin + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_count = 1'b0 ; + read_count_enable = 1'b0 ; + wait_for_wb_response = 1'b0 ; + case ({first_wb_data_access, rty_counter_almost_max_value}) + 2'b10 : + begin // if first data of the cycle (CYC_O) is retried - after each retry CYC_O goes inactive + n_state = S_IDLE ; // go to S_IDLE state for retrying the transaction + read_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired yet + last_data_transferred = 1'b0 ; + wb_read_done = 1'b0 ; + retried_d = 1'b1 ; // there was a retry + end + 2'b11 : + begin // if retry counter reached maximum value + n_state = S_READ_RTY ; // go here to wait for PCI Target to remove read request + read_rty_cnt_exp_out = 1'b1 ; // signal for reporting read counter expired + last_data_transferred = 1'b0 ; + wb_read_done = 1'b0 ; + retried_d = 1'b1 ; // there was a retry + end + default : // if retry occures after at least 1 data was transferred without breaking cycle (CYC_O inactive) + begin // then PCI device will retry access! + n_state = S_TURN_ARROUND ; // go to S_TURN_ARROUND state + read_rty_cnt_exp_out = 1'b0 ; // retry counter hasn't expired + last_data_transferred = 1'b1 ; + wb_read_done = 1'b1 ; + retried_d = 1'b0 ; // retry must not be retried, since there is not a first data + end + endcase + end + default : + begin + addr_count = 1'b0 ; + read_count_enable = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + wait_for_wb_response = 1'b1 ; // wait for WB device to response (after 8 clocks RTY CNT is incremented) + if((rty_counter_almost_max_value)&&(set_retry)) // when no WB response and RTY CNT reached maximum allowed value + begin + retried_d = 1'b1 ; + n_state = S_TURN_ARROUND ; // go here to stop read request + pcir_fifo_wenable = 1'b1 ; + pcir_fifo_control[`LAST_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b1 ; // FIFO must indicate the DATA with ERROR + pcir_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ; + pcir_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ; + last_data_transferred = 1'b1 ; + wb_read_done = 1'b1 ; + end + else + begin + retried_d = 1'b0 ; + n_state = S_READ ; // stay in S_READ state to wait WB to response + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + last_data_transferred = 1'b0 ; + wb_read_done = 1'b0 ; + end + end + endcase + end + S_READ_RTY: // Wait for PCI Target to remove read request, when retry counter reaches maximum value! + begin + // Default values for signals not used in this state + pciw_fifo_renable = 1'b0 ; + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + read_count_enable = 1'b0 ; + addr_count = 1'b0 ; + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + retried_d = 1'b0 ; + wb_read_done = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + wait_for_wb_response = 1'b0 ; + // wait for PCI Target to remove read request + if (pci_tar_read_request) + begin + n_state = S_READ_RTY ; // stay in this state until read request is removed + last_data_transferred = 1'b0 ; + end + else // when read request is removed + begin + n_state = S_IDLE ; + last_data_transferred = 1'b1 ; // when read request is removed, there is "last" data + end + end + // Turn arround cycle after writting to PCIR_FIFO (for correct data when reading from PCIW_FIFO) + default: // S_TURN_ARROUND: + begin + // Default values for signals not used in this state + pciw_fifo_renable = 1'b0 ; + pcir_fifo_wenable = 1'b0 ; + pcir_fifo_control = 4'h0 ; + addr_into_cnt = 1'b0 ; + read_count_load = 1'b0 ; + read_count_enable = 1'b0 ; + addr_count = 1'b0 ; + pci_error_sig_out = 1'b0 ; + error_source_out = 1'b0 ; + retried_d = 1'b0 ; + last_data_transferred = 1'b1 ; + wb_read_done = 1'b0 ; + write_rty_cnt_exp_out = 1'b0 ; + read_rty_cnt_exp_out = 1'b0 ; + wait_for_wb_response = 1'b0 ; + n_state = S_IDLE ; + end + endcase +end + +// Signal for retry monitor in state machine when there is read and first (or single) data access +wire ack_rty_response = wb_ack_i || wb_rty_i ; + +// Signal first_wb_data_access is set when no WB cycle present till end of first data access of WB cycle on WB bus +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + first_wb_data_access = 1'b1 ; + else + begin + if (~wb_cyc_o) + first_wb_data_access = 1'b1 ; + else if (ack_rty_response) + first_wb_data_access = 1'b0 ; + end +end + +// Signals to FIFO +assign pcir_fifo_be_out = 4'hf ; // pci_tar_be ; + +// Signals to Conf. space +assign pci_error_bc = bc_register ; + + +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + wb_read_done_out <= #`FF_DELAY 1'b0 ; + else + wb_read_done_out <= #`FF_DELAY wb_read_done ; +end + +always@(pciw_fifo_renable or addr_into_cnt_reg or pciw_fifo_control_in or pciw_fifo_empty_in) +begin + pciw_fifo_renable_out = pciw_fifo_renable || addr_into_cnt_reg ; + last_data_from_pciw_fifo_reg = pciw_fifo_control_in[`ADDR_CTRL_BIT] || pciw_fifo_empty_in ; +end + + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave.v new file mode 100644 index 000000000..4e389705d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave.v @@ -0,0 +1,1147 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "wb_slave.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_slave.v,v $ +// Revision 1.5 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.4 2003/12/19 11:11:30 mihad +// Compact PCI Hot Swap support added. +// New testcases added. +// Specification updated. +// Test application changed to support WB B3 cycles. +// +// Revision 1.3 2003/08/14 18:01:53 simons +// ifdefs moved to thier own lines, this confuses some of the tools. +// +// Revision 1.2 2003/08/03 18:05:06 mihad +// Added limited WISHBONE B3 support for WISHBONE Slave Unit. +// Doesn't support full speed bursts yet. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.4 2002/08/19 16:54:25 mihad +// Got rid of undef directives +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:47 mihad +// New project directory structure +// +// + +`include "bus_commands.v" +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_wb_slave + ( wb_clock_in, + reset_in, + wb_hit_in, + wb_conf_hit_in, + wb_map_in, + wb_pref_en_in, + wb_mrl_en_in, + wb_addr_in, + del_bc_in, + wb_del_req_pending_in, + wb_del_comp_pending_in, + pci_drcomp_pending_in, + del_bc_out, + del_req_out, + del_done_out, + del_burst_out, + del_write_out, + del_write_in, + del_error_in, + del_in_progress_out, + ccyc_addr_in, + wb_del_addr_in, + wb_del_be_in, + wb_conf_offset_out, + wb_conf_renable_out, + wb_conf_wenable_out, + wb_conf_be_out, + wb_conf_data_in, + wb_conf_data_out, + wb_data_out, + wb_cbe_out, + wbw_fifo_wenable_out, + wbw_fifo_control_out, + wbw_fifo_almost_full_in, + wbw_fifo_full_in, + wbr_fifo_renable_out, + wbr_fifo_be_in, + wbr_fifo_data_in, + wbr_fifo_control_in, + wbr_fifo_flush_out, + wbr_fifo_empty_in, + pciw_fifo_empty_in, + wbs_lock_in, + init_complete_in, + cache_line_size_not_zero, + sample_address_out, + CYC_I, + STB_I, + WE_I, + SEL_I, + SDATA_I, + SDATA_O, + ACK_O, + RTY_O, + ERR_O, + CAB_I + ); + +/*---------------------------------------------------------------------------------------------------------------------- +Various parameters needed for state machine and other stuff +----------------------------------------------------------------------------------------------------------------------*/ +parameter WBR_SEL = 1'b0 ; +parameter CONF_SEL = 1'b1 ; + +`define FSM_BITS 3 +parameter S_IDLE = `FSM_BITS'h0 ; +parameter S_DEC1 = `FSM_BITS'h1 ; +parameter S_DEC2 = `FSM_BITS'h2 ; +parameter S_START = `FSM_BITS'h3 ; +parameter S_W_ADDR_DATA = `FSM_BITS'h4 ; +parameter S_READ = `FSM_BITS'h5 ; +parameter S_CONF_WRITE = `FSM_BITS'h6 ; +parameter S_CONF_READ = `FSM_BITS'h7 ; + +/*---------------------------------------------------------------------------------------------------------------------- +System signals inputs +wb_clock_in - WISHBONE bus clock input +reset_in - system reset input controlled by bridge's reset logic +----------------------------------------------------------------------------------------------------------------------*/ +input wb_clock_in, reset_in ; + +/*---------------------------------------------------------------------------------------------------------------------- +Inputs from address decoding logic +wb_hit_in - Decoder logic indicates if address is in a range of one of images +wb_conf_hit_in - Decoder logic indicates that address is in configuration space range +wb_map_in - Decoder logic provides information about image mapping - memory mapped image - wb_map_in = 0 + IO space mapped image - wb_map_in = 1 +wb_pref_en_in - Prefetch enable signal from currently selected image - used for PCI bus command usage +wb_addr_in - Address already transalted from WB bus to PCI bus input +wb_mrl_en_in - Memory read line enable input for each image +----------------------------------------------------------------------------------------------------------------------*/ +input [4:0] wb_hit_in ; // hit indicators +input wb_conf_hit_in ; // configuration hit indicator +input [4:0] wb_pref_en_in ; // prefetch enable from all images +input [4:0] wb_mrl_en_in ; // Memory Read line command enable from images +input [4:0] wb_map_in ; // address space mapping indicators - 1 memory space mapping, 0-IO space mapping +input [31:0] wb_addr_in ; // Translated address input + +/*---------------------------------------------------------------------------------------------------------------------- +Delayed transaction control inputs and outputs: +Used for locking particular accesses when delayed transactions are in progress: +wb_del_addr_in - delayed transaction address input - when completion is ready it's used for transaction decoding +wb_del_be_in - delayed transaction byte enable input - when completion is ready it's used for transaction decoding +----------------------------------------------------------------------------------------------------------------------*/ +input [31:0] wb_del_addr_in ; +input [3:0] wb_del_be_in ; + +input [3:0] del_bc_in ; // delayed request bus command used +input wb_del_req_pending_in ; // delayed request pending indicator +input wb_del_comp_pending_in ; // delayed completion pending indicator +input pci_drcomp_pending_in ; // PCI initiated delayed read completion pending + +output [3:0] del_bc_out ; // delayed transaction bus command output + +output del_req_out ; // output for issuing delayed transaction requests + +output del_done_out ; // output indicating current delayed completion finished on WISHBONE bus + +output del_burst_out ; // delayed burst transaction indicator + +output del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation + +output del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write + +input del_write_in ; // indicates that current delayed completion is from a write request +input del_error_in ; // indicate that delayed request terminated with an error - used for write requests + +input [31:0] ccyc_addr_in ; // configuration cycle address input - it's separate from other addresses, since it is stored separately and decoded for type 0 configuration access + +/*---------------------------------------------------------------------------------------------------------------------- +Configuration space access control and data signals +wb_conf_offset_out - lower 12 bits of address input provided for register offset +wb_conf_renable - read enable signal for configuration space accesses +wb_conf_wenable - write enable signal for configuration space accesses +wb_conf_be_out - byte enable signals for configuration space accesses +wb_conf_data_in - data from configuration space +wb_conf_data_in - data provided for configuration space +----------------------------------------------------------------------------------------------------------------------*/ +output [11:0] wb_conf_offset_out ; // register offset output +output wb_conf_renable_out, // configuration read and write enable outputs + wb_conf_wenable_out ; +output [3:0] wb_conf_be_out ; // byte enable outputs for configuration space +input [31:0] wb_conf_data_in ; // configuration data input from configuration space +output [31:0] wb_conf_data_out ; // configuration data output for configuration space + +/*---------------------------------------------------------------------------------------------------------------------- +Data from WISHBONE bus output to interiror of the core: +Data output is used for normal and configuration accesses. +---------------------------------------------------------------------------------------------------------------------*/ +output [31:0] wb_data_out ; + +/*---------------------------------------------------------------------------------------------------------------------- +Bus command - byte enable output - during address phase of image access this bus holds information about PCI +bus command that should be used, during dataphases ( configuration or image access ) this bus contains inverted +SEL_I signals +---------------------------------------------------------------------------------------------------------------------*/ +output [3:0] wb_cbe_out ; + +/*---------------------------------------------------------------------------------------------------------------------- +WBW_FIFO control signals used for sinking data into WBW_FIFO and status monitoring +---------------------------------------------------------------------------------------------------------------------*/ +output wbw_fifo_wenable_out ; // write enable for WBW_FIFO output +output [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO +input wbw_fifo_almost_full_in ; // almost full status indicator from WBW_FIFO +input wbw_fifo_full_in ; // full status indicator from WBW_FIFO + +/*---------------------------------------------------------------------------------------------------------------------- +WBR_FIFO control signals used for fetching data from WBR_FIFO and status monitoring +---------------------------------------------------------------------------------------------------------------------*/ +output wbr_fifo_renable_out ; // WBR_FIFO read enable output +input [3:0] wbr_fifo_be_in ; // byte enable input from WBR_FIFO +input [31:0] wbr_fifo_data_in ; // data input from WBR_FIFO +input [3:0] wbr_fifo_control_in ; // control bus input from WBR_FIFO +output wbr_fifo_flush_out ; // flush signal for WBR_FIFO +input wbr_fifo_empty_in ; // empty status indicator from WBR_FIFO + +// used for transaction ordering requirements - WISHBONE read cannot complete until writes from PCI are completed +input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO + +/*---------------------------------------------------------------------------------------------------------------------- +wbs_lock_in: internal signal that locks out all accesses, except delayed completions or configuration accesses. +( when master operation is disabled via master enable bit in configuration spacei ) +init_complete_in: while initialization sequence is in progress, the state machine +remains in the idle state - it does not respond to accesses. +---------------------------------------------------------------------------------------------------------------------*/ +input wbs_lock_in ; +input init_complete_in ; + +// cache line size register must hold appropriate value to enable read bursts and special commands on PCI bus! +input cache_line_size_not_zero ; + +// state machine signals to wb_addr_mux when to sample wb address input +output sample_address_out ; +reg sample_address_out ; + +/*---------------------------------------------------------------------------------------------------------------------- +WISHBONE bus interface signals - can be connected directly to WISHBONE bus +---------------------------------------------------------------------------------------------------------------------*/ +input CYC_I ; // cycle indicator +input STB_I ; // strobe input - input data is valid when strobe and cycle indicator are high +input WE_I ; // write enable input - 1 - write operation, 0 - read operation +input [3:0] SEL_I ; // Byte select inputs +input [31:0] SDATA_I ; // WISHBONE slave interface input data bus +output [31:0] SDATA_O ; // WISHBONE slave interface output data bus +output ACK_O ; // Acknowledge output - qualifies valid data on data output bus or received data on data input bus +output RTY_O ; // retry output - signals to WISHBONE master that cycle should be terminated and retried later +output ERR_O ; // Signals to WISHBONE master that access resulted in an error +input CAB_I ; // consecutive address burst input - indicates that master will do a serial address transfer in current cycle + +`ifdef REGISTER_WBS_OUTPUTS +reg [31:0] SDATA_O ; +reg ACK_O ; +reg RTY_O ; +reg ERR_O ; + +reg [3:0] del_bc_out ; // delayed transaction bus command output +reg del_req_out ; // output for issuing delayed transaction requests +reg del_done_out ; // output indicating current delayed completion finished on WISHBONE bus +reg del_burst_out ; // delayed burst transaction indicator +reg del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation +reg del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write + +`ifdef HOST +reg wb_conf_wenable_out ; +reg [31:0] wb_conf_data_out ; // configuration data output for configuration space +`endif + +reg [3:0] wb_conf_be_out ; // byte enable outputs for configuration space +reg [31:0] wb_data_out ; + +reg [3:0] wb_cbe_out ; + +reg wbw_fifo_wenable_out ; // write enable for WBW_FIFO output +reg [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO + +reg wbr_fifo_renable_out ; // WBR_FIFO read enable output +`endif + +reg [(`FSM_BITS - 1):0] c_state ; //current state register + +reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register + +// state machine register control +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + c_state <= #`FF_DELAY S_IDLE ; + else + c_state <= #`FF_DELAY n_state ; +end + + +// variable for bus command multiplexer logic output for delayed requests +reg [3:0] del_bc ; + +//register for intermediate data and select storage +reg [35:0] d_incoming ; + +// enable for incoming data register +reg d_incoming_ena ; + +// incoming data register control logic +always@(posedge wb_clock_in or posedge reset_in) +begin + if (reset_in) + d_incoming <= #`FF_DELAY {35{1'b0}} ; + else if (d_incoming_ena) + d_incoming <= #`FF_DELAY {SEL_I, SDATA_I} ; +end + +/*=================================================================================================================================================================================== +Write allow for image accesses. Writes through images are allowed when all of following are true: +- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO +- delayed read from from WISHBONE to PCI request musn't be present +- delayed read from PCI to WISHBONE completion musn't be present +- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled +===================================================================================================================================================================================*/ +wire wimg_wallow = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, wb_del_req_pending_in, pci_drcomp_pending_in, wbs_lock_in } ; +reg img_wallow ; +/*=================================================================================================================================================================================== +WISHBONE slave can request an image read accesses when all of following are true: +- delayed completion is not present +- delayed request is not present +- operation is not locked because of error reporting mechanism or because PCI master is disabled +===================================================================================================================================================================================*/ +wire wdo_del_request = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ; +reg do_del_request ; +/*=================================================================================================================================================================================== +WISHBONE slave can complete an image read accesses when all of following are true: +- delayed read completion is present +- delayed read completion is the same as current read access ( dread_completion_hit is 1 ) +- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO +- WBR_FIFO empty status is not active +===================================================================================================================================================================================*/ +wire wdel_addr_hit = ( wb_del_addr_in == wb_addr_in ) && ( SEL_I == wb_del_be_in ) ; +reg del_addr_hit ; +wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ; +reg del_completion_allow ; + +/*---------------------------------------------------------------------------------------------------------------------- +img_hit - state of wb_hit_in bus when when state machine signals decode is over +---------------------------------------------------------------------------------------------------------------------*/ +reg [4:0] img_hit ; +wire wb_hit = |( img_hit ) ; + +/*---------------------------------------------------------------------------------------------------------------------- +Control logic for image control signals +pref_en - prefetch enable of currently selected image +mrl_en - Memory read line enable of currently selected image +map - Address space mapping for currently selected image +---------------------------------------------------------------------------------------------------------------------*/ +reg pref_en, mrl_en, map ; +wire wpref_en = |(wb_pref_en_in & wb_hit_in) ; +wire wmrl_en = |(wb_mrl_en_in & wb_hit_in) ; +wire wmap = |(wb_map_in & wb_hit_in) ; + +// state machine controls when results from decoders, comparison etc. are sampled into registers to decode an access +reg decode_en ; + +reg wb_conf_hit ; +always@(posedge reset_in or posedge wb_clock_in) +begin + if (reset_in) + begin + img_wallow <= #`FF_DELAY 1'b0 ; + wb_conf_hit <= #`FF_DELAY 1'b0 ; + do_del_request <= #`FF_DELAY 1'b0 ; + del_addr_hit <= #`FF_DELAY 1'b0 ; + del_completion_allow <= #`FF_DELAY 1'b0 ; + img_hit <= #`FF_DELAY 5'h00 ; + pref_en <= #`FF_DELAY 1'b0 ; + mrl_en <= #`FF_DELAY 1'b0 ; + map <= #`FF_DELAY 1'b0 ; + end + else + if (decode_en) + begin + img_wallow <= #`FF_DELAY wimg_wallow ; + wb_conf_hit <= #`FF_DELAY wb_conf_hit_in ; + do_del_request <= #`FF_DELAY wdo_del_request ; + del_addr_hit <= #`FF_DELAY wdel_addr_hit ; + del_completion_allow <= #`FF_DELAY wdel_completion_allow ; + img_hit <= #`FF_DELAY wb_hit_in ; + pref_en <= #`FF_DELAY wpref_en && cache_line_size_not_zero ; + mrl_en <= #`FF_DELAY wmrl_en && cache_line_size_not_zero ; + map <= #`FF_DELAY wmap ; + end +end + +wire del_burst = CAB_I && (pref_en || mrl_en) && ~WE_I && cache_line_size_not_zero ; // delayed burst indicator - only when WB master attempts CAB transfer and cache line size register is set appropriately and + // either prefetch enable or memory read line enable of corresponding image are set - + // applies for reads only - delayed write cannot be a burst +wire do_dread_completion = del_completion_allow && del_addr_hit ; + +`ifdef GUEST + + // wires indicating allowance for configuration cycle generation requests + wire do_ccyc_req = 1'b0 ; + wire do_ccyc_comp = 1'b0 ; + + // wires indicating allowance for interrupt acknowledge cycle generation requests + wire do_iack_req = 1'b0 ; + wire do_iack_comp = 1'b0 ; + + // variables for configuration access control signals + reg conf_wenable ; + assign wb_conf_wenable_out = 1'b0 ; + + // configuration cycle data register hit + wire ccyc_hit = 1'b0 ; + wire iack_hit = 1'b0 ; + + wire wccyc_hit = 1'b0 ; + wire wiack_hit = 1'b0 ; + +`else +`ifdef HOST + // only host implementation has access for generating interrupt acknowledge and configuration cycles + // configuration cycle data register hit + reg current_delayed_is_ccyc ; + reg current_delayed_is_iack ; + + wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) ; + + wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR}) ; + + reg iack_hit ; + reg ccyc_hit ; + always@(posedge reset_in or posedge wb_clock_in) + begin + if (reset_in) + begin + ccyc_hit <= #`FF_DELAY 1'b0 ; + iack_hit <= #`FF_DELAY 1'b0 ; + end + else + if (decode_en) + begin + ccyc_hit <= #`FF_DELAY wccyc_hit ; + iack_hit <= #`FF_DELAY wiack_hit ; + end + end + + // wires indicating allowance for configuration cycle generation requests + wire do_ccyc_req = do_del_request && ccyc_hit; + wire do_ccyc_comp = del_completion_allow && ccyc_hit && current_delayed_is_ccyc ; // && del_bc_hit + + // wires indicating allowance for interrupt acknowledge cycle generation requests + wire do_iack_req = do_del_request && iack_hit ; + wire do_iack_comp = del_completion_allow && iack_hit && current_delayed_is_iack ; // && del_bc_hit + + // variables for configuration access control signals + reg conf_wenable ; + + // following flip-flops remember whether current delayed transaction is interrupt acknowledge or configuration cycle transaction + always@(posedge wb_clock_in or posedge reset_in) + begin + if ( reset_in ) + begin + current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ; + current_delayed_is_iack <= #`FF_DELAY 1'b0 ; + end + else + if ( del_done_out ) + begin + current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ; + current_delayed_is_iack <= #`FF_DELAY 1'b0 ; + end + else + if ( del_req_out && wb_conf_hit ) + begin + current_delayed_is_ccyc <= #`FF_DELAY do_ccyc_req ; + current_delayed_is_iack <= #`FF_DELAY do_iack_req ; + end + end + +`endif +`endif + +// configuration read enable - supplied for host and guest bridges +reg conf_renable ; +assign wb_conf_renable_out = conf_renable ; + +// burst access indicator +wire burst_transfer = CYC_I && CAB_I ; + +// WBW_FIFO control output +reg [3:0] wbw_fifo_control ; + +// WBW_FIFO wenable output assignment +reg wbw_fifo_wenable ; + +// WBR_FIFO control outputs +reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs + +// flush signal for WBR_FIFO must be registered, since it asinchronously resets some status registers +wire wbr_fifo_flush_reg ; +pci_async_reset_flop async_reset_as_wbr_flush +( + .data_in (wbr_fifo_flush), + .clk_in (wb_clock_in), + .async_reset_data_out (wbr_fifo_flush_reg), + .reset_in (reset_in) +) ; +assign wbr_fifo_flush_out = wbr_fifo_flush_reg ; + +// delayed transaction request control signals +reg del_req, del_done ; + +// WISHBONE handshaking control outputs +reg ack, rty, err ; + +`ifdef REGISTER_WBS_OUTPUTS +// wire for write attempt - 1 when external WB master is attempting a write +// wire for read attempt - 1 when external master is attempting a read +wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ; +wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ; + +`else +// wire for write attempt - 1 when external WB master is attempting a write +// wire for read attempt - 1 when external master is attempting a read +wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high +wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low + +`endif +/*---------------------------------------------------------------------------------------------------------------------- +Delayed transaction bus command generation +Bus command for delayed reads depends on image's address space mapping and control bits and +whether or not these are interrupt acknowledge requests or configuration cycle requests +---------------------------------------------------------------------------------------------------------------------*/ + +always@(map or mrl_en or ccyc_hit or WE_I or wb_conf_hit or CAB_I or pref_en) +begin +`ifdef HOST +// only host implementation supports configuration and interrupt acknowledge commands + if (wb_conf_hit) + begin + case( {ccyc_hit, WE_I} ) + 2'b11: del_bc = `BC_CONF_WRITE ; + 2'b10: del_bc = `BC_CONF_READ ; + 2'b01: del_bc = `BC_RESERVED0 ; // invalid combination - interrupt acknowledge cycle must be a read + 2'b00: del_bc = `BC_IACK ; + endcase + end + else +`endif + begin + if ( map ) + begin + del_bc = `BC_IO_READ ; + end + else + begin + case ({(CAB_I && mrl_en), pref_en}) + 2'b00: del_bc = `BC_MEM_READ ; // if this is not burst transfer or memory read line command is disabled - use memory read + 2'b01: del_bc = `BC_MEM_READ ; // same as previous case + 2'b10: del_bc = `BC_MEM_READ_LN ; // burst transfer, memory read line command enabled, prefetch disabled - use memory read line command + 2'b11: del_bc = `BC_MEM_READ_MUL ; // same as previous case, except prefetch is enabled - use memory read multiple command + endcase + end + end +end + +reg del_in_progress ; // state machine indicates whether current read completion is in progress on WISHBONE bus + +wire image_access_error = (map && burst_transfer) ; // IO write is a burst + +`ifdef HOST + reg [1:0] wbw_data_out_sel ; + parameter SEL_ADDR_IN = 2'b10 ; + parameter SEL_CCYC_ADDR = 2'b11 ; + parameter SEL_DATA_IN = 2'b00 ; +`else +`ifdef GUEST + reg wbw_data_out_sel ; + parameter SEL_ADDR_IN = 1'b1 ; + parameter SEL_DATA_IN = 1'b0 ; +`endif +`endif + +`ifdef WB_DECODE_FAST + `ifdef REGISTER_WBS_OUTPUTS + `define PCI_WB_SLAVE_S_DEC1 + `endif +`endif + +`ifdef WB_DECODE_MEDIUM + `define PCI_WB_SLAVE_S_DEC1 +`endif + +`ifdef WB_DECODE_SLOW + `define PCI_WB_SLAVE_S_DEC1 + `define PCI_WB_SLAVE_S_DEC2 +`endif +// state machine logic +always@( + c_state or + wattempt or + img_wallow or + burst_transfer or + wb_hit or + map or + rattempt or + do_dread_completion or + wbr_fifo_control_in or + wb_conf_hit or + do_ccyc_req or + do_ccyc_comp or + ccyc_hit or + del_error_in or + do_iack_req or + do_iack_comp or + iack_hit or + image_access_error or + wbw_fifo_almost_full_in or + wbw_fifo_full_in or + do_del_request or + wbr_fifo_empty_in or + init_complete_in + ) +begin + // default signal values + // response signals inactive + ack = 1'b0 ; + rty = 1'b0 ; + err = 1'b0 ; + + //write signals inactive + wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b1 ; + wbw_fifo_control[`DATA_ERROR_CTRL_BIT] = 1'b0 ; + wbw_fifo_control[`LAST_CTRL_BIT] = 1'b0 ; + wbw_fifo_control[`UNUSED_CTRL_BIT] = 1'b0 ; + + wbw_fifo_wenable = 1'b0 ; + d_incoming_ena = 1'b0 ; + + // read signals inactive + wbr_fifo_flush = 1'b0 ; + wbr_fifo_renable = 1'b0 ; + del_req = 1'b0 ; + del_done = 1'b0 ; + + // configuration space control signals inactive + conf_wenable = 1'b0 ; + conf_renable = 1'b0 ; + + // read is not in progress + del_in_progress = 1'b0 ; + + decode_en = 1'b0 ; + + wbw_data_out_sel = SEL_ADDR_IN ; + + sample_address_out = 1'b0 ; + + case (c_state) + S_IDLE: begin + if ( (wattempt || rattempt) & init_complete_in ) + begin + + `ifdef PCI_WB_SLAVE_S_DEC1 + n_state = S_DEC1 ; + `else + decode_en = 1'b1 ; + n_state = S_START ; + `endif + + sample_address_out = 1'b1 ; + end + else + n_state = S_IDLE ; + end +`ifdef PCI_WB_SLAVE_S_DEC1 + S_DEC1: begin + if ( wattempt || rattempt ) + begin + + `ifdef PCI_WB_SLAVE_S_DEC2 + n_state = S_DEC2 ; + `else + decode_en = 1'b1 ; + n_state = S_START ; + `endif + + end + else + n_state = S_IDLE ; + end +`endif +`ifdef PCI_WB_SLAVE_S_DEC2 + S_DEC2: begin + + if ( wattempt || rattempt ) + begin + decode_en = 1'b1 ; + n_state = S_START ; + end + else + n_state = S_IDLE ; + end +`endif + S_START:begin + if (wb_conf_hit) // configuration space hit + begin + `ifdef HOST + wbw_data_out_sel = SEL_CCYC_ADDR ; + `endif + + if ( wattempt ) + n_state = S_CONF_WRITE ; // go to conf. write state + else + if ( rattempt ) + begin + n_state = S_CONF_READ ; // go to conf. read state + end + else + n_state = S_IDLE ; // master terminated - go back to idle state + + end // wb_conf_hit + else + if( wb_hit && (wattempt || rattempt) ) + begin + wbw_data_out_sel = SEL_DATA_IN ; + + // check error conditions for image writes or reads + if ( image_access_error ) + begin + n_state = S_IDLE ; // go back to idle state because of an error condition + err = 1'b1 ; + end // error conditions + else + // check for retry conditions for image writes or reads + if ( (wattempt && ~img_wallow) || + (rattempt && ~do_dread_completion) // write to image not allowed, no read ready yet - retry + ) + begin + n_state = S_IDLE ; // go back to IDLE + + rty = 1'b1 ; + + del_req = do_del_request && rattempt ; + + end //retry + else // everything OK - proceed + if ( wattempt ) + begin + n_state = S_W_ADDR_DATA ; // goto write transfer state + + // respond with acknowledge + ack = 1'b1 ; + + wbw_fifo_wenable = 1'b1 ; + + // data is latched to data incoming intermidiate stage - it will be put in FIFO later + d_incoming_ena = 1'b1 ; + end + else + begin + err = wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ; + ack = ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] ; + wbr_fifo_renable = 1'b1 ; + del_in_progress = 1'b1 ; + + if ( wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT] ) + begin + + n_state = S_IDLE ; // go back to idle state + // respond that read is finished + del_done = 1'b1 ; + + end // end read + else + n_state = S_READ ; // go to read state + end + end + else + n_state = S_IDLE ; + + end + + S_W_ADDR_DATA: begin + wbw_data_out_sel = SEL_DATA_IN ; + err = 1'b0 ; + rty = burst_transfer && wattempt && (wbw_fifo_almost_full_in || wbw_fifo_full_in) ; + + if ( ~burst_transfer || wattempt && ( wbw_fifo_almost_full_in || wbw_fifo_full_in ) ) + begin + n_state = S_IDLE ; + + // write last data to FIFO and don't latch new data + wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ; + wbw_fifo_control[`LAST_CTRL_BIT] = 1'b1 ; + wbw_fifo_wenable = 1'b1 ; + end + else + begin + n_state = S_W_ADDR_DATA ; + wbw_fifo_control[`ADDR_CTRL_BIT] = 1'b0 ; + wbw_fifo_control[`LAST_CTRL_BIT] = 1'b0 ; + ack = wattempt ; + wbw_fifo_wenable = wattempt ; + d_incoming_ena = wattempt ; + end + end // S_W_ADDR_DATA + + S_READ:begin + // this state is for reads only - in this state read is in progress all the time + del_in_progress = 1'b1 ; + + ack = burst_transfer && rattempt && ~wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ; + err = burst_transfer && rattempt && wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] && ~wbr_fifo_empty_in ; + + // if acknowledge is beeing signalled then enable read from wbr fifo + wbr_fifo_renable = burst_transfer && rattempt && ~wbr_fifo_empty_in ; + + if ( ~burst_transfer || rattempt && (wbr_fifo_empty_in || wbr_fifo_control_in[`DATA_ERROR_CTRL_BIT] || wbr_fifo_control_in[`LAST_CTRL_BIT]) ) + begin + n_state = S_IDLE ; + del_done = 1'b1 ; + wbr_fifo_flush = ~wbr_fifo_empty_in ; + end + else + begin + n_state = S_READ ; + end + end // S_READ + + S_CONF_WRITE: begin + `ifdef HOST + wbw_data_out_sel = SEL_CCYC_ADDR ; + del_req = do_ccyc_req && ~burst_transfer ; + del_done = do_ccyc_comp && ~burst_transfer ; + del_in_progress = do_ccyc_comp && ~burst_transfer ; + `endif + + n_state = S_IDLE ; // next state after configuration access is always idle + + if ( burst_transfer ) + begin + err = 1'b1 ; + end + else + begin + `ifdef HOST + if ( do_ccyc_req || (ccyc_hit && ~do_ccyc_comp)) + begin + rty = 1'b1 ; + end + else + if ( do_ccyc_comp ) + begin + err = del_error_in ; + ack = ~del_error_in ; + end + else + begin + ack = ~ccyc_hit ; + conf_wenable = ~ccyc_hit ; + end + `else + ack = 1'b1 ; + conf_wenable = 1'b1 ; + `endif + end + end // S_CONF_WRITE + + S_CONF_READ: begin + `ifdef HOST + wbw_data_out_sel = SEL_CCYC_ADDR ; + del_req = ~burst_transfer && ( do_ccyc_req || do_iack_req ) ; + del_done = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ; + del_in_progress = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ; + wbr_fifo_renable = ~burst_transfer && ( do_ccyc_comp || do_iack_comp ) ; + `endif + + n_state = S_IDLE ; // next state after configuration access is always idle + + if ( burst_transfer ) + begin + err = 1'b1 ; + end + else + begin + `ifdef HOST + if ( do_ccyc_req || ( ccyc_hit && ~do_ccyc_comp )) + begin + rty = 1'b1 ; + end + else + if ( do_iack_req || ( iack_hit && ~do_iack_comp )) + begin + rty = 1'b1 ; + end + else + if ( do_iack_comp || do_ccyc_comp ) + begin + err = del_error_in ; + ack = ~del_error_in ; + end + else + begin + ack = ~( ccyc_hit || iack_hit ) ; + conf_renable = ~( ccyc_hit || iack_hit ) ; + end + `else + ack = 1'b1 ; + conf_renable = 1'b1 ; + `endif + end + end //S_CONF_READ + default:begin + n_state = S_IDLE ; // return to idle state + end //default + endcase +end + +// configuration space offset output assignment +assign wb_conf_offset_out = {wb_addr_in[11:2], 2'b00} ; // upper 10 bits of address input and two zeros + +// data output assignment - for image writes, first data is address, subsequent data comes from intermediate register +reg [31:0] wb_data ; +`ifdef HOST +reg [1:0] wbw_data_out_sel_reg ; +always@(posedge wb_clock_in or posedge reset_in) +begin + if ( reset_in ) + wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ; + else + wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ; +end + +always@(wbw_data_out_sel_reg or wb_addr_in or ccyc_addr_in or d_incoming) +begin + case ( wbw_data_out_sel_reg ) + SEL_CCYC_ADDR: wb_data = ccyc_addr_in ; + SEL_DATA_IN: wb_data = d_incoming ; + default: wb_data = wb_addr_in ; + endcase +end +`else +`ifdef GUEST +reg wbw_data_out_sel_reg ; +always@(posedge wb_clock_in or posedge reset_in) +begin + if ( reset_in ) + wbw_data_out_sel_reg <= #`FF_DELAY SEL_ADDR_IN ; + else + wbw_data_out_sel_reg <= #`FF_DELAY wbw_data_out_sel ; +end + +always@(wbw_data_out_sel_reg or wb_addr_in or d_incoming) +begin + if ( wbw_data_out_sel_reg ) + wb_data = wb_addr_in ; + else + wb_data = d_incoming ; +end +`endif +`endif + +// command / byte enable assignment - with address, bus command is provided, with data - byte enables are provided +reg [3:0] wb_cbe ; + +always@(wbw_data_out_sel_reg or d_incoming or map) +begin + if (wbw_data_out_sel_reg && map) + wb_cbe = `BC_IO_WRITE ; + else + if (wbw_data_out_sel_reg) + wb_cbe = `BC_MEM_WRITE ; + else + wb_cbe = ~(d_incoming[35:32]) ; +end + +// for configuration writes, data output is always data from WISHBONE - in guest implementation data is all 0. +`ifdef GUEST + assign wb_conf_data_out = 32'h00000000 ; +`endif + +`ifdef GUEST + `ifdef NO_CNF_IMAGE + `else + `define PCI_WB_SLAVE_DO_OUT_MUX + `endif +`else +`ifdef HOST + `define PCI_WB_SLAVE_DO_OUT_MUX ; +`endif +`endif + +`ifdef PCI_WB_SLAVE_DO_OUT_MUX + reg [31:0] sdata_source ; + + // WISHBONE data output select lines for output multiplexor + wire sdata_o_sel_new = ( wb_conf_hit_in && ~wiack_hit && ~wccyc_hit ) ? CONF_SEL : WBR_SEL ; + reg sdata_o_sel ; + + always@(posedge wb_clock_in or posedge reset_in) + begin + if ( reset_in ) + sdata_o_sel <= #`FF_DELAY WBR_SEL ; + else + if ( decode_en ) + sdata_o_sel <= #`FF_DELAY sdata_o_sel_new ; + end + + always@(sdata_o_sel or wbr_fifo_data_in or wb_conf_data_in) + begin + case (sdata_o_sel) + WBR_SEL :sdata_source = wbr_fifo_data_in ; + CONF_SEL:sdata_source = wb_conf_data_in ; + endcase + end +`else + wire [31:0] sdata_source = wbr_fifo_data_in ; +`endif + +`ifdef REGISTER_WBS_OUTPUTS + +always@(posedge wb_clock_in or posedge reset_in) +begin + if ( reset_in ) + begin + ACK_O <= #`FF_DELAY 1'b0 ; + RTY_O <= #`FF_DELAY 1'b0 ; + ERR_O <= #`FF_DELAY 1'b0 ; + SDATA_O <= #`FF_DELAY 0 ; + del_write_out <= #`FF_DELAY 1'b0 ; + + `ifdef HOST + wb_conf_wenable_out <= #`FF_DELAY 1'b0 ; + wb_conf_data_out <= #`FF_DELAY 0 ; + `endif + + del_bc_out <= #`FF_DELAY `BC_RESERVED0 ; + del_req_out <= #`FF_DELAY 1'b0 ; + del_done_out <= #`FF_DELAY 1'b0 ; + del_burst_out <= #`FF_DELAY 1'b0 ; + del_in_progress_out <= #`FF_DELAY 1'b0 ; + wb_conf_be_out <= #`FF_DELAY 0 ; + wb_data_out <= #`FF_DELAY 0 ; + wb_cbe_out <= #`FF_DELAY 0 ; + wbw_fifo_wenable_out <= #`FF_DELAY 0 ; + wbw_fifo_control_out <= #`FF_DELAY 0 ; + wbr_fifo_renable_out <= #`FF_DELAY 0 ; + end + else + begin + ACK_O <= #`FF_DELAY ack && !ACK_O ; + RTY_O <= #`FF_DELAY rty && !RTY_O ; + ERR_O <= #`FF_DELAY err && !ERR_O ; + SDATA_O <= #`FF_DELAY sdata_source ; + del_write_out <= #`FF_DELAY WE_I ; + + `ifdef HOST + wb_conf_wenable_out <= #`FF_DELAY conf_wenable ; + wb_conf_data_out <= #`FF_DELAY SDATA_I ; + `endif + + del_bc_out <= #`FF_DELAY del_bc ; + del_req_out <= #`FF_DELAY del_req ; + del_done_out <= #`FF_DELAY del_done ; + del_burst_out <= #`FF_DELAY del_burst ; + del_in_progress_out <= #`FF_DELAY del_in_progress ; + wb_conf_be_out <= #`FF_DELAY SEL_I ; + wb_data_out <= #`FF_DELAY wb_data ; + wb_cbe_out <= #`FF_DELAY wb_cbe ; + wbw_fifo_wenable_out <= #`FF_DELAY wbw_fifo_wenable ; + wbw_fifo_control_out <= #`FF_DELAY wbw_fifo_control ; + wbr_fifo_renable_out <= #`FF_DELAY wbr_fifo_renable ; + end +end + +`else + +assign SDATA_O = sdata_source ; + +assign ACK_O = ack ; +assign RTY_O = rty ; +assign ERR_O = err ; + +// write operation indicator for delayed transaction requests +assign del_write_out = WE_I ; +assign del_bc_out = del_bc ; +assign del_req_out = del_req ; // read request +assign del_done_out = del_done ; // read done +assign del_burst_out = del_burst ; +assign del_in_progress_out = del_in_progress ; +`ifdef HOST +assign wb_conf_data_out = SDATA_I ; +assign wb_conf_wenable_out = conf_wenable ; +`endif +// Configuration space byte enables output +assign wb_conf_be_out = SEL_I ; // just route select lines from WISHBONE to conf space +assign wb_data_out = wb_data ; +assign wb_cbe_out = wb_cbe ; +assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO +assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO +assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo +`endif + +endmodule //WB_SLAVE diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave_unit.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave_unit.v new file mode 100644 index 000000000..cdba5b986 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_slave_unit.v @@ -0,0 +1,876 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "wb_slave_unit.v" //// +//// //// +//// This file is part of the "PCI bridge" project //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_slave_unit.v,v $ +// Revision 1.3 2004/01/24 11:54:18 mihad +// Update! SPOCI Implemented! +// +// Revision 1.2 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.8 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.7 2002/10/17 22:49:22 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.6 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.5 2002/10/08 17:17:06 mihad +// Added BIST signals for RAMs. +// +// Revision 1.4 2002/09/25 15:53:52 mihad +// Removed all logic from asynchronous reset network +// +// Revision 1.3 2002/02/01 15:25:13 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.2 2001/10/05 08:14:30 mihad +// Updated all files with inclusion of timescale file for simulation purposes. +// +// Revision 1.1.1.1 2001/10/02 15:33:46 mihad +// New project directory structure +// +// + +// Module instantiates and connects other modules lower in hierarcy +// Wishbone slave unit consists of modules that together form datapath +// between external WISHBONE masters and external PCI targets +`include "pci_constants.v" + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module pci_wb_slave_unit +( + reset_in, + wb_clock_in, + pci_clock_in, + ADDR_I, + SDATA_I, + SDATA_O, + CYC_I, + STB_I, + WE_I, + SEL_I, + ACK_O, + RTY_O, + ERR_O, + CAB_I, + wbu_map_in, + wbu_pref_en_in, + wbu_mrl_en_in, + wbu_pci_drcomp_pending_in, + wbu_conf_data_in, + wbu_pciw_empty_in, + wbu_bar0_in, + wbu_bar1_in, + wbu_bar2_in, + wbu_bar3_in, + wbu_bar4_in, + wbu_bar5_in, + wbu_am0_in, + wbu_am1_in, + wbu_am2_in, + wbu_am3_in, + wbu_am4_in, + wbu_am5_in, + wbu_ta0_in, + wbu_ta1_in, + wbu_ta2_in, + wbu_ta3_in, + wbu_ta4_in, + wbu_ta5_in, + wbu_at_en_in, + wbu_ccyc_addr_in , + wbu_master_enable_in, + wb_init_complete_in, + wbu_cache_line_size_not_zero, + wbu_cache_line_size_in, + wbu_pciif_gnt_in, + wbu_pciif_frame_in, + wbu_pciif_irdy_in, + wbu_pciif_trdy_in, + wbu_pciif_trdy_reg_in, + wbu_pciif_stop_in, + wbu_pciif_stop_reg_in, + wbu_pciif_devsel_in, + wbu_pciif_devsel_reg_in, + wbu_pciif_ad_reg_in, + wbu_pciif_req_out, + wbu_pciif_frame_out, + wbu_pciif_frame_en_out, + wbu_pciif_frame_en_in, + wbu_pciif_frame_out_in, + wbu_pciif_frame_load_out, + wbu_pciif_irdy_out, + wbu_pciif_irdy_en_out, + wbu_pciif_ad_out, + wbu_pciif_ad_en_out, + wbu_pciif_cbe_out, + wbu_pciif_cbe_en_out, + wbu_err_addr_out, + wbu_err_bc_out, + wbu_err_signal_out, + wbu_err_source_out, + wbu_err_rty_exp_out, + wbu_tabort_rec_out, + wbu_mabort_rec_out, + wbu_conf_offset_out, + wbu_conf_renable_out, + wbu_conf_wenable_out, + wbu_conf_be_out, + wbu_conf_data_out, + wbu_del_read_comp_pending_out, + wbu_wbw_fifo_empty_out, + wbu_latency_tim_val_in, + wbu_ad_load_out, + wbu_ad_load_on_transfer_out + +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif +); + +input reset_in, + wb_clock_in, + pci_clock_in ; + +input [31:0] ADDR_I ; +input [31:0] SDATA_I ; +output [31:0] SDATA_O ; +input CYC_I ; +input STB_I ; +input WE_I ; +input [3:0] SEL_I ; +output ACK_O ; +output RTY_O ; +output ERR_O ; +input CAB_I ; + +input [5:0] wbu_map_in ; +input [5:0] wbu_pref_en_in ; +input [5:0] wbu_mrl_en_in ; + +input wbu_pci_drcomp_pending_in ; + +input [31:0] wbu_conf_data_in ; + +input wbu_pciw_empty_in ; + +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in ; +input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in ; +input [5:0] wbu_at_en_in ; + +input [23:0] wbu_ccyc_addr_in ; + +input wbu_master_enable_in ; +input wb_init_complete_in ; + +input wbu_cache_line_size_not_zero ; +input [7:0] wbu_cache_line_size_in ; + +input wbu_pciif_gnt_in ; +input wbu_pciif_frame_in ; +input wbu_pciif_frame_en_in ; +input wbu_pciif_irdy_in ; +input wbu_pciif_trdy_in; +input wbu_pciif_trdy_reg_in; +input wbu_pciif_stop_in ; +input wbu_pciif_stop_reg_in ; +input wbu_pciif_devsel_in ; +input wbu_pciif_devsel_reg_in ; +input [31:0] wbu_pciif_ad_reg_in ; + +output wbu_pciif_req_out ; +output wbu_pciif_frame_out ; +output wbu_pciif_frame_en_out ; +input wbu_pciif_frame_out_in ; +output wbu_pciif_frame_load_out ; +output wbu_pciif_irdy_out ; +output wbu_pciif_irdy_en_out ; +output [31:0] wbu_pciif_ad_out ; +output wbu_pciif_ad_en_out ; +output [3:0] wbu_pciif_cbe_out ; +output wbu_pciif_cbe_en_out ; + +output [31:0] wbu_err_addr_out ; +output [3:0] wbu_err_bc_out ; +output wbu_err_signal_out ; +output wbu_err_source_out ; +output wbu_err_rty_exp_out ; +output wbu_tabort_rec_out ; +output wbu_mabort_rec_out ; + +output [11:0] wbu_conf_offset_out ; +output wbu_conf_renable_out ; +output wbu_conf_wenable_out ; +output [3:0] wbu_conf_be_out ; +output [31:0] wbu_conf_data_out ; + +output wbu_del_read_comp_pending_out ; +output wbu_wbw_fifo_empty_out ; + +input [7:0] wbu_latency_tim_val_in ; + +output wbu_ad_load_out ; +output wbu_ad_load_on_transfer_out ; + +`ifdef PCI_BIST +/*----------------------------------------------------- +BIST debug chain port signals +-----------------------------------------------------*/ +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +// pci master interface outputs +wire [31:0] pcim_if_address_out ; +wire [3:0] pcim_if_bc_out ; +wire [31:0] pcim_if_data_out ; +wire [3:0] pcim_if_be_out ; +wire pcim_if_req_out ; +wire pcim_if_rdy_out ; +wire pcim_if_last_out ; +wire pcim_if_wbw_renable_out ; +wire pcim_if_wbr_wenable_out ; +wire [31:0] pcim_if_wbr_data_out ; +wire [3:0] pcim_if_wbr_be_out ; +wire [3:0] pcim_if_wbr_control_out ; +wire pcim_if_del_complete_out ; +wire pcim_if_del_error_out ; +wire pcim_if_del_rty_exp_out ; +wire [31:0] pcim_if_err_addr_out ; +wire [3:0] pcim_if_err_bc_out ; +wire pcim_if_err_signal_out ; +wire pcim_if_err_source_out ; +wire pcim_if_err_rty_exp_out ; +wire pcim_if_tabort_out ; +wire pcim_if_mabort_out ; +wire [31:0] pcim_if_next_data_out ; +wire [3:0] pcim_if_next_be_out ; +wire pcim_if_next_last_out ; +wire pcim_if_posted_write_not_present_out ; + + + +wire pcim_sm_req_out ; +wire pcim_sm_frame_out ; +wire pcim_sm_frame_en_out ; +wire pcim_sm_irdy_out ; +wire pcim_sm_irdy_en_out ; +wire [31:0] pcim_sm_ad_out ; +wire pcim_sm_ad_en_out ; +wire [3:0] pcim_sm_cbe_out ; +wire pcim_sm_cbe_en_out ; +wire pcim_sm_ad_load_out ; +wire pcim_sm_ad_load_on_transfer_out ; + +wire pcim_sm_wait_out ; +wire pcim_sm_wtransfer_out ; +wire pcim_sm_rtransfer_out ; +wire pcim_sm_retry_out ; +wire pcim_sm_rerror_out ; +wire pcim_sm_first_out ; +wire pcim_sm_mabort_out ; +wire pcim_sm_frame_load_out ; + +assign wbu_pciif_frame_load_out = pcim_sm_frame_load_out ; + +assign wbu_err_addr_out = pcim_if_err_addr_out ; +assign wbu_err_bc_out = pcim_if_err_bc_out ; +assign wbu_err_signal_out = pcim_if_err_signal_out ; +assign wbu_err_source_out = pcim_if_err_source_out ; +assign wbu_err_rty_exp_out = pcim_if_err_rty_exp_out ; +assign wbu_tabort_rec_out = pcim_if_tabort_out ; +assign wbu_mabort_rec_out = pcim_if_mabort_out ; + +assign wbu_wbw_fifo_empty_out = pcim_if_posted_write_not_present_out ; + +// pci master state machine outputs +// pci interface signals +assign wbu_pciif_req_out = pcim_sm_req_out ; +assign wbu_pciif_frame_out = pcim_sm_frame_out ; +assign wbu_pciif_frame_en_out = pcim_sm_frame_en_out ; +assign wbu_pciif_irdy_out = pcim_sm_irdy_out ; +assign wbu_pciif_irdy_en_out = pcim_sm_irdy_en_out ; +assign wbu_pciif_ad_out = pcim_sm_ad_out ; +assign wbu_pciif_ad_en_out = pcim_sm_ad_en_out ; +assign wbu_pciif_cbe_out = pcim_sm_cbe_out ; +assign wbu_pciif_cbe_en_out = pcim_sm_cbe_en_out ; +assign wbu_ad_load_out = pcim_sm_ad_load_out ; +assign wbu_ad_load_on_transfer_out = pcim_sm_ad_load_on_transfer_out ; + +// signals to internal of the core +wire [31:0] pcim_sm_data_out ; + +// wishbone slave state machine outputs +wire [3:0] wbs_sm_del_bc_out ; +wire wbs_sm_del_req_out ; +wire wbs_sm_del_done_out ; +wire wbs_sm_del_burst_out ; +wire wbs_sm_del_write_out ; +wire [11:0] wbs_sm_conf_offset_out ; +wire wbs_sm_conf_renable_out ; +wire wbs_sm_conf_wenable_out ; +wire [3:0] wbs_sm_conf_be_out ; +wire [31:0] wbs_sm_conf_data_out ; +wire [31:0] wbs_sm_data_out ; +wire [3:0] wbs_sm_cbe_out ; +wire wbs_sm_wbw_wenable_out ; +wire [3:0] wbs_sm_wbw_control_out ; +wire wbs_sm_wbr_renable_out ; +wire wbs_sm_wbr_flush_out ; +wire wbs_sm_del_in_progress_out ; +wire [31:0] wbs_sm_sdata_out ; +wire wbs_sm_ack_out ; +wire wbs_sm_rty_out ; +wire wbs_sm_err_out ; +wire wbs_sm_sample_address_out ; + +assign wbu_conf_offset_out = wbs_sm_conf_offset_out ; +assign wbu_conf_renable_out = wbs_sm_conf_renable_out ; +assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ; +assign wbu_conf_be_out = ~wbs_sm_conf_be_out ; +assign wbu_conf_data_out = wbs_sm_conf_data_out ; + +assign SDATA_O = wbs_sm_sdata_out ; +assign ACK_O = wbs_sm_ack_out ; +assign RTY_O = wbs_sm_rty_out ; +assign ERR_O = wbs_sm_err_out ; + + +// wbw_wbr fifo outputs + +// wbw_fifo_outputs: +wire [31:0] fifos_wbw_addr_data_out ; +wire [3:0] fifos_wbw_cbe_out ; +wire [3:0] fifos_wbw_control_out ; +wire fifos_wbw_almost_full_out ; +wire fifos_wbw_full_out ; +wire fifos_wbw_empty_out ; +wire fifos_wbw_transaction_ready_out ; + +// wbr_fifo_outputs +wire [31:0] fifos_wbr_data_out ; +wire [3:0] fifos_wbr_be_out ; +wire [3:0] fifos_wbr_control_out ; +wire fifos_wbr_empty_out ; + +// address multiplexer outputs +wire [5:0] amux_hit_out ; +wire [31:0] amux_address_out ; + +// delayed transaction logic outputs +wire [31:0] del_sync_addr_out ; +wire [3:0] del_sync_be_out ; +wire del_sync_we_out ; +wire del_sync_comp_req_pending_out ; +wire del_sync_comp_comp_pending_out ; +wire del_sync_req_req_pending_out ; +wire del_sync_req_comp_pending_out ; +wire [3:0] del_sync_bc_out ; +wire del_sync_status_out ; +wire del_sync_comp_flush_out ; +wire del_sync_burst_out ; + +assign wbu_del_read_comp_pending_out = del_sync_comp_comp_pending_out ; + +// delayed write storage output +wire [31:0] del_write_data_out ; + +// config. cycle address decoder output +wire [31:0] ccyc_addr_out ; + + +// WISHBONE slave interface inputs +wire [4:0] wbs_sm_hit_in = amux_hit_out[5:1] ; +wire wbs_sm_conf_hit_in = amux_hit_out[0] ; +wire [4:0] wbs_sm_map_in = wbu_map_in[5:1] ; +wire [4:0] wbs_sm_pref_en_in = wbu_pref_en_in[5:1] ; +wire [4:0] wbs_sm_mrl_en_in = wbu_mrl_en_in[5:1] ; +wire [31:0] wbs_sm_addr_in = amux_address_out ; +wire [3:0] wbs_sm_del_bc_in = del_sync_bc_out ; +wire wbs_sm_del_req_pending_in = del_sync_req_req_pending_out ; +wire wbs_sm_wb_del_comp_pending_in = del_sync_req_comp_pending_out ; +wire wbs_sm_pci_drcomp_pending_in = wbu_pci_drcomp_pending_in ; +wire wbs_sm_del_write_in = del_sync_we_out ; +wire wbs_sm_del_error_in = del_sync_status_out ; +wire [31:0] wbs_sm_del_addr_in = del_sync_addr_out ; +wire [3:0] wbs_sm_del_be_in = del_sync_be_out ; +wire [31:0] wbs_sm_conf_data_in = wbu_conf_data_in ; +wire wbs_sm_wbw_almost_full_in = fifos_wbw_almost_full_out ; +wire wbs_sm_wbw_full_in = fifos_wbw_full_out ; +wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ; +wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ; +wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ; +wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ; +wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ; +wire wbs_sm_lock_in = ~wbu_master_enable_in ; +wire wbs_sm_cache_line_size_not_zero = wbu_cache_line_size_not_zero ; +wire wbs_sm_cyc_in = CYC_I ; +wire wbs_sm_stb_in = STB_I ; +wire wbs_sm_we_in = WE_I ; +wire [3:0] wbs_sm_sel_in = SEL_I ; +wire [31:0] wbs_sm_sdata_in = SDATA_I ; +wire wbs_sm_cab_in = CAB_I ; +wire [31:0] wbs_sm_ccyc_addr_in = ccyc_addr_out ; +wire wbs_sm_init_complete_in = wb_init_complete_in ; + +// WISHBONE slave interface instantiation +pci_wb_slave wishbone_slave( + .wb_clock_in (wb_clock_in) , + .reset_in (reset_in) , + .wb_hit_in (wbs_sm_hit_in) , + .wb_conf_hit_in (wbs_sm_conf_hit_in) , + .wb_map_in (wbs_sm_map_in) , + .wb_pref_en_in (wbs_sm_pref_en_in) , + .wb_mrl_en_in (wbs_sm_mrl_en_in) , + .wb_addr_in (wbs_sm_addr_in), + .del_bc_in (wbs_sm_del_bc_in), + .wb_del_req_pending_in (wbs_sm_del_req_pending_in), + .wb_del_comp_pending_in (wbs_sm_wb_del_comp_pending_in), + .pci_drcomp_pending_in (wbs_sm_pci_drcomp_pending_in), + .del_bc_out (wbs_sm_del_bc_out), + .del_req_out (wbs_sm_del_req_out), + .del_done_out (wbs_sm_del_done_out), + .del_burst_out (wbs_sm_del_burst_out), + .del_write_out (wbs_sm_del_write_out), + .del_write_in (wbs_sm_del_write_in), + .del_error_in (wbs_sm_del_error_in), + .wb_del_addr_in (wbs_sm_del_addr_in), + .wb_del_be_in (wbs_sm_del_be_in), + .wb_conf_offset_out (wbs_sm_conf_offset_out), + .wb_conf_renable_out (wbs_sm_conf_renable_out), + .wb_conf_wenable_out (wbs_sm_conf_wenable_out), + .wb_conf_be_out (wbs_sm_conf_be_out), + .wb_conf_data_in (wbs_sm_conf_data_in), + .wb_conf_data_out (wbs_sm_conf_data_out), + .wb_data_out (wbs_sm_data_out), + .wb_cbe_out (wbs_sm_cbe_out), + .wbw_fifo_wenable_out (wbs_sm_wbw_wenable_out), + .wbw_fifo_control_out (wbs_sm_wbw_control_out), + .wbw_fifo_almost_full_in (wbs_sm_wbw_almost_full_in), + .wbw_fifo_full_in (wbs_sm_wbw_full_in), + .wbr_fifo_renable_out (wbs_sm_wbr_renable_out), + .wbr_fifo_be_in (wbs_sm_wbr_be_in), + .wbr_fifo_data_in (wbs_sm_wbr_data_in), + .wbr_fifo_control_in (wbs_sm_wbr_control_in), + .wbr_fifo_flush_out (wbs_sm_wbr_flush_out), + .wbr_fifo_empty_in (wbs_sm_wbr_empty_in), + .pciw_fifo_empty_in (wbs_sm_pciw_empty_in), + .wbs_lock_in (wbs_sm_lock_in), + .init_complete_in (wbs_sm_init_complete_in), + .cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero), + .del_in_progress_out (wbs_sm_del_in_progress_out), + .ccyc_addr_in (wbs_sm_ccyc_addr_in), + .sample_address_out (wbs_sm_sample_address_out), + .CYC_I (wbs_sm_cyc_in), + .STB_I (wbs_sm_stb_in), + .WE_I (wbs_sm_we_in), + .SEL_I (wbs_sm_sel_in), + .SDATA_I (wbs_sm_sdata_in), + .SDATA_O (wbs_sm_sdata_out), + .ACK_O (wbs_sm_ack_out), + .RTY_O (wbs_sm_rty_out), + .ERR_O (wbs_sm_err_out), + .CAB_I (wbs_sm_cab_in) + ); + +// wbw_wbr_fifos inputs +// WBW_FIFO inputs +wire fifos_wbw_wenable_in = wbs_sm_wbw_wenable_out; +wire [31:0] fifos_wbw_addr_data_in = wbs_sm_data_out ; +wire [3:0] fifos_wbw_cbe_in = wbs_sm_cbe_out ; +wire [3:0] fifos_wbw_control_in = wbs_sm_wbw_control_out ; +wire fifos_wbw_renable_in = pcim_if_wbw_renable_out ; + +//wire fifos_wbw_flush_in = 1'b0 ; flush for write fifo not used + +// WBR_FIFO inputs +wire fifos_wbr_wenable_in = pcim_if_wbr_wenable_out ; +wire [31:0] fifos_wbr_data_in = pcim_if_wbr_data_out ; +wire [3:0] fifos_wbr_be_in = pcim_if_wbr_be_out ; +wire [3:0] fifos_wbr_control_in = pcim_if_wbr_control_out ; +wire fifos_wbr_renable_in = wbs_sm_wbr_renable_out ; +wire fifos_wbr_flush_in = wbs_sm_wbr_flush_out || del_sync_comp_flush_out ; + +// WBW_FIFO and WBR_FIFO instantiation +pci_wbw_wbr_fifos fifos +( + .wb_clock_in (wb_clock_in), + .pci_clock_in (pci_clock_in), + .reset_in (reset_in), + .wbw_wenable_in (fifos_wbw_wenable_in), + .wbw_addr_data_in (fifos_wbw_addr_data_in), + .wbw_cbe_in (fifos_wbw_cbe_in), + .wbw_control_in (fifos_wbw_control_in), + .wbw_renable_in (fifos_wbw_renable_in), + .wbw_addr_data_out (fifos_wbw_addr_data_out), + .wbw_cbe_out (fifos_wbw_cbe_out), + .wbw_control_out (fifos_wbw_control_out), +// .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used + .wbw_almost_full_out (fifos_wbw_almost_full_out), + .wbw_full_out (fifos_wbw_full_out), + .wbw_empty_out (fifos_wbw_empty_out), + .wbw_transaction_ready_out (fifos_wbw_transaction_ready_out), + .wbr_wenable_in (fifos_wbr_wenable_in), + .wbr_data_in (fifos_wbr_data_in), + .wbr_be_in (fifos_wbr_be_in), + .wbr_control_in (fifos_wbr_control_in), + .wbr_renable_in (fifos_wbr_renable_in), + .wbr_data_out (fifos_wbr_data_out), + .wbr_be_out (fifos_wbr_be_out), + .wbr_control_out (fifos_wbr_control_out), + .wbr_flush_in (fifos_wbr_flush_in), + .wbr_empty_out (fifos_wbr_empty_out) + +`ifdef PCI_BIST + , + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) +`endif +) ; + +wire [31:0] amux_addr_in = ADDR_I ; +wire amux_sample_address_in = wbs_sm_sample_address_out ; + +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in = wbu_bar0_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in = wbu_bar1_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in = wbu_bar2_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in = wbu_bar3_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in = wbu_bar4_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar5_in = wbu_bar5_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am0_in = wbu_am0_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am1_in = wbu_am1_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am2_in = wbu_am2_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am3_in = wbu_am3_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am4_in = wbu_am4_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am5_in = wbu_am5_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta0_in = wbu_ta0_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta1_in = wbu_ta1_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta2_in = wbu_ta2_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta3_in = wbu_ta3_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta4_in = wbu_ta4_in ; +wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in = wbu_ta5_in ; +wire [5:0] amux_at_en_in = wbu_at_en_in ; + +pci_wb_addr_mux wb_addr_dec +( + `ifdef REGISTER_WBS_OUTPUTS + .clk_in (wb_clock_in), + .reset_in (reset_in), + .sample_address_in (amux_sample_address_in), + `endif + .address_in (amux_addr_in), + .bar0_in (amux_bar0_in), + .bar1_in (amux_bar1_in), + .bar2_in (amux_bar2_in), + .bar3_in (amux_bar3_in), + .bar4_in (amux_bar4_in), + .bar5_in (amux_bar5_in), + .am0_in (amux_am0_in), + .am1_in (amux_am1_in), + .am2_in (amux_am2_in), + .am3_in (amux_am3_in), + .am4_in (amux_am4_in), + .am5_in (amux_am5_in), + .ta0_in (amux_ta0_in), + .ta1_in (amux_ta1_in), + .ta2_in (amux_ta2_in), + .ta3_in (amux_ta3_in), + .ta4_in (amux_ta4_in), + .ta5_in (amux_ta5_in), + .at_en_in (amux_at_en_in), + .hit_out (amux_hit_out), + .address_out (amux_address_out) +); + +// delayed transaction logic inputs +wire del_sync_req_in = wbs_sm_del_req_out ; +wire del_sync_comp_in = pcim_if_del_complete_out ; +wire del_sync_done_in = wbs_sm_del_done_out ; +wire del_sync_in_progress_in = wbs_sm_del_in_progress_out ; +wire [31:0] del_sync_addr_in = wbs_sm_data_out ; +wire [3:0] del_sync_be_in = wbs_sm_conf_be_out ; +wire del_sync_we_in = wbs_sm_del_write_out ; +wire [3:0] del_sync_bc_in = wbs_sm_del_bc_out ; +wire del_sync_status_in = pcim_if_del_error_out ; +wire del_sync_burst_in = wbs_sm_del_burst_out ; +wire del_sync_retry_expired_in = pcim_if_del_rty_exp_out ; + +// delayed transaction logic instantiation +pci_delayed_sync del_sync ( + .reset_in (reset_in), + .req_clk_in (wb_clock_in), + .comp_clk_in (pci_clock_in), + .req_in (del_sync_req_in), + .comp_in (del_sync_comp_in), + .done_in (del_sync_done_in), + .in_progress_in (del_sync_in_progress_in), + .comp_req_pending_out (del_sync_comp_req_pending_out), + .comp_comp_pending_out(del_sync_comp_comp_pending_out), + .req_req_pending_out (del_sync_req_req_pending_out), + .req_comp_pending_out (del_sync_req_comp_pending_out), + .addr_in (del_sync_addr_in), + .be_in (del_sync_be_in), + .addr_out (del_sync_addr_out), + .be_out (del_sync_be_out), + .we_in (del_sync_we_in), + .we_out (del_sync_we_out), + .bc_in (del_sync_bc_in), + .bc_out (del_sync_bc_out), + .status_in (del_sync_status_in), + .status_out (del_sync_status_out), + .comp_flush_out (del_sync_comp_flush_out), + .burst_in (del_sync_burst_in), + .burst_out (del_sync_burst_out), + .retry_expired_in (del_sync_retry_expired_in) + ); + +// delayed write storage inputs +wire del_write_we_in = wbs_sm_del_req_out && wbs_sm_del_write_out ; +wire [31:0] del_write_data_in = wbs_sm_conf_data_out ; + +pci_delayed_write_reg delayed_write_data +( + .reset_in (reset_in), + .req_clk_in (wb_clock_in), + .comp_wdata_out (del_write_data_out), + .req_we_in (del_write_we_in), + .req_wdata_in (del_write_data_in) +); + +`ifdef HOST + // configuration cycle address decoder input + wire [31:0] ccyc_addr_in = {8'h00, wbu_ccyc_addr_in} ; + + pci_conf_cyc_addr_dec ccyc_addr_dec + ( + .ccyc_addr_in (ccyc_addr_in), + .ccyc_addr_out (ccyc_addr_out) + ) ; +`else +`ifdef GUEST + assign ccyc_addr_out = 32'h0000_0000 ; +`endif +`endif + +// pci master interface inputs +wire [31:0] pcim_if_wbw_addr_data_in = fifos_wbw_addr_data_out ; +wire [3:0] pcim_if_wbw_cbe_in = fifos_wbw_cbe_out ; +wire [3:0] pcim_if_wbw_control_in = fifos_wbw_control_out ; +wire pcim_if_wbw_empty_in = fifos_wbw_empty_out ; +wire pcim_if_wbw_transaction_ready_in = fifos_wbw_transaction_ready_out ; +wire [31:0] pcim_if_data_in = pcim_sm_data_out ; +wire [31:0] pcim_if_del_wdata_in = del_write_data_out ; +wire pcim_if_del_req_in = del_sync_comp_req_pending_out ; +wire [31:0] pcim_if_del_addr_in = del_sync_addr_out ; +wire [3:0] pcim_if_del_bc_in = del_sync_bc_out ; +wire [3:0] pcim_if_del_be_in = del_sync_be_out ; +wire pcim_if_del_burst_in = del_sync_burst_out ; +wire pcim_if_del_we_in = del_sync_we_out ; +wire [7:0] pcim_if_cache_line_size_in = wbu_cache_line_size_in ; +wire pcim_if_wait_in = pcim_sm_wait_out ; +wire pcim_if_wtransfer_in = pcim_sm_wtransfer_out ; +wire pcim_if_rtransfer_in = pcim_sm_rtransfer_out ; +wire pcim_if_retry_in = pcim_sm_retry_out ; +wire pcim_if_rerror_in = pcim_sm_rerror_out ; +wire pcim_if_first_in = pcim_sm_first_out ; +wire pcim_if_mabort_in = pcim_sm_mabort_out ; + +pci_master32_sm_if pci_initiator_if +( + .clk_in (pci_clock_in), + .reset_in (reset_in), + .address_out (pcim_if_address_out), + .bc_out (pcim_if_bc_out), + .data_out (pcim_if_data_out), + .data_in (pcim_if_data_in), + .be_out (pcim_if_be_out), + .req_out (pcim_if_req_out), + .rdy_out (pcim_if_rdy_out), + .last_out (pcim_if_last_out), + .wbw_renable_out (pcim_if_wbw_renable_out), + .wbw_fifo_addr_data_in (pcim_if_wbw_addr_data_in), + .wbw_fifo_cbe_in (pcim_if_wbw_cbe_in), + .wbw_fifo_control_in (pcim_if_wbw_control_in), + .wbw_fifo_empty_in (pcim_if_wbw_empty_in), + .wbw_fifo_transaction_ready_in (pcim_if_wbw_transaction_ready_in), + .wbr_fifo_wenable_out (pcim_if_wbr_wenable_out), + .wbr_fifo_data_out (pcim_if_wbr_data_out), + .wbr_fifo_be_out (pcim_if_wbr_be_out), + .wbr_fifo_control_out (pcim_if_wbr_control_out), + .del_wdata_in (pcim_if_del_wdata_in), + .del_complete_out (pcim_if_del_complete_out), + .del_req_in (pcim_if_del_req_in), + .del_addr_in (pcim_if_del_addr_in), + .del_bc_in (pcim_if_del_bc_in), + .del_be_in (pcim_if_del_be_in), + .del_burst_in (pcim_if_del_burst_in), + .del_error_out (pcim_if_del_error_out), + .del_rty_exp_out (pcim_if_del_rty_exp_out), + .del_we_in (pcim_if_del_we_in), + .err_addr_out (pcim_if_err_addr_out), + .err_bc_out (pcim_if_err_bc_out), + .err_signal_out (pcim_if_err_signal_out), + .err_source_out (pcim_if_err_source_out), + .err_rty_exp_out (pcim_if_err_rty_exp_out), + .cache_line_size_in (pcim_if_cache_line_size_in), + .mabort_received_out (pcim_if_mabort_out), + .tabort_received_out (pcim_if_tabort_out), + .next_data_out (pcim_if_next_data_out), + .next_be_out (pcim_if_next_be_out), + .next_last_out (pcim_if_next_last_out), + .wait_in (pcim_if_wait_in), + .wtransfer_in (pcim_if_wtransfer_in), + .rtransfer_in (pcim_if_rtransfer_in), + .retry_in (pcim_if_retry_in), + .rerror_in (pcim_if_rerror_in), + .first_in (pcim_if_first_in), + .mabort_in (pcim_if_mabort_in), + .posted_write_not_present_out (pcim_if_posted_write_not_present_out) +); + +// pci master state machine inputs +wire pcim_sm_gnt_in = wbu_pciif_gnt_in ; +wire pcim_sm_frame_in = wbu_pciif_frame_in ; +wire pcim_sm_irdy_in = wbu_pciif_irdy_in ; +wire pcim_sm_trdy_in = wbu_pciif_trdy_in; +wire pcim_sm_stop_in = wbu_pciif_stop_in ; +wire pcim_sm_devsel_in = wbu_pciif_devsel_in ; +wire [31:0] pcim_sm_ad_reg_in = wbu_pciif_ad_reg_in ; +wire [31:0] pcim_sm_address_in = pcim_if_address_out ; +wire [3:0] pcim_sm_bc_in = pcim_if_bc_out ; +wire [31:0] pcim_sm_data_in = pcim_if_data_out ; +wire [3:0] pcim_sm_be_in = pcim_if_be_out ; +wire pcim_sm_req_in = pcim_if_req_out ; +wire pcim_sm_rdy_in = pcim_if_rdy_out ; +wire pcim_sm_last_in = pcim_if_last_out ; +wire [7:0] pcim_sm_latency_tim_val_in = wbu_latency_tim_val_in ; +wire [31:0] pcim_sm_next_data_in = pcim_if_next_data_out ; +wire [3:0] pcim_sm_next_be_in = pcim_if_next_be_out ; +wire pcim_sm_next_last_in = pcim_if_next_last_out ; +wire pcim_sm_trdy_reg_in = wbu_pciif_trdy_reg_in ; +wire pcim_sm_stop_reg_in = wbu_pciif_stop_reg_in ; +wire pcim_sm_devsel_reg_in = wbu_pciif_devsel_reg_in ; +wire pcim_sm_frame_en_in = wbu_pciif_frame_en_in ; +wire pcim_sm_frame_out_in = wbu_pciif_frame_out_in ; + +pci_master32_sm pci_initiator_sm +( + .clk_in (pci_clock_in), + .reset_in (reset_in), + .pci_req_out (pcim_sm_req_out), + .pci_gnt_in (pcim_sm_gnt_in), + .pci_frame_in (pcim_sm_frame_in), + .pci_frame_out (pcim_sm_frame_out), + .pci_frame_en_out (pcim_sm_frame_en_out), + .pci_frame_out_in (pcim_sm_frame_out_in), + .pci_frame_load_out (pcim_sm_frame_load_out), + .pci_frame_en_in (pcim_sm_frame_en_in), + .pci_irdy_in (pcim_sm_irdy_in), + .pci_irdy_out (pcim_sm_irdy_out), + .pci_irdy_en_out (pcim_sm_irdy_en_out), + .pci_trdy_in (pcim_sm_trdy_in), + .pci_trdy_reg_in (pcim_sm_trdy_reg_in), + .pci_stop_in (pcim_sm_stop_in), + .pci_stop_reg_in (pcim_sm_stop_reg_in), + .pci_devsel_in (pcim_sm_devsel_in), + .pci_devsel_reg_in (pcim_sm_devsel_reg_in), + .pci_ad_reg_in (pcim_sm_ad_reg_in), + .pci_ad_out (pcim_sm_ad_out), + .pci_ad_en_out (pcim_sm_ad_en_out), + .pci_cbe_out (pcim_sm_cbe_out), + .pci_cbe_en_out (pcim_sm_cbe_en_out), + .address_in (pcim_sm_address_in), + .bc_in (pcim_sm_bc_in), + .data_in (pcim_sm_data_in), + .data_out (pcim_sm_data_out), + .be_in (pcim_sm_be_in), + .req_in (pcim_sm_req_in), + .rdy_in (pcim_sm_rdy_in), + .last_in (pcim_sm_last_in), + .latency_tim_val_in (pcim_sm_latency_tim_val_in), + .next_data_in (pcim_sm_next_data_in), + .next_be_in (pcim_sm_next_be_in), + .next_last_in (pcim_sm_next_last_in), + .ad_load_out (pcim_sm_ad_load_out), + .ad_load_on_transfer_out (pcim_sm_ad_load_on_transfer_out), + .wait_out (pcim_sm_wait_out), + .wtransfer_out (pcim_sm_wtransfer_out), + .rtransfer_out (pcim_sm_rtransfer_out), + .retry_out (pcim_sm_retry_out), + .rerror_out (pcim_sm_rerror_out), + .first_out (pcim_sm_first_out), + .mabort_out (pcim_sm_mabort_out) +) ; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_tpram.v b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_tpram.v new file mode 100644 index 000000000..bd4667b7f --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/pci/rtl/pci_wb_tpram.v @@ -0,0 +1,465 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Two-Port Synchronous RAM //// +//// //// +//// This file is part of pci bridge project //// +//// http://www.opencores.org/cvsweb.shtml/pci/ //// +//// //// +//// Description //// +//// This block is a wrapper with common two-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// two-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Double-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB4_S16_S16 //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - xilinx rams need external tri-state logic //// +//// - add additional RAMs (Altera, VS etc) //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// - Miha Dolenc, mihad@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: pci_wb_tpram.v,v $ +// Revision 1.4 2004/08/19 15:27:34 mihad +// Changed minimum pci image size to 256 bytes because +// of some PC system problems with size of IO images. +// +// Revision 1.3 2003/10/17 09:11:52 markom +// mbist signals updated according to newest convention +// +// Revision 1.2 2003/08/14 13:06:03 simons +// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. +// +// Revision 1.1 2003/01/27 16:49:31 mihad +// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. +// +// Revision 1.7 2002/10/18 03:36:37 tadejm +// Changed wrong signal name mbist_sen into mbist_ctrl_i. +// +// Revision 1.6 2002/10/17 22:49:22 tadejm +// Changed BIST signals for RAMs. +// +// Revision 1.5 2002/10/11 10:09:01 mihad +// Added additional testcase and changed rst name in BIST to trst +// +// Revision 1.4 2002/10/08 17:17:06 mihad +// Added BIST signals for RAMs. +// +// Revision 1.3 2002/09/30 17:22:27 mihad +// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! +// +// Revision 1.2 2002/08/19 16:51:36 mihad +// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives +// +// Revision 1.1 2002/02/01 14:43:31 mihad +// *** empty log message *** +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "pci_constants.v" + +module pci_wb_tpram +( + // Generic synchronous two-port RAM interface + clk_a, + rst_a, + ce_a, + we_a, + oe_a, + addr_a, + di_a, + do_a, + clk_b, + rst_b, + ce_b, + we_b, + oe_b, + addr_b, + di_b, + do_b +`ifdef PCI_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif +); + +// +// Default address and data buses width +// +parameter aw = 8; +parameter dw = 40; + +// +// Generic synchronous two-port RAM interface +// +input clk_a; // Clock +input rst_a; // Reset +input ce_a; // Chip enable input +input we_a; // Write enable input +input oe_a; // Output enable input +input [aw-1:0] addr_a; // address bus inputs +input [dw-1:0] di_a; // input data bus +output [dw-1:0] do_a; // output data bus +input clk_b; // Clock +input rst_b; // Reset +input ce_b; // Chip enable input +input we_b; // Write enable input +input oe_b; // Output enable input +input [aw-1:0] addr_b; // address bus inputs +input [dw-1:0] di_b; // input data bus +output [dw-1:0] do_b; // output data bus + +`ifdef PCI_BIST +// debug chain signals +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + +// +// Internal wires and registers +// + +`ifdef WB_VS_STP + `define PCI_WB_RAM_SELECTED + `ifdef PCI_BIST + vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist + `else + vs_hdtp_64x40 i_vs_hdtp_64x40 + `endif + ( + .RCK (clk_b), + .WCK (clk_a), + .RADR (addr_b), + .WADR (addr_a), + .DI (di_a), + .DOUT (do_b), + .REN (1'b0), + .WEN (!we_a) + `ifdef PCI_BIST + , + // debug chain signals + .mbist_si_i (mbist_si_i), + .mbist_so_o (mbist_so_o), + .mbist_ctrl_i (mbist_ctrl_i) + `endif + ); + + assign do_a = 0 ; +`endif + +`ifdef WB_ARTISAN_SDP + `define PCI_WB_RAM_SELECTED + // + // Instantiation of ASIC memory: + // + // Artisan Synchronous Double-Port RAM (ra2sh) + // + `ifdef PCI_BIST + art_hsdp_64x40_bist /*#(dw, 1<= StepLockOut) then + + StepCounter <= "00000000000000000000000000000000"; -- if we just roll-ed over, then it's time to do something + + if (ProvideStaticHolding = '1') then --should we leave coils in energized state by defaul or not? + + StepDrive <= "0000"; + + else + + StepDrive <= "1111"; + + end if; + + if (InternalStepEnable = '1') then -- are we supposed to step on this clock? + + InternalStepEnable <= StepEnable; -- InternalStepEnable togles at the speed of the clock divider rollover, trailing the + -- external StepEnable by less than or equal to one rollover. + -- Putting this inside the "if internal=1" makes us wait until after move to turn off, + -- so we move at least once for each pulse of external step enable line. + + if (Direction = '1') then state <= state + "01"; end if; -- to change the direction of a stepper motor, you energize + if (Direction = '0') then state <= state - "01"; end if; -- the coils in the opposite pattern, so just run states backwards + -- this also allows a change of direction at any arbitrary point + case state is + + when "00" => + + StepDrive <= "1010"; -- these states follow proper pattern of coil energizing for turning steppers + + when "01" => + + StepDrive <= "1001"; + + when "10" => + + StepDrive <= "0101"; + + when "11" => + + StepDrive <= "0110"; + + when others => + + end case; --state + + end if; + + end if; + + end if; + + end process; + +end StepDrive; diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/aes.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/aes.v new file mode 100644 index 000000000..e5021ed16 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/aes.v @@ -0,0 +1,358 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// AES top file //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// AES top //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: aes.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module aes(clk,reset,load_i,decrypt_i,data_i,key_i,ready_o,data_o); +input clk; +input reset; +input load_i; +input decrypt_i; +input [127:0] data_i; +input [127:0] key_i; +output ready_o; +output [127:0] data_o; + +reg ready_o; +reg [127:0] data_o; + +reg next_ready_o; +reg keysched_start_i; +reg [3:0] keysched_round_i; +reg [127:0] keysched_last_key_i; +wire [127:0] keysched_new_key_o; + +wire keysched_ready_o; + +wire keysched_sbox_access_o; + +wire [7:0] keysched_sbox_data_o; + +wire keysched_sbox_decrypt_o; + +reg mixcol_start_i; +reg [127:0] mixcol_data_i; +wire mixcol_ready_o; + +wire [127:0] mixcol_data_o; + +reg subbytes_start_i; +reg [127:0] subbytes_data_i; +wire subbytes_ready_o; + +wire [127:0] subbytes_data_o; + +wire [7:0] subbytes_sbox_data_o; + +wire subbytes_sbox_decrypt_o; + +wire [7:0] sbox_data_o; + +reg [7:0] sbox_data_i; +reg sbox_decrypt_i; +reg state; +reg next_state; +reg [3:0] round; +reg [3:0] next_round; +reg [127:0] addroundkey_data_o; +reg [127:0] next_addroundkey_data_reg; +reg [127:0] addroundkey_data_reg; +reg [127:0] addroundkey_data_i; +reg addroundkey_ready_o; +reg next_addroundkey_ready_o; +reg addroundkey_start_i; +reg next_addroundkey_start_i; +reg [3:0] addroundkey_round; +reg [3:0] next_addroundkey_round; +reg first_round_reg; +reg next_first_round_reg; + +sbox sbox1 (.clk(clk), .reset(reset), .data_i(sbox_data_i), .decrypt_i(sbox_decrypt_i), .data_o(sbox_data_o)); +subbytes sub1 (.clk(clk), .reset(reset), .start_i(subbytes_start_i), .decrypt_i(decrypt_i), .data_i(subbytes_data_i), .ready_o(subbytes_ready_o), .data_o(subbytes_data_o), .sbox_data_o(subbytes_sbox_data_o), .sbox_data_i(sbox_data_o), .sbox_decrypt_o(subbytes_sbox_decrypt_o)); +mixcolum mix1 (.clk(clk), .reset(reset), .decrypt_i(decrypt_i), .start_i(mixcol_start_i), .data_i(mixcol_data_i), .ready_o(mixcol_ready_o), .data_o(mixcol_data_o)); +keysched ks1 (.clk(clk), .reset(reset), .start_i(keysched_start_i), .round_i(keysched_round_i), .last_key_i(keysched_last_key_i), .new_key_o(keysched_new_key_o), .ready_o(keysched_ready_o), .sbox_access_o(keysched_sbox_access_o), .sbox_data_o(keysched_sbox_data_o), .sbox_data_i(sbox_data_o), .sbox_decrypt_o(keysched_sbox_decrypt_o)); + +//registers: +always @(posedge clk or negedge reset) + +begin + + if(!reset) +begin + + state = (0); + ready_o = (0); + round = (0); + addroundkey_round = (0); + addroundkey_data_reg = (0); + addroundkey_ready_o = (0); + addroundkey_start_i = (0); + first_round_reg = (0); + +end +else +begin + + state = (next_state); + ready_o = (next_ready_o); + round = (next_round); + addroundkey_round = (next_addroundkey_round); + addroundkey_data_reg = (next_addroundkey_data_reg); + addroundkey_ready_o = (next_addroundkey_ready_o); + first_round_reg = (next_first_round_reg); + addroundkey_start_i = (next_addroundkey_start_i); + +end + + +end +//control: +always @( state or round or addroundkey_data_o or data_i or load_i or decrypt_i or addroundkey_ready_o or mixcol_ready_o or subbytes_ready_o or subbytes_data_o or mixcol_data_o or first_round_reg) + +begin + + + next_state = (state); + next_round = (round); + data_o = (addroundkey_data_o); + next_ready_o = (0); + + //Tokeyschedulemodule + + next_first_round_reg = (0); + + + subbytes_data_i = (0); + mixcol_data_i = (0); + addroundkey_data_i = (0); + next_addroundkey_start_i = (first_round_reg); + mixcol_start_i = ((addroundkey_ready_o&decrypt_i&round!=10)|(subbytes_ready_o&!decrypt_i)); + subbytes_start_i = ((addroundkey_ready_o&!decrypt_i)|(mixcol_ready_o&decrypt_i)|(addroundkey_ready_o&decrypt_i&round==10)); + + if(decrypt_i&&round!=10) + begin + addroundkey_data_i = (subbytes_data_o); + subbytes_data_i = (mixcol_data_o); + mixcol_data_i = (addroundkey_data_o); + end + else if(!decrypt_i&&round!=0) + begin + addroundkey_data_i = (mixcol_data_o); + subbytes_data_i = (addroundkey_data_o); + mixcol_data_i = (subbytes_data_o); + end + else + begin + mixcol_data_i = (subbytes_data_o); + subbytes_data_i = (addroundkey_data_o); + addroundkey_data_i = (data_i); + end + + + case(state) + + 0: + begin + if(load_i) + begin + next_state = (1); + if(decrypt_i) + next_round = (10); + else + next_round = (0); + next_first_round_reg = (1); + end + end + + 1: + begin + + //Counter + if(!decrypt_i&&mixcol_ready_o) + begin + next_addroundkey_start_i = (1); + addroundkey_data_i = (mixcol_data_o); + next_round = (round+1); + end + else if(decrypt_i&&subbytes_ready_o) + begin + next_addroundkey_start_i = (1); + addroundkey_data_i = (subbytes_data_o); + next_round = (round-1); + end + + //Output + if((round==9&&!decrypt_i)||(round==0&&decrypt_i)) + begin + next_addroundkey_start_i = (0); + mixcol_start_i = (0); + if(subbytes_ready_o) + begin + addroundkey_data_i = (subbytes_data_o); + next_addroundkey_start_i = (1); + next_round = (round+1); + end + end + + if((round==10&&!decrypt_i)||(round==0&&decrypt_i)) + begin + addroundkey_data_i = (subbytes_data_o); + subbytes_start_i = (0); + if(addroundkey_ready_o) + begin + next_ready_o = (1); + next_state = (0); + next_addroundkey_start_i = (0); + next_round = (0); + end + + end + + + end + + default: +begin + next_state = (0); + end + endcase + + +end +//addroundkey: +reg[127:0] data_var,round_data_var,round_key_var; +always @( addroundkey_data_i or addroundkey_start_i or addroundkey_data_reg or addroundkey_round or keysched_new_key_o or keysched_ready_o or key_i or round) + +begin + + + + round_data_var=addroundkey_data_reg; + next_addroundkey_data_reg = (addroundkey_data_reg); +next_addroundkey_ready_o = (0); + next_addroundkey_round = (addroundkey_round); + addroundkey_data_o = (addroundkey_data_reg); + + if(addroundkey_round==1||addroundkey_round==0) + keysched_last_key_i = (key_i); +else + keysched_last_key_i = (keysched_new_key_o); + + keysched_start_i = (0); + + keysched_round_i = (addroundkey_round); + + if(round==0&&addroundkey_start_i) +begin + + //Taketheinputandxorthemwithdataifround==0; + data_var=addroundkey_data_i; + round_key_var=key_i; + round_data_var=round_key_var^data_var; + next_addroundkey_data_reg = (round_data_var); +next_addroundkey_ready_o = (1); + +end +else if(addroundkey_start_i&&round!=0) +begin + + keysched_last_key_i = (key_i); + keysched_start_i = (1); + keysched_round_i = (1); + next_addroundkey_round = (1); + +end +else if(addroundkey_round!=round&&keysched_ready_o) +begin + +next_addroundkey_round = (addroundkey_round+1); + keysched_last_key_i = (keysched_new_key_o); + keysched_start_i = (1); + keysched_round_i = (addroundkey_round+1); + +end +else if(addroundkey_round==round&&keysched_ready_o) +begin + + data_var=addroundkey_data_i; + round_key_var=keysched_new_key_o; + round_data_var=round_key_var^data_var; + next_addroundkey_data_reg = (round_data_var); +next_addroundkey_ready_o = (1); + next_addroundkey_round = (0); + +end + + +end +//sbox_muxes: +always @( keysched_sbox_access_o or keysched_sbox_decrypt_o or keysched_sbox_data_o or subbytes_sbox_decrypt_o or subbytes_sbox_data_o) + +begin + + + if(keysched_sbox_access_o) +begin + + sbox_decrypt_i = (keysched_sbox_decrypt_o); + sbox_data_i = (keysched_sbox_data_o); + +end +else +begin + + sbox_decrypt_i = (subbytes_sbox_decrypt_o); +sbox_data_i = (subbytes_sbox_data_o); + +end + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/byte_mixcolum.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/byte_mixcolum.v new file mode 100644 index 000000000..b248cc400 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/byte_mixcolum.v @@ -0,0 +1,92 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Mixcolumns for 8 bit //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// Mixcolum for a byte //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: byte_mixcolum.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module byte_mixcolum(a,b,c,d,outx,outy); + +input [7:0] a,b,c,d; +output [7:0] outx, outy; + +reg [7:0] outx, outy; + +function [7:0] xtime; +input [7:0] in; +reg [3:0] xtime_t; + +begin +xtime[7:5] = in[6:4]; +xtime_t[3] = in[7]; +xtime_t[2] = in[7]; +xtime_t[1] = 0; +xtime_t[0] = in[7]; +xtime[4:1] =xtime_t^in[3:0]; +xtime[0] = in[7]; +end +endfunction + +reg [7:0] w1,w2,w3,w4,w5,w6,w7,w8,outx_var; +always @ (a, b, c, d) +begin +w1 = a ^b; +w2 = a ^c; +w3 = c ^d; +w4 = xtime(w1); +w5 = xtime(w3); +w6 = w2 ^w4 ^w5; +w7 = xtime(w6); +w8 = xtime(w7); + +outx_var = b^w3^w4; +outx=outx_var; +outy=w8^outx_var; + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/keysched.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/keysched.v new file mode 100644 index 000000000..f242c5675 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/keysched.v @@ -0,0 +1,248 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key schedule //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// Generate the next round key from the previous one //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: keysched.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module keysched(clk,reset,start_i,round_i,last_key_i,new_key_o,ready_o,sbox_access_o,sbox_data_o,sbox_data_i,sbox_decrypt_o); +input clk; +input reset; +input start_i; +input [3:0] round_i; +input [127:0] last_key_i; +output [127:0] new_key_o; +output ready_o; +output sbox_access_o; +output [7:0] sbox_data_o; +input [7:0] sbox_data_i; +output sbox_decrypt_o; + +reg [127:0] new_key_o; +reg ready_o; +reg sbox_access_o; +reg [7:0] sbox_data_o; +reg sbox_decrypt_o; + +reg [2:0] next_state; +reg [2:0] state; +reg [7:0] rcon_o; +reg [31:0] next_col; +reg [31:0] col; +reg [127:0] key_reg; +reg [127:0] next_key_reg; +reg next_ready_o; + + +//rcon: +always @( round_i) + +begin + + + case(round_i) + 1: +begin +rcon_o = (1); +end + 2: +begin +rcon_o = (2); +end + 3: +begin +rcon_o = (4); +end + 4: +begin +rcon_o = (8); +end + 5: +begin +rcon_o = ('h10); +end + 6: +begin +rcon_o = ('h20); +end + 7: +begin +rcon_o = ('h40); +end + 8: +begin +rcon_o = ('h80); +end + 9: +begin +rcon_o = ('h1B); +end + 10: +begin +rcon_o = ('h36); +end +default: +begin + rcon_o = (0); +end + endcase + + +end +//registers: +always @(posedge clk or negedge reset) + +begin + + if(!reset) + begin + state = (0); + col = (0); + key_reg = (0); + ready_o = (0); + end +else + begin + state = (next_state); + col = (next_col); + key_reg = (next_key_reg); + ready_o = (next_ready_o); + end + + +end +//generate_key: +reg[127:0] K_var,W_var; + reg[31:0] col_t; + reg[23:0] zero; + +always @( start_i or last_key_i or sbox_data_i or state or rcon_o or col or key_reg) + +begin + + + zero=0; + + col_t=col; + W_var=0; + + next_state = (state); + next_col = (col); + + next_ready_o = (0); + next_key_reg = (key_reg); + new_key_o = (key_reg); + +sbox_decrypt_o = (0); + sbox_access_o = (0); + sbox_data_o = (0); + K_var=last_key_i; + + case(state) + //Substitutethebyteswhilerotatingthem + //FouraccessestoSBoxareneeded + 0: +begin + if(start_i) +begin + + col_t=0; + sbox_access_o = (1); + sbox_data_o = (K_var[31:24]); + next_state = (1); + +end + + end + 1: +begin + sbox_access_o = (1); + sbox_data_o = (K_var[23:16]); + col_t[7:0]=sbox_data_i; + next_col = (col_t); + next_state = (2); + end + 2: +begin + sbox_access_o = (1); + sbox_data_o = (K_var[15:8]); + col_t[31:24]=sbox_data_i; + next_col = (col_t); + next_state = (3); + end + 3: +begin + sbox_access_o = (1); + sbox_data_o = (K_var[7:0]); + col_t[23:16]=sbox_data_i; + next_col = (col_t); + next_state = (4); + end + 4: +begin + sbox_access_o = (1); + col_t[15:8]=sbox_data_i; + next_col = (col_t); + W_var[127:96]=col_t^K_var[127:96]^{rcon_o,zero}; + W_var[95:64]=W_var[127:96]^K_var[95:64]; + W_var[63:32]=W_var[95:64]^K_var[63:32]; + W_var[31:0]=W_var[63:32]^K_var[31:0]; +next_ready_o = (1); +next_key_reg = (W_var); + next_state = (0); + end + +default: +begin + next_state = (0); + end +endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/mixcolum.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/mixcolum.v new file mode 100644 index 000000000..ab6dc1e67 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/mixcolum.v @@ -0,0 +1,188 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Mixcolumns module implementation //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// Mixcolum module //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: mixcolum.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + + +module mixcolum(clk,reset,decrypt_i,start_i,data_i,ready_o,data_o); +input clk; +input reset; +input decrypt_i; +input start_i; +input [127:0] data_i; +output ready_o; +output [127:0] data_o; + +reg ready_o; +reg [127:0] data_o; + +reg [127:0] data_reg; +reg [127:0] next_data_reg; +reg [127:0] data_o_reg; +reg [127:0] next_data_o; +reg next_ready_o; +reg [1:0] state; +reg [1:0] next_state; +wire [31:0] outx; + +wire [31:0] outy; + +reg [31:0] mix_word; +reg [31:0] outmux; + +word_mixcolum w1 (.in(mix_word), .outx(outx), .outy(outy)); + +//assign_data_o: +always @( data_o_reg) + +begin + + data_o = (data_o_reg); + +end +//mux: +always @( outx or outy or decrypt_i) + +begin + + outmux = (decrypt_i?outy:outx); + +end +//registers: +always @(posedge clk or negedge reset) + +begin + +if(!reset) + begin + data_reg = (0); + state = (0); + ready_o = (0); + data_o_reg = (0); + end +else + begin + data_reg = (next_data_reg); + state = (next_state); + ready_o = (next_ready_o); + data_o_reg = (next_data_o); + end + + +end +//mixcol: +reg[127:0] data_i_var; + reg[31:0] aux; + reg[127:0] data_reg_var; + +always @( decrypt_i or start_i or state or data_reg or outmux or data_o_reg or data_i) + +begin + + + data_i_var=data_i; + data_reg_var=data_reg; + next_data_reg = (data_reg); + next_state = (state); + + mix_word = (0); + + next_ready_o = (0); + next_data_o = (data_o_reg); + + case(state) + + 0: +begin + if(start_i) +begin + + aux=data_i_var[127:96]; + mix_word = (aux); + data_reg_var[127:96]=outmux; + next_data_reg = (data_reg_var); + next_state = (1); + +end + + end + 1: +begin + aux=data_i_var[95:64]; + mix_word = (aux); + data_reg_var[95:64]=outmux; + next_data_reg = (data_reg_var); + next_state = (2); + end + 2: +begin + aux=data_i_var[63:32]; + mix_word = (aux); + data_reg_var[63:32]=outmux; + next_data_reg = (data_reg_var); + next_state = (3); + end + 3: +begin + aux=data_i_var[31:0]; + mix_word = (aux); + data_reg_var[31:0]=outmux; + next_data_o = (data_reg_var); + next_ready_o = (1); + next_state = (0); + end + default: + begin + end + endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/sbox.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/sbox.v new file mode 100644 index 000000000..b5f741c30 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/sbox.v @@ -0,0 +1,392 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// S-Box calculation //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// S-box calculation calculating inverse on gallois field //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: sbox.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module sbox(clk,reset,data_i,decrypt_i,data_o); +input clk; +input reset; +input [7:0] data_i; +input decrypt_i; +output [7:0] data_o; + +reg [7:0] data_o; + +reg [7:0] inva; +reg [3:0] ah; +reg [3:0] al; +reg [3:0] ah2; +reg [3:0] al2; +reg [3:0] alxh; +reg [3:0] alph; +reg [3:0] d; +reg [3:0] ahp; +reg [3:0] alp; +reg [3:0] to_invert; +reg [3:0] next_to_invert; +reg [3:0] ah_reg; +reg [3:0] next_ah_reg; +reg [3:0] next_alph; + + +//registers: +always @(posedge clk or negedge reset) + +begin + +if(!reset) +begin + +to_invert = (0); + ah_reg = (0); +alph = (0); + +end +else +begin + + to_invert = (next_to_invert); + ah_reg = (next_ah_reg); +alph = (next_alph); + +end + + +end +//first_mux: +reg[7:0] first_mux_data_var; + reg[7:0] first_mux_InvInput; + reg[3:0] first_mux_ah_t,first_mux_al_t; + reg first_mux_aA,first_mux_aB,first_mux_aC,first_mux_aD; + +always @( data_i or decrypt_i) + +begin + + + first_mux_data_var=data_i; + first_mux_InvInput=first_mux_data_var; + + case(decrypt_i) + 1: +begin + //Applyinverseaffinetrasformation +first_mux_aA=first_mux_data_var[0]^first_mux_data_var[5];first_mux_aB=first_mux_data_var[1]^first_mux_data_var[4]; + first_mux_aC=first_mux_data_var[2]^first_mux_data_var[7];first_mux_aD=first_mux_data_var[3]^first_mux_data_var[6]; + first_mux_InvInput[0]=(!first_mux_data_var[5])^first_mux_aC; + first_mux_InvInput[1]=first_mux_data_var[0]^first_mux_aD; + first_mux_InvInput[2]=(!first_mux_data_var[7])^first_mux_aB; + first_mux_InvInput[3]=first_mux_data_var[2]^first_mux_aA; + first_mux_InvInput[4]=first_mux_data_var[1]^first_mux_aD; + first_mux_InvInput[5]=first_mux_data_var[4]^first_mux_aC; + first_mux_InvInput[6]=first_mux_data_var[3]^first_mux_aA; + first_mux_InvInput[7]=first_mux_data_var[6]^first_mux_aB; + end + default: +begin +first_mux_InvInput=first_mux_data_var; + end + endcase + + + //ConvertelementsfromGF(2^8)intotwoelementsofGF(2^4^2) + + first_mux_aA=first_mux_InvInput[1]^first_mux_InvInput[7]; + first_mux_aB=first_mux_InvInput[5]^first_mux_InvInput[7]; + first_mux_aC=first_mux_InvInput[4]^first_mux_InvInput[6]; + + + first_mux_al_t[0]=first_mux_aC^first_mux_InvInput[0]^first_mux_InvInput[5]; + first_mux_al_t[1]=first_mux_InvInput[1]^first_mux_InvInput[2]; + first_mux_al_t[2]=first_mux_aA; + first_mux_al_t[3]=first_mux_InvInput[2]^first_mux_InvInput[4]; + + first_mux_ah_t[0]=first_mux_aC^first_mux_InvInput[5]; + first_mux_ah_t[1]=first_mux_aA^first_mux_aC; + first_mux_ah_t[2]=first_mux_aB^first_mux_InvInput[2]^first_mux_InvInput[3]; + first_mux_ah_t[3]=first_mux_aB; + + al = (first_mux_al_t); + ah = (first_mux_ah_t); + next_ah_reg = (first_mux_ah_t); + +end +//end_mux: +reg[7:0] end_mux_data_var,end_mux_data_o_var; + reg end_mux_aA,end_mux_aB,end_mux_aC,end_mux_aD; + +always @( decrypt_i or inva) + +begin + + + + //Taketheoutputoftheinverter + end_mux_data_var=inva; + + case(decrypt_i) + 0: +begin + //Applyaffinetrasformation +end_mux_aA=end_mux_data_var[0]^end_mux_data_var[1];end_mux_aB=end_mux_data_var[2]^end_mux_data_var[3]; + end_mux_aC=end_mux_data_var[4]^end_mux_data_var[5];end_mux_aD=end_mux_data_var[6]^end_mux_data_var[7]; + end_mux_data_o_var[0]=(!end_mux_data_var[0])^end_mux_aC^end_mux_aD; + end_mux_data_o_var[1]=(!end_mux_data_var[5])^end_mux_aA^end_mux_aD; + end_mux_data_o_var[2]=end_mux_data_var[2]^end_mux_aA^end_mux_aD; + end_mux_data_o_var[3]=end_mux_data_var[7]^end_mux_aA^end_mux_aB; + end_mux_data_o_var[4]=end_mux_data_var[4]^end_mux_aA^end_mux_aB; + end_mux_data_o_var[5]=(!end_mux_data_var[1])^end_mux_aB^end_mux_aC; + end_mux_data_o_var[6]=(!end_mux_data_var[6])^end_mux_aB^end_mux_aC; + end_mux_data_o_var[7]=end_mux_data_var[3]^end_mux_aC^end_mux_aD; + data_o = (end_mux_data_o_var); + end + default: +begin +data_o = (end_mux_data_var); + end + endcase + + + +end +//inversemap: +reg[3:0] aA,aB; + reg[3:0] inversemap_alp_t,inversemap_ahp_t; + reg[7:0] inversemap_inva_t; + +always @( alp or ahp) +begin + + + inversemap_alp_t=alp; + inversemap_ahp_t=ahp; + + aA=inversemap_alp_t[1]^inversemap_ahp_t[3]; + aB=inversemap_ahp_t[0]^inversemap_ahp_t[1]; + + inversemap_inva_t[0]=inversemap_alp_t[0]^inversemap_ahp_t[0]; + inversemap_inva_t[1]=aB^inversemap_ahp_t[3]; + inversemap_inva_t[2]=aA^aB; + inversemap_inva_t[3]=aB^inversemap_alp_t[1]^inversemap_ahp_t[2]; + inversemap_inva_t[4]=aA^aB^inversemap_alp_t[3]; + inversemap_inva_t[5]=aB^inversemap_alp_t[2]; + inversemap_inva_t[6]=aA^inversemap_alp_t[2]^inversemap_alp_t[3]^inversemap_ahp_t[0]; + inversemap_inva_t[7]=aB^inversemap_alp_t[2]^inversemap_ahp_t[3]; + + inva = (inversemap_inva_t); + +end +//mul1: +reg[3:0] mul1_alxh_t; + reg[3:0] mul1_aA,mul1_a; + +always @( ah or al) + +begin + + //alxah + + mul1_aA=al[0]^al[3]; + mul1_a=al[2]^al[3]; + + mul1_alxh_t[0]=(al[0]&ah[0])^(al[3]&ah[1])^(al[2]&ah[2])^(al[1]&ah[3]); + mul1_alxh_t[1]=(al[1]&ah[0])^(mul1_aA&ah[1])^(mul1_a&ah[2])^((al[1]^al[2])&ah[3]); + mul1_alxh_t[2]=(al[2]&ah[0])^(al[1]&ah[1])^(mul1_aA&ah[2])^(mul1_a&ah[3]); + mul1_alxh_t[3]=(al[3]&ah[0])^(al[2]&ah[1])^(al[1]&ah[2])^(mul1_aA&ah[3]); + + alxh = (mul1_alxh_t); + +end +//mul2: +reg[3:0] mul2_ahp_t; + reg[3:0] mul2_aA,mul2_aB; + +always @( d or ah_reg) + +begin + + //ahxd + + mul2_aA=ah_reg[0]^ah_reg[3]; + mul2_aB=ah_reg[2]^ah_reg[3]; + + mul2_ahp_t[0]=(ah_reg[0]&d[0])^(ah_reg[3]&d[1])^(ah_reg[2]&d[2])^(ah_reg[1]&d[3]); + mul2_ahp_t[1]=(ah_reg[1]&d[0])^(mul2_aA&d[1])^(mul2_aB&d[2])^((ah_reg[1]^ah_reg[2])&d[3]); + mul2_ahp_t[2]=(ah_reg[2]&d[0])^(ah_reg[1]&d[1])^(mul2_aA&d[2])^(mul2_aB&d[3]); + mul2_ahp_t[3]=(ah_reg[3]&d[0])^(ah_reg[2]&d[1])^(ah_reg[1]&d[2])^(mul2_aA&d[3]); + + ahp = (mul2_ahp_t); + +end +//mul3: +reg[3:0] mul3_alp_t; + reg[3:0] mul3_aA,mul3_aB; + +always @( d or alph) + +begin + + //dxal + + mul3_aA=d[0]^d[3]; + mul3_aB=d[2]^d[3]; + + mul3_alp_t[0]=(d[0]&alph[0])^(d[3]&alph[1])^(d[2]&alph[2])^(d[1]&alph[3]); + mul3_alp_t[1]=(d[1]&alph[0])^(mul3_aA&alph[1])^(mul3_aB&alph[2])^((d[1]^d[2])&alph[3]); + mul3_alp_t[2]=(d[2]&alph[0])^(d[1]&alph[1])^(mul3_aA&alph[2])^(mul3_aB&alph[3]); + mul3_alp_t[3]=(d[3]&alph[0])^(d[2]&alph[1])^(d[1]&alph[2])^(mul3_aA&alph[3]); + + alp = (mul3_alp_t); + +end +//intermediate: +reg[3:0] intermediate_aA,intermediate_aB; + reg[3:0] intermediate_ah2e,intermediate_ah2epl2,intermediate_to_invert_var; + +always @( ah2 or al2 or alxh) + +begin + + + //ahsquareismultipliedwithe + intermediate_aA=ah2[0]^ah2[1]; + intermediate_aB=ah2[2]^ah2[3]; + intermediate_ah2e[0]=ah2[1]^intermediate_aB; + intermediate_ah2e[1]=intermediate_aA; + intermediate_ah2e[2]=intermediate_aA^ah2[2]; + intermediate_ah2e[3]=intermediate_aA^intermediate_aB; + + //Additionofintermediate_ah2eplusal2 + intermediate_ah2epl2[0]=intermediate_ah2e[0]^al2[0]; + intermediate_ah2epl2[1]=intermediate_ah2e[1]^al2[1]; + intermediate_ah2epl2[2]=intermediate_ah2e[2]^al2[2]; + intermediate_ah2epl2[3]=intermediate_ah2e[3]^al2[3]; + + //Additionoflastresultwiththeresultof(alxah) + intermediate_to_invert_var[0]=intermediate_ah2epl2[0]^alxh[0]; + intermediate_to_invert_var[1]=intermediate_ah2epl2[1]^alxh[1]; + intermediate_to_invert_var[2]=intermediate_ah2epl2[2]^alxh[2]; + intermediate_to_invert_var[3]=intermediate_ah2epl2[3]^alxh[3]; + +//Registers + next_to_invert = (intermediate_to_invert_var); + +end +//inversion: +reg[3:0] inversion_to_invert_var; + reg[3:0] inversion_aA,inversion_d_t; + +always @( to_invert) + +begin + + + inversion_to_invert_var=to_invert; + + //InverttheresultinGF(2^4) + inversion_aA=inversion_to_invert_var[1]^inversion_to_invert_var[2]^inversion_to_invert_var[3]^(inversion_to_invert_var[1]&inversion_to_invert_var[2]&inversion_to_invert_var[3]); + inversion_d_t[0]=inversion_aA^inversion_to_invert_var[0]^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^(inversion_to_invert_var[1]&inversion_to_invert_var[2])^(inversion_to_invert_var[0]&inversion_to_invert_var[1]&inversion_to_invert_var[2]); + inversion_d_t[1]=(inversion_to_invert_var[0]&inversion_to_invert_var[1])^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^(inversion_to_invert_var[1]&inversion_to_invert_var[2])^inversion_to_invert_var[3]^(inversion_to_invert_var[1]&inversion_to_invert_var[3])^(inversion_to_invert_var[0]&inversion_to_invert_var[1]&inversion_to_invert_var[3]); + inversion_d_t[2]=(inversion_to_invert_var[0]&inversion_to_invert_var[1])^inversion_to_invert_var[2]^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^inversion_to_invert_var[3]^(inversion_to_invert_var[0]&inversion_to_invert_var[3])^(inversion_to_invert_var[0]&inversion_to_invert_var[2]&inversion_to_invert_var[3]); + inversion_d_t[3]=inversion_aA^(inversion_to_invert_var[0]&inversion_to_invert_var[3])^(inversion_to_invert_var[1]&inversion_to_invert_var[3])^(inversion_to_invert_var[2]&inversion_to_invert_var[3]); + + d = (inversion_d_t); + + +end +//sum1: +reg[3:0] sum1_alph_t; + +always @( ah or al) + +begin + + + sum1_alph_t[0]=al[0]^ah[0]; + sum1_alph_t[1]=al[1]^ah[1]; + sum1_alph_t[2]=al[2]^ah[2]; + sum1_alph_t[3]=al[3]^ah[3]; + + next_alph = (sum1_alph_t); + +end +//square1: +reg[3:0] square1_ah_t; + +always @( ah) + +begin + + + square1_ah_t[0]=ah[0]^ah[2]; + square1_ah_t[1]=ah[2]; + square1_ah_t[2]=ah[1]^ah[3]; + square1_ah_t[3]=ah[3]; + + ah2 = (square1_ah_t); + +end +//square2: +reg[3:0] square2_al_t; + +always @( al) + +begin + + + square2_al_t[0]=al[0]^al[2]; + square2_al_t[1]=al[2]; + square2_al_t[2]=al[1]^al[3]; + square2_al_t[3]=al[3]; + + al2 = (square2_al_t); + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/subbytes.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/subbytes.v new file mode 100644 index 000000000..eb0470bfe --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/subbytes.v @@ -0,0 +1,254 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Subbytes module implementation //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// Subbytes module implementation //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: subbytes.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module subbytes(clk,reset,start_i,decrypt_i,data_i,ready_o,data_o,sbox_data_o,sbox_data_i,sbox_decrypt_o); +input clk; +input reset; +input start_i; +input decrypt_i; +input [127:0] data_i; +output ready_o; +output [127:0] data_o; +output [7:0] sbox_data_o; +input [7:0] sbox_data_i; +output sbox_decrypt_o; + +reg ready_o; +reg [127:0] data_o; +reg [7:0] sbox_data_o; +reg sbox_decrypt_o; + +reg [4:0] state; +reg [4:0] next_state; +reg [127:0] data_reg; +reg [127:0] next_data_reg; +reg next_ready_o; + +`define assign_array_to_128 \ + data_reg_128[127:120]=data_reg_var[0]; \ + data_reg_128[119:112]=data_reg_var[1]; \ + data_reg_128[111:104]=data_reg_var[2]; \ + data_reg_128[103:96]=data_reg_var[3]; \ + data_reg_128[95:88]=data_reg_var[4]; \ + data_reg_128[87:80]=data_reg_var[5]; \ + data_reg_128[79:72]=data_reg_var[6]; \ + data_reg_128[71:64]=data_reg_var[7]; \ + data_reg_128[63:56]=data_reg_var[8]; \ + data_reg_128[55:48]=data_reg_var[9]; \ + data_reg_128[47:40]=data_reg_var[10]; \ + data_reg_128[39:32]=data_reg_var[11]; \ + data_reg_128[31:24]=data_reg_var[12]; \ + data_reg_128[23:16]=data_reg_var[13]; \ + data_reg_128[15:8]=data_reg_var[14]; \ + data_reg_128[7:0]=data_reg_var[15]; + +`define shift_array_to_128 \ + data_reg_128[127:120]=data_reg_var[0]; \ + data_reg_128[119:112]=data_reg_var[5]; \ + data_reg_128[111:104]=data_reg_var[10]; \ + data_reg_128[103:96]=data_reg_var[15]; \ + data_reg_128[95:88]=data_reg_var[4]; \ + data_reg_128[87:80]=data_reg_var[9]; \ + data_reg_128[79:72]=data_reg_var[14]; \ + data_reg_128[71:64]=data_reg_var[3]; \ + data_reg_128[63:56]=data_reg_var[8]; \ + data_reg_128[55:48]=data_reg_var[13]; \ + data_reg_128[47:40]=data_reg_var[2]; \ + data_reg_128[39:32]=data_reg_var[7]; \ + data_reg_128[31:24]=data_reg_var[12]; \ + data_reg_128[23:16]=data_reg_var[1]; \ + data_reg_128[15:8]=data_reg_var[6]; \ + data_reg_128[7:0]=data_reg_var[11]; + +`define invert_shift_array_to_128 \ + data_reg_128[127:120]=data_reg_var[0]; \ + data_reg_128[119:112]=data_reg_var[13]; \ + data_reg_128[111:104]=data_reg_var[10]; \ + data_reg_128[103:96]=data_reg_var[7]; \ + data_reg_128[95:88]=data_reg_var[4]; \ + data_reg_128[87:80]=data_reg_var[1]; \ + data_reg_128[79:72]=data_reg_var[14]; \ + data_reg_128[71:64]=data_reg_var[11]; \ + data_reg_128[63:56]=data_reg_var[8]; \ + data_reg_128[55:48]=data_reg_var[5]; \ + data_reg_128[47:40]=data_reg_var[2]; \ + data_reg_128[39:32]=data_reg_var[15]; \ + data_reg_128[31:24]=data_reg_var[12]; \ + data_reg_128[23:16]=data_reg_var[9]; \ + data_reg_128[15:8]=data_reg_var[6]; \ + data_reg_128[7:0]=data_reg_var[3]; + + +//registers: +always @(posedge clk or negedge reset) + +begin + +if(!reset) +begin + + data_reg = (0); + state = (0); + ready_o = (0); + +end +else +begin + + data_reg = (next_data_reg); + state = (next_state); + ready_o = (next_ready_o); + +end + + +end +//sub: +reg[127:0] data_i_var,data_reg_128; +reg[7:0] data_array[15:0],data_reg_var[15:0]; + +always @( decrypt_i or start_i or state or data_i or sbox_data_i or data_reg) + +begin + + + data_i_var=data_i; + + data_array[0]=data_i_var[127:120]; + data_array[1]=data_i_var[119:112]; + data_array[2]=data_i_var[111:104]; + data_array[3]=data_i_var[103:96]; + data_array[4]=data_i_var[95:88]; + data_array[5]=data_i_var[87:80]; + data_array[6]=data_i_var[79:72]; + data_array[7]=data_i_var[71:64]; + data_array[8]=data_i_var[63:56]; + data_array[9]=data_i_var[55:48]; + data_array[10]=data_i_var[47:40]; + data_array[11]=data_i_var[39:32]; + data_array[12]=data_i_var[31:24]; + data_array[13]=data_i_var[23:16]; + data_array[14]=data_i_var[15:8]; + data_array[15]=data_i_var[7:0]; + + data_reg_var[0]=data_reg[127:120]; + data_reg_var[1]=data_reg[119:112]; + data_reg_var[2]=data_reg[111:104]; + data_reg_var[3]=data_reg[103:96]; + data_reg_var[4]=data_reg[95:88]; + data_reg_var[5]=data_reg[87:80]; + data_reg_var[6]=data_reg[79:72]; + data_reg_var[7]=data_reg[71:64]; + data_reg_var[8]=data_reg[63:56]; + data_reg_var[9]=data_reg[55:48]; + data_reg_var[10]=data_reg[47:40]; + data_reg_var[11]=data_reg[39:32]; + data_reg_var[12]=data_reg[31:24]; + data_reg_var[13]=data_reg[23:16]; + data_reg_var[14]=data_reg[15:8]; + data_reg_var[15]=data_reg[7:0]; + + + sbox_decrypt_o = (decrypt_i); + sbox_data_o = (0); + next_state = (state); + next_data_reg = (data_reg); + + next_ready_o = (0); + data_o = (data_reg); + + case(state) + + 0: +begin + if(start_i) +begin + +sbox_data_o = (data_array[0]); + next_state = (1); + +end + + end + 16: +begin + data_reg_var[15]=sbox_data_i; + //Makeshiftrowsstage + case(decrypt_i) + 0: + begin + `shift_array_to_128 + end + 1: + begin + `invert_shift_array_to_128 + end + endcase + + next_data_reg = (data_reg_128); + next_ready_o = (1); + next_state = (0); + end + default: + begin + sbox_data_o = (data_array[state]); + data_reg_var[state-1]=sbox_data_i; + `assign_array_to_128 + next_data_reg = (data_reg_128); + next_state = (state+1); + end + +endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/timescale.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/timescale.v new file mode 100644 index 000000000..ff9e265a8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps diff --git a/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/word_mixcolum.v b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/word_mixcolum.v new file mode 100644 index 000000000..9308ccc9b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/word_mixcolum.v @@ -0,0 +1,124 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Mixcolumns for a 16 bit word module implementation //// +//// //// +//// This file is part of the SystemC AES //// +//// //// +//// Description: //// +//// Mixcolum for a 16 bit word //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: word_mixcolum.v,v $ +// Revision 1.1.1.1 2004/07/05 09:46:23 jcastillo +// First import +// + +module word_mixcolum(in,outx,outy); +input [31:0] in; +output [31:0] outx; +output [31:0] outy; + +reg [31:0] outx; +reg [31:0] outy; + +reg [7:0] a; +reg [7:0] b; +reg [7:0] c; +reg [7:0] d; +wire [7:0] x1; + +wire [7:0] x2; + +wire [7:0] x3; + +wire [7:0] x4; + +wire [7:0] y1; + +wire [7:0] y2; + +wire [7:0] y3; + +wire [7:0] y4; + + +byte_mixcolum bm1 (.a(a), .b(b), .c(c), .d(d), .outx(x1), .outy(y1)); +byte_mixcolum bm2 (.a(b), .b(c), .c(d), .d(a), .outx(x2), .outy(y2)); +byte_mixcolum bm3 (.a(c), .b(d), .c(a), .d(b), .outx(x3), .outy(y3)); +byte_mixcolum bm4 (.a(d), .b(a), .c(b), .d(c), .outx(x4), .outy(y4)); + + + reg[31:0] in_var; + reg[31:0] outx_var,outy_var; +//split: +always @( in) + +begin + + + + in_var=in; + a = (in_var[31:24]); + b = (in_var[23:16]); + c = (in_var[15:8]); + d = (in_var[7:0]); + +end +//mix: +always @( x1 or x2 or x3 or x4 or y1 or y2 or y3 or y4) + +begin + + + + outx_var[31:24]=x1; + outx_var[23:16]=x2; + outx_var[15:8]=x3; + outx_var[7:0]=x4; + outy_var[31:24]=y1; + outy_var[23:16]=y2; + outy_var[15:8]=y3; + outy_var[7:0]=y4; + + outx = (outx_var); + outy = (outy_var); + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/des.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/des.v new file mode 100644 index 000000000..3147cb01d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/des.v @@ -0,0 +1,284 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES Top //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Top file of DES project //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: des.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module des(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o); +input clk; +input reset; +input load_i; +input decrypt_i; +input [63:0] data_i; +input [63:0] key_i; +output [63:0] data_o; +output ready_o; + +reg [63:0] data_o; +reg ready_o; + + +reg [3:0] stage1_iter; + +reg [3:0] next_stage1_iter; + +reg next_ready_o; + +reg[63:0] next_data_o; + +reg data_ready; + +reg next_data_ready; + +reg [31:0] stage1_L_i; + +reg [31:0] stage1_R_i; + +reg [55:0] stage1_round_key_i; + +reg [3:0] stage1_iteration_i; +wire [31:0] stage1_R_o; +wire [31:0] stage1_L_o; +wire [55:0] stage1_round_key_o; +wire [5:0] s1_stag1_i; +wire [5:0] s2_stag1_i; +wire [5:0] s3_stag1_i; +wire [5:0] s4_stag1_i; +wire [5:0] s5_stag1_i; +wire [5:0] s6_stag1_i; +wire [5:0] s7_stag1_i; +wire [5:0] s8_stag1_i; +wire [3:0] s1_stag1_o; +wire [3:0] s2_stag1_o; +wire [3:0] s3_stag1_o; +wire [3:0] s4_stag1_o; +wire [3:0] s5_stag1_o; +wire [3:0] s6_stag1_o; +wire [3:0] s7_stag1_o; +wire [3:0] s8_stag1_o; + +reg[31:0] L_i_var,R_i_var; +reg[63:0] data_i_var,data_o_var,data_o_var_t,key_i_var; +reg[55:0] key_var_perm; + + +desround rd1 (.clk(clk), .reset(reset), .iteration_i(stage1_iteration_i), .decrypt_i(decrypt_i), .R_i(stage1_R_i), .L_i(stage1_L_i), .Key_i(stage1_round_key_i), .R_o(stage1_R_o), .L_o(stage1_L_o), .Key_o(stage1_round_key_o), .s1_o(s1_stag1_i), .s2_o(s2_stag1_i), .s3_o(s3_stag1_i), .s4_o(s4_stag1_i), .s5_o(s5_stag1_i), .s6_o(s6_stag1_i), .s7_o(s7_stag1_i), .s8_o(s8_stag1_i), .s1_i(s1_stag1_o), .s2_i(s2_stag1_o), .s3_i(s3_stag1_o), .s4_i(s4_stag1_o), .s5_i(s5_stag1_o), .s6_i(s6_stag1_o), .s7_i(s7_stag1_o), .s8_i(s8_stag1_o)); +s1 sbox1 (.stage1_input(s1_stag1_i), .stage1_output(s1_stag1_o)); +s2 sbox2 (.stage1_input(s2_stag1_i), .stage1_output(s2_stag1_o)); +s3 sbox3 (.stage1_input(s3_stag1_i), .stage1_output(s3_stag1_o)); +s4 sbox4 (.stage1_input(s4_stag1_i), .stage1_output(s4_stag1_o)); +s5 sbox5 (.stage1_input(s5_stag1_i), .stage1_output(s5_stag1_o)); +s6 sbox6 (.stage1_input(s6_stag1_i), .stage1_output(s6_stag1_o)); +s7 sbox7 (.stage1_input(s7_stag1_i), .stage1_output(s7_stag1_o)); +s8 sbox8 (.stage1_input(s8_stag1_i), .stage1_output(s8_stag1_o)); + +always @(posedge clk or negedge reset) + +begin + + if(!reset) + begin + + ready_o = (0); + data_o = (0); + stage1_iter = (0); + data_ready = (1); + + end + else + begin + + ready_o = (next_ready_o); + data_o = (next_data_o); + stage1_iter = (next_stage1_iter); + data_ready = (next_data_ready); + + end +end + + +always @( data_i or key_i or load_i or stage1_iter or data_ready or stage1_R_o or stage1_L_o or stage1_round_key_o) + +begin + + + + L_i_var=0; + R_i_var=0; + data_i_var=0; + + next_ready_o = (0); + next_data_ready = (data_ready); + next_stage1_iter = (stage1_iter); + + stage1_L_i = (0); + stage1_R_i = (0); + stage1_round_key_i = (0); + + + key_i_var=key_i; + + key_var_perm[55]=key_i_var[7];key_var_perm[54]=key_i_var[15];key_var_perm[53]=key_i_var[23];key_var_perm[52]=key_i_var[31]; + key_var_perm[51]=key_i_var[39];key_var_perm[50]=key_i_var[47];key_var_perm[49]=key_i_var[55];key_var_perm[48]=key_i_var[63]; + + key_var_perm[47]=key_i_var[6];key_var_perm[46]=key_i_var[14];key_var_perm[45]=key_i_var[22];key_var_perm[44]=key_i_var[30]; + key_var_perm[43]=key_i_var[38];key_var_perm[42]=key_i_var[46];key_var_perm[41]=key_i_var[54];key_var_perm[40]=key_i_var[62]; + + key_var_perm[39]=key_i_var[5];key_var_perm[38]=key_i_var[13];key_var_perm[37]=key_i_var[21];key_var_perm[36]=key_i_var[29]; + key_var_perm[35]=key_i_var[37];key_var_perm[34]=key_i_var[45];key_var_perm[33]=key_i_var[53];key_var_perm[32]=key_i_var[61]; + + key_var_perm[31]=key_i_var[4];key_var_perm[30]=key_i_var[12];key_var_perm[29]=key_i_var[20];key_var_perm[28]=key_i_var[28]; + key_var_perm[27]=key_i_var[1];key_var_perm[26]=key_i_var[9];key_var_perm[25]=key_i_var[17];key_var_perm[24]=key_i_var[25]; + + key_var_perm[23]=key_i_var[33];key_var_perm[22]=key_i_var[41];key_var_perm[21]=key_i_var[49];key_var_perm[20]=key_i_var[57]; + key_var_perm[19]=key_i_var[2];key_var_perm[18]=key_i_var[10];key_var_perm[17]=key_i_var[18];key_var_perm[16]=key_i_var[26]; + + key_var_perm[15]=key_i_var[34];key_var_perm[14]=key_i_var[42];key_var_perm[13]=key_i_var[50];key_var_perm[12]=key_i_var[58]; + key_var_perm[11]=key_i_var[3];key_var_perm[10]=key_i_var[11];key_var_perm[9]=key_i_var[19];key_var_perm[8]=key_i_var[27]; + + key_var_perm[7]=key_i_var[35];key_var_perm[6]=key_i_var[43];key_var_perm[5]=key_i_var[51];key_var_perm[4]=key_i_var[59]; + key_var_perm[3]=key_i_var[36];key_var_perm[2]=key_i_var[44];key_var_perm[1]=key_i_var[52];key_var_perm[0]=key_i_var[60]; + + + data_i_var=data_i; + L_i_var[31]=data_i_var[6];L_i_var[30]=data_i_var[14];L_i_var[29]=data_i_var[22];L_i_var[28]=data_i_var[30]; + L_i_var[27]=data_i_var[38];L_i_var[26]=data_i_var[46];L_i_var[25]=data_i_var[54];L_i_var[24]=data_i_var[62]; + + L_i_var[23]=data_i_var[4];L_i_var[22]=data_i_var[12];L_i_var[21]=data_i_var[20];L_i_var[20]=data_i_var[28]; + L_i_var[19]=data_i_var[36];L_i_var[18]=data_i_var[44];L_i_var[17]=data_i_var[52];L_i_var[16]=data_i_var[60]; + + L_i_var[15]=data_i_var[2];L_i_var[14]=data_i_var[10];L_i_var[13]=data_i_var[18];L_i_var[12]=data_i_var[26]; + L_i_var[11]=data_i_var[34];L_i_var[10]=data_i_var[42];L_i_var[9]=data_i_var[50];L_i_var[8]=data_i_var[58]; + + L_i_var[7]=data_i_var[0];L_i_var[6]=data_i_var[8];L_i_var[5]=data_i_var[16];L_i_var[4]=data_i_var[24]; + L_i_var[3]=data_i_var[32];L_i_var[2]=data_i_var[40];L_i_var[1]=data_i_var[48];L_i_var[0]=data_i_var[56]; + + R_i_var[31]=data_i_var[7];R_i_var[30]=data_i_var[15];R_i_var[29]=data_i_var[23];R_i_var[28]=data_i_var[31]; + R_i_var[27]=data_i_var[39];R_i_var[26]=data_i_var[47];R_i_var[25]=data_i_var[55];R_i_var[24]=data_i_var[63]; + + R_i_var[23]=data_i_var[5];R_i_var[22]=data_i_var[13];R_i_var[21]=data_i_var[21];R_i_var[20]=data_i_var[29]; + R_i_var[19]=data_i_var[37];R_i_var[18]=data_i_var[45];R_i_var[17]=data_i_var[53];R_i_var[16]=data_i_var[61]; + + R_i_var[15]=data_i_var[3];R_i_var[14]=data_i_var[11];R_i_var[13]=data_i_var[19];R_i_var[12]=data_i_var[27]; + R_i_var[11]=data_i_var[35];R_i_var[10]=data_i_var[43];R_i_var[9]=data_i_var[51];R_i_var[8]=data_i_var[59]; + + R_i_var[7]=data_i_var[1];R_i_var[6]=data_i_var[9];R_i_var[5]=data_i_var[17];R_i_var[4]=data_i_var[25]; + R_i_var[3]=data_i_var[33];R_i_var[2]=data_i_var[41];R_i_var[1]=data_i_var[49];R_i_var[0]=data_i_var[57]; + + + + data_o_var_t[63:32]=stage1_R_o; + data_o_var_t[31:0]=stage1_L_o; + + data_o_var[63]=data_o_var_t[24];data_o_var[62]=data_o_var_t[56];data_o_var[61]=data_o_var_t[16];data_o_var[60]=data_o_var_t[48]; + data_o_var[59]=data_o_var_t[8];data_o_var[58]=data_o_var_t[40];data_o_var[57]=data_o_var_t[0];data_o_var[56]=data_o_var_t[32]; + + data_o_var[55]=data_o_var_t[25];data_o_var[54]=data_o_var_t[57];data_o_var[53]=data_o_var_t[17];data_o_var[52]=data_o_var_t[49]; + data_o_var[51]=data_o_var_t[9];data_o_var[50]=data_o_var_t[41];data_o_var[49]=data_o_var_t[1];data_o_var[48]=data_o_var_t[33]; + + data_o_var[47]=data_o_var_t[26];data_o_var[46]=data_o_var_t[58];data_o_var[45]=data_o_var_t[18];data_o_var[44]=data_o_var_t[50]; + data_o_var[43]=data_o_var_t[10];data_o_var[42]=data_o_var_t[42];data_o_var[41]=data_o_var_t[2];data_o_var[40]=data_o_var_t[34]; + + data_o_var[39]=data_o_var_t[27];data_o_var[38]=data_o_var_t[59];data_o_var[37]=data_o_var_t[19];data_o_var[36]=data_o_var_t[51]; + data_o_var[35]=data_o_var_t[11];data_o_var[34]=data_o_var_t[43];data_o_var[33]=data_o_var_t[3];data_o_var[32]=data_o_var_t[35]; + + data_o_var[31]=data_o_var_t[28];data_o_var[30]=data_o_var_t[60];data_o_var[29]=data_o_var_t[20];data_o_var[28]=data_o_var_t[52]; + data_o_var[27]=data_o_var_t[12];data_o_var[26]=data_o_var_t[44];data_o_var[25]=data_o_var_t[4];data_o_var[24]=data_o_var_t[36]; + + data_o_var[23]=data_o_var_t[29];data_o_var[22]=data_o_var_t[61];data_o_var[21]=data_o_var_t[21];data_o_var[20]=data_o_var_t[53]; + data_o_var[19]=data_o_var_t[13];data_o_var[18]=data_o_var_t[45];data_o_var[17]=data_o_var_t[5];data_o_var[16]=data_o_var_t[37]; + + data_o_var[15]=data_o_var_t[30];data_o_var[14]=data_o_var_t[62];data_o_var[13]=data_o_var_t[22];data_o_var[12]=data_o_var_t[54]; + data_o_var[11]=data_o_var_t[14];data_o_var[10]=data_o_var_t[46];data_o_var[9]=data_o_var_t[6];data_o_var[8]=data_o_var_t[38]; + + data_o_var[7]=data_o_var_t[31];data_o_var[6]=data_o_var_t[63];data_o_var[5]=data_o_var_t[23];data_o_var[4]=data_o_var_t[55]; + data_o_var[3]=data_o_var_t[15];data_o_var[2]=data_o_var_t[47];data_o_var[1]=data_o_var_t[7];data_o_var[0]=data_o_var_t[39]; + + next_data_o = (data_o_var); + + stage1_iteration_i = (stage1_iter); + + next_ready_o = (0); + stage1_L_i = (stage1_L_o); + stage1_R_i = (stage1_R_o); + stage1_round_key_i = (stage1_round_key_o); + + case(stage1_iter) + + 0: + begin + if(load_i) + begin + next_stage1_iter = (1); + stage1_L_i = (L_i_var); + stage1_R_i = (R_i_var); + stage1_round_key_i = (key_var_perm); + next_data_ready = (0); + end + else if (!data_ready) + begin + + next_stage1_iter = (0); + next_ready_o = (1); + next_data_ready = (1); + end + end + + 15: + next_stage1_iter = (0); + + default: + next_stage1_iter = (stage1_iter+1); + +endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/desround.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/desround.v new file mode 100644 index 000000000..bc817b5b3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/desround.v @@ -0,0 +1,223 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// DES Round //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Performs a round of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: desround.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:16 jcastillo +// First import +// + + +module desround(clk,reset,iteration_i,decrypt_i,R_i,L_i,Key_i,R_o,L_o,Key_o,s1_o,s2_o,s3_o,s4_o,s5_o,s6_o,s7_o,s8_o,s1_i,s2_i,s3_i,s4_i,s5_i,s6_i,s7_i,s8_i); + +input clk; +input reset; +input [3:0] iteration_i; +input decrypt_i; +input [31:0] R_i; +input [31:0] L_i; +input [55:0] Key_i; +output [31:0] R_o; +output [31:0] L_o; +output [55:0] Key_o; +output [5:0] s1_o; +output [5:0] s2_o; +output [5:0] s3_o; +output [5:0] s4_o; +output [5:0] s5_o; +output [5:0] s6_o; +output [5:0] s7_o; +output [5:0] s8_o; +input [3:0] s1_i; +input [3:0] s2_i; +input [3:0] s3_i; +input [3:0] s4_i; +input [3:0] s5_i; +input [3:0] s6_i; +input [3:0] s7_i; +input [3:0] s8_i; + +reg [31:0] R_o; +reg [31:0] L_o; +reg [55:0] Key_o; +reg [5:0] s1_o; +reg [5:0] s2_o; +reg [5:0] s3_o; +reg [5:0] s4_o; +reg [5:0] s5_o; +reg [5:0] s6_o; +reg [5:0] s7_o; +reg [5:0] s8_o; + + + +reg [55:0] previous_key; + +reg [3:0] iteration; + +reg decrypt; + + + +wire [55:0] non_perm_key; + + + +wire [47:0] new_key; + +reg [31:0] next_R; + +reg [31:0] expanRSig; + + reg[47:0] expandedR; + reg[47:0] round_key; + reg[47:0] KER; + reg[31:0] R_i_var; + + reg[31:0] Soutput; + reg[31:0] f; + + +key_gen kg1 (.previous_key(previous_key), .iteration(iteration), .decrypt(decrypt), .new_key(new_key), .non_perm_key(non_perm_key)); + +always @(posedge clk or negedge reset) + +begin + + + if(!reset) + begin + + L_o = (0); + R_o = (0); + Key_o = (0); + + end + else + begin + + L_o = (R_i); + R_o = (next_R); + Key_o = (non_perm_key); + + end + +end + +always @( R_i or L_i or Key_i or iteration_i or decrypt_i or new_key or s1_i or s2_i or s3_i or s4_i or s5_i or s6_i or s7_i or s8_i) + +begin + + R_i_var=R_i; + + + expandedR[47]=R_i_var[0]; expandedR[46]=R_i_var[31]; expandedR[45]=R_i_var[30]; expandedR[44]=R_i_var[29]; + expandedR[43]=R_i_var[28]; expandedR[42]=R_i_var[27]; expandedR[41]=R_i_var[28]; expandedR[40]=R_i_var[27]; + + expandedR[39]=R_i_var[26]; expandedR[38]=R_i_var[25]; expandedR[37]=R_i_var[24]; expandedR[36]=R_i_var[23]; + expandedR[35]=R_i_var[24]; expandedR[34]=R_i_var[23]; expandedR[33]=R_i_var[22]; expandedR[32]=R_i_var[21]; + + expandedR[31]=R_i_var[20]; expandedR[30]=R_i_var[19]; expandedR[29]=R_i_var[20]; expandedR[28]=R_i_var[19]; + expandedR[27]=R_i_var[18]; expandedR[26]=R_i_var[17]; expandedR[25]=R_i_var[16]; expandedR[24]=R_i_var[15]; + + expandedR[23]=R_i_var[16]; expandedR[22]=R_i_var[15]; expandedR[21]=R_i_var[14]; expandedR[20]=R_i_var[13]; + expandedR[19]=R_i_var[12]; expandedR[18]=R_i_var[11]; expandedR[17]=R_i_var[12]; expandedR[16]=R_i_var[11]; + + expandedR[15]=R_i_var[10]; expandedR[14]=R_i_var[9]; expandedR[13]=R_i_var[8]; expandedR[12]=R_i_var[7]; + expandedR[11]=R_i_var[8]; expandedR[10]=R_i_var[7]; expandedR[9]=R_i_var[6]; expandedR[8]=R_i_var[5]; + + expandedR[7]=R_i_var[4]; expandedR[6]=R_i_var[3]; expandedR[5]=R_i_var[4]; expandedR[4]=R_i_var[3]; + expandedR[3]=R_i_var[2]; expandedR[2]=R_i_var[1]; expandedR[1]=R_i_var[0]; expandedR[0]=R_i_var[31]; + + + previous_key = (Key_i); + iteration = (iteration_i); + decrypt = (decrypt_i); + + round_key=new_key; + + KER=expandedR^round_key; + + + s1_o = (KER[47:42]); + s2_o = (KER[41:36]); + s3_o = (KER[35:30]); + s4_o = (KER[29:24]); + s5_o = (KER[23:18]); + s6_o = (KER[17:12]); + s7_o = (KER[11:6]); + s8_o = (KER[5:0]); + + Soutput[31:28]=s1_i; + Soutput[27:24]=s2_i; + Soutput[23:20]=s3_i; + Soutput[19:16]=s4_i; + Soutput[15:12]=s5_i; + Soutput[11:8]=s6_i; + Soutput[7:4]=s7_i; + Soutput[3:0]=s8_i; + + + + f[31]=Soutput[16]; f[30]=Soutput[25]; f[29]=Soutput[12]; f[28]=Soutput[11]; + f[27]=Soutput[3]; f[26]=Soutput[20]; f[25]=Soutput[4]; f[24]=Soutput[15]; + + f[23]=Soutput[31]; f[22]=Soutput[17]; f[21]=Soutput[9]; f[20]=Soutput[6]; + f[19]=Soutput[27]; f[18]=Soutput[14]; f[17]=Soutput[1]; f[16]=Soutput[22]; + + f[15]=Soutput[30]; f[14]=Soutput[24]; f[13]=Soutput[8]; f[12]=Soutput[18]; + f[11]=Soutput[0]; f[10]=Soutput[5]; f[9]=Soutput[29]; f[8]=Soutput[23]; + + f[7]=Soutput[13]; f[6]=Soutput[19]; f[5]=Soutput[2]; f[4]=Soutput[26]; + f[3]=Soutput[10]; f[2]=Soutput[21]; f[1]=Soutput[28]; f[0]=Soutput[7]; + + next_R = (L_i^f); + + expanRSig = (L_i^f); + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/key_gen.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/key_gen.v new file mode 100644 index 000000000..523df364a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/key_gen.v @@ -0,0 +1,192 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Key generator //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Generate the next key from the previous one //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: key_gen.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module key_gen(previous_key,iteration,decrypt,non_perm_key,new_key); + +input [55:0] previous_key; +input [3:0] iteration; +input decrypt; +output [55:0] non_perm_key; +output [47:0] new_key; + +reg [55:0] non_perm_key; +reg [47:0] new_key; + + +reg prev0,prev1; +reg[55:0] prev_key_var,non_perm_key_var; +reg[47:0] new_key_var; +reg[27:0] semi_key; + + +always @( previous_key or iteration or decrypt) + +begin + + + + prev_key_var=previous_key; + new_key_var=0; + new_key = (0); + non_perm_key_var=0; + non_perm_key = (0); + + if(!decrypt) + begin + case(iteration) + + 0, 1, 8, 15: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[27]; + semi_key=semi_key<<1; + semi_key[0]=prev0; + non_perm_key_var[27:0]=semi_key; + end + default: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[27]; + prev1=semi_key[26]; + semi_key=semi_key<<2; + semi_key[1]=prev0; + semi_key[0]=prev1; + non_perm_key_var[27:0]=semi_key; + end + + endcase + end + else + begin + case(iteration) + + 0: + begin + semi_key=prev_key_var[55:28]; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + non_perm_key_var[27:0]=semi_key; + end + 1, 8, 15: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[0]; + semi_key=semi_key>>1; + semi_key[27]=prev0; + non_perm_key_var[27:0]=semi_key; + end + default: + begin + semi_key=prev_key_var[55:28]; + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var[55:28]=semi_key; + semi_key=prev_key_var[27:0]; + prev0=semi_key[0]; + prev1=semi_key[1]; + semi_key=semi_key>>2; + semi_key[26]=prev0; + semi_key[27]=prev1; + non_perm_key_var[27:0]=semi_key; + end + + endcase + end + + + non_perm_key = (non_perm_key_var); + + + new_key_var[47]=non_perm_key_var[42]; new_key_var[46]=non_perm_key_var[39]; new_key_var[45]=non_perm_key_var[45]; new_key_var[44]=non_perm_key_var[32]; + new_key_var[43]=non_perm_key_var[55]; new_key_var[42]=non_perm_key_var[51]; new_key_var[41]=non_perm_key_var[53]; new_key_var[40]=non_perm_key_var[28]; + + new_key_var[39]=non_perm_key_var[41]; new_key_var[38]=non_perm_key_var[50]; new_key_var[37]=non_perm_key_var[35]; new_key_var[36]=non_perm_key_var[46]; + new_key_var[35]=non_perm_key_var[33]; new_key_var[34]=non_perm_key_var[37]; new_key_var[33]=non_perm_key_var[44]; new_key_var[32]=non_perm_key_var[52]; + + new_key_var[31]=non_perm_key_var[30]; new_key_var[30]=non_perm_key_var[48]; new_key_var[29]=non_perm_key_var[40]; new_key_var[28]=non_perm_key_var[49]; + new_key_var[27]=non_perm_key_var[29]; new_key_var[26]=non_perm_key_var[36]; new_key_var[25]=non_perm_key_var[43]; new_key_var[24]=non_perm_key_var[54]; + + new_key_var[23]=non_perm_key_var[15]; new_key_var[22]=non_perm_key_var[4]; new_key_var[21]=non_perm_key_var[25]; new_key_var[20]=non_perm_key_var[19]; + new_key_var[19]=non_perm_key_var[9]; new_key_var[18]=non_perm_key_var[1]; new_key_var[17]=non_perm_key_var[26]; new_key_var[16]=non_perm_key_var[16]; + + new_key_var[15]=non_perm_key_var[5]; new_key_var[14]=non_perm_key_var[11]; new_key_var[13]=non_perm_key_var[23]; new_key_var[12]=non_perm_key_var[8]; + new_key_var[11]=non_perm_key_var[12]; new_key_var[10]=non_perm_key_var[7]; new_key_var[9]=non_perm_key_var[17]; new_key_var[8]=non_perm_key_var[0]; + + new_key_var[7]=non_perm_key_var[22]; new_key_var[6]=non_perm_key_var[3]; new_key_var[5]=non_perm_key_var[10]; new_key_var[4]=non_perm_key_var[14]; + new_key_var[3]=non_perm_key_var[6]; new_key_var[2]=non_perm_key_var[20]; new_key_var[1]=non_perm_key_var[27]; new_key_var[0]=non_perm_key_var[24]; + + new_key = (new_key_var); + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s1.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s1.v new file mode 100644 index 000000000..a45f2e72a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s1.v @@ -0,0 +1,137 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 1 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s1.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s1(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + + case(stage1_input) + 0: stage1_output = (14); + 1: stage1_output = (0); + 2: stage1_output = (4); + 3: stage1_output = (15); + 4: stage1_output = (13); + 5: stage1_output = (7); + 6: stage1_output = (1); + 7: stage1_output = (4); + 8: stage1_output = (2); + 9: stage1_output = (14); + 10: stage1_output = (15); + 11: stage1_output = (2); + 12: stage1_output = (11); + 13: stage1_output = (13); + 14: stage1_output = (8); + 15: stage1_output = (1); + 16: stage1_output = (3); + 17: stage1_output = (10); + 18: stage1_output = (10); + 19: stage1_output = (6); + 20: stage1_output = (6); + 21: stage1_output = (12); + 22: stage1_output = (12); + 23: stage1_output = (11); + 24: stage1_output = (5); + 25: stage1_output = (9); + 26: stage1_output = (9); + 27: stage1_output = (5); + 28: stage1_output = (0); + 29: stage1_output = (3); + 30: stage1_output = (7); + 31: stage1_output = (8); + 32: stage1_output = (4); + 33: stage1_output = (15); + 34: stage1_output = (1); + 35: stage1_output = (12); + 36: stage1_output = (14); + 37: stage1_output = (8); + 38: stage1_output = (8); + 39: stage1_output = (2); + 40: stage1_output = (13); + 41: stage1_output = (4); + 42: stage1_output = (6); + 43: stage1_output = (9); + 44: stage1_output = (2); + 45: stage1_output = (1); + 46: stage1_output = (11); + 47: stage1_output = (7); + 48: stage1_output = (15); + 49: stage1_output = (5); + 50: stage1_output = (12); + 51: stage1_output = (11); + 52: stage1_output = (9); + 53: stage1_output = (3); + 54: stage1_output = (7); + 55: stage1_output = (14); + 56: stage1_output = (3); + 57: stage1_output = (10); + 58: stage1_output = (10); + 59: stage1_output = (0); + 60: stage1_output = (5); + 61: stage1_output = (6); + 62: stage1_output = (0); + 63: stage1_output = (13); + +endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s2.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s2.v new file mode 100644 index 000000000..4325020b5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s2.v @@ -0,0 +1,137 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 2 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s2.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s2(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + + case(stage1_input) + 0: stage1_output = (15); + 1: stage1_output = (3); + 2: stage1_output = (1); + 3: stage1_output = (13); + 4: stage1_output = (8); + 5: stage1_output = (4); + 6: stage1_output = (14); + 7: stage1_output = (7); + 8: stage1_output = (6); + 9: stage1_output = (15); + 10: stage1_output = (11); + 11: stage1_output = (2); + 12: stage1_output = (3); + 13: stage1_output = (8); + 14: stage1_output = (4); + 15: stage1_output = (14); + 16: stage1_output = (9); + 17: stage1_output = (12); + 18: stage1_output = (7); + 19: stage1_output = (0); + 20: stage1_output = (2); + 21: stage1_output = (1); + 22: stage1_output = (13); + 23: stage1_output = (10); + 24: stage1_output = (12); + 25: stage1_output = (6); + 26: stage1_output = (0); + 27: stage1_output = (9); + 28: stage1_output = (5); + 29: stage1_output = (11); + 30: stage1_output = (10); + 31: stage1_output = (5); + 32: stage1_output = (0); + 33: stage1_output = (13); + 34: stage1_output = (14); + 35: stage1_output = (8); + 36: stage1_output = (7); + 37: stage1_output = (10); + 38: stage1_output = (11); + 39: stage1_output = (1); + 40: stage1_output = (10); + 41: stage1_output = (3); + 42: stage1_output = (4); + 43: stage1_output = (15); + 44: stage1_output = (13); + 45: stage1_output = (4); + 46: stage1_output = (1); + 47: stage1_output = (2); + 48: stage1_output = (5); + 49: stage1_output = (11); + 50: stage1_output = (8); + 51: stage1_output = (6); + 52: stage1_output = (12); + 53: stage1_output = (7); + 54: stage1_output = (6); + 55: stage1_output = (12); + 56: stage1_output = (9); + 57: stage1_output = (0); + 58: stage1_output = (3); + 59: stage1_output = (5); + 60: stage1_output = (2); + 61: stage1_output = (14); + 62: stage1_output = (15); + 63: stage1_output = (9); + +endcase + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s3.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s3.v new file mode 100644 index 000000000..bc788205e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s3.v @@ -0,0 +1,138 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 3 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s3.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s3(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (10); + 1: stage1_output = (13); + 2: stage1_output = (0); + 3: stage1_output = (7); + 4: stage1_output = (9); + 5: stage1_output = (0); + 6: stage1_output = (14); + 7: stage1_output = (9); + 8: stage1_output = (6); + 9: stage1_output = (3); + 10: stage1_output = (3); + 11: stage1_output = (4); + 12: stage1_output = (15); + 13: stage1_output = (6); + 14: stage1_output = (5); + 15: stage1_output = (10); + 16: stage1_output = (1); + 17: stage1_output = (2); + 18: stage1_output = (13); + 19: stage1_output = (8); + 20: stage1_output = (12); + 21: stage1_output = (5); + 22: stage1_output = (7); + 23: stage1_output = (14); + 24: stage1_output = (11); + 25: stage1_output = (12); + 26: stage1_output = (4); + 27: stage1_output = (11); + 28: stage1_output = (2); + 29: stage1_output = (15); + 30: stage1_output = (8); + 31: stage1_output = (1); + 32: stage1_output = (13); + 33: stage1_output = (1); + 34: stage1_output = (6); + 35: stage1_output = (10); + 36: stage1_output = (4); + 37: stage1_output = (13); + 38: stage1_output = (9); + 39: stage1_output = (0); + 40: stage1_output = (8); + 41: stage1_output = (6); + 42: stage1_output = (15); + 43: stage1_output = (9); + 44: stage1_output = (3); + 45: stage1_output = (8); + 46: stage1_output = (0); + 47: stage1_output = (7); + 48: stage1_output = (11); + 49: stage1_output = (4); + 50: stage1_output = (1); + 51: stage1_output = (15); + 52: stage1_output = (2); + 53: stage1_output = (14); + 54: stage1_output = (12); + 55: stage1_output = (3); + 56: stage1_output = (5); + 57: stage1_output = (11); + 58: stage1_output = (10); + 59: stage1_output = (5); + 60: stage1_output = (14); + 61: stage1_output = (2); + 62: stage1_output = (7); + 63: stage1_output = (12); + +endcase + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s4.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s4.v new file mode 100644 index 000000000..3d3f29e46 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s4.v @@ -0,0 +1,138 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 4 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s4.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s4(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (7); + 1: stage1_output = (13); + 2: stage1_output = (13); + 3: stage1_output = (8); + 4: stage1_output = (14); + 5: stage1_output = (11); + 6: stage1_output = (3); + 7: stage1_output = (5); + 8: stage1_output = (0); + 9: stage1_output = (6); + 10: stage1_output = (6); + 11: stage1_output = (15); + 12: stage1_output = (9); + 13: stage1_output = (0); + 14: stage1_output = (10); + 15: stage1_output = (3); + 16: stage1_output = (1); + 17: stage1_output = (4); + 18: stage1_output = (2); + 19: stage1_output = (7); + 20: stage1_output = (8); + 21: stage1_output = (2); + 22: stage1_output = (5); + 23: stage1_output = (12); + 24: stage1_output = (11); + 25: stage1_output = (1); + 26: stage1_output = (12); + 27: stage1_output = (10); + 28: stage1_output = (4); + 29: stage1_output = (14); + 30: stage1_output = (15); + 31: stage1_output = (9); + 32: stage1_output = (10); + 33: stage1_output = (3); + 34: stage1_output = (6); + 35: stage1_output = (15); + 36: stage1_output = (9); + 37: stage1_output = (0); + 38: stage1_output = (0); + 39: stage1_output = (6); + 40: stage1_output = (12); + 41: stage1_output = (10); + 42: stage1_output = (11); + 43: stage1_output = (1); + 44: stage1_output = (7); + 45: stage1_output = (13); + 46: stage1_output = (13); + 47: stage1_output = (8); + 48: stage1_output = (15); + 49: stage1_output = (9); + 50: stage1_output = (1); + 51: stage1_output = (4); + 52: stage1_output = (3); + 53: stage1_output = (5); + 54: stage1_output = (14); + 55: stage1_output = (11); + 56: stage1_output = (5); + 57: stage1_output = (12); + 58: stage1_output = (2); + 59: stage1_output = (7); + 60: stage1_output = (8); + 61: stage1_output = (2); + 62: stage1_output = (4); + 63: stage1_output = (14); + +endcase + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s5.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s5.v new file mode 100644 index 000000000..30b679535 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s5.v @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 5 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s5.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s5(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (2); + 1: stage1_output = (14); + 2: stage1_output = (12); + 3: stage1_output = (11); + 4: stage1_output = (4); + 5: stage1_output = (2); + 6: stage1_output = (1); + 7: stage1_output = (12); + 8: stage1_output = (7); + 9: stage1_output = (4); + 10: stage1_output = (10); + 11: stage1_output = (7); + 12: stage1_output = (11); + 13: stage1_output = (13); + 14: stage1_output = (6); + 15: stage1_output = (1); + 16: stage1_output = (8); + 17: stage1_output = (5); + 18: stage1_output = (5); + 19: stage1_output = (0); + 20: stage1_output = (3); + 21: stage1_output = (15); + 22: stage1_output = (15); + 23: stage1_output = (10); + 24: stage1_output = (13); + 25: stage1_output = (3); + 26: stage1_output = (0); + 27: stage1_output = (9); + 28: stage1_output = (14); + 29: stage1_output = (8); + 30: stage1_output = (9); + 31: stage1_output = (6); + 32: stage1_output = (4); + 33: stage1_output = (11); + 34: stage1_output = (2); + 35: stage1_output = (8); + 36: stage1_output = (1); + 37: stage1_output = (12); + 38: stage1_output = (11); + 39: stage1_output = (7); + 40: stage1_output = (10); + 41: stage1_output = (1); + 42: stage1_output = (13); + 43: stage1_output = (14); + 44: stage1_output = (7); + 45: stage1_output = (2); + 46: stage1_output = (8); + 47: stage1_output = (13); + 48: stage1_output = (15); + 49: stage1_output = (6); + 50: stage1_output = (9); + 51: stage1_output = (15); + 52: stage1_output = (12); + 53: stage1_output = (0); + 54: stage1_output = (5); + 55: stage1_output = (9); + 56: stage1_output = (6); + 57: stage1_output = (10); + 58: stage1_output = (3); + 59: stage1_output = (4); + 60: stage1_output = (0); + 61: stage1_output = (5); + 62: stage1_output = (14); + 63: stage1_output = (3); + +endcase + + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s6.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s6.v new file mode 100644 index 000000000..bc6be866c --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s6.v @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 6 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s6.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + + +module s6(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (12); + 1: stage1_output = (10); + 2: stage1_output = (1); + 3: stage1_output = (15); + 4: stage1_output = (10); + 5: stage1_output = (4); + 6: stage1_output = (15); + 7: stage1_output = (2); + 8: stage1_output = (9); + 9: stage1_output = (7); + 10: stage1_output = (2); + 11: stage1_output = (12); + 12: stage1_output = (6); + 13: stage1_output = (9); + 14: stage1_output = (8); + 15: stage1_output = (5); + 16: stage1_output = (0); + 17: stage1_output = (6); + 18: stage1_output = (13); + 19: stage1_output = (1); + 20: stage1_output = (3); + 21: stage1_output = (13); + 22: stage1_output = (4); + 23: stage1_output = (14); + 24: stage1_output = (14); + 25: stage1_output = (0); + 26: stage1_output = (7); + 27: stage1_output = (11); + 28: stage1_output = (5); + 29: stage1_output = (3); + 30: stage1_output = (11); + 31: stage1_output = (8); + 32: stage1_output = (9); + 33: stage1_output = (4); + 34: stage1_output = (14); + 35: stage1_output = (3); + 36: stage1_output = (15); + 37: stage1_output = (2); + 38: stage1_output = (5); + 39: stage1_output = (12); + 40: stage1_output = (2); + 41: stage1_output = (9); + 42: stage1_output = (8); + 43: stage1_output = (5); + 44: stage1_output = (12); + 45: stage1_output = (15); + 46: stage1_output = (3); + 47: stage1_output = (10); + 48: stage1_output = (7); + 49: stage1_output = (11); + 50: stage1_output = (0); + 51: stage1_output = (14); + 52: stage1_output = (4); + 53: stage1_output = (1); + 54: stage1_output = (10); + 55: stage1_output = (7); + 56: stage1_output = (1); + 57: stage1_output = (6); + 58: stage1_output = (13); + 59: stage1_output = (0); + 60: stage1_output = (11); + 61: stage1_output = (8); + 62: stage1_output = (6); + 63: stage1_output = (13); + +endcase + + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s7.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s7.v new file mode 100644 index 000000000..323c911cf --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s7.v @@ -0,0 +1,138 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 7 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s7.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + +module s7(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @( stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (4); + 1: stage1_output = (13); + 2: stage1_output = (11); + 3: stage1_output = (0); + 4: stage1_output = (2); + 5: stage1_output = (11); + 6: stage1_output = (14); + 7: stage1_output = (7); + 8: stage1_output = (15); + 9: stage1_output = (4); + 10: stage1_output = (0); + 11: stage1_output = (9); + 12: stage1_output = (8); + 13: stage1_output = (1); + 14: stage1_output = (13); + 15: stage1_output = (10); + 16: stage1_output = (3); + 17: stage1_output = (14); + 18: stage1_output = (12); + 19: stage1_output = (3); + 20: stage1_output = (9); + 21: stage1_output = (5); + 22: stage1_output = (7); + 23: stage1_output = (12); + 24: stage1_output = (5); + 25: stage1_output = (2); + 26: stage1_output = (10); + 27: stage1_output = (15); + 28: stage1_output = (6); + 29: stage1_output = (8); + 30: stage1_output = (1); + 31: stage1_output = (6); + 32: stage1_output = (1); + 33: stage1_output = (6); + 34: stage1_output = (4); + 35: stage1_output = (11); + 36: stage1_output = (11); + 37: stage1_output = (13); + 38: stage1_output = (13); + 39: stage1_output = (8); + 40: stage1_output = (12); + 41: stage1_output = (1); + 42: stage1_output = (3); + 43: stage1_output = (4); + 44: stage1_output = (7); + 45: stage1_output = (10); + 46: stage1_output = (14); + 47: stage1_output = (7); + 48: stage1_output = (10); + 49: stage1_output = (9); + 50: stage1_output = (15); + 51: stage1_output = (5); + 52: stage1_output = (6); + 53: stage1_output = (0); + 54: stage1_output = (8); + 55: stage1_output = (15); + 56: stage1_output = (0); + 57: stage1_output = (14); + 58: stage1_output = (5); + 59: stage1_output = (2); + 60: stage1_output = (9); + 61: stage1_output = (3); + 62: stage1_output = (2); + 63: stage1_output = (12); + +endcase + + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s8.v b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s8.v new file mode 100644 index 000000000..a3e2ec469 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/s8.v @@ -0,0 +1,137 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// SBOX 8 //// +//// //// +//// This file is part of the SystemC DES //// +//// //// +//// Description: //// +//// Sbox of DES algorithm //// +//// //// +//// Generated automatically using SystemC to Verilog translator //// +//// //// +//// To Do: //// +//// - done //// +//// //// +//// Author(s): //// +//// - Javier Castillo, jcastilo@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: s8.v,v $ +// Revision 1.1.1.1 2004/07/05 17:31:17 jcastillo +// First import +// + +module s8(stage1_input,stage1_output); +input [5:0] stage1_input; +output [3:0] stage1_output; + +reg [3:0] stage1_output; + + + +always @(stage1_input) + +begin + + case(stage1_input) + + 0: stage1_output = (13); + 1: stage1_output = (1); + 2: stage1_output = (2); + 3: stage1_output = (15); + 4: stage1_output = (8); + 5: stage1_output = (13); + 6: stage1_output = (4); + 7: stage1_output = (8); + 8: stage1_output = (6); + 9: stage1_output = (10); + 10: stage1_output = (15); + 11: stage1_output = (3); + 12: stage1_output = (11); + 13: stage1_output = (7); + 14: stage1_output = (1); + 15: stage1_output = (4); + 16: stage1_output = (10); + 17: stage1_output = (12); + 18: stage1_output = (9); + 19: stage1_output = (5); + 20: stage1_output = (3); + 21: stage1_output = (6); + 22: stage1_output = (14); + 23: stage1_output = (11); + 24: stage1_output = (5); + 25: stage1_output = (0); + 26: stage1_output = (0); + 27: stage1_output = (14); + 28: stage1_output = (12); + 29: stage1_output = (9); + 30: stage1_output = (7); + 31: stage1_output = (2); + 32: stage1_output = (7); + 33: stage1_output = (2); + 34: stage1_output = (11); + 35: stage1_output = (1); + 36: stage1_output = (4); + 37: stage1_output = (14); + 38: stage1_output = (1); + 39: stage1_output = (7); + 40: stage1_output = (9); + 41: stage1_output = (4); + 42: stage1_output = (12); + 43: stage1_output = (10); + 44: stage1_output = (14); + 45: stage1_output = (8); + 46: stage1_output = (2); + 47: stage1_output = (13); + 48: stage1_output = (0); + 49: stage1_output = (15); + 50: stage1_output = (6); + 51: stage1_output = (12); + 52: stage1_output = (10); + 53: stage1_output = (9); + 54: stage1_output = (13); + 55: stage1_output = (0); + 56: stage1_output = (15); + 57: stage1_output = (3); + 58: stage1_output = (3); + 59: stage1_output = (5); + 60: stage1_output = (5); + 61: stage1_output = (6); + 62: stage1_output = (8); + 63: stage1_output = (11); + +endcase + + + +end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_alu.v b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_alu.v new file mode 100644 index 000000000..2f015e219 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_alu.v @@ -0,0 +1,442 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_alu (/*AUTOARG*/ + // Outputs + Q, F_Out, + // Inputs + Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input Arith16; + input Z16; + input [3:0] ALU_Op ; + input [5:0] IR; + input [1:0] ISet; + input [7:0] BusA; + input [7:0] BusB; + input [7:0] F_In; + output [7:0] Q; + output [7:0] F_Out; + reg [7:0] Q; + reg [7:0] F_Out; + + function [4:0] AddSub4; + input [3:0] A; + input [3:0] B; + input Sub; + input Carry_In; + begin + AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [3:0] AddSub3; + input [2:0] A; + input [2:0] B; + input Sub; + input Carry_In; + begin + AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [1:0] AddSub1; + input A; + input B; + input Sub; + input Carry_In; + begin + AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + // AddSub variables (temporary signals) + reg UseCarry; + reg Carry7_v; + reg OverFlow_v; + reg HalfCarry_v; + reg Carry_v; + reg [7:0] Q_v; + + reg [7:0] BitMask; + + + always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) + begin + case (IR[5:3]) + 3'b000 : BitMask = 8'b00000001; + 3'b001 : BitMask = 8'b00000010; + 3'b010 : BitMask = 8'b00000100; + 3'b011 : BitMask = 8'b00001000; + 3'b100 : BitMask = 8'b00010000; + 3'b101 : BitMask = 8'b00100000; + 3'b110 : BitMask = 8'b01000000; + default: BitMask = 8'b10000000; + endcase // case(IR[5:3]) + + UseCarry = ~ ALU_Op[2] && ALU_Op[0]; + { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); + { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); + { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); + OverFlow_v = Carry_v ^ Carry7_v; + end // always @ * + + reg [7:0] Q_t; + reg [8:0] DAA_Q; + + always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB + or Carry_v or F_In or HalfCarry_v or IR or ISet + or OverFlow_v or Q_v or Z16) + begin + Q_t = 8'hxx; + DAA_Q = {9{1'bx}}; + + F_Out = F_In; + case (ALU_Op) + 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : + begin + F_Out[Flag_N] = 1'b0; + F_Out[Flag_C] = 1'b0; + + case (ALU_Op[2:0]) + + 3'b000, 3'b001 : // ADD, ADC + begin + Q_t = Q_v; + F_Out[Flag_C] = Carry_v; + F_Out[Flag_H] = HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP + begin + Q_t = Q_v; + F_Out[Flag_N] = 1'b1; + F_Out[Flag_C] = ~ Carry_v; + F_Out[Flag_H] = ~ HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b100 : // AND + begin + Q_t[7:0] = BusA & BusB; + F_Out[Flag_H] = 1'b1; + end + + 3'b101 : // XOR + begin + Q_t[7:0] = BusA ^ BusB; + F_Out[Flag_H] = 1'b0; + end + + default : // OR 3'b110 + begin + Q_t[7:0] = BusA | BusB; + F_Out[Flag_H] = 1'b0; + end + + endcase // case(ALU_OP[2:0]) + + if (ALU_Op[2:0] == 3'b111 ) + begin // CP + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + else + begin + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + end + + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + if (Z16 == 1'b1 ) + begin + F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC + end + end + else + begin + F_Out[Flag_Z] = 1'b0; + end // else: !if(Q_t[7:0] == 8'b00000000 ) + + F_Out[Flag_S] = Q_t[7]; + case (ALU_Op[2:0]) + 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP + ; + + default : + F_Out[Flag_P] = ~(^Q_t); + endcase // case(ALU_Op[2:0]) + + if (Arith16 == 1'b1 ) + begin + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + F_Out[Flag_P] = F_In[Flag_P]; + end + end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 + + 4'b1100 : + begin + // DAA + F_Out[Flag_H] = F_In[Flag_H]; + F_Out[Flag_C] = F_In[Flag_C]; + DAA_Q[7:0] = BusA; + DAA_Q[8] = 1'b0; + if (F_In[Flag_N] == 1'b0 ) + begin + // After addition + // Alow > 9 || H == 1 + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if ((DAA_Q[3:0] > 9) ) + begin + F_Out[Flag_H] = 1'b1; + end + else + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q = DAA_Q + 6; + end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + + // new Ahigh > 9 || C == 1 + if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q + 96; // 0x60 + end + end + else + begin + // After subtraction + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if (DAA_Q[3:0] > 5 ) + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q[7:0] = DAA_Q[7:0] - 6; + end + if (BusA > 153 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q - 352; // 0x160 + end + end // else: !if(F_In[Flag_N] == 1'b0 ) + + F_Out[Flag_X] = DAA_Q[3]; + F_Out[Flag_Y] = DAA_Q[5]; + F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; + Q_t = DAA_Q[7:0]; + + if (DAA_Q[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + + F_Out[Flag_S] = DAA_Q[7]; + F_Out[Flag_P] = ~ (^DAA_Q); + end // case: 4'b1100 + + 4'b1101, 4'b1110 : + begin + // RLD, RRD + Q_t[7:4] = BusA[7:4]; + if (ALU_Op[0] == 1'b1 ) + begin + Q_t[3:0] = BusB[7:4]; + end + else + begin + Q_t[3:0] = BusB[3:0]; + end + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_S] = Q_t[7]; + F_Out[Flag_P] = ~(^Q_t); + end // case: when 4'b1101, 4'b1110 + + 4'b1001 : + begin + // BIT + Q_t[7:0] = BusB & BitMask; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + F_Out[Flag_P] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + F_Out[Flag_P] = 1'b0; + end + F_Out[Flag_H] = 1'b1; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = 1'b0; + F_Out[Flag_Y] = 1'b0; + if (IR[2:0] != 3'b110 ) + begin + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + end // case: when 4'b1001 + + 4'b1010 : + // SET + Q_t[7:0] = BusB | BitMask; + + 4'b1011 : + // RES + Q_t[7:0] = BusB & ~ BitMask; + + 4'b1000 : + begin + // ROT + case (IR[5:3]) + 3'b000 : // RLC + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = BusA[7]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b010 : // RL + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b001 : // RRC + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[0]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b011 : // RR + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b100 : // SLA + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b0; + F_Out[Flag_C] = BusA[7]; + end + + 3'b110 : // SLL (Undocumented) / SWAP + begin + if (Mode == 3 ) + begin + Q_t[7:4] = BusA[3:0]; + Q_t[3:0] = BusA[7:4]; + F_Out[Flag_C] = 1'b0; + end + else + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b1; + F_Out[Flag_C] = BusA[7]; + end // else: !if(Mode == 3 ) + end // case: 3'b110 + + 3'b101 : // SRA + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[7]; + F_Out[Flag_C] = BusA[0]; + end + + default : // SRL + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = 1'b0; + F_Out[Flag_C] = BusA[0]; + end + endcase // case(IR[5:3]) + + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_P] = ~(^Q_t); + + if (ISet == 2'b00 ) + begin + F_Out[Flag_P] = F_In[Flag_P]; + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + end + end // case: 4'b1000 + + + default : + ; + + endcase // case(ALU_Op) + + Q = Q_t; + end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + +endmodule // T80_ALU diff --git a/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_core.v b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_core.v new file mode 100644 index 000000000..1d69f791a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_core.v @@ -0,0 +1,1304 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_core (/*AUTOARG*/ + // Outputs + m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, do, mc, ts, + intcycle_n, IntE, stop, + // Inputs + reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di + ); + // Beginning of automatic inputs (from unused autoinst inputs) + // End of automatics + + parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter IOWait = 1; // 1 => Single cycle I/O, 1 => Std I/O cycle + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input reset_n; + input clk; + input cen; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output iorq; + output no_read; + output write; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] dinst; + input [7:0] di; + output [7:0] do; + output [2:0] mc; + output [2:0] ts; + output intcycle_n; + output IntE; + output stop; + + reg m1_n; + reg iorq; + reg rfsh_n; + reg halt_n; + reg busak_n; + reg [15:0] A; + reg [7:0] do; + reg [2:0] mc; + reg [2:0] ts; + reg intcycle_n; + reg IntE; + reg stop; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + + // Registers + reg [7:0] ACC, F; + reg [7:0] Ap, Fp; + reg [7:0] I; + reg [7:0] R; + reg [15:0] SP, PC; + reg [7:0] RegDIH; + reg [7:0] RegDIL; + wire [15:0] RegBusA; + wire [15:0] RegBusB; + wire [15:0] RegBusC; + reg [2:0] RegAddrA_r; + reg [2:0] RegAddrA; + reg [2:0] RegAddrB_r; + reg [2:0] RegAddrB; + reg [2:0] RegAddrC; + reg RegWEH; + reg RegWEL; + reg Alternate; + + // Help Registers + reg [15:0] TmpAddr; // Temporary address register + reg [7:0] IR; // Instruction register + reg [1:0] ISet; // Instruction set selector + reg [15:0] RegBusA_r; + + reg [15:0] ID16; + reg [7:0] Save_Mux; + + reg [2:0] tstate; + reg [2:0] mcycle; + reg IntE_FF1; + reg IntE_FF2; + reg Halt_FF; + reg BusReq_s; + reg BusAck; + reg ClkEn; + reg NMI_s; + reg INT_s; + reg [1:0] IStatus; + + reg [7:0] DI_Reg; + reg T_Res; + reg [1:0] XY_State; + reg [2:0] Pre_XY_F_M; + reg NextIs_XY_Fetch; + reg XY_Ind; + reg No_BTR; + reg BTR_r; + reg Auto_Wait; + reg Auto_Wait_t1; + reg Auto_Wait_t2; + reg IncDecZ; + + // ALU signals + reg [7:0] BusB; + reg [7:0] BusA; + wire [7:0] ALU_Q; + wire [7:0] F_Out; + + // Registered micro code outputs + reg [4:0] Read_To_Reg_r; + reg Arith16_r; + reg Z16_r; + reg [3:0] ALU_Op_r; + reg Save_ALU_r; + reg PreserveC_r; + reg [2:0] mcycles; + + // Micro code outputs + wire [2:0] mcycles_d; + wire [2:0] tstates; + reg IntCycle; + reg NMICycle; + wire Inc_PC; + wire Inc_WZ; + wire [3:0] IncDec_16; + wire [1:0] Prefix; + wire Read_To_Acc; + wire Read_To_Reg; + wire [3:0] Set_BusB_To; + wire [3:0] Set_BusA_To; + wire [3:0] ALU_Op; + wire Save_ALU; + wire PreserveC; + wire Arith16; + wire [2:0] Set_Addr_To; + wire Jump; + wire JumpE; + wire JumpXY; + wire Call; + wire RstP; + wire LDZ; + wire LDW; + wire LDSPHL; + wire iorq_i; + wire [2:0] Special_LD; + wire ExchangeDH; + wire ExchangeRp; + wire ExchangeAF; + wire ExchangeRS; + wire I_DJNZ; + wire I_CPL; + wire I_CCF; + wire I_SCF; + wire I_RETN; + wire I_BT; + wire I_BC; + wire I_BTR; + wire I_RLD; + wire I_RRD; + wire I_INRC; + wire SetDI; + wire SetEI; + wire [1:0] IMode; + wire Halt; + + reg [15:0] PC16; + reg [15:0] PC16_B; + reg [15:0] SP16, SP16_A, SP16_B; + reg [15:0] ID16_B; + reg Oldnmi_n; + + tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode + ( + .IR (IR), + .ISet (ISet), + .MCycle (mcycle), + .F (F), + .NMICycle (NMICycle), + .IntCycle (IntCycle), + .MCycles (mcycles_d), + .TStates (tstates), + .Prefix (Prefix), + .Inc_PC (Inc_PC), + .Inc_WZ (Inc_WZ), + .IncDec_16 (IncDec_16), + .Read_To_Acc (Read_To_Acc), + .Read_To_Reg (Read_To_Reg), + .Set_BusB_To (Set_BusB_To), + .Set_BusA_To (Set_BusA_To), + .ALU_Op (ALU_Op), + .Save_ALU (Save_ALU), + .PreserveC (PreserveC), + .Arith16 (Arith16), + .Set_Addr_To (Set_Addr_To), + .IORQ (iorq_i), + .Jump (Jump), + .JumpE (JumpE), + .JumpXY (JumpXY), + .Call (Call), + .RstP (RstP), + .LDZ (LDZ), + .LDW (LDW), + .LDSPHL (LDSPHL), + .Special_LD (Special_LD), + .ExchangeDH (ExchangeDH), + .ExchangeRp (ExchangeRp), + .ExchangeAF (ExchangeAF), + .ExchangeRS (ExchangeRS), + .I_DJNZ (I_DJNZ), + .I_CPL (I_CPL), + .I_CCF (I_CCF), + .I_SCF (I_SCF), + .I_RETN (I_RETN), + .I_BT (I_BT), + .I_BC (I_BC), + .I_BTR (I_BTR), + .I_RLD (I_RLD), + .I_RRD (I_RRD), + .I_INRC (I_INRC), + .SetDI (SetDI), + .SetEI (SetEI), + .IMode (IMode), + .Halt (Halt), + .NoRead (no_read), + .Write (write) + ); + + tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu + ( + .Arith16 (Arith16_r), + .Z16 (Z16_r), + .ALU_Op (ALU_Op_r), + .IR (IR[5:0]), + .ISet (ISet), + .BusA (BusA), + .BusB (BusB), + .F_In (F), + .Q (ALU_Q), + .F_Out (F_Out) + ); + + always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg + or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind + or XY_State or cen or mcycle or tstate or tstates) + begin + ClkEn = cen && ~ BusAck; + + if (tstate == tstates) + T_Res = 1'b1; + else T_Res = 1'b0; + + if (XY_State != 2'b00 && XY_Ind == 1'b0 && + ((Set_Addr_To == aXY) || + (mcycle == 3'b001 && IR == 8'b11001011) || + (mcycle == 3'b001 && IR == 8'b00110110))) + NextIs_XY_Fetch = 1'b1; + else + NextIs_XY_Fetch = 1'b0; + + if (ExchangeRp) + Save_Mux = BusB; + else if (!Save_ALU_r) + Save_Mux = DI_Reg; + else + Save_Mux = ALU_Q; + end // always @ * + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + PC <= #1 0; // Program Counter + A <= #1 0; + TmpAddr <= #1 0; + IR <= #1 8'b00000000; + ISet <= #1 2'b00; + XY_State <= #1 2'b00; + IStatus <= #1 2'b00; + mcycles <= #1 3'b000; + do <= #1 8'b00000000; + + ACC <= #1 8'hFF; + F <= #1 8'hFF; + Ap <= #1 8'hFF; + Fp <= #1 8'hFF; + I <= #1 0; + R <= #1 0; + SP <= #1 16'hFFFF; + Alternate <= #1 1'b0; + + Read_To_Reg_r <= #1 5'b00000; + Arith16_r <= #1 1'b0; + BTR_r <= #1 1'b0; + Z16_r <= #1 1'b0; + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + PreserveC_r <= #1 1'b0; + XY_Ind <= #1 1'b0; + end + else + begin + + if (ClkEn == 1'b1 ) + begin + + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + Read_To_Reg_r <= #1 5'b00000; + + mcycles <= #1 mcycles_d; + + if (IMode != 2'b11 ) + begin + IStatus <= #1 IMode; + end + + Arith16_r <= #1 Arith16; + PreserveC_r <= #1 PreserveC; + if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle == 3'b011 ) + begin + Z16_r <= #1 1'b1; + end + else + begin + Z16_r <= #1 1'b0; + end + + if (mcycle == 3'b001 && tstate[2] == 1'b0 ) + begin + // mcycle == 1 && tstate == 1, 2, || 3 + + if (tstate == 2 && wait_n == 1'b1 ) + begin + if (Mode < 2 ) + begin + A[7:0] <= #1 R; + A[15:8] <= #1 I; + R[6:0] <= #1 R[6:0] + 1; + end + + if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) + begin + PC <= #1 PC16; + end + + if (IntCycle == 1'b1 && IStatus == 2'b01 ) + begin + IR <= #1 8'b11111111; + end + else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) + begin + IR <= #1 8'b00000000; + end + else + begin + IR <= #1 dinst; + end + + ISet <= #1 2'b00; + if (Prefix != 2'b00 ) + begin + if (Prefix == 2'b11 ) + begin + if (IR[5] == 1'b1 ) + begin + XY_State <= #1 2'b10; + end + else + begin + XY_State <= #1 2'b01; + end + end + else + begin + if (Prefix == 2'b10 ) + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + ISet <= #1 Prefix; + end + end + else + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + end // if (tstate == 2 && wait_n == 1'b1 ) + + + end + else + begin + // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) + + if (mcycle == 3'b110 ) + begin + XY_Ind <= #1 1'b1; + if (Prefix == 2'b01 ) + begin + ISet <= #1 2'b01; + end + end + + if (T_Res == 1'b1 ) + begin + BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; + if (Jump == 1'b1 ) + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 DI_Reg; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else if (JumpXY == 1'b1 ) + begin + A <= #1 RegBusC; + PC <= #1 RegBusC; + end else if (Call == 1'b1 || RstP == 1'b1 ) + begin + A <= #1 TmpAddr; + PC <= #1 TmpAddr; + end + else if (mcycle == mcycles && NMICycle == 1'b1 ) + begin + A <= #1 16'b0000000001100110; + PC <= #1 16'b0000000001100110; + end + else if (mcycle == 3'b011 && IntCycle == 1'b1 && IStatus == 2'b10 ) + begin + A[15:8] <= #1 I; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 I; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else + begin + case (Set_Addr_To) + aXY : + begin + if (XY_State == 2'b00 ) + begin + A <= #1 RegBusC; + end + else + begin + if (NextIs_XY_Fetch == 1'b1 ) + begin + A <= #1 PC; + end + else + begin + A <= #1 TmpAddr; + end + end // else: !if(XY_State == 2'b00 ) + end // case: aXY + + aIOA : + begin + if (Mode == 3 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + end + else if (Mode == 2 ) + begin + // Duplicate I/O address on 8080 + A[15:8] <= #1 DI_Reg; + end + else + begin + A[15:8] <= #1 ACC; + end + A[7:0] <= #1 DI_Reg; + end // case: aIOA + + + aSP : + begin + A <= #1 SP; + end + + aBC : + begin + if (Mode == 3 && iorq_i == 1'b1 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + A[7:0] <= #1 RegBusC[7:0]; + end + else + begin + A <= #1 RegBusC; + end + end // case: aBC + + aDE : + begin + A <= #1 RegBusC; + end + + aZI : + begin + if (Inc_WZ == 1'b1 ) + begin + A <= #1 TmpAddr + 1; + end + else + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + end + end // case: aZI + + default : + begin + A <= #1 PC; + end + endcase // case(Set_Addr_To) + + end // else: !if(mcycle == 3'b011 && IntCycle == 1'b1 && IStatus == 2'b10 ) + + + Save_ALU_r <= #1 Save_ALU; + ALU_Op_r <= #1 ALU_Op; + + if (I_CPL == 1'b1 ) + begin + // CPL + ACC <= #1 ~ ACC; + F[Flag_Y] <= #1 ~ ACC[5]; + F[Flag_H] <= #1 1'b1; + F[Flag_X] <= #1 ~ ACC[3]; + F[Flag_N] <= #1 1'b1; + end + if (I_CCF == 1'b1 ) + begin + // CCF + F[Flag_C] <= #1 ~ F[Flag_C]; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 F[Flag_C]; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + if (I_SCF == 1'b1 ) + begin + // SCF + F[Flag_C] <= #1 1'b1; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 1'b0; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + end // if (T_Res == 1'b1 ) + + + if (tstate == 2 && wait_n == 1'b1 ) + begin + if (ISet == 2'b01 && mcycle == 3'b111 ) + begin + IR <= #1 dinst; + end + if (JumpE == 1'b1 ) + begin + PC <= #1 PC16; + end + else if (Inc_PC == 1'b1 ) + begin + //PC <= #1 PC + 1; + PC <= #1 PC16; + end + if (BTR_r == 1'b1 ) + begin + //PC <= #1 PC - 2; + PC <= #1 PC16; + end + if (RstP == 1'b1 ) + begin + TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; + //TmpAddr <= #1 (others =>1'b0); + //TmpAddr[5:3] <= #1 IR[5:3]; + end + end + if (tstate == 3 && mcycle == 3'b110 ) + begin + TmpAddr <= #1 SP16; + end + + if ((tstate == 2 && wait_n == 1'b1) || (tstate == 4 && mcycle == 3'b001) ) + begin + if (IncDec_16[2:0] == 3'b111 ) + begin + SP <= #1 SP16; + end + end + + if (LDSPHL == 1'b1 ) + begin + SP <= #1 RegBusC; + end + if (ExchangeAF == 1'b1 ) + begin + Ap <= #1 ACC; + ACC <= #1 Ap; + Fp <= #1 F; + F <= #1 Fp; + end + if (ExchangeRS == 1'b1 ) + begin + Alternate <= #1 ~ Alternate; + end + end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) + + + if (tstate == 3 ) + begin + if (LDZ == 1'b1 ) + begin + TmpAddr[7:0] <= #1 DI_Reg; + end + if (LDW == 1'b1 ) + begin + TmpAddr[15:8] <= #1 DI_Reg; + end + + if (Special_LD[2] == 1'b1 ) + begin + case (Special_LD[1:0]) + 2'b00 : + begin + ACC <= #1 I; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b01 : + begin + ACC <= #1 R; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b10 : + I <= #1 ACC; + + default : + R <= #1 ACC; + endcase + end + end // if (tstate == 3 ) + + + if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + begin + if (Mode == 3 ) + begin + F[6] <= #1 F_Out[6]; + F[5] <= #1 F_Out[5]; + F[7] <= #1 F_Out[7]; + if (PreserveC_r == 1'b0 ) + begin + F[4] <= #1 F_Out[4]; + end + end + else + begin + F[7:1] <= #1 F_Out[7:1]; + if (PreserveC_r == 1'b0 ) + begin + F[Flag_C] <= #1 F_Out[0]; + end + end + end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + + if (T_Res == 1'b1 && I_INRC == 1'b1 ) + begin + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + if (DI_Reg[7:0] == 8'b00000000 ) + begin + F[Flag_Z] <= #1 1'b1; + end + else + begin + F[Flag_Z] <= #1 1'b0; + end + F[Flag_S] <= #1 DI_Reg[7]; + F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); + end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) + + + if (tstate == 1 && Auto_Wait_t1 == 1'b0 ) + begin + do <= #1 BusB; + if (I_RLD == 1'b1 ) + begin + do[3:0] <= #1 BusA[3:0]; + do[7:4] <= #1 BusB[3:0]; + end + if (I_RRD == 1'b1 ) + begin + do[3:0] <= #1 BusB[7:4]; + do[7:4] <= #1 BusA[3:0]; + end + end + + if (T_Res == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 Set_BusA_To; + Read_To_Reg_r[4] <= #1 Read_To_Reg; + if (Read_To_Acc == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 4'b0111; + Read_To_Reg_r[4] <= #1 1'b1; + end + end + + if (tstate == 1 && I_BT == 1'b1 ) + begin + F[Flag_X] <= #1 ALU_Q[3]; + F[Flag_Y] <= #1 ALU_Q[1]; + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + end + if (I_BC == 1'b1 || I_BT == 1'b1 ) + begin + F[Flag_P] <= #1 IncDecZ; + end + + if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10111 : + ACC <= #1 Save_Mux; + 5'b10110 : + do <= #1 Save_Mux; + 5'b11000 : + SP[7:0] <= #1 Save_Mux; + 5'b11001 : + SP[15:8] <= #1 Save_Mux; + 5'b11011 : + F <= #1 Save_Mux; + endcase + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + end // if (ClkEn == 1'b1 ) + end // else: !if(reset_n == 1'b0 ) + end + + + //------------------------------------------------------------------------- + // + // BC('), DE('), HL('), IX && IY + // + //------------------------------------------------------------------------- + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + // Bus A / Write + RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) + begin + RegAddrA_r <= #1 { XY_State[1], 2'b11 }; + end + + // Bus B + RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) + begin + RegAddrB_r <= #1 { XY_State[1], 2'b11 }; + end + + // Address from register + RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; + // Jump (HL), LD SP,HL + if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) + begin + RegAddrC <= #1 { Alternate, 2'b10 }; + end + if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle == 3'b110) ) + begin + RegAddrC <= #1 { XY_State[1], 2'b11 }; + end + + if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) + begin + IncDecZ <= #1 F_Out[Flag_Z]; + end + if ((tstate == 2 || (tstate == 3 && mcycle == 3'b001)) && IncDec_16[2:0] == 3'b100 ) + begin + if (ID16 == 0 ) + begin + IncDecZ <= #1 1'b0; + end + else + begin + IncDecZ <= #1 1'b1; + end + end + + RegBusA_r <= #1 RegBusA; + end + + end // always @ (posedge clk) + + + always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 + or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) + begin + if ((tstate == 2 || (tstate == 3 && mcycle == 3'b001 && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) + RegAddrA = { Alternate, IncDec_16[1:0] }; + else if ((tstate == 2 || (tstate == 3 && mcycle == 3'b001 && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) + RegAddrA = { XY_State[1], 2'b11 }; + else if (ExchangeDH == 1'b1 && tstate == 3) + RegAddrA = { Alternate, 2'b10 }; + else if (ExchangeDH == 1'b1 && tstate == 4) + RegAddrA = { Alternate, 2'b01 }; + else + RegAddrA = RegAddrA_r; + + if (ExchangeDH == 1'b1 && tstate == 3) + RegAddrB = { Alternate, 2'b01 }; + else + RegAddrB = RegAddrB_r; + end // always @ * + + + always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH + or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle + or tstate or wait_n) + begin + RegWEH = 1'b0; + RegWEL = 1'b0; + if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : + begin + RegWEH = ~ Read_To_Reg_r[0]; + RegWEL = Read_To_Reg_r[0]; + end + endcase // case(Read_To_Reg_r) + + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + + + if (ExchangeDH == 1'b1 && (tstate == 3 || tstate == 4) ) + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + + if (IncDec_16[2] == 1'b1 && ((tstate == 2 && wait_n == 1'b1 && mcycle != 3'b001) || (tstate == 3 && mcycle == 3'b001)) ) + begin + case (IncDec_16[1:0]) + 2'b00 , 2'b01 , 2'b10 : + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + endcase + end + end // always @ * + + + always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r + or RegBusB or Save_Mux or mcycle or tstate) + begin + RegDIH = Save_Mux; + RegDIL = Save_Mux; + + if (ExchangeDH == 1'b1 && tstate == 3 ) + begin + RegDIH = RegBusB[15:8]; + RegDIL = RegBusB[7:0]; + end + else if (ExchangeDH == 1'b1 && tstate == 4 ) + begin + RegDIH = RegBusA_r[15:8]; + RegDIL = RegBusA_r[7:0]; + end + else if (IncDec_16[2] == 1'b1 && ((tstate == 2 && mcycle != 3'b001) || (tstate == 3 && mcycle == 3'b001)) ) + begin + RegDIH = ID16[15:8]; + RegDIL = ID16[7:0]; + end + end + + tv80_reg i_reg + ( + .clk (clk), + .CEN (ClkEn), + .WEH (RegWEH), + .WEL (RegWEL), + .AddrA (RegAddrA), + .AddrB (RegAddrB), + .AddrC (RegAddrC), + .DIH (RegDIH), + .DIL (RegDIL), + .DOAH (RegBusA[15:8]), + .DOAL (RegBusA[7:0]), + .DOBH (RegBusB[15:8]), + .DOBL (RegBusB[7:0]), + .DOCH (RegBusC[15:8]), + .DOCL (RegBusC[7:0]) + ); + + //------------------------------------------------------------------------- + // + // Buses + // + //------------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + case (Set_BusB_To) + 4'b0111 : + BusB <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusB_To[0] == 1'b1 ) + begin + BusB <= #1 RegBusB[7:0]; + end + else + begin + BusB <= #1 RegBusB[15:8]; + end + end + 4'b0110 : + BusB <= #1 DI_Reg; + 4'b1000 : + BusB <= #1 SP[7:0]; + 4'b1001 : + BusB <= #1 SP[15:8]; + 4'b1010 : + BusB <= #1 8'b00000001; + 4'b1011 : + BusB <= #1 F; + 4'b1100 : + BusB <= #1 PC[7:0]; + 4'b1101 : + BusB <= #1 PC[15:8]; + 4'b1110 : + BusB <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + + case (Set_BusA_To) + 4'b0111 : + BusA <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusA_To[0] == 1'b1 ) + begin + BusA <= #1 RegBusA[7:0]; + end + else + begin + BusA <= #1 RegBusA[15:8]; + end + end + 4'b0110 : + BusA <= #1 DI_Reg; + 4'b1000 : + BusA <= #1 SP[7:0]; + 4'b1001 : + BusA <= #1 SP[15:8]; + 4'b1010 : + BusA <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + end + end + + //------------------------------------------------------------------------- + // + // Generate external control signals + // + //------------------------------------------------------------------------- + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + rfsh_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (mcycle == 3'b001 && ((tstate == 2 && wait_n == 1'b1) || tstate == 3) ) + begin + rfsh_n <= #1 1'b0; + end + else + begin + rfsh_n <= #1 1'b1; + end + end + end + end + + + always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle + or IntE_FF1 or di or iorq_i or mcycle or tstate) + begin + mc = mcycle; + ts = tstate; + DI_Reg = di; + halt_n = ~ Halt_FF; + busak_n = ~ BusAck; + intcycle_n = ~ IntCycle; + IntE = IntE_FF1; + iorq = iorq_i; + stop = I_DJNZ; + end + + //----------------------------------------------------------------------- + // + // Syncronise inputs + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin : sync_inputs + + if (reset_n == 1'b0 ) + begin + BusReq_s <= #1 1'b0; + INT_s <= #1 1'b0; + NMI_s <= #1 1'b0; + Oldnmi_n <= #1 1'b0; + end + else + begin + if (cen == 1'b1 ) + begin + BusReq_s <= #1 ~ busrq_n; + INT_s <= #1 ~ int_n; + if (NMICycle == 1'b1 ) + begin + NMI_s <= #1 1'b0; + end + else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) + begin + NMI_s <= #1 1'b1; + end + Oldnmi_n <= #1 nmi_n; + end + end + end + + //----------------------------------------------------------------------- + // + // Main state machine + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + mcycle <= #1 3'b001; + tstate <= #1 3'b000; + Pre_XY_F_M <= #1 3'b000; + Halt_FF <= #1 1'b0; + BusAck <= #1 1'b0; + NMICycle <= #1 1'b0; + IntCycle <= #1 1'b0; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + No_BTR <= #1 1'b0; + Auto_Wait_t1 <= #1 1'b0; + Auto_Wait_t2 <= #1 1'b0; + m1_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (T_Res == 1'b1 ) + begin + Auto_Wait_t1 <= #1 1'b0; + end + else + begin + Auto_Wait_t1 <= #1 Auto_Wait || iorq_i; + end + Auto_Wait_t2 <= #1 Auto_Wait_t1; + No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || + (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || + (I_BTR && (~ IR[4] || F[Flag_Z])); + if (tstate == 2 ) + begin + if (SetEI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b1; + IntE_FF2 <= #1 1'b1; + end + if (I_RETN == 1'b1 ) + begin + IntE_FF1 <= #1 IntE_FF2; + end + end + if (tstate == 3 ) + begin + if (SetDI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + Halt_FF <= #1 1'b0; + end + if (mcycle == 3'b001 && tstate == 2 && wait_n == 1'b1 ) + begin + m1_n <= #1 1'b1; + end + if (BusReq_s == 1'b1 && BusAck == 1'b1 ) + begin + end + else + begin + BusAck <= #1 1'b0; + if (tstate == 2 && wait_n == 1'b0 ) + begin + end + else if (T_Res == 1'b1 ) + begin + if (Halt == 1'b1 ) + begin + Halt_FF <= #1 1'b1; + end + if (BusReq_s == 1'b1 ) + begin + BusAck <= #1 1'b1; + end + else + begin + tstate <= #1 3'b001; + if (NextIs_XY_Fetch == 1'b1 ) + begin + mcycle <= #1 3'b110; + Pre_XY_F_M <= #1 mcycle; + if (IR == 8'b00110110 && Mode == 0 ) + begin + Pre_XY_F_M <= #1 3'b010; + end + end + else if ((mcycle == 3'b111) || (mcycle == 3'b110 && Mode == 1 && ISet != 2'b01) ) + begin + mcycle <= #1 Pre_XY_F_M + 1; + end + else if ((mcycle == mcycles) || + No_BTR == 1'b1 || + (mcycle == 3'b010 && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) + begin + m1_n <= #1 1'b0; + mcycle <= #1 3'b001; + IntCycle <= #1 1'b0; + NMICycle <= #1 1'b0; + if (NMI_s == 1'b1 && Prefix == 2'b00 ) + begin + NMICycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + end + else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) + begin + IntCycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + else + begin + mcycle <= #1 mcycle + 1; + end + end + end + else + begin // verilog has no "nor" operator + if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && + ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) + begin + tstate <= #1 tstate + 1; + end + end + end + if (tstate == 0 ) + begin + m1_n <= #1 1'b0; + end + end + end + end + + always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC + or RegBusA or RegBusC or SP or tstate) + begin + if (JumpE == 1'b1 ) + begin + PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else if (BTR_r == 1'b1 ) + begin + PC16_B = -2; + end + else + begin + PC16_B = 1; + end + + if (tstate == 3) + begin + SP16_A = RegBusC; + SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else + begin + // suspect that ID16 and SP16 could be shared + SP16_A = SP; + + if (IncDec_16[3] == 1'b1) + SP16_B = -1; + else + SP16_B = 1; + end + + if (IncDec_16[3]) + ID16_B = -1; + else + ID16_B = 1; + + ID16 = RegBusA + ID16_B; + PC16 = PC + PC16_B; + SP16 = SP16_A + SP16_B; + end // always @ * + + + always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) + begin + Auto_Wait = 1'b0; + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + if (mcycle == 3'b001 ) + begin + Auto_Wait = 1'b1; + end + end + end // always @ * + +// synopsys dc_script_begin +// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet +// synopsys dc_script_end +endmodule // T80 + diff --git a/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_mcode.v b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_mcode.v new file mode 100644 index 000000000..44e35f648 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_mcode.v @@ -0,0 +1,2759 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_mcode (/*AUTOARG*/ + // Outputs + MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, + Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, + Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, + LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, + ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, + I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, + // Inputs + IR, ISet, MCycle, F, NMICycle, IntCycle + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input [7:0] IR; + input [1:0] ISet ; + input [2:0] MCycle ; + input [7:0] F ; + input NMICycle ; + input IntCycle ; + output [2:0] MCycles ; + output [2:0] TStates ; + output [1:0] Prefix ; // None,BC,ED,DD/FD + output Inc_PC ; + output Inc_WZ ; + output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + output Read_To_Reg ; + output Read_To_Acc ; + output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + output [3:0] ALU_Op ; + output Save_ALU ; + output PreserveC ; + output Arith16 ; + output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + output IORQ ; + output Jump ; + output JumpE ; + output JumpXY ; + output Call ; + output RstP ; + output LDZ ; + output LDW ; + output LDSPHL ; + output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + output ExchangeDH ; + output ExchangeRp ; + output ExchangeAF ; + output ExchangeRS ; + output I_DJNZ ; + output I_CPL ; + output I_CCF ; + output I_SCF ; + output I_RETN ; + output I_BT ; + output I_BC ; + output I_BTR ; + output I_RLD ; + output I_RRD ; + output I_INRC ; + output SetDI ; + output SetEI ; + output [1:0] IMode ; + output Halt ; + output NoRead ; + output Write ; + + // regs + reg [2:0] MCycles ; + reg [2:0] TStates ; + reg [1:0] Prefix ; // None,BC,ED,DD/FD + reg Inc_PC ; + reg Inc_WZ ; + reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + reg Read_To_Reg ; + reg Read_To_Acc ; + reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + reg [3:0] ALU_Op ; + reg Save_ALU ; + reg PreserveC ; + reg Arith16 ; + reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + reg IORQ ; + reg Jump ; + reg JumpE ; + reg JumpXY ; + reg Call ; + reg RstP ; + reg LDZ ; + reg LDW ; + reg LDSPHL ; + reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + reg ExchangeDH ; + reg ExchangeRp ; + reg ExchangeAF ; + reg ExchangeRS ; + reg I_DJNZ ; + reg I_CPL ; + reg I_CCF ; + reg I_SCF ; + reg I_RETN ; + reg I_BT ; + reg I_BC ; + reg I_BTR ; + reg I_RLD ; + reg I_RRD ; + reg I_INRC ; + reg SetDI ; + reg SetEI ; + reg [1:0] IMode ; + reg Halt ; + reg NoRead ; + reg Write ; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; +// constant aNone : std_logic_vector[2:0] = 3'b000; +// constant aXY : std_logic_vector[2:0] = 3'b001; +// constant aIOA : std_logic_vector[2:0] = 3'b010; +// constant aSP : std_logic_vector[2:0] = 3'b011; +// constant aBC : std_logic_vector[2:0] = 3'b100; +// constant aDE : std_logic_vector[2:0] = 3'b101; +// constant aZI : std_logic_vector[2:0] = 3'b110; + + function is_cc_true; + input [7:0] F; + input [2:0] cc; + begin + if (Mode == 3 ) + begin + case (cc) + 3'b000 : is_cc_true = F[7] == 1'b0; // NZ + 3'b001 : is_cc_true = F[7] == 1'b1; // Z + 3'b010 : is_cc_true = F[4] == 1'b0; // NC + 3'b011 : is_cc_true = F[4] == 1'b1; // C + 3'b100 : is_cc_true = 0; + 3'b101 : is_cc_true = 0; + 3'b110 : is_cc_true = 0; + 3'b111 : is_cc_true = 0; + endcase + end + else + begin + case (cc) + 3'b000 : is_cc_true = F[6] == 1'b0; // NZ + 3'b001 : is_cc_true = F[6] == 1'b1; // Z + 3'b010 : is_cc_true = F[0] == 1'b0; // NC + 3'b011 : is_cc_true = F[0] == 1'b1; // C + 3'b100 : is_cc_true = F[2] == 1'b0; // PO + 3'b101 : is_cc_true = F[2] == 1'b1; // PE + 3'b110 : is_cc_true = F[7] == 1'b0; // P + 3'b111 : is_cc_true = F[7] == 1'b1; // M + endcase + end + end + endfunction // is_cc_true + + + reg [2:0] DDD; + reg [2:0] SSS; + reg [1:0] DPAIR; + reg [7:0] IRB; + + always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle + or NMICycle) + begin + DDD = IR[5:3]; + SSS = IR[2:0]; + DPAIR = IR[5:4]; + IRB = IR; + + MCycles = 3'b001; + if (MCycle == 3'b001 ) + begin + TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + Prefix = 2'b00; + Inc_PC = 1'b0; + Inc_WZ = 1'b0; + IncDec_16 = 4'b0000; + Read_To_Acc = 1'b0; + Read_To_Reg = 1'b0; + Set_BusB_To = 4'b0000; + Set_BusA_To = 4'b0000; + ALU_Op = { 1'b0, IR[5:3] }; + Save_ALU = 1'b0; + PreserveC = 1'b0; + Arith16 = 1'b0; + IORQ = 1'b0; + Set_Addr_To = aNone; + Jump = 1'b0; + JumpE = 1'b0; + JumpXY = 1'b0; + Call = 1'b0; + RstP = 1'b0; + LDZ = 1'b0; + LDW = 1'b0; + LDSPHL = 1'b0; + Special_LD = 3'b000; + ExchangeDH = 1'b0; + ExchangeRp = 1'b0; + ExchangeAF = 1'b0; + ExchangeRS = 1'b0; + I_DJNZ = 1'b0; + I_CPL = 1'b0; + I_CCF = 1'b0; + I_SCF = 1'b0; + I_RETN = 1'b0; + I_BT = 1'b0; + I_BC = 1'b0; + I_BTR = 1'b0; + I_RLD = 1'b0; + I_RRD = 1'b0; + I_INRC = 1'b0; + SetDI = 1'b0; + SetEI = 1'b0; + IMode = 2'b11; + Halt = 1'b0; + NoRead = 1'b0; + Write = 1'b0; + + case (ISet) + 2'b00 : + begin + +//---------------------------------------------------------------------------- +// +// Unprefixed instructions +// +//---------------------------------------------------------------------------- + + case (IRB) +// 8 BIT LOAD GROUP + 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, + 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, + 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, + 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, + 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, + 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, + 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : + begin + + // LD r,r' + Set_BusB_To[2:0] = SSS; + ExchangeRp = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... + + 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110 : + begin + // LD r,n + MCycles = 3'b010; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110 + + 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110 : + begin + // LD r,(HL) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110 + + 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111 : + begin + // LD (HL),r + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + 2 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111 + + 8'b00110110 : + begin + // LD (HL),n + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110110 + + 8'b00001010 : + begin + // LD A,(BC) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aBC; + 2 : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00001010 + + 8'b00011010 : + begin + // LD A,(DE) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aDE; + 2 : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00011010 + + 8'b00111010 : + begin + if (Mode == 3 ) + begin + // LDD A,(HL) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b1110; + end + default :; + endcase + end + else + begin + // LD A,(nn) + MCycles = 3'b100; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + 4 : + begin + Read_To_Acc = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00111010 + + 8'b00000010 : + begin + // LD (BC),A + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + 2 : + begin + Write = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b00000010 + + 8'b00010010 : + begin + // LD (DE),A + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aDE; + Set_BusB_To = 4'b0111; + end + 2 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00010010 + + 8'b00110010 : + begin + if (Mode == 3 ) + begin + // LDD (HL),A + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + 2 : + begin + Write = 1'b1; + IncDec_16 = 4'b1110; + end + default :; + endcase // case(MCycle) + + end + else + begin + // LD (nn),A + MCycles = 3'b100; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + 4 : + begin + Write = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00110010 + + +// 16 BIT LOAD GROUP + 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : + begin + // LD dd,nn + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + 3 : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 + + 8'b00101010 : + begin + if (Mode == 3 ) + begin + // LDI A,(HL) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b0110; + end + + default :; + endcase + end + else + begin + // LD HL,(nn) + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + 4 : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + 5 : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00101010 + + 8'b00100010 : + begin + if (Mode == 3 ) + begin + // LDI (HL),A + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + 2 : + begin + Write = 1'b1; + IncDec_16 = 4'b0110; + end + default :; + endcase + end + else + begin + // LD (nn),HL + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b0101; // L + end + + 4 : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b0100; // H + end + 5 : + Write = 1'b1; + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00100010 + + 8'b11111001 : + begin + // LD SP,HL + TStates = 3'b110; + LDSPHL = 1'b1; + end + + 8'b11000101,8'b11010101,8'b11100101,8'b11110101 : + begin + // PUSH qq + MCycles = 3'b011; + case (MCycle) + 1 : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b0111; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 1 + + 2 : + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b1011; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + Write = 1'b1; + end // case: 2 + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 + + 8'b11000001,8'b11010001,8'b11100001,8'b11110001 : + begin + // POP qq + MCycles = 3'b011; + case (MCycle) + 1 : + Set_Addr_To = aSP; + 2 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1011; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + 3 : + begin + IncDec_16 = 4'b0111; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b0111; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 + + +// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + 8'b11101011 : + begin + if (Mode != 3 ) + begin + // EX DE,HL + ExchangeDH = 1'b1; + end + end + + 8'b00001000 : + begin + if (Mode == 3 ) + begin + // LD (nn),SP + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b1000; + end + + 4 : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b1001; + end + + 5 : + Write = 1'b1; + default :; + endcase + end + else if (Mode < 2 ) + begin + // EX AF,AF' + ExchangeAF = 1'b1; + end + end // case: 8'b00001000 + + 8'b11011001 : + begin + if (Mode == 3 ) + begin + // RETI + MCycles = 3'b011; + case (MCycle) + 1 : + Set_Addr_To = aSP; + 2 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + 3 : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + SetEI = 1'b1; + end + default :; + endcase + end + else if (Mode < 2 ) + begin + // EXX + ExchangeRS = 1'b1; + end + end // case: 8'b11011001 + + 8'b11100011 : + begin + if (Mode != 3 ) + begin + // EX (SP),HL + MCycles = 3'b101; + case (MCycle) + 1 : + Set_Addr_To = aSP; + 2 : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0101; + Set_BusB_To = 4'b0101; + Set_Addr_To = aSP; + end + 3 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + TStates = 3'b100; + Write = 1'b1; + end + 4 : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0100; + Set_BusB_To = 4'b0100; + Set_Addr_To = aSP; + end + 5 : + begin + IncDec_16 = 4'b1111; + TStates = 3'b101; + Write = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11100011 + + +// 8 BIT ARITHMETIC AND LOGICAL GROUP + 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, + 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, + 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, + 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, + 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, + 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, + 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, + 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : + begin + // ADD A,r + // ADC A,r + // SUB A,r + // SBC A,r + // AND A,r + // OR A,r + // XOR A,r + // CP A,r + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : + begin + // ADD A,(HL) + // ADC A,(HL) + // SUB A,(HL) + // SBC A,(HL) + // AND A,(HL) + // OR A,(HL) + // XOR A,(HL) + // CP A,(HL) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 + + 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : + begin + // ADD A,n + // ADC A,n + // SUB A,n + // SBC A,n + // AND A,n + // OR A,n + // XOR A,n + // CP A,n + MCycles = 3'b010; + if (MCycle == 3'b010 ) + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 + + 8'b00000100,8'b00001100,8'b00010100,8'b00011100,8'b00100100,8'b00101100,8'b00111100 : + begin + // INC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + end + + 8'b00110100 : + begin + // INC (HL) + MCycles = 3'b011; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110100 + + 8'b00000101,8'b00001101,8'b00010101,8'b00011101,8'b00100101,8'b00101101,8'b00111101 : + begin + // DEC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0010; + end + + 8'b00110101 : + begin + // DEC (HL) + MCycles = 3'b011; + case (MCycle) + 1 : + Set_Addr_To = aXY; + 2 : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + ALU_Op = 4'b0010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110101 + +// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + 8'b00100111 : + begin + // DAA + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + ALU_Op = 4'b1100; + Save_ALU = 1'b1; + end + + 8'b00101111 : + // CPL + I_CPL = 1'b1; + + 8'b00111111 : + // CCF + I_CCF = 1'b1; + + 8'b00110111 : + // SCF + I_SCF = 1'b1; + + 8'b00000000 : + begin + if (NMICycle == 1'b1 ) + begin + // NMI + MCycles = 3'b011; + case (MCycle) + 1 : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + 2 : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + 3 : + begin + TStates = 3'b100; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + + end + else if (IntCycle == 1'b1 ) + begin + // INT (IM 2) + MCycles = 3'b101; + case (MCycle) + 1 : + begin + LDZ = 1'b1; + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + 2 : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + 3 : + begin + TStates = 3'b100; + Write = 1'b1; + end + + 4 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 5 : + Jump = 1'b1; + default :; + endcase + end + end // case: 8'b00000000 + + 8'b01110110 : + // HALT + Halt = 1'b1; + + 8'b11110011 : + // DI + SetDI = 1'b1; + + 8'b11111011 : + // EI + SetEI = 1'b1; + + // 16 BIT ARITHMETIC GROUP + 8'b00001001,8'b00011001,8'b00101001,8'b00111001 : + begin + // ADD HL,ss + MCycles = 3'b011; + case (MCycle) + 2 : + begin + NoRead = 1'b1; + ALU_Op = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + + default : + Set_BusB_To = 4'b1000; + endcase // case(IR[5:4]) + + TStates = 3'b100; + Arith16 = 1'b1; + end // case: 2 + + 3 : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + Arith16 = 1'b1; + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 + + 8'b00000011,8'b00010011,8'b00100011,8'b00110011 : + begin + // INC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b01; + IncDec_16[1:0] = DPAIR; + end + + 8'b00001011,8'b00011011,8'b00101011,8'b00111011 : + begin + // DEC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b11; + IncDec_16[1:0] = DPAIR; + end + +// ROTATE AND SHIFT GROUP + 8'b00000111, + // RLCA + 8'b00010111, + // RLA + 8'b00001111, + // RRCA + 8'b00011111 : + // RRA + begin + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // case: 8'b00000111,... + + +// JUMP GROUP + 8'b11000011 : + begin + // JP nn + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Inc_PC = 1'b1; + Jump = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11000011 + + 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IRB[4:3]) + 2'b00 : + begin + // LD ($FF00+C),A + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + 2 : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // LD (nn),A + MCycles = 3'b100; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + + 4 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: default :... + + 2'b10 : + begin + // LD A,($FF00+C) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aBC; + 2 : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD A,(nn) + MCycles = 3'b100; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + 4 : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end + endcase + end + else + begin + // JP cc,nn + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Inc_PC = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + Jump = 1'b1; + end + end + + default :; + endcase + end // else: !if(DPAIR == 2'b11 ) + end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 + + 8'b00011000 : + begin + if (Mode != 2 ) + begin + // JR e + MCycles = 3'b011; + case (MCycle) + 2 : + Inc_PC = 1'b1; + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00011000 + + 8'b00111000 : + begin + if (Mode != 2 ) + begin + // JR C,e + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + if (F[Flag_C] == 1'b0 ) + begin + MCycles = 3'b010; + end + end + + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00111000 + + 8'b00110000 : + begin + if (Mode != 2 ) + begin + // JR NC,e + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + if (F[Flag_C] == 1'b1 ) + begin + MCycles = 3'b010; + end + end + + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00110000 + + 8'b00101000 : + begin + if (Mode != 2 ) + begin + // JR Z,e + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + if (F[Flag_Z] == 1'b0 ) + begin + MCycles = 3'b010; + end + end + + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00101000 + + 8'b00100000 : + begin + if (Mode != 2 ) + begin + // JR NZ,e + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + if (F[Flag_Z] == 1'b1 ) + begin + MCycles = 3'b010; + end + end + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00100000 + + 8'b11101001 : + // JP (HL) + JumpXY = 1'b1; + + 8'b00010000 : + begin + if (Mode == 3 ) + begin + I_DJNZ = 1'b1; + end + else if (Mode < 2 ) + begin + // DJNZ,e + MCycles = 3'b011; + case (MCycle) + 1 : + begin + TStates = 3'b101; + I_DJNZ = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = 3'b000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + 2 : + begin + I_DJNZ = 1'b1; + Inc_PC = 1'b1; + end + 3 : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode < 2 ) + end // case: 8'b00010000 + + +// CALL AND RETURN GROUP + 8'b11001101 : + begin + // CALL nn + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + IncDec_16 = 4'b1111; + Inc_PC = 1'b1; + TStates = 3'b100; + Set_Addr_To = aSP; + LDW = 1'b1; + Set_BusB_To = 4'b1101; + end + 4 : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + 5 : + begin + Write = 1'b1; + Call = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b11001101 + + 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 : + begin + if (IR[5] == 1'b0 || Mode != 3 ) + begin + // CALL cc,nn + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + 3 : + begin + Inc_PC = 1'b1; + LDW = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + TStates = 3'b100; + Set_BusB_To = 4'b1101; + end + else + begin + MCycles = 3'b011; + end // else: !if(is_cc_true(F, IR[5:3]) ) + end // case: 3 + + 4 : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + 5 : + begin + Write = 1'b1; + Call = 1'b1; + end + + default :; + endcase + end // if (IR[5] == 1'b0 || Mode != 3 ) + end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 + + 8'b11001001 : + begin + // RET + MCycles = 3'b011; + case (MCycle) + 1 : + begin + TStates = 3'b101; + Set_Addr_To = aSP; + end + + 2 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + 3 : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11001001 + + 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IRB[4:3]) + 2'b00 : + begin + // LD ($FF00+nn),A + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // ADD SP,n + MCycles = 3'b011; + case (MCycle) + 2 : + begin + ALU_Op = 4'b0000; + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To = 4'b1000; + Set_BusB_To = 4'b0110; + end + + 3 : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To = 4'b1001; + Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + end + + default :; + endcase // case(MCycle) + end // case: 2'b01 + + 2'b10 : + begin + // LD A,($FF00+nn) + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + 3 : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + 4 : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + + 5 : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b11 + + endcase // case(IRB[4:3]) + + end + else + begin + // RET cc + MCycles = 3'b011; + case (MCycle) + 1 : + begin + if (is_cc_true(F, IR[5:3]) ) + begin + Set_Addr_To = aSP; + end + else + begin + MCycles = 3'b001; + end + TStates = 3'b101; + end // case: 1 + + 2 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + 3 : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + default :; + endcase + end // else: !if(IR[5] == 1'b1 && Mode == 3 ) + end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 + + 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : + begin + // RST p + MCycles = 3'b011; + case (MCycle) + 1 : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + 2 : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + 3 : + begin + Write = 1'b1; + RstP = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 + +// INPUT AND OUTPUT GROUP + 8'b11011011 : + begin + if (Mode != 3 ) + begin + // IN A,(n) + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + 3 : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11011011 + + 8'b11010011 : + begin + if (Mode != 3 ) + begin + // OUT (n),A + MCycles = 3'b011; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + 3 : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11010011 + + +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// MULTIBYTE INSTRUCTIONS +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- + + 8'b11001011 : + begin + if (Mode != 2 ) + begin + Prefix = 2'b01; + end + end + + 8'b11101101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b10; + end + end + + 8'b11011101,8'b11111101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b11; + end + end + + endcase // case(IRB) + end // case: 2'b00 + + + 2'b01 : + begin + + + //---------------------------------------------------------------------------- + // + // CB prefixed instructions + // + //---------------------------------------------------------------------------- + + Set_BusA_To[2:0] = IR[2:0]; + Set_BusB_To[2:0] = IR[2:0]; + + case (IRB) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, + 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, + 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, + 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, + 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, + 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, + 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, + 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : + begin + // RLC r + // RL r + // RRC r + // RR r + // SLA r + // SRA r + // SRL r + // SLL r (Undocumented) / SWAP r + if (MCycle == 3'b001 ) begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... + + 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 : + begin + // RLC (HL) + // RL (HL) + // RRC (HL) + // RR (HL) + // SRA (HL) + // SRL (HL) + // SLA (HL) + // SLL (HL) (Undocumented) / SWAP (HL) + MCycles = 3'b011; + case (MCycle) + 1 , 7 : + Set_Addr_To = aXY; + 2 : + begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 + + 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, + 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, + 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, + 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, + 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, + 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, + 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, + 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : + begin + // BIT b,r + if (MCycle == 3'b001 ) + begin + Set_BusB_To[2:0] = IR[2:0]; + ALU_Op = 4'b1001; + end + end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... + + 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : + begin + // BIT b,(HL) + MCycles = 3'b010; + case (MCycle) + 1 , 7 : + Set_Addr_To = aXY; + 2 : + begin + ALU_Op = 4'b1001; + TStates = 3'b100; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 + + 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, + 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, + 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, + 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, + 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, + 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, + 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, + 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : + begin + // SET b,r + if (MCycle == 3'b001 ) + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... + + 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : + begin + // SET b,(HL) + MCycles = 3'b011; + case (MCycle) + 1 , 7 : + Set_Addr_To = aXY; + 2 : + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 + + 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, + 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, + 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, + 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, + 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, + 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, + 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, + 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : + begin + // RES b,r + if (MCycle == 3'b001 ) + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : + begin + // RES b,(HL) + MCycles = 3'b011; + case (MCycle) + 1 , 7 : + Set_Addr_To = aXY; + 2 : + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + 3 : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 + + endcase // case(IRB) + end // case: 2'b01 + + + default : + begin : default_ed_block + + //---------------------------------------------------------------------------- + // + // ED prefixed instructions + // + //---------------------------------------------------------------------------- + + case (IRB) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 + ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 + ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 + ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 + ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 + ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 + ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 + ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 + + + ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 + ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 + ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 + ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 + , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 + , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 + , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 + , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 + ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 + ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 + ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 + ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 + ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 + ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 + ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 + ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : + ; // NOP, undocumented + + 8'b01111110,8'b01111111 : + // NOP, undocumented + ; + // 8 BIT LOAD GROUP + 8'b01010111 : + begin + // LD A,I + Special_LD = 3'b100; + TStates = 3'b101; + end + + 8'b01011111 : + begin + // LD A,R + Special_LD = 3'b101; + TStates = 3'b101; + end + + 8'b01000111 : + begin + // LD I,A + Special_LD = 3'b110; + TStates = 3'b101; + end + + 8'b01001111 : + begin + // LD R,A + Special_LD = 3'b111; + TStates = 3'b101; + end + + // 16 BIT LOAD GROUP + 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : + begin + // LD dd,(nn) + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + 4 : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b1; + end + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end // case: 4 + + 5 : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b0; + end + end // case: 5 + + default :; + endcase // case(MCycle) + end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 + + + 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : + begin + // LD (nn),dd + MCycles = 3'b101; + case (MCycle) + 2 : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + 3 : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1000; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + end // case: 3 + + 4 : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1001; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 4 + + 5 : + begin + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 + + 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : + begin + // LDI, LDD, LDIR, LDDR + MCycles = 3'b100; + case (MCycle) + 1 : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + 2 : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0000; + Set_Addr_To = aDE; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; // IX + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + 3 : + begin + I_BT = 1'b1; + TStates = 3'b101; + Write = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0101; // DE + end + else + begin + IncDec_16 = 4'b1101; + end + end // case: 3 + + 4 : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 + + 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : + begin + // CPI, CPD, CPIR, CPDR + MCycles = 3'b100; + case (MCycle) + 1 : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + 2 : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0111; + Save_ALU = 1'b1; + PreserveC = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + 3 : + begin + NoRead = 1'b1; + I_BC = 1'b1; + TStates = 3'b101; + end + + 4 : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 + + 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : + begin + // NEG + ALU_Op = 4'b0010; + Set_BusB_To = 4'b0111; + Set_BusA_To = 4'b1010; + Read_To_Acc = 1'b1; + Save_ALU = 1'b1; + end + + 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : + begin + // IM 0 + IMode = 2'b00; + end + + 8'b01010110,8'b01110110 : + // IM 1 + IMode = 2'b01; + + 8'b01011110,8'b01110111 : + // IM 2 + IMode = 2'b10; + + // 16 bit arithmetic + 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : + begin + // ADC HL,ss + MCycles = 3'b011; + case (MCycle) + 2 : + begin + NoRead = 1'b1; + ALU_Op = 4'b0001; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + 3 : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + end + default : + Set_BusB_To = 4'b1001; + endcase // case(IR[5:4]) + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 + + 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : + begin + // SBC HL,ss + MCycles = 3'b011; + case (MCycle) + 2 : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + 3 : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + end // case: 3 + + default :; + + endcase // case(MCycle) + end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 + + 8'b01101111 : + begin + // RLD + MCycles = 3'b100; + case (MCycle) + 2 : + begin + NoRead = 1'b1; + Set_Addr_To = aXY; + end + + 3 : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1101; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + 4 : + begin + I_RLD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01101111 + + 8'b01100111 : + begin + // RRD + MCycles = 3'b100; + case (MCycle) + 2 : + Set_Addr_To = aXY; + 3 : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1110; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + 4 : + begin + I_RRD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01100111 + + 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : + begin + // RETI, RETN + MCycles = 3'b011; + case (MCycle) + 1 : + Set_Addr_To = aSP; + + 2 : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + 3 : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 + + 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : + begin + // IN r,(C) + MCycles = 3'b010; + case (MCycle) + 1 : + Set_Addr_To = aBC; + + 2 : + begin + IORQ = 1'b1; + if (IR[5:3] != 3'b110 ) + begin + Read_To_Reg = 1'b1; + Set_BusA_To[2:0] = IR[5:3]; + end + I_INRC = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 + + 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : + begin + // OUT (C),r + // OUT (C),0 + MCycles = 3'b010; + case (MCycle) + 1 : + begin + Set_Addr_To = aBC; + Set_BusB_To[2:0] = IR[5:3]; + if (IR[5:3] == 3'b110 ) + begin + Set_BusB_To[3] = 1'b1; + end + end + + 2 : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 + + 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : + begin + // INI, IND, INIR, INDR + MCycles = 3'b100; + case (MCycle) + 1 : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + 2 : + begin + IORQ = 1'b1; + Set_BusB_To = 4'b0110; + Set_Addr_To = aXY; + end + + 3 : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0010; + end + else + begin + IncDec_16 = 4'b1010; + end + TStates = 3'b100; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + 4 : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 + + 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : + begin + // OUTI, OUTD, OTIR, OTDR + MCycles = 3'b100; + case (MCycle) + 1 : + begin + TStates = 3'b101; + Set_Addr_To = aXY; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + 2 : + begin + Set_BusB_To = 4'b0110; + Set_Addr_To = aBC; + end + + 3 : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0010; + end + else + begin + IncDec_16 = 4'b1010; + end + IORQ = 1'b1; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + 4 : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 + + endcase // case(IRB) + end // block: default_ed_block + endcase // case(ISet) + + if (Mode == 1 ) + begin + if (MCycle == 3'b001 ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + end + + if (Mode == 3 ) + begin + if (MCycle == 3'b001 ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b100; + end + end + + if (Mode < 2 ) + begin + if (MCycle == 3'b110 ) + begin + Inc_PC = 1'b1; + if (Mode == 1 ) + begin + Set_Addr_To = aXY; + TStates = 3'b100; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (IRB == 8'b00110110 || IRB == 8'b11001011 ) + begin + Set_Addr_To = aNone; + end + end + if (MCycle == 3'b111 ) + begin + if (Mode == 0 ) + begin + TStates = 3'b101; + end + if (ISet != 2'b01 ) + begin + Set_Addr_To = aXY; + end + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + if (IRB == 8'b00110110 || ISet == 2'b01 ) + begin + // LD (HL),n + Inc_PC = 1'b1; + end + else + begin + NoRead = 1'b1; + end + end + end // if (Mode < 2 ) + + end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) + +// synopsys dc_script_begin +// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet +// synopsys dc_script_end +endmodule // T80_MCode + + + diff --git a/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_reg.v b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_reg.v new file mode 100644 index 000000000..8218407b6 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80_reg.v @@ -0,0 +1,71 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_reg (/*AUTOARG*/ + // Outputs + DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, + // Inputs + AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL + ); + input [2:0] AddrC; + output [7:0] DOBH; + input [2:0] AddrA; + input [2:0] AddrB; + input [7:0] DIH; + output [7:0] DOAL; + output [7:0] DOCL; + input [7:0] DIL; + output [7:0] DOBL; + output [7:0] DOCH; + output [7:0] DOAH; + input clk, CEN, WEH, WEL; + + reg [7:0] RegsH [0:7]; + reg [7:0] RegsL [0:7]; + + always @(posedge clk) + begin + if (CEN) + begin + if (WEH) RegsH[AddrA] <= DIH; + if (WEL) RegsL[AddrA] <= DIL; + end + end + + assign DOAH = RegsH[AddrA]; + assign DOAL = RegsL[AddrA]; + assign DOBH = RegsH[AddrB]; + assign DOBL = RegsL[AddrB]; + assign DOCH = RegsH[AddrC]; + assign DOCL = RegsL[AddrC]; + + // break out ram bits for waveform debug + wire [7:0] H = RegsH[2]; + wire [7:0] L = RegsL[2]; + +// synopsys dc_script_begin +// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet +// synopsys dc_script_end +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80s.v b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80s.v new file mode 100644 index 000000000..e8b8085c3 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/tv80/rtl/tv80s.v @@ -0,0 +1,160 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80s (/*AUTOARG*/ + // Outputs + m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do, + // Inputs + reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di + ); + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2 + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + + + input reset_n; + input clk; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output mreq_n; + output iorq_n; + output rd_n; + output wr_n; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] di; + output [7:0] do; + + reg mreq_n; + reg iorq_n; + reg rd_n; + reg wr_n; + + wire cen; + wire intcycle_n; + wire no_read; + wire write; + wire iorq; + reg [7:0] di_reg; + wire [2:0] mcycle; + wire [2:0] tstate; + + assign cen = 1; + + tv80_core i_tv80_core + ( + .cen (cen), + .m1_n (m1_n), + .iorq (iorq), + .no_read (no_read), + .write (write), + .rfsh_n (rfsh_n), + .halt_n (halt_n), + .wait_n (wait_n), + .int_n (int_n), + .nmi_n (nmi_n), + .reset_n (reset_n), + .busrq_n (busrq_n), + .busak_n (busak_n), + .clk (clk), + .IntE (), + .stop (), + .A (A), + .dinst (di), + .di (di_reg), + .do (do), + .mc (mcycle), + .ts (tstate), + .intcycle_n (intcycle_n) + ); + + always @(posedge clk) + begin + if (!reset_n) + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + di_reg <= #1 0; + end + else + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + if (mcycle == 3'b001) + begin + if (tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) + begin + rd_n <= #1 ~ intcycle_n; + mreq_n <= #1 ~ intcycle_n; + iorq_n <= #1 intcycle_n; + end + if (tstate == 3'b011) + mreq_n <= #1 1'b0; + end // if (mcycle == 3'b001) + else + begin + if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0) + begin + rd_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + if (T2Write == 0) + begin + if (tstate == 3'b010 && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end + else + begin + if ((tstate == 3'b001 || (tstate == 3'b010 && wait_n == 1'b0)) && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end // else: !if(T2write == 0) + + end // else: !if(mcycle == 3'b001) + + if (tstate == 3'b010 && wait_n == 1'b1) + di_reg <= #1 di; + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + +endmodule // t80s + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc16.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc16.v new file mode 100644 index 000000000..f4c935b89 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc16.v @@ -0,0 +1,115 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB CRC5 and CRC16 Modules //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_crc16.v,v 1.2 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_crc16.v,v $ +// Revision 1.2 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:42 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +/////////////////////////////////////////////////////////////////// +// +// CRC16 +// +/////////////////////////////////////////////////////////////////// + +module usbf_crc16(crc_in, din, crc_out); +input [15:0] crc_in; +input [7:0] din; +output [15:0] crc_out; + +assign crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ + din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^ + crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^ + crc_in[14] ^ crc_in[15]; +assign crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^ + din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^ + crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15]; +assign crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9]; +assign crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10]; +assign crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11]; +assign crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12]; +assign crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13]; +assign crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14]; +assign crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15]; +assign crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15]; +assign crc_out[10] = crc_in[2]; +assign crc_out[11] = crc_in[3]; +assign crc_out[12] = crc_in[4]; +assign crc_out[13] = crc_in[5]; +assign crc_out[14] = crc_in[6]; +assign crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^ + din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^ + crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^ + crc_in[14] ^ crc_in[15]; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc5.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc5.v new file mode 100644 index 000000000..d382d8812 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_crc5.v @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB CRC5 and CRC16 Modules //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_crc5.v,v 1.2 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_crc5.v,v $ +// Revision 1.2 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:42 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +/////////////////////////////////////////////////////////////////// +// +// CRC5 +// +/////////////////////////////////////////////////////////////////// + +module usbf_crc5(crc_in, din, crc_out); +input [4:0] crc_in; +input [10:0] din; +output [4:0] crc_out; + +assign crc_out[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^ + din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^ + crc_in[0] ^ crc_in[1] ^ crc_in[4]; + +assign crc_out[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^ + din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^ + crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^ + din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^ + crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_defines.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_defines.v new file mode 100644 index 000000000..4c8f8ffac --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_defines.v @@ -0,0 +1,294 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB function defines file //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_defines.v,v 1.6 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_defines.v,v $ +// Revision 1.6 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/04 12:22:43 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:35 rudi +// Initial Release +// +// + +`timescale 1ns / 10ps + +// Uncomment the lines below to get various levels of debugging +// verbosity ... +`define USBF_DEBUG +//`define USBF_VERBOSE_DEBUG + +// Uncomment the line below to run the test bench +// Comment it out to use your own address parameters ... +`define USBF_TEST_IMPL + +// For each endpoint that should actually be instantiated, +// set the below define value to a one. Uncomment the define +// statement for unused endpoints. The endpoints should be +// sequential, e.q. 1,2,3. I have not tested what happens if +// you select endpoints in a non sequential manner e.g. 1,4,6 +// Actual (logical) endpoint IDs are set by the software. There +// is no correlation between the physical endpoint number (below) +// and the actual (logical) endpoint number. +`ifdef USBF_TEST_IMPL + // Do not modify this section + // this is to run the test bench + `define USBF_HAVE_EP1 1 + `define USBF_HAVE_EP2 1 + `define USBF_HAVE_EP3 1 +`else + // Modify this section to suit your implementation + `define USBF_HAVE_EP1 1 + `define USBF_HAVE_EP2 1 + `define USBF_HAVE_EP3 1 + //`define USBF_HAVE_EP4 1 + //`define USBF_HAVE_EP5 1 + //`define USBF_HAVE_EP6 1 + //`define USBF_HAVE_EP7 1 + //`define USBF_HAVE_EP8 1 + //`define USBF_HAVE_EP9 1 + //`define USBF_HAVE_EP10 1 + //`define USBF_HAVE_EP11 1 + //`define USBF_HAVE_EP12 1 + //`define USBF_HAVE_EP13 1 + //`define USBF_HAVE_EP14 1 + //`define USBF_HAVE_EP15 1 +`endif + + +// Highest address line number that goes to the USB core +// Typically only A0 through A17 are needed, where A17 +// selects between the internal buffer memory and the +// register file. +// Implementations may choose to have a more complex address +// decoding .... + +`ifdef USBF_TEST_IMPL + // Do not modify this section + // this is to run the test bench + `define USBF_UFC_HADR 17 + `define USBF_RF_SEL (!wb_addr_i[17]) + `define USBF_MEM_SEL (wb_addr_i[17]) + `define USBF_SSRAM_HADR 14 + //`define USBF_ASYNC_RESET + +`else + // Modify this section to suit your implementation + `define USBF_UFC_HADR 12 + // Address Decoding for Register File select + `define USBF_RF_SEL (!wb_addr_i[12]) + // Address Decoding for Buffer Memory select + `define USBF_MEM_SEL (wb_addr_i[12]) + `define USBF_SSRAM_HADR 9 + // The next statement determines if reset is async or sync. + // If the define is uncommented the reset will be ASYNC. + //`define USBF_ASYNC_RESET +`endif + + +///////////////////////////////////////////////////////////////////// +// +// Items below this point should NOT be modified by the end user +// UNLESS you know exactly what you are doing ! +// Modify at you own risk !!! +// +///////////////////////////////////////////////////////////////////// + +// PID Encodings +`define USBF_T_PID_OUT 4'b0001 +`define USBF_T_PID_IN 4'b1001 +`define USBF_T_PID_SOF 4'b0101 +`define USBF_T_PID_SETUP 4'b1101 +`define USBF_T_PID_DATA0 4'b0011 +`define USBF_T_PID_DATA1 4'b1011 +`define USBF_T_PID_DATA2 4'b0111 +`define USBF_T_PID_MDATA 4'b1111 +`define USBF_T_PID_ACK 4'b0010 +`define USBF_T_PID_NACK 4'b1010 +`define USBF_T_PID_STALL 4'b1110 +`define USBF_T_PID_NYET 4'b0110 +`define USBF_T_PID_PRE 4'b1100 +`define USBF_T_PID_ERR 4'b1100 +`define USBF_T_PID_SPLIT 4'b1000 +`define USBF_T_PID_PING 4'b0100 +`define USBF_T_PID_RES 4'b0000 + +// The HMS_DEL is a constant for the "Half Micro Second" +// Clock pulse generator. This constant specifies how many +// Phy clocks there are between two hms_clock pulses. This +// constant plus 2 represents the actual delay. +// Example: For a 60 Mhz (16.667 nS period) Phy Clock, the +// delay must be 30 phy clocks: 500ns / 16.667nS = 30 clocks +`define USBF_HMS_DEL 5'h1c + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has 622nS in Full Speed +// mode and 400nS in High Speed mode to reply. RX_ACK_TO_VAL_FS +// and RX_ACK_TO_VAL_HS are the numbers of UTMI clock cycles +// minus 2 for Full and High Speed modes. +`define USBF_RX_ACK_TO_VAL_FS 8'd36 +`define USBF_RX_ACK_TO_VAL_HS 8'd22 + + +// After sending an OUT token the host must send a data packet. +// The host has 622nS in Full Speed mode and 400nS in High Speed +// mode to send the data packet. +// TX_DATA_TO_VAL_FS and TX_DATA_TO_VAL_HS are is the numbers of +// UTMI clock cycles minus 2. +`define USBF_TX_DATA_TO_VAL_FS 8'd36 +`define USBF_TX_DATA_TO_VAL_HS 8'd22 + + +// -------------------------------------------------- +// USB Line state & Speed Negotiation Time Values + + +// Prescaler Clear value. +// The prescaler generates a 0.25uS pulse, from a nominal PHY clock of +// 60 Mhz. 250nS/16.667ns=15. The prescaler has to be cleared every 15 +// cycles. Due to the pipeline, subtract 2 from 15, resulting in 13 cycles. +// !!! This is the only place that needs to be changed if a PHY with different +// !!! clock output is used. +`define USBF_T1_PS_250_NS 4'd13 + +// uS counter representation of 2.5uS (2.5/0.25=10) +`define USBF_T1_C_2_5_US 8'd10 + +// uS counter clear value +// The uS counter counts the time in 0.25uS intervals. It also generates +// a count enable to the mS counter, every 62.5 uS. +// The clear value is 62.5uS/0.25uS=250 cycles. +`define USBF_T1_C_62_5_US 8'd250 + +// mS counter representation of 3.0mS (3.0/0.0625=48) +`define USBF_T1_C_3_0_MS 8'd48 + +// mS counter representation of 3.125mS (3.125/0.0625=50) +`define USBF_T1_C_3_125_MS 8'd50 + +// mS counter representation of 5mS (5/0.0625=80) +`define USBF_T1_C_5_MS 8'd80 + +// Multi purpose Counter Prescaler, generate 2.5 uS period +// 2500/16.667ns=150 (minus 2 for pipeline) +`define USBF_T2_C_2_5_US 8'd148 + +// Generate 0.5mS period from the 2.5 uS clock +// 500/2.5 = 200 +`define USBF_T2_C_0_5_MS 8'd200 + +// Indicate when internal wakeup has completed +// me_cnt counts 0.5 mS intervals. E.g.: 5.0mS are (5/0.5) 10 ticks +// Must be 0 =< 10 mS +`define USBF_T2_C_WAKEUP 8'd10 + +// Indicate when 100uS have passed +// me_ps2 counts 2.5uS intervals. 100uS are (100/2.5) 40 ticks +`define USBF_T2_C_100_US 8'd40 + +// Indicate when 1.0 mS have passed +// me_cnt counts 0.5 mS intervals. 1.0mS are (1/0.5) 2 ticks +`define USBF_T2_C_1_0_MS 8'd2 + +// Indicate when 1.2 mS have passed +// me_cnt counts 0.5 mS intervals. 1.2mS are (1.2/0.5) 2 ticks +`define USBF_T2_C_1_2_MS 8'd2 + +// Indicate when 100 mS have passed +// me_cnt counts 0.5 mS intervals. 100mS are (100/0.5) 200 ticks +`define USBF_T2_C_100_MS 8'd200 + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf.v new file mode 100644 index 000000000..2cb16d575 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf.v @@ -0,0 +1,516 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Endpoint register File //// +//// This module contains all registers for ONE endpoint //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_ep_rf.v,v 1.4 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_ep_rf.v,v $ +// Revision 1.4 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.3 2001/11/04 12:22:44 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.2 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:44 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_ep_rf(clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + + idin, + ep_sel, ep_match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, dma_in_buf_sz1, dma_out_buf_avail + ); + +input clk, wclk, rst; +input [1:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output dma_req; +input dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output ep_match; // Asserted to indicate a ep no is matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID sequence error interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output dma_in_buf_sz1; // Indicates that the DMA IN buffer has 1 max_pl_sz + // packet available +output dma_out_buf_avail;// Indicates that there is space for at least + // one MAX_PL_SZ packet in the buffer + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [31:0] dout; + +// CSR +reg [12:0] csr0; +reg ots_stop; +reg [12:0] csr1; +reg [1:0] uc_bsel, uc_dpd; + +reg [5:0] iena, ienb; // Interrupt enables +reg [6:0] int_stat; // Interrupt status + +wire we0, we1, we2, we3; +reg [31:0] buf0; +reg [31:0] buf1; +reg [31:0] buf0_orig; + +reg inta, intb; + +// DMA Logic Registers +reg [11:0] dma_out_cnt; +wire dma_out_cnt_is_zero; +reg dma_out_buf_avail; +reg [11:0] dma_out_left; + +reg [11:0] dma_in_cnt; +reg dma_in_buf_sz1; + +reg dma_req_r; +wire dma_req_d; +wire dma_req_in_d; +wire dma_req_out_d; +reg r1, r2, r4, r5; +wire dma_ack_i; +reg dma_req_out_hold, dma_req_in_hold ; +reg [11:0] buf0_orig_m3; +wire dma_req_hold; +reg set_r; +reg ep_match_r; +reg int_re; + +// Aliases +wire [31:0] csr; +wire [31:0] int; +wire dma_en; +wire [10:0] max_pl_sz; +wire ep_in; +wire ep_out; + +assign csr = {uc_bsel, uc_dpd, csr1, 1'h0, ots_stop, csr0}; +assign int = {2'h0, iena, 2'h0,ienb, 9'h0, int_stat}; +assign dma_en = csr[15]; +assign max_pl_sz = csr[10:0]; +assign ep_in = csr[27:26]==2'b01; +assign ep_out = csr[27:26]==2'b10; + +/////////////////////////////////////////////////////////////////// +// +// WISHBONE Access +// + +always @(adr or csr or int or buf0 or buf1) + case(adr) // synopsys full_case parallel_case + 2'h0: dout = csr; + 2'h1: dout = int; + 2'h2: dout = buf0; + 2'h3: dout = buf1; + endcase + +assign we0 = (adr==2'h0) & we; +assign we1 = (adr==2'h1) & we; +assign we2 = (adr==2'h2) & we; +assign we3 = (adr==2'h3) & we; + +// Endpoint CSR Register +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) + begin + csr0 <= 13'h0; + csr1 <= 13'h0; + ots_stop <= 1'b0; + end + else + if(we0) + begin + csr0 <= din[12:0]; + ots_stop <= din[13]; + csr1 <= din[27:15]; + end + else + if(ots_stop && out_to_small) + csr1[8:7] <= 2'b01; + +// Endpoint Interrupt Register +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) + begin + ienb <= 6'h0; + iena <= 6'h0; + end + else + if(we1) + begin + ienb <= din[21:16]; + iena <= din[29:24]; + end + +// Endpoint Buffer Registers +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf0 <= 32'hffff_ffff; + else + if(we2) buf0 <= din; + else + if(ep_match_r && buf0_rl) buf0 <= buf0_orig; + else + if(ep_match_r && buf0_set) buf0 <= idin; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf1 <= 32'hffff_ffff; + else + if(we3) buf1 <= din; + else + if(ep_match_r && + (buf1_set || out_to_small)) buf1 <= idin; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf0_orig <= 32'hffff_ffff; + else + if(we2) buf0_orig <= din; + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + + +// Indicates that this register file matches the current +// endpoint from token +assign ep_match = (ep_sel == csr[21:18]); + +always @(posedge clk) + ep_match_r <= ep_match; + +always @(posedge clk) + int_re <= re & (adr == 2'h1); + +// Interrupt Sources +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) int_stat <= 7'h0; + else + if(int_re) int_stat <= 7'h0; + else + if(ep_match_r) + begin + if(out_to_small) int_stat[6] <= 1'b1; + if(int_seqerr_set) int_stat[5] <= 1'b1; + if(int_buf1_set) int_stat[4] <= 1'b1; + if(int_buf0_set) int_stat[3] <= 1'b1; + if(int_upid_set) int_stat[2] <= 1'b1; + if(int_crc16_set) int_stat[1] <= 1'b1; + if(int_to_set) int_stat[0] <= 1'b1; + end + +// PID toggle track bits +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) uc_dpd <= 2'h0; + else + if(ep_match_r && uc_dpd_set) uc_dpd <= idin[3:2]; + +// Buffer toggle track bits +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) uc_bsel <= 2'h0; + else + if(ep_match_r && uc_bsel_set) uc_bsel <= idin[1:0]; + +/////////////////////////////////////////////////////////////////// +// +// Endpoint Interrupt Generation +// + +always @(posedge wclk) + inta <= (int_stat[0] & iena[0]) | + (int_stat[1] & iena[1]) | + (int_stat[2] & iena[2]) | + (int_stat[3] & iena[3]) | + (int_stat[4] & iena[3]) | + (int_stat[5] & iena[4]) | + (int_stat[6] & iena[5]); + +always @(posedge wclk) + intb <= (int_stat[0] & ienb[0]) | + (int_stat[1] & ienb[1]) | + (int_stat[2] & ienb[2]) | + (int_stat[3] & ienb[3]) | + (int_stat[4] & ienb[3]) | + (int_stat[5] & ienb[4]) | + (int_stat[6] & ienb[5]); + +/////////////////////////////////////////////////////////////////// +// +// Endpoint DMA Request Logic +// + +// DMA OUT endpoint counter +always @(posedge clk) + if(!dma_en) dma_out_cnt <= 12'h0; + else + if(dma_ack_i) dma_out_cnt <= dma_out_cnt - 12'h1; + else + if(ep_match_r && (set_r || buf0_set || buf0_rl)) + dma_out_cnt <= dma_out_cnt + {3'h0, max_pl_sz[10:2]}; + +// If buf0_set or buf0_rl was asserted at the same time as dma_ack_i +// remember it and perform the add next cycle ... +always @(posedge clk) + set_r <= dma_ack_i & (buf0_set | buf0_rl); + +// This signal is used to keep dma_req asserted when we know there is +// plenty of data in the buffer. +// When the buffer is "low", we do one dma_req and wait to see if there +// is more data and repeat until the buffer is empty. +// This is because of the sync logic - it has to propagate first +// before we can determine that the buffer is really empty. +always @(posedge wclk) + dma_req_out_hold <= |dma_out_cnt[11:2] & ep_out; + +assign dma_out_cnt_is_zero = dma_out_cnt == 12'h0; + +// DMA IN endpoint counter +always @(posedge clk) + if(!dma_en) dma_in_cnt <= 12'h0; + else + if(dma_ack_i) dma_in_cnt <= dma_in_cnt + 12'h1; + else + if(ep_match_r && (set_r || buf0_set || buf0_rl)) + dma_in_cnt <= dma_in_cnt - {3'h0, max_pl_sz[10:2]}; + +// Indicates to Protocol Engine when we have gotten at least one packet in to buffer +// This is for IN transfers only +always @(posedge clk) + dma_in_buf_sz1 <= (dma_in_cnt >= {3'h0,max_pl_sz[10:2]}) & + (max_pl_sz[10:0] != 11'h0); + +// Indicates to Protocol Engine that there is space for at least one MAX_PL_SZ +// packet in buffer. OUT transfers only. +always @(posedge clk) + dma_out_left <= (buf0_orig[30:19] - dma_out_cnt); + +always @(posedge clk) + dma_out_buf_avail <= (dma_out_left >= {3'h0, max_pl_sz[10:2]}); + +// DMA Request Generation +assign dma_req_d = dma_en & (dma_req_in_d | dma_req_out_d); + +// For OUT +assign dma_req_out_d = ep_out & !dma_out_cnt_is_zero; + +// FOR IN +assign dma_req_in_d = ep_in & (dma_in_cnt < buf0_orig[30:19]); + + +always @(posedge wclk) + buf0_orig_m3 <= buf0_orig[30:19] - 12'h3; + +reg dma_req_in_hold2; + +always @(posedge wclk) + dma_req_in_hold2 <= (dma_in_cnt < buf0_orig_m3); + +always @(posedge wclk) + dma_req_in_hold <= ep_in & |buf0_orig[30:21]; + +assign dma_req_hold = ep_out ? dma_req_out_hold : (dma_req_in_hold & dma_req_in_hold2); + +// Generate a Sync. Request +assign dma_req = dma_req_r; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) dma_req_r <= 1'b0; + else + if(r1 && !r2) dma_req_r <= 1'b1; + else + if(dma_ack && !dma_req_hold) dma_req_r <= 1'b0; + +always @(posedge wclk) + r1 <= dma_req_d & !r2 & !r4 & !r5; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) r2 <= 1'b0; + else + if(r1) r2 <= 1'b1; + else + if(r4) r2 <= 1'b0; + +// Synchronize ACK +reg dma_ack_wr1; +reg dma_ack_clr1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) dma_ack_wr1 <= 1'b0; + else + if(dma_ack) dma_ack_wr1 <= 1'b1; + else + if(dma_ack_clr1) dma_ack_wr1 <= 1'b0; + +always @(posedge wclk) + dma_ack_clr1 <= r4; + +always @(posedge clk) + r4 <= dma_ack_wr1; + +always @(posedge clk) + r5 <= r4; + +assign dma_ack_i = r5; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf_dummy.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf_dummy.v new file mode 100644 index 000000000..e486792ea --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_ep_rf_dummy.v @@ -0,0 +1,152 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Dummy Endpoint register File //// +//// This module contains termination for registers in ONE //// +//// endpoint. It is used to replace the actual endpoint //// +//// register file for non existing endpoints. //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_ep_rf_dummy.v,v 1.2 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_ep_rf_dummy.v,v $ +// Revision 1.2 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.1 2001/03/31 12:45:13 rudi +// +// This is the endpoint register file for non existing endpoints. It will be used for +// endpoints that are commented out in the usd_defines.v file. +// It will terminate all outputs to a known good level ... +// +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_ep_rf_dummy( + clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + + idin, + ep_sel, ep_match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, dma_in_buf_sz1, dma_out_buf_avail + ); + +input clk, wclk, rst; +input [1:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output dma_req; +input dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output ep_match; // Asserted to indicate a ep no is matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID sequence error interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output dma_in_buf_sz1; // Indicates that the DMA IN buffer has 1 max_pl_sz + // packet available +output dma_out_buf_avail;// Indicates that there is space for at least + // one MAX_PL_SZ packet in the buffer + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + +assign dout = 32'h0; +assign inta = 1'b0; +assign intb = 1'b0; +assign dma_req = 1'b0; +assign ep_match = 1'b0; +assign csr = 32'h0; +assign buf0 = 32'hffff_ffff; +assign buf1 = 32'hffff_ffff; +assign dma_in_buf_sz1 = 1'b0; +assign dma_out_buf_avail = 1'b0; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_idma.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_idma.v new file mode 100644 index 000000000..68d525f16 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_idma.v @@ -0,0 +1,636 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Internal DMA Engine //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_idma.v,v 1.8 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_idma.v,v $ +// Revision 1.8 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.7 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.6 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.5 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/19 14:38:57 rudi +// +// Fixed TxValid handling bug. +// +// Revision 1.2 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:50 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_idma( clk, rst, + + // Packet Disassembler/Assembler interface + rx_data_st, rx_data_valid, rx_data_done, + send_data, tx_data_st, rd_next, + + // Protocol Engine + rx_dma_en, tx_dma_en, + abort, idma_done, + buf_size, dma_en, + send_zero_length, + + // Register File Manager Interface + adr, size, sizu_c, + + // Memory Arb interface + madr, mdout, mdin, mwe, mreq, mack + ); + +parameter SSRAM_HADR = 14; + +// Packet Disassembler/Assembler interface +input clk, rst; +input [7:0] rx_data_st; +input rx_data_valid; +input rx_data_done; +output send_data; +output [7:0] tx_data_st; +input rd_next; + +// Protocol Engine +input rx_dma_en; // Allows the data to be stored +input tx_dma_en; // Allows for data to be retrieved +input abort; // Abort Transfer (time_out, crc_err or rx_error) +output idma_done; // DMA is done +input [13:0] buf_size; // Actual buffer size +input dma_en; // External DMA enabled +input send_zero_length; + +// Register File Manager Interface +input [SSRAM_HADR + 2:0] adr; // Byte Address +input [13:0] size; // Size in bytes +output [10:0] sizu_c; // Up and Down counting size registers, used to update + +// Memory Arb interface +output [SSRAM_HADR:0] madr; // word address +output [31:0] mdout; +input [31:0] mdin; +output mwe; +output mreq; +input mack; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [7:0] // synopsys enum state + IDLE = 8'b00000001, + WAIT_MRD = 8'b00000010, + MEM_WR = 8'b00000100, + MEM_WR1 = 8'b00001000, + MEM_WR2 = 8'b00010000, + MEM_RD1 = 8'b00100000, + MEM_RD2 = 8'b01000000, + MEM_RD3 = 8'b10000000; + +reg [7:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg tx_dma_en_r, rx_dma_en_r; + +reg [SSRAM_HADR:0] adr_cw; // Internal word address counter +reg [2:0] adr_cb; // Internal byte address counter +reg [SSRAM_HADR:0] adrw_next; // next address +reg [SSRAM_HADR:0] adrw_next1; // next address (after overrun check) +reg [SSRAM_HADR:0] last_buf_adr; // Last Buffer Address +reg [2:0] adrb_next; // next byte address +reg [13:0] sizd_c; // Internal size counter +reg [10:0] sizu_c; // Internal size counter +wire adr_incw; +wire adr_incb; +wire siz_dec; +wire siz_inc; + +reg word_done; // Indicates that a word has been + // assembled +reg mreq_d; // Memory request from State Machine +reg [31:0] dtmp_r; // Temp data assembly register +reg [31:0] dout_r; // Data output register +reg mwe_d; // Memory Write enable +reg dtmp_sel; // Selects tmp data register for pre-fetch + +reg sizd_is_zero; // Indicates when all bytes have been + // transferred +wire sizd_is_zero_d; + +reg [7:0] tx_data_st; // Data output to packet assembler +reg [31:0] rd_buf0, rd_buf1; // Mem Rd. buffers for TX +reg rd_first; // Indicates initial fill of buffers + +reg idma_done; // DMA transfer is done + +reg mack_r; +wire send_data; // Enable UTMI Transmitter +reg send_data_r; + +reg word_done_r; +reg wr_last; +reg wr_last_en; +reg wr_done; +reg wr_done_r; +reg dtmp_sel_r; +reg mwe; +reg rx_data_done_r2; +wire fill_buf0, fill_buf1; +wire adrb_is_3; + +reg rx_data_done_r; +reg rx_data_valid_r; +reg [7:0] rx_data_st_r; + +reg send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// Memory Arb interface +// + +// Memory Request +assign mreq = (mreq_d & !mack_r) | word_done_r; + +// Output Data +assign mdout = dout_r; + +// Memory Address +assign madr = adr_cw; + +always @(posedge clk) + mwe <= mwe_d; + +always @(posedge clk) + mack_r <= mreq & mack; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + rx_data_valid_r <= rx_data_valid; + +always @(posedge clk) + rx_data_st_r <= rx_data_st; + +always @(posedge clk) + rx_data_done_r <= rx_data_done; + +always @(posedge clk) + rx_data_done_r2 <= rx_data_done_r; + +// Generate one cycle pulses for tx and rx dma enable +always @(posedge clk) + tx_dma_en_r <= tx_dma_en; + +always @(posedge clk) + rx_dma_en_r <= rx_dma_en; + +always @(posedge clk) + send_zero_length_r <= send_zero_length; + +// address counter +always @(posedge clk) + if(rx_dma_en_r || tx_dma_en_r) adr_cw <= adr[SSRAM_HADR + 2:2]; + else adr_cw <= adrw_next1; + +always @(posedge clk) + last_buf_adr <= adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size }; + +always @(dma_en or adrw_next or last_buf_adr) + if(adrw_next == last_buf_adr && dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}}; + else adrw_next1 = adrw_next; + +always @(adr_incw or adr_cw) + if(adr_incw) adrw_next = adr_cw + {{SSRAM_HADR{1'b0}}, 1'b1}; + else adrw_next = adr_cw; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) adr_cb <= 3'h0; + else + if(rx_dma_en_r || tx_dma_en_r) adr_cb <= adr[2:0]; + else adr_cb <= adrb_next; + +always @(adr_incb or adr_cb) + if(adr_incb) adrb_next = adr_cb + 3'h1; + else adrb_next = adr_cb; + +assign adr_incb = rx_data_valid_r | rd_next; +assign adr_incw = !dtmp_sel_r & mack_r; + +// Size Counter (counting backward from input size) +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sizd_c <= 14'h3fff; + else + if(tx_dma_en || tx_dma_en_r) sizd_c <= size; + else + if(siz_dec) sizd_c <= sizd_c - 14'h1; + +assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0)); + +assign sizd_is_zero_d = sizd_c == 14'h0; + +always @(posedge clk) + sizd_is_zero <= sizd_is_zero_d; + +// Size Counter (counting up from zero) +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sizu_c <= 11'h0; + else + // Do I need to add "abort" in the next line ??? + if(rx_dma_en_r) sizu_c <= 11'h0; + else + if(siz_inc) sizu_c <= sizu_c + 11'h1; + +assign siz_inc = rx_data_valid_r; + +// DMA Done Indicator +always @(posedge clk) + idma_done <= (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en; + +/////////////////////////////////////////////////////////////////// +// +// RX Logic +// + +always @(posedge clk) + dtmp_sel_r <= dtmp_sel; + +// Memory data input +always @(posedge clk) + if(dtmp_sel_r) dtmp_r <= mdin; + else + if(rx_data_valid_r) + begin + if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= rx_data_st_r; + end + +always @(posedge clk) + word_done <= ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last; + +always @(posedge clk) + word_done_r <= word_done & !word_done_r; + +// Store output data and address when we got a word +always @(posedge clk) + if(word_done) dout_r <= dtmp_r; + +always @(posedge clk) + wr_last <= (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en; + +always @(posedge clk) + wr_done_r <= rx_data_done_r; + +always @(posedge clk) + wr_done <= wr_done_r; + +/////////////////////////////////////////////////////////////////// +// +// TX Logic +// + +// Fill TX Buffers +always @(posedge clk) + if(fill_buf0) rd_buf0 <= mdin; + +always @(posedge clk) + if(fill_buf1) rd_buf1 <= mdin; + +always @(adrb_next or rd_buf0 or rd_buf1) + case(adrb_next[2:0]) // synopsys full_case parallel_case + 3'h0: tx_data_st = rd_buf0[07:00]; + 3'h1: tx_data_st = rd_buf0[15:08]; + 3'h2: tx_data_st = rd_buf0[23:16]; + 3'h3: tx_data_st = rd_buf0[31:24]; + 3'h4: tx_data_st = rd_buf1[07:00]; + 3'h5: tx_data_st = rd_buf1[15:08]; + 3'h6: tx_data_st = rd_buf1[23:16]; + 3'h7: tx_data_st = rd_buf1[31:24]; + endcase + +assign fill_buf0 = !adr_cw[0] & mack_r; +assign fill_buf1 = adr_cw[0] & mack_r; + +assign adrb_is_3 = adr_cb[1:0] == 2'h3; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) send_data_r <= 1'b0; + else + if(rd_first) send_data_r <= 1'b1; + else + if(((sizd_c==14'h1) && rd_next) || sizd_is_zero_d) send_data_r <= 1'b0; + +assign send_data = send_data_r | send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// IDMA Load/Store State Machine +// + +// store incoming data to memory until rx_data done +// First pre-fetch data from memory, so that bytes can be stuffed properly + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or mack_r or abort or rx_dma_en_r or tx_dma_en_r or + sizd_is_zero or wr_last or wr_done or rx_data_done_r2 or + rd_next or adrb_is_3 or send_zero_length_r) + begin + next_state = state; // Default do not change state + mreq_d = 1'b0; + mwe_d = 1'b0; + rd_first = 1'b0; + dtmp_sel = 1'b0; + wr_last_en = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered IDLE state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(rst) +begin +if(rx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: rx_dma_en_r is unknown. (%t)", $time); +if(tx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: tx_dma_en_r is unknown. (%t)", $time); +if(abort === 1'bx) $display("ERROR: IDMA: IDLE: abort is unknown. (%t)", $time); +end +`endif +// synopsys translate_on + + if(rx_dma_en_r && !abort) + begin + next_state = WAIT_MRD; + end + if(tx_dma_en_r && !abort && !send_zero_length_r) + begin + next_state = MEM_RD1; + end + end + + WAIT_MRD: // Pre-fetch a word from memory + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered WAIT_MRD state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: WAIT_MRD: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: WAIT_MRD: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_WR; + else + begin + dtmp_sel = 1'b1; + mreq_d = 1'b1; + end + end + + MEM_WR: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR: abort is unknown. (%t)", $time); +if(rx_data_done_r2 === 1'bx) $display("ERROR: IDMA: MEM_WR: rx_data_done_r2 is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + if(abort) next_state = IDLE; + else + if(rx_data_done_r2) + begin + wr_last_en = 1'b1; + next_state = MEM_WR1; + end + + end + MEM_WR1: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR1 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR1: abort is unknown. (%t)", $time); +if(wr_last === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_last is unknown. (%t)", $time); +if(wr_done === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_done is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + wr_last_en = 1'b1; + if(abort) next_state = IDLE; + else + if(wr_last) next_state = MEM_WR2; + else + if(wr_done) next_state = IDLE; + end + + MEM_WR2: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR2 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_WR2: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + if(mack_r) next_state = IDLE; + end + + MEM_RD1: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD1 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD1: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD1: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mreq_d = 1'b1; + if(mack_r) rd_first = 1'b1; + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_RD2; + end + MEM_RD2: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD2 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD2: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD2: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mreq_d = 1'b1; + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_RD3; + end + MEM_RD3: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD3 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD3: abort is unknown. (%t)", $time); +if(sizd_is_zero===1'bx) $display("ERROR: IDMA: MEM_RD3: sizd_is_zero is unknown. (%t)", $time); +if(adrb_is_3 === 1'bx) $display("ERROR: IDMA: MEM_RD3: adrb_is_3 is unknown. (%t)", $time); +if(rd_next === 1'bx) $display("ERROR: IDMA: MEM_RD3: rd_next is unknown. (%t)", $time); +`endif +// synopsys translate_on + + if(sizd_is_zero || abort) next_state = IDLE; + else + if(adrb_is_3 && rd_next) next_state = MEM_RD2; + end + endcase + + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_mem_arb.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_mem_arb.v new file mode 100644 index 000000000..c5fc24254 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_mem_arb.v @@ -0,0 +1,196 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Memory Buffer Arbiter //// +//// Arbitrates between the internal DMA and external bus //// +//// interface for the internal buffer memory //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_mem_arb.v,v 1.3 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_mem_arb.v,v $ +// Revision 1.3 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.2 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:52 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_mem_arb( phy_clk, wclk, rst, + + // SSRAM Interface + sram_adr, sram_din, sram_dout, sram_re, sram_we, + + // IDMA Memory Interface + madr, mdout, mdin, mwe, mreq, mack, + + // WISHBONE Memory Interface + wadr, wdout, wdin, wwe, wreq, wack + + ); + +parameter SSRAM_HADR = 14; + +input phy_clk, wclk, rst; + +output [SSRAM_HADR:0] sram_adr; +input [31:0] sram_din; +output [31:0] sram_dout; +output sram_re, sram_we; + +input [SSRAM_HADR:0] madr; +output [31:0] mdout; +input [31:0] mdin; +input mwe; +input mreq; +output mack; + +input [SSRAM_HADR:0] wadr; +output [31:0] wdout; +input [31:0] wdin; +input wwe; +input wreq; +output wack; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire wsel; +reg [SSRAM_HADR:0] sram_adr; +reg [31:0] sram_dout; +reg sram_we; +wire mack; +wire mcyc; +reg wack_r; + +/////////////////////////////////////////////////////////////////// +// +// Memory Arbiter Logic +// + +// IDMA has always first priority + +// ----------------------------------------- +// Ctrl Signals + +assign wsel = (wreq | wack) & !mreq; + +// ----------------------------------------- +// SSRAM Specific +// Data Path +always @(wsel or wdin or mdin) + if(wsel) sram_dout = wdin; + else sram_dout = mdin; + +// Address Path +always @(wsel or wadr or madr) + if(wsel) sram_adr = wadr; + else sram_adr = madr; + +// Write Enable Path +always @(wsel or wwe or wreq or mwe or mcyc) + if(wsel) sram_we = wreq & wwe; + else sram_we = mwe & mcyc; + +assign sram_re = 1'b1; + +// ----------------------------------------- +// IDMA specific + +assign mdout = sram_din; + +assign mack = mreq; + +assign mcyc = mack; // Qualifier for writes + +// ----------------------------------------- +// WISHBONE specific +assign wdout = sram_din; + +assign wack = wack_r & !mreq; + +`ifdef USBF_ASYNC_RESET +always @(posedge phy_clk or negedge rst) +`else +always @(posedge phy_clk) +`endif + if(!rst) wack_r <= 1'b0; + else wack_r <= wreq & !mreq & !wack; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pa.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pa.v new file mode 100644 index 000000000..c3231d840 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pa.v @@ -0,0 +1,386 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Packet Assembler //// +//// Assembles Token and Data USB packets //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pa.v,v 1.6 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_pa.v,v $ +// Revision 1.6 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.3 2001/09/19 14:38:57 rudi +// +// Fixed TxValid handling bug. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:54 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pa( clk, rst, + + // UTMI TX I/F + tx_data, tx_valid, tx_valid_last, tx_ready, + tx_first, + + // Protocol Engine Interface + send_token, token_pid_sel, + send_data, data_pid_sel, + send_zero_length, + + // IDMA Interface + tx_data_st, rd_next + ); + +input clk, rst; + +// UTMI TX Interface +output [7:0] tx_data; +output tx_valid; +output tx_valid_last; +input tx_ready; +output tx_first; + +// Protocol Engine Interface +input send_token; +input [1:0] token_pid_sel; +input send_data; +input [1:0] data_pid_sel; +input send_zero_length; + +// IDMA Interface +input [7:0] tx_data_st; +output rd_next; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [4:0] // synopsys enum state + IDLE = 5'b00001, + DATA = 5'b00010, + CRC1 = 5'b00100, + CRC2 = 5'b01000, + WAIT = 5'b10000; + +reg [4:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg last; +reg rd_next; + +reg [7:0] token_pid, data_pid; // PIDs from selectors +reg [7:0] tx_data_d; +reg [7:0] tx_data_data; +reg dsel; +reg tx_valid_d; +reg send_token_r; +reg [7:0] tx_spec_data; +reg crc_sel1, crc_sel2; +reg tx_first_r; +reg send_data_r; +wire crc16_clr; +reg [15:0] crc16; +wire [15:0] crc16_next; +wire [15:0] crc16_rev; +wire crc16_add; +reg send_data_r2; +reg tx_valid_r; +reg tx_valid_r1; +reg zero_length_r; +reg send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + send_zero_length_r <= send_zero_length; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) zero_length_r <= 1'b0; + else + if(last) zero_length_r <= 1'b0; + else + if(crc16_clr) zero_length_r <= send_zero_length_r; + +always @(posedge clk) + tx_valid_r1 <= tx_valid; + +always @(posedge clk) + tx_valid_r <= tx_valid_r1; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) send_token_r <= 1'b0; + else + if(send_token) send_token_r <= 1'b1; + else + if(tx_ready) send_token_r <= 1'b0; + +// PID Select +always @(token_pid_sel) + case(token_pid_sel) // synopsys full_case parallel_case + 2'd0: token_pid = { ~`USBF_T_PID_ACK, `USBF_T_PID_ACK}; + 2'd1: token_pid = { ~`USBF_T_PID_NACK, `USBF_T_PID_NACK}; + 2'd2: token_pid = {~`USBF_T_PID_STALL, `USBF_T_PID_STALL}; + 2'd3: token_pid = { ~`USBF_T_PID_NYET, `USBF_T_PID_NYET}; + endcase + +always @(data_pid_sel) + case(data_pid_sel) // synopsys full_case parallel_case + 2'd0: data_pid = { ~`USBF_T_PID_DATA0, `USBF_T_PID_DATA0}; + 2'd1: data_pid = { ~`USBF_T_PID_DATA1, `USBF_T_PID_DATA1}; + 2'd2: data_pid = { ~`USBF_T_PID_DATA2, `USBF_T_PID_DATA2}; + 2'd3: data_pid = { ~`USBF_T_PID_MDATA, `USBF_T_PID_MDATA}; + endcase + +// Data path Muxes + +always @(send_token or send_token_r or token_pid or tx_data_data) + if(send_token || send_token_r) tx_data_d = token_pid; + else tx_data_d = tx_data_data; + +always @(dsel or tx_data_st or tx_spec_data) + if(dsel) tx_data_data = tx_spec_data; + else tx_data_data = tx_data_st; + +always @(crc_sel1 or crc_sel2 or data_pid or crc16_rev) + if(!crc_sel1 && !crc_sel2) tx_spec_data = data_pid; + else + if(crc_sel1) tx_spec_data = crc16_rev[15:8]; // CRC 1 + else tx_spec_data = crc16_rev[7:0]; // CRC 2 + +assign tx_data = tx_data_d; + +// TX Valid assignment +assign tx_valid_last = send_token | last; +assign tx_valid = tx_valid_d; + +always @(posedge clk) + tx_first_r <= send_token | send_data; + +assign tx_first = (send_token | send_data) & ! tx_first_r; + +// CRC Logic +always @(posedge clk) + send_data_r <= send_data; + +always @(posedge clk) + send_data_r2 <= send_data_r; + +assign crc16_clr = send_data & !send_data_r; + +assign crc16_add = !zero_length_r & (send_data_r & !send_data_r2) | (rd_next & !crc_sel1); + +always @(posedge clk) + if(crc16_clr) crc16 <= 16'hffff; + else + if(crc16_add) crc16 <= crc16_next; + + +usbf_crc16 u1( + .crc_in( crc16 ), + .din( {tx_data_st[0], tx_data_st[1], + tx_data_st[2], tx_data_st[3], + tx_data_st[4], tx_data_st[5], + tx_data_st[6], tx_data_st[7]} ), + .crc_out( crc16_next ) ); + +assign crc16_rev[15] = ~crc16[8]; +assign crc16_rev[14] = ~crc16[9]; +assign crc16_rev[13] = ~crc16[10]; +assign crc16_rev[12] = ~crc16[11]; +assign crc16_rev[11] = ~crc16[12]; +assign crc16_rev[10] = ~crc16[13]; +assign crc16_rev[9] = ~crc16[14]; +assign crc16_rev[8] = ~crc16[15]; +assign crc16_rev[7] = ~crc16[0]; +assign crc16_rev[6] = ~crc16[1]; +assign crc16_rev[5] = ~crc16[2]; +assign crc16_rev[4] = ~crc16[3]; +assign crc16_rev[3] = ~crc16[4]; +assign crc16_rev[2] = ~crc16[5]; +assign crc16_rev[1] = ~crc16[6]; +assign crc16_rev[0] = ~crc16[7]; + +/////////////////////////////////////////////////////////////////// +// +// Transmit/Encode state machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or send_data or tx_ready or tx_valid_r or send_zero_length_r) + begin + next_state = state; // Default don't change current state + tx_valid_d = 1'b0; + dsel = 1'b0; + rd_next = 1'b0; + last = 1'b0; + crc_sel1 = 1'b0; + crc_sel2 = 1'b0; + case(state) // synopsys full_case parallel_case + IDLE: + begin + if(send_zero_length_r && send_data) + begin + tx_valid_d = 1'b1; + next_state = WAIT; + dsel = 1'b1; + end + else + if(send_data) // Send DATA packet + begin + tx_valid_d = 1'b1; + next_state = DATA; + dsel = 1'b1; + end + end + DATA: + begin + if(tx_ready && tx_valid_r) + rd_next = 1'b1; + + tx_valid_d = 1'b1; + if(!send_data && tx_ready && tx_valid_r) + begin + dsel = 1'b1; + crc_sel1 = 1'b1; + next_state = CRC1; + end + end + WAIT: // In case of early tx_ready ... + begin + crc_sel1 = 1'b1; + dsel = 1'b1; + tx_valid_d = 1'b1; + next_state = CRC1; + end + CRC1: + begin + dsel = 1'b1; + tx_valid_d = 1'b1; + if(tx_ready) + begin + last = 1'b1; + crc_sel2 = 1'b1; + next_state = CRC2; + end + else + begin + tx_valid_d = 1'b1; + crc_sel1 = 1'b1; + end + + end + CRC2: + begin + dsel = 1'b1; + crc_sel2 = 1'b1; + if(tx_ready) + begin + next_state = IDLE; + end + else + begin + last = 1'b1; + end + + end + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pd.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pd.v new file mode 100644 index 000000000..cbc0a97aa --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pd.v @@ -0,0 +1,437 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Packet Disassembler //// +//// Disassembles Token and Data USB packets //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pd.v,v 1.7 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_pd.v,v $ +// Revision 1.7 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.4 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.3 2001/09/10 15:54:20 rudi +// +// Fixed crc5 checking. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:59 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pd( clk, rst, + + // UTMI RX I/F + rx_data, rx_valid, rx_active, rx_err, + + // PID Information + pid_OUT, pid_IN, pid_SOF, pid_SETUP, + pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, + pid_ACK, pid_NACK, pid_STALL, pid_NYET, + pid_PRE, pid_ERR, pid_SPLIT, pid_PING, + pid_cks_err, + + // Token Information + token_fadr, token_endp, token_valid, crc5_err, + frame_no, + + // Receive Data Output + rx_data_st, rx_data_valid, rx_data_done, crc16_err, + + // Misc. + seq_err + ); + +input clk, rst; + + //UTMI RX Interface +input [7:0] rx_data; +input rx_valid, rx_active, rx_err; + + // Decoded PIDs (used when token_valid is asserted) +output pid_OUT, pid_IN, pid_SOF, pid_SETUP; +output pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +output pid_ACK, pid_NACK, pid_STALL, pid_NYET; +output pid_PRE, pid_ERR, pid_SPLIT, pid_PING; +output pid_cks_err; // Indicates a PID checksum error + + +output [6:0] token_fadr; // Function address from token +output [3:0] token_endp; // Endpoint number from token +output token_valid; // Token is valid +output crc5_err; // Token crc5 error +output [10:0] frame_no; // Frame number for SOF tokens + +output [7:0] rx_data_st; // Data to memory store unit +output rx_data_valid; // Data on rx_data_st is valid +output rx_data_done; // Indicates end of a transfer +output crc16_err; // Data packet CRC 16 error + +output seq_err; // State Machine Sequence Error + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [3:0] // synopsys enum state + IDLE = 4'b0001, + ACTIVE = 4'b0010, + TOKEN = 4'b0100, + DATA = 4'b1000; + +reg [3:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg [7:0] pid; // Packet PDI +reg pid_le_sm; // PID Load enable from State Machine +wire pid_ld_en; // Enable loading of PID (all conditions) +wire pid_cks_err; // Indicates a pid checksum err + + // Decoded PID values +wire pid_OUT, pid_IN, pid_SOF, pid_SETUP; +wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +wire pid_ACK, pid_NACK, pid_STALL, pid_NYET; +wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING, pid_RES; +wire pid_TOKEN; // All TOKEN packet that we recognize +wire pid_DATA; // All DATA packets that we recognize + +reg [7:0] token0, token1; // Token Registers +reg token_le_1, token_le_2; // Latch enables for token storage registers +wire [4:0] token_crc5; + +reg [7:0] d0, d1, d2; // Data path delay line (used to filter out crcs) +reg data_valid_d; // Data Valid output from State Machine +reg data_done; // Data cycle complete output from State Machine +reg data_valid0; // Data valid delay line +reg rxv1; +reg rxv2; + +reg seq_err; // State machine sequence error + +reg got_pid_ack; + +reg token_valid_r1; +reg token_valid_str1; + +reg rx_active_r; + +wire [4:0] crc5_out; +wire [4:0] crc5_out2; +wire crc16_clr; +reg [15:0] crc16_sum; +wire [15:0] crc16_out; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// PID Decoding Logic +assign pid_ld_en = pid_le_sm & rx_active & rx_valid; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) pid <= 8'hf0; + else + if(pid_ld_en) pid <= rx_data; + +assign pid_cks_err = (pid[3:0] != ~pid[7:4]); + +assign pid_OUT = pid[3:0] == `USBF_T_PID_OUT; +assign pid_IN = pid[3:0] == `USBF_T_PID_IN; +assign pid_SOF = pid[3:0] == `USBF_T_PID_SOF; +assign pid_SETUP = pid[3:0] == `USBF_T_PID_SETUP; +assign pid_DATA0 = pid[3:0] == `USBF_T_PID_DATA0; +assign pid_DATA1 = pid[3:0] == `USBF_T_PID_DATA1; +assign pid_DATA2 = pid[3:0] == `USBF_T_PID_DATA2; +assign pid_MDATA = pid[3:0] == `USBF_T_PID_MDATA; +assign pid_ACK = pid[3:0] == `USBF_T_PID_ACK; +assign pid_NACK = pid[3:0] == `USBF_T_PID_NACK; +assign pid_STALL = pid[3:0] == `USBF_T_PID_STALL; +assign pid_NYET = pid[3:0] == `USBF_T_PID_NYET; +assign pid_PRE = pid[3:0] == `USBF_T_PID_PRE; +assign pid_ERR = pid[3:0] == `USBF_T_PID_ERR; +assign pid_SPLIT = pid[3:0] == `USBF_T_PID_SPLIT; +assign pid_PING = pid[3:0] == `USBF_T_PID_PING; +assign pid_RES = pid[3:0] == `USBF_T_PID_RES; + +assign pid_TOKEN = pid_OUT | pid_IN | pid_SOF | pid_SETUP | pid_PING; +assign pid_DATA = pid_DATA0 | pid_DATA1 | pid_DATA2 | pid_MDATA; + +// Token Decoding LOGIC +always @(posedge clk) + if(token_le_1) token0 <= rx_data; + +always @(posedge clk) + if(token_le_2) token1 <= rx_data; + +always @(posedge clk) + token_valid_r1 <= token_le_2; + +always @(posedge clk) + token_valid_str1 <= token_valid_r1 | got_pid_ack; + +assign token_valid = token_valid_str1; + +// CRC 5 should perform the check in one cycle (flow through logic) +// 11 bits and crc5 input, 1 bit output +assign crc5_err = token_valid & (crc5_out2 != token_crc5); + +usbf_crc5 u0( + .crc_in( 5'h1f ), + .din( { token_fadr[0], + token_fadr[1], + token_fadr[2], + token_fadr[3], + token_fadr[4], + token_fadr[5], + token_fadr[6], + token_endp[0], + token_endp[1], + token_endp[2], + token_endp[3] } ), + .crc_out( crc5_out ) ); + +// Invert and reverse result bits +assign crc5_out2 = ~{crc5_out[0], crc5_out[1], crc5_out[2], crc5_out[3], + crc5_out[4]}; + +assign frame_no = { token1[2:0], token0}; +assign token_fadr = token0[6:0]; +assign token_endp = {token1[2:0], token0[7]}; +assign token_crc5 = token1[7:3]; + +// Data receiving logic +// build a delay line and stop when we are about to get crc +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rxv1 <= 1'b0; + else + if(data_valid_d) rxv1 <= 1'b1; + else + if(data_done) rxv1 <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rxv2 <= 1'b0; + else + if(rxv1 && data_valid_d)rxv2 <= 1'b1; + else + if(data_done) rxv2 <= 1'b0; + +always @(posedge clk) + data_valid0 <= rxv2 & data_valid_d; + +always @(posedge clk) + begin + if(data_valid_d) d0 <= rx_data; + if(data_valid_d) d1 <= d0; + if(data_valid_d) d2 <= d1; + end + +assign rx_data_st = d2; +assign rx_data_valid = data_valid0; +assign rx_data_done = data_done; + +// crc16 accumulates rx_data as long as data_valid_d is asserted. +// when data_done is asserted, crc16 reports status, and resets itself +// next cycle. +always @(posedge clk) + rx_active_r <= rx_active; + +assign crc16_clr = rx_active & !rx_active_r; + +always @(posedge clk) + if(crc16_clr) crc16_sum <= 16'hffff; + else + if(data_valid_d) crc16_sum <= crc16_out; + +usbf_crc16 u1( + .crc_in( crc16_sum ), + .din( {rx_data[0], rx_data[1], rx_data[2], rx_data[3], + rx_data[4], rx_data[5], rx_data[6], rx_data[7]} ), + .crc_out( crc16_out ) ); + +// Verify against polynomial +assign crc16_err = data_done & (crc16_sum != 16'h800d); + +/////////////////////////////////////////////////////////////////// +// +// Receive/Decode State machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or rx_valid or rx_active or rx_err or pid_ACK or pid_TOKEN + or pid_DATA) + begin + next_state = state; // Default don't change current state + pid_le_sm = 1'b0; + token_le_1 = 1'b0; + token_le_2 = 1'b0; + data_valid_d = 1'b0; + data_done = 1'b0; + seq_err = 1'b0; + got_pid_ack = 1'b0; + case(state) // synopsys full_case parallel_case + IDLE: + begin + pid_le_sm = 1'b1; + if(rx_valid && rx_active) next_state = ACTIVE; + end + ACTIVE: + begin + // Received a ACK from Host + if(pid_ACK && !rx_err) + begin + got_pid_ack = 1'b1; + if(!rx_active) next_state = IDLE; + end + else + // Receiving a TOKEN + if(pid_TOKEN && rx_valid && rx_active && !rx_err) + begin + token_le_1 = 1'b1; + next_state = TOKEN; + end + else + // Receiving DATA + if(pid_DATA && rx_valid && rx_active && !rx_err) + begin + data_valid_d = 1'b1; + next_state = DATA; + end + else + if( !rx_active || rx_err || + (rx_valid && !(pid_TOKEN || pid_DATA)) ) + begin + seq_err = !rx_err; + if(!rx_active) next_state = IDLE; + end + end + TOKEN: + begin + if(rx_valid && rx_active && !rx_err) + begin + token_le_2 = 1'b1; + next_state = IDLE; + end + else + if(!rx_active || rx_err) + begin + seq_err = !rx_err; + if(!rx_active) next_state = IDLE; + end + end + DATA: + begin + if(rx_valid && rx_active && !rx_err) data_valid_d = 1'b1; + if(!rx_active || rx_err) + begin + data_done = 1'b1; + if(!rx_active) next_state = IDLE; + end + end + + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pe.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pe.v new file mode 100644 index 000000000..756453fa4 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pe.v @@ -0,0 +1,1095 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Protocol Engine //// +//// Performs automatic protocol functions //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pe.v,v 1.8 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_pe.v,v $ +// Revision 1.8 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.7 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.6 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.5 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:07 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pe( clk, rst, + + // UTMI Interfaces + tx_valid, rx_active, + + // PID Information + pid_OUT, pid_IN, pid_SOF, pid_SETUP, + pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, + pid_ACK, pid_NACK, pid_STALL, pid_NYET, + pid_PRE, pid_ERR, pid_SPLIT, pid_PING, + + // Speed Mode + mode_hs, + + // Token Information + token_valid, crc5_err, + + // Receive Data Output + rx_data_valid, rx_data_done, crc16_err, + + // Packet Assembler Interface + send_token, token_pid_sel, + data_pid_sel, send_zero_length, + + // IDMA Interface + rx_dma_en, tx_dma_en, + abort, idma_done, + adr, size, buf_size, + sizu_c, dma_en, + + // Register File Interface + fsel, idin, + dma_in_buf_sz1, dma_out_buf_avail, + ep_sel, match, nse_err, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1 + + ); + +parameter SSRAM_HADR = 14; + +input clk, rst; +input tx_valid, rx_active; + +// Packet Disassembler Interface + // Decoded PIDs (used when token_valid is asserted) +input pid_OUT, pid_IN, pid_SOF, pid_SETUP; +input pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +input pid_ACK, pid_NACK, pid_STALL, pid_NYET; +input pid_PRE, pid_ERR, pid_SPLIT, pid_PING; + +input mode_hs; +input token_valid; // Token is valid +input crc5_err; // Token crc5 error + +input rx_data_valid; // Data on rx_data_st is valid +input rx_data_done; // Indicates end of a transfer +input crc16_err; // Data packet CRC 16 error + +// Packet Assembler Interface +output send_token; +output [1:0] token_pid_sel; +output [1:0] data_pid_sel; +output send_zero_length; + +// IDMA Interface +output rx_dma_en; // Allows the data to be stored +output tx_dma_en; // Allows for data to be retrieved +output abort; // Abort Transfer (time_out, crc_err or rx_error) +input idma_done; // DMA is done indicator +output [SSRAM_HADR + 2:0] adr; // Byte Address +output [13:0] size; // Size in bytes +output [13:0] buf_size; // Actual buffer size +input [10:0] sizu_c; // Up and Down counting size registers, used to update +output dma_en; // USB external DMA mode enabled + +// Register File interface +input fsel; // This function is selected +output [31:0] idin; // Data Output +input [3:0] ep_sel; // Endpoint Number Input +input match; // Endpoint Matched +output nse_err; // no such endpoint error +input dma_in_buf_sz1, dma_out_buf_avail; + +output buf0_rl; // Reload Buf 0 with original values +output buf0_set; // Write to buf 0 +output buf1_set; // Write to buf 1 +output uc_bsel_set; // Write to the uc_bsel field +output uc_dpd_set; // Write to the uc_dpd field +output int_buf1_set; // Set buf1 full/empty interrupt +output int_buf0_set; // Set buf0 full/empty interrupt +output int_upid_set; // Set unsupported PID interrupt +output int_crc16_set; // Set CRC16 error interrupt +output int_to_set; // Set time out interrupt +output int_seqerr_set; // Set PID sequence error interrupt +output out_to_small; // OUT packet was to small for DMA operation + +input [31:0] csr; // Internal CSR Output +input [31:0] buf0; // Internal Buf 0 Output +input [31:0] buf1; // Internal Buf 1 Output + + + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// tx token decoding +parameter ACK = 0, + NACK = 1, + STALL = 2, + NYET = 3; + +// State decoding +parameter [9:0] // synopsys enum state + IDLE = 10'b000000_0001, + TOKEN = 10'b000000_0010, + IN = 10'b000000_0100, + IN2 = 10'b000000_1000, + OUT = 10'b000001_0000, + OUT2A = 10'b000010_0000, + OUT2B = 10'b000100_0000, + UPDATEW = 10'b001000_0000, + UPDATE = 10'b010000_0000, + UPDATE2 = 10'b100000_0000; + +reg [1:0] token_pid_sel; +reg [1:0] token_pid_sel_d; +reg send_token; +reg send_token_d; +reg rx_dma_en, tx_dma_en; +reg int_seqerr_set_d; +reg int_seqerr_set; +reg int_upid_set; + +reg match_r; + +// Endpoint Decoding +wire IN_ep, OUT_ep, CTRL_ep; // Endpoint Types +wire txfr_iso, txfr_bulk; // Transfer Types +wire ep_disabled, ep_stall; // Endpoint forced conditions + +wire lrg_ok, sml_ok; // Packet size acceptance +wire [1:0] tr_fr; // Number of transfers per micro-frame +wire [10:0] max_pl_sz; // Max payload size + +wire [1:0] uc_dpd, uc_bsel; + +// Buffer checks +wire buf_sel; +reg buf0_na, buf1_na; +wire [SSRAM_HADR + 2:0] buf0_adr, buf1_adr; +wire [13:0] buf0_sz, buf1_sz; +reg [9:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +// PID next and current decoders +reg [1:0] next_dpid; +reg [1:0] this_dpid; +reg pid_seq_err; +wire [1:0] tr_fr_d; + +wire [13:0] size_next; +wire buf_smaller; + +reg [SSRAM_HADR + 2:0] adr; +reg [13:0] new_size; +reg [13:0] new_sizeb; +reg buffer_full; +reg buffer_empty; +wire [SSRAM_HADR + 2:0] new_adr; +reg buffer_done; + +reg no_bufs0, no_bufs1; +wire no_bufs; + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has XXXnS to reply. +// "rx_ack_to" indicates when this time has expired. +// rx_ack_to_clr, clears the timer +reg rx_ack_to_clr; +reg rx_ack_to_clr_d; +reg rx_ack_to; +reg [7:0] rx_ack_to_cnt; + +// After sending a OUT token the host must send a data packet. +// The host has XX nS to send the packet. "tx_data_to" indicates +// when this time has expired. +// tx_data_to_clr, clears the timer +wire tx_data_to_clr; +reg tx_data_to; +reg [7:0] tx_data_to_cnt; + +wire [7:0] rx_ack_to_val, tx_data_to_val; + +reg int_set_en; + +wire [1:0] next_bsel; +reg buf_set_d; +reg uc_stat_set_d; +reg [31:0] idin; +reg buf0_set, buf1_set; +reg uc_bsel_set; +reg uc_dpd_set; +reg buf0_rl_d; +reg buf0_rl; +wire no_buf0_dma; +reg buf0_st_max; +reg buf1_st_max; + +reg [SSRAM_HADR + 2:0] adr_r; +reg [13:0] size_next_r; + +reg in_token; +reg out_token; +reg setup_token; + +wire in_op, out_op; // Indicate a IN or OUT operation +reg to_small; // Indicates a "to small packer" error +reg to_large; // Indicates a "to large packer" error + +reg buffer_overflow; +reg [1:0] allow_pid; + +reg nse_err; +reg out_to_small, out_to_small_r; +reg abort; + +reg buf0_not_aloc, buf1_not_aloc; + +reg send_zero_length; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// Endpoint/CSR Decoding +assign IN_ep = csr[27:26]==2'b01; +assign OUT_ep = csr[27:26]==2'b10; +assign CTRL_ep = csr[27:26]==2'b00; + +assign txfr_iso = csr[25:24]==2'b01; +assign txfr_bulk = csr[25:24]==2'b10; + +assign ep_disabled = csr[23:22]==2'b01; +assign ep_stall = csr[23:22]==2'b10; + +assign lrg_ok = csr[17]; +assign sml_ok = csr[16]; +assign dma_en = csr[15] & !CTRL_ep; + +assign tr_fr = csr[12:11]; +assign max_pl_sz = csr[10:0]; + +assign uc_dpd = csr[29:28]; +assign uc_bsel = csr[31:30]; + +// Buffer decoding and allocation checks +assign buf0_adr = buf0[SSRAM_HADR + 2:0]; +assign buf1_adr = buf1[SSRAM_HADR + 2:0]; +assign buf0_sz = buf0[30:17]; +assign buf1_sz = buf1[30:17]; + +// Buffers Not Available +always @(posedge clk) + buf0_na <= buf0[31] | ( &buf0_adr ); + +always @(posedge clk) + buf1_na <= buf1[31] | ( &buf1_adr ); + +// Buffer Not Allocated +always @(posedge clk) + buf0_not_aloc <= &buf0_adr; + +always @(posedge clk) + buf1_not_aloc <= &buf1_adr; + +always @(posedge clk) + match_r <= match; + +// No Such Endpoint Indicator +always @(posedge clk) + nse_err <= token_valid & (pid_OUT | pid_IN | pid_SETUP) & !match; + +always @(posedge clk) + send_token <= send_token_d; + +always @(posedge clk) + token_pid_sel <= token_pid_sel_d; + +/////////////////////////////////////////////////////////////////// +// +// Data Pid Sequencer +// + +assign tr_fr_d = mode_hs ? tr_fr : 2'h0; + +always @(posedge clk) // tr/mf:ep/type:tr/type:last dpd + casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case + 8'b0?_01_01_??: next_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf + + 8'b10_01_01_?0: next_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf + 8'b10_01_01_?1: next_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf + + 8'b11_01_01_00: next_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_01: next_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_10: next_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf + + 8'b0?_10_01_??: next_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf + + 8'b10_10_01_??: // ISO txfr. OUT, 2 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA1}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + + 8'b11_10_01_00: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + 8'b11_10_01_01: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b10; + 2'b01: next_dpid <= 2'b00; + endcase + end + 8'b11_10_01_10: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + + 8'b??_01_00_?0, // IN/OUT endpoint only + 8'b??_10_00_?0: next_dpid <= 2'b01; // INT transfers + + 8'b??_01_00_?1, // IN/OUT endpoint only + 8'b??_10_00_?1: next_dpid <= 2'b00; // INT transfers + + 8'b??_01_10_?0, // IN/OUT endpoint only + 8'b??_10_10_?0: next_dpid <= 2'b01; // BULK transfers + + 8'b??_01_10_?1, // IN/OUT endpoint only + 8'b??_10_10_?1: next_dpid <= 2'b00; // BULK transfers + + 8'b??_00_??_??: // CTRL Endpoint + casex({setup_token, in_op, out_op, uc_dpd}) // synopsys full_case parallel_case + 5'b1_??_??: next_dpid <= 2'b11; // SETUP operation + 5'b0_10_0?: next_dpid <= 2'b11; // IN operation + 5'b0_10_1?: next_dpid <= 2'b01; // IN operation + 5'b0_01_?0: next_dpid <= 2'b11; // OUT operation + 5'b0_01_?1: next_dpid <= 2'b10; // OUT operation + endcase + + endcase + +// Current PID decoder + +// Allow any PID for ISO. transfers when mode full speed or tr_fr is zero +always @(pid_DATA0 or pid_DATA1 or pid_DATA2 or pid_MDATA) + case({pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA} ) // synopsys full_case parallel_case + 4'b1000: allow_pid = 2'b00; + 4'b0100: allow_pid = 2'b01; + 4'b0010: allow_pid = 2'b10; + 4'b0001: allow_pid = 2'b11; + endcase + +always @(posedge clk) // tf/mf:ep/type:tr/type:last dpd + casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case + 8'b0?_01_01_??: this_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf + + 8'b10_01_01_?0: this_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf + 8'b10_01_01_?1: this_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf + + 8'b11_01_01_00: this_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_01: this_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_10: this_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf + + 8'b00_10_01_??: this_dpid <= allow_pid; // ISO txfr. OUT, 0 tr/mf + 8'b01_10_01_??: this_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf + + 8'b10_10_01_?0: this_dpid <= 2'b11; // ISO txfr. OUT, 2 tr/mf + 8'b10_10_01_?1: this_dpid <= 2'b01; // ISO txfr. OUT, 2 tr/mf + + 8'b11_10_01_00: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf + 8'b11_10_01_01: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf + 8'b11_10_01_10: this_dpid <= 2'b10; // ISO txfr. OUT, 3 tr/mf + + 8'b??_01_00_?0, // IN/OUT endpoint only + 8'b??_10_00_?0: this_dpid <= 2'b00; // INT transfers + 8'b??_01_00_?1, // IN/OUT endpoint only + 8'b??_10_00_?1: this_dpid <= 2'b01; // INT transfers + + 8'b??_01_10_?0, // IN/OUT endpoint only + 8'b??_10_10_?0: this_dpid <= 2'b00; // BULK transfers + 8'b??_01_10_?1, // IN/OUT endpoint only + 8'b??_10_10_?1: this_dpid <= 2'b01; // BULK transfers + + 8'b??_00_??_??: // CTRL Endpoint + casex({setup_token,in_op, out_op, uc_dpd}) // synopsys full_case parallel_case + 5'b1_??_??: this_dpid <= 2'b00; // SETUP operation + 5'b0_10_0?: this_dpid <= 2'b00; // IN operation + 5'b0_10_1?: this_dpid <= 2'b01; // IN operation + 5'b0_01_?0: this_dpid <= 2'b00; // OUT operation + 5'b0_01_?1: this_dpid <= 2'b01; // OUT operation + endcase + endcase + +// Assign PID for outgoing packets +assign data_pid_sel = this_dpid; + +// Verify PID for incoming data packets +always @(posedge clk) + pid_seq_err <= !( (this_dpid==2'b00 & pid_DATA0) | + (this_dpid==2'b01 & pid_DATA1) | + (this_dpid==2'b10 & pid_DATA2) | + (this_dpid==2'b11 & pid_MDATA) ); + +/////////////////////////////////////////////////////////////////// +// +// IDMA Setup & src/dst buffer select +// + +// For Control endpoints things are different: +// buffer0 is used for OUT (incoming) data packets +// buffer1 is used for IN (outgoing) data packets + +// Keep track of last token for control endpoints +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) in_token <= 1'b0; + else + if(pid_IN) in_token <= 1'b1; + else + if(pid_OUT || pid_SETUP) in_token <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) out_token <= 1'b0; + else + if(pid_OUT || pid_SETUP) out_token <= 1'b1; + else + if(pid_IN) out_token <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) setup_token <= 1'b0; + else + if(pid_SETUP) setup_token <= 1'b1; + else + if(pid_OUT || pid_IN) setup_token <= 1'b0; + +// Indicates if we are performing an IN operation +assign in_op = IN_ep | (CTRL_ep & in_token); + +// Indicates if we are performing an OUT operation +assign out_op = OUT_ep | (CTRL_ep & out_token); + +// Select buffer: buf_sel==0 buffer0; buf_sel==1 buffer1 +assign buf_sel = dma_en ? 1'b0 : CTRL_ep ? in_token : ((uc_bsel[0] | buf0_na) & !buf1_na); + +// Select Address for IDMA +always @(posedge clk) + adr <= buf_sel ? buf1_adr : buf0_adr; + +// Size from Buffer +assign buf_size = buf_sel ? buf1_sz : buf0_sz; + +// Determine which is smaller: buffer or max_pl_sz +assign buf_smaller = buf_size < {3'h0, max_pl_sz}; + +// Determine actual size for this transfer (for IDMA) IN endpoint only +// (OUT endpoint uses sizeu_c from IDMA) +assign size_next = buf_smaller ? buf_size : max_pl_sz; +assign size = size_next; // "size" is an output for IDMA + +// Buffer Full (only for OUT endpoints) +// Indicates that there is not enough space in the buffer for one +// more max_pl_sz packet +always @(posedge clk) + buffer_full <= new_size < {3'h0, max_pl_sz}; + +// Buffer Empty (only for IN endpoints) +// Indicates that there are zero bytes left in the buffer +always @(posedge clk) + buffer_empty <= (new_size == 14'h0); + +// Joint buffer full/empty flag This is the "USED" flag +always @(posedge clk) + buffer_done <= in_op ? buffer_empty : buffer_full; + +// No More buffer space at all (For high speed out - issue NYET) +assign no_buf0_dma = dma_en & + ((IN_ep & !dma_in_buf_sz1) | (OUT_ep & !dma_out_buf_avail)); + +always @(posedge clk) + buf0_st_max <= (buf0_sz < {3'h0, max_pl_sz}); + +always @(posedge clk) + buf1_st_max <= (buf1_sz < {3'h0, max_pl_sz}); + +always @(posedge clk) + no_bufs0 <= buf0_na | no_buf0_dma | + (buf_sel ? buf0_st_max : (buffer_full & !dma_en)); + +always @(posedge clk) + no_bufs1 <= buf1_na | (buf_sel ? buffer_full : buf1_st_max); + +assign no_bufs = no_bufs0 & no_bufs1; + +// New Size (to be written to register file) +always @(posedge clk) + new_sizeb <= (out_op && dma_en) ? max_pl_sz : (in_op ? size_next : sizu_c); + +always @(posedge clk) + new_size <= buf_size - new_sizeb; + + +// New Buffer Address (to be written to register file) +always @(posedge clk) + adr_r <= adr; + +always @(posedge clk) + size_next_r <= size_next; + +assign new_adr = adr_r[SSRAM_HADR + 2:0] + + ((out_op && dma_en) ? {{SSRAM_HADR + 2-10{1'b0}}, max_pl_sz[10:0]} : + (in_op ? {{SSRAM_HADR + 2-13{1'b0}}, size_next_r[13:0] } : + { {SSRAM_HADR + 2-10{1'b0}}, sizu_c[10:0]})); + +// Buffer Overflow +always @(posedge clk) + buffer_overflow <= ( {3'h0, sizu_c} > buf_size) & rx_data_valid; + + +// OUT packet smaller than MAX_PL_SZ in DMA operation +always @(posedge clk) + out_to_small_r <= uc_stat_set_d & out_op & dma_en & (sizu_c != max_pl_sz); + +always @(posedge clk) + out_to_small <= out_to_small_r; + +/////////////////////////////////////////////////////////////////// +// +// Determine if packet is to small or to large +// This is used to NACK and ignore packet for OUT endpoints +// + +always @(posedge clk) + to_small <= !sml_ok & (sizu_c < max_pl_sz); + +always @(posedge clk) + to_large <= !lrg_ok & (sizu_c > max_pl_sz); + +/////////////////////////////////////////////////////////////////// +// +// Register File Update Logic +// + +assign next_bsel = dma_en ? 2'h0 : buffer_done ? uc_bsel + 2'h1 : uc_bsel; // FIX_ME + +always @(posedge clk) + idin[31:17] <= out_to_small_r ? {4'h0,sizu_c} : {buffer_done,new_size}; + +always @(posedge clk) + idin[SSRAM_HADR + 2:4] <= out_to_small_r ? buf0_adr[SSRAM_HADR + 2:4] : + new_adr[SSRAM_HADR + 2:4]; + +always @(posedge clk) + if(buf_set_d) idin[3:0] <= new_adr[3:0]; + else + if(out_to_small_r) idin[3:0] <= buf0_adr[3:0]; + else idin[3:0] <= {next_dpid, next_bsel}; + +always @(posedge clk) + buf0_set <= !buf_sel & buf_set_d; + +always @(posedge clk) + buf1_set <= buf_sel & buf_set_d; + +always @(posedge clk) + uc_bsel_set <= uc_stat_set_d; + +always @(posedge clk) + uc_dpd_set <= uc_stat_set_d; + +always @(posedge clk) + buf0_rl <= buf0_rl_d; + +// Abort signal +always @(posedge clk) + abort <= buffer_overflow | (match & (state != IDLE) ) | (match_r & to_large); + +/////////////////////////////////////////////////////////////////// +// +// TIME OUT TIMERS +// + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has 622nS in Full Speed +// mode and 400nS in High Speed mode to reply. +// "rx_ack_to" indicates when this time has expired. +// rx_ack_to_clr, clears the timer + +always @(posedge clk) + rx_ack_to_clr <= tx_valid | rx_ack_to_clr_d; + +always @(posedge clk) + if(rx_ack_to_clr) rx_ack_to_cnt <= 8'h0; + else rx_ack_to_cnt <= rx_ack_to_cnt + 8'h1; + +always @(posedge clk) + rx_ack_to <= (rx_ack_to_cnt == rx_ack_to_val); + +assign rx_ack_to_val = mode_hs ? `USBF_RX_ACK_TO_VAL_HS : `USBF_RX_ACK_TO_VAL_FS; + +// After sending a OUT token the host must send a data packet. +// The host has 622nS in Full Speed mode and 400nS in High Speed +// mode to send the data packet. +// "tx_data_to" indicates when this time has expired. +// "tx_data_to_clr" clears the timer + +assign tx_data_to_clr = rx_active; + +always @(posedge clk) + if(tx_data_to_clr) tx_data_to_cnt <= 8'h0; + else tx_data_to_cnt <= tx_data_to_cnt + 8'h1; + +always @(posedge clk) + tx_data_to <= (tx_data_to_cnt == tx_data_to_val); + +assign tx_data_to_val = mode_hs ? `USBF_TX_DATA_TO_VAL_HS : `USBF_TX_DATA_TO_VAL_FS; + +/////////////////////////////////////////////////////////////////// +// +// Interrupts +// +reg pid_OUT_r, pid_IN_r, pid_PING_r, pid_SETUP_r; + +assign int_buf1_set = !buf_sel & buffer_done & int_set_en & !buf1_not_aloc; +assign int_buf0_set = buf_sel & buffer_done & int_set_en & !buf0_not_aloc; + +always @(posedge clk) + pid_OUT_r <= pid_OUT; + +always @(posedge clk) + pid_IN_r <= pid_IN; + +always @(posedge clk) + pid_PING_r <= pid_PING; + +always @(posedge clk) + pid_SETUP_r <= pid_SETUP; + +always @(posedge clk) + int_upid_set <= match_r & !pid_SOF & ( + ( OUT_ep & !(pid_OUT_r | pid_PING_r)) | + ( IN_ep & !pid_IN_r) | + (CTRL_ep & !(pid_IN_r | pid_OUT_r | pid_PING_r | pid_SETUP_r)) + ); + +assign int_to_set = ((state == IN2) & rx_ack_to) | ((state == OUT) & tx_data_to); + +assign int_crc16_set = rx_data_done & crc16_err; + +always @(posedge clk) + int_seqerr_set <= int_seqerr_set_d; + +/////////////////////////////////////////////////////////////////// +// +// Main Protocol State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else + if(match) state <= IDLE; + else state <= next_state; + +always @(state or ep_stall or buf0_na or buf1_na or + pid_seq_err or idma_done or token_valid or pid_ACK or rx_data_done or + tx_data_to or crc16_err or ep_disabled or no_bufs or mode_hs + or dma_en or rx_ack_to or pid_PING or txfr_iso or to_small or to_large or + CTRL_ep or pid_IN or pid_OUT or IN_ep or OUT_ep or pid_SETUP or pid_SOF + or match_r or abort or buffer_done or no_buf0_dma or max_pl_sz) + begin + next_state = state; + token_pid_sel_d = ACK; + send_token_d = 1'b0; + rx_dma_en = 1'b0; + tx_dma_en = 1'b0; + buf_set_d = 1'b0; + uc_stat_set_d = 1'b0; + buf0_rl_d = 1'b0; + int_set_en = 1'b0; + rx_ack_to_clr_d = 1'b1; + int_seqerr_set_d = 1'b0; + send_zero_length = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IDLE (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(rst && match_r && !ep_disabled && !pid_SOF) + begin + if(match_r === 1'bx) $display("ERROR: IDLE: match_r is unknown. (%t)", $time); + if(ep_disabled === 1'bx)$display("ERROR: IDLE: ep_disabled is unknown. (%t)", $time); + if(pid_SOF === 1'bx) $display("ERROR: IDLE: pid_SOF is unknown. (%t)", $time); + if(ep_stall === 1'bx) $display("ERROR: IDLE: ep_stall is unknown. (%t)", $time); + if(buf0_na === 1'bx) $display("ERROR: IDLE: buf0_na is unknown. (%t)", $time); + if(buf1_na === 1'bx) $display("ERROR: IDLE: buf1_na is unknown. (%t)", $time); + if(no_buf0_dma === 1'bx)$display("ERROR: IDLE: no_buf0_dma is unknown. (%t)", $time); + if(CTRL_ep === 1'bx) $display("ERROR: IDLE: CTRL_ep is unknown. (%t)", $time); + if(pid_IN === 1'bx) $display("ERROR: IDLE: pid_IN is unknown. (%t)", $time); + if(pid_OUT === 1'bx) $display("ERROR: IDLE: pid_OUT is unknown. (%t)", $time); + if(pid_SETUP === 1'bx) $display("ERROR: IDLE: pid_SETUP is unknown. (%t)", $time); + if(pid_PING === 1'bx) $display("ERROR: IDLE: pid_PING is unknown. (%t)", $time); + if(mode_hs === 1'bx) $display("ERROR: IDLE: mode_hs is unknown. (%t)", $time); + if(IN_ep === 1'bx) $display("ERROR: IDLE: IN_ep is unknown. (%t)", $time); + if(OUT_ep === 1'bx) $display("ERROR: IDLE: OUT_ep is unknown. (%t)", $time); + end +`endif +// synopsys translate_on + + if(match_r && !ep_disabled && !pid_SOF) + begin + if(ep_stall) // Halt Forced send STALL + begin + token_pid_sel_d = STALL; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if( (buf0_na && buf1_na) || no_buf0_dma || + (CTRL_ep && pid_IN && buf1_na) || + (CTRL_ep && pid_OUT && buf0_na) + ) + begin // No buffers send NAK + token_pid_sel_d = NACK; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if(pid_PING && mode_hs) + begin + token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if(IN_ep || (CTRL_ep && pid_IN)) + begin + if(max_pl_sz == 11'h0) send_zero_length = 1'b1; + tx_dma_en = 1'b1; + next_state = IN; + end + else + if(OUT_ep || (CTRL_ep && (pid_OUT || pid_SETUP))) + begin + rx_dma_en = 1'b1; + next_state = OUT; + end + end + end + + TOKEN: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state TOKEN (%t)", $time); +`endif +// synopsys translate_on + next_state = IDLE; + end + + IN: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IN (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(idma_done === 1'bx) $display("ERROR: IN: idma_done is unknown. (%t)", $time); + if(txfr_iso === 1'bx) $display("ERROR: IN: txfr_iso is unknown. (%t)", $time); +`endif +// synopsys translate_on + rx_ack_to_clr_d = 1'b0; + if(idma_done) + begin + if(txfr_iso) next_state = UPDATE; + else next_state = IN2; + end + + end + IN2: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IN2 (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(rx_ack_to === 1'bx) $display("ERROR: IN2: rx_ack_to is unknown. (%t)", $time); + if(token_valid === 1'bx)$display("ERROR: IN2: token_valid is unknown. (%t)", $time); + if(pid_ACK === 1'bx) $display("ERROR: IN2: pid_ACK is unknown. (%t)", $time); +`endif +// synopsys translate_on + rx_ack_to_clr_d = 1'b0; + // Wait for ACK from HOST or Timeout + if(rx_ack_to) next_state = IDLE; + else + if(token_valid && pid_ACK) + begin + next_state = UPDATE; + end + end + + OUT: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(tx_data_to === 1'bx) $display("ERROR: OUT: tx_data_to is unknown. (%t)", $time); + if(crc16_err === 1'bx) $display("ERROR: OUT: crc16_err is unknown. (%t)", $time); + if(abort === 1'bx) $display("ERROR: OUT: abort is unknown. (%t)", $time); + if(rx_data_done === 1'bx)$display("ERROR: OUT: rx_data_done is unknown. (%t)", $time); + if(txfr_iso === 1'bx) $display("ERROR: OUT: txfr_iso is unknown. (%t)", $time); + if(pid_seq_err === 1'bx)$display("ERROR: OUT: rx_data_done is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(tx_data_to || crc16_err || abort ) + next_state = IDLE; + else + if(rx_data_done) + begin // Send Ack + if(txfr_iso) + begin + if(pid_seq_err) int_seqerr_set_d = 1'b1; + next_state = UPDATEW; + end + else next_state = OUT2A; + end + end + + OUT2A: + begin // This is a delay State to NACK to small or to + // large packets. this state could be skipped +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT2A (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(abort === 1'bx) $display("ERROR: OUT2A: abort is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(abort) next_state = IDLE; + else next_state = OUT2B; + end + OUT2B: + begin // Send ACK/NACK/NYET +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT2B (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(abort === 1'bx) $display("ERROR: OUT2B: abort is unknown. (%t)", $time); + if(to_small === 1'bx) $display("ERROR: OUT2B: to_small is unknown. (%t)", $time); + if(to_large === 1'bx) $display("ERROR: OUT2B: to_large is unknown. (%t)", $time); + if(pid_seq_err === 1'bx)$display("ERROR: OUT2B: rx_data_done is unknown. (%t)", $time); + if(mode_hs === 1'bx) $display("ERROR: OUT2B: mode_hs is unknown. (%t)", $time); + if(no_bufs === 1'bx) $display("ERROR: OUT2B: no_bufs is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(abort) next_state = IDLE; + else + if(to_small || to_large) + begin + token_pid_sel_d = NACK; + next_state = IDLE; + end + else + if(pid_seq_err) + begin + token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = IDLE; + end + else + begin + if(mode_hs && no_bufs) token_pid_sel_d = NYET; + else token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = UPDATE; + end + end + + UPDATEW: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATEW (%t)", $time); +`endif +// synopsys translate_on + next_state = UPDATE; + end + UPDATE: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATE (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(buffer_done === 1'bx) $display("ERROR: UPDATE: buffer_done is unknown. (%t)", $time); + if(dma_en === 1'bx) $display("ERROR: UPDATE: dma_en is unknown. (%t)", $time); +`endif +// synopsys translate_on + // Interrupts + int_set_en = 1'b1; + // Buffer (used, size, adr) set or reload + if(buffer_done && dma_en) + begin + buf0_rl_d = 1'b1; + end + else + begin + buf_set_d = 1'b1; + end + next_state = UPDATE2; + end + UPDATE2: // Update Register File & state + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATE2 (%t)", $time); +`endif +// synopsys translate_on + // pid sequence & buffer usage + uc_stat_set_d = 1'b1; + next_state = IDLE; + end + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pl.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pl.v new file mode 100644 index 000000000..ff8b4bbe6 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_pl.v @@ -0,0 +1,483 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Protocol Layer //// +//// This block is typically referred to as the SEI in USB //// +//// Specification. It encapsulates the Packet Assembler, //// +//// disassembler, protocol engine and internal DMA //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pl.v,v 1.5 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_pl.v,v $ +// Revision 1.5 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.4 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:11:11 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pl( clk, rst, + + // UTMI Interface + rx_data, rx_valid, rx_active, rx_err, + tx_data, tx_valid, tx_valid_last, tx_ready, + tx_first, tx_valid_out, + mode_hs, usb_reset, usb_suspend, usb_attached, + + // memory interface + madr, mdout, mdin, mwe, mreq, mack, + + // Register File Interface + fa, idin, + ep_sel, match, + dma_in_buf_sz1, dma_out_buf_avail, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, csr, buf0, buf1, + + // Misc + frm_nat, + pid_cs_err, nse_err, + crc5_err + ); + +parameter SSRAM_HADR = 14; + +// UTMI Interface +input clk, rst; +input [7:0] rx_data; +input rx_valid, rx_active, rx_err; +output [7:0] tx_data; +output tx_valid; +output tx_valid_last; +input tx_ready; +output tx_first; +input tx_valid_out; +input mode_hs; // High Speed Mode +input usb_reset; // USB Reset +input usb_suspend; // USB Suspend +input usb_attached; // Attached to USB + +// Memory Arbiter Interface +output [SSRAM_HADR:0] madr; // word address +output [31:0] mdout; +input [31:0] mdin; +output mwe; +output mreq; +input mack; + +// Register File interface +input [6:0] fa; // Function Address (as set by the controller) +output [31:0] idin; // Data Input +output [3:0] ep_sel; // Endpoint Number Input +input match; // Endpoint Matched +input dma_in_buf_sz1; +input dma_out_buf_avail; +output nse_err; // no such endpoint error + +output buf0_rl; // Reload Buf 0 with original values +output buf0_set; // Write to buf 0 +output buf1_set; // Write to buf 1 +output uc_bsel_set; // Write to the uc_bsel field +output uc_dpd_set; // Write to the uc_dpd field +output int_buf1_set; // Set buf1 full/empty interrupt +output int_buf0_set; // Set buf0 full/empty interrupt +output int_upid_set; // Set unsupported PID interrupt +output int_crc16_set; // Set CRC16 error interrupt +output int_to_set; // Set time out interrupt +output int_seqerr_set; // Set PID sequence error interrupt +output out_to_small; // OUT packet was to small for DMA operation + +input [31:0] csr; // Internal CSR Output +input [31:0] buf0; // Internal Buf 0 Output +input [31:0] buf1; // Internal Buf 1 Output + +// Misc +output pid_cs_err; // pid checksum error +output crc5_err; // crc5 error +output [31:0] frm_nat; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// Packet Disassembler Interface +wire clk, rst; +wire [7:0] rx_data; +wire pid_OUT, pid_IN, pid_SOF, pid_SETUP; +wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +wire pid_ACK, pid_NACK, pid_STALL, pid_NYET; +wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING; +wire [6:0] token_fadr; +wire token_valid; +wire crc5_err; +wire [10:0] frame_no; +wire [7:0] rx_data_st; +wire rx_data_valid; +wire rx_data_done; +wire crc16_err; +wire rx_seq_err; + +// Packet Assembler Interface +wire send_token; +wire [1:0] token_pid_sel; +wire send_data; +wire [1:0] data_pid_sel; +wire [7:0] tx_data_st; +wire rd_next; + +// IDMA Interface +wire rx_dma_en; // Allows the data to be stored +wire tx_dma_en; // Allows for data to be retrieved +wire abort; // Abort Transfer (time_out, crc_err or rx_error) +wire idma_done; // DMA is done +wire [SSRAM_HADR + 2:0] adr; // Byte Address +wire [13:0] size; // Size in bytes +wire [10:0] sizu_c; // Up and Down counting size registers, used + // to update +wire [13:0] buf_size; // Actual buffer size +wire dma_en; // external dma enabled + +// Memory Arbiter Interface +wire [SSRAM_HADR:0] madr; // word address +wire [31:0] mdout; +wire [31:0] mdin; +wire mwe; +wire mreq; +wire mack; + +// Local signals +wire pid_bad, pid_bad1, pid_bad2; + +reg hms_clk; // 0.5 Micro Second Clock +reg [4:0] hms_cnt; +reg [10:0] frame_no_r; // Current Frame Number register +wire frame_no_we; +reg frame_no_same; // Indicates current and prev. frame numbers + // are equal +reg [3:0] mfm_cnt; // Micro Frame Counter +reg [11:0] sof_time; // Time since last sof +reg clr_sof_time; +wire fsel; // This Function is selected +wire match_o; + +reg frame_no_we_r; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// PIDs we should never receive +assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE | + pid_ERR | pid_SPLIT; + +// PIDs we should never get in full speed mode (high speed mode only) +assign pid_bad2 = !mode_hs & pid_PING; + +// All bad pids +assign pid_bad = pid_bad1 | pid_bad2; + +assign match_o = !pid_bad & fsel & match & token_valid & !crc5_err; + +// Frame Number (from SOF token) +assign frame_no_we = token_valid & !crc5_err & pid_SOF; + +always @(posedge clk) + frame_no_we_r <= frame_no_we; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) frame_no_r <= 11'h0; + else + if(frame_no_we_r) frame_no_r <= frame_no; + +// Micro Frame Counter +always @(posedge clk) + frame_no_same <= frame_no_we & (frame_no_r == frame_no); + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) mfm_cnt <= 4'h0; + else + if(frame_no_we_r && !frame_no_same) + mfm_cnt <= 4'h0; + else + if(frame_no_same) mfm_cnt <= mfm_cnt + 4'h1; + +//SOF delay counter +always @(posedge clk) + clr_sof_time <= frame_no_we; + +always @(posedge clk) + if(clr_sof_time) sof_time <= 12'h0; + else + if(hms_clk) sof_time <= sof_time + 12'h1; + +assign frm_nat = {mfm_cnt, 1'b0, frame_no_r, 4'h0, sof_time}; + +// 0.5 Micro Seconds Clock Generator +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) hms_cnt <= 5'h0; + else + if(hms_clk || frame_no_we_r) hms_cnt <= 5'h0; + else hms_cnt <= hms_cnt + 5'h1; + +always @(posedge clk) + hms_clk <= (hms_cnt == `USBF_HMS_DEL); + +/////////////////////////////////////////////////////////////////// + +// This function is addressed +assign fsel = (token_fadr == fa); + +/////////////////////////////////////////////////////////////////// +// +// Module Instantiations +// + +//Packet Decoder +usbf_pd u0( .clk( clk ), + .rst( rst ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .pid_OUT( pid_OUT ), + .pid_IN( pid_IN ), + .pid_SOF( pid_SOF ), + .pid_SETUP( pid_SETUP ), + .pid_DATA0( pid_DATA0 ), + .pid_DATA1( pid_DATA1 ), + .pid_DATA2( pid_DATA2 ), + .pid_MDATA( pid_MDATA ), + .pid_ACK( pid_ACK ), + .pid_NACK( pid_NACK ), + .pid_STALL( pid_STALL ), + .pid_NYET( pid_NYET ), + .pid_PRE( pid_PRE ), + .pid_ERR( pid_ERR ), + .pid_SPLIT( pid_SPLIT ), + .pid_PING( pid_PING ), + .pid_cks_err( pid_cs_err ), + .token_fadr( token_fadr ), + .token_endp( ep_sel ), + .token_valid( token_valid ), + .crc5_err( crc5_err ), + .frame_no( frame_no ), + .rx_data_st( rx_data_st ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .crc16_err( crc16_err ), + .seq_err( rx_seq_err ) + ); + +// Packet Assembler +usbf_pa u1( .clk( clk ), + .rst( rst ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .send_token( send_token ), + .token_pid_sel( token_pid_sel ), + .send_data( send_data ), + .data_pid_sel( data_pid_sel ), + .send_zero_length( send_zero_length ), + .tx_data_st( tx_data_st ), + .rd_next( rd_next ) + ); + +// Internal DMA / Memory Arbiter Interface +usbf_idma #(SSRAM_HADR) + u2( .clk( clk ), + .rst( rst ), + .rx_data_st( rx_data_st ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .send_data( send_data ), + .tx_data_st( tx_data_st ), + .rd_next( rd_next ), + .rx_dma_en( rx_dma_en ), + .tx_dma_en( tx_dma_en ), + .abort( abort ), + .idma_done( idma_done ), + .adr( adr ), + .size( size ), + .buf_size( buf_size ), + .dma_en( dma_en ), + .send_zero_length( send_zero_length ), + .madr( madr ), + .sizu_c( sizu_c ), + .mdout( mdout ), + .mdin( mdin ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ) + ); + +// Protocol Engine +usbf_pe #(SSRAM_HADR) + u3( .clk( clk ), + .rst( rst ), + .tx_valid( tx_valid_out ), + .rx_active( rx_active ), + .pid_OUT( pid_OUT ), + .pid_IN( pid_IN ), + .pid_SOF( pid_SOF ), + .pid_SETUP( pid_SETUP ), + .pid_DATA0( pid_DATA0 ), + .pid_DATA1( pid_DATA1 ), + .pid_DATA2( pid_DATA2 ), + .pid_MDATA( pid_MDATA ), + .pid_ACK( pid_ACK ), + .pid_NACK( pid_NACK ), + .pid_STALL( pid_STALL ), + .pid_NYET( pid_NYET ), + .pid_PRE( pid_PRE ), + .pid_ERR( pid_ERR ), + .pid_SPLIT( pid_SPLIT ), + .pid_PING( pid_PING ), + .mode_hs( mode_hs ), + .token_valid( token_valid ), + .crc5_err( crc5_err ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .crc16_err( crc16_err ), + .send_token( send_token ), + .token_pid_sel( token_pid_sel ), + .data_pid_sel( data_pid_sel ), + .send_zero_length( send_zero_length ), + .rx_dma_en( rx_dma_en ), + .tx_dma_en( tx_dma_en ), + .abort( abort ), + .idma_done( idma_done ), + .adr( adr ), + .size( size ), + .buf_size( buf_size ), + .sizu_c( sizu_c ), + .dma_en( dma_en ), + .fsel( fsel ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match_o ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .nse_err( nse_err ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ) + ); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_rf.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_rf.v new file mode 100644 index 000000000..54c85a500 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_rf.v @@ -0,0 +1,1909 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Register File //// +//// This module contains all top level registers and //// +//// instantiates the register files for endpoints //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_rf.v,v 1.6 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_rf.v,v $ +// Revision 1.6 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/11/03 03:26:23 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB controll signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:32 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_rf( clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + idin, + ep_sel, match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, + funct_adr, + dma_in_buf_sz1, dma_out_buf_avail, + + // Misc + frm_nat, + utmi_vend_stat, utmi_vend_ctrl, utmi_vend_wr, + line_stat, usb_attached, mode_hs, suspend, + attached, usb_reset, pid_cs_err, nse_err, + crc5_err, rx_err, rf_resume_req + ); + +input clk, wclk, rst; +input [6:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output [15:0] dma_req; +input [15:0] dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output match; // Endpoint Matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID Sequence Error Interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output [6:0] funct_adr; // Function Address +output dma_in_buf_sz1, dma_out_buf_avail; + +input [31:0] frm_nat; + +input [7:0] utmi_vend_stat; // UTMI Vendor C/S bus +output [3:0] utmi_vend_ctrl; +output utmi_vend_wr; + +input [1:0] line_stat; // Below are signals for interrupt generation +input usb_attached; +input mode_hs; +input suspend; +input attached; +input usb_reset; +input nse_err; +input pid_cs_err; +input crc5_err; +input rx_err; +output rf_resume_req; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire [31:0] ep0_dout, ep1_dout, ep2_dout, ep3_dout; +wire [31:0] ep4_dout, ep5_dout, ep6_dout, ep7_dout; +wire [31:0] ep8_dout, ep9_dout, ep10_dout, ep11_dout; +wire [31:0] ep12_dout, ep13_dout, ep14_dout, ep15_dout; + +wire ep0_re, ep1_re, ep2_re, ep3_re; +wire ep4_re, ep5_re, ep6_re, ep7_re; +wire ep8_re, ep9_re, ep10_re, ep11_re; +wire ep12_re, ep13_re, ep14_re, ep15_re; + +wire ep0_we, ep1_we, ep2_we, ep3_we; +wire ep4_we, ep5_we, ep6_we, ep7_we; +wire ep8_we, ep9_we, ep10_we, ep11_we; +wire ep12_we, ep13_we, ep14_we, ep15_we; + +wire ep0_inta, ep1_inta, ep2_inta, ep3_inta; +wire ep4_inta, ep5_inta, ep6_inta, ep7_inta; +wire ep8_inta, ep9_inta, ep10_inta, ep11_inta; +wire ep12_inta, ep13_inta, ep14_inta, ep15_inta; + +wire ep0_intb, ep1_intb, ep2_intb, ep3_intb; +wire ep4_intb, ep5_intb, ep6_intb, ep7_intb; +wire ep8_intb, ep9_intb, ep10_intb, ep11_intb; +wire ep12_intb, ep13_intb, ep14_intb, ep15_intb; + +wire ep0_match, ep1_match, ep2_match, ep3_match; +wire ep4_match, ep5_match, ep6_match, ep7_match; +wire ep8_match, ep9_match, ep10_match, ep11_match; +wire ep12_match, ep13_match, ep14_match, ep15_match; + +wire [31:0] ep0_csr, ep1_csr, ep2_csr, ep3_csr; +wire [31:0] ep4_csr, ep5_csr, ep6_csr, ep7_csr; +wire [31:0] ep8_csr, ep9_csr, ep10_csr, ep11_csr; +wire [31:0] ep12_csr, ep13_csr, ep14_csr, ep15_csr; + +wire [31:0] ep0_buf0, ep1_buf0, ep2_buf0, ep3_buf0; +wire [31:0] ep4_buf0, ep5_buf0, ep6_buf0, ep7_buf0; +wire [31:0] ep8_buf0, ep9_buf0, ep10_buf0, ep11_buf0; +wire [31:0] ep12_buf0, ep13_buf0, ep14_buf0, ep15_buf0; + +wire [31:0] ep0_buf1, ep1_buf1, ep2_buf1, ep3_buf1; +wire [31:0] ep4_buf1, ep5_buf1, ep6_buf1, ep7_buf1; +wire [31:0] ep8_buf1, ep9_buf1, ep10_buf1, ep11_buf1; +wire [31:0] ep12_buf1, ep13_buf1, ep14_buf1, ep15_buf1; + +wire ep0_dma_in_buf_sz1, ep1_dma_in_buf_sz1; +wire ep2_dma_in_buf_sz1, ep3_dma_in_buf_sz1; +wire ep4_dma_in_buf_sz1, ep5_dma_in_buf_sz1; +wire ep6_dma_in_buf_sz1, ep7_dma_in_buf_sz1; +wire ep8_dma_in_buf_sz1, ep9_dma_in_buf_sz1; +wire ep10_dma_in_buf_sz1, ep11_dma_in_buf_sz1; +wire ep12_dma_in_buf_sz1, ep13_dma_in_buf_sz1; +wire ep14_dma_in_buf_sz1, ep15_dma_in_buf_sz1; + +wire ep0_dma_out_buf_avail, ep1_dma_out_buf_avail; +wire ep2_dma_out_buf_avail, ep3_dma_out_buf_avail; +wire ep4_dma_out_buf_avail, ep5_dma_out_buf_avail; +wire ep6_dma_out_buf_avail, ep7_dma_out_buf_avail; +wire ep8_dma_out_buf_avail, ep9_dma_out_buf_avail; +wire ep10_dma_out_buf_avail, ep11_dma_out_buf_avail; +wire ep12_dma_out_buf_avail, ep13_dma_out_buf_avail; +wire ep14_dma_out_buf_avail, ep15_dma_out_buf_avail; + +reg dma_in_buf_sz1; +reg dma_out_buf_avail; + +reg [31:0] dtmp; +reg [31:0] dout; + +wire [31:0] main_csr; +reg [6:0] funct_adr; +reg [8:0] intb_msk, inta_msk; + +reg match_r1; +reg [31:0] csr; +reg [31:0] buf0; +reg [31:0] buf1; + +reg [3:0] utmi_vend_ctrl; +reg utmi_vend_wr; +reg [7:0] utmi_vend_stat_r; + +reg int_src_re; +reg [8:0] int_srcb; +reg [15:0] int_srca; +reg attach_r, attach_r1; +wire attach, deattach; +reg suspend_r, suspend_r1; +wire suspend_start, suspend_end; +reg usb_reset_r; +reg rx_err_r; +reg nse_err_r; +reg pid_cs_err_r; +reg crc5_err_r; + +reg rf_resume_req_r, rf_resume_req; + +wire inta_ep, intb_ep; +wire inta_rf, intb_rf; +reg inta, intb; + +/////////////////////////////////////////////////////////////////// +// +// WISHBONE Access +// + +// Main CSR Alias +assign main_csr = {27'h0, line_stat, usb_attached, mode_hs, suspend}; + +// Read Registers Logic +always @(adr or main_csr or funct_adr or inta_msk or intb_msk or int_srca + or int_srcb or frm_nat or utmi_vend_stat_r) + case(adr[2:0]) // synopsys full_case parallel_case + 3'h0: dtmp = main_csr; + 3'h1: dtmp = { 25'h0, funct_adr}; + 3'h2: dtmp = { 7'h0, intb_msk, 7'h0, inta_msk}; + 3'h3: dtmp = { 3'h0, int_srcb, 4'h0, int_srca}; + 3'h4: dtmp = frm_nat; + 3'h5: dtmp = { 24'h0, utmi_vend_stat_r}; + endcase + +// Interrupt Source Read Register +always @(posedge wclk) + int_src_re <= adr[6:0] == 7'h3 & re; + +// UTMI Vendor Control Stuff +always @(posedge wclk) + utmi_vend_stat_r <= utmi_vend_stat; + +reg utmi_vend_wr_r; +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) utmi_vend_wr_r <= 1'b0; + else + if(adr[6:0] == 7'h5 && we) utmi_vend_wr_r <= 1'b1; + else + if(utmi_vend_wr) utmi_vend_wr_r <= 1'b0; + +always @(posedge clk) // Second Stage sync + utmi_vend_wr <= utmi_vend_wr_r; + + +reg [3:0] utmi_vend_ctrl_r; +always @(posedge wclk) + if(adr[6:0] == 7'h5 && we) utmi_vend_ctrl_r <= din[3:0]; + +always @(posedge clk) // Second Stage sync + utmi_vend_ctrl <= utmi_vend_ctrl_r; + +// Resume Request +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) rf_resume_req_r <= 1'b0; + else + if(adr[6:0] == 7'h0 && we) rf_resume_req_r <= din[5]; + else + if(rf_resume_req) rf_resume_req_r <= 1'b0; + +always @(posedge clk) // Second Stage sync + rf_resume_req <= rf_resume_req_r; + +// Function Address Register +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) funct_adr <= 7'h0; + else + if(adr[6:0] == 7'h1 && we) funct_adr <= din[6:0]; + +// Interrup Mask Register +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) + begin + inta_msk <= 9'h0; + intb_msk <= 9'h0; + end + else + if(adr[6:0] == 7'h2 && we) + begin + intb_msk <= din[24:16]; + inta_msk <= din[08:00]; + end + +always @(posedge wclk) + case(adr[6:2]) // synopsys full_case parallel_case + 5'h00: dout <= dtmp; // Addr: 0h + 5'h01: dout <= dtmp; + 5'h02: dout <= 32'h0; + 5'h03: dout <= 32'h0; + 5'h04: dout <= ep0_dout; + 5'h05: dout <= ep1_dout; + 5'h06: dout <= ep2_dout; + 5'h07: dout <= ep3_dout; + 5'h08: dout <= ep4_dout; + 5'h09: dout <= ep5_dout; + 5'h0a: dout <= ep6_dout; + 5'h0b: dout <= ep7_dout; + 5'h0c: dout <= ep8_dout; + 5'h0d: dout <= ep9_dout; + 5'h0e: dout <= ep10_dout; + 5'h0f: dout <= ep11_dout; + 5'h10: dout <= ep12_dout; + 5'h11: dout <= ep13_dout; + 5'h12: dout <= ep14_dout; + 5'h13: dout <= ep15_dout; + endcase + +assign ep0_re = (adr[6:2] == 5'h04) & re; +assign ep1_re = (adr[6:2] == 5'h05) & re; +assign ep2_re = (adr[6:2] == 5'h06) & re; +assign ep3_re = (adr[6:2] == 5'h07) & re; +assign ep4_re = (adr[6:2] == 5'h08) & re; +assign ep5_re = (adr[6:2] == 5'h09) & re; +assign ep6_re = (adr[6:2] == 5'h0a) & re; +assign ep7_re = (adr[6:2] == 5'h0b) & re; +assign ep8_re = (adr[6:2] == 5'h0c) & re; +assign ep9_re = (adr[6:2] == 5'h0d) & re; +assign ep10_re = (adr[6:2] == 5'h0e) & re; +assign ep11_re = (adr[6:2] == 5'h0f) & re; +assign ep12_re = (adr[6:2] == 5'h10) & re; +assign ep13_re = (adr[6:2] == 5'h11) & re; +assign ep14_re = (adr[6:2] == 5'h12) & re; +assign ep15_re = (adr[6:2] == 5'h13) & re; + +assign ep0_we = (adr[6:2] == 5'h04) & we; +assign ep1_we = (adr[6:2] == 5'h05) & we; +assign ep2_we = (adr[6:2] == 5'h06) & we; +assign ep3_we = (adr[6:2] == 5'h07) & we; +assign ep4_we = (adr[6:2] == 5'h08) & we; +assign ep5_we = (adr[6:2] == 5'h09) & we; +assign ep6_we = (adr[6:2] == 5'h0a) & we; +assign ep7_we = (adr[6:2] == 5'h0b) & we; +assign ep8_we = (adr[6:2] == 5'h0c) & we; +assign ep9_we = (adr[6:2] == 5'h0d) & we; +assign ep10_we = (adr[6:2] == 5'h0e) & we; +assign ep11_we = (adr[6:2] == 5'h0f) & we; +assign ep12_we = (adr[6:2] == 5'h10) & we; +assign ep13_we = (adr[6:2] == 5'h11) & we; +assign ep14_we = (adr[6:2] == 5'h12) & we; +assign ep15_we = (adr[6:2] == 5'h13) & we; + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + +assign match = match_r1; + +always @(posedge clk) + match_r1 <= ep0_match | ep1_match | ep2_match | ep3_match | + ep4_match | ep5_match | ep6_match | ep7_match | + ep8_match | ep9_match | ep10_match | ep11_match | + ep12_match | ep13_match | ep14_match | ep15_match; + +always @(posedge clk) + if(ep0_match) csr <= ep0_csr; + else + if(ep1_match) csr <= ep1_csr; + else + if(ep2_match) csr <= ep2_csr; + else + if(ep3_match) csr <= ep3_csr; + else + if(ep4_match) csr <= ep4_csr; + else + if(ep5_match) csr <= ep5_csr; + else + if(ep6_match) csr <= ep6_csr; + else + if(ep7_match) csr <= ep7_csr; + else + if(ep8_match) csr <= ep8_csr; + else + if(ep9_match) csr <= ep9_csr; + else + if(ep10_match) csr <= ep10_csr; + else + if(ep11_match) csr <= ep11_csr; + else + if(ep12_match) csr <= ep12_csr; + else + if(ep13_match) csr <= ep13_csr; + else + if(ep14_match) csr <= ep14_csr; + else + if(ep15_match) csr <= ep15_csr; + +always @(posedge clk) + if(ep0_match) buf0 <= ep0_buf0; + else + if(ep1_match) buf0 <= ep1_buf0; + else + if(ep2_match) buf0 <= ep2_buf0; + else + if(ep3_match) buf0 <= ep3_buf0; + else + if(ep4_match) buf0 <= ep4_buf0; + else + if(ep5_match) buf0 <= ep5_buf0; + else + if(ep6_match) buf0 <= ep6_buf0; + else + if(ep7_match) buf0 <= ep7_buf0; + else + if(ep8_match) buf0 <= ep8_buf0; + else + if(ep9_match) buf0 <= ep9_buf0; + else + if(ep10_match) buf0 <= ep10_buf0; + else + if(ep11_match) buf0 <= ep11_buf0; + else + if(ep12_match) buf0 <= ep12_buf0; + else + if(ep13_match) buf0 <= ep13_buf0; + else + if(ep14_match) buf0 <= ep14_buf0; + else + if(ep15_match) buf0 <= ep15_buf0; + +always @(posedge clk) + if(ep0_match) buf1 <= ep0_buf1; + else + if(ep1_match) buf1 <= ep1_buf1; + else + if(ep2_match) buf1 <= ep2_buf1; + else + if(ep3_match) buf1 <= ep3_buf1; + else + if(ep4_match) buf1 <= ep4_buf1; + else + if(ep5_match) buf1 <= ep5_buf1; + else + if(ep6_match) buf1 <= ep6_buf1; + else + if(ep7_match) buf1 <= ep7_buf1; + else + if(ep8_match) buf1 <= ep8_buf1; + else + if(ep9_match) buf1 <= ep9_buf1; + else + if(ep10_match) buf1 <= ep10_buf1; + else + if(ep11_match) buf1 <= ep11_buf1; + else + if(ep12_match) buf1 <= ep12_buf1; + else + if(ep13_match) buf1 <= ep13_buf1; + else + if(ep14_match) buf1 <= ep14_buf1; + else + if(ep15_match) buf1 <= ep15_buf1; + +always @(posedge clk) + if(ep0_match) dma_in_buf_sz1 <= ep0_dma_in_buf_sz1; + else + if(ep1_match) dma_in_buf_sz1 <= ep1_dma_in_buf_sz1; + else + if(ep2_match) dma_in_buf_sz1 <= ep2_dma_in_buf_sz1; + else + if(ep3_match) dma_in_buf_sz1 <= ep3_dma_in_buf_sz1; + else + if(ep4_match) dma_in_buf_sz1 <= ep4_dma_in_buf_sz1; + else + if(ep5_match) dma_in_buf_sz1 <= ep5_dma_in_buf_sz1; + else + if(ep6_match) dma_in_buf_sz1 <= ep6_dma_in_buf_sz1; + else + if(ep7_match) dma_in_buf_sz1 <= ep7_dma_in_buf_sz1; + else + if(ep8_match) dma_in_buf_sz1 <= ep8_dma_in_buf_sz1; + else + if(ep9_match) dma_in_buf_sz1 <= ep9_dma_in_buf_sz1; + else + if(ep10_match) dma_in_buf_sz1 <= ep10_dma_in_buf_sz1; + else + if(ep11_match) dma_in_buf_sz1 <= ep11_dma_in_buf_sz1; + else + if(ep12_match) dma_in_buf_sz1 <= ep12_dma_in_buf_sz1; + else + if(ep13_match) dma_in_buf_sz1 <= ep13_dma_in_buf_sz1; + else + if(ep14_match) dma_in_buf_sz1 <= ep14_dma_in_buf_sz1; + else + if(ep15_match) dma_in_buf_sz1 <= ep15_dma_in_buf_sz1; + +always @(posedge clk) + if(ep0_match) dma_out_buf_avail <= ep0_dma_out_buf_avail; + else + if(ep1_match) dma_out_buf_avail <= ep1_dma_out_buf_avail; + else + if(ep2_match) dma_out_buf_avail <= ep2_dma_out_buf_avail; + else + if(ep3_match) dma_out_buf_avail <= ep3_dma_out_buf_avail; + else + if(ep4_match) dma_out_buf_avail <= ep4_dma_out_buf_avail; + else + if(ep5_match) dma_out_buf_avail <= ep5_dma_out_buf_avail; + else + if(ep6_match) dma_out_buf_avail <= ep6_dma_out_buf_avail; + else + if(ep7_match) dma_out_buf_avail <= ep7_dma_out_buf_avail; + else + if(ep8_match) dma_out_buf_avail <= ep8_dma_out_buf_avail; + else + if(ep9_match) dma_out_buf_avail <= ep9_dma_out_buf_avail; + else + if(ep10_match) dma_out_buf_avail <= ep10_dma_out_buf_avail; + else + if(ep11_match) dma_out_buf_avail <= ep11_dma_out_buf_avail; + else + if(ep12_match) dma_out_buf_avail <= ep12_dma_out_buf_avail; + else + if(ep13_match) dma_out_buf_avail <= ep13_dma_out_buf_avail; + else + if(ep14_match) dma_out_buf_avail <= ep14_dma_out_buf_avail; + else + if(ep15_match) dma_out_buf_avail <= ep15_dma_out_buf_avail; + + +/////////////////////////////////////////////////////////////////// +// +// Interrupt Generation +// + +always @(posedge wclk) + attach_r <= usb_attached; + +always @(posedge wclk) + attach_r1 <= attach_r; + +always @(posedge wclk) + suspend_r <= suspend; + +always @(posedge wclk) + suspend_r1 <= suspend_r; + +always @(posedge wclk) + usb_reset_r <= usb_reset; + +always @(posedge wclk) + rx_err_r <= rx_err; + +always @(posedge wclk) + nse_err_r <= nse_err; + +always @(posedge wclk) + pid_cs_err_r <= pid_cs_err; + +always @(posedge wclk) + crc5_err_r <= crc5_err; + +assign attach = !attach_r1 & attach_r; +assign deattach = attach_r1 & !attach_r; +assign suspend_start = !suspend_r1 & suspend_r; +assign suspend_end = suspend_r1 & !suspend_r; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[8] <= 1'b0; + else + if(int_src_re) int_srcb[8] <= 1'b0; + else + if(usb_reset_r) int_srcb[8] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[7] <= 1'b0; + else + if(int_src_re) int_srcb[7] <= 1'b0; + else + if(rx_err_r) int_srcb[7] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[6] <= 1'b0; + else + if(int_src_re) int_srcb[6] <= 1'b0; + else + if(deattach) int_srcb[6] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[5] <= 1'b0; + else + if(int_src_re) int_srcb[5] <= 1'b0; + else + if(attach) int_srcb[5] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[4] <= 1'b0; + else + if(int_src_re) int_srcb[4] <= 1'b0; + else + if(suspend_end) int_srcb[4] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[3] <= 1'b0; + else + if(int_src_re) int_srcb[3] <= 1'b0; + else + if(suspend_start) int_srcb[3] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[2] <= 1'b0; + else + if(int_src_re) int_srcb[2] <= 1'b0; + else + if(nse_err_r) int_srcb[2] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[1] <= 1'b0; + else + if(int_src_re) int_srcb[1] <= 1'b0; + else + if(pid_cs_err_r) int_srcb[1] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[0] <= 1'b0; + else + if(int_src_re) int_srcb[0] <= 1'b0; + else + if(crc5_err_r) int_srcb[0] <= 1'b1; + +always @(posedge wclk) + begin + int_srca[15] <= ep15_inta | ep15_intb; + int_srca[14] <= ep14_inta | ep14_intb; + int_srca[13] <= ep13_inta | ep13_intb; + int_srca[12] <= ep12_inta | ep12_intb; + int_srca[11] <= ep11_inta | ep11_intb; + int_srca[10] <= ep10_inta | ep10_intb; + int_srca[09] <= ep9_inta | ep9_intb; + int_srca[08] <= ep8_inta | ep8_intb; + int_srca[07] <= ep7_inta | ep7_intb; + int_srca[06] <= ep6_inta | ep6_intb; + int_srca[05] <= ep5_inta | ep5_intb; + int_srca[04] <= ep4_inta | ep4_intb; + int_srca[03] <= ep3_inta | ep3_intb; + int_srca[02] <= ep2_inta | ep2_intb; + int_srca[01] <= ep1_inta | ep1_intb; + int_srca[00] <= ep0_inta | ep0_intb; + end + +assign inta_ep =ep0_inta | ep1_inta | ep2_inta | ep3_inta | + ep4_inta | ep5_inta | ep6_inta | ep7_inta | + ep8_inta | ep9_inta | ep10_inta | ep11_inta | + ep12_inta | ep13_inta | ep14_inta | ep15_inta; + +assign intb_ep =ep0_intb | ep1_intb | ep2_intb | ep3_intb | + ep4_intb | ep5_intb | ep6_intb | ep7_intb | + ep8_intb | ep9_intb | ep10_intb | ep11_intb | + ep12_intb | ep13_intb | ep14_intb | ep15_intb; + +assign inta_rf = |(int_srcb & inta_msk); +assign intb_rf = |(int_srcb & intb_msk); + +always @(posedge wclk) + inta <= inta_ep | inta_rf; + +always @(posedge wclk) + intb <= intb_ep | intb_rf; + +/////////////////////////////////////////////////////////////////// +// +// Endpoint Register Files +// + +usbf_ep_rf u0( + .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep0_re ), + .we( ep0_we ), + .din( din ), + .dout( ep0_dout ), + .inta( ep0_inta ), + .intb( ep0_intb ), + .dma_req( dma_req[0] ), + .dma_ack( dma_ack[0] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep0_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep0_csr ), + .buf0( ep0_buf0 ), + .buf1( ep0_buf1 ), + .dma_in_buf_sz1( ep0_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep0_dma_out_buf_avail ) + ); + +`ifdef USBF_HAVE_EP1 +usbf_ep_rf u1( + .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep1_re ), + .we( ep1_we ), + .din( din ), + .dout( ep1_dout ), + .inta( ep1_inta ), + .intb( ep1_intb ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep1_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep1_csr ), + .buf0( ep1_buf0 ), + .buf1( ep1_buf1 ), + .dma_in_buf_sz1( ep1_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep1_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u1( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep1_re ), + .we( ep1_we ), + .din( din ), + .dout( ep1_dout ), + .inta( ep1_inta ), + .intb( ep1_intb ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep1_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep1_csr ), + .buf0( ep1_buf0 ), + .buf1( ep1_buf1 ), + .dma_in_buf_sz1( ep1_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep1_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP2 +usbf_ep_rf u2( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep2_re ), + .we( ep2_we ), + .din( din ), + .dout( ep2_dout ), + .inta( ep2_inta ), + .intb( ep2_intb ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep2_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep2_csr ), + .buf0( ep2_buf0 ), + .buf1( ep2_buf1 ), + .dma_in_buf_sz1( ep2_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep2_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u2( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep2_re ), + .we( ep2_we ), + .din( din ), + .dout( ep2_dout ), + .inta( ep2_inta ), + .intb( ep2_intb ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep2_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep2_csr ), + .buf0( ep2_buf0 ), + .buf1( ep2_buf1 ), + .dma_in_buf_sz1( ep2_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep2_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP3 +usbf_ep_rf u3( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep3_re ), + .we( ep3_we ), + .din( din ), + .dout( ep3_dout ), + .inta( ep3_inta ), + .intb( ep3_intb ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep3_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep3_csr ), + .buf0( ep3_buf0 ), + .buf1( ep3_buf1 ), + .dma_in_buf_sz1( ep3_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep3_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u3( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep3_re ), + .we( ep3_we ), + .din( din ), + .dout( ep3_dout ), + .inta( ep3_inta ), + .intb( ep3_intb ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep3_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep3_csr ), + .buf0( ep3_buf0 ), + .buf1( ep3_buf1 ), + .dma_in_buf_sz1( ep3_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep3_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP4 +usbf_ep_rf u4( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep4_re ), + .we( ep4_we ), + .din( din ), + .dout( ep4_dout ), + .inta( ep4_inta ), + .intb( ep4_intb ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep4_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep4_csr ), + .buf0( ep4_buf0 ), + .buf1( ep4_buf1 ), + .dma_in_buf_sz1( ep4_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep4_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u4( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep4_re ), + .we( ep4_we ), + .din( din ), + .dout( ep4_dout ), + .inta( ep4_inta ), + .intb( ep4_intb ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep4_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep4_csr ), + .buf0( ep4_buf0 ), + .buf1( ep4_buf1 ), + .dma_in_buf_sz1( ep4_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep4_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP5 +usbf_ep_rf u5( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep5_re ), + .we( ep5_we ), + .din( din ), + .dout( ep5_dout ), + .inta( ep5_inta ), + .intb( ep5_intb ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep5_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep5_csr ), + .buf0( ep5_buf0 ), + .buf1( ep5_buf1 ), + .dma_in_buf_sz1( ep5_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep5_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u5( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep5_re ), + .we( ep5_we ), + .din( din ), + .dout( ep5_dout ), + .inta( ep5_inta ), + .intb( ep5_intb ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep5_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep5_csr ), + .buf0( ep5_buf0 ), + .buf1( ep5_buf1 ), + .dma_in_buf_sz1( ep5_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep5_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP6 +usbf_ep_rf u6( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep6_re ), + .we( ep6_we ), + .din( din ), + .dout( ep6_dout ), + .inta( ep6_inta ), + .intb( ep6_intb ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep6_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep6_csr ), + .buf0( ep6_buf0 ), + .buf1( ep6_buf1 ), + .dma_in_buf_sz1( ep6_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep6_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u6( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep6_re ), + .we( ep6_we ), + .din( din ), + .dout( ep6_dout ), + .inta( ep6_inta ), + .intb( ep6_intb ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep6_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep6_csr ), + .buf0( ep6_buf0 ), + .buf1( ep6_buf1 ), + .dma_in_buf_sz1( ep6_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep6_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP7 +usbf_ep_rf u7( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep7_re ), + .we( ep7_we ), + .din( din ), + .dout( ep7_dout ), + .inta( ep7_inta ), + .intb( ep7_intb ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep7_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep7_csr ), + .buf0( ep7_buf0 ), + .buf1( ep7_buf1 ), + .dma_in_buf_sz1( ep7_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep7_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u7( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep7_re ), + .we( ep7_we ), + .din( din ), + .dout( ep7_dout ), + .inta( ep7_inta ), + .intb( ep7_intb ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep7_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep7_csr ), + .buf0( ep7_buf0 ), + .buf1( ep7_buf1 ), + .dma_in_buf_sz1( ep7_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep7_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP8 +usbf_ep_rf u8( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep8_re ), + .we( ep8_we ), + .din( din ), + .dout( ep8_dout ), + .inta( ep8_inta ), + .intb( ep8_intb ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep8_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep8_csr ), + .buf0( ep8_buf0 ), + .buf1( ep8_buf1 ), + .dma_in_buf_sz1( ep8_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep8_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u8( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep8_re ), + .we( ep8_we ), + .din( din ), + .dout( ep8_dout ), + .inta( ep8_inta ), + .intb( ep8_intb ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep8_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep8_csr ), + .buf0( ep8_buf0 ), + .buf1( ep8_buf1 ), + .dma_in_buf_sz1( ep8_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep8_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP9 +usbf_ep_rf u9( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep9_re ), + .we( ep9_we ), + .din( din ), + .dout( ep9_dout ), + .inta( ep9_inta ), + .intb( ep9_intb ), + .dma_req( dma_req[9] ), + .dma_ack( dma_ack[9] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep9_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep9_csr ), + .buf0( ep9_buf0 ), + .buf1( ep9_buf1 ), + .dma_in_buf_sz1( ep9_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep9_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u9( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep9_re ), + .we( ep9_we ), + .din( din ), + .dout( ep9_dout ), + .inta( ep9_inta ), + .intb( ep9_intb ), + .dma_req( dma_req[9] ), + .dma_ack( dma_ack[9] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep9_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep9_csr ), + .buf0( ep9_buf0 ), + .buf1( ep9_buf1 ), + .dma_in_buf_sz1( ep9_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep9_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP10 +usbf_ep_rf u10( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep10_re ), + .we( ep10_we ), + .din( din ), + .dout( ep10_dout ), + .inta( ep10_inta ), + .intb( ep10_intb ), + .dma_req( dma_req[10] ), + .dma_ack( dma_ack[10] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep10_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep10_csr ), + .buf0( ep10_buf0 ), + .buf1( ep10_buf1 ), + .dma_in_buf_sz1( ep10_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep10_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u10( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep10_re ), + .we( ep10_we ), + .din( din ), + .dout( ep10_dout ), + .inta( ep10_inta ), + .intb( ep10_intb ), + .dma_req( dma_req[10] ), + .dma_ack( dma_ack[10] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep10_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep10_csr ), + .buf0( ep10_buf0 ), + .buf1( ep10_buf1 ), + .dma_in_buf_sz1( ep10_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep10_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP11 +usbf_ep_rf u11( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep11_re ), + .we( ep11_we ), + .din( din ), + .dout( ep11_dout ), + .inta( ep11_inta ), + .intb( ep11_intb ), + .dma_req( dma_req[11] ), + .dma_ack( dma_ack[11] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep11_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep11_csr ), + .buf0( ep11_buf0 ), + .buf1( ep11_buf1 ), + .dma_in_buf_sz1( ep11_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep11_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u11( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep11_re ), + .we( ep11_we ), + .din( din ), + .dout( ep11_dout ), + .inta( ep11_inta ), + .intb( ep11_intb ), + .dma_req( dma_req[11] ), + .dma_ack( dma_ack[11] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep11_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep11_csr ), + .buf0( ep11_buf0 ), + .buf1( ep11_buf1 ), + .dma_in_buf_sz1( ep11_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep11_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP12 +usbf_ep_rf u12( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep12_re ), + .we( ep12_we ), + .din( din ), + .dout( ep12_dout ), + .inta( ep12_inta ), + .intb( ep12_intb ), + .dma_req( dma_req[12] ), + .dma_ack( dma_ack[12] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep12_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep12_csr ), + .buf0( ep12_buf0 ), + .buf1( ep12_buf1 ), + .dma_in_buf_sz1( ep12_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep12_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u12( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep12_re ), + .we( ep12_we ), + .din( din ), + .dout( ep12_dout ), + .inta( ep12_inta ), + .intb( ep12_intb ), + .dma_req( dma_req[12] ), + .dma_ack( dma_ack[12] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep12_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep12_csr ), + .buf0( ep12_buf0 ), + .buf1( ep12_buf1 ), + .dma_in_buf_sz1( ep12_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep12_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP13 +usbf_ep_rf u13( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep13_re ), + .we( ep13_we ), + .din( din ), + .dout( ep13_dout ), + .inta( ep13_inta ), + .intb( ep13_intb ), + .dma_req( dma_req[13] ), + .dma_ack( dma_ack[13] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep13_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep13_csr ), + .buf0( ep13_buf0 ), + .buf1( ep13_buf1 ), + .dma_in_buf_sz1( ep13_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep13_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u13( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep13_re ), + .we( ep13_we ), + .din( din ), + .dout( ep13_dout ), + .inta( ep13_inta ), + .intb( ep13_intb ), + .dma_req( dma_req[13] ), + .dma_ack( dma_ack[13] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep13_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep13_csr ), + .buf0( ep13_buf0 ), + .buf1( ep13_buf1 ), + .dma_in_buf_sz1( ep13_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep13_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP14 +usbf_ep_rf u14( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep14_re ), + .we( ep14_we ), + .din( din ), + .dout( ep14_dout ), + .inta( ep14_inta ), + .intb( ep14_intb ), + .dma_req( dma_req[14] ), + .dma_ack( dma_ack[14] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep14_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep14_csr ), + .buf0( ep14_buf0 ), + .buf1( ep14_buf1 ), + .dma_in_buf_sz1( ep14_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep14_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u14( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep14_re ), + .we( ep14_we ), + .din( din ), + .dout( ep14_dout ), + .inta( ep14_inta ), + .intb( ep14_intb ), + .dma_req( dma_req[14] ), + .dma_ack( dma_ack[14] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep14_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep14_csr ), + .buf0( ep14_buf0 ), + .buf1( ep14_buf1 ), + .dma_in_buf_sz1( ep14_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep14_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP15 +usbf_ep_rf u15( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep15_re ), + .we( ep15_we ), + .din( din ), + .dout( ep15_dout ), + .inta( ep15_inta ), + .intb( ep15_intb ), + .dma_req( dma_req[15] ), + .dma_ack( dma_ack[15] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep15_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep15_csr ), + .buf0( ep15_buf0 ), + .buf1( ep15_buf1 ), + .dma_in_buf_sz1( ep15_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep15_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u15( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep15_re ), + .we( ep15_we ), + .din( din ), + .dout( ep15_dout ), + .inta( ep15_inta ), + .intb( ep15_intb ), + .dma_req( dma_req[15] ), + .dma_ack( dma_ack[15] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep15_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep15_csr ), + .buf0( ep15_buf0 ), + .buf1( ep15_buf1 ), + .dma_in_buf_sz1( ep15_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep15_dma_out_buf_avail ) + ); +`endif + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_top.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_top.v new file mode 100644 index 000000000..029f9e145 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_top.v @@ -0,0 +1,622 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB function core //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_top.v,v 1.7 2003/11/11 07:15:16 rudi Exp $ +// +// $Date: 2003/11/11 07:15:16 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_top.v,v $ +// Revision 1.7 2003/11/11 07:15:16 rudi +// Fixed Resume signaling and initial attachment +// +// Revision 1.6 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/11/03 03:26:23 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:40 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_top(// WISHBONE Interface + clk_i, rst_i, wb_addr_i, wb_data_i, wb_data_o, + wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, inta_o, intb_o, + dma_req_o, dma_ack_i, susp_o, resume_req_i, + + // UTMI Interface + phy_clk_pad_i, phy_rst_pad_o, + DataOut_pad_o, TxValid_pad_o, TxReady_pad_i, + + RxValid_pad_i, RxActive_pad_i, RxError_pad_i, + DataIn_pad_i, XcvSelect_pad_o, TermSel_pad_o, + SuspendM_pad_o, LineState_pad_i, + + OpMode_pad_o, usb_vbus_pad_i, + VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i, + + // Buffer Memory Interface + sram_adr_o, sram_data_i, sram_data_o, sram_re_o, sram_we_o + + ); + +parameter SSRAM_HADR = `USBF_SSRAM_HADR; +input clk_i; +input rst_i; +input [`USBF_UFC_HADR:0] wb_addr_i; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output wb_ack_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +output inta_o; +output intb_o; +output [15:0] dma_req_o; +input [15:0] dma_ack_i; +output susp_o; +input resume_req_i; + +input phy_clk_pad_i; +output phy_rst_pad_o; + +output [7:0] DataOut_pad_o; +output TxValid_pad_o; +input TxReady_pad_i; + +input [7:0] DataIn_pad_i; +input RxValid_pad_i; +input RxActive_pad_i; +input RxError_pad_i; + +output XcvSelect_pad_o; +output TermSel_pad_o; +output SuspendM_pad_o; +input [1:0] LineState_pad_i; +output [1:0] OpMode_pad_o; +input usb_vbus_pad_i; +output VControl_Load_pad_o; +output [3:0] VControl_pad_o; +input [7:0] VStatus_pad_i; + +output [SSRAM_HADR:0] sram_adr_o; +input [31:0] sram_data_i; +output [31:0] sram_data_o; +output sram_re_o; +output sram_we_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// UTMI Interface +wire [7:0] rx_data; +wire rx_valid, rx_active, rx_err; +wire [7:0] tx_data; +wire tx_valid; +wire tx_ready; +wire tx_first; +wire tx_valid_last; + +// Misc UTMI USB status +wire mode_hs; // High Speed Mode +wire usb_reset; // USB Reset +wire usb_suspend; // USB Sleep +wire usb_attached; // Attached to USB +wire resume_req; // Resume Request + +// Memory Arbiter Interface +wire [SSRAM_HADR:0] madr; // word address +wire [31:0] mdout; +wire [31:0] mdin; +wire mwe; +wire mreq; +wire mack; +wire rst; + +// Wishbone Memory interface +wire [`USBF_UFC_HADR:0] ma_adr; +wire [31:0] ma2wb_d; +wire [31:0] wb2ma_d; +wire ma_we; +wire ma_req; +wire ma_ack; + +// WISHBONE Register File interface +wire rf_re; +wire rf_we; +wire [31:0] wb2rf_d; +wire [31:0] rf2wb_d; + +// Internal Register File Interface +wire [6:0] funct_adr; // This functions address (set by controller) +wire [31:0] idin; // Data Input +wire [3:0] ep_sel; // Endpoint Number Input +wire match; // Endpoint Matched +wire dma_in_buf_sz1; +wire dma_out_buf_avail; +wire buf0_rl; // Reload Buf 0 with original values +wire buf0_set; // Write to buf 0 +wire buf1_set; // Write to buf 1 +wire uc_bsel_set; // Write to the uc_bsel field +wire uc_dpd_set; // Write to the uc_dpd field +wire int_buf1_set; // Set buf1 full/empty interrupt +wire int_buf0_set; // Set buf0 full/empty interrupt +wire int_upid_set; // Set unsupported PID interrupt +wire int_crc16_set; // Set CRC16 error interrupt +wire int_to_set; // Set time out interrupt +wire int_seqerr_set; // Set PID sequence error interrupt +wire out_to_small; // OUT packet was to small for DMA operation +wire [31:0] csr; // Internal CSR Output +wire [31:0] buf0; // Internal Buf 0 Output +wire [31:0] buf1; // Internal Buf 1 Output +wire [31:0] frm_nat; // Frame Number and Time Register +wire nse_err; // No Such Endpoint Error +wire pid_cs_err; // PID CS error +wire crc5_err; // CRC5 Error +wire rf_resume_req; // Resume Request From main CSR + +reg susp_o; +reg [1:0] LineState_r; // Added to make a full synchronizer +reg [7:0] VStatus_r; // Added to make a full synchronizer + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// +assign rst = rst_i; +assign phy_rst_pad_o = rst_i; +assign resume_req = resume_req_i; + +always @(posedge clk_i) + susp_o <= usb_suspend; + +always @(posedge phy_clk_pad_i) // First Stage Synchronizer + LineState_r <= LineState_pad_i; + +always @(posedge phy_clk_pad_i) // First Stage Synchronizer + VStatus_r <= VStatus_pad_i; + +/////////////////////////////////////////////////////////////////// +// +// Module Instantiations +// + +reg resume_req_r; +reg suspend_clr_wr; +wire suspend_clr; + +always @(posedge clk_i) + suspend_clr_wr <= suspend_clr; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk_i or negedge rst) +`else +always @(posedge clk_i) +`endif + if(!rst) resume_req_r <= 1'b0; + else + if(suspend_clr_wr) resume_req_r <= 1'b0; + else + if(resume_req) resume_req_r <= 1'b1; + + +// UTMI Interface +usbf_utmi_if u0( + .phy_clk( phy_clk_pad_i ), + .rst( rst ), + .DataOut( DataOut_pad_o ), + .TxValid( TxValid_pad_o ), + .TxReady( TxReady_pad_i ), + .RxValid( RxValid_pad_i ), + .RxActive( RxActive_pad_i ), + .RxError( RxError_pad_i ), + .DataIn( DataIn_pad_i ), + .XcvSelect( XcvSelect_pad_o ), + .TermSel( TermSel_pad_o ), + .SuspendM( SuspendM_pad_o ), + .LineState( LineState_pad_i ), + .OpMode( OpMode_pad_o ), + .usb_vbus( usb_vbus_pad_i ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .mode_hs( mode_hs ), + .usb_reset( usb_reset ), + .usb_suspend( usb_suspend ), + .usb_attached( usb_attached ), + .resume_req( resume_req_r ), + .suspend_clr( suspend_clr ) + ); + +// Protocol Layer +usbf_pl #(SSRAM_HADR) + u1( .clk( phy_clk_pad_i ), + .rst( rst ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .tx_valid_out( TxValid_pad_o ), + .mode_hs( mode_hs ), + .usb_reset( usb_reset ), + .usb_suspend( usb_suspend ), + .usb_attached( usb_attached ), + .madr( madr ), + .mdout( mdout ), + .mdin( mdin ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ), + .fa( funct_adr ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ), + .frm_nat( frm_nat ), + .pid_cs_err( pid_cs_err ), + .nse_err( nse_err ), + .crc5_err( crc5_err ) + ); + +// Memory Arbiter +usbf_mem_arb #(SSRAM_HADR) + u2( .phy_clk( phy_clk_pad_i ), + .wclk( clk_i ), + .rst( rst ), + + .sram_adr( sram_adr_o ), + .sram_din( sram_data_i ), + .sram_dout( sram_data_o ), + .sram_re( sram_re_o ), + .sram_we( sram_we_o ), + + .madr( madr ), + .mdout( mdin ), + .mdin( mdout ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ), + + .wadr( ma_adr[SSRAM_HADR + 2:2] ), + .wdout( ma2wb_d ), + .wdin( wb2ma_d ), + .wwe( ma_we ), + .wreq( ma_req ), + .wack( ma_ack ) + ); + +// Register File +usbf_rf u4( .clk( phy_clk_pad_i ), + .wclk( clk_i ), + .rst( rst ), + + .adr( ma_adr[8:2] ), + .re( rf_re ), + .we( rf_we ), + .din( wb2rf_d ), + .dout( rf2wb_d ), + + .inta( inta_o ), + .intb( intb_o ), + .dma_req( dma_req_o ), + .dma_ack( dma_ack_i ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ), + .funct_adr( funct_adr ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .frm_nat( frm_nat ), + .utmi_vend_stat( VStatus_r ), + .utmi_vend_ctrl( VControl_pad_o ), + .utmi_vend_wr( VControl_Load_pad_o ), + .line_stat( LineState_r ), + .usb_attached( usb_attached ), + .mode_hs( mode_hs ), + .suspend( usb_suspend ), + .attached( usb_attached ), + .usb_reset( usb_reset ), + .pid_cs_err( pid_cs_err ), + .nse_err( nse_err ), + .crc5_err( crc5_err ), + .rx_err( rx_err ), + .rf_resume_req( rf_resume_req ) + ); + + +// WISHBONE Interface +usbf_wb u5( .phy_clk( phy_clk_pad_i ), + .wb_clk( clk_i ), + .rst( rst ), + .wb_addr_i( wb_addr_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( wb_data_o ), + .wb_ack_o( wb_ack_o ), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + + .ma_adr( ma_adr ), + .ma_dout( wb2ma_d ), + .ma_din( ma2wb_d ), + .ma_we( ma_we ), + .ma_req( ma_req ), + .ma_ack( ma_ack ), + + .rf_re( rf_re ), + .rf_we( rf_we ), + .rf_dout( wb2rf_d ), + .rf_din( rf2wb_d ) + ); + + +/////////////////////////////////////////////////////////////////// +// +// Initialization +// This section does not add any functionality. It is only provided +// to make sure that the core is configured properly and to provide +// configuration information for simulations. +// + +// synopsys translate_off +integer ep_cnt, ep_cnt2; +reg [15:0] ep_check; +initial + begin + $display("\n"); + ep_cnt = 1; + ep_cnt2 = 0; + ep_check = 0; + +`ifdef USBF_HAVE_EP1 + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP2 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP3 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP4 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP5 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP6 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP7 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP8 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP9 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP10 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP11 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP12 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP13 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP14 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP15 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif + + $display(""); + $display("INFO: USB Function core instantiated (%m)"); + $display(" Supported Endpoints: %0d (0 through %0d)",ep_cnt, ep_cnt-1); + $display(" WISHBONE Address bus size: A%0d:0", `USBF_UFC_HADR ); + $display(" SSRAM Address bus size: A%0d:0", SSRAM_HADR ); + $display(" Buffer Memory Size: %0d bytes", (1< `USBF_T1_C_2_5_US); + +always @(posedge clk) // Smaller Than 3 mS (Actual Time will be 0-2.9375mS) + T1_st_3_0_mS <= !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS); + +always @(posedge clk) // Greater Than 3 mS (Actual Time will be T0+3.0625mS) + T1_gt_3_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS); + +always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS) + T1_gt_3_125_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS); + +always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS) + T1_gt_5_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS); + +// --------------------------------------------------------- +// Misc Events Counter + +// Pre-scaler - 2.5uS +always @(posedge clk) + if(me_cnt_clr || me_ps_2_5_us) me_ps <= 8'h0; + else me_ps <= me_ps + 8'h1; + +always @(posedge clk) // Generate a pulse every 2.5 uS + me_ps_2_5_us <= (me_ps == `USBF_T2_C_2_5_US); + +// Second Pre-scaler - 0.5mS +always @(posedge clk) + if(me_cnt_clr || me_ps2_0_5_ms ) me_ps2 <= 8'h0; + else + if(me_ps_2_5_us) me_ps2 <= me_ps2 + 8'h1; + +always @(posedge clk) // Generate a pulse every 0.5 mS + me_ps2_0_5_ms <= (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms; + +// final misc Counter +always @(posedge clk) + if(me_cnt_clr) me_cnt <= 8'h0; + else + if(!me_cnt_100_ms && me_ps2_0_5_ms) me_cnt <= me_cnt + 8'h1; + +always @(posedge clk) // Indicate when 100uS have passed + T2_gt_100_uS <= !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS + +always @(posedge clk) // Indicate when wakeup period has passed + T2_wakeup <= !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP); + +always @(posedge clk) // Indicate when 1 mS has passed + T2_gt_1_0_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS + +always @(posedge clk) // Indicate when 1.2 mS has passed + T2_gt_1_2_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS + +always @(posedge clk) // Generate a pulse after 100 mS + me_cnt_100_ms <= !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS + +// --------------------------------------------------------- +// Chirp Counter + +always @(posedge clk) + if(chirp_cnt_clr) chirp_cnt <= 3'h0; + else + if(chirp_cnt_inc) chirp_cnt <= chirp_cnt + 3'h1; + +always @(posedge clk) + chirp_cnt_is_6 <= (chirp_cnt == 3'h6); + +/////////////////////////////////////////////////////////////////// +// +// Main State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= POR; + else + if(usb_vbus) state <= POR; + else state <= next_state; + +always @(state or mode_hs or idle_long or resume_req_s or me_cnt_100_ms or + j_long or k_long or se0_long or ls_se0 or + T1_gt_2_5_uS or T1_st_3_0_mS or T1_gt_3_0_mS or + T1_gt_5_0_mS or T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or + T2_gt_1_2_mS or chirp_cnt_is_6) + begin + next_state = state; // Default don't change state + + mode_set_hs = 1'b0; + mode_set_fs = 1'b0; + suspend_set = 1'b0; + suspend_clr = 1'b0; + attached_set = 1'b0; + attached_clr = 1'b0; + usb_reset_d = 1'b0; + + fs_term_on = 1'b0; + fs_term_off = 1'b0; + xcv_set_hs = 1'b0; + xcv_set_fs = 1'b0; + bit_stuff_on = 1'b0; + bit_stuff_off = 1'b0; + + idle_cnt_clr = 1'b0; + me_cnt_clr = 1'b0; + drive_k_d = 1'b0; + chirp_cnt_clr = 1'b0; + chirp_cnt_inc = 1'b0; + + case(state) // synopsys full_case parallel_case + POR: // Power On/Reset + begin + me_cnt_clr = 1'b1; + xcv_set_fs = 1'b1; + fs_term_on = 1'b1; + mode_set_fs = 1'b1; + attached_clr = 1'b1; + bit_stuff_on = 1'b0; + suspend_clr = 1'b1; + next_state = ATTACH; + end + + NORMAL: // Normal Operation + begin + if(!mode_hs && T1_gt_2_5_uS && T1_st_3_0_mS && !idle_long) + begin + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(!mode_hs && T1_gt_3_0_mS) + begin + idle_cnt_clr = 1'b1; + suspend_set = 1'b1; + next_state = SUSPEND; + end + else + if(mode_hs && T1_gt_3_0_mS) + begin // Switch to FS mode, and decide + // if it's a RESET or SUSPEND + me_cnt_clr = 1'b1; + xcv_set_fs = 1'b1; + fs_term_on = 1'b1; + next_state = RES_SUSP; + end + end + + RES_SUSP: // Decide if it's a Reset or Suspend Signaling + begin // We are now in FS mode, wait 100uS first + if(T2_gt_100_uS && se0_long) + begin + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(T2_gt_100_uS && j_long) + begin + idle_cnt_clr = 1'b1; + suspend_set = 1'b1; + next_state = SUSPEND; + end + end + + SUSPEND: // In Suspend + begin + if(T1_gt_2_5_uS && se0_long) + begin + suspend_clr = 1'b1; + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(k_long) // Start Resuming + next_state = RESUME; + else + if(T1_gt_5_0_mS && resume_req_s) + next_state = RESUME_REQUEST; + end + + RESUME: + begin + suspend_clr = 1'b1; + if(ls_se0) + begin + if(mode_hs) + begin // Switch Back to HS mode + xcv_set_hs = 1'b1; + fs_term_off = 1'b1; + end + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + me_cnt_clr = 1'b1; + next_state = RESUME_WAIT; + end + end + + RESUME_WAIT: + begin + if(T2_gt_100_uS) next_state = NORMAL; + end + + RESUME_REQUEST: // Function Resume Request + begin + suspend_clr = 1'b1; + // Wait for internal wake up + if(T2_wakeup) + begin + fs_term_on = 1'b1; // Switch Termination to Full Speed + bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding + me_cnt_clr = 1'b1; + next_state = RESUME_SIG; + end + end + + RESUME_SIG: // Signal resume + begin + // Drive Resume ('K') for 1-15 mS + drive_k_d = 1'b1; + // Stop driving after 1.5 mS + if(T2_gt_1_0_mS) next_state = RESUME; + end + + ATTACH: // Attach To USB Detected + begin + idle_cnt_clr = 1'b1; + if(me_cnt_100_ms) + //if(me_cnt_100_ms && j_long) + begin + attached_set = 1'b1; + next_state = NORMAL; + end + /* + if(me_cnt_100_ms && se0_long) + begin + attached_set = 1'b1; + me_cnt_clr = 1'b1; + next_state = RESET; + end + */ + end + + RESET: // In Reset + begin + usb_reset_d = 1'b1; // Assert Internal USB Reset + xcv_set_hs = 1'b1; // Switch xcvr to HS mode + fs_term_on = 1'b1; // Turn FS termination On + mode_set_fs = 1'b1; // Change mode to FS + bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding + // Get out of reset after 1.5 mS + if(T2_gt_1_0_mS) + begin + me_cnt_clr = 1'b1; + next_state = SPEED_NEG; + end + end + + SPEED_NEG: // Speed Negotiation + begin + drive_k_d = 1'b1; + chirp_cnt_clr = 1'b1; + // Start looking for 'K' after 1.5 mS + if(T2_gt_1_2_mS) next_state = SPEED_NEG_K; + end + + SPEED_NEG_K: + begin + if(chirp_cnt_is_6) next_state = SPEED_NEG_HS; + else + begin + if(k_long) + begin + chirp_cnt_inc = 1'b1; + next_state = SPEED_NEG_J; + end + if(se0_long) + next_state = SPEED_NEG_FS; + end + end + + SPEED_NEG_J: + begin + if(chirp_cnt_is_6) next_state = SPEED_NEG_HS; + else + begin + if(j_long) + begin + chirp_cnt_inc = 1'b1; + next_state = SPEED_NEG_K; + end + if(se0_long) + next_state = SPEED_NEG_FS; + end + end + + SPEED_NEG_HS: + begin + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + xcv_set_hs = 1'b1; // Switch xcvr to HS mode + fs_term_off = 1'b1; // Turn FS termination Off + mode_set_hs = 1'b1; // Change mode to HS + if(se0_long) next_state = NORMAL; + end + + SPEED_NEG_FS: + begin + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + xcv_set_fs = 1'b1; // Switch xcvr to FS mode + fs_term_on = 1'b1; // Turn FS termination On + mode_set_fs = 1'b1; // Change mode to FS + next_state = NORMAL; + end + + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_wb.v b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_wb.v new file mode 100644 index 000000000..30428d476 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/usbf_wb.v @@ -0,0 +1,282 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Interface //// +//// This is the external bus interface, that is WISHBONE //// +//// SoC compliant. //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_wb.v,v 1.4 2003/10/17 02:36:57 rudi Exp $ +// +// $Date: 2003/10/17 02:36:57 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usbf_wb.v,v $ +// Revision 1.4 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:11:47 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_wb( // WISHBONE Interface + wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o, + wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, + + // Memory Arbiter Interface + ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack, + + // Register File interface + rf_re, rf_we, rf_din, rf_dout); + +input wb_clk, phy_clk; +input rst; +input [`USBF_UFC_HADR:0] wb_addr_i; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output wb_ack_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; + +// Memory Arbiter Interface +output [`USBF_UFC_HADR:0] ma_adr; +output [31:0] ma_dout; +input [31:0] ma_din; +output ma_we; +output ma_req; +input ma_ack; + +// Register File interface +output rf_re; +output rf_we; +input [31:0] rf_din; +output [31:0] rf_dout; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [5:0] // synopsys enum state + IDLE = 6'b00_0001, + MA_WR = 6'b00_0010, + MA_RD = 6'b00_0100, + W0 = 6'b00_1000, + W1 = 6'b01_0000, + W2 = 6'b10_0000; + +reg [5:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg wb_req_s1; +reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2; +reg ma_we; +reg rf_re, rf_we_d; +reg ma_req; +reg wb_ack_o; +reg [31:0] wb_data_o; + +/////////////////////////////////////////////////////////////////// +// +// Interface Logic +// + +assign ma_adr = wb_addr_i; +assign ma_dout = wb_data_i; +assign rf_dout = wb_data_i; + +always @(posedge wb_clk) + if( `USBF_RF_SEL ) wb_data_o <= rf_din; + else wb_data_o <= ma_din; + +// Sync WISHBONE Request +always @(posedge phy_clk) + wb_req_s1 <= wb_stb_i & wb_cyc_i; + +// Sync WISHBONE Ack +always @(posedge wb_clk) + wb_ack_s1 <= wb_ack_d; + +always @(posedge wb_clk) + wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o; + +always @(posedge wb_clk) + wb_ack_s1a <= wb_ack_s1; + +always @(posedge wb_clk) + wb_ack_s2 <= wb_ack_s1a; + +assign rf_we = rf_we_d; + +/////////////////////////////////////////////////////////////////// +// +// Interface State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge phy_clk or negedge rst) +`else +always @(posedge phy_clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i) + begin + next_state = state; + ma_req = 1'b0; + ma_we = 1'b0; + wb_ack_d = 1'b0; + rf_re = 1'b0; + rf_we_d = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin + if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i) + begin + ma_req = 1'b1; + ma_we = 1'b1; + next_state = MA_WR; + end + if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i) + begin + ma_req = 1'b1; + next_state = MA_RD; + end + if(wb_req_s1 && `USBF_RF_SEL && wb_we_i) + begin + rf_we_d = 1'b1; + next_state = W0; + end + if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i) + begin + rf_re = 1'b1; + next_state = W0; + end + end + + MA_WR: + begin + if(!ma_ack) + begin + ma_req = 1'b1; + ma_we = 1'b1; + end + else + begin + wb_ack_d = 1'b1; + next_state = W1; + end + end + + MA_RD: + begin + if(!ma_ack) + begin + ma_req = 1'b1; + end + else + begin + wb_ack_d = 1'b1; + next_state = W1; + end + end + + W0: + begin + wb_ack_d = 1'b1; + next_state = W1; + end + + W1: + begin + next_state = W2; + end + + W2: + begin + next_state = IDLE; + end + + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/timescale.v b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/timescale.v new file mode 100644 index 000000000..ff9e265a8 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps diff --git a/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_phy.v b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_phy.v new file mode 100644 index 000000000..4ee345add --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_phy.v @@ -0,0 +1,184 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_phy.v,v 1.4 2003/10/21 05:58:40 rudi Exp $ +// +// $Date: 2003/10/21 05:58:40 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usb_phy.v,v $ +// Revision 1.4 2003/10/21 05:58:40 rudi +// usb_rst is no longer or'ed with the incomming reset internally. +// Now usb_rst is simply an output, the application can decide how +// to utilize it. +// +// Revision 1.3 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.2 2002/09/16 16:06:37 rudi +// Changed top level name to be consistent ... +// +// Revision 1.1.1.1 2002/09/16 14:26:59 rudi +// Created Directory Structure +// +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_phy(clk, rst, phy_tx_mode, usb_rst, + + // Transciever Interface + txdp, txdn, txoe, + rxd, rxdp, rxdn, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o, RxValid_o, + RxActive_o, RxError_o, DataIn_o, LineState_o + ); + +input clk; +input rst; +input phy_tx_mode; +output usb_rst; +output txdp, txdn, txoe; +input rxd, rxdp, rxdn; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +output [1:0] LineState_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [4:0] rst_cnt; +reg usb_rst; +wire fs_ce; +wire rst; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +/////////////////////////////////////////////////////////////////// +// +// TX Phy +// + +usb_tx_phy i_tx_phy( + .clk( clk ), + .rst( rst ), + .fs_ce( fs_ce ), + .phy_mode( phy_tx_mode ), + + // Transciever Interface + .txdp( txdp ), + .txdn( txdn ), + .txoe( txoe ), + + // UTMI Interface + .DataOut_i( DataOut_i ), + .TxValid_i( TxValid_i ), + .TxReady_o( TxReady_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// RX Phy and DPLL +// + +usb_rx_phy i_rx_phy( + .clk( clk ), + .rst( rst ), + .fs_ce( fs_ce ), + + // Transciever Interface + .rxd( rxd ), + .rxdp( rxdp ), + .rxdn( rxdn ), + + // UTMI Interface + .DataIn_o( DataIn_o ), + .RxValid_o( RxValid_o ), + .RxActive_o( RxActive_o ), + .RxError_o( RxError_o ), + .RxEn_i( txoe ), + .LineState( LineState_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// Generate an USB Reset is we see SE0 for at least 2.5uS +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rst_cnt <= 5'h0; + else + if(LineState_o != 2'h0) rst_cnt <= 5'h0; + else + if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1; + +always @(posedge clk) + usb_rst <= (rst_cnt == 5'h1f); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_rx_phy.v b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_rx_phy.v new file mode 100644 index 000000000..c0568fb7d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_rx_phy.v @@ -0,0 +1,452 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// RX & DPLL //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_rx_phy.v,v 1.5 2004/10/19 09:29:07 rudi Exp $ +// +// $Date: 2004/10/19 09:29:07 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usb_rx_phy.v,v $ +// Revision 1.5 2004/10/19 09:29:07 rudi +// Fixed DPLL alignment in the rx_phy and bit stuffing errors in the tx_phy (if last bit bit was a stuff bit in a packet it was omitted). +// +// Revision 1.4 2003/12/02 04:56:00 rudi +// Fixed a bug reported by Karl C. Posch from Graz University of Technology. Thanks Karl ! +// +// Revision 1.3 2003/10/19 18:07:45 rudi +// - Fixed Sync Error to be only checked/generated during the sync phase +// +// Revision 1.2 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.1.1.1 2002/09/16 14:27:01 rudi +// Created Directory Structure +// +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_rx_phy( clk, rst, fs_ce, + + // Transciever Interface + rxd, rxdp, rxdn, + + // UTMI Interface + RxValid_o, RxActive_o, RxError_o, DataIn_o, + RxEn_i, LineState); + +input clk; +input rst; +output fs_ce; +input rxd, rxdp, rxdn; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +input RxEn_i; +output [1:0] LineState; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg rxd_s0, rxd_s1, rxd_s; +reg rxdp_s0, rxdp_s1, rxdp_s, rxdp_s_r; +reg rxdn_s0, rxdn_s1, rxdn_s, rxdn_s_r; +reg synced_d; +wire k, j, se0; +reg rxd_r; +reg rx_en; +reg rx_active; +reg [2:0] bit_cnt; +reg rx_valid1, rx_valid; +reg shift_en; +reg sd_r; +reg sd_nrzi; +reg [7:0] hold_reg; +wire drop_bit; // Indicates a stuffed bit +reg [2:0] one_cnt; + +reg [1:0] dpll_state, dpll_next_state; +reg fs_ce_d; +reg fs_ce; +wire change; +wire lock_en; +reg [2:0] fs_state, fs_next_state; +reg rx_valid_r; +reg sync_err_d, sync_err; +reg bit_stuff_err; +reg se0_r, byte_err; +reg se0_s; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign RxActive_o = rx_active; +assign RxValid_o = rx_valid; +assign RxError_o = sync_err | bit_stuff_err | byte_err; +assign DataIn_o = hold_reg; +assign LineState = {rxdn_s1, rxdp_s1}; + +always @(posedge clk) rx_en <= RxEn_i; +always @(posedge clk) sync_err <= !rx_active & sync_err_d; + +/////////////////////////////////////////////////////////////////// +// +// Synchronize Inputs +// + +// First synchronize to the local system clock to +// avoid metastability outside the sync block (*_s0). +// Then make sure we see the signal for at least two +// clock cycles stable to avoid glitches and noise + +always @(posedge clk) rxd_s0 <= rxd; +always @(posedge clk) rxd_s1 <= rxd_s0; +always @(posedge clk) // Avoid detecting Line Glitches and noise + if(rxd_s0 && rxd_s1) rxd_s <= 1'b1; + else + if(!rxd_s0 && !rxd_s1) rxd_s <= 1'b0; + +always @(posedge clk) rxdp_s0 <= rxdp; +always @(posedge clk) rxdp_s1 <= rxdp_s0; +always @(posedge clk) rxdp_s_r <= rxdp_s0 & rxdp_s1; +always @(posedge clk) rxdp_s <= (rxdp_s0 & rxdp_s1) | rxdp_s_r; // Avoid detecting Line Glitches and noise + +always @(posedge clk) rxdn_s0 <= rxdn; +always @(posedge clk) rxdn_s1 <= rxdn_s0; +always @(posedge clk) rxdn_s_r <= rxdn_s0 & rxdn_s1; +always @(posedge clk) rxdn_s <= (rxdn_s0 & rxdn_s1) | rxdn_s_r; // Avoid detecting Line Glitches and noise + +assign k = !rxdp_s & rxdn_s; +assign j = rxdp_s & !rxdn_s; +assign se0 = !rxdp_s & !rxdn_s; + +always @(posedge clk) if(fs_ce) se0_s <= se0; + +/////////////////////////////////////////////////////////////////// +// +// DPLL +// + +// This design uses a clock enable to do 12Mhz timing and not a +// real 12Mhz clock. Everything always runs at 48Mhz. We want to +// make sure however, that the clock enable is always exactly in +// the middle between two virtual 12Mhz rising edges. +// We monitor rxdp and rxdn for any changes and do the appropiate +// adjustments. +// In addition to the locking done in the dpll FSM, we adjust the +// final latch enable to compensate for various sync registers ... + +// Allow lockinf only when we are receiving +assign lock_en = rx_en; + +always @(posedge clk) rxd_r <= rxd_s; + +// Edge detector +assign change = rxd_r != rxd_s; + +// DPLL FSM +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) dpll_state <= 2'h1; + else dpll_state <= dpll_next_state; + +always @(dpll_state or lock_en or change) + begin + fs_ce_d = 1'b0; + case(dpll_state) // synopsys full_case parallel_case + 2'h0: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h1; + 2'h1:begin + fs_ce_d = 1'b1; + if(lock_en && change) dpll_next_state = 2'h3; + else dpll_next_state = 2'h2; + end + 2'h2: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h3; + 2'h3: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h0; + endcase + end + +// Compensate for sync registers at the input - allign full speed +// clock enable to be in the middle between two bit changes ... +reg fs_ce_r1, fs_ce_r2; + +always @(posedge clk) fs_ce_r1 <= fs_ce_d; +always @(posedge clk) fs_ce_r2 <= fs_ce_r1; +always @(posedge clk) fs_ce <= fs_ce_r2; + + +/////////////////////////////////////////////////////////////////// +// +// Find Sync Pattern FSM +// + +parameter FS_IDLE = 3'h0, + K1 = 3'h1, + J1 = 3'h2, + K2 = 3'h3, + J2 = 3'h4, + K3 = 3'h5, + J3 = 3'h6, + K4 = 3'h7; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) fs_state <= FS_IDLE; + else fs_state <= fs_next_state; + +always @(fs_state or fs_ce or k or j or rx_en or rx_active or se0 or se0_s) + begin + synced_d = 1'b0; + sync_err_d = 1'b0; + fs_next_state = fs_state; + if(fs_ce && !rx_active && !se0 && !se0_s) + case(fs_state) // synopsys full_case parallel_case + FS_IDLE: + begin + if(k && rx_en) fs_next_state = K1; + end + K1: + begin + if(j && rx_en) fs_next_state = J1; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J1: + begin + if(k && rx_en) fs_next_state = K2; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K2: + begin + if(j && rx_en) fs_next_state = J2; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J2: + begin + if(k && rx_en) fs_next_state = K3; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K3: + begin + if(j && rx_en) fs_next_state = J3; + else + if(k && rx_en) + begin + fs_next_state = FS_IDLE; // Allow missing first K-J + synced_d = 1'b1; + end + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J3: + begin + if(k && rx_en) fs_next_state = K4; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K4: + begin + if(k) synced_d = 1'b1; + fs_next_state = FS_IDLE; + end + endcase + end + +/////////////////////////////////////////////////////////////////// +// +// Generate RxActive +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_active <= 1'b0; + else + if(synced_d && rx_en) rx_active <= 1'b1; + else + if(se0 && rx_valid_r) rx_active <= 1'b0; + +always @(posedge clk) + if(rx_valid) rx_valid_r <= 1'b1; + else + if(fs_ce) rx_valid_r <= 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// NRZI Decoder +// + +always @(posedge clk) + if(fs_ce) sd_r <= rxd_s; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi <= 1'b0; + else + if(!rx_active) sd_nrzi <= 1'b1; + else + if(rx_active && fs_ce) sd_nrzi <= !(rxd_s ^ sd_r); + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuff Detect +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= 3'h0; + else + if(!shift_en) one_cnt <= 3'h0; + else + if(fs_ce) + begin + if(!sd_nrzi || drop_bit) one_cnt <= 3'h0; + else one_cnt <= one_cnt + 3'h1; + end + +assign drop_bit = (one_cnt==3'h6); + +always @(posedge clk) bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active; // Bit Stuff Error + +/////////////////////////////////////////////////////////////////// +// +// Serial => Parallel converter +// + +always @(posedge clk) + if(fs_ce) shift_en <= synced_d | rx_active; + +always @(posedge clk) + if(fs_ce && shift_en && !drop_bit) + hold_reg <= {sd_nrzi, hold_reg[7:1]}; + +/////////////////////////////////////////////////////////////////// +// +// Generate RxValid +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= 3'b0; + else + if(!shift_en) bit_cnt <= 3'h0; + else + if(fs_ce && !drop_bit) bit_cnt <= bit_cnt + 3'h1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_valid1 <= 1'b0; + else + if(fs_ce && !drop_bit && (bit_cnt==3'h7)) rx_valid1 <= 1'b1; + else + if(rx_valid1 && fs_ce && !drop_bit) rx_valid1 <= 1'b0; + +always @(posedge clk) rx_valid <= !drop_bit & rx_valid1 & fs_ce; + +always @(posedge clk) se0_r <= se0; + +always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt[2:1]) & rx_active; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_tx_phy.v b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_tx_phy.v new file mode 100644 index 000000000..7f61ffd3b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/usb_tx_phy.v @@ -0,0 +1,465 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// TX //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_tx_phy.v,v 1.4 2004/10/19 09:29:07 rudi Exp $ +// +// $Date: 2004/10/19 09:29:07 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: usb_tx_phy.v,v $ +// Revision 1.4 2004/10/19 09:29:07 rudi +// Fixed DPLL alignment in the rx_phy and bit stuffing errors in the tx_phy (if last bit bit was a stuff bit in a packet it was omitted). +// +// Revision 1.3 2003/10/21 05:58:41 rudi +// usb_rst is no longer or'ed with the incomming reset internally. +// Now usb_rst is simply an output, the application can decide how +// to utilize it. +// +// Revision 1.2 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.1.1.1 2002/09/16 14:27:02 rudi +// Created Directory Structure +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_tx_phy( + clk, rst, fs_ce, phy_mode, + + // Transciever Interface + txdp, txdn, txoe, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o + ); + +input clk; +input rst; +input fs_ce; +input phy_mode; +output txdp, txdn, txoe; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter IDLE = 3'd0, + SOP = 3'h1, + DATA = 3'h2, + EOP1 = 3'h3, + EOP2 = 3'h4, + WAIT = 3'h5; + +reg TxReady_o; +reg [2:0] state, next_state; +reg tx_ready_d; +reg ld_sop_d; +reg ld_data_d; +reg ld_eop_d; +reg tx_ip; +reg tx_ip_sync; +reg [2:0] bit_cnt; +reg [7:0] hold_reg; +reg [7:0] hold_reg_d; + +reg sd_raw_o; +wire hold; +reg data_done; +reg sft_done; +reg sft_done_r; +wire sft_done_e; +reg ld_data; +wire eop_done; +reg [2:0] one_cnt; +wire stuff; +reg sd_bs_o; +reg sd_nrzi_o; +reg append_eop; +reg append_eop_sync1; +reg append_eop_sync2; +reg append_eop_sync3; +reg append_eop_sync4; +reg txdp, txdn; +reg txoe_r1, txoe_r2; +reg txoe; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) TxReady_o <= 1'b0; + else TxReady_o <= tx_ready_d & TxValid_i; + +always @(posedge clk) ld_data <= ld_data_d; + +/////////////////////////////////////////////////////////////////// +// +// Transmit in progress indicator +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip <= 1'b0; + else + if(ld_sop_d) tx_ip <= 1'b1; + else + if(eop_done) tx_ip <= 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip_sync <= 1'b0; + else + if(fs_ce) tx_ip_sync <= tx_ip; + +// data_done helps us to catch cases where TxValid drops due to +// packet end and then gets re-asserted as a new packet starts. +// We might not see this because we are still transmitting. +// data_done should solve those cases ... +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) data_done <= 1'b0; + else + if(TxValid_i && ! tx_ip) data_done <= 1'b1; + else + if(!TxValid_i) data_done <= 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// Shift Register +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= 3'h0; + else + if(!tx_ip_sync) bit_cnt <= 3'h0; + else + if(fs_ce && !hold) bit_cnt <= bit_cnt + 3'h1; + +assign hold = stuff; + +always @(posedge clk) + if(!tx_ip_sync) sd_raw_o <= 1'b0; + else + case(bit_cnt) // synopsys full_case parallel_case + 3'h0: sd_raw_o <= hold_reg_d[0]; + 3'h1: sd_raw_o <= hold_reg_d[1]; + 3'h2: sd_raw_o <= hold_reg_d[2]; + 3'h3: sd_raw_o <= hold_reg_d[3]; + 3'h4: sd_raw_o <= hold_reg_d[4]; + 3'h5: sd_raw_o <= hold_reg_d[5]; + 3'h6: sd_raw_o <= hold_reg_d[6]; + 3'h7: sd_raw_o <= hold_reg_d[7]; + endcase + +always @(posedge clk) + sft_done <= !hold & (bit_cnt == 3'h7); + +always @(posedge clk) + sft_done_r <= sft_done; + +assign sft_done_e = sft_done & !sft_done_r; + +// Out Data Hold Register +always @(posedge clk) + if(ld_sop_d) hold_reg <= 8'h80; + else + if(ld_data) hold_reg <= DataOut_i; + +always @(posedge clk) hold_reg_d <= hold_reg; + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuffer +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= 3'h0; + else + if(!tx_ip_sync) one_cnt <= 3'h0; + else + if(fs_ce) + begin + if(!sd_raw_o || stuff) one_cnt <= 3'h0; + else one_cnt <= one_cnt + 3'h1; + end + +assign stuff = (one_cnt==3'h6); + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_bs_o <= 1'h0; + else + if(fs_ce) sd_bs_o <= !tx_ip_sync ? 1'b0 : (stuff ? 1'b0 : sd_raw_o); + +/////////////////////////////////////////////////////////////////// +// +// NRZI Encoder +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi_o <= 1'b1; + else + if(!tx_ip_sync || !txoe_r1) sd_nrzi_o <= 1'b1; + else + if(fs_ce) sd_nrzi_o <= sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o; + +/////////////////////////////////////////////////////////////////// +// +// EOP append logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop <= 1'b0; + else + if(ld_eop_d) append_eop <= 1'b1; + else + if(append_eop_sync2) append_eop <= 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync1 <= 1'b0; + else + if(fs_ce) append_eop_sync1 <= append_eop; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync2 <= 1'b0; + else + if(fs_ce) append_eop_sync2 <= append_eop_sync1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync3 <= 1'b0; + else + if(fs_ce) append_eop_sync3 <= append_eop_sync2 | + (append_eop_sync3 & !append_eop_sync4); // Make sure always 2 bit wide + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync4 <= 1'b0; + else + if(fs_ce) append_eop_sync4 <= append_eop_sync3; + +assign eop_done = append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Output Enable Logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r1 <= 1'b0; + else + if(fs_ce) txoe_r1 <= tx_ip_sync; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r2 <= 1'b0; + else + if(fs_ce) txoe_r2 <= txoe_r1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe <= 1'b1; + else + if(fs_ce) txoe <= !(txoe_r1 | txoe_r2); + +/////////////////////////////////////////////////////////////////// +// +// Output Registers +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdp <= 1'b1; + else + if(fs_ce) txdp <= phy_mode ? + (!append_eop_sync3 & sd_nrzi_o) : + sd_nrzi_o; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdn <= 1'b0; + else + if(fs_ce) txdn <= phy_mode ? + (!append_eop_sync3 & ~sd_nrzi_o) : + append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Tx Statemashine +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or TxValid_i or data_done or sft_done_e or eop_done or fs_ce) + begin + next_state = state; + tx_ready_d = 1'b0; + + ld_sop_d = 1'b0; + ld_data_d = 1'b0; + ld_eop_d = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + if(TxValid_i) + begin + ld_sop_d = 1'b1; + next_state = SOP; + end + SOP: + if(sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + next_state = DATA; + end + DATA: + begin + if(!data_done && sft_done_e) + begin + ld_eop_d = 1'b1; + next_state = EOP1; + end + + if(data_done && sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + end + end + EOP1: + if(eop_done) next_state = EOP2; + EOP2: + if(!eop_done && fs_ce) next_state = WAIT; + WAIT: + if(fs_ce) next_state = IDLE; + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/generic_dpram.v b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/generic_dpram.v new file mode 100644 index 000000000..7016af86d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/generic_dpram.v @@ -0,0 +1,515 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Dual-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// +//// //// +//// Description //// +//// This block is a wrapper with common dual-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// dual-port synchronous RAM. //// +//// It also contains a fully synthesizeable model for FPGAs. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Dual-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage 2-port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Generic FPGA (VENDOR_FPGA) //// +//// Tested RAMs: Altera, Xilinx //// +//// Synthesis tools: LeonardoSpectrum, Synplicity //// +//// - Xilinx (VENDOR_XILINX) //// +//// - Altera (VENDOR_ALTERA) //// +//// //// +//// To Do: //// +//// - fix Avant! //// +//// - add additional RAMs (VS etc) //// +//// //// +//// Author(s): //// +//// - Richard Herveille, richard@asics.ws //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: generic_dpram.v,v $ +// Revision 1.3 2003/03/18 21:45:48 rherveille +// Added WISHBONE revB.3 Registered Feedback Cycles support +// +// Revision 1.4 2002/09/28 08:18:52 rherveille +// Changed synthesizeable FPGA memory implementation. +// Fixed some issues with Xilinx BlockRAM +// +// Revision 1.3 2001/11/09 00:34:18 samg +// minor changes: unified with all common rams +// +// Revision 1.2 2001/11/08 19:11:31 samg +// added valid checks to behvioral model +// +// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille +// Major cleanup. +// Files are now compliant to Altera & Xilinx memories. +// Memories are now compatible, i.e. drop-in replacements. +// Added synthesizeable generic FPGA description. +// Created "generic_memories" cvs entry. +// +// Revision 1.1.1.2 2001/08/21 13:09:27 damjan +// *** empty log message *** +// +// Revision 1.1 2001/08/20 18:23:20 damjan +// Initial revision +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +//synopsys translate_off +`include "timescale.v" +//synopsys translate_on + +`define VENDOR_FPGA +//`define VENDOR_XILINX +//`define VENDOR_ALTERA + +module generic_dpram( + // Generic synchronous dual-port RAM interface + rclk, rrst, rce, oe, raddr, do, + wclk, wrst, wce, we, waddr, di +); + + // + // Default address and data buses width + // + parameter aw = 5; // number of bits in address-bus + parameter dw = 16; // number of bits in data-bus + + // + // Generic synchronous double-port RAM interface + // + // read port + input rclk; // read clock, rising edge trigger + input rrst; // read port reset, active high + input rce; // read port chip enable, active high + input oe; // output enable, active high + input [aw-1:0] raddr; // read address + output [dw-1:0] do; // data output + + // write port + input wclk; // write clock, rising edge trigger + input wrst; // write port reset, active high + input wce; // write port chip enable, active high + input we; // write enable, active high + input [aw-1:0] waddr; // write address + input [dw-1:0] di; // data input + + // + // Module body + // + +`ifdef VENDOR_FPGA + // + // Instantiation synthesizeable FPGA memory + // + // This code has been tested using LeonardoSpectrum and Synplicity. + // The code correctly instantiates Altera EABs and Xilinx BlockRAMs. + // + + // NOTE: + // 'synthesis syn_ramstyle="block_ram"' is a Synplify attribute. + // It instructs Synplify to map to BlockRAMs instead of the default SelectRAMs + + reg [dw-1:0] mem [(1<= cursor_x) && (xcnt < (cursor_x + (cursor_res ? 16'h7f : 16'h1f) )); + inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y + (cursor_res ? 16'h7f : 16'h1f) )); + end + + assign inbox = inbox_x && inbox_y; + + always@(posedge clk) + dinbox <= #1 inbox; + + always@(posedge clk) + if (didat_wreq) + ddinbox <= #1 dinbox; + + always@(posedge clk) + dddinbox <= #1 ddinbox; + + // + // generate cursor buffer address counter + always@(posedge clk) + if (!cursor_en || ydone) + cbuf_ra <= #1 12'h0; + else if (inbox && idat_wreq) + cbuf_ra <= #1 cbuf_ra +12'h1; + + always@(posedge clk) + dcbuf_ra <= #1 cbuf_ra[2:0]; + + assign cbuf_a = cursor_we ? cursor_wadr : cursor_res ? cbuf_ra[11:3] : cbuf_ra[9:1]; + + // hookup local cursor memory (generic synchronous single port memory) + // cursor memory should never be written to/read from at the same time + generic_spram #(9, 32) cbuf( + .clk(clk), + .rst(1'b0), // no reset + .ce(1'b1), // always enable memory + .we(cursor_we), + .oe(1'b1), // always output data + .addr(cbuf_a), + .di(cursor_wdat), + .do(cbuf_q) + ); + + // + // decode cursor data for 32x32x16bpp mode + always@(posedge clk) + if (didat_wreq) + cdat <= #1 dcbuf_ra[0] ? cbuf_q[31:16] : cbuf_q[15:0]; + + always@(posedge clk) + dcdat <= #1 cdat; + + // + // decode cursor data for 64x64x4bpp mode + + // generate cursor-color address + always@(posedge clk) + if (didat_wreq) + case (dcbuf_ra) + 3'b000: cc_adr_o <= cbuf_q[ 3: 0]; + 3'b001: cc_adr_o <= cbuf_q[ 7: 4]; + 3'b010: cc_adr_o <= cbuf_q[11: 8]; + 3'b011: cc_adr_o <= cbuf_q[15:12]; + 3'b100: cc_adr_o <= cbuf_q[19:16]; + 3'b101: cc_adr_o <= cbuf_q[23:20]; + 3'b110: cc_adr_o <= cbuf_q[27:24]; + 3'b111: cc_adr_o <= cbuf_q[31:28]; + endcase + + // + // generate cursor colors + assign cursor_isalpha = cursor_res ? cc_dat_i[15] : dcdat[15]; + assign cursor_alpha = cursor_res ? cc_dat_i[7:0] : dcdat[7:0]; + assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dcdat[14:10], 3'h0}; + assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dcdat[ 9: 5], 3'h0}; + assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : dcdat[ 4: 0], 3'h0}; + + // + // delay image data + always@(posedge clk) + didat <= #1 idat; + + always@(posedge clk) + if (didat_wreq) + ddidat <= #1 didat; + + always@(posedge clk) + dddidat <= #1 ddidat; + + always@(posedge clk) + begin + didat_wreq <= #1 idat_wreq; + ddidat_wreq <= #1 didat_wreq; + end + + // + // generate selection unit + always@(posedge clk) + dcursor_en <= #1 cursor_en; + + always@(posedge clk) + if (didat_wreq) + ddcursor_en <= #1 dcursor_en; + + always@(posedge clk) + dddcursor_en <= #1 ddcursor_en; + + // Alpha blending: + // rgb = (rgb1 * alhpa1) + (rgb2 * alpha2) + // We generate an alpha mixer (alpha1 + alpha2 = 1) + // rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2) + // We always mix to black (rgb2 = 0) + // rgb = (alpha1)(rgb1) + always@(posedge clk) + if (ddidat_wreq) + if (!dddcursor_en || !dddinbox) + rgb <= #1 dddidat; + else if (cursor_isalpha) + `ifdef VGA_HWC_3D + rgb <= #1 dddidat * cursor_alpha; + `else + rgb <= #1 dddidat; + `endif + else + rgb <= #1 {cursor_r, cursor_g, cursor_b}; + + // + // generate write request signal + always@(posedge clk) + if (rst_i) + begin + store1 <= #1 1'b0; + store2 <= #1 1'b0; + end + else + begin + store1 <= #1 didat_wreq | store1; + store2 <= #1 (didat_wreq & store1) | store2; + end + + // skip 2 idat_wreq signal, to keep in pace with rgb_fifo_full signal + always@(posedge clk) + rgb_fifo_wreq <= #1 ddidat_wreq & store2; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_defines.v b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_defines.v new file mode 100644 index 000000000..727c21870 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_defines.v @@ -0,0 +1,102 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Defines file //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_defines.v,v 1.6 2003/08/01 11:46:38 rherveille Exp $ +// +// $Date: 2003/08/01 11:46:38 $ +// $Revision: 1.6 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: vga_defines.v,v $ +// Revision 1.6 2003/08/01 11:46:38 rherveille +// 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. +// 2) Changed top level and pixel generator to reflect changes in the fifo. +// 3) Changed a bug in vga_fifo. +// 4) Changed pixel generator and wishbone master to reflect changes. +// +// Revision 1.5 2003/05/07 09:48:54 rherveille +// Fixed some Wishbone RevB.3 related bugs. +// Changed layout of the core. Blocks are located more logically now. +// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters. +// +// Revision 1.4 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + + +//////////////////////// +// +// Global settings +// + +// +// define memory vendor +// for FPGA implementations use `define VENDOR_FPGA + +`define VENDOR_FPGA + +// +// enable / disable 12bit DVI output +// (for use with external DVI transmitters) +//`define VGA_12BIT_DVI + + +//////////////////////// +// +// Hardware Cursors +// + +// +// enable / disable hardware cursors +// +//`define VGA_HWC0 +//`define VGA_HWC1 + + +// +// enable / disabled 3D support for hardware cursors +// +//`define VGA_HWC_3D + diff --git a/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_enh_top.v b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_enh_top.v new file mode 100644 index 000000000..f1bf24db0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_enh_top.v @@ -0,0 +1,448 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant Enhanced VGA/LCD Core //// +//// Top Level //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001,2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_enh_top.v,v 1.6 2003/08/01 11:46:38 rherveille Exp $ +// +// $Date: 2003/08/01 11:46:38 $ +// $Revision: 1.6 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: vga_enh_top.v,v $ +// Revision 1.6 2003/08/01 11:46:38 rherveille +// 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. +// 2) Changed top level and pixel generator to reflect changes in the fifo. +// 3) Changed a bug in vga_fifo. +// 4) Changed pixel generator and wishbone master to reflect changes. +// +// Revision 1.5 2003/07/03 15:09:06 rherveille +// Removed 'or negedge arst' from sluint/luint sensitivity list +// +// Revision 1.4 2003/05/07 09:48:54 rherveille +// Fixed some Wishbone RevB.3 related bugs. +// Changed layout of the core. Blocks are located more logically now. +// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters. +// +// Revision 1.3 2003/03/18 21:45:48 rherveille +// Added WISHBONE revB.3 Registered Feedback Cycles support +// +// Revision 1.2 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// Revision 1.1 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +//synopsys translate_off +`include "timescale.v" +//synopsys translate_on +`include "vga_defines.v" + +module vga_enh_top ( + wb_clk_i, wb_rst_i, rst_i, wb_inta_o, + wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_rty_o, wbs_err_o, + wbm_adr_o, wbm_dat_i, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i, + clk_p_i, +`ifdef VGA_12BIT_DVI + dvi_pclk_p_o, dvi_pclk_m_o, dvi_hsync_o, dvi_vsync_o, dvi_de_o, dvi_d_o, +`endif + clk_p_o, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o + ); + + // + // parameters + // + parameter ARST_LVL = 1'b0; + parameter LINE_FIFO_AWIDTH = 7; + + // + // inputs & outputs + // + + // syscon interface + input wb_clk_i; // wishbone clock input + input wb_rst_i; // synchronous active high reset + input rst_i; // asynchronous reset + output wb_inta_o; // interrupt request output + + // slave signals + input [11:0] wbs_adr_i; // addressbus input (only 32bit databus accesses supported) + input [31:0] wbs_dat_i; // Slave databus output + output [31:0] wbs_dat_o; // Slave databus input + input [ 3:0] wbs_sel_i; // byte select inputs + input wbs_we_i; // write enabel input + input wbs_stb_i; // strobe/select input + input wbs_cyc_i; // valid bus cycle input + output wbs_ack_o; // bus cycle acknowledge output + output wbs_rty_o; // busy cycle retry output + output wbs_err_o; // bus cycle error output + + // master signals + output [31:0] wbm_adr_o; // addressbus output + input [31:0] wbm_dat_i; // Master databus input + output [ 3:0] wbm_sel_o; // byte select outputs + output wbm_we_o; // write enable output + output wbm_stb_o; // strobe output + output wbm_cyc_o; // valid bus cycle output + output [ 2:0] wbm_cti_o; // cycle type identifier + output [ 1:0] wbm_bte_o; // burst type extensions + input wbm_ack_i; // bus cycle acknowledge input + input wbm_err_i; // bus cycle error input + + // VGA signals + input clk_p_i; // pixel clock + // in DVI mode this is 2x as high (!!) + + `ifdef VGA_12BIT_DVI + output dvi_pclk_p_o; // dvi pclk+ + output dvi_pclk_m_o; // dvi pclk- + output dvi_hsync_o; // dvi hsync + output dvi_vsync_o; // dvi vsync + output dvi_de_o; // dvi data enable + output [11:0] dvi_d_o; // dvi 12bit output + `endif + + output clk_p_o; // VGA pixel clock output + output hsync_pad_o; // horizontal sync + output vsync_pad_o; // vertical sync + output csync_pad_o; // composite sync + output blank_pad_o; // blanking signal + output [ 7:0] r_pad_o, g_pad_o, b_pad_o; // RGB color signals + + // + // variable declarations + // + + // programable asynchronous reset + wire arst = rst_i ^ ARST_LVL; + + // from wb_slave + wire ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven; + wire [ 1: 0] ctrl_cd, ctrl_vbl, ctrl_dvi_odf; + wire [ 7: 0] Thsync, Thgdel, Tvsync, Tvgdel; + wire [15: 0] Thgate, Thlen, Tvgate, Tvlen; + wire [31: 2] VBARa, VBARb; + + wire [ 8: 0] cursor_adr; + wire [31: 0] cursor0_xy, cursor1_xy; + wire cursor0_en, cursor1_en; + wire [31:11] cursor0_ba, cursor1_ba; + wire cursor0_ld, cursor1_ld; + wire cursor0_res, cursor1_res; + wire [15: 0] cc0_dat_o, cc1_dat_o; + + // to wb_slave + wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint; + wire wmb_busy; + reg luint; + wire [ 3: 0] cc0_adr_i, cc1_adr_i; + + // pixel generator + wire fb_data_fifo_rreq, fb_data_fifo_empty; + wire [31:0] fb_data_fifo_q; + wire ImDoneFifoQ; + + // line fifo connections + wire line_fifo_wreq, line_fifo_rreq, line_fifo_empty_rd; + wire [23:0] line_fifo_d, line_fifo_q; + + // clut connections + wire ext_clut_req, ext_clut_ack; + wire [23:0] ext_clut_q; + wire cp_clut_req, cp_clut_ack; + wire [ 8:0] cp_clut_adr; + wire [23:0] cp_clut_q; + + // + // Module body + // + + // hookup wishbone slave + vga_wb_slave wbs ( + // wishbone interface + .clk_i ( wb_clk_i ), + .rst_i ( wb_rst_i ), + .arst_i ( arst ), + .adr_i ( wbs_adr_i[11:2] ), + .dat_i ( wbs_dat_i ), + .dat_o ( wbs_dat_o ), + .sel_i ( wbs_sel_i ), + .we_i ( wbs_we_i ), + .stb_i ( wbs_stb_i ), + .cyc_i ( wbs_cyc_i ), + .ack_o ( wbs_ack_o ), + .rty_o ( wbs_rty_o ), + .err_o ( wbs_err_o ), + .inta_o ( wb_inta_o ), + + // internal connections + .wbm_busy ( wbm_busy ), // Data transfer in progress + .dvi_odf ( ctrl_dvi_odf ), // DVI output data format + .bl ( ctrl_bl ), // blank polarization level + .csl ( ctrl_csl ), // csync polarization level + .vsl ( ctrl_vsl ), // vsync polarization level + .hsl ( ctrl_hsl ), // hsync polarization level + .pc ( ctrl_pc ), // pseudo-color mode (only for 8bpp) + .cd ( ctrl_cd ), // color depth + .vbl ( ctrl_vbl ), // video memory burst length + .cbsw ( ctrl_cbsw ), // color lookup table bank switch enable + .vbsw ( ctrl_vbsw ), // video bank switch enable + .ven ( ctrl_ven ), // video enable + .acmp ( stat_acmp ), // active color lookup table page + .avmp ( stat_avmp ), // active video memory page + .cursor0_res ( cursor0_res ), // cursor0 resolution + .cursor0_en ( cursor0_en ), // cursor0 enable + .cursor0_xy ( cursor0_xy ), // cursor0 (x,y) + .cursor0_ba ( cursor0_ba ), // curso0 video memory base address + .cursor0_ld ( cursor0_ld ), // reload curso0 from video memory + .cc0_adr_i ( cc0_adr_i ), // cursor0 color registers address + .cc0_dat_o ( cc0_dat_o ), // cursor0 color registers data + .cursor1_res ( cursor1_res ), // cursor1 resolution + .cursor1_en ( cursor1_en ), // cursor1 enable + .cursor1_xy ( cursor1_xy ), // cursor1 (x,y) + .cursor1_ba ( cursor1_ba ), // cursor1 video memory base address + .cursor1_ld ( cursor1_ld ), // reload cursor1 from video memory + .cc1_adr_i ( cc1_adr_i ), // cursor1 color registers address + .cc1_dat_o ( cc1_dat_o ), // cursor1 color registers data + .vbsint_in ( vmem_swint ), // video memory bank switch interrupt + .cbsint_in ( clut_swint ), // clut memory bank switch interrupt + .hint_in ( hint ), // horizontal interrupt + .vint_in ( vint ), // vertical interrupt + .luint_in ( luint ), // line fifo underrun interrupt + .sint_in ( sint ), // system-error interrupt + .Thsync ( Thsync ), + .Thgdel ( Thgdel ), + .Thgate ( Thgate ), + .Thlen ( Thlen ), + .Tvsync ( Tvsync ), + .Tvgdel ( Tvgdel ), + .Tvgate ( Tvgate ), + .Tvlen ( Tvlen ), + .VBARa ( VBARa ), + .VBARb ( VBARb ), + .clut_acc ( ext_clut_req ), + .clut_ack ( ext_clut_ack ), + .clut_q ( ext_clut_q ) + ); + + // hookup wishbone master + vga_wb_master wbm ( + // wishbone interface + .clk_i ( wb_clk_i ), + .rst_i ( wb_rst_i ), + .nrst_i ( arst ), + .cyc_o ( wbm_cyc_o ), + .stb_o ( wbm_stb_o ), + .cti_o ( wbm_cti_o ), + .bte_o ( wbm_bte_o ), + .we_o ( wbm_we_o ), + .adr_o ( wbm_adr_o ), + .sel_o ( wbm_sel_o ), + .ack_i ( wbm_ack_i ), + .err_i ( wbm_err_i ), + .dat_i ( wbm_dat_i ), + + // internal connections + .sint (sint ), + .ctrl_ven (ctrl_ven ), + .ctrl_cd (ctrl_cd ), + .ctrl_vbl (ctrl_vbl ), + .ctrl_vbsw (ctrl_vbsw ), + .busy (wbm_busy ), + .VBAa (VBARa ), + .VBAb (VBARb ), + .Thgate (Thgate ), + .Tvgate (Tvgate ), + .stat_avmp (stat_avmp ), + .vmem_switch (vmem_swint ), + .ImDoneFifoQ ( ImDoneFifoQ ), + + .cursor_adr ( cursor_adr ), + .cursor0_ba ( cursor0_ba ), // curso0 video memory base address + .cursor0_ld ( cursor0_ld ), // reload curso0 from video memory + .cursor1_ba ( cursor1_ba ), // cursor1 video memory base address + .cursor1_ld ( cursor1_ld ), // reload cursor1 from video memory + + .fb_data_fifo_rreq ( fb_data_fifo_rreq ), + .fb_data_fifo_q ( fb_data_fifo_q ), + .fb_data_fifo_empty ( fb_data_fifo_empty ) + ); + + // hookup CLUT + vga_csm_pb #(24, 9) clut_mem( + .clk_i(wb_clk_i), + + // color processor access + .req0_i(cp_clut_req), + .ack0_o(cp_clut_ack), + .adr0_i(cp_clut_adr), + .dat0_i(24'h0), + .dat0_o(cp_clut_q), + .we0_i(1'b0), // no writes + + // external access + .req1_i(ext_clut_req), + .ack1_o(ext_clut_ack), + .adr1_i(wbs_adr_i[10:2]), + .dat1_i(wbs_dat_i[23:0]), + .dat1_o(ext_clut_q), + .we1_i(wbs_we_i) + ); + + // hookup pixel and video timing generator + vga_pgen pixel_generator ( + .clk_i ( wb_clk_i ), + .ctrl_ven ( ctrl_ven ), + .ctrl_HSyncL ( ctrl_hsl ), + .Thsync ( Thsync ), + .Thgdel ( Thgdel ), + .Thgate ( Thgate ), + .Thlen ( Thlen ), + .ctrl_VSyncL ( ctrl_vsl ), + .Tvsync ( Tvsync ), + .Tvgdel ( Tvgdel ), + .Tvgate ( Tvgate ), + .Tvlen ( Tvlen ), + .ctrl_CSyncL ( ctrl_csl ), + .ctrl_BlankL ( ctrl_bl ), + .eoh ( hint ), + .eov ( vint ), + + // frame buffer data (from wbm) + .fb_data_fifo_rreq ( fb_data_fifo_rreq ), + .fb_data_fifo_q ( fb_data_fifo_q ), + .fb_data_fifo_empty ( fb_data_fifo_empty ), + .ImDoneFifoQ ( ImDoneFifoQ ), + + // clut memory signals + .stat_acmp ( stat_acmp ), + .clut_req ( cp_clut_req ), + .clut_ack ( cp_clut_ack ), + .clut_adr ( cp_clut_adr ), + .clut_q ( cp_clut_q ), + .ctrl_cbsw ( ctrl_cbsw ), + .clut_switch ( clut_swint ), + + .cursor_adr ( cursor_adr ), // cursor data address (from wbm) + .cursor0_en ( cursor0_en ), // cursor0 enable + .cursor0_res ( cursor0_res ), // cursor0 resolution + .cursor0_xy ( cursor0_xy ), // cursor0 (x,y) + .cc0_adr_o ( cc0_adr_i ), // cursor0 color registers address + .cc0_dat_i ( cc0_dat_o ), // cursor0 color registers data + .cursor1_en ( cursor1_en ), // cursor1 enable + .cursor1_res ( cursor1_res ), // cursor1 resolution + .cursor1_xy ( cursor1_xy ), // cursor1 (x,y) + .cc1_adr_o ( cc1_adr_i ), // cursor1 color registers address + .cc1_dat_i ( cc1_dat_o ), // cursor1 color registers data + + .ctrl_dvi_odf ( ctrl_dvi_odf ), + .ctrl_cd ( ctrl_cd ), + .ctrl_pc ( ctrl_pc ), + + // line fifo memory signals + .line_fifo_wreq ( line_fifo_wreq ), + .line_fifo_d ( line_fifo_d ), + .line_fifo_full ( line_fifo_full_wr ), + .line_fifo_rreq ( line_fifo_rreq ), + .line_fifo_q ( line_fifo_q ), + + .pclk_i ( clk_p_i ), + `ifdef VGA_12BIT_DVI + .dvi_pclk_p_o ( dvi_pclk_p_o ), + .dvi_pclk_m_o ( dvi_pclk_m_o ), + .dvi_hsync_o ( dvi_hsync_o ), + .dvi_vsync_o ( dvi_vsync_o ), + .dvi_de_o ( dvi_de_o ), + .dvi_d_o ( dvi_d_o ), + `endif + .pclk_o ( clk_p_o ), + .hsync_o ( hsync_pad_o ), + .vsync_o ( vsync_pad_o ), + .csync_o ( csync_pad_o ), + .blank_o ( blank_pad_o ), + .r_o ( r_pad_o ), + .g_o ( g_pad_o ), + .b_o ( b_pad_o ) + + ); + + // hookup line-fifo + wire ctrl_ven_not = ~ctrl_ven; + vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) line_fifo ( + .rclk ( clk_p_i ), + .wclk ( wb_clk_i ), + .rclr ( 1'b0 ), + .wclr ( ctrl_ven_not ), + .wreq ( line_fifo_wreq ), + .d ( line_fifo_d ), + .rreq ( line_fifo_rreq ), + .q ( line_fifo_q ), + .empty ( line_fifo_empty_rd ), + .full ( line_fifo_full_wr ) + ); + + // generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt) + reg luint_pclk, sluint; + + always @(posedge clk_p_i) + luint_pclk <= #1 line_fifo_rreq & line_fifo_empty_rd; + + always @(posedge wb_clk_i) + if (!ctrl_ven) + begin + sluint <= #1 1'b0; + luint <= #1 1'b0; + end + else + begin + sluint <= #1 luint_pclk; // resample at wb_clk_i clock + luint <= #1 sluint; // sample again, reduce metastability risk + end + +endmodule + + + + + diff --git a/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_fifo.v b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_fifo.v new file mode 100644 index 000000000..b467a621b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_fifo.v @@ -0,0 +1,259 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// generic FIFO, uses LFSRs for read/write pointers //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_fifo.v,v 1.8 2003/08/01 11:46:38 rherveille Exp $ +// +// $Date: 2003/08/01 11:46:38 $ +// $Revision: 1.8 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: vga_fifo.v,v $ +// Revision 1.8 2003/08/01 11:46:38 rherveille +// 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme. +// 2) Changed top level and pixel generator to reflect changes in the fifo. +// 3) Changed a bug in vga_fifo. +// 4) Changed pixel generator and wishbone master to reflect changes. +// +// Revision 1.7 2003/05/07 09:48:54 rherveille +// Fixed some Wishbone RevB.3 related bugs. +// Changed layout of the core. Blocks are located more logically now. +// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters. +// +// Revision 1.6 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +//synopsys translate_off +`include "timescale.v" +//synopsys translate_on + + +// set FIFO_RW_CHECK to prevent writing to a full and reading from an empty FIFO +//`define FIFO_RW_CHECK + +// Long Pseudo Random Generators can generate (N^2 -1) combinations. This means +// 1 FIFO entry is unavailable. This might be a problem, especially for small +// FIFOs. Setting VGA_FIFO_ALL_ENTRIES creates additional logic that ensures that +// all FIFO entries are used at the expense of some additional logic. +`define VGA_FIFO_ALL_ENTRIES + +module vga_fifo ( + clk, + aclr, + sclr, + wreq, + rreq, + d, + q, + nword, + empty, + full, + aempty, + afull + ); + + // + // parameters + // + parameter aw = 3; // no.of entries (in bits; 2^7=128 entries) + parameter dw = 8; // datawidth (in bits) + + // + // inputs & outputs + // + input clk; // master clock + input aclr; // asynchronous active low reset + input sclr; // synchronous active high reset + + input wreq; // write request + input rreq; // read request + input [dw:1] d; // data-input + output [dw:1] q; // data-output + + output [aw:0] nword; // number of words in FIFO + + output empty; // fifo empty + output full; // fifo full + + output aempty; // fifo asynchronous/almost empty (1 entry left) + output afull; // fifo asynchronous/almost full (1 entry left) + + reg [aw:0] nword; + reg empty, full; + + // + // Module body + // + reg [aw:1] rp, wp; + wire [dw:1] ramq; + wire fwreq, frreq; + +`ifdef VGA_FIFO_ALL_ENTRIES + function lsb; + input [aw:1] q; + case (aw) + 2: lsb = ~q[2]; + 3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]); + 4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]); + 5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]); + 6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]); + 7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]); + 8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]); + 9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]); + 10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]); + 11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]); + 12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]); + 13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]); + 14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]); + 15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]); + 16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]); + endcase + endfunction +`else + function lsb; + input [aw:1] q; + case (aw) + 2: lsb = ~q[2]; + 3: lsb = ~(q[3] ^ q[2]); + 4: lsb = ~(q[4] ^ q[3]); + 5: lsb = ~(q[5] ^ q[3]); + 6: lsb = ~(q[6] ^ q[5]); + 7: lsb = ~(q[7] ^ q[6]); + 8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]); + 9: lsb = ~(q[9] ^ q[5]); + 10: lsb = ~(q[10] ^ q[7]); + 11: lsb = ~(q[11] ^ q[9]); + 12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]); + 13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]); + 14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]); + 15: lsb = ~(q[15] ^ q[14]); + 16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]); + endcase + endfunction +`endif + +`ifdef RW_CHECK + assign fwreq = wreq & ~full; + assign frreq = rreq & ~empty; +`else + assign fwreq = wreq; + assign frreq = rreq; +`endif + + // + // hookup read-pointer + // + always @(posedge clk or negedge aclr) + if (~aclr) rp <= #1 0; + else if (sclr) rp <= #1 0; + else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)}; + + // + // hookup write-pointer + // + always @(posedge clk or negedge aclr) + if (~aclr) wp <= #1 0; + else if (sclr) wp <= #1 0; + else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)}; + + + // + // hookup memory-block + // + reg [dw:1] mem [(1<> 2; // 8bpp, 4 pixels per cycle + 2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle + 2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle + 2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle + endcase + + hgate_div_cnt <= 2'b10; + end + else if (vmem_ack) + if (hdone) + begin + case(ctrl_cd) // synopsys full_case parallel_case + 2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle + 2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle + 2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle + 2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle + endcase + + hgate_div_cnt <= 2'b10; + end + else //if (vmem_ack) + begin + hgate_cnt <= #1 hgate_cnt_val[15:0]; + + if ( hgate_div_val[2] ) + hgate_div_cnt <= #1 2'b10; + else + hgate_div_cnt <= #1 hgate_div_val[1:0]; + end + + // vgate counter + reg [15:0] vgate_cnt; + wire [16:0] vgate_cnt_val; + wire vdone; + + assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1; + assign vdone = vgate_cnt_val[16]; + + always @(posedge clk_i) + if (sclr | ImDoneStrb) + vgate_cnt <= #1 Tvgate; + else if (hdone) + vgate_cnt <= #1 vgate_cnt_val[15:0]; + + assign ImDone = hdone & vdone; + + assign ImDoneStrb = ImDone & !dImDone; + + always @(posedge clk_i) + begin + dImDone <= #1 ImDone; + dImDoneStrb <= #1 ImDoneStrb; + end + + // + // generate addresses + // + + // select video memory base address + always @(posedge clk_i) + if (sclr | dImDoneStrb) + if (!sel_VBA) + vmemA <= #1 VBAa; + else + vmemA <= #1 VBAb; + else if (vmem_ack) + vmemA <= #1 vmemA +30'h1; + + + //////////////////////////////////// + // hardware cursor signals section + // + always @(posedge clk_i) + if (ImDone) + cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority + + always @(posedge clk_i) + if (sclr) + begin + ld_cursor0 <= #1 1'b0; + ld_cursor1 <= #1 1'b0; + end + else + begin + ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel)); + ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel)); + end + + // select cursor base address + always @(posedge clk_i) + if (!cur_acc) + cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba; + + // generate pattern offset + wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1; + assign cur_done = next_cursor_adr[9] & cur_ack; + + always @(posedge clk_i) + if (!cur_acc) + cursor_adr <= #1 9'h0; + else if (cur_ack) + cursor_adr <= #1 next_cursor_adr; + + // generate cursor buffers write enable signals + assign cursor1_we = cur_ack & !cur_acc_sel; + assign cursor0_we = cur_ack & cur_acc_sel; + + + ////////////////////////////// + // generate wishbone signals + // + assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00}; + wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone || + cur_acc & !cur_done; + + always @(posedge clk_i or negedge nrst_i) + if (!nrst_i) + begin + cyc_o <= #1 1'b0; + stb_o <= #1 1'b0; + sel_o <= #1 4'b1111; + cti_o <= #1 3'b000; + bte_o <= #1 2'b00; + we_o <= #1 1'b0; + end + else + if (rst_i) + begin + cyc_o <= #1 1'b0; + stb_o <= #1 1'b0; + sel_o <= #1 4'b1111; + cti_o <= #1 3'b000; + bte_o <= #1 2'b00; + we_o <= #1 1'b0; + end + else + begin + cyc_o <= #1 wb_cycle; + stb_o <= #1 wb_cycle; + sel_o <= #1 4'b1111; // only 32bit accesses are supported + + if (wb_cycle) begin + if (cur_acc) + cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010; + else if (ctrl_vbl == 2'b00) + cti_o <= #1 3'b000; + else if (vmem_ack) + cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010; + end else + cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010; + + bte_o <= #1 2'b00; // linear burst + we_o <= #1 1'b0; // read only + end + + // + // video-data buffer (temporary store data read from video memory) + wire [4:0] fb_data_fifo_nword; +// wire fb_data_fifo_full; + + vga_fifo #(4, 32) data_fifo ( + .clk ( clk_i ), + .aclr ( 1'b1 ), + .sclr ( sclr ), + .d ( dat_i ), + .wreq ( vmem_ack ), + .q ( fb_data_fifo_q ), + .rreq ( fb_data_fifo_rreq ), + .nword ( fb_data_fifo_nword ), + .empty ( fb_data_fifo_empty ), + .full ( ),//fb_data_fifo_full ), + .aempty ( ), + .afull ( ) + ); + + assign vmem_req = ~fb_data_fifo_nword[4] & ~fb_data_fifo_nword[3]; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_wb_slave.v b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_wb_slave.v new file mode 100644 index 000000000..47aad8a11 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/vga_wb_slave.v @@ -0,0 +1,465 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant enhanced VGA/LCD Core //// +//// Wishbone slave interface //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/vga_lcd //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001, 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: vga_wb_slave.v,v 1.12 2003/05/07 09:48:54 rherveille Exp $ +// +// $Date: 2003/05/07 09:48:54 $ +// $Revision: 1.12 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: vga_wb_slave.v,v $ +// Revision 1.12 2003/05/07 09:48:54 rherveille +// Fixed some Wishbone RevB.3 related bugs. +// Changed layout of the core. Blocks are located more logically now. +// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters. +// +// Revision 1.11 2002/04/20 10:02:39 rherveille +// Changed video timing generator. +// Changed wishbone master vertical gate count code. +// Fixed a potential bug in the wishbone slave (cursor color register readout). +// +// Revision 1.10 2002/03/28 04:59:25 rherveille +// Fixed two small bugs that only showed up when the hardware cursors were disabled +// +// Revision 1.9 2002/03/04 16:05:52 rherveille +// Added hardware cursor support to wishbone master. +// Added provision to turn-off 3D cursors. +// Fixed some minor bugs. +// +// Revision 1.8 2002/03/04 11:01:59 rherveille +// Added 64x64pixels 4bpp hardware cursor support. +// +// Revision 1.7 2002/02/25 06:13:44 rherveille +// Fixed dat_o incomplete sensitivity list. +// +// Revision 1.6 2002/02/07 05:42:10 rherveille +// Fixed some bugs discovered by modified testbench +// Removed / Changed some strange logic constructions +// Started work on hardware cursor support (not finished yet) +// Changed top-level name to vga_enh_top.v +// + +//synopsys translate_off +`include "timescale.v" +//synopsys translate_on +`include "vga_defines.v" + +module vga_wb_slave( + clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, rty_o, err_o, inta_o, + wbm_busy, dvi_odf, bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, + cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o, + cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o, + vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in, + Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, + clut_acc, clut_ack, clut_q + ); + + // + // inputs & outputs + // + + // wishbone slave interface + input clk_i; + input rst_i; + input arst_i; + input [11:2] adr_i; + input [31:0] dat_i; + output [31:0] dat_o; + reg [31:0] dat_o; + input [ 3:0] sel_i; + input we_i; + input stb_i; + input cyc_i; + output ack_o; + reg ack_o; + output rty_o; + reg rty_o; + output err_o; + reg err_o; + output inta_o; + reg inta_o; + + // wishbone master controller feedback + input wbm_busy; // data transfer in progress + + // control register settings + output [1:0] dvi_odf; // DVI output data format + output bl; // blanking level + output csl; // composite sync level + output vsl; // vsync level + output hsl; // hsync level + output pc; // pseudo color + output [1:0] cd; // color depth + output [1:0] vbl; // video memory burst length + output cbsw; // clut bank switch enable + output vbsw; // video memory bank switch enable + output ven; // video system enable + + // hardware cursor settings + output cursor0_res; // cursor0 resolution + output cursor0_en; // cursor0 enable + output [31: 0] cursor0_xy; // cursor0 location + output [31:11] cursor0_ba; // cursor0 base address + output cursor0_ld; // reload cursor0 from video memory + input [ 3: 0] cc0_adr_i; // cursor0 color register address + output [15: 0] cc0_dat_o; // cursor0 color register data + output cursor1_res; // cursor1 resolution + output cursor1_en; // cursor1 enable + output [31: 0] cursor1_xy; // cursor1 location + output [31:11] cursor1_ba; // cursor1 base address + output cursor1_ld; // reload cursor1 from video memory + input [ 3: 0] cc1_adr_i; // cursor1 color register address + output [15: 0] cc1_dat_o; // cursor1 color register data + + reg [31: 0] cursor0_xy; + reg [31:11] cursor0_ba; + reg cursor0_ld; + reg [31: 0] cursor1_xy; + reg [31:11] cursor1_ba; + reg cursor1_ld; + + // status register inputs + input avmp; // active video memory page + input acmp; // active clut memory page + input vbsint_in; // bank switch interrupt request + input cbsint_in; // clut switch interrupt request + input hint_in; // hsync interrupt request + input vint_in; // vsync interrupt request + input luint_in; // line fifo underrun interrupt request + input sint_in; // system error interrupt request + + // Horizontal Timing Register + output [ 7:0] Thsync; + output [ 7:0] Thgdel; + output [15:0] Thgate; + output [15:0] Thlen; + + // Vertical Timing Register + output [ 7:0] Tvsync; + output [ 7:0] Tvgdel; + output [15:0] Tvgate; + output [15:0] Tvlen; + + // video base addresses + output [31:2] VBARa; + reg [31:2] VBARa; + output [31:2] VBARb; + reg [31:2] VBARb; + + // color lookup table signals + output clut_acc; + input clut_ack; + input [23:0] clut_q; + + + // + // variable declarations + // + parameter REG_ADR_HIBIT = 7; + + wire [REG_ADR_HIBIT:0] REG_ADR = adr_i[REG_ADR_HIBIT : 2]; + wire CLUT_ADR = adr_i[11]; + + parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 6'b00_0000; + parameter [REG_ADR_HIBIT : 0] STAT_ADR = 6'b00_0001; + parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 6'b00_0010; + parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 6'b00_0011; + parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 6'b00_0100; + parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 6'b00_0101; + parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 6'b00_0110; + parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 6'b00_1100; + parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 6'b00_1101; + parameter [REG_ADR_HIBIT : 0] CCR0_ADR = 6'b01_0???; + parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 6'b01_1100; + parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 6'b01_1101; + parameter [REG_ADR_HIBIT : 0] CCR1_ADR = 6'b10_0???; + + + reg [31:0] ctrl, stat, htim, vtim, hvlen; + wire hint, vint, vbsint, cbsint, luint, sint; + wire hie, vie, vbsie, cbsie; + wire acc, acc32, reg_acc, reg_wacc; + wire cc0_acc, cc1_acc; + wire [31:0] ccr0_dat_o, ccr1_dat_o; + + + reg [31:0] reg_dato; // data output from registers + + // + // Module body + // + + assign acc = cyc_i & stb_i; + assign acc32 = (sel_i == 4'b1111); + assign clut_acc = CLUT_ADR & acc & acc32; + assign reg_acc = ~CLUT_ADR & acc & acc32; + assign reg_wacc = reg_acc & we_i; + + assign cc0_acc = (REG_ADR == CCR0_ADR) & acc & acc32; + assign cc1_acc = (REG_ADR == CCR1_ADR) & acc & acc32; + + always @(posedge clk_i) + ack_o <= #1 ((reg_acc & acc32) | clut_ack) & ~(wbm_busy & REG_ADR == CTRL_ADR) & ~ack_o ; + + always @(posedge clk_i) + rty_o <= #1 ((reg_acc & acc32) | clut_ack) & (wbm_busy & REG_ADR == CTRL_ADR) & ~rty_o ; + + always @(posedge clk_i) + err_o <= #1 acc & ~acc32 & ~err_o; + + + // generate registers + always @(posedge clk_i or negedge arst_i) + begin : gen_regs + if (!arst_i) + begin + htim <= #1 0; + vtim <= #1 0; + hvlen <= #1 0; + VBARa <= #1 0; + VBARb <= #1 0; + cursor0_xy <= #1 0; + cursor0_ba <= #1 0; + cursor1_xy <= #1 0; + cursor1_ba <= #1 0; + end + else if (rst_i) + begin + htim <= #1 0; + vtim <= #1 0; + hvlen <= #1 0; + VBARa <= #1 0; + VBARb <= #1 0; + cursor0_xy <= #1 0; + cursor0_ba <= #1 0; + cursor1_xy <= #1 0; + cursor1_ba <= #1 0; + end + else if (reg_wacc) + case (adr_i) // synopsis full_case parallel_case + HTIM_ADR : htim <= #1 dat_i; + VTIM_ADR : vtim <= #1 dat_i; + HVLEN_ADR : hvlen <= #1 dat_i; + VBARA_ADR : VBARa <= #1 dat_i[31: 2]; + VBARB_ADR : VBARb <= #1 dat_i[31: 2]; + C0XY_ADR : cursor0_xy <= #1 dat_i[31: 0]; + C0BAR_ADR : cursor0_ba <= #1 dat_i[31:11]; + C1XY_ADR : cursor1_xy <= #1 dat_i[31: 0]; + C1BAR_ADR : cursor1_ba <= #1 dat_i[31:11]; + endcase + end + + always @(posedge clk_i) + begin + cursor0_ld <= #1 reg_wacc && (adr_i == C0BAR_ADR); + cursor1_ld <= #1 reg_wacc && (adr_i == C1BAR_ADR); + end + + // generate control register + always @(posedge clk_i or negedge arst_i) + if (!arst_i) + ctrl <= #1 0; + else if (rst_i) + ctrl <= #1 0; + else if (reg_wacc & (REG_ADR == CTRL_ADR) & ~wbm_busy ) + ctrl <= #1 dat_i; + else begin + ctrl[6] <= #1 ctrl[6] & !cbsint_in; + ctrl[5] <= #1 ctrl[5] & !vbsint_in; + end + + + // generate status register + always @(posedge clk_i or negedge arst_i) + if (!arst_i) + stat <= #1 0; + else if (rst_i) + stat <= #1 0; + else begin + `ifdef VGA_HWC1 + stat[21] <= #1 1'b1; + `else + stat[21] <= #1 1'b0; + `endif + `ifdef VGA_HWC0 + stat[20] <= #1 1'b1; + `else + stat[20] <= #1 1'b0; + `endif + + stat[17] <= #1 acmp; + stat[16] <= #1 avmp; + + if (reg_wacc & (REG_ADR == STAT_ADR) ) + begin + stat[7] <= #1 cbsint_in | (stat[7] & !dat_i[7]); + stat[6] <= #1 vbsint_in | (stat[6] & !dat_i[6]); + stat[5] <= #1 hint_in | (stat[5] & !dat_i[5]); + stat[4] <= #1 vint_in | (stat[4] & !dat_i[4]); + stat[1] <= #1 luint_in | (stat[3] & !dat_i[1]); + stat[0] <= #1 sint_in | (stat[0] & !dat_i[0]); + end + else + begin + stat[7] <= #1 stat[7] | cbsint_in; + stat[6] <= #1 stat[6] | vbsint_in; + stat[5] <= #1 stat[5] | hint_in; + stat[4] <= #1 stat[4] | vint_in; + stat[1] <= #1 stat[1] | luint_in; + stat[0] <= #1 stat[0] | sint_in; + end + end + + + // decode control register + assign dvi_odf = ctrl[29:28]; + assign cursor1_res = ctrl[25]; + assign cursor1_en = ctrl[24]; + assign cursor0_res = ctrl[23]; + assign cursor0_en = ctrl[20]; + assign bl = ctrl[15]; + assign csl = ctrl[14]; + assign vsl = ctrl[13]; + assign hsl = ctrl[12]; + assign pc = ctrl[11]; + assign cd = ctrl[10:9]; + assign vbl = ctrl[8:7]; + assign cbsw = ctrl[6]; + assign vbsw = ctrl[5]; + assign cbsie = ctrl[4]; + assign vbsie = ctrl[3]; + assign hie = ctrl[2]; + assign vie = ctrl[1]; + assign ven = ctrl[0]; + + // decode status register + assign cbsint = stat[7]; + assign vbsint = stat[6]; + assign hint = stat[5]; + assign vint = stat[4]; + assign luint = stat[1]; + assign sint = stat[0]; + + // decode Horizontal Timing Register + assign Thsync = htim[31:24]; + assign Thgdel = htim[23:16]; + assign Thgate = htim[15:0]; + assign Thlen = hvlen[31:16]; + + // decode Vertical Timing Register + assign Tvsync = vtim[31:24]; + assign Tvgdel = vtim[23:16]; + assign Tvgate = vtim[15:0]; + assign Tvlen = hvlen[15:0]; + + + `ifdef VGA_HWC0 + // hookup cursor0 color registers + vga_cur_cregs cregs0( + .clk_i(clk_i), + .rst_i(rst_i), + .arst_i(arst_i), + .hsel_i(cc0_acc), + .hadr_i(adr_i[4:2]), + .hwe_i(we_i), + .hdat_i(dat_i), + .hdat_o(ccr0_dat_o), // host access + .hack_o(), + .cadr_i(cc0_adr_i), + .cdat_o(cc0_dat_o) // cursor processor access + ); + `else + assign ccr0_dat_o = 32'h0; + assign cc0_dat_o = 32'h0; + `endif + + `ifdef VGA_HWC1 + // hookup cursor1 color registers + vga_cur_cregs cregs1( + .clk_i(clk_i), + .rst_i(rst_i), + .arst_i(arst_i), + .hsel_i(cc1_acc), + .hadr_i(adr_i[4:2]), + .hwe_i(we_i), + .hdat_i(dat_i), + .hdat_o(ccr1_dat_o), // host access + .hack_o(), + .cadr_i(cc1_adr_i), + .cdat_o(cc1_dat_o) // cursor processor access + ); + `else + assign ccr1_dat_o = 32'h0; + assign cc1_dat_o = 32'h0; + `endif + + + // assign output + always @(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or + cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba or ccr0_dat_o or ccr1_dat_o) + casez (REG_ADR) // synopsis full_case parallel_case + CTRL_ADR : reg_dato = ctrl; + STAT_ADR : reg_dato = stat; + HTIM_ADR : reg_dato = htim; + VTIM_ADR : reg_dato = vtim; + HVLEN_ADR : reg_dato = hvlen; + VBARA_ADR : reg_dato = {VBARa, 2'b0}; + VBARB_ADR : reg_dato = {VBARb, 2'b0}; + C0XY_ADR : reg_dato = cursor0_xy; + C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0}; + CCR0_ADR : reg_dato = ccr0_dat_o; + C1XY_ADR : reg_dato = cursor1_xy; + C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0}; + CCR1_ADR : reg_dato = ccr1_dat_o; + default : reg_dato = 32'h0000_0000; + endcase + + always @(posedge clk_i) + dat_o <= #1 reg_acc ? reg_dato : {8'h0, clut_q}; + + // generate interrupt request signal + always @(posedge clk_i) + inta_o <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint; +endmodule + + + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_arb.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_arb.v new file mode 100644 index 000000000..4a50e873e --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_arb.v @@ -0,0 +1,267 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// General Round Robin Arbiter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_arb.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_arb.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:40 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_arb(clk, rst, req, gnt, next); + +input clk; +input rst; +input [7:0] req; // Req input +output [2:0] gnt; // Grant output +input next; // Next Target + +/////////////////////////////////////////////////////////////////////// +// +// Parameters +// + +parameter [2:0] + grant0 = 3'h0, + grant1 = 3'h1, + grant2 = 3'h2, + grant3 = 3'h3, + grant4 = 3'h4, + grant5 = 3'h5, + grant6 = 3'h6, + grant7 = 3'h7; + +/////////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [2:0] state, next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign gnt = state; + +always@(posedge clk or posedge rst) + if(rst) state <= #1 grant0; + else state <= #1 next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Next State Logic +// - implements round robin arbitration algorithm +// - switches grant if current req is dropped or next is asserted +// - parks at last grant +// + +always@(state or req or next) + begin + next_state = state; // Default Keep State + case(state) // synopsys parallel_case full_case + grant0: + // if this req is dropped or next is asserted, check for other req's + if(!req[0] | next) + begin + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + end + grant1: + // if this req is dropped or next is asserted, check for other req's + if(!req[1] | next) + begin + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + end + grant2: + // if this req is dropped or next is asserted, check for other req's + if(!req[2] | next) + begin + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] | next) + begin + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + end + grant4: + // if this req is dropped or next is asserted, check for other req's + if(!req[4] | next) + begin + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + end + grant5: + // if this req is dropped or next is asserted, check for other req's + if(!req[5] | next) + begin + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + end + grant6: + // if this req is dropped or next is asserted, check for other req's + if(!req[6] | next) + begin + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + end + grant7: + // if this req is dropped or next is asserted, check for other req's + if(!req[7] | next) + begin + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + end + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_defines.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_defines.v new file mode 100644 index 000000000..1f0968505 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_defines.v @@ -0,0 +1,65 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_defines.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_defines.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:40 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// +// +// + +`timescale 1ns / 10ps + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_master_if.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_master_if.v new file mode 100644 index 000000000..51fc868d0 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_master_if.v @@ -0,0 +1,659 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Master Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_master_if.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_master_if.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:41 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_master_if( + + clk_i, rst_i, + + // Master interface + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + + // Slave 0 Interface + s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, + + // Slave 1 Interface + s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, + + // Slave 2 Interface + s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, + + // Slave 3 Interface + s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, + + // Slave 4 Interface + s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, + + // Slave 5 Interface + s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, + + // Slave 6 Interface + s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, + + // Slave 7 Interface + s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, + + // Slave 8 Interface + s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o, + s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i, + + // Slave 9 Interface + s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o, + s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i, + + // Slave 10 Interface + s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o, + s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i, + + // Slave 11 Interface + s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o, + s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i, + + // Slave 12 Interface + s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o, + s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i, + + // Slave 13 Interface + s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o, + s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i, + + // Slave 14 Interface + s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o, + s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i, + + // Slave 15 Interface + s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o, + s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Master Interface +input [dw-1:0] wb_data_i; +output [dw-1:0] wb_data_o; +input [aw-1:0] wb_addr_i; +input [sw-1:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_data_i; +output [dw-1:0] s0_data_o; +output [aw-1:0] s0_addr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_data_i; +output [dw-1:0] s1_data_o; +output [aw-1:0] s1_addr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_data_i; +output [dw-1:0] s2_data_o; +output [aw-1:0] s2_addr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_data_i; +output [dw-1:0] s3_data_o; +output [aw-1:0] s3_addr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_data_i; +output [dw-1:0] s4_data_o; +output [aw-1:0] s4_addr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_data_i; +output [dw-1:0] s5_data_o; +output [aw-1:0] s5_addr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_data_i; +output [dw-1:0] s6_data_o; +output [aw-1:0] s6_addr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_data_i; +output [dw-1:0] s7_data_o; +output [aw-1:0] s7_addr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + +// Slave 8 Interface +input [dw-1:0] s8_data_i; +output [dw-1:0] s8_data_o; +output [aw-1:0] s8_addr_o; +output [sw-1:0] s8_sel_o; +output s8_we_o; +output s8_cyc_o; +output s8_stb_o; +input s8_ack_i; +input s8_err_i; +input s8_rty_i; + +// Slave 9 Interface +input [dw-1:0] s9_data_i; +output [dw-1:0] s9_data_o; +output [aw-1:0] s9_addr_o; +output [sw-1:0] s9_sel_o; +output s9_we_o; +output s9_cyc_o; +output s9_stb_o; +input s9_ack_i; +input s9_err_i; +input s9_rty_i; + +// Slave 10 Interface +input [dw-1:0] s10_data_i; +output [dw-1:0] s10_data_o; +output [aw-1:0] s10_addr_o; +output [sw-1:0] s10_sel_o; +output s10_we_o; +output s10_cyc_o; +output s10_stb_o; +input s10_ack_i; +input s10_err_i; +input s10_rty_i; + +// Slave 11 Interface +input [dw-1:0] s11_data_i; +output [dw-1:0] s11_data_o; +output [aw-1:0] s11_addr_o; +output [sw-1:0] s11_sel_o; +output s11_we_o; +output s11_cyc_o; +output s11_stb_o; +input s11_ack_i; +input s11_err_i; +input s11_rty_i; + +// Slave 12 Interface +input [dw-1:0] s12_data_i; +output [dw-1:0] s12_data_o; +output [aw-1:0] s12_addr_o; +output [sw-1:0] s12_sel_o; +output s12_we_o; +output s12_cyc_o; +output s12_stb_o; +input s12_ack_i; +input s12_err_i; +input s12_rty_i; + +// Slave 13 Interface +input [dw-1:0] s13_data_i; +output [dw-1:0] s13_data_o; +output [aw-1:0] s13_addr_o; +output [sw-1:0] s13_sel_o; +output s13_we_o; +output s13_cyc_o; +output s13_stb_o; +input s13_ack_i; +input s13_err_i; +input s13_rty_i; + +// Slave 14 Interface +input [dw-1:0] s14_data_i; +output [dw-1:0] s14_data_o; +output [aw-1:0] s14_addr_o; +output [sw-1:0] s14_sel_o; +output s14_we_o; +output s14_cyc_o; +output s14_stb_o; +input s14_ack_i; +input s14_err_i; +input s14_rty_i; + +// Slave 15 Interface +input [dw-1:0] s15_data_i; +output [dw-1:0] s15_data_o; +output [aw-1:0] s15_addr_o; +output [sw-1:0] s15_sel_o; +output s15_we_o; +output s15_cyc_o; +output s15_stb_o; +input s15_ack_i; +input s15_err_i; +input s15_rty_i; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [dw-1:0] wb_data_o; +reg wb_ack_o; +reg wb_err_o; +reg wb_rty_o; +wire [3:0] slv_sel; + +wire s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next; +wire s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next; +wire s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next; +wire s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next; + +reg s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o; +reg s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o; +reg s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o; +reg s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o; + +//////////////////////////////////////////////////////////////////// +// +// Select logic +// + +assign slv_sel = wb_addr_i[aw-1:aw-4]; + +//////////////////////////////////////////////////////////////////// +// +// Address & Data Pass +// + +assign s0_addr_o = wb_addr_i; +assign s1_addr_o = wb_addr_i; +assign s2_addr_o = wb_addr_i; +assign s3_addr_o = wb_addr_i; +assign s4_addr_o = wb_addr_i; +assign s5_addr_o = wb_addr_i; +assign s6_addr_o = wb_addr_i; +assign s7_addr_o = wb_addr_i; +assign s8_addr_o = wb_addr_i; +assign s9_addr_o = wb_addr_i; +assign s10_addr_o = wb_addr_i; +assign s11_addr_o = wb_addr_i; +assign s12_addr_o = wb_addr_i; +assign s13_addr_o = wb_addr_i; +assign s14_addr_o = wb_addr_i; +assign s15_addr_o = wb_addr_i; + +assign s0_sel_o = wb_sel_i; +assign s1_sel_o = wb_sel_i; +assign s2_sel_o = wb_sel_i; +assign s3_sel_o = wb_sel_i; +assign s4_sel_o = wb_sel_i; +assign s5_sel_o = wb_sel_i; +assign s6_sel_o = wb_sel_i; +assign s7_sel_o = wb_sel_i; +assign s8_sel_o = wb_sel_i; +assign s9_sel_o = wb_sel_i; +assign s10_sel_o = wb_sel_i; +assign s11_sel_o = wb_sel_i; +assign s12_sel_o = wb_sel_i; +assign s13_sel_o = wb_sel_i; +assign s14_sel_o = wb_sel_i; +assign s15_sel_o = wb_sel_i; + +assign s0_data_o = wb_data_i; +assign s1_data_o = wb_data_i; +assign s2_data_o = wb_data_i; +assign s3_data_o = wb_data_i; +assign s4_data_o = wb_data_i; +assign s5_data_o = wb_data_i; +assign s6_data_o = wb_data_i; +assign s7_data_o = wb_data_i; +assign s8_data_o = wb_data_i; +assign s9_data_o = wb_data_i; +assign s10_data_o = wb_data_i; +assign s11_data_o = wb_data_i; +assign s12_data_o = wb_data_i; +assign s13_data_o = wb_data_i; +assign s14_data_o = wb_data_i; +assign s15_data_o = wb_data_i; + +always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or + s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or + s9_data_i or s10_data_i or s11_data_i or s12_data_i or + s13_data_i or s14_data_i or s15_data_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_data_o = s0_data_i; + 4'd1: wb_data_o = s1_data_i; + 4'd2: wb_data_o = s2_data_i; + 4'd3: wb_data_o = s3_data_i; + 4'd4: wb_data_o = s4_data_i; + 4'd5: wb_data_o = s5_data_i; + 4'd6: wb_data_o = s6_data_i; + 4'd7: wb_data_o = s7_data_i; + 4'd8: wb_data_o = s8_data_i; + 4'd9: wb_data_o = s9_data_i; + 4'd10: wb_data_o = s10_data_i; + 4'd11: wb_data_o = s11_data_i; + 4'd12: wb_data_o = s12_data_i; + 4'd13: wb_data_o = s13_data_i; + 4'd14: wb_data_o = s14_data_i; + 4'd15: wb_data_o = s15_data_i; + default: wb_data_o = {dw{1'bx}}; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Control Signal Pass +// + +assign s0_we_o = wb_we_i; +assign s1_we_o = wb_we_i; +assign s2_we_o = wb_we_i; +assign s3_we_o = wb_we_i; +assign s4_we_o = wb_we_i; +assign s5_we_o = wb_we_i; +assign s6_we_o = wb_we_i; +assign s7_we_o = wb_we_i; +assign s8_we_o = wb_we_i; +assign s9_we_o = wb_we_i; +assign s10_we_o = wb_we_i; +assign s11_we_o = wb_we_i; +assign s12_we_o = wb_we_i; +assign s13_we_o = wb_we_i; +assign s14_we_o = wb_we_i; +assign s15_we_o = wb_we_i; + +assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0); +assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0); +assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0); +assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0); +assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0); +assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0); +assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0); +assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0); +assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0); +assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0); +assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0); +assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0); +assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0); +assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0); +assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0); +assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0); + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s0_cyc_o <= #1 1'b0; + else s0_cyc_o <= #1 s0_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s1_cyc_o <= #1 1'b0; + else s1_cyc_o <= #1 s1_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s2_cyc_o <= #1 1'b0; + else s2_cyc_o <= #1 s2_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s3_cyc_o <= #1 1'b0; + else s3_cyc_o <= #1 s3_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s4_cyc_o <= #1 1'b0; + else s4_cyc_o <= #1 s4_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s5_cyc_o <= #1 1'b0; + else s5_cyc_o <= #1 s5_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s6_cyc_o <= #1 1'b0; + else s6_cyc_o <= #1 s6_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s7_cyc_o <= #1 1'b0; + else s7_cyc_o <= #1 s7_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s8_cyc_o <= #1 1'b0; + else s8_cyc_o <= #1 s8_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s9_cyc_o <= #1 1'b0; + else s9_cyc_o <= #1 s9_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s10_cyc_o <= #1 1'b0; + else s10_cyc_o <= #1 s10_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s11_cyc_o <= #1 1'b0; + else s11_cyc_o <= #1 s11_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s12_cyc_o <= #1 1'b0; + else s12_cyc_o <= #1 s12_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s13_cyc_o <= #1 1'b0; + else s13_cyc_o <= #1 s13_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s14_cyc_o <= #1 1'b0; + else s14_cyc_o <= #1 s14_cyc_o_next; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) s15_cyc_o <= #1 1'b0; + else s15_cyc_o <= #1 s15_cyc_o_next; + +assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0; +assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0; +assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0; +assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0; +assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0; +assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0; +assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0; +assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0; +assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0; +assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0; +assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0; +assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0; +assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0; +assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0; +assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0; +assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0; + +always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or + s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or + s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or + s13_ack_i or s14_ack_i or s15_ack_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_ack_o = s0_ack_i; + 4'd1: wb_ack_o = s1_ack_i; + 4'd2: wb_ack_o = s2_ack_i; + 4'd3: wb_ack_o = s3_ack_i; + 4'd4: wb_ack_o = s4_ack_i; + 4'd5: wb_ack_o = s5_ack_i; + 4'd6: wb_ack_o = s6_ack_i; + 4'd7: wb_ack_o = s7_ack_i; + 4'd8: wb_ack_o = s8_ack_i; + 4'd9: wb_ack_o = s9_ack_i; + 4'd10: wb_ack_o = s10_ack_i; + 4'd11: wb_ack_o = s11_ack_i; + 4'd12: wb_ack_o = s12_ack_i; + 4'd13: wb_ack_o = s13_ack_i; + 4'd14: wb_ack_o = s14_ack_i; + 4'd15: wb_ack_o = s15_ack_i; + default: wb_ack_o = 1'b0; + endcase + +always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or + s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or + s9_err_i or s10_err_i or s11_err_i or s12_err_i or + s13_err_i or s14_err_i or s15_err_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_err_o = s0_err_i; + 4'd1: wb_err_o = s1_err_i; + 4'd2: wb_err_o = s2_err_i; + 4'd3: wb_err_o = s3_err_i; + 4'd4: wb_err_o = s4_err_i; + 4'd5: wb_err_o = s5_err_i; + 4'd6: wb_err_o = s6_err_i; + 4'd7: wb_err_o = s7_err_i; + 4'd8: wb_err_o = s8_err_i; + 4'd9: wb_err_o = s9_err_i; + 4'd10: wb_err_o = s10_err_i; + 4'd11: wb_err_o = s11_err_i; + 4'd12: wb_err_o = s12_err_i; + 4'd13: wb_err_o = s13_err_i; + 4'd14: wb_err_o = s14_err_i; + 4'd15: wb_err_o = s15_err_i; + default: wb_err_o = 1'b0; + endcase + +always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or + s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or + s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or + s13_rty_i or s14_rty_i or s15_rty_i) + case(slv_sel) // synopsys parallel_case + 4'd0: wb_rty_o = s0_rty_i; + 4'd1: wb_rty_o = s1_rty_i; + 4'd2: wb_rty_o = s2_rty_i; + 4'd3: wb_rty_o = s3_rty_i; + 4'd4: wb_rty_o = s4_rty_i; + 4'd5: wb_rty_o = s5_rty_i; + 4'd6: wb_rty_o = s6_rty_i; + 4'd7: wb_rty_o = s7_rty_i; + 4'd8: wb_rty_o = s8_rty_i; + 4'd9: wb_rty_o = s9_rty_i; + 4'd10: wb_rty_o = s10_rty_i; + 4'd11: wb_rty_o = s11_rty_i; + 4'd12: wb_rty_o = s12_rty_i; + 4'd13: wb_rty_o = s13_rty_i; + 4'd14: wb_rty_o = s14_rty_i; + 4'd15: wb_rty_o = s15_rty_i; + default: wb_rty_o = 1'b0; + endcase + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_msel.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_msel.v new file mode 100644 index 000000000..7dd76759d --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_msel.v @@ -0,0 +1,246 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Master Select //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_msel.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_msel.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:38 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_msel( + clk_i, rst_i, + conf, req, sel, next + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; +input [15:0] conf; +input [7:0] req; +output [2:0] sel; +input next; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [1:0] pri0, pri1, pri2, pri3; +wire [1:0] pri4, pri5, pri6, pri7; +wire [1:0] pri_out_d; +reg [1:0] pri_out; + +wire [7:0] req_p0, req_p1, req_p2, req_p3; +wire [2:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; + +reg [2:0] sel1, sel2; +wire [2:0] sel; + +//////////////////////////////////////////////////////////////////// +// +// Priority Select logic +// + +assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0]; +assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0; + +assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2]; +assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0; + +assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4]; +assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0; + +assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6]; +assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0; + +assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8]; +assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0; + +assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10]; +assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0; + +assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12]; +assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0; + +assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14]; +assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0; + +// Priority Encoder +wb_conmax_pri_enc #(pri_sel) pri_enc( + .valid( req ), + .pri0( pri0 ), + .pri1( pri1 ), + .pri2( pri2 ), + .pri3( pri3 ), + .pri4( pri4 ), + .pri5( pri5 ), + .pri6( pri6 ), + .pri7( pri7 ), + .pri_out( pri_out_d ) + ); + +always @(posedge clk_i) + if(rst_i) pri_out <= #1 2'h0; + else + if(next) pri_out <= #1 pri_out_d; + +//////////////////////////////////////////////////////////////////// +// +// Arbiters +// + +assign req_p0[0] = req[0] & (pri0 == 2'd0); +assign req_p0[1] = req[1] & (pri1 == 2'd0); +assign req_p0[2] = req[2] & (pri2 == 2'd0); +assign req_p0[3] = req[3] & (pri3 == 2'd0); +assign req_p0[4] = req[4] & (pri4 == 2'd0); +assign req_p0[5] = req[5] & (pri5 == 2'd0); +assign req_p0[6] = req[6] & (pri6 == 2'd0); +assign req_p0[7] = req[7] & (pri7 == 2'd0); + +assign req_p1[0] = req[0] & (pri0 == 2'd1); +assign req_p1[1] = req[1] & (pri1 == 2'd1); +assign req_p1[2] = req[2] & (pri2 == 2'd1); +assign req_p1[3] = req[3] & (pri3 == 2'd1); +assign req_p1[4] = req[4] & (pri4 == 2'd1); +assign req_p1[5] = req[5] & (pri5 == 2'd1); +assign req_p1[6] = req[6] & (pri6 == 2'd1); +assign req_p1[7] = req[7] & (pri7 == 2'd1); + +assign req_p2[0] = req[0] & (pri0 == 2'd2); +assign req_p2[1] = req[1] & (pri1 == 2'd2); +assign req_p2[2] = req[2] & (pri2 == 2'd2); +assign req_p2[3] = req[3] & (pri3 == 2'd2); +assign req_p2[4] = req[4] & (pri4 == 2'd2); +assign req_p2[5] = req[5] & (pri5 == 2'd2); +assign req_p2[6] = req[6] & (pri6 == 2'd2); +assign req_p2[7] = req[7] & (pri7 == 2'd2); + +assign req_p3[0] = req[0] & (pri0 == 2'd3); +assign req_p3[1] = req[1] & (pri1 == 2'd3); +assign req_p3[2] = req[2] & (pri2 == 2'd3); +assign req_p3[3] = req[3] & (pri3 == 2'd3); +assign req_p3[4] = req[4] & (pri4 == 2'd3); +assign req_p3[5] = req[5] & (pri5 == 2'd3); +assign req_p3[6] = req[6] & (pri6 == 2'd3); +assign req_p3[7] = req[7] & (pri7 == 2'd3); + +wb_conmax_arb arb0( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p0 ), + .gnt( gnt_p0 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb1( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p1 ), + .gnt( gnt_p1 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb2( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p2 ), + .gnt( gnt_p2 ), + .next( 1'b0 ) + ); + +wb_conmax_arb arb3( + .clk( clk_i ), + .rst( rst_i ), + .req( req_p3 ), + .gnt( gnt_p3 ), + .next( 1'b0 ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Final Master Select +// + +always @(pri_out or gnt_p0 or gnt_p1) + if(pri_out[0]) sel1 = gnt_p1; + else sel1 = gnt_p0; + + +always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3) + case(pri_out) + 2'd0: sel2 = gnt_p0; + 2'd1: sel2 = gnt_p1; + 2'd2: sel2 = gnt_p2; + 2'd3: sel2 = gnt_p3; + endcase + + +assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 ); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_dec.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_dec.v new file mode 100644 index 000000000..585c28077 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_dec.v @@ -0,0 +1,119 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Priority Decoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_pri_dec.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_pri_dec.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:42 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_pri_dec(valid, pri_in, pri_out); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input valid; +input [1:0] pri_in; +output [3:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [3:0] pri_out; +reg [3:0] pri_out_d0; +reg [3:0] pri_out_d1; + +//////////////////////////////////////////////////////////////////// +// +// Priority Decoder +// + +// 4 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d1 = 4'b0001; + else + if(pri_in==2'h0) pri_out_d1 = 4'b0001; + else + if(pri_in==2'h1) pri_out_d1 = 4'b0010; + else + if(pri_in==2'h2) pri_out_d1 = 4'b0100; + else pri_out_d1 = 4'b1000; + +// 2 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d0 = 4'b0001; + else + if(pri_in==2'h0) pri_out_d0 = 4'b0001; + else pri_out_d0 = 4'b0010; + +// Select Configured Priority + +assign pri_out = (pri_sel==2'd0) ? 4'h0 : ( (pri_sel==1'd1) ? pri_out_d0 : pri_out_d1 ); + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_enc.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_enc.v new file mode 100644 index 000000000..6b688f6b6 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_pri_enc.v @@ -0,0 +1,186 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Priority Encoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_pri_enc.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_pri_enc.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:41 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_pri_enc( + valid, + pri0, pri1, pri2, pri3, + pri4, pri5, pri6, pri7, + pri_out + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input [7:0] valid; +input [1:0] pri0, pri1, pri2, pri3; +input [1:0] pri4, pri5, pri6, pri7; +output [1:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out; +wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out; +wire [3:0] pri_out_tmp; +reg [1:0] pri_out0, pri_out1; +wire [1:0] pri_out; + +//////////////////////////////////////////////////////////////////// +// +// Priority Decoders +// + +wb_conmax_pri_dec #(pri_sel) pd0( + .valid( valid[0] ), + .pri_in( pri0 ), + .pri_out( pri0_out ) + ); + + +wb_conmax_pri_dec #(pri_sel) pd1( + .valid( valid[1] ), + .pri_in( pri1 ), + .pri_out( pri1_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd2( + .valid( valid[2] ), + .pri_in( pri2 ), + .pri_out( pri2_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd3( + .valid( valid[3] ), + .pri_in( pri3 ), + .pri_out( pri3_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd4( + .valid( valid[4] ), + .pri_in( pri4 ), + .pri_out( pri4_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd5( + .valid( valid[5] ), + .pri_in( pri5 ), + .pri_out( pri5_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd6( + .valid( valid[6] ), + .pri_in( pri6 ), + .pri_out( pri6_out ) + ); + +wb_conmax_pri_dec #(pri_sel) pd7( + .valid( valid[7] ), + .pri_in( pri7 ), + .pri_out( pri7_out ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Priority Encoding +// + +assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | + pri4_out | pri5_out | pri6_out | pri7_out; + +// 4 Priority Levels +always @(pri_out_tmp) + if(pri_out_tmp[3]) pri_out1 = 2'h3; + else + if(pri_out_tmp[2]) pri_out1 = 2'h2; + else + if(pri_out_tmp[1]) pri_out1 = 2'h1; + else pri_out1 = 2'h0; + +// 2 Priority Levels +always @(pri_out_tmp) + if(pri_out_tmp[1]) pri_out0 = 2'h1; + else pri_out0 = 2'h0; + +//////////////////////////////////////////////////////////////////// +// +// Final Priority Output +// + +// Select configured priority + +assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 ); + +endmodule + + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_rf.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_rf.v new file mode 100644 index 000000000..4d76d9075 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_rf.v @@ -0,0 +1,311 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_rf.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_rf.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:42 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_rf( + clk_i, rst_i, + + // Internal Wishbone Interface + i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i, + i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o, + + // External Wishbone Interface + e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o, + e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i, + + // Configuration Registers + conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7, + conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15 + + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [3:0] rf_addr = 4'hf; +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Internal Wishbone Interface +input [dw-1:0] i_wb_data_i; +output [dw-1:0] i_wb_data_o; +input [aw-1:0] i_wb_addr_i; +input [sw-1:0] i_wb_sel_i; +input i_wb_we_i; +input i_wb_cyc_i; +input i_wb_stb_i; +output i_wb_ack_o; +output i_wb_err_o; +output i_wb_rty_o; + +// External Wishbone Interface +input [dw-1:0] e_wb_data_i; +output [dw-1:0] e_wb_data_o; +output [aw-1:0] e_wb_addr_o; +output [sw-1:0] e_wb_sel_o; +output e_wb_we_o; +output e_wb_cyc_o; +output e_wb_stb_o; +input e_wb_ack_i; +input e_wb_err_i; +input e_wb_rty_i; + +// Configuration Registers +output [15:0] conf0; +output [15:0] conf1; +output [15:0] conf2; +output [15:0] conf3; +output [15:0] conf4; +output [15:0] conf5; +output [15:0] conf6; +output [15:0] conf7; +output [15:0] conf8; +output [15:0] conf9; +output [15:0] conf10; +output [15:0] conf11; +output [15:0] conf12; +output [15:0] conf13; +output [15:0] conf14; +output [15:0] conf15; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5; +reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11; +reg [15:0] conf12, conf13, conf14, conf15; + +//synopsys infer_multibit "conf0" +//synopsys infer_multibit "conf1" +//synopsys infer_multibit "conf2" +//synopsys infer_multibit "conf3" +//synopsys infer_multibit "conf4" +//synopsys infer_multibit "conf5" +//synopsys infer_multibit "conf6" +//synopsys infer_multibit "conf7" +//synopsys infer_multibit "conf8" +//synopsys infer_multibit "conf9" +//synopsys infer_multibit "conf10" +//synopsys infer_multibit "conf11" +//synopsys infer_multibit "conf12" +//synopsys infer_multibit "conf13" +//synopsys infer_multibit "conf14" +//synopsys infer_multibit "conf15" + +wire rf_sel; +reg [15:0] rf_dout; +reg rf_ack; +reg rf_we; + +//////////////////////////////////////////////////////////////////// +// +// Register File Select Logic +// + +assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr); + +//////////////////////////////////////////////////////////////////// +// +// Register File Logic +// + +always @(posedge clk_i) + rf_we <= #1 rf_sel & i_wb_we_i & !rf_we; + +always @(posedge clk_i) + rf_ack <= #1 rf_sel & !rf_ack; + +// Writre Logic +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf0 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf1 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf2 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf3 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf4 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf5 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf6 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf7 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf8 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf9 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf10 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf11 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf12 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf13 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf14 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0]; + +always @(posedge clk_i or posedge rst_i) + if(rst_i) conf15 <= #1 16'h0; + else + if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0]; + +// Read Logic +always @(posedge clk_i) + if(!rf_sel) rf_dout <= #1 16'h0; + else + case(i_wb_addr_i[5:2]) + 4'd0: rf_dout <= #1 conf0; + 4'd1: rf_dout <= #1 conf1; + 4'd2: rf_dout <= #1 conf2; + 4'd3: rf_dout <= #1 conf3; + 4'd4: rf_dout <= #1 conf4; + 4'd5: rf_dout <= #1 conf5; + 4'd6: rf_dout <= #1 conf6; + 4'd7: rf_dout <= #1 conf7; + 4'd8: rf_dout <= #1 conf8; + 4'd9: rf_dout <= #1 conf9; + 4'd10: rf_dout <= #1 conf10; + 4'd11: rf_dout <= #1 conf11; + 4'd12: rf_dout <= #1 conf12; + 4'd13: rf_dout <= #1 conf13; + 4'd14: rf_dout <= #1 conf14; + 4'd15: rf_dout <= #1 conf15; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Register File By-Pass Logic +// + +assign e_wb_addr_o = i_wb_addr_i; +assign e_wb_sel_o = i_wb_sel_i; +assign e_wb_data_o = i_wb_data_i; + +assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i; +assign e_wb_stb_o = i_wb_stb_i; +assign e_wb_we_o = i_wb_we_i; + +assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i; +assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i; +assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i; +assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_slave_if.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_slave_if.v new file mode 100644 index 000000000..788d088ac --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_slave_if.v @@ -0,0 +1,449 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Slave Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_slave_if.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_slave_if.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:39 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_slave_if( + + clk_i, rst_i, conf, + + // Slave interface + wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + // Master 0 Interface + m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, + + // Master 1 Interface + m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, + + // Master 2 Interface + m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, + + // Master 3 Interface + m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, + + // Master 4 Interface + m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, + + // Master 5 Interface + m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, + + // Master 6 Interface + m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, + + // Master 7 Interface + m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter [1:0] pri_sel = 2'd2; +parameter aw = 32; // Address bus Width +parameter dw = 32; // Data bus Width +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; +input [15:0] conf; + +// Slave Interface +input [dw-1:0] wb_data_i; +output [dw-1:0] wb_data_o; +output [aw-1:0] wb_addr_o; +output [sw-1:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// Master 0 Interface +input [dw-1:0] m0_data_i; +output [dw-1:0] m0_data_o; +input [aw-1:0] m0_addr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_data_i; +output [dw-1:0] m1_data_o; +input [aw-1:0] m1_addr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_data_i; +output [dw-1:0] m2_data_o; +input [aw-1:0] m2_addr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_data_i; +output [dw-1:0] m3_data_o; +input [aw-1:0] m3_addr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_data_i; +output [dw-1:0] m4_data_o; +input [aw-1:0] m4_addr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_data_i; +output [dw-1:0] m5_data_o; +input [aw-1:0] m5_addr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_data_i; +output [dw-1:0] m6_data_o; +input [aw-1:0] m6_addr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_data_i; +output [dw-1:0] m7_data_o; +input [aw-1:0] m7_addr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [aw-1:0] wb_addr_o; +reg [dw-1:0] wb_data_o; +reg [sw-1:0] wb_sel_o; +reg wb_we_o; +reg wb_cyc_o; +reg wb_stb_o; +wire [2:0] mast_sel_simple; +wire [2:0] mast_sel_pe; +wire [2:0] mast_sel; + +reg next; +reg m0_cyc_r, m1_cyc_r, m2_cyc_r, m3_cyc_r; +reg m4_cyc_r, m5_cyc_r, m6_cyc_r, m7_cyc_r; + +//////////////////////////////////////////////////////////////////// +// +// Select logic +// + +always @(posedge clk_i) + next <= #1 ~wb_cyc_o; + + +wb_conmax_arb arb( + .clk( clk_i ), + .rst( rst_i ), + .req( { m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i } ), + .gnt( mast_sel_simple ), + .next( 1'b0 ) + ); + +wb_conmax_msel #(pri_sel) msel( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf ), + .req( { m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i} ), + .sel( mast_sel_pe ), + .next( next ) + ); + +assign mast_sel = (pri_sel == 2'd0) ? mast_sel_simple : mast_sel_pe; + +//////////////////////////////////////////////////////////////////// +// +// Address & Data Pass +// + +always @(mast_sel or m0_addr_i or m1_addr_i or m2_addr_i or m3_addr_i + or m4_addr_i or m5_addr_i or m6_addr_i or m7_addr_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_addr_o = m0_addr_i; + 3'd1: wb_addr_o = m1_addr_i; + 3'd2: wb_addr_o = m2_addr_i; + 3'd3: wb_addr_o = m3_addr_i; + 3'd4: wb_addr_o = m4_addr_i; + 3'd5: wb_addr_o = m5_addr_i; + 3'd6: wb_addr_o = m6_addr_i; + 3'd7: wb_addr_o = m7_addr_i; + default: wb_addr_o = {aw{1'bx}}; + endcase + +always @(mast_sel or m0_sel_i or m1_sel_i or m2_sel_i or m3_sel_i + or m4_sel_i or m5_sel_i or m6_sel_i or m7_sel_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_sel_o = m0_sel_i; + 3'd1: wb_sel_o = m1_sel_i; + 3'd2: wb_sel_o = m2_sel_i; + 3'd3: wb_sel_o = m3_sel_i; + 3'd4: wb_sel_o = m4_sel_i; + 3'd5: wb_sel_o = m5_sel_i; + 3'd6: wb_sel_o = m6_sel_i; + 3'd7: wb_sel_o = m7_sel_i; + default: wb_sel_o = {sw{1'bx}}; + endcase + +always @(mast_sel or m0_data_i or m1_data_i or m2_data_i or m3_data_i + or m4_data_i or m5_data_i or m6_data_i or m7_data_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_data_o = m0_data_i; + 3'd1: wb_data_o = m1_data_i; + 3'd2: wb_data_o = m2_data_i; + 3'd3: wb_data_o = m3_data_i; + 3'd4: wb_data_o = m4_data_i; + 3'd5: wb_data_o = m5_data_i; + 3'd6: wb_data_o = m6_data_i; + 3'd7: wb_data_o = m7_data_i; + default: wb_data_o = {dw{1'bx}}; + endcase + +assign m0_data_o = wb_data_i; +assign m1_data_o = wb_data_i; +assign m2_data_o = wb_data_i; +assign m3_data_o = wb_data_i; +assign m4_data_o = wb_data_i; +assign m5_data_o = wb_data_i; +assign m6_data_o = wb_data_i; +assign m7_data_o = wb_data_i; + +//////////////////////////////////////////////////////////////////// +// +// Control Signal Pass +// + +always @(mast_sel or m0_we_i or m1_we_i or m2_we_i or m3_we_i + or m4_we_i or m5_we_i or m6_we_i or m7_we_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_we_o = m0_we_i; + 3'd1: wb_we_o = m1_we_i; + 3'd2: wb_we_o = m2_we_i; + 3'd3: wb_we_o = m3_we_i; + 3'd4: wb_we_o = m4_we_i; + 3'd5: wb_we_o = m5_we_i; + 3'd6: wb_we_o = m6_we_i; + 3'd7: wb_we_o = m7_we_i; + default: wb_we_o = 1'bx; + endcase + +always @(posedge clk_i) + m0_cyc_r <= #1 m0_cyc_i; + +always @(posedge clk_i) + m1_cyc_r <= #1 m1_cyc_i; + +always @(posedge clk_i) + m2_cyc_r <= #1 m2_cyc_i; + +always @(posedge clk_i) + m3_cyc_r <= #1 m3_cyc_i; + +always @(posedge clk_i) + m4_cyc_r <= #1 m4_cyc_i; + +always @(posedge clk_i) + m5_cyc_r <= #1 m5_cyc_i; + +always @(posedge clk_i) + m6_cyc_r <= #1 m6_cyc_i; + +always @(posedge clk_i) + m7_cyc_r <= #1 m7_cyc_i; + +always @(mast_sel or m0_cyc_i or m1_cyc_i or m2_cyc_i or m3_cyc_i + or m4_cyc_i or m5_cyc_i or m6_cyc_i or m7_cyc_i + or m0_cyc_r or m1_cyc_r or m2_cyc_r or m3_cyc_r + or m4_cyc_r or m5_cyc_r or m6_cyc_r or m7_cyc_r) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_cyc_o = m0_cyc_i & m0_cyc_r; + 3'd1: wb_cyc_o = m1_cyc_i & m1_cyc_r; + 3'd2: wb_cyc_o = m2_cyc_i & m2_cyc_r; + 3'd3: wb_cyc_o = m3_cyc_i & m3_cyc_r; + 3'd4: wb_cyc_o = m4_cyc_i & m4_cyc_r; + 3'd5: wb_cyc_o = m5_cyc_i & m5_cyc_r; + 3'd6: wb_cyc_o = m6_cyc_i & m6_cyc_r; + 3'd7: wb_cyc_o = m7_cyc_i & m7_cyc_r; + default: wb_cyc_o = 1'b0; + endcase + +always @(mast_sel or m0_stb_i or m1_stb_i or m2_stb_i or m3_stb_i + or m4_stb_i or m5_stb_i or m6_stb_i or m7_stb_i) + case(mast_sel) // synopsys parallel_case + 3'd0: wb_stb_o = m0_stb_i; + 3'd1: wb_stb_o = m1_stb_i; + 3'd2: wb_stb_o = m2_stb_i; + 3'd3: wb_stb_o = m3_stb_i; + 3'd4: wb_stb_o = m4_stb_i; + 3'd5: wb_stb_o = m5_stb_i; + 3'd6: wb_stb_o = m6_stb_i; + 3'd7: wb_stb_o = m7_stb_i; + default: wb_stb_o = 1'b0; + endcase + +assign m0_ack_o = (mast_sel==3'd0) & wb_ack_i; +assign m1_ack_o = (mast_sel==3'd1) & wb_ack_i; +assign m2_ack_o = (mast_sel==3'd2) & wb_ack_i; +assign m3_ack_o = (mast_sel==3'd3) & wb_ack_i; +assign m4_ack_o = (mast_sel==3'd4) & wb_ack_i; +assign m5_ack_o = (mast_sel==3'd5) & wb_ack_i; +assign m6_ack_o = (mast_sel==3'd6) & wb_ack_i; +assign m7_ack_o = (mast_sel==3'd7) & wb_ack_i; + +assign m0_err_o = (mast_sel==3'd0) & wb_err_i; +assign m1_err_o = (mast_sel==3'd1) & wb_err_i; +assign m2_err_o = (mast_sel==3'd2) & wb_err_i; +assign m3_err_o = (mast_sel==3'd3) & wb_err_i; +assign m4_err_o = (mast_sel==3'd4) & wb_err_i; +assign m5_err_o = (mast_sel==3'd5) & wb_err_i; +assign m6_err_o = (mast_sel==3'd6) & wb_err_i; +assign m7_err_o = (mast_sel==3'd7) & wb_err_i; + +assign m0_rty_o = (mast_sel==3'd0) & wb_rty_i; +assign m1_rty_o = (mast_sel==3'd1) & wb_rty_i; +assign m2_rty_o = (mast_sel==3'd2) & wb_rty_i; +assign m3_rty_o = (mast_sel==3'd3) & wb_rty_i; +assign m4_rty_o = (mast_sel==3'd4) & wb_rty_i; +assign m5_rty_o = (mast_sel==3'd5) & wb_rty_i; +assign m6_rty_o = (mast_sel==3'd6) & wb_rty_i; +assign m7_rty_o = (mast_sel==3'd7) & wb_rty_i; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_top.v b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_top.v new file mode 100644 index 000000000..524d5eb08 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/wb_conmax_top.v @@ -0,0 +1,4806 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_conmax_top.v,v 1.2 2002/10/03 05:40:07 rudi Exp $ +// +// $Date: 2002/10/03 05:40:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_conmax_top.v,v $ +// Revision 1.2 2002/10/03 05:40:07 rudi +// Fixed a minor bug in parameter passing, updated headers and specification. +// +// Revision 1.1.1.1 2001/10/19 11:01:38 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// + +`include "wb_conmax_defines.v" + +module wb_conmax_top( + clk_i, rst_i, + + // Master 0 Interface + m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, + + // Master 1 Interface + m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, + + // Master 2 Interface + m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, + + // Master 3 Interface + m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, + + // Master 4 Interface + m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, + + // Master 5 Interface + m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, + + // Master 6 Interface + m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, + + // Master 7 Interface + m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, + + // Slave 0 Interface + s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, + + // Slave 1 Interface + s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, + + // Slave 2 Interface + s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, + + // Slave 3 Interface + s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, + + // Slave 4 Interface + s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, + + // Slave 5 Interface + s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, + + // Slave 6 Interface + s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, + + // Slave 7 Interface + s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, + + // Slave 8 Interface + s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o, + s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i, + + // Slave 9 Interface + s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o, + s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i, + + // Slave 10 Interface + s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o, + s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i, + + // Slave 11 Interface + s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o, + s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i, + + // Slave 12 Interface + s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o, + s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i, + + // Slave 13 Interface + s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o, + s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i, + + // Slave 14 Interface + s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o, + s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i, + + // Slave 15 Interface + s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o, + s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +parameter dw = 32; // Data bus Width +parameter aw = 32; // Address bus Width +parameter [3:0] rf_addr = 4'hf; +parameter [1:0] pri_sel0 = 2'd2; +parameter [1:0] pri_sel1 = 2'd2; +parameter [1:0] pri_sel2 = 2'd2; +parameter [1:0] pri_sel3 = 2'd2; +parameter [1:0] pri_sel4 = 2'd2; +parameter [1:0] pri_sel5 = 2'd2; +parameter [1:0] pri_sel6 = 2'd2; +parameter [1:0] pri_sel7 = 2'd2; +parameter [1:0] pri_sel8 = 2'd2; +parameter [1:0] pri_sel9 = 2'd2; +parameter [1:0] pri_sel10 = 2'd2; +parameter [1:0] pri_sel11 = 2'd2; +parameter [1:0] pri_sel12 = 2'd2; +parameter [1:0] pri_sel13 = 2'd2; +parameter [1:0] pri_sel14 = 2'd2; +parameter [1:0] pri_sel15 = 2'd2; + +parameter sw = dw / 8; // Number of Select Lines + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Master 0 Interface +input [dw-1:0] m0_data_i; +output [dw-1:0] m0_data_o; +input [aw-1:0] m0_addr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_data_i; +output [dw-1:0] m1_data_o; +input [aw-1:0] m1_addr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_data_i; +output [dw-1:0] m2_data_o; +input [aw-1:0] m2_addr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_data_i; +output [dw-1:0] m3_data_o; +input [aw-1:0] m3_addr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_data_i; +output [dw-1:0] m4_data_o; +input [aw-1:0] m4_addr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_data_i; +output [dw-1:0] m5_data_o; +input [aw-1:0] m5_addr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_data_i; +output [dw-1:0] m6_data_o; +input [aw-1:0] m6_addr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_data_i; +output [dw-1:0] m7_data_o; +input [aw-1:0] m7_addr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_data_i; +output [dw-1:0] s0_data_o; +output [aw-1:0] s0_addr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_data_i; +output [dw-1:0] s1_data_o; +output [aw-1:0] s1_addr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_data_i; +output [dw-1:0] s2_data_o; +output [aw-1:0] s2_addr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_data_i; +output [dw-1:0] s3_data_o; +output [aw-1:0] s3_addr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_data_i; +output [dw-1:0] s4_data_o; +output [aw-1:0] s4_addr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_data_i; +output [dw-1:0] s5_data_o; +output [aw-1:0] s5_addr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_data_i; +output [dw-1:0] s6_data_o; +output [aw-1:0] s6_addr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_data_i; +output [dw-1:0] s7_data_o; +output [aw-1:0] s7_addr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + +// Slave 8 Interface +input [dw-1:0] s8_data_i; +output [dw-1:0] s8_data_o; +output [aw-1:0] s8_addr_o; +output [sw-1:0] s8_sel_o; +output s8_we_o; +output s8_cyc_o; +output s8_stb_o; +input s8_ack_i; +input s8_err_i; +input s8_rty_i; + +// Slave 9 Interface +input [dw-1:0] s9_data_i; +output [dw-1:0] s9_data_o; +output [aw-1:0] s9_addr_o; +output [sw-1:0] s9_sel_o; +output s9_we_o; +output s9_cyc_o; +output s9_stb_o; +input s9_ack_i; +input s9_err_i; +input s9_rty_i; + +// Slave 10 Interface +input [dw-1:0] s10_data_i; +output [dw-1:0] s10_data_o; +output [aw-1:0] s10_addr_o; +output [sw-1:0] s10_sel_o; +output s10_we_o; +output s10_cyc_o; +output s10_stb_o; +input s10_ack_i; +input s10_err_i; +input s10_rty_i; + +// Slave 11 Interface +input [dw-1:0] s11_data_i; +output [dw-1:0] s11_data_o; +output [aw-1:0] s11_addr_o; +output [sw-1:0] s11_sel_o; +output s11_we_o; +output s11_cyc_o; +output s11_stb_o; +input s11_ack_i; +input s11_err_i; +input s11_rty_i; + +// Slave 12 Interface +input [dw-1:0] s12_data_i; +output [dw-1:0] s12_data_o; +output [aw-1:0] s12_addr_o; +output [sw-1:0] s12_sel_o; +output s12_we_o; +output s12_cyc_o; +output s12_stb_o; +input s12_ack_i; +input s12_err_i; +input s12_rty_i; + +// Slave 13 Interface +input [dw-1:0] s13_data_i; +output [dw-1:0] s13_data_o; +output [aw-1:0] s13_addr_o; +output [sw-1:0] s13_sel_o; +output s13_we_o; +output s13_cyc_o; +output s13_stb_o; +input s13_ack_i; +input s13_err_i; +input s13_rty_i; + +// Slave 14 Interface +input [dw-1:0] s14_data_i; +output [dw-1:0] s14_data_o; +output [aw-1:0] s14_addr_o; +output [sw-1:0] s14_sel_o; +output s14_we_o; +output s14_cyc_o; +output s14_stb_o; +input s14_ack_i; +input s14_err_i; +input s14_rty_i; + +// Slave 15 Interface +input [dw-1:0] s15_data_i; +output [dw-1:0] s15_data_o; +output [aw-1:0] s15_addr_o; +output [sw-1:0] s15_sel_o; +output s15_we_o; +output s15_cyc_o; +output s15_stb_o; +input s15_ack_i; +input s15_err_i; +input s15_rty_i; + +//////////////////////////////////////////////////////////////////// +// +// Local wires +// + +wire [dw-1:0] i_s15_data_i; +wire [dw-1:0] i_s15_data_o; +wire [aw-1:0] i_s15_addr_o; +wire [sw-1:0] i_s15_sel_o; +wire i_s15_we_o; +wire i_s15_cyc_o; +wire i_s15_stb_o; +wire i_s15_ack_i; +wire i_s15_err_i; +wire i_s15_rty_i; + +wire [dw-1:0] m0s0_data_i; +wire [dw-1:0] m0s0_data_o; +wire [aw-1:0] m0s0_addr; +wire [sw-1:0] m0s0_sel; +wire m0s0_we; +wire m0s0_cyc; +wire m0s0_stb; +wire m0s0_ack; +wire m0s0_err; +wire m0s0_rty; +wire [dw-1:0] m0s1_data_i; +wire [dw-1:0] m0s1_data_o; +wire [aw-1:0] m0s1_addr; +wire [sw-1:0] m0s1_sel; +wire m0s1_we; +wire m0s1_cyc; +wire m0s1_stb; +wire m0s1_ack; +wire m0s1_err; +wire m0s1_rty; +wire [dw-1:0] m0s2_data_i; +wire [dw-1:0] m0s2_data_o; +wire [aw-1:0] m0s2_addr; +wire [sw-1:0] m0s2_sel; +wire m0s2_we; +wire m0s2_cyc; +wire m0s2_stb; +wire m0s2_ack; +wire m0s2_err; +wire m0s2_rty; +wire [dw-1:0] m0s3_data_i; +wire [dw-1:0] m0s3_data_o; +wire [aw-1:0] m0s3_addr; +wire [sw-1:0] m0s3_sel; +wire m0s3_we; +wire m0s3_cyc; +wire m0s3_stb; +wire m0s3_ack; +wire m0s3_err; +wire m0s3_rty; +wire [dw-1:0] m0s4_data_i; +wire [dw-1:0] m0s4_data_o; +wire [aw-1:0] m0s4_addr; +wire [sw-1:0] m0s4_sel; +wire m0s4_we; +wire m0s4_cyc; +wire m0s4_stb; +wire m0s4_ack; +wire m0s4_err; +wire m0s4_rty; +wire [dw-1:0] m0s5_data_i; +wire [dw-1:0] m0s5_data_o; +wire [aw-1:0] m0s5_addr; +wire [sw-1:0] m0s5_sel; +wire m0s5_we; +wire m0s5_cyc; +wire m0s5_stb; +wire m0s5_ack; +wire m0s5_err; +wire m0s5_rty; +wire [dw-1:0] m0s6_data_i; +wire [dw-1:0] m0s6_data_o; +wire [aw-1:0] m0s6_addr; +wire [sw-1:0] m0s6_sel; +wire m0s6_we; +wire m0s6_cyc; +wire m0s6_stb; +wire m0s6_ack; +wire m0s6_err; +wire m0s6_rty; +wire [dw-1:0] m0s7_data_i; +wire [dw-1:0] m0s7_data_o; +wire [aw-1:0] m0s7_addr; +wire [sw-1:0] m0s7_sel; +wire m0s7_we; +wire m0s7_cyc; +wire m0s7_stb; +wire m0s7_ack; +wire m0s7_err; +wire m0s7_rty; +wire [dw-1:0] m0s8_data_i; +wire [dw-1:0] m0s8_data_o; +wire [aw-1:0] m0s8_addr; +wire [sw-1:0] m0s8_sel; +wire m0s8_we; +wire m0s8_cyc; +wire m0s8_stb; +wire m0s8_ack; +wire m0s8_err; +wire m0s8_rty; +wire [dw-1:0] m0s9_data_i; +wire [dw-1:0] m0s9_data_o; +wire [aw-1:0] m0s9_addr; +wire [sw-1:0] m0s9_sel; +wire m0s9_we; +wire m0s9_cyc; +wire m0s9_stb; +wire m0s9_ack; +wire m0s9_err; +wire m0s9_rty; +wire [dw-1:0] m0s10_data_i; +wire [dw-1:0] m0s10_data_o; +wire [aw-1:0] m0s10_addr; +wire [sw-1:0] m0s10_sel; +wire m0s10_we; +wire m0s10_cyc; +wire m0s10_stb; +wire m0s10_ack; +wire m0s10_err; +wire m0s10_rty; +wire [dw-1:0] m0s11_data_i; +wire [dw-1:0] m0s11_data_o; +wire [aw-1:0] m0s11_addr; +wire [sw-1:0] m0s11_sel; +wire m0s11_we; +wire m0s11_cyc; +wire m0s11_stb; +wire m0s11_ack; +wire m0s11_err; +wire m0s11_rty; +wire [dw-1:0] m0s12_data_i; +wire [dw-1:0] m0s12_data_o; +wire [aw-1:0] m0s12_addr; +wire [sw-1:0] m0s12_sel; +wire m0s12_we; +wire m0s12_cyc; +wire m0s12_stb; +wire m0s12_ack; +wire m0s12_err; +wire m0s12_rty; +wire [dw-1:0] m0s13_data_i; +wire [dw-1:0] m0s13_data_o; +wire [aw-1:0] m0s13_addr; +wire [sw-1:0] m0s13_sel; +wire m0s13_we; +wire m0s13_cyc; +wire m0s13_stb; +wire m0s13_ack; +wire m0s13_err; +wire m0s13_rty; +wire [dw-1:0] m0s14_data_i; +wire [dw-1:0] m0s14_data_o; +wire [aw-1:0] m0s14_addr; +wire [sw-1:0] m0s14_sel; +wire m0s14_we; +wire m0s14_cyc; +wire m0s14_stb; +wire m0s14_ack; +wire m0s14_err; +wire m0s14_rty; +wire [dw-1:0] m0s15_data_i; +wire [dw-1:0] m0s15_data_o; +wire [aw-1:0] m0s15_addr; +wire [sw-1:0] m0s15_sel; +wire m0s15_we; +wire m0s15_cyc; +wire m0s15_stb; +wire m0s15_ack; +wire m0s15_err; +wire m0s15_rty; +wire [dw-1:0] m1s0_data_i; +wire [dw-1:0] m1s0_data_o; +wire [aw-1:0] m1s0_addr; +wire [sw-1:0] m1s0_sel; +wire m1s0_we; +wire m1s0_cyc; +wire m1s0_stb; +wire m1s0_ack; +wire m1s0_err; +wire m1s0_rty; +wire [dw-1:0] m1s1_data_i; +wire [dw-1:0] m1s1_data_o; +wire [aw-1:0] m1s1_addr; +wire [sw-1:0] m1s1_sel; +wire m1s1_we; +wire m1s1_cyc; +wire m1s1_stb; +wire m1s1_ack; +wire m1s1_err; +wire m1s1_rty; +wire [dw-1:0] m1s2_data_i; +wire [dw-1:0] m1s2_data_o; +wire [aw-1:0] m1s2_addr; +wire [sw-1:0] m1s2_sel; +wire m1s2_we; +wire m1s2_cyc; +wire m1s2_stb; +wire m1s2_ack; +wire m1s2_err; +wire m1s2_rty; +wire [dw-1:0] m1s3_data_i; +wire [dw-1:0] m1s3_data_o; +wire [aw-1:0] m1s3_addr; +wire [sw-1:0] m1s3_sel; +wire m1s3_we; +wire m1s3_cyc; +wire m1s3_stb; +wire m1s3_ack; +wire m1s3_err; +wire m1s3_rty; +wire [dw-1:0] m1s4_data_i; +wire [dw-1:0] m1s4_data_o; +wire [aw-1:0] m1s4_addr; +wire [sw-1:0] m1s4_sel; +wire m1s4_we; +wire m1s4_cyc; +wire m1s4_stb; +wire m1s4_ack; +wire m1s4_err; +wire m1s4_rty; +wire [dw-1:0] m1s5_data_i; +wire [dw-1:0] m1s5_data_o; +wire [aw-1:0] m1s5_addr; +wire [sw-1:0] m1s5_sel; +wire m1s5_we; +wire m1s5_cyc; +wire m1s5_stb; +wire m1s5_ack; +wire m1s5_err; +wire m1s5_rty; +wire [dw-1:0] m1s6_data_i; +wire [dw-1:0] m1s6_data_o; +wire [aw-1:0] m1s6_addr; +wire [sw-1:0] m1s6_sel; +wire m1s6_we; +wire m1s6_cyc; +wire m1s6_stb; +wire m1s6_ack; +wire m1s6_err; +wire m1s6_rty; +wire [dw-1:0] m1s7_data_i; +wire [dw-1:0] m1s7_data_o; +wire [aw-1:0] m1s7_addr; +wire [sw-1:0] m1s7_sel; +wire m1s7_we; +wire m1s7_cyc; +wire m1s7_stb; +wire m1s7_ack; +wire m1s7_err; +wire m1s7_rty; +wire [dw-1:0] m1s8_data_i; +wire [dw-1:0] m1s8_data_o; +wire [aw-1:0] m1s8_addr; +wire [sw-1:0] m1s8_sel; +wire m1s8_we; +wire m1s8_cyc; +wire m1s8_stb; +wire m1s8_ack; +wire m1s8_err; +wire m1s8_rty; +wire [dw-1:0] m1s9_data_i; +wire [dw-1:0] m1s9_data_o; +wire [aw-1:0] m1s9_addr; +wire [sw-1:0] m1s9_sel; +wire m1s9_we; +wire m1s9_cyc; +wire m1s9_stb; +wire m1s9_ack; +wire m1s9_err; +wire m1s9_rty; +wire [dw-1:0] m1s10_data_i; +wire [dw-1:0] m1s10_data_o; +wire [aw-1:0] m1s10_addr; +wire [sw-1:0] m1s10_sel; +wire m1s10_we; +wire m1s10_cyc; +wire m1s10_stb; +wire m1s10_ack; +wire m1s10_err; +wire m1s10_rty; +wire [dw-1:0] m1s11_data_i; +wire [dw-1:0] m1s11_data_o; +wire [aw-1:0] m1s11_addr; +wire [sw-1:0] m1s11_sel; +wire m1s11_we; +wire m1s11_cyc; +wire m1s11_stb; +wire m1s11_ack; +wire m1s11_err; +wire m1s11_rty; +wire [dw-1:0] m1s12_data_i; +wire [dw-1:0] m1s12_data_o; +wire [aw-1:0] m1s12_addr; +wire [sw-1:0] m1s12_sel; +wire m1s12_we; +wire m1s12_cyc; +wire m1s12_stb; +wire m1s12_ack; +wire m1s12_err; +wire m1s12_rty; +wire [dw-1:0] m1s13_data_i; +wire [dw-1:0] m1s13_data_o; +wire [aw-1:0] m1s13_addr; +wire [sw-1:0] m1s13_sel; +wire m1s13_we; +wire m1s13_cyc; +wire m1s13_stb; +wire m1s13_ack; +wire m1s13_err; +wire m1s13_rty; +wire [dw-1:0] m1s14_data_i; +wire [dw-1:0] m1s14_data_o; +wire [aw-1:0] m1s14_addr; +wire [sw-1:0] m1s14_sel; +wire m1s14_we; +wire m1s14_cyc; +wire m1s14_stb; +wire m1s14_ack; +wire m1s14_err; +wire m1s14_rty; +wire [dw-1:0] m1s15_data_i; +wire [dw-1:0] m1s15_data_o; +wire [aw-1:0] m1s15_addr; +wire [sw-1:0] m1s15_sel; +wire m1s15_we; +wire m1s15_cyc; +wire m1s15_stb; +wire m1s15_ack; +wire m1s15_err; +wire m1s15_rty; +wire [dw-1:0] m2s0_data_i; +wire [dw-1:0] m2s0_data_o; +wire [aw-1:0] m2s0_addr; +wire [sw-1:0] m2s0_sel; +wire m2s0_we; +wire m2s0_cyc; +wire m2s0_stb; +wire m2s0_ack; +wire m2s0_err; +wire m2s0_rty; +wire [dw-1:0] m2s1_data_i; +wire [dw-1:0] m2s1_data_o; +wire [aw-1:0] m2s1_addr; +wire [sw-1:0] m2s1_sel; +wire m2s1_we; +wire m2s1_cyc; +wire m2s1_stb; +wire m2s1_ack; +wire m2s1_err; +wire m2s1_rty; +wire [dw-1:0] m2s2_data_i; +wire [dw-1:0] m2s2_data_o; +wire [aw-1:0] m2s2_addr; +wire [sw-1:0] m2s2_sel; +wire m2s2_we; +wire m2s2_cyc; +wire m2s2_stb; +wire m2s2_ack; +wire m2s2_err; +wire m2s2_rty; +wire [dw-1:0] m2s3_data_i; +wire [dw-1:0] m2s3_data_o; +wire [aw-1:0] m2s3_addr; +wire [sw-1:0] m2s3_sel; +wire m2s3_we; +wire m2s3_cyc; +wire m2s3_stb; +wire m2s3_ack; +wire m2s3_err; +wire m2s3_rty; +wire [dw-1:0] m2s4_data_i; +wire [dw-1:0] m2s4_data_o; +wire [aw-1:0] m2s4_addr; +wire [sw-1:0] m2s4_sel; +wire m2s4_we; +wire m2s4_cyc; +wire m2s4_stb; +wire m2s4_ack; +wire m2s4_err; +wire m2s4_rty; +wire [dw-1:0] m2s5_data_i; +wire [dw-1:0] m2s5_data_o; +wire [aw-1:0] m2s5_addr; +wire [sw-1:0] m2s5_sel; +wire m2s5_we; +wire m2s5_cyc; +wire m2s5_stb; +wire m2s5_ack; +wire m2s5_err; +wire m2s5_rty; +wire [dw-1:0] m2s6_data_i; +wire [dw-1:0] m2s6_data_o; +wire [aw-1:0] m2s6_addr; +wire [sw-1:0] m2s6_sel; +wire m2s6_we; +wire m2s6_cyc; +wire m2s6_stb; +wire m2s6_ack; +wire m2s6_err; +wire m2s6_rty; +wire [dw-1:0] m2s7_data_i; +wire [dw-1:0] m2s7_data_o; +wire [aw-1:0] m2s7_addr; +wire [sw-1:0] m2s7_sel; +wire m2s7_we; +wire m2s7_cyc; +wire m2s7_stb; +wire m2s7_ack; +wire m2s7_err; +wire m2s7_rty; +wire [dw-1:0] m2s8_data_i; +wire [dw-1:0] m2s8_data_o; +wire [aw-1:0] m2s8_addr; +wire [sw-1:0] m2s8_sel; +wire m2s8_we; +wire m2s8_cyc; +wire m2s8_stb; +wire m2s8_ack; +wire m2s8_err; +wire m2s8_rty; +wire [dw-1:0] m2s9_data_i; +wire [dw-1:0] m2s9_data_o; +wire [aw-1:0] m2s9_addr; +wire [sw-1:0] m2s9_sel; +wire m2s9_we; +wire m2s9_cyc; +wire m2s9_stb; +wire m2s9_ack; +wire m2s9_err; +wire m2s9_rty; +wire [dw-1:0] m2s10_data_i; +wire [dw-1:0] m2s10_data_o; +wire [aw-1:0] m2s10_addr; +wire [sw-1:0] m2s10_sel; +wire m2s10_we; +wire m2s10_cyc; +wire m2s10_stb; +wire m2s10_ack; +wire m2s10_err; +wire m2s10_rty; +wire [dw-1:0] m2s11_data_i; +wire [dw-1:0] m2s11_data_o; +wire [aw-1:0] m2s11_addr; +wire [sw-1:0] m2s11_sel; +wire m2s11_we; +wire m2s11_cyc; +wire m2s11_stb; +wire m2s11_ack; +wire m2s11_err; +wire m2s11_rty; +wire [dw-1:0] m2s12_data_i; +wire [dw-1:0] m2s12_data_o; +wire [aw-1:0] m2s12_addr; +wire [sw-1:0] m2s12_sel; +wire m2s12_we; +wire m2s12_cyc; +wire m2s12_stb; +wire m2s12_ack; +wire m2s12_err; +wire m2s12_rty; +wire [dw-1:0] m2s13_data_i; +wire [dw-1:0] m2s13_data_o; +wire [aw-1:0] m2s13_addr; +wire [sw-1:0] m2s13_sel; +wire m2s13_we; +wire m2s13_cyc; +wire m2s13_stb; +wire m2s13_ack; +wire m2s13_err; +wire m2s13_rty; +wire [dw-1:0] m2s14_data_i; +wire [dw-1:0] m2s14_data_o; +wire [aw-1:0] m2s14_addr; +wire [sw-1:0] m2s14_sel; +wire m2s14_we; +wire m2s14_cyc; +wire m2s14_stb; +wire m2s14_ack; +wire m2s14_err; +wire m2s14_rty; +wire [dw-1:0] m2s15_data_i; +wire [dw-1:0] m2s15_data_o; +wire [aw-1:0] m2s15_addr; +wire [sw-1:0] m2s15_sel; +wire m2s15_we; +wire m2s15_cyc; +wire m2s15_stb; +wire m2s15_ack; +wire m2s15_err; +wire m2s15_rty; +wire [dw-1:0] m3s0_data_i; +wire [dw-1:0] m3s0_data_o; +wire [aw-1:0] m3s0_addr; +wire [sw-1:0] m3s0_sel; +wire m3s0_we; +wire m3s0_cyc; +wire m3s0_stb; +wire m3s0_ack; +wire m3s0_err; +wire m3s0_rty; +wire [dw-1:0] m3s1_data_i; +wire [dw-1:0] m3s1_data_o; +wire [aw-1:0] m3s1_addr; +wire [sw-1:0] m3s1_sel; +wire m3s1_we; +wire m3s1_cyc; +wire m3s1_stb; +wire m3s1_ack; +wire m3s1_err; +wire m3s1_rty; +wire [dw-1:0] m3s2_data_i; +wire [dw-1:0] m3s2_data_o; +wire [aw-1:0] m3s2_addr; +wire [sw-1:0] m3s2_sel; +wire m3s2_we; +wire m3s2_cyc; +wire m3s2_stb; +wire m3s2_ack; +wire m3s2_err; +wire m3s2_rty; +wire [dw-1:0] m3s3_data_i; +wire [dw-1:0] m3s3_data_o; +wire [aw-1:0] m3s3_addr; +wire [sw-1:0] m3s3_sel; +wire m3s3_we; +wire m3s3_cyc; +wire m3s3_stb; +wire m3s3_ack; +wire m3s3_err; +wire m3s3_rty; +wire [dw-1:0] m3s4_data_i; +wire [dw-1:0] m3s4_data_o; +wire [aw-1:0] m3s4_addr; +wire [sw-1:0] m3s4_sel; +wire m3s4_we; +wire m3s4_cyc; +wire m3s4_stb; +wire m3s4_ack; +wire m3s4_err; +wire m3s4_rty; +wire [dw-1:0] m3s5_data_i; +wire [dw-1:0] m3s5_data_o; +wire [aw-1:0] m3s5_addr; +wire [sw-1:0] m3s5_sel; +wire m3s5_we; +wire m3s5_cyc; +wire m3s5_stb; +wire m3s5_ack; +wire m3s5_err; +wire m3s5_rty; +wire [dw-1:0] m3s6_data_i; +wire [dw-1:0] m3s6_data_o; +wire [aw-1:0] m3s6_addr; +wire [sw-1:0] m3s6_sel; +wire m3s6_we; +wire m3s6_cyc; +wire m3s6_stb; +wire m3s6_ack; +wire m3s6_err; +wire m3s6_rty; +wire [dw-1:0] m3s7_data_i; +wire [dw-1:0] m3s7_data_o; +wire [aw-1:0] m3s7_addr; +wire [sw-1:0] m3s7_sel; +wire m3s7_we; +wire m3s7_cyc; +wire m3s7_stb; +wire m3s7_ack; +wire m3s7_err; +wire m3s7_rty; +wire [dw-1:0] m3s8_data_i; +wire [dw-1:0] m3s8_data_o; +wire [aw-1:0] m3s8_addr; +wire [sw-1:0] m3s8_sel; +wire m3s8_we; +wire m3s8_cyc; +wire m3s8_stb; +wire m3s8_ack; +wire m3s8_err; +wire m3s8_rty; +wire [dw-1:0] m3s9_data_i; +wire [dw-1:0] m3s9_data_o; +wire [aw-1:0] m3s9_addr; +wire [sw-1:0] m3s9_sel; +wire m3s9_we; +wire m3s9_cyc; +wire m3s9_stb; +wire m3s9_ack; +wire m3s9_err; +wire m3s9_rty; +wire [dw-1:0] m3s10_data_i; +wire [dw-1:0] m3s10_data_o; +wire [aw-1:0] m3s10_addr; +wire [sw-1:0] m3s10_sel; +wire m3s10_we; +wire m3s10_cyc; +wire m3s10_stb; +wire m3s10_ack; +wire m3s10_err; +wire m3s10_rty; +wire [dw-1:0] m3s11_data_i; +wire [dw-1:0] m3s11_data_o; +wire [aw-1:0] m3s11_addr; +wire [sw-1:0] m3s11_sel; +wire m3s11_we; +wire m3s11_cyc; +wire m3s11_stb; +wire m3s11_ack; +wire m3s11_err; +wire m3s11_rty; +wire [dw-1:0] m3s12_data_i; +wire [dw-1:0] m3s12_data_o; +wire [aw-1:0] m3s12_addr; +wire [sw-1:0] m3s12_sel; +wire m3s12_we; +wire m3s12_cyc; +wire m3s12_stb; +wire m3s12_ack; +wire m3s12_err; +wire m3s12_rty; +wire [dw-1:0] m3s13_data_i; +wire [dw-1:0] m3s13_data_o; +wire [aw-1:0] m3s13_addr; +wire [sw-1:0] m3s13_sel; +wire m3s13_we; +wire m3s13_cyc; +wire m3s13_stb; +wire m3s13_ack; +wire m3s13_err; +wire m3s13_rty; +wire [dw-1:0] m3s14_data_i; +wire [dw-1:0] m3s14_data_o; +wire [aw-1:0] m3s14_addr; +wire [sw-1:0] m3s14_sel; +wire m3s14_we; +wire m3s14_cyc; +wire m3s14_stb; +wire m3s14_ack; +wire m3s14_err; +wire m3s14_rty; +wire [dw-1:0] m3s15_data_i; +wire [dw-1:0] m3s15_data_o; +wire [aw-1:0] m3s15_addr; +wire [sw-1:0] m3s15_sel; +wire m3s15_we; +wire m3s15_cyc; +wire m3s15_stb; +wire m3s15_ack; +wire m3s15_err; +wire m3s15_rty; +wire [dw-1:0] m4s0_data_i; +wire [dw-1:0] m4s0_data_o; +wire [aw-1:0] m4s0_addr; +wire [sw-1:0] m4s0_sel; +wire m4s0_we; +wire m4s0_cyc; +wire m4s0_stb; +wire m4s0_ack; +wire m4s0_err; +wire m4s0_rty; +wire [dw-1:0] m4s1_data_i; +wire [dw-1:0] m4s1_data_o; +wire [aw-1:0] m4s1_addr; +wire [sw-1:0] m4s1_sel; +wire m4s1_we; +wire m4s1_cyc; +wire m4s1_stb; +wire m4s1_ack; +wire m4s1_err; +wire m4s1_rty; +wire [dw-1:0] m4s2_data_i; +wire [dw-1:0] m4s2_data_o; +wire [aw-1:0] m4s2_addr; +wire [sw-1:0] m4s2_sel; +wire m4s2_we; +wire m4s2_cyc; +wire m4s2_stb; +wire m4s2_ack; +wire m4s2_err; +wire m4s2_rty; +wire [dw-1:0] m4s3_data_i; +wire [dw-1:0] m4s3_data_o; +wire [aw-1:0] m4s3_addr; +wire [sw-1:0] m4s3_sel; +wire m4s3_we; +wire m4s3_cyc; +wire m4s3_stb; +wire m4s3_ack; +wire m4s3_err; +wire m4s3_rty; +wire [dw-1:0] m4s4_data_i; +wire [dw-1:0] m4s4_data_o; +wire [aw-1:0] m4s4_addr; +wire [sw-1:0] m4s4_sel; +wire m4s4_we; +wire m4s4_cyc; +wire m4s4_stb; +wire m4s4_ack; +wire m4s4_err; +wire m4s4_rty; +wire [dw-1:0] m4s5_data_i; +wire [dw-1:0] m4s5_data_o; +wire [aw-1:0] m4s5_addr; +wire [sw-1:0] m4s5_sel; +wire m4s5_we; +wire m4s5_cyc; +wire m4s5_stb; +wire m4s5_ack; +wire m4s5_err; +wire m4s5_rty; +wire [dw-1:0] m4s6_data_i; +wire [dw-1:0] m4s6_data_o; +wire [aw-1:0] m4s6_addr; +wire [sw-1:0] m4s6_sel; +wire m4s6_we; +wire m4s6_cyc; +wire m4s6_stb; +wire m4s6_ack; +wire m4s6_err; +wire m4s6_rty; +wire [dw-1:0] m4s7_data_i; +wire [dw-1:0] m4s7_data_o; +wire [aw-1:0] m4s7_addr; +wire [sw-1:0] m4s7_sel; +wire m4s7_we; +wire m4s7_cyc; +wire m4s7_stb; +wire m4s7_ack; +wire m4s7_err; +wire m4s7_rty; +wire [dw-1:0] m4s8_data_i; +wire [dw-1:0] m4s8_data_o; +wire [aw-1:0] m4s8_addr; +wire [sw-1:0] m4s8_sel; +wire m4s8_we; +wire m4s8_cyc; +wire m4s8_stb; +wire m4s8_ack; +wire m4s8_err; +wire m4s8_rty; +wire [dw-1:0] m4s9_data_i; +wire [dw-1:0] m4s9_data_o; +wire [aw-1:0] m4s9_addr; +wire [sw-1:0] m4s9_sel; +wire m4s9_we; +wire m4s9_cyc; +wire m4s9_stb; +wire m4s9_ack; +wire m4s9_err; +wire m4s9_rty; +wire [dw-1:0] m4s10_data_i; +wire [dw-1:0] m4s10_data_o; +wire [aw-1:0] m4s10_addr; +wire [sw-1:0] m4s10_sel; +wire m4s10_we; +wire m4s10_cyc; +wire m4s10_stb; +wire m4s10_ack; +wire m4s10_err; +wire m4s10_rty; +wire [dw-1:0] m4s11_data_i; +wire [dw-1:0] m4s11_data_o; +wire [aw-1:0] m4s11_addr; +wire [sw-1:0] m4s11_sel; +wire m4s11_we; +wire m4s11_cyc; +wire m4s11_stb; +wire m4s11_ack; +wire m4s11_err; +wire m4s11_rty; +wire [dw-1:0] m4s12_data_i; +wire [dw-1:0] m4s12_data_o; +wire [aw-1:0] m4s12_addr; +wire [sw-1:0] m4s12_sel; +wire m4s12_we; +wire m4s12_cyc; +wire m4s12_stb; +wire m4s12_ack; +wire m4s12_err; +wire m4s12_rty; +wire [dw-1:0] m4s13_data_i; +wire [dw-1:0] m4s13_data_o; +wire [aw-1:0] m4s13_addr; +wire [sw-1:0] m4s13_sel; +wire m4s13_we; +wire m4s13_cyc; +wire m4s13_stb; +wire m4s13_ack; +wire m4s13_err; +wire m4s13_rty; +wire [dw-1:0] m4s14_data_i; +wire [dw-1:0] m4s14_data_o; +wire [aw-1:0] m4s14_addr; +wire [sw-1:0] m4s14_sel; +wire m4s14_we; +wire m4s14_cyc; +wire m4s14_stb; +wire m4s14_ack; +wire m4s14_err; +wire m4s14_rty; +wire [dw-1:0] m4s15_data_i; +wire [dw-1:0] m4s15_data_o; +wire [aw-1:0] m4s15_addr; +wire [sw-1:0] m4s15_sel; +wire m4s15_we; +wire m4s15_cyc; +wire m4s15_stb; +wire m4s15_ack; +wire m4s15_err; +wire m4s15_rty; +wire [dw-1:0] m5s0_data_i; +wire [dw-1:0] m5s0_data_o; +wire [aw-1:0] m5s0_addr; +wire [sw-1:0] m5s0_sel; +wire m5s0_we; +wire m5s0_cyc; +wire m5s0_stb; +wire m5s0_ack; +wire m5s0_err; +wire m5s0_rty; +wire [dw-1:0] m5s1_data_i; +wire [dw-1:0] m5s1_data_o; +wire [aw-1:0] m5s1_addr; +wire [sw-1:0] m5s1_sel; +wire m5s1_we; +wire m5s1_cyc; +wire m5s1_stb; +wire m5s1_ack; +wire m5s1_err; +wire m5s1_rty; +wire [dw-1:0] m5s2_data_i; +wire [dw-1:0] m5s2_data_o; +wire [aw-1:0] m5s2_addr; +wire [sw-1:0] m5s2_sel; +wire m5s2_we; +wire m5s2_cyc; +wire m5s2_stb; +wire m5s2_ack; +wire m5s2_err; +wire m5s2_rty; +wire [dw-1:0] m5s3_data_i; +wire [dw-1:0] m5s3_data_o; +wire [aw-1:0] m5s3_addr; +wire [sw-1:0] m5s3_sel; +wire m5s3_we; +wire m5s3_cyc; +wire m5s3_stb; +wire m5s3_ack; +wire m5s3_err; +wire m5s3_rty; +wire [dw-1:0] m5s4_data_i; +wire [dw-1:0] m5s4_data_o; +wire [aw-1:0] m5s4_addr; +wire [sw-1:0] m5s4_sel; +wire m5s4_we; +wire m5s4_cyc; +wire m5s4_stb; +wire m5s4_ack; +wire m5s4_err; +wire m5s4_rty; +wire [dw-1:0] m5s5_data_i; +wire [dw-1:0] m5s5_data_o; +wire [aw-1:0] m5s5_addr; +wire [sw-1:0] m5s5_sel; +wire m5s5_we; +wire m5s5_cyc; +wire m5s5_stb; +wire m5s5_ack; +wire m5s5_err; +wire m5s5_rty; +wire [dw-1:0] m5s6_data_i; +wire [dw-1:0] m5s6_data_o; +wire [aw-1:0] m5s6_addr; +wire [sw-1:0] m5s6_sel; +wire m5s6_we; +wire m5s6_cyc; +wire m5s6_stb; +wire m5s6_ack; +wire m5s6_err; +wire m5s6_rty; +wire [dw-1:0] m5s7_data_i; +wire [dw-1:0] m5s7_data_o; +wire [aw-1:0] m5s7_addr; +wire [sw-1:0] m5s7_sel; +wire m5s7_we; +wire m5s7_cyc; +wire m5s7_stb; +wire m5s7_ack; +wire m5s7_err; +wire m5s7_rty; +wire [dw-1:0] m5s8_data_i; +wire [dw-1:0] m5s8_data_o; +wire [aw-1:0] m5s8_addr; +wire [sw-1:0] m5s8_sel; +wire m5s8_we; +wire m5s8_cyc; +wire m5s8_stb; +wire m5s8_ack; +wire m5s8_err; +wire m5s8_rty; +wire [dw-1:0] m5s9_data_i; +wire [dw-1:0] m5s9_data_o; +wire [aw-1:0] m5s9_addr; +wire [sw-1:0] m5s9_sel; +wire m5s9_we; +wire m5s9_cyc; +wire m5s9_stb; +wire m5s9_ack; +wire m5s9_err; +wire m5s9_rty; +wire [dw-1:0] m5s10_data_i; +wire [dw-1:0] m5s10_data_o; +wire [aw-1:0] m5s10_addr; +wire [sw-1:0] m5s10_sel; +wire m5s10_we; +wire m5s10_cyc; +wire m5s10_stb; +wire m5s10_ack; +wire m5s10_err; +wire m5s10_rty; +wire [dw-1:0] m5s11_data_i; +wire [dw-1:0] m5s11_data_o; +wire [aw-1:0] m5s11_addr; +wire [sw-1:0] m5s11_sel; +wire m5s11_we; +wire m5s11_cyc; +wire m5s11_stb; +wire m5s11_ack; +wire m5s11_err; +wire m5s11_rty; +wire [dw-1:0] m5s12_data_i; +wire [dw-1:0] m5s12_data_o; +wire [aw-1:0] m5s12_addr; +wire [sw-1:0] m5s12_sel; +wire m5s12_we; +wire m5s12_cyc; +wire m5s12_stb; +wire m5s12_ack; +wire m5s12_err; +wire m5s12_rty; +wire [dw-1:0] m5s13_data_i; +wire [dw-1:0] m5s13_data_o; +wire [aw-1:0] m5s13_addr; +wire [sw-1:0] m5s13_sel; +wire m5s13_we; +wire m5s13_cyc; +wire m5s13_stb; +wire m5s13_ack; +wire m5s13_err; +wire m5s13_rty; +wire [dw-1:0] m5s14_data_i; +wire [dw-1:0] m5s14_data_o; +wire [aw-1:0] m5s14_addr; +wire [sw-1:0] m5s14_sel; +wire m5s14_we; +wire m5s14_cyc; +wire m5s14_stb; +wire m5s14_ack; +wire m5s14_err; +wire m5s14_rty; +wire [dw-1:0] m5s15_data_i; +wire [dw-1:0] m5s15_data_o; +wire [aw-1:0] m5s15_addr; +wire [sw-1:0] m5s15_sel; +wire m5s15_we; +wire m5s15_cyc; +wire m5s15_stb; +wire m5s15_ack; +wire m5s15_err; +wire m5s15_rty; +wire [dw-1:0] m6s0_data_i; +wire [dw-1:0] m6s0_data_o; +wire [aw-1:0] m6s0_addr; +wire [sw-1:0] m6s0_sel; +wire m6s0_we; +wire m6s0_cyc; +wire m6s0_stb; +wire m6s0_ack; +wire m6s0_err; +wire m6s0_rty; +wire [dw-1:0] m6s1_data_i; +wire [dw-1:0] m6s1_data_o; +wire [aw-1:0] m6s1_addr; +wire [sw-1:0] m6s1_sel; +wire m6s1_we; +wire m6s1_cyc; +wire m6s1_stb; +wire m6s1_ack; +wire m6s1_err; +wire m6s1_rty; +wire [dw-1:0] m6s2_data_i; +wire [dw-1:0] m6s2_data_o; +wire [aw-1:0] m6s2_addr; +wire [sw-1:0] m6s2_sel; +wire m6s2_we; +wire m6s2_cyc; +wire m6s2_stb; +wire m6s2_ack; +wire m6s2_err; +wire m6s2_rty; +wire [dw-1:0] m6s3_data_i; +wire [dw-1:0] m6s3_data_o; +wire [aw-1:0] m6s3_addr; +wire [sw-1:0] m6s3_sel; +wire m6s3_we; +wire m6s3_cyc; +wire m6s3_stb; +wire m6s3_ack; +wire m6s3_err; +wire m6s3_rty; +wire [dw-1:0] m6s4_data_i; +wire [dw-1:0] m6s4_data_o; +wire [aw-1:0] m6s4_addr; +wire [sw-1:0] m6s4_sel; +wire m6s4_we; +wire m6s4_cyc; +wire m6s4_stb; +wire m6s4_ack; +wire m6s4_err; +wire m6s4_rty; +wire [dw-1:0] m6s5_data_i; +wire [dw-1:0] m6s5_data_o; +wire [aw-1:0] m6s5_addr; +wire [sw-1:0] m6s5_sel; +wire m6s5_we; +wire m6s5_cyc; +wire m6s5_stb; +wire m6s5_ack; +wire m6s5_err; +wire m6s5_rty; +wire [dw-1:0] m6s6_data_i; +wire [dw-1:0] m6s6_data_o; +wire [aw-1:0] m6s6_addr; +wire [sw-1:0] m6s6_sel; +wire m6s6_we; +wire m6s6_cyc; +wire m6s6_stb; +wire m6s6_ack; +wire m6s6_err; +wire m6s6_rty; +wire [dw-1:0] m6s7_data_i; +wire [dw-1:0] m6s7_data_o; +wire [aw-1:0] m6s7_addr; +wire [sw-1:0] m6s7_sel; +wire m6s7_we; +wire m6s7_cyc; +wire m6s7_stb; +wire m6s7_ack; +wire m6s7_err; +wire m6s7_rty; +wire [dw-1:0] m6s8_data_i; +wire [dw-1:0] m6s8_data_o; +wire [aw-1:0] m6s8_addr; +wire [sw-1:0] m6s8_sel; +wire m6s8_we; +wire m6s8_cyc; +wire m6s8_stb; +wire m6s8_ack; +wire m6s8_err; +wire m6s8_rty; +wire [dw-1:0] m6s9_data_i; +wire [dw-1:0] m6s9_data_o; +wire [aw-1:0] m6s9_addr; +wire [sw-1:0] m6s9_sel; +wire m6s9_we; +wire m6s9_cyc; +wire m6s9_stb; +wire m6s9_ack; +wire m6s9_err; +wire m6s9_rty; +wire [dw-1:0] m6s10_data_i; +wire [dw-1:0] m6s10_data_o; +wire [aw-1:0] m6s10_addr; +wire [sw-1:0] m6s10_sel; +wire m6s10_we; +wire m6s10_cyc; +wire m6s10_stb; +wire m6s10_ack; +wire m6s10_err; +wire m6s10_rty; +wire [dw-1:0] m6s11_data_i; +wire [dw-1:0] m6s11_data_o; +wire [aw-1:0] m6s11_addr; +wire [sw-1:0] m6s11_sel; +wire m6s11_we; +wire m6s11_cyc; +wire m6s11_stb; +wire m6s11_ack; +wire m6s11_err; +wire m6s11_rty; +wire [dw-1:0] m6s12_data_i; +wire [dw-1:0] m6s12_data_o; +wire [aw-1:0] m6s12_addr; +wire [sw-1:0] m6s12_sel; +wire m6s12_we; +wire m6s12_cyc; +wire m6s12_stb; +wire m6s12_ack; +wire m6s12_err; +wire m6s12_rty; +wire [dw-1:0] m6s13_data_i; +wire [dw-1:0] m6s13_data_o; +wire [aw-1:0] m6s13_addr; +wire [sw-1:0] m6s13_sel; +wire m6s13_we; +wire m6s13_cyc; +wire m6s13_stb; +wire m6s13_ack; +wire m6s13_err; +wire m6s13_rty; +wire [dw-1:0] m6s14_data_i; +wire [dw-1:0] m6s14_data_o; +wire [aw-1:0] m6s14_addr; +wire [sw-1:0] m6s14_sel; +wire m6s14_we; +wire m6s14_cyc; +wire m6s14_stb; +wire m6s14_ack; +wire m6s14_err; +wire m6s14_rty; +wire [dw-1:0] m6s15_data_i; +wire [dw-1:0] m6s15_data_o; +wire [aw-1:0] m6s15_addr; +wire [sw-1:0] m6s15_sel; +wire m6s15_we; +wire m6s15_cyc; +wire m6s15_stb; +wire m6s15_ack; +wire m6s15_err; +wire m6s15_rty; +wire [dw-1:0] m7s0_data_i; +wire [dw-1:0] m7s0_data_o; +wire [aw-1:0] m7s0_addr; +wire [sw-1:0] m7s0_sel; +wire m7s0_we; +wire m7s0_cyc; +wire m7s0_stb; +wire m7s0_ack; +wire m7s0_err; +wire m7s0_rty; +wire [dw-1:0] m7s1_data_i; +wire [dw-1:0] m7s1_data_o; +wire [aw-1:0] m7s1_addr; +wire [sw-1:0] m7s1_sel; +wire m7s1_we; +wire m7s1_cyc; +wire m7s1_stb; +wire m7s1_ack; +wire m7s1_err; +wire m7s1_rty; +wire [dw-1:0] m7s2_data_i; +wire [dw-1:0] m7s2_data_o; +wire [aw-1:0] m7s2_addr; +wire [sw-1:0] m7s2_sel; +wire m7s2_we; +wire m7s2_cyc; +wire m7s2_stb; +wire m7s2_ack; +wire m7s2_err; +wire m7s2_rty; +wire [dw-1:0] m7s3_data_i; +wire [dw-1:0] m7s3_data_o; +wire [aw-1:0] m7s3_addr; +wire [sw-1:0] m7s3_sel; +wire m7s3_we; +wire m7s3_cyc; +wire m7s3_stb; +wire m7s3_ack; +wire m7s3_err; +wire m7s3_rty; +wire [dw-1:0] m7s4_data_i; +wire [dw-1:0] m7s4_data_o; +wire [aw-1:0] m7s4_addr; +wire [sw-1:0] m7s4_sel; +wire m7s4_we; +wire m7s4_cyc; +wire m7s4_stb; +wire m7s4_ack; +wire m7s4_err; +wire m7s4_rty; +wire [dw-1:0] m7s5_data_i; +wire [dw-1:0] m7s5_data_o; +wire [aw-1:0] m7s5_addr; +wire [sw-1:0] m7s5_sel; +wire m7s5_we; +wire m7s5_cyc; +wire m7s5_stb; +wire m7s5_ack; +wire m7s5_err; +wire m7s5_rty; +wire [dw-1:0] m7s6_data_i; +wire [dw-1:0] m7s6_data_o; +wire [aw-1:0] m7s6_addr; +wire [sw-1:0] m7s6_sel; +wire m7s6_we; +wire m7s6_cyc; +wire m7s6_stb; +wire m7s6_ack; +wire m7s6_err; +wire m7s6_rty; +wire [dw-1:0] m7s7_data_i; +wire [dw-1:0] m7s7_data_o; +wire [aw-1:0] m7s7_addr; +wire [sw-1:0] m7s7_sel; +wire m7s7_we; +wire m7s7_cyc; +wire m7s7_stb; +wire m7s7_ack; +wire m7s7_err; +wire m7s7_rty; +wire [dw-1:0] m7s8_data_i; +wire [dw-1:0] m7s8_data_o; +wire [aw-1:0] m7s8_addr; +wire [sw-1:0] m7s8_sel; +wire m7s8_we; +wire m7s8_cyc; +wire m7s8_stb; +wire m7s8_ack; +wire m7s8_err; +wire m7s8_rty; +wire [dw-1:0] m7s9_data_i; +wire [dw-1:0] m7s9_data_o; +wire [aw-1:0] m7s9_addr; +wire [sw-1:0] m7s9_sel; +wire m7s9_we; +wire m7s9_cyc; +wire m7s9_stb; +wire m7s9_ack; +wire m7s9_err; +wire m7s9_rty; +wire [dw-1:0] m7s10_data_i; +wire [dw-1:0] m7s10_data_o; +wire [aw-1:0] m7s10_addr; +wire [sw-1:0] m7s10_sel; +wire m7s10_we; +wire m7s10_cyc; +wire m7s10_stb; +wire m7s10_ack; +wire m7s10_err; +wire m7s10_rty; +wire [dw-1:0] m7s11_data_i; +wire [dw-1:0] m7s11_data_o; +wire [aw-1:0] m7s11_addr; +wire [sw-1:0] m7s11_sel; +wire m7s11_we; +wire m7s11_cyc; +wire m7s11_stb; +wire m7s11_ack; +wire m7s11_err; +wire m7s11_rty; +wire [dw-1:0] m7s12_data_i; +wire [dw-1:0] m7s12_data_o; +wire [aw-1:0] m7s12_addr; +wire [sw-1:0] m7s12_sel; +wire m7s12_we; +wire m7s12_cyc; +wire m7s12_stb; +wire m7s12_ack; +wire m7s12_err; +wire m7s12_rty; +wire [dw-1:0] m7s13_data_i; +wire [dw-1:0] m7s13_data_o; +wire [aw-1:0] m7s13_addr; +wire [sw-1:0] m7s13_sel; +wire m7s13_we; +wire m7s13_cyc; +wire m7s13_stb; +wire m7s13_ack; +wire m7s13_err; +wire m7s13_rty; +wire [dw-1:0] m7s14_data_i; +wire [dw-1:0] m7s14_data_o; +wire [aw-1:0] m7s14_addr; +wire [sw-1:0] m7s14_sel; +wire m7s14_we; +wire m7s14_cyc; +wire m7s14_stb; +wire m7s14_ack; +wire m7s14_err; +wire m7s14_rty; +wire [dw-1:0] m7s15_data_i; +wire [dw-1:0] m7s15_data_o; +wire [aw-1:0] m7s15_addr; +wire [sw-1:0] m7s15_sel; +wire m7s15_we; +wire m7s15_cyc; +wire m7s15_stb; +wire m7s15_ack; +wire m7s15_err; +wire m7s15_rty; + +wire [15:0] conf0; +wire [15:0] conf1; +wire [15:0] conf2; +wire [15:0] conf3; +wire [15:0] conf4; +wire [15:0] conf5; +wire [15:0] conf6; +wire [15:0] conf7; +wire [15:0] conf8; +wire [15:0] conf9; +wire [15:0] conf10; +wire [15:0] conf11; +wire [15:0] conf12; +wire [15:0] conf13; +wire [15:0] conf14; +wire [15:0] conf15; + +//////////////////////////////////////////////////////////////////// +// +// Initial Configuration Check +// + +// synopsys translate_off +initial + begin + if(dw<16) + begin + $display("ERROR: Setting Data bus width to less than 16 bits, will"); + $display(" make it impossible to use the configurations registers."); + $finish; + end + end +// synopsys translate_on + +//////////////////////////////////////////////////////////////////// +// +// Master Interfaces +// + +wb_conmax_master_if #(dw,aw,sw) m0( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m0_data_i ), + .wb_data_o( m0_data_o ), + .wb_addr_i( m0_addr_i ), + .wb_sel_i( m0_sel_i ), + .wb_we_i( m0_we_i ), + .wb_cyc_i( m0_cyc_i ), + .wb_stb_i( m0_stb_i ), + .wb_ack_o( m0_ack_o ), + .wb_err_o( m0_err_o ), + .wb_rty_o( m0_rty_o ), + .s0_data_i( m0s0_data_i ), + .s0_data_o( m0s0_data_o ), + .s0_addr_o( m0s0_addr ), + .s0_sel_o( m0s0_sel ), + .s0_we_o( m0s0_we ), + .s0_cyc_o( m0s0_cyc ), + .s0_stb_o( m0s0_stb ), + .s0_ack_i( m0s0_ack ), + .s0_err_i( m0s0_err ), + .s0_rty_i( m0s0_rty ), + .s1_data_i( m0s1_data_i ), + .s1_data_o( m0s1_data_o ), + .s1_addr_o( m0s1_addr ), + .s1_sel_o( m0s1_sel ), + .s1_we_o( m0s1_we ), + .s1_cyc_o( m0s1_cyc ), + .s1_stb_o( m0s1_stb ), + .s1_ack_i( m0s1_ack ), + .s1_err_i( m0s1_err ), + .s1_rty_i( m0s1_rty ), + .s2_data_i( m0s2_data_i ), + .s2_data_o( m0s2_data_o ), + .s2_addr_o( m0s2_addr ), + .s2_sel_o( m0s2_sel ), + .s2_we_o( m0s2_we ), + .s2_cyc_o( m0s2_cyc ), + .s2_stb_o( m0s2_stb ), + .s2_ack_i( m0s2_ack ), + .s2_err_i( m0s2_err ), + .s2_rty_i( m0s2_rty ), + .s3_data_i( m0s3_data_i ), + .s3_data_o( m0s3_data_o ), + .s3_addr_o( m0s3_addr ), + .s3_sel_o( m0s3_sel ), + .s3_we_o( m0s3_we ), + .s3_cyc_o( m0s3_cyc ), + .s3_stb_o( m0s3_stb ), + .s3_ack_i( m0s3_ack ), + .s3_err_i( m0s3_err ), + .s3_rty_i( m0s3_rty ), + .s4_data_i( m0s4_data_i ), + .s4_data_o( m0s4_data_o ), + .s4_addr_o( m0s4_addr ), + .s4_sel_o( m0s4_sel ), + .s4_we_o( m0s4_we ), + .s4_cyc_o( m0s4_cyc ), + .s4_stb_o( m0s4_stb ), + .s4_ack_i( m0s4_ack ), + .s4_err_i( m0s4_err ), + .s4_rty_i( m0s4_rty ), + .s5_data_i( m0s5_data_i ), + .s5_data_o( m0s5_data_o ), + .s5_addr_o( m0s5_addr ), + .s5_sel_o( m0s5_sel ), + .s5_we_o( m0s5_we ), + .s5_cyc_o( m0s5_cyc ), + .s5_stb_o( m0s5_stb ), + .s5_ack_i( m0s5_ack ), + .s5_err_i( m0s5_err ), + .s5_rty_i( m0s5_rty ), + .s6_data_i( m0s6_data_i ), + .s6_data_o( m0s6_data_o ), + .s6_addr_o( m0s6_addr ), + .s6_sel_o( m0s6_sel ), + .s6_we_o( m0s6_we ), + .s6_cyc_o( m0s6_cyc ), + .s6_stb_o( m0s6_stb ), + .s6_ack_i( m0s6_ack ), + .s6_err_i( m0s6_err ), + .s6_rty_i( m0s6_rty ), + .s7_data_i( m0s7_data_i ), + .s7_data_o( m0s7_data_o ), + .s7_addr_o( m0s7_addr ), + .s7_sel_o( m0s7_sel ), + .s7_we_o( m0s7_we ), + .s7_cyc_o( m0s7_cyc ), + .s7_stb_o( m0s7_stb ), + .s7_ack_i( m0s7_ack ), + .s7_err_i( m0s7_err ), + .s7_rty_i( m0s7_rty ), + .s8_data_i( m0s8_data_i ), + .s8_data_o( m0s8_data_o ), + .s8_addr_o( m0s8_addr ), + .s8_sel_o( m0s8_sel ), + .s8_we_o( m0s8_we ), + .s8_cyc_o( m0s8_cyc ), + .s8_stb_o( m0s8_stb ), + .s8_ack_i( m0s8_ack ), + .s8_err_i( m0s8_err ), + .s8_rty_i( m0s8_rty ), + .s9_data_i( m0s9_data_i ), + .s9_data_o( m0s9_data_o ), + .s9_addr_o( m0s9_addr ), + .s9_sel_o( m0s9_sel ), + .s9_we_o( m0s9_we ), + .s9_cyc_o( m0s9_cyc ), + .s9_stb_o( m0s9_stb ), + .s9_ack_i( m0s9_ack ), + .s9_err_i( m0s9_err ), + .s9_rty_i( m0s9_rty ), + .s10_data_i( m0s10_data_i ), + .s10_data_o( m0s10_data_o ), + .s10_addr_o( m0s10_addr ), + .s10_sel_o( m0s10_sel ), + .s10_we_o( m0s10_we ), + .s10_cyc_o( m0s10_cyc ), + .s10_stb_o( m0s10_stb ), + .s10_ack_i( m0s10_ack ), + .s10_err_i( m0s10_err ), + .s10_rty_i( m0s10_rty ), + .s11_data_i( m0s11_data_i ), + .s11_data_o( m0s11_data_o ), + .s11_addr_o( m0s11_addr ), + .s11_sel_o( m0s11_sel ), + .s11_we_o( m0s11_we ), + .s11_cyc_o( m0s11_cyc ), + .s11_stb_o( m0s11_stb ), + .s11_ack_i( m0s11_ack ), + .s11_err_i( m0s11_err ), + .s11_rty_i( m0s11_rty ), + .s12_data_i( m0s12_data_i ), + .s12_data_o( m0s12_data_o ), + .s12_addr_o( m0s12_addr ), + .s12_sel_o( m0s12_sel ), + .s12_we_o( m0s12_we ), + .s12_cyc_o( m0s12_cyc ), + .s12_stb_o( m0s12_stb ), + .s12_ack_i( m0s12_ack ), + .s12_err_i( m0s12_err ), + .s12_rty_i( m0s12_rty ), + .s13_data_i( m0s13_data_i ), + .s13_data_o( m0s13_data_o ), + .s13_addr_o( m0s13_addr ), + .s13_sel_o( m0s13_sel ), + .s13_we_o( m0s13_we ), + .s13_cyc_o( m0s13_cyc ), + .s13_stb_o( m0s13_stb ), + .s13_ack_i( m0s13_ack ), + .s13_err_i( m0s13_err ), + .s13_rty_i( m0s13_rty ), + .s14_data_i( m0s14_data_i ), + .s14_data_o( m0s14_data_o ), + .s14_addr_o( m0s14_addr ), + .s14_sel_o( m0s14_sel ), + .s14_we_o( m0s14_we ), + .s14_cyc_o( m0s14_cyc ), + .s14_stb_o( m0s14_stb ), + .s14_ack_i( m0s14_ack ), + .s14_err_i( m0s14_err ), + .s14_rty_i( m0s14_rty ), + .s15_data_i( m0s15_data_i ), + .s15_data_o( m0s15_data_o ), + .s15_addr_o( m0s15_addr ), + .s15_sel_o( m0s15_sel ), + .s15_we_o( m0s15_we ), + .s15_cyc_o( m0s15_cyc ), + .s15_stb_o( m0s15_stb ), + .s15_ack_i( m0s15_ack ), + .s15_err_i( m0s15_err ), + .s15_rty_i( m0s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m1( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m1_data_i ), + .wb_data_o( m1_data_o ), + .wb_addr_i( m1_addr_i ), + .wb_sel_i( m1_sel_i ), + .wb_we_i( m1_we_i ), + .wb_cyc_i( m1_cyc_i ), + .wb_stb_i( m1_stb_i ), + .wb_ack_o( m1_ack_o ), + .wb_err_o( m1_err_o ), + .wb_rty_o( m1_rty_o ), + .s0_data_i( m1s0_data_i ), + .s0_data_o( m1s0_data_o ), + .s0_addr_o( m1s0_addr ), + .s0_sel_o( m1s0_sel ), + .s0_we_o( m1s0_we ), + .s0_cyc_o( m1s0_cyc ), + .s0_stb_o( m1s0_stb ), + .s0_ack_i( m1s0_ack ), + .s0_err_i( m1s0_err ), + .s0_rty_i( m1s0_rty ), + .s1_data_i( m1s1_data_i ), + .s1_data_o( m1s1_data_o ), + .s1_addr_o( m1s1_addr ), + .s1_sel_o( m1s1_sel ), + .s1_we_o( m1s1_we ), + .s1_cyc_o( m1s1_cyc ), + .s1_stb_o( m1s1_stb ), + .s1_ack_i( m1s1_ack ), + .s1_err_i( m1s1_err ), + .s1_rty_i( m1s1_rty ), + .s2_data_i( m1s2_data_i ), + .s2_data_o( m1s2_data_o ), + .s2_addr_o( m1s2_addr ), + .s2_sel_o( m1s2_sel ), + .s2_we_o( m1s2_we ), + .s2_cyc_o( m1s2_cyc ), + .s2_stb_o( m1s2_stb ), + .s2_ack_i( m1s2_ack ), + .s2_err_i( m1s2_err ), + .s2_rty_i( m1s2_rty ), + .s3_data_i( m1s3_data_i ), + .s3_data_o( m1s3_data_o ), + .s3_addr_o( m1s3_addr ), + .s3_sel_o( m1s3_sel ), + .s3_we_o( m1s3_we ), + .s3_cyc_o( m1s3_cyc ), + .s3_stb_o( m1s3_stb ), + .s3_ack_i( m1s3_ack ), + .s3_err_i( m1s3_err ), + .s3_rty_i( m1s3_rty ), + .s4_data_i( m1s4_data_i ), + .s4_data_o( m1s4_data_o ), + .s4_addr_o( m1s4_addr ), + .s4_sel_o( m1s4_sel ), + .s4_we_o( m1s4_we ), + .s4_cyc_o( m1s4_cyc ), + .s4_stb_o( m1s4_stb ), + .s4_ack_i( m1s4_ack ), + .s4_err_i( m1s4_err ), + .s4_rty_i( m1s4_rty ), + .s5_data_i( m1s5_data_i ), + .s5_data_o( m1s5_data_o ), + .s5_addr_o( m1s5_addr ), + .s5_sel_o( m1s5_sel ), + .s5_we_o( m1s5_we ), + .s5_cyc_o( m1s5_cyc ), + .s5_stb_o( m1s5_stb ), + .s5_ack_i( m1s5_ack ), + .s5_err_i( m1s5_err ), + .s5_rty_i( m1s5_rty ), + .s6_data_i( m1s6_data_i ), + .s6_data_o( m1s6_data_o ), + .s6_addr_o( m1s6_addr ), + .s6_sel_o( m1s6_sel ), + .s6_we_o( m1s6_we ), + .s6_cyc_o( m1s6_cyc ), + .s6_stb_o( m1s6_stb ), + .s6_ack_i( m1s6_ack ), + .s6_err_i( m1s6_err ), + .s6_rty_i( m1s6_rty ), + .s7_data_i( m1s7_data_i ), + .s7_data_o( m1s7_data_o ), + .s7_addr_o( m1s7_addr ), + .s7_sel_o( m1s7_sel ), + .s7_we_o( m1s7_we ), + .s7_cyc_o( m1s7_cyc ), + .s7_stb_o( m1s7_stb ), + .s7_ack_i( m1s7_ack ), + .s7_err_i( m1s7_err ), + .s7_rty_i( m1s7_rty ), + .s8_data_i( m1s8_data_i ), + .s8_data_o( m1s8_data_o ), + .s8_addr_o( m1s8_addr ), + .s8_sel_o( m1s8_sel ), + .s8_we_o( m1s8_we ), + .s8_cyc_o( m1s8_cyc ), + .s8_stb_o( m1s8_stb ), + .s8_ack_i( m1s8_ack ), + .s8_err_i( m1s8_err ), + .s8_rty_i( m1s8_rty ), + .s9_data_i( m1s9_data_i ), + .s9_data_o( m1s9_data_o ), + .s9_addr_o( m1s9_addr ), + .s9_sel_o( m1s9_sel ), + .s9_we_o( m1s9_we ), + .s9_cyc_o( m1s9_cyc ), + .s9_stb_o( m1s9_stb ), + .s9_ack_i( m1s9_ack ), + .s9_err_i( m1s9_err ), + .s9_rty_i( m1s9_rty ), + .s10_data_i( m1s10_data_i ), + .s10_data_o( m1s10_data_o ), + .s10_addr_o( m1s10_addr ), + .s10_sel_o( m1s10_sel ), + .s10_we_o( m1s10_we ), + .s10_cyc_o( m1s10_cyc ), + .s10_stb_o( m1s10_stb ), + .s10_ack_i( m1s10_ack ), + .s10_err_i( m1s10_err ), + .s10_rty_i( m1s10_rty ), + .s11_data_i( m1s11_data_i ), + .s11_data_o( m1s11_data_o ), + .s11_addr_o( m1s11_addr ), + .s11_sel_o( m1s11_sel ), + .s11_we_o( m1s11_we ), + .s11_cyc_o( m1s11_cyc ), + .s11_stb_o( m1s11_stb ), + .s11_ack_i( m1s11_ack ), + .s11_err_i( m1s11_err ), + .s11_rty_i( m1s11_rty ), + .s12_data_i( m1s12_data_i ), + .s12_data_o( m1s12_data_o ), + .s12_addr_o( m1s12_addr ), + .s12_sel_o( m1s12_sel ), + .s12_we_o( m1s12_we ), + .s12_cyc_o( m1s12_cyc ), + .s12_stb_o( m1s12_stb ), + .s12_ack_i( m1s12_ack ), + .s12_err_i( m1s12_err ), + .s12_rty_i( m1s12_rty ), + .s13_data_i( m1s13_data_i ), + .s13_data_o( m1s13_data_o ), + .s13_addr_o( m1s13_addr ), + .s13_sel_o( m1s13_sel ), + .s13_we_o( m1s13_we ), + .s13_cyc_o( m1s13_cyc ), + .s13_stb_o( m1s13_stb ), + .s13_ack_i( m1s13_ack ), + .s13_err_i( m1s13_err ), + .s13_rty_i( m1s13_rty ), + .s14_data_i( m1s14_data_i ), + .s14_data_o( m1s14_data_o ), + .s14_addr_o( m1s14_addr ), + .s14_sel_o( m1s14_sel ), + .s14_we_o( m1s14_we ), + .s14_cyc_o( m1s14_cyc ), + .s14_stb_o( m1s14_stb ), + .s14_ack_i( m1s14_ack ), + .s14_err_i( m1s14_err ), + .s14_rty_i( m1s14_rty ), + .s15_data_i( m1s15_data_i ), + .s15_data_o( m1s15_data_o ), + .s15_addr_o( m1s15_addr ), + .s15_sel_o( m1s15_sel ), + .s15_we_o( m1s15_we ), + .s15_cyc_o( m1s15_cyc ), + .s15_stb_o( m1s15_stb ), + .s15_ack_i( m1s15_ack ), + .s15_err_i( m1s15_err ), + .s15_rty_i( m1s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m2( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m2_data_i ), + .wb_data_o( m2_data_o ), + .wb_addr_i( m2_addr_i ), + .wb_sel_i( m2_sel_i ), + .wb_we_i( m2_we_i ), + .wb_cyc_i( m2_cyc_i ), + .wb_stb_i( m2_stb_i ), + .wb_ack_o( m2_ack_o ), + .wb_err_o( m2_err_o ), + .wb_rty_o( m2_rty_o ), + .s0_data_i( m2s0_data_i ), + .s0_data_o( m2s0_data_o ), + .s0_addr_o( m2s0_addr ), + .s0_sel_o( m2s0_sel ), + .s0_we_o( m2s0_we ), + .s0_cyc_o( m2s0_cyc ), + .s0_stb_o( m2s0_stb ), + .s0_ack_i( m2s0_ack ), + .s0_err_i( m2s0_err ), + .s0_rty_i( m2s0_rty ), + .s1_data_i( m2s1_data_i ), + .s1_data_o( m2s1_data_o ), + .s1_addr_o( m2s1_addr ), + .s1_sel_o( m2s1_sel ), + .s1_we_o( m2s1_we ), + .s1_cyc_o( m2s1_cyc ), + .s1_stb_o( m2s1_stb ), + .s1_ack_i( m2s1_ack ), + .s1_err_i( m2s1_err ), + .s1_rty_i( m2s1_rty ), + .s2_data_i( m2s2_data_i ), + .s2_data_o( m2s2_data_o ), + .s2_addr_o( m2s2_addr ), + .s2_sel_o( m2s2_sel ), + .s2_we_o( m2s2_we ), + .s2_cyc_o( m2s2_cyc ), + .s2_stb_o( m2s2_stb ), + .s2_ack_i( m2s2_ack ), + .s2_err_i( m2s2_err ), + .s2_rty_i( m2s2_rty ), + .s3_data_i( m2s3_data_i ), + .s3_data_o( m2s3_data_o ), + .s3_addr_o( m2s3_addr ), + .s3_sel_o( m2s3_sel ), + .s3_we_o( m2s3_we ), + .s3_cyc_o( m2s3_cyc ), + .s3_stb_o( m2s3_stb ), + .s3_ack_i( m2s3_ack ), + .s3_err_i( m2s3_err ), + .s3_rty_i( m2s3_rty ), + .s4_data_i( m2s4_data_i ), + .s4_data_o( m2s4_data_o ), + .s4_addr_o( m2s4_addr ), + .s4_sel_o( m2s4_sel ), + .s4_we_o( m2s4_we ), + .s4_cyc_o( m2s4_cyc ), + .s4_stb_o( m2s4_stb ), + .s4_ack_i( m2s4_ack ), + .s4_err_i( m2s4_err ), + .s4_rty_i( m2s4_rty ), + .s5_data_i( m2s5_data_i ), + .s5_data_o( m2s5_data_o ), + .s5_addr_o( m2s5_addr ), + .s5_sel_o( m2s5_sel ), + .s5_we_o( m2s5_we ), + .s5_cyc_o( m2s5_cyc ), + .s5_stb_o( m2s5_stb ), + .s5_ack_i( m2s5_ack ), + .s5_err_i( m2s5_err ), + .s5_rty_i( m2s5_rty ), + .s6_data_i( m2s6_data_i ), + .s6_data_o( m2s6_data_o ), + .s6_addr_o( m2s6_addr ), + .s6_sel_o( m2s6_sel ), + .s6_we_o( m2s6_we ), + .s6_cyc_o( m2s6_cyc ), + .s6_stb_o( m2s6_stb ), + .s6_ack_i( m2s6_ack ), + .s6_err_i( m2s6_err ), + .s6_rty_i( m2s6_rty ), + .s7_data_i( m2s7_data_i ), + .s7_data_o( m2s7_data_o ), + .s7_addr_o( m2s7_addr ), + .s7_sel_o( m2s7_sel ), + .s7_we_o( m2s7_we ), + .s7_cyc_o( m2s7_cyc ), + .s7_stb_o( m2s7_stb ), + .s7_ack_i( m2s7_ack ), + .s7_err_i( m2s7_err ), + .s7_rty_i( m2s7_rty ), + .s8_data_i( m2s8_data_i ), + .s8_data_o( m2s8_data_o ), + .s8_addr_o( m2s8_addr ), + .s8_sel_o( m2s8_sel ), + .s8_we_o( m2s8_we ), + .s8_cyc_o( m2s8_cyc ), + .s8_stb_o( m2s8_stb ), + .s8_ack_i( m2s8_ack ), + .s8_err_i( m2s8_err ), + .s8_rty_i( m2s8_rty ), + .s9_data_i( m2s9_data_i ), + .s9_data_o( m2s9_data_o ), + .s9_addr_o( m2s9_addr ), + .s9_sel_o( m2s9_sel ), + .s9_we_o( m2s9_we ), + .s9_cyc_o( m2s9_cyc ), + .s9_stb_o( m2s9_stb ), + .s9_ack_i( m2s9_ack ), + .s9_err_i( m2s9_err ), + .s9_rty_i( m2s9_rty ), + .s10_data_i( m2s10_data_i ), + .s10_data_o( m2s10_data_o ), + .s10_addr_o( m2s10_addr ), + .s10_sel_o( m2s10_sel ), + .s10_we_o( m2s10_we ), + .s10_cyc_o( m2s10_cyc ), + .s10_stb_o( m2s10_stb ), + .s10_ack_i( m2s10_ack ), + .s10_err_i( m2s10_err ), + .s10_rty_i( m2s10_rty ), + .s11_data_i( m2s11_data_i ), + .s11_data_o( m2s11_data_o ), + .s11_addr_o( m2s11_addr ), + .s11_sel_o( m2s11_sel ), + .s11_we_o( m2s11_we ), + .s11_cyc_o( m2s11_cyc ), + .s11_stb_o( m2s11_stb ), + .s11_ack_i( m2s11_ack ), + .s11_err_i( m2s11_err ), + .s11_rty_i( m2s11_rty ), + .s12_data_i( m2s12_data_i ), + .s12_data_o( m2s12_data_o ), + .s12_addr_o( m2s12_addr ), + .s12_sel_o( m2s12_sel ), + .s12_we_o( m2s12_we ), + .s12_cyc_o( m2s12_cyc ), + .s12_stb_o( m2s12_stb ), + .s12_ack_i( m2s12_ack ), + .s12_err_i( m2s12_err ), + .s12_rty_i( m2s12_rty ), + .s13_data_i( m2s13_data_i ), + .s13_data_o( m2s13_data_o ), + .s13_addr_o( m2s13_addr ), + .s13_sel_o( m2s13_sel ), + .s13_we_o( m2s13_we ), + .s13_cyc_o( m2s13_cyc ), + .s13_stb_o( m2s13_stb ), + .s13_ack_i( m2s13_ack ), + .s13_err_i( m2s13_err ), + .s13_rty_i( m2s13_rty ), + .s14_data_i( m2s14_data_i ), + .s14_data_o( m2s14_data_o ), + .s14_addr_o( m2s14_addr ), + .s14_sel_o( m2s14_sel ), + .s14_we_o( m2s14_we ), + .s14_cyc_o( m2s14_cyc ), + .s14_stb_o( m2s14_stb ), + .s14_ack_i( m2s14_ack ), + .s14_err_i( m2s14_err ), + .s14_rty_i( m2s14_rty ), + .s15_data_i( m2s15_data_i ), + .s15_data_o( m2s15_data_o ), + .s15_addr_o( m2s15_addr ), + .s15_sel_o( m2s15_sel ), + .s15_we_o( m2s15_we ), + .s15_cyc_o( m2s15_cyc ), + .s15_stb_o( m2s15_stb ), + .s15_ack_i( m2s15_ack ), + .s15_err_i( m2s15_err ), + .s15_rty_i( m2s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m3( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m3_data_i ), + .wb_data_o( m3_data_o ), + .wb_addr_i( m3_addr_i ), + .wb_sel_i( m3_sel_i ), + .wb_we_i( m3_we_i ), + .wb_cyc_i( m3_cyc_i ), + .wb_stb_i( m3_stb_i ), + .wb_ack_o( m3_ack_o ), + .wb_err_o( m3_err_o ), + .wb_rty_o( m3_rty_o ), + .s0_data_i( m3s0_data_i ), + .s0_data_o( m3s0_data_o ), + .s0_addr_o( m3s0_addr ), + .s0_sel_o( m3s0_sel ), + .s0_we_o( m3s0_we ), + .s0_cyc_o( m3s0_cyc ), + .s0_stb_o( m3s0_stb ), + .s0_ack_i( m3s0_ack ), + .s0_err_i( m3s0_err ), + .s0_rty_i( m3s0_rty ), + .s1_data_i( m3s1_data_i ), + .s1_data_o( m3s1_data_o ), + .s1_addr_o( m3s1_addr ), + .s1_sel_o( m3s1_sel ), + .s1_we_o( m3s1_we ), + .s1_cyc_o( m3s1_cyc ), + .s1_stb_o( m3s1_stb ), + .s1_ack_i( m3s1_ack ), + .s1_err_i( m3s1_err ), + .s1_rty_i( m3s1_rty ), + .s2_data_i( m3s2_data_i ), + .s2_data_o( m3s2_data_o ), + .s2_addr_o( m3s2_addr ), + .s2_sel_o( m3s2_sel ), + .s2_we_o( m3s2_we ), + .s2_cyc_o( m3s2_cyc ), + .s2_stb_o( m3s2_stb ), + .s2_ack_i( m3s2_ack ), + .s2_err_i( m3s2_err ), + .s2_rty_i( m3s2_rty ), + .s3_data_i( m3s3_data_i ), + .s3_data_o( m3s3_data_o ), + .s3_addr_o( m3s3_addr ), + .s3_sel_o( m3s3_sel ), + .s3_we_o( m3s3_we ), + .s3_cyc_o( m3s3_cyc ), + .s3_stb_o( m3s3_stb ), + .s3_ack_i( m3s3_ack ), + .s3_err_i( m3s3_err ), + .s3_rty_i( m3s3_rty ), + .s4_data_i( m3s4_data_i ), + .s4_data_o( m3s4_data_o ), + .s4_addr_o( m3s4_addr ), + .s4_sel_o( m3s4_sel ), + .s4_we_o( m3s4_we ), + .s4_cyc_o( m3s4_cyc ), + .s4_stb_o( m3s4_stb ), + .s4_ack_i( m3s4_ack ), + .s4_err_i( m3s4_err ), + .s4_rty_i( m3s4_rty ), + .s5_data_i( m3s5_data_i ), + .s5_data_o( m3s5_data_o ), + .s5_addr_o( m3s5_addr ), + .s5_sel_o( m3s5_sel ), + .s5_we_o( m3s5_we ), + .s5_cyc_o( m3s5_cyc ), + .s5_stb_o( m3s5_stb ), + .s5_ack_i( m3s5_ack ), + .s5_err_i( m3s5_err ), + .s5_rty_i( m3s5_rty ), + .s6_data_i( m3s6_data_i ), + .s6_data_o( m3s6_data_o ), + .s6_addr_o( m3s6_addr ), + .s6_sel_o( m3s6_sel ), + .s6_we_o( m3s6_we ), + .s6_cyc_o( m3s6_cyc ), + .s6_stb_o( m3s6_stb ), + .s6_ack_i( m3s6_ack ), + .s6_err_i( m3s6_err ), + .s6_rty_i( m3s6_rty ), + .s7_data_i( m3s7_data_i ), + .s7_data_o( m3s7_data_o ), + .s7_addr_o( m3s7_addr ), + .s7_sel_o( m3s7_sel ), + .s7_we_o( m3s7_we ), + .s7_cyc_o( m3s7_cyc ), + .s7_stb_o( m3s7_stb ), + .s7_ack_i( m3s7_ack ), + .s7_err_i( m3s7_err ), + .s7_rty_i( m3s7_rty ), + .s8_data_i( m3s8_data_i ), + .s8_data_o( m3s8_data_o ), + .s8_addr_o( m3s8_addr ), + .s8_sel_o( m3s8_sel ), + .s8_we_o( m3s8_we ), + .s8_cyc_o( m3s8_cyc ), + .s8_stb_o( m3s8_stb ), + .s8_ack_i( m3s8_ack ), + .s8_err_i( m3s8_err ), + .s8_rty_i( m3s8_rty ), + .s9_data_i( m3s9_data_i ), + .s9_data_o( m3s9_data_o ), + .s9_addr_o( m3s9_addr ), + .s9_sel_o( m3s9_sel ), + .s9_we_o( m3s9_we ), + .s9_cyc_o( m3s9_cyc ), + .s9_stb_o( m3s9_stb ), + .s9_ack_i( m3s9_ack ), + .s9_err_i( m3s9_err ), + .s9_rty_i( m3s9_rty ), + .s10_data_i( m3s10_data_i ), + .s10_data_o( m3s10_data_o ), + .s10_addr_o( m3s10_addr ), + .s10_sel_o( m3s10_sel ), + .s10_we_o( m3s10_we ), + .s10_cyc_o( m3s10_cyc ), + .s10_stb_o( m3s10_stb ), + .s10_ack_i( m3s10_ack ), + .s10_err_i( m3s10_err ), + .s10_rty_i( m3s10_rty ), + .s11_data_i( m3s11_data_i ), + .s11_data_o( m3s11_data_o ), + .s11_addr_o( m3s11_addr ), + .s11_sel_o( m3s11_sel ), + .s11_we_o( m3s11_we ), + .s11_cyc_o( m3s11_cyc ), + .s11_stb_o( m3s11_stb ), + .s11_ack_i( m3s11_ack ), + .s11_err_i( m3s11_err ), + .s11_rty_i( m3s11_rty ), + .s12_data_i( m3s12_data_i ), + .s12_data_o( m3s12_data_o ), + .s12_addr_o( m3s12_addr ), + .s12_sel_o( m3s12_sel ), + .s12_we_o( m3s12_we ), + .s12_cyc_o( m3s12_cyc ), + .s12_stb_o( m3s12_stb ), + .s12_ack_i( m3s12_ack ), + .s12_err_i( m3s12_err ), + .s12_rty_i( m3s12_rty ), + .s13_data_i( m3s13_data_i ), + .s13_data_o( m3s13_data_o ), + .s13_addr_o( m3s13_addr ), + .s13_sel_o( m3s13_sel ), + .s13_we_o( m3s13_we ), + .s13_cyc_o( m3s13_cyc ), + .s13_stb_o( m3s13_stb ), + .s13_ack_i( m3s13_ack ), + .s13_err_i( m3s13_err ), + .s13_rty_i( m3s13_rty ), + .s14_data_i( m3s14_data_i ), + .s14_data_o( m3s14_data_o ), + .s14_addr_o( m3s14_addr ), + .s14_sel_o( m3s14_sel ), + .s14_we_o( m3s14_we ), + .s14_cyc_o( m3s14_cyc ), + .s14_stb_o( m3s14_stb ), + .s14_ack_i( m3s14_ack ), + .s14_err_i( m3s14_err ), + .s14_rty_i( m3s14_rty ), + .s15_data_i( m3s15_data_i ), + .s15_data_o( m3s15_data_o ), + .s15_addr_o( m3s15_addr ), + .s15_sel_o( m3s15_sel ), + .s15_we_o( m3s15_we ), + .s15_cyc_o( m3s15_cyc ), + .s15_stb_o( m3s15_stb ), + .s15_ack_i( m3s15_ack ), + .s15_err_i( m3s15_err ), + .s15_rty_i( m3s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m4( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m4_data_i ), + .wb_data_o( m4_data_o ), + .wb_addr_i( m4_addr_i ), + .wb_sel_i( m4_sel_i ), + .wb_we_i( m4_we_i ), + .wb_cyc_i( m4_cyc_i ), + .wb_stb_i( m4_stb_i ), + .wb_ack_o( m4_ack_o ), + .wb_err_o( m4_err_o ), + .wb_rty_o( m4_rty_o ), + .s0_data_i( m4s0_data_i ), + .s0_data_o( m4s0_data_o ), + .s0_addr_o( m4s0_addr ), + .s0_sel_o( m4s0_sel ), + .s0_we_o( m4s0_we ), + .s0_cyc_o( m4s0_cyc ), + .s0_stb_o( m4s0_stb ), + .s0_ack_i( m4s0_ack ), + .s0_err_i( m4s0_err ), + .s0_rty_i( m4s0_rty ), + .s1_data_i( m4s1_data_i ), + .s1_data_o( m4s1_data_o ), + .s1_addr_o( m4s1_addr ), + .s1_sel_o( m4s1_sel ), + .s1_we_o( m4s1_we ), + .s1_cyc_o( m4s1_cyc ), + .s1_stb_o( m4s1_stb ), + .s1_ack_i( m4s1_ack ), + .s1_err_i( m4s1_err ), + .s1_rty_i( m4s1_rty ), + .s2_data_i( m4s2_data_i ), + .s2_data_o( m4s2_data_o ), + .s2_addr_o( m4s2_addr ), + .s2_sel_o( m4s2_sel ), + .s2_we_o( m4s2_we ), + .s2_cyc_o( m4s2_cyc ), + .s2_stb_o( m4s2_stb ), + .s2_ack_i( m4s2_ack ), + .s2_err_i( m4s2_err ), + .s2_rty_i( m4s2_rty ), + .s3_data_i( m4s3_data_i ), + .s3_data_o( m4s3_data_o ), + .s3_addr_o( m4s3_addr ), + .s3_sel_o( m4s3_sel ), + .s3_we_o( m4s3_we ), + .s3_cyc_o( m4s3_cyc ), + .s3_stb_o( m4s3_stb ), + .s3_ack_i( m4s3_ack ), + .s3_err_i( m4s3_err ), + .s3_rty_i( m4s3_rty ), + .s4_data_i( m4s4_data_i ), + .s4_data_o( m4s4_data_o ), + .s4_addr_o( m4s4_addr ), + .s4_sel_o( m4s4_sel ), + .s4_we_o( m4s4_we ), + .s4_cyc_o( m4s4_cyc ), + .s4_stb_o( m4s4_stb ), + .s4_ack_i( m4s4_ack ), + .s4_err_i( m4s4_err ), + .s4_rty_i( m4s4_rty ), + .s5_data_i( m4s5_data_i ), + .s5_data_o( m4s5_data_o ), + .s5_addr_o( m4s5_addr ), + .s5_sel_o( m4s5_sel ), + .s5_we_o( m4s5_we ), + .s5_cyc_o( m4s5_cyc ), + .s5_stb_o( m4s5_stb ), + .s5_ack_i( m4s5_ack ), + .s5_err_i( m4s5_err ), + .s5_rty_i( m4s5_rty ), + .s6_data_i( m4s6_data_i ), + .s6_data_o( m4s6_data_o ), + .s6_addr_o( m4s6_addr ), + .s6_sel_o( m4s6_sel ), + .s6_we_o( m4s6_we ), + .s6_cyc_o( m4s6_cyc ), + .s6_stb_o( m4s6_stb ), + .s6_ack_i( m4s6_ack ), + .s6_err_i( m4s6_err ), + .s6_rty_i( m4s6_rty ), + .s7_data_i( m4s7_data_i ), + .s7_data_o( m4s7_data_o ), + .s7_addr_o( m4s7_addr ), + .s7_sel_o( m4s7_sel ), + .s7_we_o( m4s7_we ), + .s7_cyc_o( m4s7_cyc ), + .s7_stb_o( m4s7_stb ), + .s7_ack_i( m4s7_ack ), + .s7_err_i( m4s7_err ), + .s7_rty_i( m4s7_rty ), + .s8_data_i( m4s8_data_i ), + .s8_data_o( m4s8_data_o ), + .s8_addr_o( m4s8_addr ), + .s8_sel_o( m4s8_sel ), + .s8_we_o( m4s8_we ), + .s8_cyc_o( m4s8_cyc ), + .s8_stb_o( m4s8_stb ), + .s8_ack_i( m4s8_ack ), + .s8_err_i( m4s8_err ), + .s8_rty_i( m4s8_rty ), + .s9_data_i( m4s9_data_i ), + .s9_data_o( m4s9_data_o ), + .s9_addr_o( m4s9_addr ), + .s9_sel_o( m4s9_sel ), + .s9_we_o( m4s9_we ), + .s9_cyc_o( m4s9_cyc ), + .s9_stb_o( m4s9_stb ), + .s9_ack_i( m4s9_ack ), + .s9_err_i( m4s9_err ), + .s9_rty_i( m4s9_rty ), + .s10_data_i( m4s10_data_i ), + .s10_data_o( m4s10_data_o ), + .s10_addr_o( m4s10_addr ), + .s10_sel_o( m4s10_sel ), + .s10_we_o( m4s10_we ), + .s10_cyc_o( m4s10_cyc ), + .s10_stb_o( m4s10_stb ), + .s10_ack_i( m4s10_ack ), + .s10_err_i( m4s10_err ), + .s10_rty_i( m4s10_rty ), + .s11_data_i( m4s11_data_i ), + .s11_data_o( m4s11_data_o ), + .s11_addr_o( m4s11_addr ), + .s11_sel_o( m4s11_sel ), + .s11_we_o( m4s11_we ), + .s11_cyc_o( m4s11_cyc ), + .s11_stb_o( m4s11_stb ), + .s11_ack_i( m4s11_ack ), + .s11_err_i( m4s11_err ), + .s11_rty_i( m4s11_rty ), + .s12_data_i( m4s12_data_i ), + .s12_data_o( m4s12_data_o ), + .s12_addr_o( m4s12_addr ), + .s12_sel_o( m4s12_sel ), + .s12_we_o( m4s12_we ), + .s12_cyc_o( m4s12_cyc ), + .s12_stb_o( m4s12_stb ), + .s12_ack_i( m4s12_ack ), + .s12_err_i( m4s12_err ), + .s12_rty_i( m4s12_rty ), + .s13_data_i( m4s13_data_i ), + .s13_data_o( m4s13_data_o ), + .s13_addr_o( m4s13_addr ), + .s13_sel_o( m4s13_sel ), + .s13_we_o( m4s13_we ), + .s13_cyc_o( m4s13_cyc ), + .s13_stb_o( m4s13_stb ), + .s13_ack_i( m4s13_ack ), + .s13_err_i( m4s13_err ), + .s13_rty_i( m4s13_rty ), + .s14_data_i( m4s14_data_i ), + .s14_data_o( m4s14_data_o ), + .s14_addr_o( m4s14_addr ), + .s14_sel_o( m4s14_sel ), + .s14_we_o( m4s14_we ), + .s14_cyc_o( m4s14_cyc ), + .s14_stb_o( m4s14_stb ), + .s14_ack_i( m4s14_ack ), + .s14_err_i( m4s14_err ), + .s14_rty_i( m4s14_rty ), + .s15_data_i( m4s15_data_i ), + .s15_data_o( m4s15_data_o ), + .s15_addr_o( m4s15_addr ), + .s15_sel_o( m4s15_sel ), + .s15_we_o( m4s15_we ), + .s15_cyc_o( m4s15_cyc ), + .s15_stb_o( m4s15_stb ), + .s15_ack_i( m4s15_ack ), + .s15_err_i( m4s15_err ), + .s15_rty_i( m4s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m5( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m5_data_i ), + .wb_data_o( m5_data_o ), + .wb_addr_i( m5_addr_i ), + .wb_sel_i( m5_sel_i ), + .wb_we_i( m5_we_i ), + .wb_cyc_i( m5_cyc_i ), + .wb_stb_i( m5_stb_i ), + .wb_ack_o( m5_ack_o ), + .wb_err_o( m5_err_o ), + .wb_rty_o( m5_rty_o ), + .s0_data_i( m5s0_data_i ), + .s0_data_o( m5s0_data_o ), + .s0_addr_o( m5s0_addr ), + .s0_sel_o( m5s0_sel ), + .s0_we_o( m5s0_we ), + .s0_cyc_o( m5s0_cyc ), + .s0_stb_o( m5s0_stb ), + .s0_ack_i( m5s0_ack ), + .s0_err_i( m5s0_err ), + .s0_rty_i( m5s0_rty ), + .s1_data_i( m5s1_data_i ), + .s1_data_o( m5s1_data_o ), + .s1_addr_o( m5s1_addr ), + .s1_sel_o( m5s1_sel ), + .s1_we_o( m5s1_we ), + .s1_cyc_o( m5s1_cyc ), + .s1_stb_o( m5s1_stb ), + .s1_ack_i( m5s1_ack ), + .s1_err_i( m5s1_err ), + .s1_rty_i( m5s1_rty ), + .s2_data_i( m5s2_data_i ), + .s2_data_o( m5s2_data_o ), + .s2_addr_o( m5s2_addr ), + .s2_sel_o( m5s2_sel ), + .s2_we_o( m5s2_we ), + .s2_cyc_o( m5s2_cyc ), + .s2_stb_o( m5s2_stb ), + .s2_ack_i( m5s2_ack ), + .s2_err_i( m5s2_err ), + .s2_rty_i( m5s2_rty ), + .s3_data_i( m5s3_data_i ), + .s3_data_o( m5s3_data_o ), + .s3_addr_o( m5s3_addr ), + .s3_sel_o( m5s3_sel ), + .s3_we_o( m5s3_we ), + .s3_cyc_o( m5s3_cyc ), + .s3_stb_o( m5s3_stb ), + .s3_ack_i( m5s3_ack ), + .s3_err_i( m5s3_err ), + .s3_rty_i( m5s3_rty ), + .s4_data_i( m5s4_data_i ), + .s4_data_o( m5s4_data_o ), + .s4_addr_o( m5s4_addr ), + .s4_sel_o( m5s4_sel ), + .s4_we_o( m5s4_we ), + .s4_cyc_o( m5s4_cyc ), + .s4_stb_o( m5s4_stb ), + .s4_ack_i( m5s4_ack ), + .s4_err_i( m5s4_err ), + .s4_rty_i( m5s4_rty ), + .s5_data_i( m5s5_data_i ), + .s5_data_o( m5s5_data_o ), + .s5_addr_o( m5s5_addr ), + .s5_sel_o( m5s5_sel ), + .s5_we_o( m5s5_we ), + .s5_cyc_o( m5s5_cyc ), + .s5_stb_o( m5s5_stb ), + .s5_ack_i( m5s5_ack ), + .s5_err_i( m5s5_err ), + .s5_rty_i( m5s5_rty ), + .s6_data_i( m5s6_data_i ), + .s6_data_o( m5s6_data_o ), + .s6_addr_o( m5s6_addr ), + .s6_sel_o( m5s6_sel ), + .s6_we_o( m5s6_we ), + .s6_cyc_o( m5s6_cyc ), + .s6_stb_o( m5s6_stb ), + .s6_ack_i( m5s6_ack ), + .s6_err_i( m5s6_err ), + .s6_rty_i( m5s6_rty ), + .s7_data_i( m5s7_data_i ), + .s7_data_o( m5s7_data_o ), + .s7_addr_o( m5s7_addr ), + .s7_sel_o( m5s7_sel ), + .s7_we_o( m5s7_we ), + .s7_cyc_o( m5s7_cyc ), + .s7_stb_o( m5s7_stb ), + .s7_ack_i( m5s7_ack ), + .s7_err_i( m5s7_err ), + .s7_rty_i( m5s7_rty ), + .s8_data_i( m5s8_data_i ), + .s8_data_o( m5s8_data_o ), + .s8_addr_o( m5s8_addr ), + .s8_sel_o( m5s8_sel ), + .s8_we_o( m5s8_we ), + .s8_cyc_o( m5s8_cyc ), + .s8_stb_o( m5s8_stb ), + .s8_ack_i( m5s8_ack ), + .s8_err_i( m5s8_err ), + .s8_rty_i( m5s8_rty ), + .s9_data_i( m5s9_data_i ), + .s9_data_o( m5s9_data_o ), + .s9_addr_o( m5s9_addr ), + .s9_sel_o( m5s9_sel ), + .s9_we_o( m5s9_we ), + .s9_cyc_o( m5s9_cyc ), + .s9_stb_o( m5s9_stb ), + .s9_ack_i( m5s9_ack ), + .s9_err_i( m5s9_err ), + .s9_rty_i( m5s9_rty ), + .s10_data_i( m5s10_data_i ), + .s10_data_o( m5s10_data_o ), + .s10_addr_o( m5s10_addr ), + .s10_sel_o( m5s10_sel ), + .s10_we_o( m5s10_we ), + .s10_cyc_o( m5s10_cyc ), + .s10_stb_o( m5s10_stb ), + .s10_ack_i( m5s10_ack ), + .s10_err_i( m5s10_err ), + .s10_rty_i( m5s10_rty ), + .s11_data_i( m5s11_data_i ), + .s11_data_o( m5s11_data_o ), + .s11_addr_o( m5s11_addr ), + .s11_sel_o( m5s11_sel ), + .s11_we_o( m5s11_we ), + .s11_cyc_o( m5s11_cyc ), + .s11_stb_o( m5s11_stb ), + .s11_ack_i( m5s11_ack ), + .s11_err_i( m5s11_err ), + .s11_rty_i( m5s11_rty ), + .s12_data_i( m5s12_data_i ), + .s12_data_o( m5s12_data_o ), + .s12_addr_o( m5s12_addr ), + .s12_sel_o( m5s12_sel ), + .s12_we_o( m5s12_we ), + .s12_cyc_o( m5s12_cyc ), + .s12_stb_o( m5s12_stb ), + .s12_ack_i( m5s12_ack ), + .s12_err_i( m5s12_err ), + .s12_rty_i( m5s12_rty ), + .s13_data_i( m5s13_data_i ), + .s13_data_o( m5s13_data_o ), + .s13_addr_o( m5s13_addr ), + .s13_sel_o( m5s13_sel ), + .s13_we_o( m5s13_we ), + .s13_cyc_o( m5s13_cyc ), + .s13_stb_o( m5s13_stb ), + .s13_ack_i( m5s13_ack ), + .s13_err_i( m5s13_err ), + .s13_rty_i( m5s13_rty ), + .s14_data_i( m5s14_data_i ), + .s14_data_o( m5s14_data_o ), + .s14_addr_o( m5s14_addr ), + .s14_sel_o( m5s14_sel ), + .s14_we_o( m5s14_we ), + .s14_cyc_o( m5s14_cyc ), + .s14_stb_o( m5s14_stb ), + .s14_ack_i( m5s14_ack ), + .s14_err_i( m5s14_err ), + .s14_rty_i( m5s14_rty ), + .s15_data_i( m5s15_data_i ), + .s15_data_o( m5s15_data_o ), + .s15_addr_o( m5s15_addr ), + .s15_sel_o( m5s15_sel ), + .s15_we_o( m5s15_we ), + .s15_cyc_o( m5s15_cyc ), + .s15_stb_o( m5s15_stb ), + .s15_ack_i( m5s15_ack ), + .s15_err_i( m5s15_err ), + .s15_rty_i( m5s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m6( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m6_data_i ), + .wb_data_o( m6_data_o ), + .wb_addr_i( m6_addr_i ), + .wb_sel_i( m6_sel_i ), + .wb_we_i( m6_we_i ), + .wb_cyc_i( m6_cyc_i ), + .wb_stb_i( m6_stb_i ), + .wb_ack_o( m6_ack_o ), + .wb_err_o( m6_err_o ), + .wb_rty_o( m6_rty_o ), + .s0_data_i( m6s0_data_i ), + .s0_data_o( m6s0_data_o ), + .s0_addr_o( m6s0_addr ), + .s0_sel_o( m6s0_sel ), + .s0_we_o( m6s0_we ), + .s0_cyc_o( m6s0_cyc ), + .s0_stb_o( m6s0_stb ), + .s0_ack_i( m6s0_ack ), + .s0_err_i( m6s0_err ), + .s0_rty_i( m6s0_rty ), + .s1_data_i( m6s1_data_i ), + .s1_data_o( m6s1_data_o ), + .s1_addr_o( m6s1_addr ), + .s1_sel_o( m6s1_sel ), + .s1_we_o( m6s1_we ), + .s1_cyc_o( m6s1_cyc ), + .s1_stb_o( m6s1_stb ), + .s1_ack_i( m6s1_ack ), + .s1_err_i( m6s1_err ), + .s1_rty_i( m6s1_rty ), + .s2_data_i( m6s2_data_i ), + .s2_data_o( m6s2_data_o ), + .s2_addr_o( m6s2_addr ), + .s2_sel_o( m6s2_sel ), + .s2_we_o( m6s2_we ), + .s2_cyc_o( m6s2_cyc ), + .s2_stb_o( m6s2_stb ), + .s2_ack_i( m6s2_ack ), + .s2_err_i( m6s2_err ), + .s2_rty_i( m6s2_rty ), + .s3_data_i( m6s3_data_i ), + .s3_data_o( m6s3_data_o ), + .s3_addr_o( m6s3_addr ), + .s3_sel_o( m6s3_sel ), + .s3_we_o( m6s3_we ), + .s3_cyc_o( m6s3_cyc ), + .s3_stb_o( m6s3_stb ), + .s3_ack_i( m6s3_ack ), + .s3_err_i( m6s3_err ), + .s3_rty_i( m6s3_rty ), + .s4_data_i( m6s4_data_i ), + .s4_data_o( m6s4_data_o ), + .s4_addr_o( m6s4_addr ), + .s4_sel_o( m6s4_sel ), + .s4_we_o( m6s4_we ), + .s4_cyc_o( m6s4_cyc ), + .s4_stb_o( m6s4_stb ), + .s4_ack_i( m6s4_ack ), + .s4_err_i( m6s4_err ), + .s4_rty_i( m6s4_rty ), + .s5_data_i( m6s5_data_i ), + .s5_data_o( m6s5_data_o ), + .s5_addr_o( m6s5_addr ), + .s5_sel_o( m6s5_sel ), + .s5_we_o( m6s5_we ), + .s5_cyc_o( m6s5_cyc ), + .s5_stb_o( m6s5_stb ), + .s5_ack_i( m6s5_ack ), + .s5_err_i( m6s5_err ), + .s5_rty_i( m6s5_rty ), + .s6_data_i( m6s6_data_i ), + .s6_data_o( m6s6_data_o ), + .s6_addr_o( m6s6_addr ), + .s6_sel_o( m6s6_sel ), + .s6_we_o( m6s6_we ), + .s6_cyc_o( m6s6_cyc ), + .s6_stb_o( m6s6_stb ), + .s6_ack_i( m6s6_ack ), + .s6_err_i( m6s6_err ), + .s6_rty_i( m6s6_rty ), + .s7_data_i( m6s7_data_i ), + .s7_data_o( m6s7_data_o ), + .s7_addr_o( m6s7_addr ), + .s7_sel_o( m6s7_sel ), + .s7_we_o( m6s7_we ), + .s7_cyc_o( m6s7_cyc ), + .s7_stb_o( m6s7_stb ), + .s7_ack_i( m6s7_ack ), + .s7_err_i( m6s7_err ), + .s7_rty_i( m6s7_rty ), + .s8_data_i( m6s8_data_i ), + .s8_data_o( m6s8_data_o ), + .s8_addr_o( m6s8_addr ), + .s8_sel_o( m6s8_sel ), + .s8_we_o( m6s8_we ), + .s8_cyc_o( m6s8_cyc ), + .s8_stb_o( m6s8_stb ), + .s8_ack_i( m6s8_ack ), + .s8_err_i( m6s8_err ), + .s8_rty_i( m6s8_rty ), + .s9_data_i( m6s9_data_i ), + .s9_data_o( m6s9_data_o ), + .s9_addr_o( m6s9_addr ), + .s9_sel_o( m6s9_sel ), + .s9_we_o( m6s9_we ), + .s9_cyc_o( m6s9_cyc ), + .s9_stb_o( m6s9_stb ), + .s9_ack_i( m6s9_ack ), + .s9_err_i( m6s9_err ), + .s9_rty_i( m6s9_rty ), + .s10_data_i( m6s10_data_i ), + .s10_data_o( m6s10_data_o ), + .s10_addr_o( m6s10_addr ), + .s10_sel_o( m6s10_sel ), + .s10_we_o( m6s10_we ), + .s10_cyc_o( m6s10_cyc ), + .s10_stb_o( m6s10_stb ), + .s10_ack_i( m6s10_ack ), + .s10_err_i( m6s10_err ), + .s10_rty_i( m6s10_rty ), + .s11_data_i( m6s11_data_i ), + .s11_data_o( m6s11_data_o ), + .s11_addr_o( m6s11_addr ), + .s11_sel_o( m6s11_sel ), + .s11_we_o( m6s11_we ), + .s11_cyc_o( m6s11_cyc ), + .s11_stb_o( m6s11_stb ), + .s11_ack_i( m6s11_ack ), + .s11_err_i( m6s11_err ), + .s11_rty_i( m6s11_rty ), + .s12_data_i( m6s12_data_i ), + .s12_data_o( m6s12_data_o ), + .s12_addr_o( m6s12_addr ), + .s12_sel_o( m6s12_sel ), + .s12_we_o( m6s12_we ), + .s12_cyc_o( m6s12_cyc ), + .s12_stb_o( m6s12_stb ), + .s12_ack_i( m6s12_ack ), + .s12_err_i( m6s12_err ), + .s12_rty_i( m6s12_rty ), + .s13_data_i( m6s13_data_i ), + .s13_data_o( m6s13_data_o ), + .s13_addr_o( m6s13_addr ), + .s13_sel_o( m6s13_sel ), + .s13_we_o( m6s13_we ), + .s13_cyc_o( m6s13_cyc ), + .s13_stb_o( m6s13_stb ), + .s13_ack_i( m6s13_ack ), + .s13_err_i( m6s13_err ), + .s13_rty_i( m6s13_rty ), + .s14_data_i( m6s14_data_i ), + .s14_data_o( m6s14_data_o ), + .s14_addr_o( m6s14_addr ), + .s14_sel_o( m6s14_sel ), + .s14_we_o( m6s14_we ), + .s14_cyc_o( m6s14_cyc ), + .s14_stb_o( m6s14_stb ), + .s14_ack_i( m6s14_ack ), + .s14_err_i( m6s14_err ), + .s14_rty_i( m6s14_rty ), + .s15_data_i( m6s15_data_i ), + .s15_data_o( m6s15_data_o ), + .s15_addr_o( m6s15_addr ), + .s15_sel_o( m6s15_sel ), + .s15_we_o( m6s15_we ), + .s15_cyc_o( m6s15_cyc ), + .s15_stb_o( m6s15_stb ), + .s15_ack_i( m6s15_ack ), + .s15_err_i( m6s15_err ), + .s15_rty_i( m6s15_rty ) + ); + +wb_conmax_master_if #(dw,aw,sw) m7( + .clk_i( clk_i ), + .rst_i( rst_i ), + .wb_data_i( m7_data_i ), + .wb_data_o( m7_data_o ), + .wb_addr_i( m7_addr_i ), + .wb_sel_i( m7_sel_i ), + .wb_we_i( m7_we_i ), + .wb_cyc_i( m7_cyc_i ), + .wb_stb_i( m7_stb_i ), + .wb_ack_o( m7_ack_o ), + .wb_err_o( m7_err_o ), + .wb_rty_o( m7_rty_o ), + .s0_data_i( m7s0_data_i ), + .s0_data_o( m7s0_data_o ), + .s0_addr_o( m7s0_addr ), + .s0_sel_o( m7s0_sel ), + .s0_we_o( m7s0_we ), + .s0_cyc_o( m7s0_cyc ), + .s0_stb_o( m7s0_stb ), + .s0_ack_i( m7s0_ack ), + .s0_err_i( m7s0_err ), + .s0_rty_i( m7s0_rty ), + .s1_data_i( m7s1_data_i ), + .s1_data_o( m7s1_data_o ), + .s1_addr_o( m7s1_addr ), + .s1_sel_o( m7s1_sel ), + .s1_we_o( m7s1_we ), + .s1_cyc_o( m7s1_cyc ), + .s1_stb_o( m7s1_stb ), + .s1_ack_i( m7s1_ack ), + .s1_err_i( m7s1_err ), + .s1_rty_i( m7s1_rty ), + .s2_data_i( m7s2_data_i ), + .s2_data_o( m7s2_data_o ), + .s2_addr_o( m7s2_addr ), + .s2_sel_o( m7s2_sel ), + .s2_we_o( m7s2_we ), + .s2_cyc_o( m7s2_cyc ), + .s2_stb_o( m7s2_stb ), + .s2_ack_i( m7s2_ack ), + .s2_err_i( m7s2_err ), + .s2_rty_i( m7s2_rty ), + .s3_data_i( m7s3_data_i ), + .s3_data_o( m7s3_data_o ), + .s3_addr_o( m7s3_addr ), + .s3_sel_o( m7s3_sel ), + .s3_we_o( m7s3_we ), + .s3_cyc_o( m7s3_cyc ), + .s3_stb_o( m7s3_stb ), + .s3_ack_i( m7s3_ack ), + .s3_err_i( m7s3_err ), + .s3_rty_i( m7s3_rty ), + .s4_data_i( m7s4_data_i ), + .s4_data_o( m7s4_data_o ), + .s4_addr_o( m7s4_addr ), + .s4_sel_o( m7s4_sel ), + .s4_we_o( m7s4_we ), + .s4_cyc_o( m7s4_cyc ), + .s4_stb_o( m7s4_stb ), + .s4_ack_i( m7s4_ack ), + .s4_err_i( m7s4_err ), + .s4_rty_i( m7s4_rty ), + .s5_data_i( m7s5_data_i ), + .s5_data_o( m7s5_data_o ), + .s5_addr_o( m7s5_addr ), + .s5_sel_o( m7s5_sel ), + .s5_we_o( m7s5_we ), + .s5_cyc_o( m7s5_cyc ), + .s5_stb_o( m7s5_stb ), + .s5_ack_i( m7s5_ack ), + .s5_err_i( m7s5_err ), + .s5_rty_i( m7s5_rty ), + .s6_data_i( m7s6_data_i ), + .s6_data_o( m7s6_data_o ), + .s6_addr_o( m7s6_addr ), + .s6_sel_o( m7s6_sel ), + .s6_we_o( m7s6_we ), + .s6_cyc_o( m7s6_cyc ), + .s6_stb_o( m7s6_stb ), + .s6_ack_i( m7s6_ack ), + .s6_err_i( m7s6_err ), + .s6_rty_i( m7s6_rty ), + .s7_data_i( m7s7_data_i ), + .s7_data_o( m7s7_data_o ), + .s7_addr_o( m7s7_addr ), + .s7_sel_o( m7s7_sel ), + .s7_we_o( m7s7_we ), + .s7_cyc_o( m7s7_cyc ), + .s7_stb_o( m7s7_stb ), + .s7_ack_i( m7s7_ack ), + .s7_err_i( m7s7_err ), + .s7_rty_i( m7s7_rty ), + .s8_data_i( m7s8_data_i ), + .s8_data_o( m7s8_data_o ), + .s8_addr_o( m7s8_addr ), + .s8_sel_o( m7s8_sel ), + .s8_we_o( m7s8_we ), + .s8_cyc_o( m7s8_cyc ), + .s8_stb_o( m7s8_stb ), + .s8_ack_i( m7s8_ack ), + .s8_err_i( m7s8_err ), + .s8_rty_i( m7s8_rty ), + .s9_data_i( m7s9_data_i ), + .s9_data_o( m7s9_data_o ), + .s9_addr_o( m7s9_addr ), + .s9_sel_o( m7s9_sel ), + .s9_we_o( m7s9_we ), + .s9_cyc_o( m7s9_cyc ), + .s9_stb_o( m7s9_stb ), + .s9_ack_i( m7s9_ack ), + .s9_err_i( m7s9_err ), + .s9_rty_i( m7s9_rty ), + .s10_data_i( m7s10_data_i ), + .s10_data_o( m7s10_data_o ), + .s10_addr_o( m7s10_addr ), + .s10_sel_o( m7s10_sel ), + .s10_we_o( m7s10_we ), + .s10_cyc_o( m7s10_cyc ), + .s10_stb_o( m7s10_stb ), + .s10_ack_i( m7s10_ack ), + .s10_err_i( m7s10_err ), + .s10_rty_i( m7s10_rty ), + .s11_data_i( m7s11_data_i ), + .s11_data_o( m7s11_data_o ), + .s11_addr_o( m7s11_addr ), + .s11_sel_o( m7s11_sel ), + .s11_we_o( m7s11_we ), + .s11_cyc_o( m7s11_cyc ), + .s11_stb_o( m7s11_stb ), + .s11_ack_i( m7s11_ack ), + .s11_err_i( m7s11_err ), + .s11_rty_i( m7s11_rty ), + .s12_data_i( m7s12_data_i ), + .s12_data_o( m7s12_data_o ), + .s12_addr_o( m7s12_addr ), + .s12_sel_o( m7s12_sel ), + .s12_we_o( m7s12_we ), + .s12_cyc_o( m7s12_cyc ), + .s12_stb_o( m7s12_stb ), + .s12_ack_i( m7s12_ack ), + .s12_err_i( m7s12_err ), + .s12_rty_i( m7s12_rty ), + .s13_data_i( m7s13_data_i ), + .s13_data_o( m7s13_data_o ), + .s13_addr_o( m7s13_addr ), + .s13_sel_o( m7s13_sel ), + .s13_we_o( m7s13_we ), + .s13_cyc_o( m7s13_cyc ), + .s13_stb_o( m7s13_stb ), + .s13_ack_i( m7s13_ack ), + .s13_err_i( m7s13_err ), + .s13_rty_i( m7s13_rty ), + .s14_data_i( m7s14_data_i ), + .s14_data_o( m7s14_data_o ), + .s14_addr_o( m7s14_addr ), + .s14_sel_o( m7s14_sel ), + .s14_we_o( m7s14_we ), + .s14_cyc_o( m7s14_cyc ), + .s14_stb_o( m7s14_stb ), + .s14_ack_i( m7s14_ack ), + .s14_err_i( m7s14_err ), + .s14_rty_i( m7s14_rty ), + .s15_data_i( m7s15_data_i ), + .s15_data_o( m7s15_data_o ), + .s15_addr_o( m7s15_addr ), + .s15_sel_o( m7s15_sel ), + .s15_we_o( m7s15_we ), + .s15_cyc_o( m7s15_cyc ), + .s15_stb_o( m7s15_stb ), + .s15_ack_i( m7s15_ack ), + .s15_err_i( m7s15_err ), + .s15_rty_i( m7s15_rty ) + ); + +//////////////////////////////////////////////////////////////////// +// +// Slave Interfaces +// + +wb_conmax_slave_if #(pri_sel0,aw,dw,sw) s0( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf0 ), + .wb_data_i( s0_data_i ), + .wb_data_o( s0_data_o ), + .wb_addr_o( s0_addr_o ), + .wb_sel_o( s0_sel_o ), + .wb_we_o( s0_we_o ), + .wb_cyc_o( s0_cyc_o ), + .wb_stb_o( s0_stb_o ), + .wb_ack_i( s0_ack_i ), + .wb_err_i( s0_err_i ), + .wb_rty_i( s0_rty_i ), + .m0_data_i( m0s0_data_o ), + .m0_data_o( m0s0_data_i ), + .m0_addr_i( m0s0_addr ), + .m0_sel_i( m0s0_sel ), + .m0_we_i( m0s0_we ), + .m0_cyc_i( m0s0_cyc ), + .m0_stb_i( m0s0_stb ), + .m0_ack_o( m0s0_ack ), + .m0_err_o( m0s0_err ), + .m0_rty_o( m0s0_rty ), + .m1_data_i( m1s0_data_o ), + .m1_data_o( m1s0_data_i ), + .m1_addr_i( m1s0_addr ), + .m1_sel_i( m1s0_sel ), + .m1_we_i( m1s0_we ), + .m1_cyc_i( m1s0_cyc ), + .m1_stb_i( m1s0_stb ), + .m1_ack_o( m1s0_ack ), + .m1_err_o( m1s0_err ), + .m1_rty_o( m1s0_rty ), + .m2_data_i( m2s0_data_o ), + .m2_data_o( m2s0_data_i ), + .m2_addr_i( m2s0_addr ), + .m2_sel_i( m2s0_sel ), + .m2_we_i( m2s0_we ), + .m2_cyc_i( m2s0_cyc ), + .m2_stb_i( m2s0_stb ), + .m2_ack_o( m2s0_ack ), + .m2_err_o( m2s0_err ), + .m2_rty_o( m2s0_rty ), + .m3_data_i( m3s0_data_o ), + .m3_data_o( m3s0_data_i ), + .m3_addr_i( m3s0_addr ), + .m3_sel_i( m3s0_sel ), + .m3_we_i( m3s0_we ), + .m3_cyc_i( m3s0_cyc ), + .m3_stb_i( m3s0_stb ), + .m3_ack_o( m3s0_ack ), + .m3_err_o( m3s0_err ), + .m3_rty_o( m3s0_rty ), + .m4_data_i( m4s0_data_o ), + .m4_data_o( m4s0_data_i ), + .m4_addr_i( m4s0_addr ), + .m4_sel_i( m4s0_sel ), + .m4_we_i( m4s0_we ), + .m4_cyc_i( m4s0_cyc ), + .m4_stb_i( m4s0_stb ), + .m4_ack_o( m4s0_ack ), + .m4_err_o( m4s0_err ), + .m4_rty_o( m4s0_rty ), + .m5_data_i( m5s0_data_o ), + .m5_data_o( m5s0_data_i ), + .m5_addr_i( m5s0_addr ), + .m5_sel_i( m5s0_sel ), + .m5_we_i( m5s0_we ), + .m5_cyc_i( m5s0_cyc ), + .m5_stb_i( m5s0_stb ), + .m5_ack_o( m5s0_ack ), + .m5_err_o( m5s0_err ), + .m5_rty_o( m5s0_rty ), + .m6_data_i( m6s0_data_o ), + .m6_data_o( m6s0_data_i ), + .m6_addr_i( m6s0_addr ), + .m6_sel_i( m6s0_sel ), + .m6_we_i( m6s0_we ), + .m6_cyc_i( m6s0_cyc ), + .m6_stb_i( m6s0_stb ), + .m6_ack_o( m6s0_ack ), + .m6_err_o( m6s0_err ), + .m6_rty_o( m6s0_rty ), + .m7_data_i( m7s0_data_o ), + .m7_data_o( m7s0_data_i ), + .m7_addr_i( m7s0_addr ), + .m7_sel_i( m7s0_sel ), + .m7_we_i( m7s0_we ), + .m7_cyc_i( m7s0_cyc ), + .m7_stb_i( m7s0_stb ), + .m7_ack_o( m7s0_ack ), + .m7_err_o( m7s0_err ), + .m7_rty_o( m7s0_rty ) + ); + +wb_conmax_slave_if #(pri_sel1,aw,dw,sw) s1( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf1 ), + .wb_data_i( s1_data_i ), + .wb_data_o( s1_data_o ), + .wb_addr_o( s1_addr_o ), + .wb_sel_o( s1_sel_o ), + .wb_we_o( s1_we_o ), + .wb_cyc_o( s1_cyc_o ), + .wb_stb_o( s1_stb_o ), + .wb_ack_i( s1_ack_i ), + .wb_err_i( s1_err_i ), + .wb_rty_i( s1_rty_i ), + .m0_data_i( m0s1_data_o ), + .m0_data_o( m0s1_data_i ), + .m0_addr_i( m0s1_addr ), + .m0_sel_i( m0s1_sel ), + .m0_we_i( m0s1_we ), + .m0_cyc_i( m0s1_cyc ), + .m0_stb_i( m0s1_stb ), + .m0_ack_o( m0s1_ack ), + .m0_err_o( m0s1_err ), + .m0_rty_o( m0s1_rty ), + .m1_data_i( m1s1_data_o ), + .m1_data_o( m1s1_data_i ), + .m1_addr_i( m1s1_addr ), + .m1_sel_i( m1s1_sel ), + .m1_we_i( m1s1_we ), + .m1_cyc_i( m1s1_cyc ), + .m1_stb_i( m1s1_stb ), + .m1_ack_o( m1s1_ack ), + .m1_err_o( m1s1_err ), + .m1_rty_o( m1s1_rty ), + .m2_data_i( m2s1_data_o ), + .m2_data_o( m2s1_data_i ), + .m2_addr_i( m2s1_addr ), + .m2_sel_i( m2s1_sel ), + .m2_we_i( m2s1_we ), + .m2_cyc_i( m2s1_cyc ), + .m2_stb_i( m2s1_stb ), + .m2_ack_o( m2s1_ack ), + .m2_err_o( m2s1_err ), + .m2_rty_o( m2s1_rty ), + .m3_data_i( m3s1_data_o ), + .m3_data_o( m3s1_data_i ), + .m3_addr_i( m3s1_addr ), + .m3_sel_i( m3s1_sel ), + .m3_we_i( m3s1_we ), + .m3_cyc_i( m3s1_cyc ), + .m3_stb_i( m3s1_stb ), + .m3_ack_o( m3s1_ack ), + .m3_err_o( m3s1_err ), + .m3_rty_o( m3s1_rty ), + .m4_data_i( m4s1_data_o ), + .m4_data_o( m4s1_data_i ), + .m4_addr_i( m4s1_addr ), + .m4_sel_i( m4s1_sel ), + .m4_we_i( m4s1_we ), + .m4_cyc_i( m4s1_cyc ), + .m4_stb_i( m4s1_stb ), + .m4_ack_o( m4s1_ack ), + .m4_err_o( m4s1_err ), + .m4_rty_o( m4s1_rty ), + .m5_data_i( m5s1_data_o ), + .m5_data_o( m5s1_data_i ), + .m5_addr_i( m5s1_addr ), + .m5_sel_i( m5s1_sel ), + .m5_we_i( m5s1_we ), + .m5_cyc_i( m5s1_cyc ), + .m5_stb_i( m5s1_stb ), + .m5_ack_o( m5s1_ack ), + .m5_err_o( m5s1_err ), + .m5_rty_o( m5s1_rty ), + .m6_data_i( m6s1_data_o ), + .m6_data_o( m6s1_data_i ), + .m6_addr_i( m6s1_addr ), + .m6_sel_i( m6s1_sel ), + .m6_we_i( m6s1_we ), + .m6_cyc_i( m6s1_cyc ), + .m6_stb_i( m6s1_stb ), + .m6_ack_o( m6s1_ack ), + .m6_err_o( m6s1_err ), + .m6_rty_o( m6s1_rty ), + .m7_data_i( m7s1_data_o ), + .m7_data_o( m7s1_data_i ), + .m7_addr_i( m7s1_addr ), + .m7_sel_i( m7s1_sel ), + .m7_we_i( m7s1_we ), + .m7_cyc_i( m7s1_cyc ), + .m7_stb_i( m7s1_stb ), + .m7_ack_o( m7s1_ack ), + .m7_err_o( m7s1_err ), + .m7_rty_o( m7s1_rty ) + ); + +wb_conmax_slave_if #(pri_sel2,aw,dw,sw) s2( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf2 ), + .wb_data_i( s2_data_i ), + .wb_data_o( s2_data_o ), + .wb_addr_o( s2_addr_o ), + .wb_sel_o( s2_sel_o ), + .wb_we_o( s2_we_o ), + .wb_cyc_o( s2_cyc_o ), + .wb_stb_o( s2_stb_o ), + .wb_ack_i( s2_ack_i ), + .wb_err_i( s2_err_i ), + .wb_rty_i( s2_rty_i ), + .m0_data_i( m0s2_data_o ), + .m0_data_o( m0s2_data_i ), + .m0_addr_i( m0s2_addr ), + .m0_sel_i( m0s2_sel ), + .m0_we_i( m0s2_we ), + .m0_cyc_i( m0s2_cyc ), + .m0_stb_i( m0s2_stb ), + .m0_ack_o( m0s2_ack ), + .m0_err_o( m0s2_err ), + .m0_rty_o( m0s2_rty ), + .m1_data_i( m1s2_data_o ), + .m1_data_o( m1s2_data_i ), + .m1_addr_i( m1s2_addr ), + .m1_sel_i( m1s2_sel ), + .m1_we_i( m1s2_we ), + .m1_cyc_i( m1s2_cyc ), + .m1_stb_i( m1s2_stb ), + .m1_ack_o( m1s2_ack ), + .m1_err_o( m1s2_err ), + .m1_rty_o( m1s2_rty ), + .m2_data_i( m2s2_data_o ), + .m2_data_o( m2s2_data_i ), + .m2_addr_i( m2s2_addr ), + .m2_sel_i( m2s2_sel ), + .m2_we_i( m2s2_we ), + .m2_cyc_i( m2s2_cyc ), + .m2_stb_i( m2s2_stb ), + .m2_ack_o( m2s2_ack ), + .m2_err_o( m2s2_err ), + .m2_rty_o( m2s2_rty ), + .m3_data_i( m3s2_data_o ), + .m3_data_o( m3s2_data_i ), + .m3_addr_i( m3s2_addr ), + .m3_sel_i( m3s2_sel ), + .m3_we_i( m3s2_we ), + .m3_cyc_i( m3s2_cyc ), + .m3_stb_i( m3s2_stb ), + .m3_ack_o( m3s2_ack ), + .m3_err_o( m3s2_err ), + .m3_rty_o( m3s2_rty ), + .m4_data_i( m4s2_data_o ), + .m4_data_o( m4s2_data_i ), + .m4_addr_i( m4s2_addr ), + .m4_sel_i( m4s2_sel ), + .m4_we_i( m4s2_we ), + .m4_cyc_i( m4s2_cyc ), + .m4_stb_i( m4s2_stb ), + .m4_ack_o( m4s2_ack ), + .m4_err_o( m4s2_err ), + .m4_rty_o( m4s2_rty ), + .m5_data_i( m5s2_data_o ), + .m5_data_o( m5s2_data_i ), + .m5_addr_i( m5s2_addr ), + .m5_sel_i( m5s2_sel ), + .m5_we_i( m5s2_we ), + .m5_cyc_i( m5s2_cyc ), + .m5_stb_i( m5s2_stb ), + .m5_ack_o( m5s2_ack ), + .m5_err_o( m5s2_err ), + .m5_rty_o( m5s2_rty ), + .m6_data_i( m6s2_data_o ), + .m6_data_o( m6s2_data_i ), + .m6_addr_i( m6s2_addr ), + .m6_sel_i( m6s2_sel ), + .m6_we_i( m6s2_we ), + .m6_cyc_i( m6s2_cyc ), + .m6_stb_i( m6s2_stb ), + .m6_ack_o( m6s2_ack ), + .m6_err_o( m6s2_err ), + .m6_rty_o( m6s2_rty ), + .m7_data_i( m7s2_data_o ), + .m7_data_o( m7s2_data_i ), + .m7_addr_i( m7s2_addr ), + .m7_sel_i( m7s2_sel ), + .m7_we_i( m7s2_we ), + .m7_cyc_i( m7s2_cyc ), + .m7_stb_i( m7s2_stb ), + .m7_ack_o( m7s2_ack ), + .m7_err_o( m7s2_err ), + .m7_rty_o( m7s2_rty ) + ); + +wb_conmax_slave_if #(pri_sel3,aw,dw,sw) s3( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf3 ), + .wb_data_i( s3_data_i ), + .wb_data_o( s3_data_o ), + .wb_addr_o( s3_addr_o ), + .wb_sel_o( s3_sel_o ), + .wb_we_o( s3_we_o ), + .wb_cyc_o( s3_cyc_o ), + .wb_stb_o( s3_stb_o ), + .wb_ack_i( s3_ack_i ), + .wb_err_i( s3_err_i ), + .wb_rty_i( s3_rty_i ), + .m0_data_i( m0s3_data_o ), + .m0_data_o( m0s3_data_i ), + .m0_addr_i( m0s3_addr ), + .m0_sel_i( m0s3_sel ), + .m0_we_i( m0s3_we ), + .m0_cyc_i( m0s3_cyc ), + .m0_stb_i( m0s3_stb ), + .m0_ack_o( m0s3_ack ), + .m0_err_o( m0s3_err ), + .m0_rty_o( m0s3_rty ), + .m1_data_i( m1s3_data_o ), + .m1_data_o( m1s3_data_i ), + .m1_addr_i( m1s3_addr ), + .m1_sel_i( m1s3_sel ), + .m1_we_i( m1s3_we ), + .m1_cyc_i( m1s3_cyc ), + .m1_stb_i( m1s3_stb ), + .m1_ack_o( m1s3_ack ), + .m1_err_o( m1s3_err ), + .m1_rty_o( m1s3_rty ), + .m2_data_i( m2s3_data_o ), + .m2_data_o( m2s3_data_i ), + .m2_addr_i( m2s3_addr ), + .m2_sel_i( m2s3_sel ), + .m2_we_i( m2s3_we ), + .m2_cyc_i( m2s3_cyc ), + .m2_stb_i( m2s3_stb ), + .m2_ack_o( m2s3_ack ), + .m2_err_o( m2s3_err ), + .m2_rty_o( m2s3_rty ), + .m3_data_i( m3s3_data_o ), + .m3_data_o( m3s3_data_i ), + .m3_addr_i( m3s3_addr ), + .m3_sel_i( m3s3_sel ), + .m3_we_i( m3s3_we ), + .m3_cyc_i( m3s3_cyc ), + .m3_stb_i( m3s3_stb ), + .m3_ack_o( m3s3_ack ), + .m3_err_o( m3s3_err ), + .m3_rty_o( m3s3_rty ), + .m4_data_i( m4s3_data_o ), + .m4_data_o( m4s3_data_i ), + .m4_addr_i( m4s3_addr ), + .m4_sel_i( m4s3_sel ), + .m4_we_i( m4s3_we ), + .m4_cyc_i( m4s3_cyc ), + .m4_stb_i( m4s3_stb ), + .m4_ack_o( m4s3_ack ), + .m4_err_o( m4s3_err ), + .m4_rty_o( m4s3_rty ), + .m5_data_i( m5s3_data_o ), + .m5_data_o( m5s3_data_i ), + .m5_addr_i( m5s3_addr ), + .m5_sel_i( m5s3_sel ), + .m5_we_i( m5s3_we ), + .m5_cyc_i( m5s3_cyc ), + .m5_stb_i( m5s3_stb ), + .m5_ack_o( m5s3_ack ), + .m5_err_o( m5s3_err ), + .m5_rty_o( m5s3_rty ), + .m6_data_i( m6s3_data_o ), + .m6_data_o( m6s3_data_i ), + .m6_addr_i( m6s3_addr ), + .m6_sel_i( m6s3_sel ), + .m6_we_i( m6s3_we ), + .m6_cyc_i( m6s3_cyc ), + .m6_stb_i( m6s3_stb ), + .m6_ack_o( m6s3_ack ), + .m6_err_o( m6s3_err ), + .m6_rty_o( m6s3_rty ), + .m7_data_i( m7s3_data_o ), + .m7_data_o( m7s3_data_i ), + .m7_addr_i( m7s3_addr ), + .m7_sel_i( m7s3_sel ), + .m7_we_i( m7s3_we ), + .m7_cyc_i( m7s3_cyc ), + .m7_stb_i( m7s3_stb ), + .m7_ack_o( m7s3_ack ), + .m7_err_o( m7s3_err ), + .m7_rty_o( m7s3_rty ) + ); + +wb_conmax_slave_if #(pri_sel4,aw,dw,sw) s4( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf4 ), + .wb_data_i( s4_data_i ), + .wb_data_o( s4_data_o ), + .wb_addr_o( s4_addr_o ), + .wb_sel_o( s4_sel_o ), + .wb_we_o( s4_we_o ), + .wb_cyc_o( s4_cyc_o ), + .wb_stb_o( s4_stb_o ), + .wb_ack_i( s4_ack_i ), + .wb_err_i( s4_err_i ), + .wb_rty_i( s4_rty_i ), + .m0_data_i( m0s4_data_o ), + .m0_data_o( m0s4_data_i ), + .m0_addr_i( m0s4_addr ), + .m0_sel_i( m0s4_sel ), + .m0_we_i( m0s4_we ), + .m0_cyc_i( m0s4_cyc ), + .m0_stb_i( m0s4_stb ), + .m0_ack_o( m0s4_ack ), + .m0_err_o( m0s4_err ), + .m0_rty_o( m0s4_rty ), + .m1_data_i( m1s4_data_o ), + .m1_data_o( m1s4_data_i ), + .m1_addr_i( m1s4_addr ), + .m1_sel_i( m1s4_sel ), + .m1_we_i( m1s4_we ), + .m1_cyc_i( m1s4_cyc ), + .m1_stb_i( m1s4_stb ), + .m1_ack_o( m1s4_ack ), + .m1_err_o( m1s4_err ), + .m1_rty_o( m1s4_rty ), + .m2_data_i( m2s4_data_o ), + .m2_data_o( m2s4_data_i ), + .m2_addr_i( m2s4_addr ), + .m2_sel_i( m2s4_sel ), + .m2_we_i( m2s4_we ), + .m2_cyc_i( m2s4_cyc ), + .m2_stb_i( m2s4_stb ), + .m2_ack_o( m2s4_ack ), + .m2_err_o( m2s4_err ), + .m2_rty_o( m2s4_rty ), + .m3_data_i( m3s4_data_o ), + .m3_data_o( m3s4_data_i ), + .m3_addr_i( m3s4_addr ), + .m3_sel_i( m3s4_sel ), + .m3_we_i( m3s4_we ), + .m3_cyc_i( m3s4_cyc ), + .m3_stb_i( m3s4_stb ), + .m3_ack_o( m3s4_ack ), + .m3_err_o( m3s4_err ), + .m3_rty_o( m3s4_rty ), + .m4_data_i( m4s4_data_o ), + .m4_data_o( m4s4_data_i ), + .m4_addr_i( m4s4_addr ), + .m4_sel_i( m4s4_sel ), + .m4_we_i( m4s4_we ), + .m4_cyc_i( m4s4_cyc ), + .m4_stb_i( m4s4_stb ), + .m4_ack_o( m4s4_ack ), + .m4_err_o( m4s4_err ), + .m4_rty_o( m4s4_rty ), + .m5_data_i( m5s4_data_o ), + .m5_data_o( m5s4_data_i ), + .m5_addr_i( m5s4_addr ), + .m5_sel_i( m5s4_sel ), + .m5_we_i( m5s4_we ), + .m5_cyc_i( m5s4_cyc ), + .m5_stb_i( m5s4_stb ), + .m5_ack_o( m5s4_ack ), + .m5_err_o( m5s4_err ), + .m5_rty_o( m5s4_rty ), + .m6_data_i( m6s4_data_o ), + .m6_data_o( m6s4_data_i ), + .m6_addr_i( m6s4_addr ), + .m6_sel_i( m6s4_sel ), + .m6_we_i( m6s4_we ), + .m6_cyc_i( m6s4_cyc ), + .m6_stb_i( m6s4_stb ), + .m6_ack_o( m6s4_ack ), + .m6_err_o( m6s4_err ), + .m6_rty_o( m6s4_rty ), + .m7_data_i( m7s4_data_o ), + .m7_data_o( m7s4_data_i ), + .m7_addr_i( m7s4_addr ), + .m7_sel_i( m7s4_sel ), + .m7_we_i( m7s4_we ), + .m7_cyc_i( m7s4_cyc ), + .m7_stb_i( m7s4_stb ), + .m7_ack_o( m7s4_ack ), + .m7_err_o( m7s4_err ), + .m7_rty_o( m7s4_rty ) + ); + +wb_conmax_slave_if #(pri_sel5,aw,dw,sw) s5( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf5 ), + .wb_data_i( s5_data_i ), + .wb_data_o( s5_data_o ), + .wb_addr_o( s5_addr_o ), + .wb_sel_o( s5_sel_o ), + .wb_we_o( s5_we_o ), + .wb_cyc_o( s5_cyc_o ), + .wb_stb_o( s5_stb_o ), + .wb_ack_i( s5_ack_i ), + .wb_err_i( s5_err_i ), + .wb_rty_i( s5_rty_i ), + .m0_data_i( m0s5_data_o ), + .m0_data_o( m0s5_data_i ), + .m0_addr_i( m0s5_addr ), + .m0_sel_i( m0s5_sel ), + .m0_we_i( m0s5_we ), + .m0_cyc_i( m0s5_cyc ), + .m0_stb_i( m0s5_stb ), + .m0_ack_o( m0s5_ack ), + .m0_err_o( m0s5_err ), + .m0_rty_o( m0s5_rty ), + .m1_data_i( m1s5_data_o ), + .m1_data_o( m1s5_data_i ), + .m1_addr_i( m1s5_addr ), + .m1_sel_i( m1s5_sel ), + .m1_we_i( m1s5_we ), + .m1_cyc_i( m1s5_cyc ), + .m1_stb_i( m1s5_stb ), + .m1_ack_o( m1s5_ack ), + .m1_err_o( m1s5_err ), + .m1_rty_o( m1s5_rty ), + .m2_data_i( m2s5_data_o ), + .m2_data_o( m2s5_data_i ), + .m2_addr_i( m2s5_addr ), + .m2_sel_i( m2s5_sel ), + .m2_we_i( m2s5_we ), + .m2_cyc_i( m2s5_cyc ), + .m2_stb_i( m2s5_stb ), + .m2_ack_o( m2s5_ack ), + .m2_err_o( m2s5_err ), + .m2_rty_o( m2s5_rty ), + .m3_data_i( m3s5_data_o ), + .m3_data_o( m3s5_data_i ), + .m3_addr_i( m3s5_addr ), + .m3_sel_i( m3s5_sel ), + .m3_we_i( m3s5_we ), + .m3_cyc_i( m3s5_cyc ), + .m3_stb_i( m3s5_stb ), + .m3_ack_o( m3s5_ack ), + .m3_err_o( m3s5_err ), + .m3_rty_o( m3s5_rty ), + .m4_data_i( m4s5_data_o ), + .m4_data_o( m4s5_data_i ), + .m4_addr_i( m4s5_addr ), + .m4_sel_i( m4s5_sel ), + .m4_we_i( m4s5_we ), + .m4_cyc_i( m4s5_cyc ), + .m4_stb_i( m4s5_stb ), + .m4_ack_o( m4s5_ack ), + .m4_err_o( m4s5_err ), + .m4_rty_o( m4s5_rty ), + .m5_data_i( m5s5_data_o ), + .m5_data_o( m5s5_data_i ), + .m5_addr_i( m5s5_addr ), + .m5_sel_i( m5s5_sel ), + .m5_we_i( m5s5_we ), + .m5_cyc_i( m5s5_cyc ), + .m5_stb_i( m5s5_stb ), + .m5_ack_o( m5s5_ack ), + .m5_err_o( m5s5_err ), + .m5_rty_o( m5s5_rty ), + .m6_data_i( m6s5_data_o ), + .m6_data_o( m6s5_data_i ), + .m6_addr_i( m6s5_addr ), + .m6_sel_i( m6s5_sel ), + .m6_we_i( m6s5_we ), + .m6_cyc_i( m6s5_cyc ), + .m6_stb_i( m6s5_stb ), + .m6_ack_o( m6s5_ack ), + .m6_err_o( m6s5_err ), + .m6_rty_o( m6s5_rty ), + .m7_data_i( m7s5_data_o ), + .m7_data_o( m7s5_data_i ), + .m7_addr_i( m7s5_addr ), + .m7_sel_i( m7s5_sel ), + .m7_we_i( m7s5_we ), + .m7_cyc_i( m7s5_cyc ), + .m7_stb_i( m7s5_stb ), + .m7_ack_o( m7s5_ack ), + .m7_err_o( m7s5_err ), + .m7_rty_o( m7s5_rty ) + ); + +wb_conmax_slave_if #(pri_sel6,aw,dw,sw) s6( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf6 ), + .wb_data_i( s6_data_i ), + .wb_data_o( s6_data_o ), + .wb_addr_o( s6_addr_o ), + .wb_sel_o( s6_sel_o ), + .wb_we_o( s6_we_o ), + .wb_cyc_o( s6_cyc_o ), + .wb_stb_o( s6_stb_o ), + .wb_ack_i( s6_ack_i ), + .wb_err_i( s6_err_i ), + .wb_rty_i( s6_rty_i ), + .m0_data_i( m0s6_data_o ), + .m0_data_o( m0s6_data_i ), + .m0_addr_i( m0s6_addr ), + .m0_sel_i( m0s6_sel ), + .m0_we_i( m0s6_we ), + .m0_cyc_i( m0s6_cyc ), + .m0_stb_i( m0s6_stb ), + .m0_ack_o( m0s6_ack ), + .m0_err_o( m0s6_err ), + .m0_rty_o( m0s6_rty ), + .m1_data_i( m1s6_data_o ), + .m1_data_o( m1s6_data_i ), + .m1_addr_i( m1s6_addr ), + .m1_sel_i( m1s6_sel ), + .m1_we_i( m1s6_we ), + .m1_cyc_i( m1s6_cyc ), + .m1_stb_i( m1s6_stb ), + .m1_ack_o( m1s6_ack ), + .m1_err_o( m1s6_err ), + .m1_rty_o( m1s6_rty ), + .m2_data_i( m2s6_data_o ), + .m2_data_o( m2s6_data_i ), + .m2_addr_i( m2s6_addr ), + .m2_sel_i( m2s6_sel ), + .m2_we_i( m2s6_we ), + .m2_cyc_i( m2s6_cyc ), + .m2_stb_i( m2s6_stb ), + .m2_ack_o( m2s6_ack ), + .m2_err_o( m2s6_err ), + .m2_rty_o( m2s6_rty ), + .m3_data_i( m3s6_data_o ), + .m3_data_o( m3s6_data_i ), + .m3_addr_i( m3s6_addr ), + .m3_sel_i( m3s6_sel ), + .m3_we_i( m3s6_we ), + .m3_cyc_i( m3s6_cyc ), + .m3_stb_i( m3s6_stb ), + .m3_ack_o( m3s6_ack ), + .m3_err_o( m3s6_err ), + .m3_rty_o( m3s6_rty ), + .m4_data_i( m4s6_data_o ), + .m4_data_o( m4s6_data_i ), + .m4_addr_i( m4s6_addr ), + .m4_sel_i( m4s6_sel ), + .m4_we_i( m4s6_we ), + .m4_cyc_i( m4s6_cyc ), + .m4_stb_i( m4s6_stb ), + .m4_ack_o( m4s6_ack ), + .m4_err_o( m4s6_err ), + .m4_rty_o( m4s6_rty ), + .m5_data_i( m5s6_data_o ), + .m5_data_o( m5s6_data_i ), + .m5_addr_i( m5s6_addr ), + .m5_sel_i( m5s6_sel ), + .m5_we_i( m5s6_we ), + .m5_cyc_i( m5s6_cyc ), + .m5_stb_i( m5s6_stb ), + .m5_ack_o( m5s6_ack ), + .m5_err_o( m5s6_err ), + .m5_rty_o( m5s6_rty ), + .m6_data_i( m6s6_data_o ), + .m6_data_o( m6s6_data_i ), + .m6_addr_i( m6s6_addr ), + .m6_sel_i( m6s6_sel ), + .m6_we_i( m6s6_we ), + .m6_cyc_i( m6s6_cyc ), + .m6_stb_i( m6s6_stb ), + .m6_ack_o( m6s6_ack ), + .m6_err_o( m6s6_err ), + .m6_rty_o( m6s6_rty ), + .m7_data_i( m7s6_data_o ), + .m7_data_o( m7s6_data_i ), + .m7_addr_i( m7s6_addr ), + .m7_sel_i( m7s6_sel ), + .m7_we_i( m7s6_we ), + .m7_cyc_i( m7s6_cyc ), + .m7_stb_i( m7s6_stb ), + .m7_ack_o( m7s6_ack ), + .m7_err_o( m7s6_err ), + .m7_rty_o( m7s6_rty ) + ); + +wb_conmax_slave_if #(pri_sel7,aw,dw,sw) s7( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf7 ), + .wb_data_i( s7_data_i ), + .wb_data_o( s7_data_o ), + .wb_addr_o( s7_addr_o ), + .wb_sel_o( s7_sel_o ), + .wb_we_o( s7_we_o ), + .wb_cyc_o( s7_cyc_o ), + .wb_stb_o( s7_stb_o ), + .wb_ack_i( s7_ack_i ), + .wb_err_i( s7_err_i ), + .wb_rty_i( s7_rty_i ), + .m0_data_i( m0s7_data_o ), + .m0_data_o( m0s7_data_i ), + .m0_addr_i( m0s7_addr ), + .m0_sel_i( m0s7_sel ), + .m0_we_i( m0s7_we ), + .m0_cyc_i( m0s7_cyc ), + .m0_stb_i( m0s7_stb ), + .m0_ack_o( m0s7_ack ), + .m0_err_o( m0s7_err ), + .m0_rty_o( m0s7_rty ), + .m1_data_i( m1s7_data_o ), + .m1_data_o( m1s7_data_i ), + .m1_addr_i( m1s7_addr ), + .m1_sel_i( m1s7_sel ), + .m1_we_i( m1s7_we ), + .m1_cyc_i( m1s7_cyc ), + .m1_stb_i( m1s7_stb ), + .m1_ack_o( m1s7_ack ), + .m1_err_o( m1s7_err ), + .m1_rty_o( m1s7_rty ), + .m2_data_i( m2s7_data_o ), + .m2_data_o( m2s7_data_i ), + .m2_addr_i( m2s7_addr ), + .m2_sel_i( m2s7_sel ), + .m2_we_i( m2s7_we ), + .m2_cyc_i( m2s7_cyc ), + .m2_stb_i( m2s7_stb ), + .m2_ack_o( m2s7_ack ), + .m2_err_o( m2s7_err ), + .m2_rty_o( m2s7_rty ), + .m3_data_i( m3s7_data_o ), + .m3_data_o( m3s7_data_i ), + .m3_addr_i( m3s7_addr ), + .m3_sel_i( m3s7_sel ), + .m3_we_i( m3s7_we ), + .m3_cyc_i( m3s7_cyc ), + .m3_stb_i( m3s7_stb ), + .m3_ack_o( m3s7_ack ), + .m3_err_o( m3s7_err ), + .m3_rty_o( m3s7_rty ), + .m4_data_i( m4s7_data_o ), + .m4_data_o( m4s7_data_i ), + .m4_addr_i( m4s7_addr ), + .m4_sel_i( m4s7_sel ), + .m4_we_i( m4s7_we ), + .m4_cyc_i( m4s7_cyc ), + .m4_stb_i( m4s7_stb ), + .m4_ack_o( m4s7_ack ), + .m4_err_o( m4s7_err ), + .m4_rty_o( m4s7_rty ), + .m5_data_i( m5s7_data_o ), + .m5_data_o( m5s7_data_i ), + .m5_addr_i( m5s7_addr ), + .m5_sel_i( m5s7_sel ), + .m5_we_i( m5s7_we ), + .m5_cyc_i( m5s7_cyc ), + .m5_stb_i( m5s7_stb ), + .m5_ack_o( m5s7_ack ), + .m5_err_o( m5s7_err ), + .m5_rty_o( m5s7_rty ), + .m6_data_i( m6s7_data_o ), + .m6_data_o( m6s7_data_i ), + .m6_addr_i( m6s7_addr ), + .m6_sel_i( m6s7_sel ), + .m6_we_i( m6s7_we ), + .m6_cyc_i( m6s7_cyc ), + .m6_stb_i( m6s7_stb ), + .m6_ack_o( m6s7_ack ), + .m6_err_o( m6s7_err ), + .m6_rty_o( m6s7_rty ), + .m7_data_i( m7s7_data_o ), + .m7_data_o( m7s7_data_i ), + .m7_addr_i( m7s7_addr ), + .m7_sel_i( m7s7_sel ), + .m7_we_i( m7s7_we ), + .m7_cyc_i( m7s7_cyc ), + .m7_stb_i( m7s7_stb ), + .m7_ack_o( m7s7_ack ), + .m7_err_o( m7s7_err ), + .m7_rty_o( m7s7_rty ) + ); + +wb_conmax_slave_if #(pri_sel8,aw,dw,sw) s8( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf8 ), + .wb_data_i( s8_data_i ), + .wb_data_o( s8_data_o ), + .wb_addr_o( s8_addr_o ), + .wb_sel_o( s8_sel_o ), + .wb_we_o( s8_we_o ), + .wb_cyc_o( s8_cyc_o ), + .wb_stb_o( s8_stb_o ), + .wb_ack_i( s8_ack_i ), + .wb_err_i( s8_err_i ), + .wb_rty_i( s8_rty_i ), + .m0_data_i( m0s8_data_o ), + .m0_data_o( m0s8_data_i ), + .m0_addr_i( m0s8_addr ), + .m0_sel_i( m0s8_sel ), + .m0_we_i( m0s8_we ), + .m0_cyc_i( m0s8_cyc ), + .m0_stb_i( m0s8_stb ), + .m0_ack_o( m0s8_ack ), + .m0_err_o( m0s8_err ), + .m0_rty_o( m0s8_rty ), + .m1_data_i( m1s8_data_o ), + .m1_data_o( m1s8_data_i ), + .m1_addr_i( m1s8_addr ), + .m1_sel_i( m1s8_sel ), + .m1_we_i( m1s8_we ), + .m1_cyc_i( m1s8_cyc ), + .m1_stb_i( m1s8_stb ), + .m1_ack_o( m1s8_ack ), + .m1_err_o( m1s8_err ), + .m1_rty_o( m1s8_rty ), + .m2_data_i( m2s8_data_o ), + .m2_data_o( m2s8_data_i ), + .m2_addr_i( m2s8_addr ), + .m2_sel_i( m2s8_sel ), + .m2_we_i( m2s8_we ), + .m2_cyc_i( m2s8_cyc ), + .m2_stb_i( m2s8_stb ), + .m2_ack_o( m2s8_ack ), + .m2_err_o( m2s8_err ), + .m2_rty_o( m2s8_rty ), + .m3_data_i( m3s8_data_o ), + .m3_data_o( m3s8_data_i ), + .m3_addr_i( m3s8_addr ), + .m3_sel_i( m3s8_sel ), + .m3_we_i( m3s8_we ), + .m3_cyc_i( m3s8_cyc ), + .m3_stb_i( m3s8_stb ), + .m3_ack_o( m3s8_ack ), + .m3_err_o( m3s8_err ), + .m3_rty_o( m3s8_rty ), + .m4_data_i( m4s8_data_o ), + .m4_data_o( m4s8_data_i ), + .m4_addr_i( m4s8_addr ), + .m4_sel_i( m4s8_sel ), + .m4_we_i( m4s8_we ), + .m4_cyc_i( m4s8_cyc ), + .m4_stb_i( m4s8_stb ), + .m4_ack_o( m4s8_ack ), + .m4_err_o( m4s8_err ), + .m4_rty_o( m4s8_rty ), + .m5_data_i( m5s8_data_o ), + .m5_data_o( m5s8_data_i ), + .m5_addr_i( m5s8_addr ), + .m5_sel_i( m5s8_sel ), + .m5_we_i( m5s8_we ), + .m5_cyc_i( m5s8_cyc ), + .m5_stb_i( m5s8_stb ), + .m5_ack_o( m5s8_ack ), + .m5_err_o( m5s8_err ), + .m5_rty_o( m5s8_rty ), + .m6_data_i( m6s8_data_o ), + .m6_data_o( m6s8_data_i ), + .m6_addr_i( m6s8_addr ), + .m6_sel_i( m6s8_sel ), + .m6_we_i( m6s8_we ), + .m6_cyc_i( m6s8_cyc ), + .m6_stb_i( m6s8_stb ), + .m6_ack_o( m6s8_ack ), + .m6_err_o( m6s8_err ), + .m6_rty_o( m6s8_rty ), + .m7_data_i( m7s8_data_o ), + .m7_data_o( m7s8_data_i ), + .m7_addr_i( m7s8_addr ), + .m7_sel_i( m7s8_sel ), + .m7_we_i( m7s8_we ), + .m7_cyc_i( m7s8_cyc ), + .m7_stb_i( m7s8_stb ), + .m7_ack_o( m7s8_ack ), + .m7_err_o( m7s8_err ), + .m7_rty_o( m7s8_rty ) + ); + +wb_conmax_slave_if #(pri_sel9,aw,dw,sw) s9( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf9 ), + .wb_data_i( s9_data_i ), + .wb_data_o( s9_data_o ), + .wb_addr_o( s9_addr_o ), + .wb_sel_o( s9_sel_o ), + .wb_we_o( s9_we_o ), + .wb_cyc_o( s9_cyc_o ), + .wb_stb_o( s9_stb_o ), + .wb_ack_i( s9_ack_i ), + .wb_err_i( s9_err_i ), + .wb_rty_i( s9_rty_i ), + .m0_data_i( m0s9_data_o ), + .m0_data_o( m0s9_data_i ), + .m0_addr_i( m0s9_addr ), + .m0_sel_i( m0s9_sel ), + .m0_we_i( m0s9_we ), + .m0_cyc_i( m0s9_cyc ), + .m0_stb_i( m0s9_stb ), + .m0_ack_o( m0s9_ack ), + .m0_err_o( m0s9_err ), + .m0_rty_o( m0s9_rty ), + .m1_data_i( m1s9_data_o ), + .m1_data_o( m1s9_data_i ), + .m1_addr_i( m1s9_addr ), + .m1_sel_i( m1s9_sel ), + .m1_we_i( m1s9_we ), + .m1_cyc_i( m1s9_cyc ), + .m1_stb_i( m1s9_stb ), + .m1_ack_o( m1s9_ack ), + .m1_err_o( m1s9_err ), + .m1_rty_o( m1s9_rty ), + .m2_data_i( m2s9_data_o ), + .m2_data_o( m2s9_data_i ), + .m2_addr_i( m2s9_addr ), + .m2_sel_i( m2s9_sel ), + .m2_we_i( m2s9_we ), + .m2_cyc_i( m2s9_cyc ), + .m2_stb_i( m2s9_stb ), + .m2_ack_o( m2s9_ack ), + .m2_err_o( m2s9_err ), + .m2_rty_o( m2s9_rty ), + .m3_data_i( m3s9_data_o ), + .m3_data_o( m3s9_data_i ), + .m3_addr_i( m3s9_addr ), + .m3_sel_i( m3s9_sel ), + .m3_we_i( m3s9_we ), + .m3_cyc_i( m3s9_cyc ), + .m3_stb_i( m3s9_stb ), + .m3_ack_o( m3s9_ack ), + .m3_err_o( m3s9_err ), + .m3_rty_o( m3s9_rty ), + .m4_data_i( m4s9_data_o ), + .m4_data_o( m4s9_data_i ), + .m4_addr_i( m4s9_addr ), + .m4_sel_i( m4s9_sel ), + .m4_we_i( m4s9_we ), + .m4_cyc_i( m4s9_cyc ), + .m4_stb_i( m4s9_stb ), + .m4_ack_o( m4s9_ack ), + .m4_err_o( m4s9_err ), + .m4_rty_o( m4s9_rty ), + .m5_data_i( m5s9_data_o ), + .m5_data_o( m5s9_data_i ), + .m5_addr_i( m5s9_addr ), + .m5_sel_i( m5s9_sel ), + .m5_we_i( m5s9_we ), + .m5_cyc_i( m5s9_cyc ), + .m5_stb_i( m5s9_stb ), + .m5_ack_o( m5s9_ack ), + .m5_err_o( m5s9_err ), + .m5_rty_o( m5s9_rty ), + .m6_data_i( m6s9_data_o ), + .m6_data_o( m6s9_data_i ), + .m6_addr_i( m6s9_addr ), + .m6_sel_i( m6s9_sel ), + .m6_we_i( m6s9_we ), + .m6_cyc_i( m6s9_cyc ), + .m6_stb_i( m6s9_stb ), + .m6_ack_o( m6s9_ack ), + .m6_err_o( m6s9_err ), + .m6_rty_o( m6s9_rty ), + .m7_data_i( m7s9_data_o ), + .m7_data_o( m7s9_data_i ), + .m7_addr_i( m7s9_addr ), + .m7_sel_i( m7s9_sel ), + .m7_we_i( m7s9_we ), + .m7_cyc_i( m7s9_cyc ), + .m7_stb_i( m7s9_stb ), + .m7_ack_o( m7s9_ack ), + .m7_err_o( m7s9_err ), + .m7_rty_o( m7s9_rty ) + ); + +wb_conmax_slave_if #(pri_sel10,aw,dw,sw) s10( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf10 ), + .wb_data_i( s10_data_i ), + .wb_data_o( s10_data_o ), + .wb_addr_o( s10_addr_o ), + .wb_sel_o( s10_sel_o ), + .wb_we_o( s10_we_o ), + .wb_cyc_o( s10_cyc_o ), + .wb_stb_o( s10_stb_o ), + .wb_ack_i( s10_ack_i ), + .wb_err_i( s10_err_i ), + .wb_rty_i( s10_rty_i ), + .m0_data_i( m0s10_data_o ), + .m0_data_o( m0s10_data_i ), + .m0_addr_i( m0s10_addr ), + .m0_sel_i( m0s10_sel ), + .m0_we_i( m0s10_we ), + .m0_cyc_i( m0s10_cyc ), + .m0_stb_i( m0s10_stb ), + .m0_ack_o( m0s10_ack ), + .m0_err_o( m0s10_err ), + .m0_rty_o( m0s10_rty ), + .m1_data_i( m1s10_data_o ), + .m1_data_o( m1s10_data_i ), + .m1_addr_i( m1s10_addr ), + .m1_sel_i( m1s10_sel ), + .m1_we_i( m1s10_we ), + .m1_cyc_i( m1s10_cyc ), + .m1_stb_i( m1s10_stb ), + .m1_ack_o( m1s10_ack ), + .m1_err_o( m1s10_err ), + .m1_rty_o( m1s10_rty ), + .m2_data_i( m2s10_data_o ), + .m2_data_o( m2s10_data_i ), + .m2_addr_i( m2s10_addr ), + .m2_sel_i( m2s10_sel ), + .m2_we_i( m2s10_we ), + .m2_cyc_i( m2s10_cyc ), + .m2_stb_i( m2s10_stb ), + .m2_ack_o( m2s10_ack ), + .m2_err_o( m2s10_err ), + .m2_rty_o( m2s10_rty ), + .m3_data_i( m3s10_data_o ), + .m3_data_o( m3s10_data_i ), + .m3_addr_i( m3s10_addr ), + .m3_sel_i( m3s10_sel ), + .m3_we_i( m3s10_we ), + .m3_cyc_i( m3s10_cyc ), + .m3_stb_i( m3s10_stb ), + .m3_ack_o( m3s10_ack ), + .m3_err_o( m3s10_err ), + .m3_rty_o( m3s10_rty ), + .m4_data_i( m4s10_data_o ), + .m4_data_o( m4s10_data_i ), + .m4_addr_i( m4s10_addr ), + .m4_sel_i( m4s10_sel ), + .m4_we_i( m4s10_we ), + .m4_cyc_i( m4s10_cyc ), + .m4_stb_i( m4s10_stb ), + .m4_ack_o( m4s10_ack ), + .m4_err_o( m4s10_err ), + .m4_rty_o( m4s10_rty ), + .m5_data_i( m5s10_data_o ), + .m5_data_o( m5s10_data_i ), + .m5_addr_i( m5s10_addr ), + .m5_sel_i( m5s10_sel ), + .m5_we_i( m5s10_we ), + .m5_cyc_i( m5s10_cyc ), + .m5_stb_i( m5s10_stb ), + .m5_ack_o( m5s10_ack ), + .m5_err_o( m5s10_err ), + .m5_rty_o( m5s10_rty ), + .m6_data_i( m6s10_data_o ), + .m6_data_o( m6s10_data_i ), + .m6_addr_i( m6s10_addr ), + .m6_sel_i( m6s10_sel ), + .m6_we_i( m6s10_we ), + .m6_cyc_i( m6s10_cyc ), + .m6_stb_i( m6s10_stb ), + .m6_ack_o( m6s10_ack ), + .m6_err_o( m6s10_err ), + .m6_rty_o( m6s10_rty ), + .m7_data_i( m7s10_data_o ), + .m7_data_o( m7s10_data_i ), + .m7_addr_i( m7s10_addr ), + .m7_sel_i( m7s10_sel ), + .m7_we_i( m7s10_we ), + .m7_cyc_i( m7s10_cyc ), + .m7_stb_i( m7s10_stb ), + .m7_ack_o( m7s10_ack ), + .m7_err_o( m7s10_err ), + .m7_rty_o( m7s10_rty ) + ); + +wb_conmax_slave_if #(pri_sel11,aw,dw,sw) s11( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf11 ), + .wb_data_i( s11_data_i ), + .wb_data_o( s11_data_o ), + .wb_addr_o( s11_addr_o ), + .wb_sel_o( s11_sel_o ), + .wb_we_o( s11_we_o ), + .wb_cyc_o( s11_cyc_o ), + .wb_stb_o( s11_stb_o ), + .wb_ack_i( s11_ack_i ), + .wb_err_i( s11_err_i ), + .wb_rty_i( s11_rty_i ), + .m0_data_i( m0s11_data_o ), + .m0_data_o( m0s11_data_i ), + .m0_addr_i( m0s11_addr ), + .m0_sel_i( m0s11_sel ), + .m0_we_i( m0s11_we ), + .m0_cyc_i( m0s11_cyc ), + .m0_stb_i( m0s11_stb ), + .m0_ack_o( m0s11_ack ), + .m0_err_o( m0s11_err ), + .m0_rty_o( m0s11_rty ), + .m1_data_i( m1s11_data_o ), + .m1_data_o( m1s11_data_i ), + .m1_addr_i( m1s11_addr ), + .m1_sel_i( m1s11_sel ), + .m1_we_i( m1s11_we ), + .m1_cyc_i( m1s11_cyc ), + .m1_stb_i( m1s11_stb ), + .m1_ack_o( m1s11_ack ), + .m1_err_o( m1s11_err ), + .m1_rty_o( m1s11_rty ), + .m2_data_i( m2s11_data_o ), + .m2_data_o( m2s11_data_i ), + .m2_addr_i( m2s11_addr ), + .m2_sel_i( m2s11_sel ), + .m2_we_i( m2s11_we ), + .m2_cyc_i( m2s11_cyc ), + .m2_stb_i( m2s11_stb ), + .m2_ack_o( m2s11_ack ), + .m2_err_o( m2s11_err ), + .m2_rty_o( m2s11_rty ), + .m3_data_i( m3s11_data_o ), + .m3_data_o( m3s11_data_i ), + .m3_addr_i( m3s11_addr ), + .m3_sel_i( m3s11_sel ), + .m3_we_i( m3s11_we ), + .m3_cyc_i( m3s11_cyc ), + .m3_stb_i( m3s11_stb ), + .m3_ack_o( m3s11_ack ), + .m3_err_o( m3s11_err ), + .m3_rty_o( m3s11_rty ), + .m4_data_i( m4s11_data_o ), + .m4_data_o( m4s11_data_i ), + .m4_addr_i( m4s11_addr ), + .m4_sel_i( m4s11_sel ), + .m4_we_i( m4s11_we ), + .m4_cyc_i( m4s11_cyc ), + .m4_stb_i( m4s11_stb ), + .m4_ack_o( m4s11_ack ), + .m4_err_o( m4s11_err ), + .m4_rty_o( m4s11_rty ), + .m5_data_i( m5s11_data_o ), + .m5_data_o( m5s11_data_i ), + .m5_addr_i( m5s11_addr ), + .m5_sel_i( m5s11_sel ), + .m5_we_i( m5s11_we ), + .m5_cyc_i( m5s11_cyc ), + .m5_stb_i( m5s11_stb ), + .m5_ack_o( m5s11_ack ), + .m5_err_o( m5s11_err ), + .m5_rty_o( m5s11_rty ), + .m6_data_i( m6s11_data_o ), + .m6_data_o( m6s11_data_i ), + .m6_addr_i( m6s11_addr ), + .m6_sel_i( m6s11_sel ), + .m6_we_i( m6s11_we ), + .m6_cyc_i( m6s11_cyc ), + .m6_stb_i( m6s11_stb ), + .m6_ack_o( m6s11_ack ), + .m6_err_o( m6s11_err ), + .m6_rty_o( m6s11_rty ), + .m7_data_i( m7s11_data_o ), + .m7_data_o( m7s11_data_i ), + .m7_addr_i( m7s11_addr ), + .m7_sel_i( m7s11_sel ), + .m7_we_i( m7s11_we ), + .m7_cyc_i( m7s11_cyc ), + .m7_stb_i( m7s11_stb ), + .m7_ack_o( m7s11_ack ), + .m7_err_o( m7s11_err ), + .m7_rty_o( m7s11_rty ) + ); + +wb_conmax_slave_if #(pri_sel12,aw,dw,sw) s12( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf12 ), + .wb_data_i( s12_data_i ), + .wb_data_o( s12_data_o ), + .wb_addr_o( s12_addr_o ), + .wb_sel_o( s12_sel_o ), + .wb_we_o( s12_we_o ), + .wb_cyc_o( s12_cyc_o ), + .wb_stb_o( s12_stb_o ), + .wb_ack_i( s12_ack_i ), + .wb_err_i( s12_err_i ), + .wb_rty_i( s12_rty_i ), + .m0_data_i( m0s12_data_o ), + .m0_data_o( m0s12_data_i ), + .m0_addr_i( m0s12_addr ), + .m0_sel_i( m0s12_sel ), + .m0_we_i( m0s12_we ), + .m0_cyc_i( m0s12_cyc ), + .m0_stb_i( m0s12_stb ), + .m0_ack_o( m0s12_ack ), + .m0_err_o( m0s12_err ), + .m0_rty_o( m0s12_rty ), + .m1_data_i( m1s12_data_o ), + .m1_data_o( m1s12_data_i ), + .m1_addr_i( m1s12_addr ), + .m1_sel_i( m1s12_sel ), + .m1_we_i( m1s12_we ), + .m1_cyc_i( m1s12_cyc ), + .m1_stb_i( m1s12_stb ), + .m1_ack_o( m1s12_ack ), + .m1_err_o( m1s12_err ), + .m1_rty_o( m1s12_rty ), + .m2_data_i( m2s12_data_o ), + .m2_data_o( m2s12_data_i ), + .m2_addr_i( m2s12_addr ), + .m2_sel_i( m2s12_sel ), + .m2_we_i( m2s12_we ), + .m2_cyc_i( m2s12_cyc ), + .m2_stb_i( m2s12_stb ), + .m2_ack_o( m2s12_ack ), + .m2_err_o( m2s12_err ), + .m2_rty_o( m2s12_rty ), + .m3_data_i( m3s12_data_o ), + .m3_data_o( m3s12_data_i ), + .m3_addr_i( m3s12_addr ), + .m3_sel_i( m3s12_sel ), + .m3_we_i( m3s12_we ), + .m3_cyc_i( m3s12_cyc ), + .m3_stb_i( m3s12_stb ), + .m3_ack_o( m3s12_ack ), + .m3_err_o( m3s12_err ), + .m3_rty_o( m3s12_rty ), + .m4_data_i( m4s12_data_o ), + .m4_data_o( m4s12_data_i ), + .m4_addr_i( m4s12_addr ), + .m4_sel_i( m4s12_sel ), + .m4_we_i( m4s12_we ), + .m4_cyc_i( m4s12_cyc ), + .m4_stb_i( m4s12_stb ), + .m4_ack_o( m4s12_ack ), + .m4_err_o( m4s12_err ), + .m4_rty_o( m4s12_rty ), + .m5_data_i( m5s12_data_o ), + .m5_data_o( m5s12_data_i ), + .m5_addr_i( m5s12_addr ), + .m5_sel_i( m5s12_sel ), + .m5_we_i( m5s12_we ), + .m5_cyc_i( m5s12_cyc ), + .m5_stb_i( m5s12_stb ), + .m5_ack_o( m5s12_ack ), + .m5_err_o( m5s12_err ), + .m5_rty_o( m5s12_rty ), + .m6_data_i( m6s12_data_o ), + .m6_data_o( m6s12_data_i ), + .m6_addr_i( m6s12_addr ), + .m6_sel_i( m6s12_sel ), + .m6_we_i( m6s12_we ), + .m6_cyc_i( m6s12_cyc ), + .m6_stb_i( m6s12_stb ), + .m6_ack_o( m6s12_ack ), + .m6_err_o( m6s12_err ), + .m6_rty_o( m6s12_rty ), + .m7_data_i( m7s12_data_o ), + .m7_data_o( m7s12_data_i ), + .m7_addr_i( m7s12_addr ), + .m7_sel_i( m7s12_sel ), + .m7_we_i( m7s12_we ), + .m7_cyc_i( m7s12_cyc ), + .m7_stb_i( m7s12_stb ), + .m7_ack_o( m7s12_ack ), + .m7_err_o( m7s12_err ), + .m7_rty_o( m7s12_rty ) + ); + +wb_conmax_slave_if #(pri_sel13,aw,dw,sw) s13( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf13 ), + .wb_data_i( s13_data_i ), + .wb_data_o( s13_data_o ), + .wb_addr_o( s13_addr_o ), + .wb_sel_o( s13_sel_o ), + .wb_we_o( s13_we_o ), + .wb_cyc_o( s13_cyc_o ), + .wb_stb_o( s13_stb_o ), + .wb_ack_i( s13_ack_i ), + .wb_err_i( s13_err_i ), + .wb_rty_i( s13_rty_i ), + .m0_data_i( m0s13_data_o ), + .m0_data_o( m0s13_data_i ), + .m0_addr_i( m0s13_addr ), + .m0_sel_i( m0s13_sel ), + .m0_we_i( m0s13_we ), + .m0_cyc_i( m0s13_cyc ), + .m0_stb_i( m0s13_stb ), + .m0_ack_o( m0s13_ack ), + .m0_err_o( m0s13_err ), + .m0_rty_o( m0s13_rty ), + .m1_data_i( m1s13_data_o ), + .m1_data_o( m1s13_data_i ), + .m1_addr_i( m1s13_addr ), + .m1_sel_i( m1s13_sel ), + .m1_we_i( m1s13_we ), + .m1_cyc_i( m1s13_cyc ), + .m1_stb_i( m1s13_stb ), + .m1_ack_o( m1s13_ack ), + .m1_err_o( m1s13_err ), + .m1_rty_o( m1s13_rty ), + .m2_data_i( m2s13_data_o ), + .m2_data_o( m2s13_data_i ), + .m2_addr_i( m2s13_addr ), + .m2_sel_i( m2s13_sel ), + .m2_we_i( m2s13_we ), + .m2_cyc_i( m2s13_cyc ), + .m2_stb_i( m2s13_stb ), + .m2_ack_o( m2s13_ack ), + .m2_err_o( m2s13_err ), + .m2_rty_o( m2s13_rty ), + .m3_data_i( m3s13_data_o ), + .m3_data_o( m3s13_data_i ), + .m3_addr_i( m3s13_addr ), + .m3_sel_i( m3s13_sel ), + .m3_we_i( m3s13_we ), + .m3_cyc_i( m3s13_cyc ), + .m3_stb_i( m3s13_stb ), + .m3_ack_o( m3s13_ack ), + .m3_err_o( m3s13_err ), + .m3_rty_o( m3s13_rty ), + .m4_data_i( m4s13_data_o ), + .m4_data_o( m4s13_data_i ), + .m4_addr_i( m4s13_addr ), + .m4_sel_i( m4s13_sel ), + .m4_we_i( m4s13_we ), + .m4_cyc_i( m4s13_cyc ), + .m4_stb_i( m4s13_stb ), + .m4_ack_o( m4s13_ack ), + .m4_err_o( m4s13_err ), + .m4_rty_o( m4s13_rty ), + .m5_data_i( m5s13_data_o ), + .m5_data_o( m5s13_data_i ), + .m5_addr_i( m5s13_addr ), + .m5_sel_i( m5s13_sel ), + .m5_we_i( m5s13_we ), + .m5_cyc_i( m5s13_cyc ), + .m5_stb_i( m5s13_stb ), + .m5_ack_o( m5s13_ack ), + .m5_err_o( m5s13_err ), + .m5_rty_o( m5s13_rty ), + .m6_data_i( m6s13_data_o ), + .m6_data_o( m6s13_data_i ), + .m6_addr_i( m6s13_addr ), + .m6_sel_i( m6s13_sel ), + .m6_we_i( m6s13_we ), + .m6_cyc_i( m6s13_cyc ), + .m6_stb_i( m6s13_stb ), + .m6_ack_o( m6s13_ack ), + .m6_err_o( m6s13_err ), + .m6_rty_o( m6s13_rty ), + .m7_data_i( m7s13_data_o ), + .m7_data_o( m7s13_data_i ), + .m7_addr_i( m7s13_addr ), + .m7_sel_i( m7s13_sel ), + .m7_we_i( m7s13_we ), + .m7_cyc_i( m7s13_cyc ), + .m7_stb_i( m7s13_stb ), + .m7_ack_o( m7s13_ack ), + .m7_err_o( m7s13_err ), + .m7_rty_o( m7s13_rty ) + ); + +wb_conmax_slave_if #(pri_sel14,aw,dw,sw) s14( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf14 ), + .wb_data_i( s14_data_i ), + .wb_data_o( s14_data_o ), + .wb_addr_o( s14_addr_o ), + .wb_sel_o( s14_sel_o ), + .wb_we_o( s14_we_o ), + .wb_cyc_o( s14_cyc_o ), + .wb_stb_o( s14_stb_o ), + .wb_ack_i( s14_ack_i ), + .wb_err_i( s14_err_i ), + .wb_rty_i( s14_rty_i ), + .m0_data_i( m0s14_data_o ), + .m0_data_o( m0s14_data_i ), + .m0_addr_i( m0s14_addr ), + .m0_sel_i( m0s14_sel ), + .m0_we_i( m0s14_we ), + .m0_cyc_i( m0s14_cyc ), + .m0_stb_i( m0s14_stb ), + .m0_ack_o( m0s14_ack ), + .m0_err_o( m0s14_err ), + .m0_rty_o( m0s14_rty ), + .m1_data_i( m1s14_data_o ), + .m1_data_o( m1s14_data_i ), + .m1_addr_i( m1s14_addr ), + .m1_sel_i( m1s14_sel ), + .m1_we_i( m1s14_we ), + .m1_cyc_i( m1s14_cyc ), + .m1_stb_i( m1s14_stb ), + .m1_ack_o( m1s14_ack ), + .m1_err_o( m1s14_err ), + .m1_rty_o( m1s14_rty ), + .m2_data_i( m2s14_data_o ), + .m2_data_o( m2s14_data_i ), + .m2_addr_i( m2s14_addr ), + .m2_sel_i( m2s14_sel ), + .m2_we_i( m2s14_we ), + .m2_cyc_i( m2s14_cyc ), + .m2_stb_i( m2s14_stb ), + .m2_ack_o( m2s14_ack ), + .m2_err_o( m2s14_err ), + .m2_rty_o( m2s14_rty ), + .m3_data_i( m3s14_data_o ), + .m3_data_o( m3s14_data_i ), + .m3_addr_i( m3s14_addr ), + .m3_sel_i( m3s14_sel ), + .m3_we_i( m3s14_we ), + .m3_cyc_i( m3s14_cyc ), + .m3_stb_i( m3s14_stb ), + .m3_ack_o( m3s14_ack ), + .m3_err_o( m3s14_err ), + .m3_rty_o( m3s14_rty ), + .m4_data_i( m4s14_data_o ), + .m4_data_o( m4s14_data_i ), + .m4_addr_i( m4s14_addr ), + .m4_sel_i( m4s14_sel ), + .m4_we_i( m4s14_we ), + .m4_cyc_i( m4s14_cyc ), + .m4_stb_i( m4s14_stb ), + .m4_ack_o( m4s14_ack ), + .m4_err_o( m4s14_err ), + .m4_rty_o( m4s14_rty ), + .m5_data_i( m5s14_data_o ), + .m5_data_o( m5s14_data_i ), + .m5_addr_i( m5s14_addr ), + .m5_sel_i( m5s14_sel ), + .m5_we_i( m5s14_we ), + .m5_cyc_i( m5s14_cyc ), + .m5_stb_i( m5s14_stb ), + .m5_ack_o( m5s14_ack ), + .m5_err_o( m5s14_err ), + .m5_rty_o( m5s14_rty ), + .m6_data_i( m6s14_data_o ), + .m6_data_o( m6s14_data_i ), + .m6_addr_i( m6s14_addr ), + .m6_sel_i( m6s14_sel ), + .m6_we_i( m6s14_we ), + .m6_cyc_i( m6s14_cyc ), + .m6_stb_i( m6s14_stb ), + .m6_ack_o( m6s14_ack ), + .m6_err_o( m6s14_err ), + .m6_rty_o( m6s14_rty ), + .m7_data_i( m7s14_data_o ), + .m7_data_o( m7s14_data_i ), + .m7_addr_i( m7s14_addr ), + .m7_sel_i( m7s14_sel ), + .m7_we_i( m7s14_we ), + .m7_cyc_i( m7s14_cyc ), + .m7_stb_i( m7s14_stb ), + .m7_ack_o( m7s14_ack ), + .m7_err_o( m7s14_err ), + .m7_rty_o( m7s14_rty ) + ); + +wb_conmax_slave_if #(pri_sel15,aw,dw,sw) s15( + .clk_i( clk_i ), + .rst_i( rst_i ), + .conf( conf15 ), + .wb_data_i( i_s15_data_i ), + .wb_data_o( i_s15_data_o ), + .wb_addr_o( i_s15_addr_o ), + .wb_sel_o( i_s15_sel_o ), + .wb_we_o( i_s15_we_o ), + .wb_cyc_o( i_s15_cyc_o ), + .wb_stb_o( i_s15_stb_o ), + .wb_ack_i( i_s15_ack_i ), + .wb_err_i( i_s15_err_i ), + .wb_rty_i( i_s15_rty_i ), + .m0_data_i( m0s15_data_o ), + .m0_data_o( m0s15_data_i ), + .m0_addr_i( m0s15_addr ), + .m0_sel_i( m0s15_sel ), + .m0_we_i( m0s15_we ), + .m0_cyc_i( m0s15_cyc ), + .m0_stb_i( m0s15_stb ), + .m0_ack_o( m0s15_ack ), + .m0_err_o( m0s15_err ), + .m0_rty_o( m0s15_rty ), + .m1_data_i( m1s15_data_o ), + .m1_data_o( m1s15_data_i ), + .m1_addr_i( m1s15_addr ), + .m1_sel_i( m1s15_sel ), + .m1_we_i( m1s15_we ), + .m1_cyc_i( m1s15_cyc ), + .m1_stb_i( m1s15_stb ), + .m1_ack_o( m1s15_ack ), + .m1_err_o( m1s15_err ), + .m1_rty_o( m1s15_rty ), + .m2_data_i( m2s15_data_o ), + .m2_data_o( m2s15_data_i ), + .m2_addr_i( m2s15_addr ), + .m2_sel_i( m2s15_sel ), + .m2_we_i( m2s15_we ), + .m2_cyc_i( m2s15_cyc ), + .m2_stb_i( m2s15_stb ), + .m2_ack_o( m2s15_ack ), + .m2_err_o( m2s15_err ), + .m2_rty_o( m2s15_rty ), + .m3_data_i( m3s15_data_o ), + .m3_data_o( m3s15_data_i ), + .m3_addr_i( m3s15_addr ), + .m3_sel_i( m3s15_sel ), + .m3_we_i( m3s15_we ), + .m3_cyc_i( m3s15_cyc ), + .m3_stb_i( m3s15_stb ), + .m3_ack_o( m3s15_ack ), + .m3_err_o( m3s15_err ), + .m3_rty_o( m3s15_rty ), + .m4_data_i( m4s15_data_o ), + .m4_data_o( m4s15_data_i ), + .m4_addr_i( m4s15_addr ), + .m4_sel_i( m4s15_sel ), + .m4_we_i( m4s15_we ), + .m4_cyc_i( m4s15_cyc ), + .m4_stb_i( m4s15_stb ), + .m4_ack_o( m4s15_ack ), + .m4_err_o( m4s15_err ), + .m4_rty_o( m4s15_rty ), + .m5_data_i( m5s15_data_o ), + .m5_data_o( m5s15_data_i ), + .m5_addr_i( m5s15_addr ), + .m5_sel_i( m5s15_sel ), + .m5_we_i( m5s15_we ), + .m5_cyc_i( m5s15_cyc ), + .m5_stb_i( m5s15_stb ), + .m5_ack_o( m5s15_ack ), + .m5_err_o( m5s15_err ), + .m5_rty_o( m5s15_rty ), + .m6_data_i( m6s15_data_o ), + .m6_data_o( m6s15_data_i ), + .m6_addr_i( m6s15_addr ), + .m6_sel_i( m6s15_sel ), + .m6_we_i( m6s15_we ), + .m6_cyc_i( m6s15_cyc ), + .m6_stb_i( m6s15_stb ), + .m6_ack_o( m6s15_ack ), + .m6_err_o( m6s15_err ), + .m6_rty_o( m6s15_rty ), + .m7_data_i( m7s15_data_o ), + .m7_data_o( m7s15_data_i ), + .m7_addr_i( m7s15_addr ), + .m7_sel_i( m7s15_sel ), + .m7_we_i( m7s15_we ), + .m7_cyc_i( m7s15_cyc ), + .m7_stb_i( m7s15_stb ), + .m7_ack_o( m7s15_ack ), + .m7_err_o( m7s15_err ), + .m7_rty_o( m7s15_rty ) + ); + +wb_conmax_rf #(rf_addr,dw,aw,sw) rf( + .clk_i( clk_i ), + .rst_i( rst_i ), + .i_wb_data_i( i_s15_data_o ), + .i_wb_data_o( i_s15_data_i ), + .i_wb_addr_i( i_s15_addr_o ), + .i_wb_sel_i( i_s15_sel_o ), + .i_wb_we_i( i_s15_we_o ), + .i_wb_cyc_i( i_s15_cyc_o ), + .i_wb_stb_i( i_s15_stb_o ), + .i_wb_ack_o( i_s15_ack_i ), + .i_wb_err_o( i_s15_err_i ), + .i_wb_rty_o( i_s15_rty_i ), + + .e_wb_data_i( s15_data_i ), + .e_wb_data_o( s15_data_o ), + .e_wb_addr_o( s15_addr_o ), + .e_wb_sel_o( s15_sel_o ), + .e_wb_we_o( s15_we_o ), + .e_wb_cyc_o( s15_cyc_o ), + .e_wb_stb_o( s15_stb_o ), + .e_wb_ack_i( s15_ack_i ), + .e_wb_err_i( s15_err_i ), + .e_wb_rty_i( s15_rty_i ), + + .conf0( conf0 ), + .conf1( conf1 ), + .conf2( conf2 ), + .conf3( conf3 ), + .conf4( conf4 ), + .conf5( conf5 ), + .conf6( conf6 ), + .conf7( conf7 ), + .conf8( conf8 ), + .conf9( conf9 ), + .conf10( conf10 ), + .conf11( conf11 ), + .conf12( conf12 ), + .conf13( conf13 ), + .conf14( conf14 ), + .conf15( conf15 ) + ); +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_arb.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_arb.v new file mode 100644 index 000000000..06ccf8b32 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_arb.v @@ -0,0 +1,2157 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Channel Arbiter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_arb.v,v 1.2 2002/02/01 01:54:44 rudi Exp $ +// +// $Date: 2002/02/01 01:54:44 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_ch_arb.v,v $ +// Revision 1.2 2002/02/01 01:54:44 rudi +// +// - Minor cleanup +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:51:25 rudi +// +// +// Changed Module name to match file name. +// +// Revision 1.3 2001/06/13 02:26:46 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:34 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:47 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +// Arbiter +// +// Implements a simple round robin arbiter for DMA channels of +// same priority + +module wb_dma_ch_arb(clk, rst, req, gnt, advance); + +input clk; +input rst; +input [30:0] req; // Req input +output [4:0] gnt; // Grant output +input advance; // Next Target + +/////////////////////////////////////////////////////////////////////// +// +// Definitions +// + +parameter [4:0] + grant0 = 5'h0, + grant1 = 5'h1, + grant2 = 5'h2, + grant3 = 5'h3, + grant4 = 5'h4, + grant5 = 5'h5, + grant6 = 5'h6, + grant7 = 5'h7, + grant8 = 5'h8, + grant9 = 5'h9, + grant10 = 5'ha, + grant11 = 5'hb, + grant12 = 5'hc, + grant13 = 5'hd, + grant14 = 5'he, + grant15 = 5'hf, + grant16 = 5'h10, + grant17 = 5'h11, + grant18 = 5'h12, + grant19 = 5'h13, + grant20 = 5'h14, + grant21 = 5'h15, + grant22 = 5'h16, + grant23 = 5'h17, + grant24 = 5'h18, + grant25 = 5'h19, + grant26 = 5'h1a, + grant27 = 5'h1b, + grant28 = 5'h1c, + grant29 = 5'h1d, + grant30 = 5'h1e; + +/////////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [4:0] state, next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign gnt = state; + +always@(posedge clk or negedge rst) + if(!rst) state <= #1 grant0; + else state <= #1 next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Next State Logic +// - implements round robin arbitration algorithm +// - switches grant if current req is dropped or next is asserted +// - parks at last grant +// + +always@(state or req or advance) + begin + next_state = state; // Default Keep State + case(state) // synopsys parallel_case full_case + grant0: + // if this req is dropped or next is asserted, check for other req's + if(!req[0] | advance) + begin + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + end + grant1: + // if this req is dropped or next is asserted, check for other req's + if(!req[1] | advance) + begin + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + end + grant2: + // if this req is dropped or next is asserted, check for other req's + if(!req[2] | advance) + begin + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] | advance) + begin + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + end + grant4: + // if this req is dropped or next is asserted, check for other req's + if(!req[4] | advance) + begin + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + end + grant5: + // if this req is dropped or next is asserted, check for other req's + if(!req[5] | advance) + begin + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + end + grant6: + // if this req is dropped or next is asserted, check for other req's + if(!req[6] | advance) + begin + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + end + grant7: + // if this req is dropped or next is asserted, check for other req's + if(!req[7] | advance) + begin + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + end + grant8: + // if this req is dropped or next is asserted, check for other req's + if(!req[8] | advance) + begin + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + end + grant9: + // if this req is dropped or next is asserted, check for other req's + if(!req[9] | advance) + begin + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + end + grant10: + // if this req is dropped or next is asserted, check for other req's + if(!req[10] | advance) + begin + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + end + grant11: + // if this req is dropped or next is asserted, check for other req's + if(!req[11] | advance) + begin + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + end + grant12: + // if this req is dropped or next is asserted, check for other req's + if(!req[12] | advance) + begin + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + end + grant13: + // if this req is dropped or next is asserted, check for other req's + if(!req[13] | advance) + begin + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + end + grant14: + // if this req is dropped or next is asserted, check for other req's + if(!req[14] | advance) + begin + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + end + grant15: + // if this req is dropped or next is asserted, check for other req's + if(!req[15] | advance) + begin + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + end + grant16: + // if this req is dropped or next is asserted, check for other req's + if(!req[16] | advance) + begin + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + end + grant17: + // if this req is dropped or next is asserted, check for other req's + if(!req[17] | advance) + begin + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + end + grant18: + // if this req is dropped or next is asserted, check for other req's + if(!req[18] | advance) + begin + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + end + grant19: + // if this req is dropped or next is asserted, check for other req's + if(!req[19] | advance) + begin + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + end + grant20: + // if this req is dropped or next is asserted, check for other req's + if(!req[20] | advance) + begin + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + end + grant21: + // if this req is dropped or next is asserted, check for other req's + if(!req[21] | advance) + begin + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + end + grant22: + // if this req is dropped or next is asserted, check for other req's + if(!req[22] | advance) + begin + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + end + grant23: + // if this req is dropped or next is asserted, check for other req's + if(!req[23] | advance) + begin + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + end + grant24: + // if this req is dropped or next is asserted, check for other req's + if(!req[24] | advance) + begin + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + end + grant25: + // if this req is dropped or next is asserted, check for other req's + if(!req[25] | advance) + begin + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + end + grant26: + // if this req is dropped or next is asserted, check for other req's + if(!req[26] | advance) + begin + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + end + grant27: + // if this req is dropped or next is asserted, check for other req's + if(!req[27] | advance) + begin + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + end + grant28: + // if this req is dropped or next is asserted, check for other req's + if(!req[28] | advance) + begin + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + end + grant29: + // if this req is dropped or next is asserted, check for other req's + if(!req[29] | advance) + begin + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + end + grant30: + // if this req is dropped or next is asserted, check for other req's + if(!req[30] | advance) + begin + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + end + endcase + end + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_pri_enc.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_pri_enc.v new file mode 100644 index 000000000..88427eca1 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_pri_enc.v @@ -0,0 +1,384 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Priority Encoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_pri_enc.v,v 1.5 2002/02/01 01:54:44 rudi Exp $ +// +// $Date: 2002/02/01 01:54:44 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_ch_pri_enc.v,v $ +// Revision 1.5 2002/02/01 01:54:44 rudi +// +// - Minor cleanup +// +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.2 2001/08/07 08:00:43 rudi +// +// +// Split up priority encoder modules to separate files +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:50 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +// Priority Encoder +// +// Determines the channel with the highest priority, also takes +// the valid bit in consideration + +module wb_dma_ch_pri_enc(clk, valid, + pri0, pri1, pri2, pri3, + pri4, pri5, pri6, pri7, + pri8, pri9, pri10, pri11, + pri12, pri13, pri14, pri15, + pri16, pri17, pri18, pri19, + pri20, pri21, pri22, pri23, + pri24, pri25, pri26, pri27, + pri28, pri29, pri30, + pri_out); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [1:0] pri_sel = 2'd0; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk; +input [30:0] valid; // Channel Valid bits +input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities +input [2:0] pri4, pri5, pri6, pri7; +input [2:0] pri8, pri9, pri10, pri11; +input [2:0] pri12, pri13, pri14, pri15; +input [2:0] pri16, pri17, pri18, pri19; +input [2:0] pri20, pri21, pri22, pri23; +input [2:0] pri24, pri25, pri26, pri27; +input [2:0] pri28, pri29, pri30; +output [2:0] pri_out; // Highest unserviced priority + +wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out; +wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out; +wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out; +wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out; +wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out; +wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out; +wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out; +wire [7:0] pri28_out, pri29_out, pri30_out; + +wire [7:0] pri_out_tmp; +reg [2:0] pri_out; +reg [2:0] pri_out2; +reg [2:0] pri_out1; +reg [2:0] pri_out0; + +wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder + .valid( valid[0] ), + .pri_in( pri0 ), + .pri_out( pri0_out ) + ); +wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1( + .valid( valid[1] ), + .pri_in( pri1 ), + .pri_out( pri1_out ) + ); +wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2( + .valid( valid[2] ), + .pri_in( pri2 ), + .pri_out( pri2_out ) + ); +wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3( + .valid( valid[3] ), + .pri_in( pri3 ), + .pri_out( pri3_out ) + ); +wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4( + .valid( valid[4] ), + .pri_in( pri4 ), + .pri_out( pri4_out ) + ); +wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5( + .valid( valid[5] ), + .pri_in( pri5 ), + .pri_out( pri5_out ) + ); +wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6( + .valid( valid[6] ), + .pri_in( pri6 ), + .pri_out( pri6_out ) + ); +wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7( + .valid( valid[7] ), + .pri_in( pri7 ), + .pri_out( pri7_out ) + ); +wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8( + .valid( valid[8] ), + .pri_in( pri8 ), + .pri_out( pri8_out ) + ); +wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9( + .valid( valid[9] ), + .pri_in( pri9 ), + .pri_out( pri9_out ) + ); +wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10( + .valid( valid[10] ), + .pri_in( pri10 ), + .pri_out( pri10_out ) + ); +wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11( + .valid( valid[11] ), + .pri_in( pri11 ), + .pri_out( pri11_out ) + ); +wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12( + .valid( valid[12] ), + .pri_in( pri12 ), + .pri_out( pri12_out ) + ); +wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13( + .valid( valid[13] ), + .pri_in( pri13 ), + .pri_out( pri13_out ) + ); +wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14( + .valid( valid[14] ), + .pri_in( pri14 ), + .pri_out( pri14_out ) + ); +wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15( + .valid( valid[15] ), + .pri_in( pri15 ), + .pri_out( pri15_out ) + ); +wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16( + .valid( valid[16] ), + .pri_in( pri16 ), + .pri_out( pri16_out ) + ); +wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17( + .valid( valid[17] ), + .pri_in( pri17 ), + .pri_out( pri17_out ) + ); +wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18( + .valid( valid[18] ), + .pri_in( pri18 ), + .pri_out( pri18_out ) + ); +wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19( + .valid( valid[19] ), + .pri_in( pri19 ), + .pri_out( pri19_out ) + ); +wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20( + .valid( valid[20] ), + .pri_in( pri20 ), + .pri_out( pri20_out ) + ); +wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21( + .valid( valid[21] ), + .pri_in( pri21 ), + .pri_out( pri21_out ) + ); +wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22( + .valid( valid[22] ), + .pri_in( pri22 ), + .pri_out( pri22_out ) + ); +wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23( + .valid( valid[23] ), + .pri_in( pri23 ), + .pri_out( pri23_out ) + ); +wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24( + .valid( valid[24] ), + .pri_in( pri24 ), + .pri_out( pri24_out ) + ); +wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25( + .valid( valid[25] ), + .pri_in( pri25 ), + .pri_out( pri25_out ) + ); +wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26( + .valid( valid[26] ), + .pri_in( pri26 ), + .pri_out( pri26_out ) + ); +wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27( + .valid( valid[27] ), + .pri_in( pri27 ), + .pri_out( pri27_out ) + ); +wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28( + .valid( valid[28] ), + .pri_in( pri28 ), + .pri_out( pri28_out ) + ); +wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29( + .valid( valid[29] ), + .pri_in( pri29 ), + .pri_out( pri29_out ) + ); +wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30( + .valid( valid[30] ), + .pri_in( pri30 ), + .pri_out( pri30_out ) + ); + +assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | + pri4_out | pri5_out | pri6_out | pri7_out | + pri8_out | pri9_out | pri10_out | pri11_out | + pri12_out | pri13_out | pri14_out | pri15_out | + pri16_out | pri17_out | pri18_out | pri19_out | + pri20_out | pri21_out | pri22_out | pri23_out | + pri24_out | pri25_out | pri26_out | pri27_out | + pri28_out | pri29_out | pri30_out; + +// 8 Priority Levels +always @(posedge clk) + if(pri_out_tmp[7]) pri_out2 <= #1 3'h7; + else + if(pri_out_tmp[6]) pri_out2 <= #1 3'h6; + else + if(pri_out_tmp[5]) pri_out2 <= #1 3'h5; + else + if(pri_out_tmp[4]) pri_out2 <= #1 3'h4; + else + if(pri_out_tmp[3]) pri_out2 <= #1 3'h3; + else + if(pri_out_tmp[2]) pri_out2 <= #1 3'h2; + else + if(pri_out_tmp[1]) pri_out2 <= #1 3'h1; + else pri_out2 <= #1 3'h0; + +// 4 Priority Levels +always @(posedge clk) + if(pri_out_tmp[3]) pri_out1 <= #1 3'h3; + else + if(pri_out_tmp[2]) pri_out1 <= #1 3'h2; + else + if(pri_out_tmp[1]) pri_out1 <= #1 3'h1; + else pri_out1 <= #1 3'h0; + +// 2 Priority Levels +always @(posedge clk) + if(pri_out_tmp[1]) pri_out0 <= #1 3'h1; + else pri_out0 <= #1 3'h0; + +// Select configured priority +always @(pri_sel or pri_out0 or pri_out1 or pri_out2) + case(pri_sel) // synopsys parallel_case full_case + 2'd0: pri_out = pri_out0; + 2'd1: pri_out = pri_out1; + 2'd2: pri_out = pri_out2; + endcase + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_rf.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_rf.v new file mode 100644 index 000000000..fa580cafb --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_rf.v @@ -0,0 +1,587 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA One Channel Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_rf.v,v 1.5 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_ch_rf.v,v $ +// Revision 1.5 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.4 2001/10/30 02:06:17 rudi +// +// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/14 08:50:01 rudi +// +// Changed Module Name to match file name. +// +// Revision 1.2 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.1 2001/06/05 10:25:27 rudi +// +// +// Initial checkin of register file for one channel. +// +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_ch_rf( clk, rst, + pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, + ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, + + wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, + de_fetch_descr, dma_rest, + ptr_set + + ); + +parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID +parameter [0:0] CH_EN = 1'b1; // This channel exists +parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS +parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors +parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers + +input clk, rst; + +output [31:0] pointer; +output [31:0] pointer_s; +output [31:0] ch_csr; +output [31:0] ch_txsz; +output [31:0] ch_adr0; +output [31:0] ch_adr1; +output [31:0] ch_am0; +output [31:0] ch_am1; +output [31:0] sw_pointer; +output ch_stop; +output ch_dis; +output int; + +input [31:0] wb_rf_din; +input [7:0] wb_rf_adr; +input wb_rf_we; +input wb_rf_re; + +input [4:0] ch_sel; +input ndnr; + +// DMA Engine Status +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire [31:0] pointer; +reg [27:0] pointer_r; +reg [27:0] pointer_sr; +reg ptr_valid; +reg ch_eol; + +wire [31:0] ch_csr, ch_txsz; + +reg [8:0] ch_csr_r; +reg [2:0] ch_csr_r2; +reg [2:0] ch_csr_r3; +reg [2:0] int_src_r; +reg ch_err_r; +reg ch_stop; +reg ch_busy; +reg ch_done; +reg ch_err; +reg rest_en; + +reg [10:0] ch_chk_sz_r; +reg [11:0] ch_tot_sz_r; +reg [22:0] ch_txsz_s; +reg ch_sz_inf; + +wire [31:0] ch_adr0, ch_adr1; +reg [29:0] ch_adr0_r, ch_adr1_r; +wire [31:0] ch_am0, ch_am1; +reg [27:0] ch_am0_r, ch_am1_r; + +reg [29:0] ch_adr0_s, ch_adr1_s; + +reg [29:0] sw_pointer_r; +wire sw_pointer_we; +wire [28:0] cmp_adr; +reg ch_dis; +wire ch_enable; + +wire pointer_we; +wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we; +wire ch_am0_we, ch_am1_we; +reg ch_rl; +wire ch_done_we; +wire ch_err_we; +wire chunk_done_we; + +wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe; + +wire this_ptr_set; +wire ptr_inv; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0; +assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0; +assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0; +assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0; +assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0; + +assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0; +assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0; +assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2, + ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0; +assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0; + +assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// CH0 control signals +// + +parameter [4:0] CH_ADR = CH_NO + 5'h1; + +assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); +assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); +assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1); +assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2); +assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3); +assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4); +assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5); +assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6); +assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7); + +assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) & + (ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]); +assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done; +assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err; +assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO); +assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO); +assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO); +assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO); + +assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr; +assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO); + +always @(posedge clk) + ch_rl <= #1 CH_EN & HAVE_ARS & ( + (rest_en & dma_rest) | + ((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED]) + ); + +// --------------------------------------------------- +// Pointers + +always @(posedge clk or negedge rst) + if(!rst) ptr_valid <= #1 1'b0; + else + if(CH_EN & HAVE_ED) + begin + if( this_ptr_set | (rest_en & dma_rest) ) + ptr_valid <= #1 1'b1; + else + if(ptr_inv) ptr_valid <= #1 1'b0; + end + else ptr_valid <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) ch_eol <= #1 1'b0; + else + if(CH_EN & HAVE_ED) + begin + if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL]; + else + if(ch_done_we) ch_eol <= #1 1'b0; + end + else ch_eol <= #1 1'b0; + +always @(posedge clk) + if(CH_EN & HAVE_ED) + begin + if(pointer_we) pointer_r <= #1 wb_rf_din[31:4]; + else + if(this_ptr_set) pointer_r <= #1 de_csr[31:4]; + end + else pointer_r <= #1 1'b0; + +always @(posedge clk) + if(CH_EN & HAVE_ED) + begin + if(this_ptr_set) pointer_sr <= #1 pointer_r; + end + else pointer_sr <= #1 1'b0; + +// --------------------------------------------------- +// CSR + +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0]; + else + begin + if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0; + if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16]; + end + end + +// done bit +always @(posedge clk or negedge rst) + if(!rst) ch_done <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN]; + else + if(ch_done_we) ch_done <= #1 1'b1; + end + +// busy bit +always @(posedge clk) + ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy; + +// stop bit +always @(posedge clk) + ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP]; + +// error bit +always @(posedge clk or negedge rst) + if(!rst) ch_err <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_err_we) ch_err <= #1 1'b1; + else + if(ch_csr_re) ch_err <= #1 1'b0; + end + +// Priority Bits +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r2 <= #1 3'h0; + else + if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13]; + +// Restart Enable Bit (REST) +always @(posedge clk or negedge rst) + if(!rst) rest_en <= #1 1'b0; + else + if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16]; + +// INT Mask +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r3 <= #1 3'h0; + else + if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17]; + +// INT Source +always @(posedge clk or negedge rst) + if(!rst) int_src_r[2] <= #1 1'b0; + else + if(CH_EN) + begin + if(chunk_done_we) int_src_r[2] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[2] <= #1 1'b0; + end + +always @(posedge clk or negedge rst) + if(!rst) int_src_r[1] <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_done_we) int_src_r[1] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[1] <= #1 1'b0; + end + +always @(posedge clk or negedge rst) + if(!rst) int_src_r[0] <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_err_we) int_src_r[0] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[0] <= #1 1'b0; + end + +// Interrupt Output +assign int = |(int_src_r & ch_csr_r3) & CH_EN; + +// --------------------------------------------------- +// TXZS +always @(posedge clk) + if(CH_EN) + begin + if(ch_txsz_we) + {ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; + else + if(ch_txsz_dewe) + ch_tot_sz_r <= #1 de_txsz; + else + if(ch_rl) + {ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; + end + +// txsz shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + + if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; + else + if(rest_en & ch_txsz_dewe & de_fetch_descr) + ch_txsz_s[11:0] <= #1 de_txsz[11:0]; + end + +// Infinite Size indicator +always @(posedge clk) + if(CH_EN) + begin + if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15]; + end + +// --------------------------------------------------- +// ADR0 +always @(posedge clk) + if(CH_EN) + begin + if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2]; + else + if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2]; + else + if(ch_rl) ch_adr0_r <= #1 ch_adr0_s; + end + +// Adr0 shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2]; + else + if(rest_en & ch_adr0_dewe & de_fetch_descr) + ch_adr0_s <= #1 de_adr0[31:2]; + end + +// --------------------------------------------------- +// AM0 +always @(posedge clk or negedge rst) + if(!rst) ch_am0_r <= #1 28'hfffffff; + else + if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// ADR1 +always @(posedge clk) + if(CH_EN) + begin + if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2]; + else + if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2]; + else + if(ch_rl) ch_adr1_r <= #1 ch_adr1_s; + end + +// Adr1 shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2]; + else + if(rest_en & ch_adr1_dewe & de_fetch_descr) + ch_adr1_s <= #1 de_adr1[31:2]; + end + +// --------------------------------------------------- +// AM1 +always @(posedge clk or negedge rst) + if(!rst) ch_am1_r <= #1 28'hfffffff; + else + if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// Software Pointer +always @(posedge clk or negedge rst) + if(!rst) sw_pointer_r <= #1 28'h0; + else + if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// Software Pointer Match logic + +assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2]; + +always @(posedge clk) + ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31]; + +endmodule + + +module wb_dma_ch_rf_dummy(clk, rst, + pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, + ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, + + wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, + de_fetch_descr, dma_rest, + ptr_set + + ); + +parameter CH_NO = 0; +parameter HAVE_ARS = 1; +parameter HAVE_ED = 1; +parameter HAVE_CBUF= 1; + +input clk, rst; + +output [31:0] pointer; +output [31:0] pointer_s; +output [31:0] ch_csr; +output [31:0] ch_txsz; +output [31:0] ch_adr0; +output [31:0] ch_adr1; +output [31:0] ch_am0; +output [31:0] ch_am1; +output [31:0] sw_pointer; +output ch_stop; +output ch_dis; +output int; + +input [31:0] wb_rf_din; +input [7:0] wb_rf_adr; +input wb_rf_we; +input wb_rf_re; + +input [4:0] ch_sel; +input ndnr; + +// DMA Engine Status +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input dma_rest; + +assign pointer = 32'h0; +assign pointer_s = 32'h0; +assign ch_csr = 32'h0; +assign ch_txsz = 32'h0; +assign ch_adr0 = 32'h0; +assign ch_adr1 = 32'h0; +assign ch_am0 = 32'h0; +assign ch_am1 = 32'h0; +assign sw_pointer = 32'h0; +assign ch_stop = 1'b0; +assign ch_dis = 1'b0; +assign int = 1'b0; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_sel.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_sel.v new file mode 100644 index 000000000..210cb3a9b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_ch_sel.v @@ -0,0 +1,1392 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Channel Select //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_sel.v,v 1.4 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_ch_sel.v,v $ +// Revision 1.4 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:52:00 rudi +// +// +// Changed arbiter module name. +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:35 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_ch_sel(clk, rst, + + // DMA Request Lines + req_i, ack_o, nd_i, + + // DMA Registers Inputs + pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, + pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, + pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, + pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, + pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, + pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, + pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, + pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, + pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, + pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, + pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, + pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, + pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, + pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, + pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, + pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, + pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, + pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, + pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, + pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, + pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, + pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, + pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, + pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, + pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, + pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, + pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, + pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, + pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, + pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, + pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Interface + de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1, + pointer_s, next_ch, de_ack, dma_busy + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [1:0] pri_sel = 2'h0; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk, rst; + +// DMA Request Lines +input [30:0] req_i; +output [30:0] ack_o; +input [30:0] nd_i; + +// Channel Registers Inputs +input [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +input [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +input [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +input [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +input [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +input [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +input [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +input [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +input [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +input [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +input [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +input [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +input [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +input [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +input [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +input [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +input [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +input [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +input [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +input [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +input [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +input [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +input [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +input [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +input [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +input [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +input [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +input [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +input [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +input [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +input [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +output [4:0] ch_sel; // Write Back Channel Select +output [30:0] ndnr; // Next Descriptor No Request + +output de_start; // Start DMA Engine Indicator +output ndr; // Next Descriptor With Request (for current channel) +output [31:0] csr; // Selected Channel CSR +output [31:0] pointer; // LL Descriptor pointer +output [31:0] pointer_s; // LL Descriptor previous pointer +output [31:0] txsz; // Selected Channel Transfer Size +output [31:0] adr0, adr1; // Selected Channel Addresses +output [31:0] am0, am1; // Selected Channel Address Masks + +input next_ch; // Indicates the DMA Engine is done + // with current transfer +input de_ack; // DMA engine ack output + +input dma_busy; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [30:0] ack_o; +wire [30:0] valid; // Indicates which channel is valid +reg valid_sel; +reg [30:0] req_r; // Channel Request inputs +reg [30:0] ndr_r; // Next Descriptor Registered (and Request) +reg [30:0] ndnr; // Next Descriptor Registered (and Not Request) +wire [2:0] pri_out; // Highest unserviced priority +wire [2:0] pri0, pri1, pri2, pri3; // Channel Priorities +wire [2:0] pri4, pri5, pri6, pri7; +wire [2:0] pri8, pri9, pri10, pri11; +wire [2:0] pri12, pri13, pri14, pri15; +wire [2:0] pri16, pri17, pri18, pri19; +wire [2:0] pri20, pri21, pri22, pri23; +wire [2:0] pri24, pri25, pri26, pri27; +wire [2:0] pri28, pri29, pri30; +reg [4:0] ch_sel_d; +reg [4:0] ch_sel_r; + +reg ndr; +reg next_start; +reg de_start_r; +reg [31:0] csr; // Selected Channel CSR +reg [31:0] pointer; +reg [31:0] pointer_s; +reg [31:0] txsz; // Selected Channel Transfer Size +reg [31:0] adr0, adr1; // Selected Channel Addresses +reg [31:0] am0, am1; // Selected Channel Address Masks + + // Arbiter Request Inputs +wire [30:0] req_p0, req_p1, req_p2, req_p3; +wire [30:0] req_p4, req_p5, req_p6, req_p7; +wire [30:0] req_p8, req_p9, req_p10, req_p11; +wire [30:0] req_p12, req_p13, req_p14, req_p15; +wire [30:0] req_p16, req_p17, req_p18, req_p19; +wire [30:0] req_p20, req_p21, req_p22, req_p23; +wire [30:0] req_p24, req_p25, req_p26, req_p27; +wire [30:0] req_p28, req_p29, req_p30; + // Arbiter Grant Outputs +wire [4:0] gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d; +wire [4:0] gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d; +wire [4:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; +wire [4:0] gnt_p4, gnt_p5, gnt_p6, gnt_p7; +wire [4:0] gnt_p8, gnt_p9, gnt_p10, gnt_p11; +wire [4:0] gnt_p12, gnt_p13, gnt_p14, gnt_p15; +wire [4:0] gnt_p16, gnt_p17, gnt_p18, gnt_p19; +wire [4:0] gnt_p20, gnt_p21, gnt_p22, gnt_p23; +wire [4:0] gnt_p24, gnt_p25, gnt_p26, gnt_p27; +wire [4:0] gnt_p28, gnt_p29, gnt_p30; + + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign pri0[0] = ch0_csr[13]; +assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14]; +assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0; +assign pri1[0] = ch1_csr[13]; +assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14]; +assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0; +assign pri2[0] = ch2_csr[13]; +assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14]; +assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0; +assign pri3[0] = ch3_csr[13]; +assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14]; +assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0; +assign pri4[0] = ch4_csr[13]; +assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14]; +assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0; +assign pri5[0] = ch5_csr[13]; +assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14]; +assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0; +assign pri6[0] = ch6_csr[13]; +assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14]; +assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0; +assign pri7[0] = ch7_csr[13]; +assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14]; +assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0; +assign pri8[0] = ch8_csr[13]; +assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14]; +assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0; +assign pri9[0] = ch9_csr[13]; +assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14]; +assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0; +assign pri10[0] = ch10_csr[13]; +assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14]; +assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0; +assign pri11[0] = ch11_csr[13]; +assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14]; +assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0; +assign pri12[0] = ch12_csr[13]; +assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14]; +assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0; +assign pri13[0] = ch13_csr[13]; +assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14]; +assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0; +assign pri14[0] = ch14_csr[13]; +assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14]; +assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0; +assign pri15[0] = ch15_csr[13]; +assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14]; +assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0; +assign pri16[0] = ch16_csr[13]; +assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14]; +assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0; +assign pri17[0] = ch17_csr[13]; +assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14]; +assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0; +assign pri18[0] = ch18_csr[13]; +assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14]; +assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0; +assign pri19[0] = ch19_csr[13]; +assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14]; +assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0; +assign pri20[0] = ch20_csr[13]; +assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14]; +assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0; +assign pri21[0] = ch21_csr[13]; +assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14]; +assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0; +assign pri22[0] = ch22_csr[13]; +assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14]; +assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0; +assign pri23[0] = ch23_csr[13]; +assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14]; +assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0; +assign pri24[0] = ch24_csr[13]; +assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14]; +assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0; +assign pri25[0] = ch25_csr[13]; +assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14]; +assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0; +assign pri26[0] = ch26_csr[13]; +assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14]; +assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0; +assign pri27[0] = ch27_csr[13]; +assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14]; +assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0; +assign pri28[0] = ch28_csr[13]; +assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14]; +assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0; +assign pri29[0] = ch29_csr[13]; +assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14]; +assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0; +assign pri30[0] = ch30_csr[13]; +assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14]; +assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Misc logic +// + +// Chanel Valid flag +// The valid flag is asserted when the channel is enabled, +// and is either in "normal mode" (software control) or +// "hw handshake mode" (reqN control) +// validN = ch_enabled & (sw_mode | (hw_mode & reqN) ) + +always @(posedge clk) + req_r <= #1 req_i & ~ack_o; + +assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1); +assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1); +assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1); +assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1); +assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1); +assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1); +assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1); +assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1); +assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1); +assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1); +assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1); +assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1); +assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1); +assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1); +assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1); +assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1); +assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1); +assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1); +assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1); +assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1); +assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1); +assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1); +assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1); +assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1); +assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1); +assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1); +assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1); +assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1); +assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1); +assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1); +assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1); + +always @(posedge clk) + ndr_r <= #1 nd_i & req_i; + +always @(posedge clk) + ndnr <= #1 nd_i & ~req_i; + +// Start Signal for DMA engine +assign de_start = (valid_sel & !de_start_r ) | next_start; + +always @(posedge clk) + de_start_r <= #1 valid_sel; + +always @(posedge clk) + next_start <= #1 next_ch & valid_sel; + +// Ack outputs for HW handshake mode +always @(posedge clk) + ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack; + +// Channel Select +always @(posedge clk or negedge rst) + if(!rst) ch_sel_r <= #1 0; + else + if(de_start) ch_sel_r <= #1 ch_sel_d; + +assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r; + +//////////////////////////////////////////////////////////////////// +// +// Select Registers based on arbiter (and priority) outputs +// + +always @(ch_sel or valid) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: valid_sel = valid[0]; + 5'h1: valid_sel = valid[1]; + 5'h2: valid_sel = valid[2]; + 5'h3: valid_sel = valid[3]; + 5'h4: valid_sel = valid[4]; + 5'h5: valid_sel = valid[5]; + 5'h6: valid_sel = valid[6]; + 5'h7: valid_sel = valid[7]; + 5'h8: valid_sel = valid[8]; + 5'h9: valid_sel = valid[9]; + 5'ha: valid_sel = valid[10]; + 5'hb: valid_sel = valid[11]; + 5'hc: valid_sel = valid[12]; + 5'hd: valid_sel = valid[13]; + 5'he: valid_sel = valid[14]; + 5'hf: valid_sel = valid[15]; + 5'h10: valid_sel = valid[16]; + 5'h11: valid_sel = valid[17]; + 5'h12: valid_sel = valid[18]; + 5'h13: valid_sel = valid[19]; + 5'h14: valid_sel = valid[20]; + 5'h15: valid_sel = valid[21]; + 5'h16: valid_sel = valid[22]; + 5'h17: valid_sel = valid[23]; + 5'h18: valid_sel = valid[24]; + 5'h19: valid_sel = valid[25]; + 5'h1a: valid_sel = valid[26]; + 5'h1b: valid_sel = valid[27]; + 5'h1c: valid_sel = valid[28]; + 5'h1d: valid_sel = valid[29]; + 5'h1e: valid_sel = valid[30]; + endcase + +always @(ch_sel or ndr_r) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: ndr = ndr_r[0]; + 5'h1: ndr = ndr_r[1]; + 5'h2: ndr = ndr_r[2]; + 5'h3: ndr = ndr_r[3]; + 5'h4: ndr = ndr_r[4]; + 5'h5: ndr = ndr_r[5]; + 5'h6: ndr = ndr_r[6]; + 5'h7: ndr = ndr_r[7]; + 5'h8: ndr = ndr_r[8]; + 5'h9: ndr = ndr_r[9]; + 5'ha: ndr = ndr_r[10]; + 5'hb: ndr = ndr_r[11]; + 5'hc: ndr = ndr_r[12]; + 5'hd: ndr = ndr_r[13]; + 5'he: ndr = ndr_r[14]; + 5'hf: ndr = ndr_r[15]; + 5'h10: ndr = ndr_r[16]; + 5'h11: ndr = ndr_r[17]; + 5'h12: ndr = ndr_r[18]; + 5'h13: ndr = ndr_r[19]; + 5'h14: ndr = ndr_r[20]; + 5'h15: ndr = ndr_r[21]; + 5'h16: ndr = ndr_r[22]; + 5'h17: ndr = ndr_r[23]; + 5'h18: ndr = ndr_r[24]; + 5'h19: ndr = ndr_r[25]; + 5'h1a: ndr = ndr_r[26]; + 5'h1b: ndr = ndr_r[27]; + 5'h1c: ndr = ndr_r[28]; + 5'h1d: ndr = ndr_r[29]; + 5'h1e: ndr = ndr_r[30]; + endcase + +always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4 + or pointer5 or pointer6 or pointer7 or pointer8 or pointer9 + or pointer10 or pointer11 or pointer12 or pointer13 or pointer14 + or pointer15 or pointer16 or pointer17 or pointer18 or pointer19 + or pointer20 or pointer21 or pointer22 or pointer23 or pointer24 + or pointer25 or pointer26 or pointer27 or pointer28 or pointer29 + or pointer30 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: pointer = pointer0; + 5'h1: pointer = pointer1; + 5'h2: pointer = pointer2; + 5'h3: pointer = pointer3; + 5'h4: pointer = pointer4; + 5'h5: pointer = pointer5; + 5'h6: pointer = pointer6; + 5'h7: pointer = pointer7; + 5'h8: pointer = pointer8; + 5'h9: pointer = pointer9; + 5'ha: pointer = pointer10; + 5'hb: pointer = pointer11; + 5'hc: pointer = pointer12; + 5'hd: pointer = pointer13; + 5'he: pointer = pointer14; + 5'hf: pointer = pointer15; + 5'h10: pointer = pointer16; + 5'h11: pointer = pointer17; + 5'h12: pointer = pointer18; + 5'h13: pointer = pointer19; + 5'h14: pointer = pointer20; + 5'h15: pointer = pointer21; + 5'h16: pointer = pointer22; + 5'h17: pointer = pointer23; + 5'h18: pointer = pointer24; + 5'h19: pointer = pointer25; + 5'h1a: pointer = pointer26; + 5'h1b: pointer = pointer27; + 5'h1c: pointer = pointer28; + 5'h1d: pointer = pointer29; + 5'h1e: pointer = pointer30; + endcase + +always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s + or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s + or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s + or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s + or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s + or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s + or pointer30_s ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: pointer_s = pointer0_s; + 5'h1: pointer_s = pointer1_s; + 5'h2: pointer_s = pointer2_s; + 5'h3: pointer_s = pointer3_s; + 5'h4: pointer_s = pointer4_s; + 5'h5: pointer_s = pointer5_s; + 5'h6: pointer_s = pointer6_s; + 5'h7: pointer_s = pointer7_s; + 5'h8: pointer_s = pointer8_s; + 5'h9: pointer_s = pointer9_s; + 5'ha: pointer_s = pointer10_s; + 5'hb: pointer_s = pointer11_s; + 5'hc: pointer_s = pointer12_s; + 5'hd: pointer_s = pointer13_s; + 5'he: pointer_s = pointer14_s; + 5'hf: pointer_s = pointer15_s; + 5'h10: pointer_s = pointer16_s; + 5'h11: pointer_s = pointer17_s; + 5'h12: pointer_s = pointer18_s; + 5'h13: pointer_s = pointer19_s; + 5'h14: pointer_s = pointer20_s; + 5'h15: pointer_s = pointer21_s; + 5'h16: pointer_s = pointer22_s; + 5'h17: pointer_s = pointer23_s; + 5'h18: pointer_s = pointer24_s; + 5'h19: pointer_s = pointer25_s; + 5'h1a: pointer_s = pointer26_s; + 5'h1b: pointer_s = pointer27_s; + 5'h1c: pointer_s = pointer28_s; + 5'h1d: pointer_s = pointer29_s; + 5'h1e: pointer_s = pointer30_s; + endcase + +always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr + or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr + or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr + or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr + or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr + or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr + or ch30_csr ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: csr = ch0_csr; + 5'h1: csr = ch1_csr; + 5'h2: csr = ch2_csr; + 5'h3: csr = ch3_csr; + 5'h4: csr = ch4_csr; + 5'h5: csr = ch5_csr; + 5'h6: csr = ch6_csr; + 5'h7: csr = ch7_csr; + 5'h8: csr = ch8_csr; + 5'h9: csr = ch9_csr; + 5'ha: csr = ch10_csr; + 5'hb: csr = ch11_csr; + 5'hc: csr = ch12_csr; + 5'hd: csr = ch13_csr; + 5'he: csr = ch14_csr; + 5'hf: csr = ch15_csr; + 5'h10: csr = ch16_csr; + 5'h11: csr = ch17_csr; + 5'h12: csr = ch18_csr; + 5'h13: csr = ch19_csr; + 5'h14: csr = ch20_csr; + 5'h15: csr = ch21_csr; + 5'h16: csr = ch22_csr; + 5'h17: csr = ch23_csr; + 5'h18: csr = ch24_csr; + 5'h19: csr = ch25_csr; + 5'h1a: csr = ch26_csr; + 5'h1b: csr = ch27_csr; + 5'h1c: csr = ch28_csr; + 5'h1d: csr = ch29_csr; + 5'h1e: csr = ch30_csr; + endcase + +always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz + or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz + or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz + or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz + or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz + or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz + or ch30_txsz ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: txsz = ch0_txsz; + 5'h1: txsz = ch1_txsz; + 5'h2: txsz = ch2_txsz; + 5'h3: txsz = ch3_txsz; + 5'h4: txsz = ch4_txsz; + 5'h5: txsz = ch5_txsz; + 5'h6: txsz = ch6_txsz; + 5'h7: txsz = ch7_txsz; + 5'h8: txsz = ch8_txsz; + 5'h9: txsz = ch9_txsz; + 5'ha: txsz = ch10_txsz; + 5'hb: txsz = ch11_txsz; + 5'hc: txsz = ch12_txsz; + 5'hd: txsz = ch13_txsz; + 5'he: txsz = ch14_txsz; + 5'hf: txsz = ch15_txsz; + 5'h10: txsz = ch16_txsz; + 5'h11: txsz = ch17_txsz; + 5'h12: txsz = ch18_txsz; + 5'h13: txsz = ch19_txsz; + 5'h14: txsz = ch20_txsz; + 5'h15: txsz = ch21_txsz; + 5'h16: txsz = ch22_txsz; + 5'h17: txsz = ch23_txsz; + 5'h18: txsz = ch24_txsz; + 5'h19: txsz = ch25_txsz; + 5'h1a: txsz = ch26_txsz; + 5'h1b: txsz = ch27_txsz; + 5'h1c: txsz = ch28_txsz; + 5'h1d: txsz = ch29_txsz; + 5'h1e: txsz = ch30_txsz; + endcase + +always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0 + or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0 + or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0 + or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0 + or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0 + or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0 + or ch30_adr0 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: adr0 = ch0_adr0; + 5'h1: adr0 = ch1_adr0; + 5'h2: adr0 = ch2_adr0; + 5'h3: adr0 = ch3_adr0; + 5'h4: adr0 = ch4_adr0; + 5'h5: adr0 = ch5_adr0; + 5'h6: adr0 = ch6_adr0; + 5'h7: adr0 = ch7_adr0; + 5'h8: adr0 = ch8_adr0; + 5'h9: adr0 = ch9_adr0; + 5'ha: adr0 = ch10_adr0; + 5'hb: adr0 = ch11_adr0; + 5'hc: adr0 = ch12_adr0; + 5'hd: adr0 = ch13_adr0; + 5'he: adr0 = ch14_adr0; + 5'hf: adr0 = ch15_adr0; + 5'h10: adr0 = ch16_adr0; + 5'h11: adr0 = ch17_adr0; + 5'h12: adr0 = ch18_adr0; + 5'h13: adr0 = ch19_adr0; + 5'h14: adr0 = ch20_adr0; + 5'h15: adr0 = ch21_adr0; + 5'h16: adr0 = ch22_adr0; + 5'h17: adr0 = ch23_adr0; + 5'h18: adr0 = ch24_adr0; + 5'h19: adr0 = ch25_adr0; + 5'h1a: adr0 = ch26_adr0; + 5'h1b: adr0 = ch27_adr0; + 5'h1c: adr0 = ch28_adr0; + 5'h1d: adr0 = ch29_adr0; + 5'h1e: adr0 = ch30_adr0; + endcase + +always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1 + or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1 + or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1 + or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1 + or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1 + or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1 + or ch30_adr1 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: adr1 = ch0_adr1; + 5'h1: adr1 = ch1_adr1; + 5'h2: adr1 = ch2_adr1; + 5'h3: adr1 = ch3_adr1; + 5'h4: adr1 = ch4_adr1; + 5'h5: adr1 = ch5_adr1; + 5'h6: adr1 = ch6_adr1; + 5'h7: adr1 = ch7_adr1; + 5'h8: adr1 = ch8_adr1; + 5'h9: adr1 = ch9_adr1; + 5'ha: adr1 = ch10_adr1; + 5'hb: adr1 = ch11_adr1; + 5'hc: adr1 = ch12_adr1; + 5'hd: adr1 = ch13_adr1; + 5'he: adr1 = ch14_adr1; + 5'hf: adr1 = ch15_adr1; + 5'h10: adr1 = ch16_adr1; + 5'h11: adr1 = ch17_adr1; + 5'h12: adr1 = ch18_adr1; + 5'h13: adr1 = ch19_adr1; + 5'h14: adr1 = ch20_adr1; + 5'h15: adr1 = ch21_adr1; + 5'h16: adr1 = ch22_adr1; + 5'h17: adr1 = ch23_adr1; + 5'h18: adr1 = ch24_adr1; + 5'h19: adr1 = ch25_adr1; + 5'h1a: adr1 = ch26_adr1; + 5'h1b: adr1 = ch27_adr1; + 5'h1c: adr1 = ch28_adr1; + 5'h1d: adr1 = ch29_adr1; + 5'h1e: adr1 = ch30_adr1; + endcase + +always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0 + or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0 + or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0 + or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0 + or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0 + or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0 + or ch30_am0 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: am0 = ch0_am0; + 5'h1: am0 = ch1_am0; + 5'h2: am0 = ch2_am0; + 5'h3: am0 = ch3_am0; + 5'h4: am0 = ch4_am0; + 5'h5: am0 = ch5_am0; + 5'h6: am0 = ch6_am0; + 5'h7: am0 = ch7_am0; + 5'h8: am0 = ch8_am0; + 5'h9: am0 = ch9_am0; + 5'ha: am0 = ch10_am0; + 5'hb: am0 = ch11_am0; + 5'hc: am0 = ch12_am0; + 5'hd: am0 = ch13_am0; + 5'he: am0 = ch14_am0; + 5'hf: am0 = ch15_am0; + 5'h10: am0 = ch16_am0; + 5'h11: am0 = ch17_am0; + 5'h12: am0 = ch18_am0; + 5'h13: am0 = ch19_am0; + 5'h14: am0 = ch20_am0; + 5'h15: am0 = ch21_am0; + 5'h16: am0 = ch22_am0; + 5'h17: am0 = ch23_am0; + 5'h18: am0 = ch24_am0; + 5'h19: am0 = ch25_am0; + 5'h1a: am0 = ch26_am0; + 5'h1b: am0 = ch27_am0; + 5'h1c: am0 = ch28_am0; + 5'h1d: am0 = ch29_am0; + 5'h1e: am0 = ch30_am0; + endcase + +always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1 + or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1 + or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1 + or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1 + or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1 + or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1 + or ch30_am1 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: am1 = ch0_am1; + 5'h1: am1 = ch1_am1; + 5'h2: am1 = ch2_am1; + 5'h3: am1 = ch3_am1; + 5'h4: am1 = ch4_am1; + 5'h5: am1 = ch5_am1; + 5'h6: am1 = ch6_am1; + 5'h7: am1 = ch7_am1; + 5'h8: am1 = ch8_am1; + 5'h9: am1 = ch9_am1; + 5'ha: am1 = ch10_am1; + 5'hb: am1 = ch11_am1; + 5'hc: am1 = ch12_am1; + 5'hd: am1 = ch13_am1; + 5'he: am1 = ch14_am1; + 5'hf: am1 = ch15_am1; + 5'h10: am1 = ch16_am1; + 5'h11: am1 = ch17_am1; + 5'h12: am1 = ch18_am1; + 5'h13: am1 = ch19_am1; + 5'h14: am1 = ch20_am1; + 5'h15: am1 = ch21_am1; + 5'h16: am1 = ch22_am1; + 5'h17: am1 = ch23_am1; + 5'h18: am1 = ch24_am1; + 5'h19: am1 = ch25_am1; + 5'h1a: am1 = ch26_am1; + 5'h1b: am1 = ch27_am1; + 5'h1c: am1 = ch28_am1; + 5'h1d: am1 = ch29_am1; + 5'h1e: am1 = ch30_am1; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Actual Chanel Arbiter and Priority Encoder +// + +// Select the arbiter for current highest priority +always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4 + or gnt_p5 or gnt_p6 or gnt_p7 ) + case(pri_out) // synopsys parallel_case full_case + 3'h0: ch_sel_d = gnt_p0; + 3'h1: ch_sel_d = gnt_p1; + 3'h2: ch_sel_d = gnt_p2; + 3'h3: ch_sel_d = gnt_p3; + 3'h4: ch_sel_d = gnt_p4; + 3'h5: ch_sel_d = gnt_p5; + 3'h6: ch_sel_d = gnt_p6; + 3'h7: ch_sel_d = gnt_p7; + endcase + + +// Priority Encoder +wb_dma_ch_pri_enc + #( pri_sel, + ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u0( + .clk( clk ), + .valid( valid ), + .pri0( pri0 ), + .pri1( pri1 ), + .pri2( pri2 ), + .pri3( pri3 ), + .pri4( pri4 ), + .pri5( pri5 ), + .pri6( pri6 ), + .pri7( pri7 ), + .pri8( pri8 ), + .pri9( pri9 ), + .pri10( pri10 ), + .pri11( pri11 ), + .pri12( pri12 ), + .pri13( pri13 ), + .pri14( pri14 ), + .pri15( pri15 ), + .pri16( pri16 ), + .pri17( pri17 ), + .pri18( pri18 ), + .pri19( pri19 ), + .pri20( pri20 ), + .pri21( pri21 ), + .pri22( pri22 ), + .pri23( pri23 ), + .pri24( pri24 ), + .pri25( pri25 ), + .pri26( pri26 ), + .pri27( pri27 ), + .pri28( pri28 ), + .pri29( pri29 ), + .pri30( pri30 ), + .pri_out( pri_out ) + ); + +// Arbiter request lines +// Generate request depending on priority and valid bits + +assign req_p0[0] = valid[0] & (pri0==3'h0); +assign req_p0[1] = valid[1] & (pri1==3'h0); +assign req_p0[2] = valid[2] & (pri2==3'h0); +assign req_p0[3] = valid[3] & (pri3==3'h0); +assign req_p0[4] = valid[4] & (pri4==3'h0); +assign req_p0[5] = valid[5] & (pri5==3'h0); +assign req_p0[6] = valid[6] & (pri6==3'h0); +assign req_p0[7] = valid[7] & (pri7==3'h0); +assign req_p0[8] = valid[8] & (pri8==3'h0); +assign req_p0[9] = valid[9] & (pri9==3'h0); +assign req_p0[10] = valid[10] & (pri10==3'h0); +assign req_p0[11] = valid[11] & (pri11==3'h0); +assign req_p0[12] = valid[12] & (pri12==3'h0); +assign req_p0[13] = valid[13] & (pri13==3'h0); +assign req_p0[14] = valid[14] & (pri14==3'h0); +assign req_p0[15] = valid[15] & (pri15==3'h0); +assign req_p0[16] = valid[16] & (pri16==3'h0); +assign req_p0[17] = valid[17] & (pri17==3'h0); +assign req_p0[18] = valid[18] & (pri18==3'h0); +assign req_p0[19] = valid[19] & (pri19==3'h0); +assign req_p0[20] = valid[20] & (pri20==3'h0); +assign req_p0[21] = valid[21] & (pri21==3'h0); +assign req_p0[22] = valid[22] & (pri22==3'h0); +assign req_p0[23] = valid[23] & (pri23==3'h0); +assign req_p0[24] = valid[24] & (pri24==3'h0); +assign req_p0[25] = valid[25] & (pri25==3'h0); +assign req_p0[26] = valid[26] & (pri26==3'h0); +assign req_p0[27] = valid[27] & (pri27==3'h0); +assign req_p0[28] = valid[28] & (pri28==3'h0); +assign req_p0[29] = valid[29] & (pri29==3'h0); +assign req_p0[30] = valid[30] & (pri30==3'h0); + +assign req_p1[0] = valid[0] & (pri0==3'h1); +assign req_p1[1] = valid[1] & (pri1==3'h1); +assign req_p1[2] = valid[2] & (pri2==3'h1); +assign req_p1[3] = valid[3] & (pri3==3'h1); +assign req_p1[4] = valid[4] & (pri4==3'h1); +assign req_p1[5] = valid[5] & (pri5==3'h1); +assign req_p1[6] = valid[6] & (pri6==3'h1); +assign req_p1[7] = valid[7] & (pri7==3'h1); +assign req_p1[8] = valid[8] & (pri8==3'h1); +assign req_p1[9] = valid[9] & (pri9==3'h1); +assign req_p1[10] = valid[10] & (pri10==3'h1); +assign req_p1[11] = valid[11] & (pri11==3'h1); +assign req_p1[12] = valid[12] & (pri12==3'h1); +assign req_p1[13] = valid[13] & (pri13==3'h1); +assign req_p1[14] = valid[14] & (pri14==3'h1); +assign req_p1[15] = valid[15] & (pri15==3'h1); +assign req_p1[16] = valid[16] & (pri16==3'h1); +assign req_p1[17] = valid[17] & (pri17==3'h1); +assign req_p1[18] = valid[18] & (pri18==3'h1); +assign req_p1[19] = valid[19] & (pri19==3'h1); +assign req_p1[20] = valid[20] & (pri20==3'h1); +assign req_p1[21] = valid[21] & (pri21==3'h1); +assign req_p1[22] = valid[22] & (pri22==3'h1); +assign req_p1[23] = valid[23] & (pri23==3'h1); +assign req_p1[24] = valid[24] & (pri24==3'h1); +assign req_p1[25] = valid[25] & (pri25==3'h1); +assign req_p1[26] = valid[26] & (pri26==3'h1); +assign req_p1[27] = valid[27] & (pri27==3'h1); +assign req_p1[28] = valid[28] & (pri28==3'h1); +assign req_p1[29] = valid[29] & (pri29==3'h1); +assign req_p1[30] = valid[30] & (pri30==3'h1); + +assign req_p2[0] = valid[0] & (pri0==3'h2); +assign req_p2[1] = valid[1] & (pri1==3'h2); +assign req_p2[2] = valid[2] & (pri2==3'h2); +assign req_p2[3] = valid[3] & (pri3==3'h2); +assign req_p2[4] = valid[4] & (pri4==3'h2); +assign req_p2[5] = valid[5] & (pri5==3'h2); +assign req_p2[6] = valid[6] & (pri6==3'h2); +assign req_p2[7] = valid[7] & (pri7==3'h2); +assign req_p2[8] = valid[8] & (pri8==3'h2); +assign req_p2[9] = valid[9] & (pri9==3'h2); +assign req_p2[10] = valid[10] & (pri10==3'h2); +assign req_p2[11] = valid[11] & (pri11==3'h2); +assign req_p2[12] = valid[12] & (pri12==3'h2); +assign req_p2[13] = valid[13] & (pri13==3'h2); +assign req_p2[14] = valid[14] & (pri14==3'h2); +assign req_p2[15] = valid[15] & (pri15==3'h2); +assign req_p2[16] = valid[16] & (pri16==3'h2); +assign req_p2[17] = valid[17] & (pri17==3'h2); +assign req_p2[18] = valid[18] & (pri18==3'h2); +assign req_p2[19] = valid[19] & (pri19==3'h2); +assign req_p2[20] = valid[20] & (pri20==3'h2); +assign req_p2[21] = valid[21] & (pri21==3'h2); +assign req_p2[22] = valid[22] & (pri22==3'h2); +assign req_p2[23] = valid[23] & (pri23==3'h2); +assign req_p2[24] = valid[24] & (pri24==3'h2); +assign req_p2[25] = valid[25] & (pri25==3'h2); +assign req_p2[26] = valid[26] & (pri26==3'h2); +assign req_p2[27] = valid[27] & (pri27==3'h2); +assign req_p2[28] = valid[28] & (pri28==3'h2); +assign req_p2[29] = valid[29] & (pri29==3'h2); +assign req_p2[30] = valid[30] & (pri30==3'h2); + +assign req_p3[0] = valid[0] & (pri0==3'h3); +assign req_p3[1] = valid[1] & (pri1==3'h3); +assign req_p3[2] = valid[2] & (pri2==3'h3); +assign req_p3[3] = valid[3] & (pri3==3'h3); +assign req_p3[4] = valid[4] & (pri4==3'h3); +assign req_p3[5] = valid[5] & (pri5==3'h3); +assign req_p3[6] = valid[6] & (pri6==3'h3); +assign req_p3[7] = valid[7] & (pri7==3'h3); +assign req_p3[8] = valid[8] & (pri8==3'h3); +assign req_p3[9] = valid[9] & (pri9==3'h3); +assign req_p3[10] = valid[10] & (pri10==3'h3); +assign req_p3[11] = valid[11] & (pri11==3'h3); +assign req_p3[12] = valid[12] & (pri12==3'h3); +assign req_p3[13] = valid[13] & (pri13==3'h3); +assign req_p3[14] = valid[14] & (pri14==3'h3); +assign req_p3[15] = valid[15] & (pri15==3'h3); +assign req_p3[16] = valid[16] & (pri16==3'h3); +assign req_p3[17] = valid[17] & (pri17==3'h3); +assign req_p3[18] = valid[18] & (pri18==3'h3); +assign req_p3[19] = valid[19] & (pri19==3'h3); +assign req_p3[20] = valid[20] & (pri20==3'h3); +assign req_p3[21] = valid[21] & (pri21==3'h3); +assign req_p3[22] = valid[22] & (pri22==3'h3); +assign req_p3[23] = valid[23] & (pri23==3'h3); +assign req_p3[24] = valid[24] & (pri24==3'h3); +assign req_p3[25] = valid[25] & (pri25==3'h3); +assign req_p3[26] = valid[26] & (pri26==3'h3); +assign req_p3[27] = valid[27] & (pri27==3'h3); +assign req_p3[28] = valid[28] & (pri28==3'h3); +assign req_p3[29] = valid[29] & (pri29==3'h3); +assign req_p3[30] = valid[30] & (pri30==3'h3); + +assign req_p4[0] = valid[0] & (pri0==3'h4); +assign req_p4[1] = valid[1] & (pri1==3'h4); +assign req_p4[2] = valid[2] & (pri2==3'h4); +assign req_p4[3] = valid[3] & (pri3==3'h4); +assign req_p4[4] = valid[4] & (pri4==3'h4); +assign req_p4[5] = valid[5] & (pri5==3'h4); +assign req_p4[6] = valid[6] & (pri6==3'h4); +assign req_p4[7] = valid[7] & (pri7==3'h4); +assign req_p4[8] = valid[8] & (pri8==3'h4); +assign req_p4[9] = valid[9] & (pri9==3'h4); +assign req_p4[10] = valid[10] & (pri10==3'h4); +assign req_p4[11] = valid[11] & (pri11==3'h4); +assign req_p4[12] = valid[12] & (pri12==3'h4); +assign req_p4[13] = valid[13] & (pri13==3'h4); +assign req_p4[14] = valid[14] & (pri14==3'h4); +assign req_p4[15] = valid[15] & (pri15==3'h4); +assign req_p4[16] = valid[16] & (pri16==3'h4); +assign req_p4[17] = valid[17] & (pri17==3'h4); +assign req_p4[18] = valid[18] & (pri18==3'h4); +assign req_p4[19] = valid[19] & (pri19==3'h4); +assign req_p4[20] = valid[20] & (pri20==3'h4); +assign req_p4[21] = valid[21] & (pri21==3'h4); +assign req_p4[22] = valid[22] & (pri22==3'h4); +assign req_p4[23] = valid[23] & (pri23==3'h4); +assign req_p4[24] = valid[24] & (pri24==3'h4); +assign req_p4[25] = valid[25] & (pri25==3'h4); +assign req_p4[26] = valid[26] & (pri26==3'h4); +assign req_p4[27] = valid[27] & (pri27==3'h4); +assign req_p4[28] = valid[28] & (pri28==3'h4); +assign req_p4[29] = valid[29] & (pri29==3'h4); +assign req_p4[30] = valid[30] & (pri30==3'h4); + +assign req_p5[0] = valid[0] & (pri0==3'h5); +assign req_p5[1] = valid[1] & (pri1==3'h5); +assign req_p5[2] = valid[2] & (pri2==3'h5); +assign req_p5[3] = valid[3] & (pri3==3'h5); +assign req_p5[4] = valid[4] & (pri4==3'h5); +assign req_p5[5] = valid[5] & (pri5==3'h5); +assign req_p5[6] = valid[6] & (pri6==3'h5); +assign req_p5[7] = valid[7] & (pri7==3'h5); +assign req_p5[8] = valid[8] & (pri8==3'h5); +assign req_p5[9] = valid[9] & (pri9==3'h5); +assign req_p5[10] = valid[10] & (pri10==3'h5); +assign req_p5[11] = valid[11] & (pri11==3'h5); +assign req_p5[12] = valid[12] & (pri12==3'h5); +assign req_p5[13] = valid[13] & (pri13==3'h5); +assign req_p5[14] = valid[14] & (pri14==3'h5); +assign req_p5[15] = valid[15] & (pri15==3'h5); +assign req_p5[16] = valid[16] & (pri16==3'h5); +assign req_p5[17] = valid[17] & (pri17==3'h5); +assign req_p5[18] = valid[18] & (pri18==3'h5); +assign req_p5[19] = valid[19] & (pri19==3'h5); +assign req_p5[20] = valid[20] & (pri20==3'h5); +assign req_p5[21] = valid[21] & (pri21==3'h5); +assign req_p5[22] = valid[22] & (pri22==3'h5); +assign req_p5[23] = valid[23] & (pri23==3'h5); +assign req_p5[24] = valid[24] & (pri24==3'h5); +assign req_p5[25] = valid[25] & (pri25==3'h5); +assign req_p5[26] = valid[26] & (pri26==3'h5); +assign req_p5[27] = valid[27] & (pri27==3'h5); +assign req_p5[28] = valid[28] & (pri28==3'h5); +assign req_p5[29] = valid[29] & (pri29==3'h5); +assign req_p5[30] = valid[30] & (pri30==3'h5); + +assign req_p6[0] = valid[0] & (pri0==3'h6); +assign req_p6[1] = valid[1] & (pri1==3'h6); +assign req_p6[2] = valid[2] & (pri2==3'h6); +assign req_p6[3] = valid[3] & (pri3==3'h6); +assign req_p6[4] = valid[4] & (pri4==3'h6); +assign req_p6[5] = valid[5] & (pri5==3'h6); +assign req_p6[6] = valid[6] & (pri6==3'h6); +assign req_p6[7] = valid[7] & (pri7==3'h6); +assign req_p6[8] = valid[8] & (pri8==3'h6); +assign req_p6[9] = valid[9] & (pri9==3'h6); +assign req_p6[10] = valid[10] & (pri10==3'h6); +assign req_p6[11] = valid[11] & (pri11==3'h6); +assign req_p6[12] = valid[12] & (pri12==3'h6); +assign req_p6[13] = valid[13] & (pri13==3'h6); +assign req_p6[14] = valid[14] & (pri14==3'h6); +assign req_p6[15] = valid[15] & (pri15==3'h6); +assign req_p6[16] = valid[16] & (pri16==3'h6); +assign req_p6[17] = valid[17] & (pri17==3'h6); +assign req_p6[18] = valid[18] & (pri18==3'h6); +assign req_p6[19] = valid[19] & (pri19==3'h6); +assign req_p6[20] = valid[20] & (pri20==3'h6); +assign req_p6[21] = valid[21] & (pri21==3'h6); +assign req_p6[22] = valid[22] & (pri22==3'h6); +assign req_p6[23] = valid[23] & (pri23==3'h6); +assign req_p6[24] = valid[24] & (pri24==3'h6); +assign req_p6[25] = valid[25] & (pri25==3'h6); +assign req_p6[26] = valid[26] & (pri26==3'h6); +assign req_p6[27] = valid[27] & (pri27==3'h6); +assign req_p6[28] = valid[28] & (pri28==3'h6); +assign req_p6[29] = valid[29] & (pri29==3'h6); +assign req_p6[30] = valid[30] & (pri30==3'h6); + +assign req_p7[0] = valid[0] & (pri0==3'h7); +assign req_p7[1] = valid[1] & (pri1==3'h7); +assign req_p7[2] = valid[2] & (pri2==3'h7); +assign req_p7[3] = valid[3] & (pri3==3'h7); +assign req_p7[4] = valid[4] & (pri4==3'h7); +assign req_p7[5] = valid[5] & (pri5==3'h7); +assign req_p7[6] = valid[6] & (pri6==3'h7); +assign req_p7[7] = valid[7] & (pri7==3'h7); +assign req_p7[8] = valid[8] & (pri8==3'h7); +assign req_p7[9] = valid[9] & (pri9==3'h7); +assign req_p7[10] = valid[10] & (pri10==3'h7); +assign req_p7[11] = valid[11] & (pri11==3'h7); +assign req_p7[12] = valid[12] & (pri12==3'h7); +assign req_p7[13] = valid[13] & (pri13==3'h7); +assign req_p7[14] = valid[14] & (pri14==3'h7); +assign req_p7[15] = valid[15] & (pri15==3'h7); +assign req_p7[16] = valid[16] & (pri16==3'h7); +assign req_p7[17] = valid[17] & (pri17==3'h7); +assign req_p7[18] = valid[18] & (pri18==3'h7); +assign req_p7[19] = valid[19] & (pri19==3'h7); +assign req_p7[20] = valid[20] & (pri20==3'h7); +assign req_p7[21] = valid[21] & (pri21==3'h7); +assign req_p7[22] = valid[22] & (pri22==3'h7); +assign req_p7[23] = valid[23] & (pri23==3'h7); +assign req_p7[24] = valid[24] & (pri24==3'h7); +assign req_p7[25] = valid[25] & (pri25==3'h7); +assign req_p7[26] = valid[26] & (pri26==3'h7); +assign req_p7[27] = valid[27] & (pri27==3'h7); +assign req_p7[28] = valid[28] & (pri28==3'h7); +assign req_p7[29] = valid[29] & (pri29==3'h7); +assign req_p7[30] = valid[30] & (pri30==3'h7); + +// RR Arbiter for priority 0 +wb_dma_ch_arb u1( + .clk( clk ), + .rst( rst ), + .req( req_p0 ), + .gnt( gnt_p0_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 1 +wb_dma_ch_arb u2( + .clk( clk ), + .rst( rst ), + .req( req_p1 ), + .gnt( gnt_p1_d ), + .advance( next_ch ) + ); + +// RR Arbiter for priority 2 +wb_dma_ch_arb u3( + .clk( clk ), + .rst( rst ), + .req( req_p2 ), + .gnt( gnt_p2_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 3 +wb_dma_ch_arb u4( + .clk( clk ), + .rst( rst ), + .req( req_p3 ), + .gnt( gnt_p3_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 4 +wb_dma_ch_arb u5( + .clk( clk ), + .rst( rst ), + .req( req_p4 ), + .gnt( gnt_p4_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 5 +wb_dma_ch_arb u6( + .clk( clk ), + .rst( rst ), + .req( req_p5 ), + .gnt( gnt_p5_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 6 +wb_dma_ch_arb u7( + .clk( clk ), + .rst( rst ), + .req( req_p6 ), + .gnt( gnt_p6_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 7 +wb_dma_ch_arb u8( + .clk( clk ), + .rst( rst ), + .req( req_p7 ), + .gnt( gnt_p7_d ), + .advance( next_ch ) + ); + +// Select grant based on number of priorities +assign gnt_p0 = gnt_p0_d; +assign gnt_p1 = gnt_p1_d; +assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d; +assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d; +assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0; +assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0; +assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0; +assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_de.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_de.v new file mode 100644 index 000000000..264972353 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_de.v @@ -0,0 +1,632 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA DMA Engine Core //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_de.v,v 1.3 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_de.v,v $ +// Revision 1.3 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:44 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_de(clk, rst, + + // WISHBONE MASTER INTERFACE 0 + mast0_go, mast0_we, mast0_adr, mast0_din, + mast0_dout, mast0_err, mast0_drdy, mast0_wait, + + // WISHBONE MASTER INTERFACE 1 + mast1_go, mast1_we, mast1_adr, mast1_din, + mast1_dout, mast1_err, mast1_drdy, mast1_wait, + + // DMA Engine Init & Setup + de_start, nd, csr, pointer, pointer_s, txsz, + adr0, adr1, am0, am1, + + // DMA Engine Register File Update Outputs + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set, + de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr, + + // DMA Engine Control Outputs + next_ch, de_ack, + + // DMA Engine Status + pause_req, paused, + dma_abort, dma_busy, dma_err, dma_done, dma_done_all + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE MASTER INTERFACE 0 + +output mast0_go; // Perform a Master Cycle +output mast0_we; // Read/Write +output [31:0] mast0_adr; // Address for the transfer +input [31:0] mast0_din; // Internal Input Data +output [31:0] mast0_dout; // Internal Output Data +input mast0_err; // Indicates an error has occurred +input mast0_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +output mast0_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// -------------------------------------- +// WISHBONE MASTER INTERFACE 1 + +output mast1_go; // Perform a Master Cycle +output mast1_we; // Read/Write +output [31:0] mast1_adr; // Address for the transfer +input [31:0] mast1_din; // Internal Input Data +output [31:0] mast1_dout; // Internal Output Data +input mast1_err; // Indicates an error has occurred +input mast1_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +output mast1_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// -------------------------------------- +// DMA Engine Signals + +// DMA Engine Init & Setup +input de_start; // Start DMA Engine Indicator +input nd; // Next Descriptor Indicator +input [31:0] csr; // Selected Channel CSR +input [31:0] pointer; // Linked List Descriptor pointer +input [31:0] pointer_s; // Previous Pointer +input [31:0] txsz; // Selected Channel Transfer Size +input [31:0] adr0, adr1; // Selected Channel Addresses +input [31:0] am0, am1; // Selected Channel Address Masks + +// DMA Engine Register File Update Outputs +output de_csr_we; // Write enable for csr register +output de_txsz_we; // Write enable for txsz register +output de_adr0_we; // Write enable for adr0 register +output de_adr1_we; // Write enable for adr1 register +output ptr_set; // Set Pointer as Valid +output [31:0] de_csr; // Write Data for CSR when loading External Desc. +output [11:0] de_txsz; // Write back data for txsz register +output [31:0] de_adr0; // Write back data for adr0 register +output [31:0] de_adr1; // Write back data for adr1 register +output de_fetch_descr; // Indicates that we are fetching a descriptor + +// DMA Engine Control Outputs +output next_ch; // Indicates the DMA Engine is done +output de_ack; + +// DMA Abort from RF (software forced abort) +input dma_abort; + +// DMA Engine Status +input pause_req; +output paused; +output dma_busy, dma_err, dma_done, dma_done_all; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter [10:0] // synopsys enum state + IDLE = 11'b000_0000_0001, + READ = 11'b000_0000_0010, + WRITE = 11'b000_0000_0100, + UPDATE = 11'b000_0000_1000, + LD_DESC1 = 11'b000_0001_0000, + LD_DESC2 = 11'b000_0010_0000, + LD_DESC3 = 11'b000_0100_0000, + LD_DESC4 = 11'b000_1000_0000, + LD_DESC5 = 11'b001_0000_0000, + WB = 11'b010_0000_0000, + PAUSE = 11'b100_0000_0000; + +reg [10:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg [31:0] mast0_adr, mast1_adr; + +reg [29:0] adr0_cnt, adr1_cnt; +wire [29:0] adr0_cnt_next, adr1_cnt_next; +wire [29:0] adr0_cnt_next1, adr1_cnt_next1; +reg adr0_inc, adr1_inc; + +reg [8:0] chunk_cnt; +reg chunk_dec; + +reg [11:0] tsz_cnt; +reg tsz_dec; + +reg de_txsz_we; +reg de_csr_we; +reg de_adr0_we; +reg de_adr1_we; +reg ld_desc_sel; + +wire chunk_cnt_is_0_d; +reg chunk_cnt_is_0_r; +wire tsz_cnt_is_0_d; +reg tsz_cnt_is_0_r; + +reg read, write; +reg read_r, write_r; +wire rd_ack, wr_ack; +reg rd_ack_r; + +reg chunk_0; +wire done; +reg dma_done_d; +reg dma_done_r; +reg dma_abort_r; +reg next_ch; +wire read_hold, write_hold; +reg write_hold_r; + +reg [1:0] ptr_adr_low; +reg m0_go; +reg m0_we; +reg ptr_set; + +// Aliases +wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable +wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable +wire ptr_valid = pointer[0]; +wire use_ed = csr[`WDMA_USE_ED]; + +reg mast0_drdy_r; +reg paused; + +reg de_fetch_descr; // Indicates that we are fetching a descriptor +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + dma_done_r <= #1 dma_done; + +// Address Counter 0 (Source Address) +always @(posedge clk) + if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2]; + else + if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next; + +// 30 Bit Incrementor (registered) +wb_dma_inc30r u0( .clk( clk ), + .in( adr0_cnt ), + .out( adr0_cnt_next1 ) ); + +assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0]; +assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2]; +assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3]; +assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4]; +assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5]; +assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6]; +assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7]; +assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8]; +assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9]; +assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10]; +assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11]; +assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12]; +assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13]; +assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14]; +assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15]; +assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16]; +assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17]; +assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18]; +assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19]; +assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20]; +assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21]; +assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22]; +assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23]; +assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24]; +assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25]; +assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26]; +assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27]; +assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28]; +assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29]; + + +// Address Counter 1 (Destination Address) +always @(posedge clk) + if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2]; + else + if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next; + +// 30 Bit Incrementor (registered) +wb_dma_inc30r u1( .clk( clk ), + .in( adr1_cnt ), + .out( adr1_cnt_next1 ) ); + +assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0]; +assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2]; +assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3]; +assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4]; +assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5]; +assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6]; +assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7]; +assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8]; +assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9]; +assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10]; +assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11]; +assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12]; +assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13]; +assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14]; +assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15]; +assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16]; +assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17]; +assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18]; +assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19]; +assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20]; +assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21]; +assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22]; +assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23]; +assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24]; +assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25]; +assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26]; +assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27]; +assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28]; +assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29]; + +// Chunk Counter +always @(posedge clk) + if(de_start) chunk_cnt <= #1 txsz[24:16]; + else + if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1; + +assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0); + +always @(posedge clk) + chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d; + +// Total Size Counter +always @(posedge clk) + if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0]; + else + if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1; + +assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15]; + +always @(posedge clk) + tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d; + +// Counter Control Logic +always @(posedge clk) + chunk_dec <= #1 read & !read_r; + +always @(posedge clk) + tsz_dec <= #1 read & !read_r; + +//always @(posedge clk) +always @(rd_ack or read_r) + adr0_inc = rd_ack & read_r; + +//always @(posedge clk) +always @(wr_ack or write_r) + adr1_inc = wr_ack & write_r; + +// Done logic +always @(posedge clk) + chunk_0 <= #1 (txsz[24:16] == 9'h0); + +assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d); +assign dma_done = dma_done_d & done; +assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d)); + +always @(posedge clk) + next_ch <= #1 dma_done; + +// Register Update Outputs +assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt; +assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00}; +assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00}; +assign de_csr = mast0_din; + +// Abort logic +always @(posedge clk) + dma_abort_r <= #1 dma_abort | mast0_err | mast1_err; + +assign dma_err = dma_abort_r; + +assign dma_busy = (state != IDLE); + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Interface Logic +// + +always @(posedge clk) + read_r <= #1 read; + +always @(posedge clk) + write_r <= #1 write; + +always @(posedge clk) + rd_ack_r <= #1 read_r; + +// Data Path +assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din; +assign mast1_dout = csr[2] ? mast1_din : mast0_din; + +// Address Path +always @(posedge clk) + mast0_adr <= #1 m0_go ? + (m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) : + read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; + +always @(posedge clk) + mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; + +// CTRL +assign write_hold = (read | write) & write_hold_r; + +always @(posedge clk) + write_hold_r <= #1 read | write; + +assign read_hold = done ? read : (read | write); + +assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go; +assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold); + +assign mast0_we = m0_go ? m0_we : (!csr[1] & write); +assign mast1_we = csr[1] & write; + +assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy); +assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy); + +assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go; +assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write)); + +always @(posedge clk) + mast0_drdy_r <= #1 mast0_drdy; + +assign de_ack = dma_done; + +//////////////////////////////////////////////////////////////////// +// +// State Machine +// + +always @(posedge clk or negedge rst) + if(!rst) state <= #1 IDLE; + else state <= #1 next_state; + +always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or + done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd) + begin + next_state = state; // Default keep state + read = 1'b0; + write = 1'b0; + dma_done_d = 1'b0; + de_csr_we = 1'b0; + de_txsz_we = 1'b0; + de_adr0_we = 1'b0; + de_adr1_we = 1'b0; + de_fetch_descr = 1'b0; + + m0_go = 1'b0; + m0_we = 1'b0; + ptr_adr_low = 2'h0; + ptr_set = 1'b0; + ld_desc_sel = 1'b0; + paused = 1'b0; + + case(state) // synopsys parallel_case full_case + + IDLE: + begin + if(pause_req) next_state = PAUSE; + else + if(de_start & !csr[`WDMA_ERR]) + begin + if(use_ed & !ptr_valid) next_state = LD_DESC1; + else next_state = READ; + end + end + + PAUSE: + begin + paused = 1'b1; + if(!pause_req) next_state = IDLE; + end + + READ: // Read From Source + begin + if(dma_abort_r) next_state = UPDATE; + else + if(!rd_ack) read = 1'b1; + else + begin + write = 1'b1; + next_state = WRITE; + end + end + + WRITE: // Write To Destination + begin + if(dma_abort_r) next_state = UPDATE; + else + if(!wr_ack) write = 1'b1; + else + begin + if(done) next_state = UPDATE; + else + begin + read = 1'b1; + next_state = READ; + end + end + end + + UPDATE: // Update Registers + begin + dma_done_d = 1'b1; + de_txsz_we = 1'b1; + de_adr0_we = 1'b1; + de_adr1_we = 1'b1; + if(use_ed & csr[`WDMA_WRB] & nd) + begin + m0_we = 1'b1; + m0_go = 1'b1; + next_state = WB; + end + else next_state = IDLE; + end + + WB: + begin + m0_we = 1'b1; + if(mast0_drdy) + begin + next_state = IDLE; + end + else m0_go = 1'b1; + end + + LD_DESC1: // Load Descriptor from memory to registers + begin + ptr_adr_low = 2'h0; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + de_csr_we = 1'b1; + de_txsz_we = 1'b1; + de_fetch_descr = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h1; + next_state = LD_DESC2; + end + end + + LD_DESC2: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_csr_we = 1'b1; + if(mast0_drdy_r) de_txsz_we = 1'b1; + ptr_adr_low = 2'h1; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h2; + next_state = LD_DESC3; + end + end + + LD_DESC3: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_adr0_we = 1'b1; + ptr_adr_low = 2'h2; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h3; + next_state = LD_DESC4; + end + end + + LD_DESC4: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_adr1_we = 1'b1; + ptr_adr_low = 2'h3; + ld_desc_sel = 1'b1; + if(mast0_drdy) + begin + next_state = LD_DESC5; + end + else m0_go = 1'b1; + end + + LD_DESC5: + begin + de_fetch_descr = 1'b1; + ptr_set = 1'b1; + next_state = READ; + end + + endcase + + end + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_defines.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_defines.v new file mode 100644 index 000000000..68331c6e2 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_defines.v @@ -0,0 +1,120 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_defines.v,v 1.5 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_defines.v,v $ +// Revision 1.5 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/09/07 15:34:38 rudi +// +// Changed reset to active high. +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:09 rudi +// Initial Release +// +// +// + +`timescale 1ns / 10ps + +// This define selects how the slave interface determines if +// the internal register file or pass through mode are selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +// NOTE: The entire pass-through mode is implemented in combinatorial +// logic only. So the more address lines we look at and compare here +// the higher will be the initial delay when pass-through mode is selected. +// Here we look at the top 8 address bit. If they are all 1, the +// register file is selected. Use this with caution !!! +`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr) + + +// DO NOT MODIFY BEYOND THIS POINT +// CSR Bits +`define WDMA_CH_EN 0 +`define WDMA_DST_SEL 1 +`define WDMA_SRC_SEL 2 +`define WDMA_INC_DST 3 +`define WDMA_INC_SRC 4 +`define WDMA_MODE 5 +`define WDMA_ARS 6 +`define WDMA_USE_ED 7 +`define WDMA_WRB 8 +`define WDMA_STOP 9 +`define WDMA_BUSY 10 +`define WDMA_DONE 11 +`define WDMA_ERR 12 +`define WDMA_ED_EOL 20 + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_inc30r.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_inc30r.v new file mode 100644 index 000000000..73c4cb4b7 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_inc30r.v @@ -0,0 +1,96 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Primitives //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_inc30r.v,v 1.2 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_inc30r.v,v $ +// Revision 1.2 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:12 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_inc30r(clk, in, out); +input clk; +input [29:0] in; +output [29:0] out; + +// INC30_CENTER indicates the center bit of the 30 bit incrementor +// so it can be easily manually optimized for best performance +parameter INC30_CENTER = 16; + +reg [INC30_CENTER:0] out_r; + +always @(posedge clk) + out_r <= #1 in[(INC30_CENTER - 1):0] + 1; + +assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER]; +assign out[(INC30_CENTER - 1):0] = out_r; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_pri_enc_sub.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_pri_enc_sub.v new file mode 100644 index 000000000..4e42ec2b5 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_pri_enc_sub.v @@ -0,0 +1,146 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Priority Encoder Sub-Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_pri_enc_sub.v,v $ +// Revision 1.4 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/08/07 08:00:43 rudi +// +// +// Split up priority encoder modules to separate files +// +// +// +// +// +// + +`include "wb_dma_defines.v" + +// Priority Encoder +// +// Determines the channel with the highest priority, also takes +// the valid bit in consideration + +module wb_dma_pri_enc_sub(valid, pri_in, pri_out); + +parameter [3:0] ch_conf = 4'b0000; +parameter [1:0] pri_sel = 2'd0; + +input valid; +input [2:0] pri_in; +output [7:0] pri_out; + +wire [7:0] pri_out; +reg [7:0] pri_out_d; +reg [7:0] pri_out_d0; +reg [7:0] pri_out_d1; +reg [7:0] pri_out_d2; + +assign pri_out = ch_conf[0] ? pri_out_d : 8'h0; + +// Select Configured Priority +always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2) + case(pri_sel) // synopsys parallel_case full_case + 2'd0: pri_out_d = pri_out_d0; + 2'd1: pri_out_d = pri_out_d1; + 2'd2: pri_out_d = pri_out_d2; + endcase + +// 8 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d2 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001; + else + if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010; + else + if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100; + else + if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000; + else + if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000; + else + if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000; + else + if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000; + else pri_out_d2 = 8'b1000_0000; + +// 4 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d1 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001; + else + if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010; + else + if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100; + else pri_out_d1 = 8'b0000_1000; + +// 2 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d0 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001; + else pri_out_d0 = 8'b0000_0010; + +endmodule + diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_rf.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_rf.v new file mode 100644 index 000000000..cbc714c0a --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_rf.v @@ -0,0 +1,1860 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_rf.v,v 1.4 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_rf.v,v $ +// Revision 1.4 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:50:46 rudi +// +// Changed name of channel register file module. +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:11 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_rf(clk, rst, + + // WISHBONE Access + wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we, + + // WISHBONE Interrupt outputs + inta_o, intb_o, + + // DMA Registers Outputs + pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, + pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, + pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, + pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, + pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, + pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, + pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, + pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, + pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, + pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, + pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, + pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, + pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, + pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, + pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, + pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, + pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, + pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, + pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, + pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, + pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, + pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, + pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, + pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, + pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, + pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, + pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, + pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, + pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, + pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, + pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest, + ptr_set + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk, rst; + +// WISHBONE Access +input [7:0] wb_rf_adr; +input [31:0] wb_rf_din; +output [31:0] wb_rf_dout; +input wb_rf_re; +input wb_rf_we; + +// WISHBONE Interrupt outputs +output inta_o, intb_o; + +// Channel Registers Inputs +output [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +output [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +output [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +output [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +output [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +output [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +output [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +output [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +output [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +output [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +output [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +output [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +output [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +output [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +output [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +output [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +output [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +output [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +output [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +output [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +output [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +output [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +output [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +output [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +output [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +output [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +output [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +output [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +output [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +output [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +output [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +input [4:0] ch_sel; // Write Back Channel Select +input [30:0] ndnr; // Next Descriptor No Request + +// DMA Engine Abort +output dma_abort; + +// DMA Engine Status +output pause_req; +input paused; +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input [30:0] dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [31:0] wb_rf_dout; +reg inta_o, intb_o; +reg [30:0] int_maska_r, int_maskb_r; +wire [31:0] int_maska, int_maskb; +wire [31:0] int_srca, int_srcb; +wire int_maska_we, int_maskb_we; +wire [30:0] ch_int; +wire csr_we; +wire [31:0] csr; +reg [7:0] csr_r; + +wire [30:0] ch_stop; +wire [30:0] ch_dis; + +wire [31:0] ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +wire [31:0] ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +wire [31:0] ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +wire [31:0] ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +wire [31:0] ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +wire [31:0] ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +wire [31:0] ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +wire [31:0] ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +wire [31:0] ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +wire [31:0] ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +wire [31:0] ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +wire [31:0] ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +wire [31:0] ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +wire [31:0] ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +wire [31:0] ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +wire [31:0] ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +wire [31:0] ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +wire [31:0] ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +wire [31:0] ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +wire [31:0] ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +wire [31:0] ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +wire [31:0] ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +wire [31:0] ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +wire [31:0] ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +wire [31:0] ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +wire [31:0] ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +wire [31:0] ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +wire [31:0] ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +wire [31:0] ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +wire [31:0] ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +wire [31:0] ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +wire [31:0] sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3; +wire [31:0] sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7; +wire [31:0] sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11; +wire [31:0] sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15; +wire [31:0] sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19; +wire [31:0] sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23; +wire [31:0] sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27; +wire [31:0] sw_pointer28, sw_pointer29, sw_pointer30; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign int_maska = {1'h0, int_maska_r}; +assign int_maskb = {1'h0, int_maskb_r}; +assign csr = {31'h0, paused}; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign dma_abort = |ch_stop; +assign pause_req = csr_r[0]; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Read Logic +// + +always @(posedge clk) + case(wb_rf_adr) // synopsys parallel_case full_case + 8'h0: wb_rf_dout <= #1 csr; + 8'h1: wb_rf_dout <= #1 int_maska; + 8'h2: wb_rf_dout <= #1 int_maskb; + 8'h3: wb_rf_dout <= #1 int_srca; + 8'h4: wb_rf_dout <= #1 int_srcb; + + 8'h8: wb_rf_dout <= #1 ch0_csr; + 8'h9: wb_rf_dout <= #1 ch0_txsz; + 8'ha: wb_rf_dout <= #1 ch0_adr0; + 8'hb: wb_rf_dout <= #1 ch0_am0; + 8'hc: wb_rf_dout <= #1 ch0_adr1; + 8'hd: wb_rf_dout <= #1 ch0_am1; + 8'he: wb_rf_dout <= #1 pointer0; + 8'hf: wb_rf_dout <= #1 sw_pointer0; + + 8'h10: wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr : 32'h0; + 8'h11: wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz : 32'h0; + 8'h12: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0 : 32'h0; + 8'h13: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0 : 32'h0; + 8'h14: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1 : 32'h0; + 8'h15: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1 : 32'h0; + 8'h16: wb_rf_dout <= #1 ch1_conf[0] ? pointer1 : 32'h0; + 8'h17: wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1 : 32'h0; + + 8'h18: wb_rf_dout <= #1 ch2_conf[0] ? ch2_csr : 32'h0; + 8'h19: wb_rf_dout <= #1 ch2_conf[0] ? ch2_txsz : 32'h0; + 8'h1a: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr0 : 32'h0; + 8'h1b: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am0 : 32'h0; + 8'h1c: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr1 : 32'h0; + 8'h1d: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am1 : 32'h0; + 8'h1e: wb_rf_dout <= #1 ch2_conf[0] ? pointer2 : 32'h0; + 8'h1f: wb_rf_dout <= #1 ch2_conf[0] ? sw_pointer2 : 32'h0; + + 8'h20: wb_rf_dout <= #1 ch3_conf[0] ? ch3_csr : 32'h0; + 8'h21: wb_rf_dout <= #1 ch3_conf[0] ? ch3_txsz : 32'h0; + 8'h22: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr0 : 32'h0; + 8'h23: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am0 : 32'h0; + 8'h24: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr1 : 32'h0; + 8'h25: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am1 : 32'h0; + 8'h26: wb_rf_dout <= #1 ch3_conf[0] ? pointer3 : 32'h0; + 8'h27: wb_rf_dout <= #1 ch3_conf[0] ? sw_pointer3 : 32'h0; + + 8'h28: wb_rf_dout <= #1 ch4_conf[0] ? ch4_csr : 32'h0; + 8'h29: wb_rf_dout <= #1 ch4_conf[0] ? ch4_txsz : 32'h0; + 8'h2a: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr0 : 32'h0; + 8'h2b: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am0 : 32'h0; + 8'h2c: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr1 : 32'h0; + 8'h2d: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am1 : 32'h0; + 8'h2e: wb_rf_dout <= #1 ch4_conf[0] ? pointer4 : 32'h0; + 8'h2f: wb_rf_dout <= #1 ch4_conf[0] ? sw_pointer4 : 32'h0; + + 8'h30: wb_rf_dout <= #1 ch5_conf[0] ? ch5_csr : 32'h0; + 8'h31: wb_rf_dout <= #1 ch5_conf[0] ? ch5_txsz : 32'h0; + 8'h32: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr0 : 32'h0; + 8'h33: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am0 : 32'h0; + 8'h34: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr1 : 32'h0; + 8'h35: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am1 : 32'h0; + 8'h36: wb_rf_dout <= #1 ch5_conf[0] ? pointer5 : 32'h0; + 8'h37: wb_rf_dout <= #1 ch5_conf[0] ? sw_pointer5 : 32'h0; + + 8'h38: wb_rf_dout <= #1 ch6_conf[0] ? ch6_csr : 32'h0; + 8'h39: wb_rf_dout <= #1 ch6_conf[0] ? ch6_txsz : 32'h0; + 8'h3a: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr0 : 32'h0; + 8'h3b: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am0 : 32'h0; + 8'h3c: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr1 : 32'h0; + 8'h3d: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am1 : 32'h0; + 8'h3e: wb_rf_dout <= #1 ch6_conf[0] ? pointer6 : 32'h0; + 8'h3f: wb_rf_dout <= #1 ch6_conf[0] ? sw_pointer6 : 32'h0; + + 8'h40: wb_rf_dout <= #1 ch7_conf[0] ? ch7_csr : 32'h0; + 8'h41: wb_rf_dout <= #1 ch7_conf[0] ? ch7_txsz : 32'h0; + 8'h42: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr0 : 32'h0; + 8'h43: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am0 : 32'h0; + 8'h44: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr1 : 32'h0; + 8'h45: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am1 : 32'h0; + 8'h46: wb_rf_dout <= #1 ch7_conf[0] ? pointer7 : 32'h0; + 8'h47: wb_rf_dout <= #1 ch7_conf[0] ? sw_pointer7 : 32'h0; + + 8'h48: wb_rf_dout <= #1 ch8_conf[0] ? ch8_csr : 32'h0; + 8'h49: wb_rf_dout <= #1 ch8_conf[0] ? ch8_txsz : 32'h0; + 8'h4a: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr0 : 32'h0; + 8'h4b: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am0 : 32'h0; + 8'h4c: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr1 : 32'h0; + 8'h4d: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am1 : 32'h0; + 8'h4e: wb_rf_dout <= #1 ch8_conf[0] ? pointer8 : 32'h0; + 8'h4f: wb_rf_dout <= #1 ch8_conf[0] ? sw_pointer8 : 32'h0; + + 8'h50: wb_rf_dout <= #1 ch9_conf[0] ? ch9_csr : 32'h0; + 8'h51: wb_rf_dout <= #1 ch9_conf[0] ? ch9_txsz : 32'h0; + 8'h52: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr0 : 32'h0; + 8'h53: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am0 : 32'h0; + 8'h54: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr1 : 32'h0; + 8'h55: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am1 : 32'h0; + 8'h56: wb_rf_dout <= #1 ch9_conf[0] ? pointer9 : 32'h0; + 8'h57: wb_rf_dout <= #1 ch9_conf[0] ? sw_pointer9 : 32'h0; + + 8'h58: wb_rf_dout <= #1 ch10_conf[0] ? ch10_csr : 32'h0; + 8'h59: wb_rf_dout <= #1 ch10_conf[0] ? ch10_txsz : 32'h0; + 8'h5a: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr0 : 32'h0; + 8'h5b: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am0 : 32'h0; + 8'h5c: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr1 : 32'h0; + 8'h5d: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am1 : 32'h0; + 8'h5e: wb_rf_dout <= #1 ch10_conf[0] ? pointer10 : 32'h0; + 8'h5f: wb_rf_dout <= #1 ch10_conf[0] ? sw_pointer10 : 32'h0; + + 8'h60: wb_rf_dout <= #1 ch11_conf[0] ? ch11_csr : 32'h0; + 8'h61: wb_rf_dout <= #1 ch11_conf[0] ? ch11_txsz : 32'h0; + 8'h62: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr0 : 32'h0; + 8'h63: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am0 : 32'h0; + 8'h64: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr1 : 32'h0; + 8'h65: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am1 : 32'h0; + 8'h66: wb_rf_dout <= #1 ch11_conf[0] ? pointer11 : 32'h0; + 8'h67: wb_rf_dout <= #1 ch11_conf[0] ? sw_pointer11 : 32'h0; + + 8'h68: wb_rf_dout <= #1 ch12_conf[0] ? ch12_csr : 32'h0; + 8'h69: wb_rf_dout <= #1 ch12_conf[0] ? ch12_txsz : 32'h0; + 8'h6a: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr0 : 32'h0; + 8'h6b: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am0 : 32'h0; + 8'h6c: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr1 : 32'h0; + 8'h6d: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am1 : 32'h0; + 8'h6e: wb_rf_dout <= #1 ch12_conf[0] ? pointer12 : 32'h0; + 8'h6f: wb_rf_dout <= #1 ch12_conf[0] ? sw_pointer12 : 32'h0; + + 8'h70: wb_rf_dout <= #1 ch13_conf[0] ? ch13_csr : 32'h0; + 8'h71: wb_rf_dout <= #1 ch13_conf[0] ? ch13_txsz : 32'h0; + 8'h72: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr0 : 32'h0; + 8'h73: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am0 : 32'h0; + 8'h74: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr1 : 32'h0; + 8'h75: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am1 : 32'h0; + 8'h76: wb_rf_dout <= #1 ch13_conf[0] ? pointer13 : 32'h0; + 8'h77: wb_rf_dout <= #1 ch13_conf[0] ? sw_pointer13 : 32'h0; + + 8'h78: wb_rf_dout <= #1 ch14_conf[0] ? ch14_csr : 32'h0; + 8'h79: wb_rf_dout <= #1 ch14_conf[0] ? ch14_txsz : 32'h0; + 8'h7a: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr0 : 32'h0; + 8'h7b: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am0 : 32'h0; + 8'h7c: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr1 : 32'h0; + 8'h7d: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am1 : 32'h0; + 8'h7e: wb_rf_dout <= #1 ch14_conf[0] ? pointer14 : 32'h0; + 8'h7f: wb_rf_dout <= #1 ch14_conf[0] ? sw_pointer14 : 32'h0; + + 8'h80: wb_rf_dout <= #1 ch15_conf[0] ? ch15_csr : 32'h0; + 8'h81: wb_rf_dout <= #1 ch15_conf[0] ? ch15_txsz : 32'h0; + 8'h82: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr0 : 32'h0; + 8'h83: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am0 : 32'h0; + 8'h84: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr1 : 32'h0; + 8'h85: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am1 : 32'h0; + 8'h86: wb_rf_dout <= #1 ch15_conf[0] ? pointer15 : 32'h0; + 8'h87: wb_rf_dout <= #1 ch15_conf[0] ? sw_pointer15 : 32'h0; + + 8'h88: wb_rf_dout <= #1 ch16_conf[0] ? ch16_csr : 32'h0; + 8'h89: wb_rf_dout <= #1 ch16_conf[0] ? ch16_txsz : 32'h0; + 8'h8a: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr0 : 32'h0; + 8'h8b: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am0 : 32'h0; + 8'h8c: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr1 : 32'h0; + 8'h8d: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am1 : 32'h0; + 8'h8e: wb_rf_dout <= #1 ch16_conf[0] ? pointer16 : 32'h0; + 8'h8f: wb_rf_dout <= #1 ch16_conf[0] ? sw_pointer16 : 32'h0; + + 8'h90: wb_rf_dout <= #1 ch17_conf[0] ? ch17_csr : 32'h0; + 8'h91: wb_rf_dout <= #1 ch17_conf[0] ? ch17_txsz : 32'h0; + 8'h92: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr0 : 32'h0; + 8'h93: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am0 : 32'h0; + 8'h94: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr1 : 32'h0; + 8'h95: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am1 : 32'h0; + 8'h96: wb_rf_dout <= #1 ch17_conf[0] ? pointer17 : 32'h0; + 8'h97: wb_rf_dout <= #1 ch17_conf[0] ? sw_pointer17 : 32'h0; + + 8'h98: wb_rf_dout <= #1 ch18_conf[0] ? ch18_csr : 32'h0; + 8'h99: wb_rf_dout <= #1 ch18_conf[0] ? ch18_txsz : 32'h0; + 8'h9a: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr0 : 32'h0; + 8'h9b: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am0 : 32'h0; + 8'h9c: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr1 : 32'h0; + 8'h9d: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am1 : 32'h0; + 8'h9e: wb_rf_dout <= #1 ch18_conf[0] ? pointer18 : 32'h0; + 8'h9f: wb_rf_dout <= #1 ch18_conf[0] ? sw_pointer18 : 32'h0; + + 8'ha0: wb_rf_dout <= #1 ch19_conf[0] ? ch19_csr : 32'h0; + 8'ha1: wb_rf_dout <= #1 ch19_conf[0] ? ch19_txsz : 32'h0; + 8'ha2: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr0 : 32'h0; + 8'ha3: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am0 : 32'h0; + 8'ha4: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr1 : 32'h0; + 8'ha5: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am1 : 32'h0; + 8'ha6: wb_rf_dout <= #1 ch19_conf[0] ? pointer19 : 32'h0; + 8'ha7: wb_rf_dout <= #1 ch19_conf[0] ? sw_pointer19 : 32'h0; + + 8'ha8: wb_rf_dout <= #1 ch20_conf[0] ? ch20_csr : 32'h0; + 8'ha9: wb_rf_dout <= #1 ch20_conf[0] ? ch20_txsz : 32'h0; + 8'haa: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr0 : 32'h0; + 8'hab: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am0 : 32'h0; + 8'hac: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr1 : 32'h0; + 8'had: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am1 : 32'h0; + 8'hae: wb_rf_dout <= #1 ch20_conf[0] ? pointer20 : 32'h0; + 8'haf: wb_rf_dout <= #1 ch20_conf[0] ? sw_pointer20 : 32'h0; + + 8'hb0: wb_rf_dout <= #1 ch21_conf[0] ? ch21_csr : 32'h0; + 8'hb1: wb_rf_dout <= #1 ch21_conf[0] ? ch21_txsz : 32'h0; + 8'hb2: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr0 : 32'h0; + 8'hb3: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am0 : 32'h0; + 8'hb4: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr1 : 32'h0; + 8'hb5: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am1 : 32'h0; + 8'hb6: wb_rf_dout <= #1 ch21_conf[0] ? pointer21 : 32'h0; + 8'hb7: wb_rf_dout <= #1 ch21_conf[0] ? sw_pointer21 : 32'h0; + + 8'hb8: wb_rf_dout <= #1 ch22_conf[0] ? ch22_csr : 32'h0; + 8'hb9: wb_rf_dout <= #1 ch22_conf[0] ? ch22_txsz : 32'h0; + 8'hba: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr0 : 32'h0; + 8'hbb: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am0 : 32'h0; + 8'hbc: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr1 : 32'h0; + 8'hbd: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am1 : 32'h0; + 8'hbe: wb_rf_dout <= #1 ch22_conf[0] ? pointer22 : 32'h0; + 8'hbf: wb_rf_dout <= #1 ch22_conf[0] ? sw_pointer22 : 32'h0; + + 8'hc0: wb_rf_dout <= #1 ch23_conf[0] ? ch23_csr : 32'h0; + 8'hc1: wb_rf_dout <= #1 ch23_conf[0] ? ch23_txsz : 32'h0; + 8'hc2: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr0 : 32'h0; + 8'hc3: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am0 : 32'h0; + 8'hc4: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr1 : 32'h0; + 8'hc5: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am1 : 32'h0; + 8'hc6: wb_rf_dout <= #1 ch23_conf[0] ? pointer23 : 32'h0; + 8'hc7: wb_rf_dout <= #1 ch23_conf[0] ? sw_pointer23 : 32'h0; + + 8'hc8: wb_rf_dout <= #1 ch24_conf[0] ? ch24_csr : 32'h0; + 8'hc9: wb_rf_dout <= #1 ch24_conf[0] ? ch24_txsz : 32'h0; + 8'hca: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr0 : 32'h0; + 8'hcb: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am0 : 32'h0; + 8'hcc: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr1 : 32'h0; + 8'hcd: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am1 : 32'h0; + 8'hce: wb_rf_dout <= #1 ch24_conf[0] ? pointer24 : 32'h0; + 8'hcf: wb_rf_dout <= #1 ch24_conf[0] ? sw_pointer24 : 32'h0; + + 8'hd0: wb_rf_dout <= #1 ch25_conf[0] ? ch25_csr : 32'h0; + 8'hd1: wb_rf_dout <= #1 ch25_conf[0] ? ch25_txsz : 32'h0; + 8'hd2: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr0 : 32'h0; + 8'hd3: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am0 : 32'h0; + 8'hd4: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr1 : 32'h0; + 8'hd5: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am1 : 32'h0; + 8'hd6: wb_rf_dout <= #1 ch25_conf[0] ? pointer25 : 32'h0; + 8'hd7: wb_rf_dout <= #1 ch25_conf[0] ? sw_pointer25 : 32'h0; + + 8'hd8: wb_rf_dout <= #1 ch26_conf[0] ? ch26_csr : 32'h0; + 8'hd9: wb_rf_dout <= #1 ch26_conf[0] ? ch26_txsz : 32'h0; + 8'hda: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr0 : 32'h0; + 8'hdb: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am0 : 32'h0; + 8'hdc: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr1 : 32'h0; + 8'hdd: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am1 : 32'h0; + 8'hde: wb_rf_dout <= #1 ch26_conf[0] ? pointer26 : 32'h0; + 8'hdf: wb_rf_dout <= #1 ch26_conf[0] ? sw_pointer26 : 32'h0; + + 8'he0: wb_rf_dout <= #1 ch27_conf[0] ? ch27_csr : 32'h0; + 8'he1: wb_rf_dout <= #1 ch27_conf[0] ? ch27_txsz : 32'h0; + 8'he2: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr0 : 32'h0; + 8'he3: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am0 : 32'h0; + 8'he4: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr1 : 32'h0; + 8'he5: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am1 : 32'h0; + 8'he6: wb_rf_dout <= #1 ch27_conf[0] ? pointer27 : 32'h0; + 8'he7: wb_rf_dout <= #1 ch27_conf[0] ? sw_pointer27 : 32'h0; + + 8'he8: wb_rf_dout <= #1 ch28_conf[0] ? ch28_csr : 32'h0; + 8'he9: wb_rf_dout <= #1 ch28_conf[0] ? ch28_txsz : 32'h0; + 8'hea: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr0 : 32'h0; + 8'heb: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am0 : 32'h0; + 8'hec: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr1 : 32'h0; + 8'hed: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am1 : 32'h0; + 8'hee: wb_rf_dout <= #1 ch28_conf[0] ? pointer28 : 32'h0; + 8'hef: wb_rf_dout <= #1 ch28_conf[0] ? sw_pointer28 : 32'h0; + + 8'hf0: wb_rf_dout <= #1 ch29_conf[0] ? ch29_csr : 32'h0; + 8'hf1: wb_rf_dout <= #1 ch29_conf[0] ? ch29_txsz : 32'h0; + 8'hf2: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr0 : 32'h0; + 8'hf3: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am0 : 32'h0; + 8'hf4: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr1 : 32'h0; + 8'hf5: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am1 : 32'h0; + 8'hf6: wb_rf_dout <= #1 ch29_conf[0] ? pointer29 : 32'h0; + 8'hf7: wb_rf_dout <= #1 ch29_conf[0] ? sw_pointer29 : 32'h0; + + 8'hf8: wb_rf_dout <= #1 ch30_conf[0] ? ch30_csr : 32'h0; + 8'hf9: wb_rf_dout <= #1 ch30_conf[0] ? ch30_txsz : 32'h0; + 8'hfa: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr0 : 32'h0; + 8'hfb: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am0 : 32'h0; + 8'hfc: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr1 : 32'h0; + 8'hfd: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am1 : 32'h0; + 8'hfe: wb_rf_dout <= #1 ch30_conf[0] ? pointer30 : 32'h0; + 8'hff: wb_rf_dout <= #1 ch30_conf[0] ? sw_pointer30 : 32'h0; + + endcase + + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Write Logic +// And DMA Engine register Update Logic +// + +// Global Registers +assign csr_we = wb_rf_we & (wb_rf_adr == 8'h0); +assign int_maska_we = wb_rf_we & (wb_rf_adr == 8'h1); +assign int_maskb_we = wb_rf_we & (wb_rf_adr == 8'h2); + +// --------------------------------------------------- + +always @(posedge clk or negedge rst) + if(!rst) csr_r <= #1 8'h0; + else + if(csr_we) csr_r <= #1 wb_rf_din[7:0]; + +// --------------------------------------------------- +// INT_MASK +always @(posedge clk or negedge rst) + if(!rst) int_maska_r <= #1 31'h0; + else + if(int_maska_we) int_maska_r <= #1 wb_rf_din[30:0]; + +always @(posedge clk or negedge rst) + if(!rst) int_maskb_r <= #1 31'h0; + else + if(int_maskb_we) int_maskb_r <= #1 wb_rf_din[30:0]; + +//////////////////////////////////////////////////////////////////// +// +// Interrupts +// + +assign int_srca = {1'b0, (int_maska_r & ch_int) }; +assign int_srcb = {1'b0, (int_maskb_r & ch_int) }; + +// Interrupt Outputs +always @(posedge clk) + inta_o <= #1 |int_srca; + +always @(posedge clk) + intb_o <= #1 |int_srcb; + +//////////////////////////////////////////////////////////////////// +// +// Channel Register File +// + +// chXX_conf = { CBUF, ED, ARS, EN } + +wb_dma_ch_rf #(0, ch0_conf[0], ch0_conf[1], ch0_conf[2], ch0_conf[3]) u0( + .clk( clk ), + .rst( rst ), + .pointer( pointer0 ), + .pointer_s( pointer0_s ), + .ch_csr( ch0_csr ), + .ch_txsz( ch0_txsz ), + .ch_adr0( ch0_adr0 ), + .ch_adr1( ch0_adr1 ), + .ch_am0( ch0_am0 ), + .ch_am1( ch0_am1 ), + .sw_pointer( sw_pointer0 ), + .ch_stop( ch_stop[0] ), + .ch_dis( ch_dis[0] ), + .int( ch_int[0] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[0] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[0] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(1, ch1_conf[0], ch1_conf[1], ch1_conf[2], ch1_conf[3]) u1( + .clk( clk ), + .rst( rst ), + .pointer( pointer1 ), + .pointer_s( pointer1_s ), + .ch_csr( ch1_csr ), + .ch_txsz( ch1_txsz ), + .ch_adr0( ch1_adr0 ), + .ch_adr1( ch1_adr1 ), + .ch_am0( ch1_am0 ), + .ch_am1( ch1_am1 ), + .sw_pointer( sw_pointer1 ), + .ch_stop( ch_stop[1] ), + .ch_dis( ch_dis[1] ), + .int( ch_int[1] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[1] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[1] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(2, ch2_conf[0], ch2_conf[1], ch2_conf[2], ch2_conf[3]) u2( + .clk( clk ), + .rst( rst ), + .pointer( pointer2 ), + .pointer_s( pointer2_s ), + .ch_csr( ch2_csr ), + .ch_txsz( ch2_txsz ), + .ch_adr0( ch2_adr0 ), + .ch_adr1( ch2_adr1 ), + .ch_am0( ch2_am0 ), + .ch_am1( ch2_am1 ), + .sw_pointer( sw_pointer2 ), + .ch_stop( ch_stop[2] ), + .ch_dis( ch_dis[2] ), + .int( ch_int[2] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[2] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[2] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(3, ch3_conf[0], ch3_conf[1], ch3_conf[2], ch3_conf[3]) u3( + .clk( clk ), + .rst( rst ), + .pointer( pointer3 ), + .pointer_s( pointer3_s ), + .ch_csr( ch3_csr ), + .ch_txsz( ch3_txsz ), + .ch_adr0( ch3_adr0 ), + .ch_adr1( ch3_adr1 ), + .ch_am0( ch3_am0 ), + .ch_am1( ch3_am1 ), + .sw_pointer( sw_pointer3 ), + .ch_stop( ch_stop[3] ), + .ch_dis( ch_dis[3] ), + .int( ch_int[3] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[3] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[3] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(4, ch4_conf[0], ch4_conf[1], ch4_conf[2], ch4_conf[3]) u4( + .clk( clk ), + .rst( rst ), + .pointer( pointer4 ), + .pointer_s( pointer4_s ), + .ch_csr( ch4_csr ), + .ch_txsz( ch4_txsz ), + .ch_adr0( ch4_adr0 ), + .ch_adr1( ch4_adr1 ), + .ch_am0( ch4_am0 ), + .ch_am1( ch4_am1 ), + .sw_pointer( sw_pointer4 ), + .ch_stop( ch_stop[4] ), + .ch_dis( ch_dis[4] ), + .int( ch_int[4] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[4] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[4] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(5, ch5_conf[0], ch5_conf[1], ch5_conf[2], ch5_conf[3]) u5( + .clk( clk ), + .rst( rst ), + .pointer( pointer5 ), + .pointer_s( pointer5_s ), + .ch_csr( ch5_csr ), + .ch_txsz( ch5_txsz ), + .ch_adr0( ch5_adr0 ), + .ch_adr1( ch5_adr1 ), + .ch_am0( ch5_am0 ), + .ch_am1( ch5_am1 ), + .sw_pointer( sw_pointer5 ), + .ch_stop( ch_stop[5] ), + .ch_dis( ch_dis[5] ), + .int( ch_int[5] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[5] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[5] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(6, ch6_conf[0], ch6_conf[1], ch6_conf[2], ch6_conf[3]) u6( + .clk( clk ), + .rst( rst ), + .pointer( pointer6 ), + .pointer_s( pointer6_s ), + .ch_csr( ch6_csr ), + .ch_txsz( ch6_txsz ), + .ch_adr0( ch6_adr0 ), + .ch_adr1( ch6_adr1 ), + .ch_am0( ch6_am0 ), + .ch_am1( ch6_am1 ), + .sw_pointer( sw_pointer6 ), + .ch_stop( ch_stop[6] ), + .ch_dis( ch_dis[6] ), + .int( ch_int[6] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[6] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[6] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(7, ch7_conf[0], ch7_conf[1], ch7_conf[2], ch7_conf[3]) u7( + .clk( clk ), + .rst( rst ), + .pointer( pointer7 ), + .pointer_s( pointer7_s ), + .ch_csr( ch7_csr ), + .ch_txsz( ch7_txsz ), + .ch_adr0( ch7_adr0 ), + .ch_adr1( ch7_adr1 ), + .ch_am0( ch7_am0 ), + .ch_am1( ch7_am1 ), + .sw_pointer( sw_pointer7 ), + .ch_stop( ch_stop[7] ), + .ch_dis( ch_dis[7] ), + .int( ch_int[7] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[7] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[7] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(8, ch8_conf[0], ch8_conf[1], ch8_conf[2], ch8_conf[3]) u8( + .clk( clk ), + .rst( rst ), + .pointer( pointer8 ), + .pointer_s( pointer8_s ), + .ch_csr( ch8_csr ), + .ch_txsz( ch8_txsz ), + .ch_adr0( ch8_adr0 ), + .ch_adr1( ch8_adr1 ), + .ch_am0( ch8_am0 ), + .ch_am1( ch8_am1 ), + .sw_pointer( sw_pointer8 ), + .ch_stop( ch_stop[8] ), + .ch_dis( ch_dis[8] ), + .int( ch_int[8] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[8] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[8] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(9, ch9_conf[0], ch9_conf[1], ch9_conf[2], ch9_conf[3]) u9( + .clk( clk ), + .rst( rst ), + .pointer( pointer9 ), + .pointer_s( pointer9_s ), + .ch_csr( ch9_csr ), + .ch_txsz( ch9_txsz ), + .ch_adr0( ch9_adr0 ), + .ch_adr1( ch9_adr1 ), + .ch_am0( ch9_am0 ), + .ch_am1( ch9_am1 ), + .sw_pointer( sw_pointer9 ), + .ch_stop( ch_stop[9] ), + .ch_dis( ch_dis[9] ), + .int( ch_int[9] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[9] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[9] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(10, ch10_conf[0], ch10_conf[1], ch10_conf[2], ch10_conf[3]) u10( + .clk( clk ), + .rst( rst ), + .pointer( pointer10 ), + .pointer_s( pointer10_s ), + .ch_csr( ch10_csr ), + .ch_txsz( ch10_txsz ), + .ch_adr0( ch10_adr0 ), + .ch_adr1( ch10_adr1 ), + .ch_am0( ch10_am0 ), + .ch_am1( ch10_am1 ), + .sw_pointer( sw_pointer10 ), + .ch_stop( ch_stop[10] ), + .ch_dis( ch_dis[10] ), + .int( ch_int[10] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[10] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[10] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(11, ch11_conf[0], ch11_conf[1], ch11_conf[2], ch11_conf[3]) u11( + .clk( clk ), + .rst( rst ), + .pointer( pointer11 ), + .pointer_s( pointer11_s ), + .ch_csr( ch11_csr ), + .ch_txsz( ch11_txsz ), + .ch_adr0( ch11_adr0 ), + .ch_adr1( ch11_adr1 ), + .ch_am0( ch11_am0 ), + .ch_am1( ch11_am1 ), + .sw_pointer( sw_pointer11 ), + .ch_stop( ch_stop[11] ), + .ch_dis( ch_dis[11] ), + .int( ch_int[11] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[11] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[11] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(12, ch12_conf[0], ch12_conf[1], ch12_conf[2], ch12_conf[3]) u12( + .clk( clk ), + .rst( rst ), + .pointer( pointer12 ), + .pointer_s( pointer12_s ), + .ch_csr( ch12_csr ), + .ch_txsz( ch12_txsz ), + .ch_adr0( ch12_adr0 ), + .ch_adr1( ch12_adr1 ), + .ch_am0( ch12_am0 ), + .ch_am1( ch12_am1 ), + .sw_pointer( sw_pointer12 ), + .ch_stop( ch_stop[12] ), + .ch_dis( ch_dis[12] ), + .int( ch_int[12] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[12] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[12] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(13, ch13_conf[0], ch13_conf[1], ch13_conf[2], ch13_conf[3]) u13( + .clk( clk ), + .rst( rst ), + .pointer( pointer13 ), + .pointer_s( pointer13_s ), + .ch_csr( ch13_csr ), + .ch_txsz( ch13_txsz ), + .ch_adr0( ch13_adr0 ), + .ch_adr1( ch13_adr1 ), + .ch_am0( ch13_am0 ), + .ch_am1( ch13_am1 ), + .sw_pointer( sw_pointer13 ), + .ch_stop( ch_stop[13] ), + .ch_dis( ch_dis[13] ), + .int( ch_int[13] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[13] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[13] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(14, ch14_conf[0], ch14_conf[1], ch14_conf[2], ch14_conf[3]) u14( + .clk( clk ), + .rst( rst ), + .pointer( pointer14 ), + .pointer_s( pointer14_s ), + .ch_csr( ch14_csr ), + .ch_txsz( ch14_txsz ), + .ch_adr0( ch14_adr0 ), + .ch_adr1( ch14_adr1 ), + .ch_am0( ch14_am0 ), + .ch_am1( ch14_am1 ), + .sw_pointer( sw_pointer14 ), + .ch_stop( ch_stop[14] ), + .ch_dis( ch_dis[14] ), + .int( ch_int[14] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[14] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[14] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(15, ch15_conf[0], ch15_conf[1], ch15_conf[2], ch15_conf[3]) u15( + .clk( clk ), + .rst( rst ), + .pointer( pointer15 ), + .pointer_s( pointer15_s ), + .ch_csr( ch15_csr ), + .ch_txsz( ch15_txsz ), + .ch_adr0( ch15_adr0 ), + .ch_adr1( ch15_adr1 ), + .ch_am0( ch15_am0 ), + .ch_am1( ch15_am1 ), + .sw_pointer( sw_pointer15 ), + .ch_stop( ch_stop[15] ), + .ch_dis( ch_dis[15] ), + .int( ch_int[15] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[15] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[15] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(16, ch16_conf[0], ch16_conf[1], ch16_conf[2], ch16_conf[3]) u16( + .clk( clk ), + .rst( rst ), + .pointer( pointer16 ), + .pointer_s( pointer16_s ), + .ch_csr( ch16_csr ), + .ch_txsz( ch16_txsz ), + .ch_adr0( ch16_adr0 ), + .ch_adr1( ch16_adr1 ), + .ch_am0( ch16_am0 ), + .ch_am1( ch16_am1 ), + .sw_pointer( sw_pointer16 ), + .ch_stop( ch_stop[16] ), + .ch_dis( ch_dis[16] ), + .int( ch_int[16] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[16] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[16] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(17, ch17_conf[0], ch17_conf[1], ch17_conf[2], ch17_conf[3]) u17( + .clk( clk ), + .rst( rst ), + .pointer( pointer17 ), + .pointer_s( pointer17_s ), + .ch_csr( ch17_csr ), + .ch_txsz( ch17_txsz ), + .ch_adr0( ch17_adr0 ), + .ch_adr1( ch17_adr1 ), + .ch_am0( ch17_am0 ), + .ch_am1( ch17_am1 ), + .sw_pointer( sw_pointer17 ), + .ch_stop( ch_stop[17] ), + .ch_dis( ch_dis[17] ), + .int( ch_int[17] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[17] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[17] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(18, ch18_conf[0], ch18_conf[1], ch18_conf[2], ch18_conf[3]) u18( + .clk( clk ), + .rst( rst ), + .pointer( pointer18 ), + .pointer_s( pointer18_s ), + .ch_csr( ch18_csr ), + .ch_txsz( ch18_txsz ), + .ch_adr0( ch18_adr0 ), + .ch_adr1( ch18_adr1 ), + .ch_am0( ch18_am0 ), + .ch_am1( ch18_am1 ), + .sw_pointer( sw_pointer18 ), + .ch_stop( ch_stop[18] ), + .ch_dis( ch_dis[18] ), + .int( ch_int[18] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[18] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[18] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(19, ch19_conf[0], ch19_conf[1], ch19_conf[2], ch19_conf[3]) u19( + .clk( clk ), + .rst( rst ), + .pointer( pointer19 ), + .pointer_s( pointer19_s ), + .ch_csr( ch19_csr ), + .ch_txsz( ch19_txsz ), + .ch_adr0( ch19_adr0 ), + .ch_adr1( ch19_adr1 ), + .ch_am0( ch19_am0 ), + .ch_am1( ch19_am1 ), + .sw_pointer( sw_pointer19 ), + .ch_stop( ch_stop[19] ), + .ch_dis( ch_dis[19] ), + .int( ch_int[19] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[19] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[19] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(20, ch20_conf[0], ch20_conf[1], ch20_conf[2], ch20_conf[3]) u20( + .clk( clk ), + .rst( rst ), + .pointer( pointer20 ), + .pointer_s( pointer20_s ), + .ch_csr( ch20_csr ), + .ch_txsz( ch20_txsz ), + .ch_adr0( ch20_adr0 ), + .ch_adr1( ch20_adr1 ), + .ch_am0( ch20_am0 ), + .ch_am1( ch20_am1 ), + .sw_pointer( sw_pointer20 ), + .ch_stop( ch_stop[20] ), + .ch_dis( ch_dis[20] ), + .int( ch_int[20] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[20] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[20] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(21, ch21_conf[0], ch21_conf[1], ch21_conf[2], ch21_conf[3]) u21( + .clk( clk ), + .rst( rst ), + .pointer( pointer21 ), + .pointer_s( pointer21_s ), + .ch_csr( ch21_csr ), + .ch_txsz( ch21_txsz ), + .ch_adr0( ch21_adr0 ), + .ch_adr1( ch21_adr1 ), + .ch_am0( ch21_am0 ), + .ch_am1( ch21_am1 ), + .sw_pointer( sw_pointer21 ), + .ch_stop( ch_stop[21] ), + .ch_dis( ch_dis[21] ), + .int( ch_int[21] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[21] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[21] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(22, ch22_conf[0], ch22_conf[1], ch22_conf[2], ch22_conf[3]) u22( + .clk( clk ), + .rst( rst ), + .pointer( pointer22 ), + .pointer_s( pointer22_s ), + .ch_csr( ch22_csr ), + .ch_txsz( ch22_txsz ), + .ch_adr0( ch22_adr0 ), + .ch_adr1( ch22_adr1 ), + .ch_am0( ch22_am0 ), + .ch_am1( ch22_am1 ), + .sw_pointer( sw_pointer22 ), + .ch_stop( ch_stop[22] ), + .ch_dis( ch_dis[22] ), + .int( ch_int[22] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[22] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[22] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(23, ch23_conf[0], ch23_conf[1], ch23_conf[2], ch23_conf[3]) u23( + .clk( clk ), + .rst( rst ), + .pointer( pointer23 ), + .pointer_s( pointer23_s ), + .ch_csr( ch23_csr ), + .ch_txsz( ch23_txsz ), + .ch_adr0( ch23_adr0 ), + .ch_adr1( ch23_adr1 ), + .ch_am0( ch23_am0 ), + .ch_am1( ch23_am1 ), + .sw_pointer( sw_pointer23 ), + .ch_stop( ch_stop[23] ), + .ch_dis( ch_dis[23] ), + .int( ch_int[23] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[23] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[23] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(24, ch24_conf[0], ch24_conf[1], ch24_conf[2], ch24_conf[3]) u24( + .clk( clk ), + .rst( rst ), + .pointer( pointer24 ), + .pointer_s( pointer24_s ), + .ch_csr( ch24_csr ), + .ch_txsz( ch24_txsz ), + .ch_adr0( ch24_adr0 ), + .ch_adr1( ch24_adr1 ), + .ch_am0( ch24_am0 ), + .ch_am1( ch24_am1 ), + .sw_pointer( sw_pointer24 ), + .ch_stop( ch_stop[24] ), + .ch_dis( ch_dis[24] ), + .int( ch_int[24] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[24] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[24] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(25, ch25_conf[0], ch25_conf[1], ch25_conf[2], ch25_conf[3]) u25( + .clk( clk ), + .rst( rst ), + .pointer( pointer25 ), + .pointer_s( pointer25_s ), + .ch_csr( ch25_csr ), + .ch_txsz( ch25_txsz ), + .ch_adr0( ch25_adr0 ), + .ch_adr1( ch25_adr1 ), + .ch_am0( ch25_am0 ), + .ch_am1( ch25_am1 ), + .sw_pointer( sw_pointer25 ), + .ch_stop( ch_stop[25] ), + .ch_dis( ch_dis[25] ), + .int( ch_int[25] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[25] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[25] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(26, ch26_conf[0], ch26_conf[1], ch26_conf[2], ch26_conf[3]) u26( + .clk( clk ), + .rst( rst ), + .pointer( pointer26 ), + .pointer_s( pointer26_s ), + .ch_csr( ch26_csr ), + .ch_txsz( ch26_txsz ), + .ch_adr0( ch26_adr0 ), + .ch_adr1( ch26_adr1 ), + .ch_am0( ch26_am0 ), + .ch_am1( ch26_am1 ), + .sw_pointer( sw_pointer26 ), + .ch_stop( ch_stop[26] ), + .ch_dis( ch_dis[26] ), + .int( ch_int[26] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[26] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[26] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(27, ch27_conf[0], ch27_conf[1], ch27_conf[2], ch27_conf[3]) u27( + .clk( clk ), + .rst( rst ), + .pointer( pointer27 ), + .pointer_s( pointer27_s ), + .ch_csr( ch27_csr ), + .ch_txsz( ch27_txsz ), + .ch_adr0( ch27_adr0 ), + .ch_adr1( ch27_adr1 ), + .ch_am0( ch27_am0 ), + .ch_am1( ch27_am1 ), + .sw_pointer( sw_pointer27 ), + .ch_stop( ch_stop[27] ), + .ch_dis( ch_dis[27] ), + .int( ch_int[27] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[27] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[27] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(28, ch28_conf[0], ch28_conf[1], ch28_conf[2], ch28_conf[3]) u28( + .clk( clk ), + .rst( rst ), + .pointer( pointer28 ), + .pointer_s( pointer28_s ), + .ch_csr( ch28_csr ), + .ch_txsz( ch28_txsz ), + .ch_adr0( ch28_adr0 ), + .ch_adr1( ch28_adr1 ), + .ch_am0( ch28_am0 ), + .ch_am1( ch28_am1 ), + .sw_pointer( sw_pointer28 ), + .ch_stop( ch_stop[28] ), + .ch_dis( ch_dis[28] ), + .int( ch_int[28] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[28] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[28] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(29, ch29_conf[0], ch29_conf[1], ch29_conf[2], ch29_conf[3]) u29( + .clk( clk ), + .rst( rst ), + .pointer( pointer29 ), + .pointer_s( pointer29_s ), + .ch_csr( ch29_csr ), + .ch_txsz( ch29_txsz ), + .ch_adr0( ch29_adr0 ), + .ch_adr1( ch29_adr1 ), + .ch_am0( ch29_am0 ), + .ch_am1( ch29_am1 ), + .sw_pointer( sw_pointer29 ), + .ch_stop( ch_stop[29] ), + .ch_dis( ch_dis[29] ), + .int( ch_int[29] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[29] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[29] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(30, ch30_conf[0], ch30_conf[1], ch30_conf[2], ch30_conf[3]) u30( + .clk( clk ), + .rst( rst ), + .pointer( pointer30 ), + .pointer_s( pointer30_s ), + .ch_csr( ch30_csr ), + .ch_txsz( ch30_txsz ), + .ch_adr0( ch30_adr0 ), + .ch_adr1( ch30_adr1 ), + .ch_am0( ch30_am0 ), + .ch_am1( ch30_am1 ), + .sw_pointer( sw_pointer30 ), + .ch_stop( ch_stop[30] ), + .ch_dis( ch_dis[30] ), + .int( ch_int[30] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[30] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[30] ), + .ptr_set( ptr_set ) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_top.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_top.v new file mode 100644 index 000000000..3d6a3148b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_top.v @@ -0,0 +1,1126 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_top.v,v 1.5 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_top.v,v $ +// Revision 1.5 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/09/07 15:34:38 rudi +// +// Changed reset to active high. +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/13 02:26:50 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:23 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_top(clk_i, rst_i, + + wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i, + wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o, + wb0m_data_i, wb0m_data_o, wb0_addr_o, wb0_sel_o, wb0_we_o, wb0_cyc_o, + wb0_stb_o, wb0_ack_i, wb0_err_i, wb0_rty_i, + + wb1s_data_i, wb1s_data_o, wb1_addr_i, wb1_sel_i, wb1_we_i, wb1_cyc_i, + wb1_stb_i, wb1_ack_o, wb1_err_o, wb1_rty_o, + wb1m_data_i, wb1m_data_o, wb1_addr_o, wb1_sel_o, wb1_we_o, wb1_cyc_o, + wb1_stb_o, wb1_ack_i, wb1_err_i, wb1_rty_i, + + dma_req_i, dma_ack_o, dma_nd_i, dma_rest_i, + + inta_o, intb_o + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter rf_addr = 0; +parameter [1:0] pri_sel = 2'h0; +parameter ch_count = 1; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE INTERFACE 0 + +// Slave Interface +input [31:0] wb0s_data_i; +output [31:0] wb0s_data_o; +input [31:0] wb0_addr_i; +input [3:0] wb0_sel_i; +input wb0_we_i; +input wb0_cyc_i; +input wb0_stb_i; +output wb0_ack_o; +output wb0_err_o; +output wb0_rty_o; + +// Master Interface +input [31:0] wb0m_data_i; +output [31:0] wb0m_data_o; +output [31:0] wb0_addr_o; +output [3:0] wb0_sel_o; +output wb0_we_o; +output wb0_cyc_o; +output wb0_stb_o; +input wb0_ack_i; +input wb0_err_i; +input wb0_rty_i; + +// -------------------------------------- +// WISHBONE INTERFACE 1 + +// Slave Interface +input [31:0] wb1s_data_i; +output [31:0] wb1s_data_o; +input [31:0] wb1_addr_i; +input [3:0] wb1_sel_i; +input wb1_we_i; +input wb1_cyc_i; +input wb1_stb_i; +output wb1_ack_o; +output wb1_err_o; +output wb1_rty_o; + +// Master Interface +input [31:0] wb1m_data_i; +output [31:0] wb1m_data_o; +output [31:0] wb1_addr_o; +output [3:0] wb1_sel_o; +output wb1_we_o; +output wb1_cyc_o; +output wb1_stb_o; +input wb1_ack_i; +input wb1_err_i; +input wb1_rty_i; + +// -------------------------------------- +// Misc Signals +input [ch_count-1:0] dma_req_i; +input [ch_count-1:0] dma_nd_i; +output [ch_count-1:0] dma_ack_o; +input [ch_count-1:0] dma_rest_i; +output inta_o; +output intb_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +wire [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +wire [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +wire [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +wire [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +wire [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +wire [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +wire [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +wire [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +wire [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +wire [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +wire [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +wire [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +wire [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +wire [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +wire [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +wire [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +wire [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +wire [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +wire [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +wire [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +wire [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +wire [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +wire [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +wire [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +wire [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +wire [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +wire [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +wire [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +wire [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +wire [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +wire [4:0] ch_sel; // Write Back Channel Select +wire [30:0] ndnr; // Next Descriptor No Request +wire de_start; // Start DMA Engine +wire ndr; // Next Descriptor With Request +wire [31:0] csr; // Selected Channel CSR +wire [31:0] pointer; +wire [31:0] pointer_s; +wire [31:0] txsz; // Selected Channel Transfer Size +wire [31:0] adr0, adr1; // Selected Channel Addresses +wire [31:0] am0, am1; // Selected Channel Address Masks +wire next_ch; // Indicates the DMA Engine is done + +wire inta_o, intb_o; +wire dma_abort; +wire dma_busy, dma_err, dma_done, dma_done_all; +wire [31:0] de_csr; +wire [11:0] de_txsz; +wire [31:0] de_adr0; +wire [31:0] de_adr1; +wire de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we; +wire de_fetch_descr; +wire ptr_set; +wire de_ack; +wire pause_req; +wire paused; + +wire mast0_go; // Perform a Master Cycle (as long as this +wire mast0_we; // Read/Write +wire [31:0] mast0_adr; // Address for the transfer +wire [31:0] mast0_din; // Internal Input Data +wire [31:0] mast0_dout; // Internal Output Data +wire mast0_err; // Indicates an error has occurred +wire mast0_drdy; // Indicated that either data is available +wire mast0_wait; // Tells the master to insert wait cycles + +wire [31:0] slv0_adr; // Slave Address +wire [31:0] slv0_din; // Slave Input Data +wire [31:0] slv0_dout; // Slave Output Data +wire slv0_re; // Slave Read Enable +wire slv0_we; // Slave Write Enable + +wire pt0_sel_i; // Pass Through Mode Selected +wire [70:0] mast0_pt_in; // Grouped WISHBONE inputs +wire [34:0] mast0_pt_out; // Grouped WISHBONE outputs + +wire pt0_sel_o; // Pass Through Mode Active +wire [70:0] slv0_pt_out; // Grouped WISHBONE out signals +wire [34:0] slv0_pt_in; // Grouped WISHBONE in signals + +wire mast1_go; // Perform a Master Cycle (as long as this +wire mast1_we; // Read/Write +wire [31:0] mast1_adr; // Address for the transfer +wire [31:0] mast1_din; // Internal Input Data +wire [31:0] mast1_dout; // Internal Output Data +wire mast1_err; // Indicates an error has occurred +wire mast1_drdy; // Indicated that either data is available +wire mast1_wait; // Tells the master to insert wait cycles + +wire [31:0] slv1_adr; // Slave Address +wire [31:0] slv1_dout; // Slave Output Data +wire slv1_re; // Slave Read Enable +wire slv1_we; // Slave Write Enable + +wire pt1_sel_i; // Pass Through Mode Selected +wire [70:0] mast1_pt_in; // Grouped WISHBONE inputs +wire [34:0] mast1_pt_out; // Grouped WISHBONE outputs + +wire pt1_sel_o; // Pass Through Mode Active +wire [70:0] slv1_pt_out; // Grouped WISHBONE out signals +wire [34:0] slv1_pt_in; // Grouped WISHBONE in signals + +wire [30:0] dma_req; +wire [30:0] dma_nd; +wire [30:0] dma_ack; +wire [30:0] dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +wire [31:0] tmp_gnd = 32'h0; + +assign dma_req[ch_count-1:0] = dma_req_i; +assign dma_nd[ch_count-1:0] = dma_nd_i; +assign dma_rest[ch_count-1:0] = dma_rest_i; +assign dma_ack_o = {tmp_gnd[31-ch_count:0], dma_ack[ch_count-1:0]}; + +// -------------------------------------------------- +// This should go in to a separate Pass Through Block +assign pt1_sel_i = pt0_sel_o; +assign pt0_sel_i = pt1_sel_o; +assign mast1_pt_in = slv0_pt_out; +assign slv0_pt_in = mast1_pt_out; +assign mast0_pt_in = slv1_pt_out; +assign slv1_pt_in = mast0_pt_out; +// -------------------------------------------------- + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +// DMA Register File +wb_dma_rf #( ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u0( + .clk( clk_i ), + .rst( ~rst_i ), + .wb_rf_adr( slv0_adr[9:2] ), + .wb_rf_din( slv0_dout ), + .wb_rf_dout( slv0_din ), + .wb_rf_re( slv0_re ), + .wb_rf_we( slv0_we ), + .inta_o( inta_o ), + .intb_o( intb_o ), + .pointer0( pointer0 ), + .pointer0_s( pointer0_s ), + .ch0_csr( ch0_csr ), + .ch0_txsz( ch0_txsz ), + .ch0_adr0( ch0_adr0 ), + .ch0_adr1( ch0_adr1 ), + .ch0_am0( ch0_am0 ), + .ch0_am1( ch0_am1 ), + .pointer1( pointer1 ), + .pointer1_s( pointer1_s ), + .ch1_csr( ch1_csr ), + .ch1_txsz( ch1_txsz ), + .ch1_adr0( ch1_adr0 ), + .ch1_adr1( ch1_adr1 ), + .ch1_am0( ch1_am0 ), + .ch1_am1( ch1_am1 ), + .pointer2( pointer2 ), + .pointer2_s( pointer2_s ), + .ch2_csr( ch2_csr ), + .ch2_txsz( ch2_txsz ), + .ch2_adr0( ch2_adr0 ), + .ch2_adr1( ch2_adr1 ), + .ch2_am0( ch2_am0 ), + .ch2_am1( ch2_am1 ), + .pointer3( pointer3 ), + .pointer3_s( pointer3_s ), + .ch3_csr( ch3_csr ), + .ch3_txsz( ch3_txsz ), + .ch3_adr0( ch3_adr0 ), + .ch3_adr1( ch3_adr1 ), + .ch3_am0( ch3_am0 ), + .ch3_am1( ch3_am1 ), + .pointer4( pointer4 ), + .pointer4_s( pointer4_s ), + .ch4_csr( ch4_csr ), + .ch4_txsz( ch4_txsz ), + .ch4_adr0( ch4_adr0 ), + .ch4_adr1( ch4_adr1 ), + .ch4_am0( ch4_am0 ), + .ch4_am1( ch4_am1 ), + .pointer5( pointer5 ), + .pointer5_s( pointer5_s ), + .ch5_csr( ch5_csr ), + .ch5_txsz( ch5_txsz ), + .ch5_adr0( ch5_adr0 ), + .ch5_adr1( ch5_adr1 ), + .ch5_am0( ch5_am0 ), + .ch5_am1( ch5_am1 ), + .pointer6( pointer6 ), + .pointer6_s( pointer6_s ), + .ch6_csr( ch6_csr ), + .ch6_txsz( ch6_txsz ), + .ch6_adr0( ch6_adr0 ), + .ch6_adr1( ch6_adr1 ), + .ch6_am0( ch6_am0 ), + .ch6_am1( ch6_am1 ), + .pointer7( pointer7 ), + .pointer7_s( pointer7_s ), + .ch7_csr( ch7_csr ), + .ch7_txsz( ch7_txsz ), + .ch7_adr0( ch7_adr0 ), + .ch7_adr1( ch7_adr1 ), + .ch7_am0( ch7_am0 ), + .ch7_am1( ch7_am1 ), + .pointer8( pointer8 ), + .pointer8_s( pointer8_s ), + .ch8_csr( ch8_csr ), + .ch8_txsz( ch8_txsz ), + .ch8_adr0( ch8_adr0 ), + .ch8_adr1( ch8_adr1 ), + .ch8_am0( ch8_am0 ), + .ch8_am1( ch8_am1 ), + .pointer9( pointer9 ), + .pointer9_s( pointer9_s ), + .ch9_csr( ch9_csr ), + .ch9_txsz( ch9_txsz ), + .ch9_adr0( ch9_adr0 ), + .ch9_adr1( ch9_adr1 ), + .ch9_am0( ch9_am0 ), + .ch9_am1( ch9_am1 ), + .pointer10( pointer10 ), + .pointer10_s( pointer10_s ), + .ch10_csr( ch10_csr ), + .ch10_txsz( ch10_txsz ), + .ch10_adr0( ch10_adr0 ), + .ch10_adr1( ch10_adr1 ), + .ch10_am0( ch10_am0 ), + .ch10_am1( ch10_am1 ), + .pointer11( pointer11 ), + .pointer11_s( pointer11_s ), + .ch11_csr( ch11_csr ), + .ch11_txsz( ch11_txsz ), + .ch11_adr0( ch11_adr0 ), + .ch11_adr1( ch11_adr1 ), + .ch11_am0( ch11_am0 ), + .ch11_am1( ch11_am1 ), + .pointer12( pointer12 ), + .pointer12_s( pointer12_s ), + .ch12_csr( ch12_csr ), + .ch12_txsz( ch12_txsz ), + .ch12_adr0( ch12_adr0 ), + .ch12_adr1( ch12_adr1 ), + .ch12_am0( ch12_am0 ), + .ch12_am1( ch12_am1 ), + .pointer13( pointer13 ), + .pointer13_s( pointer13_s ), + .ch13_csr( ch13_csr ), + .ch13_txsz( ch13_txsz ), + .ch13_adr0( ch13_adr0 ), + .ch13_adr1( ch13_adr1 ), + .ch13_am0( ch13_am0 ), + .ch13_am1( ch13_am1 ), + .pointer14( pointer14 ), + .pointer14_s( pointer14_s ), + .ch14_csr( ch14_csr ), + .ch14_txsz( ch14_txsz ), + .ch14_adr0( ch14_adr0 ), + .ch14_adr1( ch14_adr1 ), + .ch14_am0( ch14_am0 ), + .ch14_am1( ch14_am1 ), + .pointer15( pointer15 ), + .pointer15_s( pointer15_s ), + .ch15_csr( ch15_csr ), + .ch15_txsz( ch15_txsz ), + .ch15_adr0( ch15_adr0 ), + .ch15_adr1( ch15_adr1 ), + .ch15_am0( ch15_am0 ), + .ch15_am1( ch15_am1 ), + .pointer16( pointer16 ), + .pointer16_s( pointer16_s ), + .ch16_csr( ch16_csr ), + .ch16_txsz( ch16_txsz ), + .ch16_adr0( ch16_adr0 ), + .ch16_adr1( ch16_adr1 ), + .ch16_am0( ch16_am0 ), + .ch16_am1( ch16_am1 ), + .pointer17( pointer17 ), + .pointer17_s( pointer17_s ), + .ch17_csr( ch17_csr ), + .ch17_txsz( ch17_txsz ), + .ch17_adr0( ch17_adr0 ), + .ch17_adr1( ch17_adr1 ), + .ch17_am0( ch17_am0 ), + .ch17_am1( ch17_am1 ), + .pointer18( pointer18 ), + .pointer18_s( pointer18_s ), + .ch18_csr( ch18_csr ), + .ch18_txsz( ch18_txsz ), + .ch18_adr0( ch18_adr0 ), + .ch18_adr1( ch18_adr1 ), + .ch18_am0( ch18_am0 ), + .ch18_am1( ch18_am1 ), + .pointer19( pointer19 ), + .pointer19_s( pointer19_s ), + .ch19_csr( ch19_csr ), + .ch19_txsz( ch19_txsz ), + .ch19_adr0( ch19_adr0 ), + .ch19_adr1( ch19_adr1 ), + .ch19_am0( ch19_am0 ), + .ch19_am1( ch19_am1 ), + .pointer20( pointer20 ), + .pointer20_s( pointer20_s ), + .ch20_csr( ch20_csr ), + .ch20_txsz( ch20_txsz ), + .ch20_adr0( ch20_adr0 ), + .ch20_adr1( ch20_adr1 ), + .ch20_am0( ch20_am0 ), + .ch20_am1( ch20_am1 ), + .pointer21( pointer21 ), + .pointer21_s( pointer21_s ), + .ch21_csr( ch21_csr ), + .ch21_txsz( ch21_txsz ), + .ch21_adr0( ch21_adr0 ), + .ch21_adr1( ch21_adr1 ), + .ch21_am0( ch21_am0 ), + .ch21_am1( ch21_am1 ), + .pointer22( pointer22 ), + .pointer22_s( pointer22_s ), + .ch22_csr( ch22_csr ), + .ch22_txsz( ch22_txsz ), + .ch22_adr0( ch22_adr0 ), + .ch22_adr1( ch22_adr1 ), + .ch22_am0( ch22_am0 ), + .ch22_am1( ch22_am1 ), + .pointer23( pointer23 ), + .pointer23_s( pointer23_s ), + .ch23_csr( ch23_csr ), + .ch23_txsz( ch23_txsz ), + .ch23_adr0( ch23_adr0 ), + .ch23_adr1( ch23_adr1 ), + .ch23_am0( ch23_am0 ), + .ch23_am1( ch23_am1 ), + .pointer24( pointer24 ), + .pointer24_s( pointer24_s ), + .ch24_csr( ch24_csr ), + .ch24_txsz( ch24_txsz ), + .ch24_adr0( ch24_adr0 ), + .ch24_adr1( ch24_adr1 ), + .ch24_am0( ch24_am0 ), + .ch24_am1( ch24_am1 ), + .pointer25( pointer25 ), + .pointer25_s( pointer25_s ), + .ch25_csr( ch25_csr ), + .ch25_txsz( ch25_txsz ), + .ch25_adr0( ch25_adr0 ), + .ch25_adr1( ch25_adr1 ), + .ch25_am0( ch25_am0 ), + .ch25_am1( ch25_am1 ), + .pointer26( pointer26 ), + .pointer26_s( pointer26_s ), + .ch26_csr( ch26_csr ), + .ch26_txsz( ch26_txsz ), + .ch26_adr0( ch26_adr0 ), + .ch26_adr1( ch26_adr1 ), + .ch26_am0( ch26_am0 ), + .ch26_am1( ch26_am1 ), + .pointer27( pointer27 ), + .pointer27_s( pointer27_s ), + .ch27_csr( ch27_csr ), + .ch27_txsz( ch27_txsz ), + .ch27_adr0( ch27_adr0 ), + .ch27_adr1( ch27_adr1 ), + .ch27_am0( ch27_am0 ), + .ch27_am1( ch27_am1 ), + .pointer28( pointer28 ), + .pointer28_s( pointer28_s ), + .ch28_csr( ch28_csr ), + .ch28_txsz( ch28_txsz ), + .ch28_adr0( ch28_adr0 ), + .ch28_adr1( ch28_adr1 ), + .ch28_am0( ch28_am0 ), + .ch28_am1( ch28_am1 ), + .pointer29( pointer29 ), + .pointer29_s( pointer29_s ), + .ch29_csr( ch29_csr ), + .ch29_txsz( ch29_txsz ), + .ch29_adr0( ch29_adr0 ), + .ch29_adr1( ch29_adr1 ), + .ch29_am0( ch29_am0 ), + .ch29_am1( ch29_am1 ), + .pointer30( pointer30 ), + .pointer30_s( pointer30_s ), + .ch30_csr( ch30_csr ), + .ch30_txsz( ch30_txsz ), + .ch30_adr0( ch30_adr0 ), + .ch30_adr1( ch30_adr1 ), + .ch30_am0( ch30_am0 ), + .ch30_am1( ch30_am1 ), + .ch_sel( ch_sel ), + .ndnr( ndnr ), + .pause_req( pause_req ), + .paused( paused ), + .dma_abort( dma_abort ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest ), + .ptr_set( ptr_set ) + ); + +// Channel Select +wb_dma_ch_sel #(pri_sel, + ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u1( + .clk( clk_i ), + .rst( ~rst_i ), + .req_i( dma_req ), + .ack_o( dma_ack ), + .nd_i( dma_nd ), + + .pointer0( pointer0 ), + .pointer0_s( pointer0_s ), + .ch0_csr( ch0_csr ), + .ch0_txsz( ch0_txsz ), + .ch0_adr0( ch0_adr0 ), + .ch0_adr1( ch0_adr1 ), + .ch0_am0( ch0_am0 ), + .ch0_am1( ch0_am1 ), + .pointer1( pointer1 ), + .pointer1_s( pointer1_s ), + .ch1_csr( ch1_csr ), + .ch1_txsz( ch1_txsz ), + .ch1_adr0( ch1_adr0 ), + .ch1_adr1( ch1_adr1 ), + .ch1_am0( ch1_am0 ), + .ch1_am1( ch1_am1 ), + .pointer2( pointer2 ), + .pointer2_s( pointer2_s ), + .ch2_csr( ch2_csr ), + .ch2_txsz( ch2_txsz ), + .ch2_adr0( ch2_adr0 ), + .ch2_adr1( ch2_adr1 ), + .ch2_am0( ch2_am0 ), + .ch2_am1( ch2_am1 ), + .pointer3( pointer3 ), + .pointer3_s( pointer3_s ), + .ch3_csr( ch3_csr ), + .ch3_txsz( ch3_txsz ), + .ch3_adr0( ch3_adr0 ), + .ch3_adr1( ch3_adr1 ), + .ch3_am0( ch3_am0 ), + .ch3_am1( ch3_am1 ), + .pointer4( pointer4 ), + .pointer4_s( pointer4_s ), + .ch4_csr( ch4_csr ), + .ch4_txsz( ch4_txsz ), + .ch4_adr0( ch4_adr0 ), + .ch4_adr1( ch4_adr1 ), + .ch4_am0( ch4_am0 ), + .ch4_am1( ch4_am1 ), + .pointer5( pointer5 ), + .pointer5_s( pointer5_s ), + .ch5_csr( ch5_csr ), + .ch5_txsz( ch5_txsz ), + .ch5_adr0( ch5_adr0 ), + .ch5_adr1( ch5_adr1 ), + .ch5_am0( ch5_am0 ), + .ch5_am1( ch5_am1 ), + .pointer6( pointer6 ), + .pointer6_s( pointer6_s ), + .ch6_csr( ch6_csr ), + .ch6_txsz( ch6_txsz ), + .ch6_adr0( ch6_adr0 ), + .ch6_adr1( ch6_adr1 ), + .ch6_am0( ch6_am0 ), + .ch6_am1( ch6_am1 ), + .pointer7( pointer7 ), + .pointer7_s( pointer7_s ), + .ch7_csr( ch7_csr ), + .ch7_txsz( ch7_txsz ), + .ch7_adr0( ch7_adr0 ), + .ch7_adr1( ch7_adr1 ), + .ch7_am0( ch7_am0 ), + .ch7_am1( ch7_am1 ), + .pointer8( pointer8 ), + .pointer8_s( pointer8_s ), + .ch8_csr( ch8_csr ), + .ch8_txsz( ch8_txsz ), + .ch8_adr0( ch8_adr0 ), + .ch8_adr1( ch8_adr1 ), + .ch8_am0( ch8_am0 ), + .ch8_am1( ch8_am1 ), + .pointer9( pointer9 ), + .pointer9_s( pointer9_s ), + .ch9_csr( ch9_csr ), + .ch9_txsz( ch9_txsz ), + .ch9_adr0( ch9_adr0 ), + .ch9_adr1( ch9_adr1 ), + .ch9_am0( ch9_am0 ), + .ch9_am1( ch9_am1 ), + .pointer10( pointer10 ), + .pointer10_s( pointer10_s ), + .ch10_csr( ch10_csr ), + .ch10_txsz( ch10_txsz ), + .ch10_adr0( ch10_adr0 ), + .ch10_adr1( ch10_adr1 ), + .ch10_am0( ch10_am0 ), + .ch10_am1( ch10_am1 ), + .pointer11( pointer11 ), + .pointer11_s( pointer11_s ), + .ch11_csr( ch11_csr ), + .ch11_txsz( ch11_txsz ), + .ch11_adr0( ch11_adr0 ), + .ch11_adr1( ch11_adr1 ), + .ch11_am0( ch11_am0 ), + .ch11_am1( ch11_am1 ), + .pointer12( pointer12 ), + .pointer12_s( pointer12_s ), + .ch12_csr( ch12_csr ), + .ch12_txsz( ch12_txsz ), + .ch12_adr0( ch12_adr0 ), + .ch12_adr1( ch12_adr1 ), + .ch12_am0( ch12_am0 ), + .ch12_am1( ch12_am1 ), + .pointer13( pointer13 ), + .pointer13_s( pointer13_s ), + .ch13_csr( ch13_csr ), + .ch13_txsz( ch13_txsz ), + .ch13_adr0( ch13_adr0 ), + .ch13_adr1( ch13_adr1 ), + .ch13_am0( ch13_am0 ), + .ch13_am1( ch13_am1 ), + .pointer14( pointer14 ), + .pointer14_s( pointer14_s ), + .ch14_csr( ch14_csr ), + .ch14_txsz( ch14_txsz ), + .ch14_adr0( ch14_adr0 ), + .ch14_adr1( ch14_adr1 ), + .ch14_am0( ch14_am0 ), + .ch14_am1( ch14_am1 ), + .pointer15( pointer15 ), + .pointer15_s( pointer15_s ), + .ch15_csr( ch15_csr ), + .ch15_txsz( ch15_txsz ), + .ch15_adr0( ch15_adr0 ), + .ch15_adr1( ch15_adr1 ), + .ch15_am0( ch15_am0 ), + .ch15_am1( ch15_am1 ), + .pointer16( pointer16 ), + .pointer16_s( pointer16_s ), + .ch16_csr( ch16_csr ), + .ch16_txsz( ch16_txsz ), + .ch16_adr0( ch16_adr0 ), + .ch16_adr1( ch16_adr1 ), + .ch16_am0( ch16_am0 ), + .ch16_am1( ch16_am1 ), + .pointer17( pointer17 ), + .pointer17_s( pointer17_s ), + .ch17_csr( ch17_csr ), + .ch17_txsz( ch17_txsz ), + .ch17_adr0( ch17_adr0 ), + .ch17_adr1( ch17_adr1 ), + .ch17_am0( ch17_am0 ), + .ch17_am1( ch17_am1 ), + .pointer18( pointer18 ), + .pointer18_s( pointer18_s ), + .ch18_csr( ch18_csr ), + .ch18_txsz( ch18_txsz ), + .ch18_adr0( ch18_adr0 ), + .ch18_adr1( ch18_adr1 ), + .ch18_am0( ch18_am0 ), + .ch18_am1( ch18_am1 ), + .pointer19( pointer19 ), + .pointer19_s( pointer19_s ), + .ch19_csr( ch19_csr ), + .ch19_txsz( ch19_txsz ), + .ch19_adr0( ch19_adr0 ), + .ch19_adr1( ch19_adr1 ), + .ch19_am0( ch19_am0 ), + .ch19_am1( ch19_am1 ), + .pointer20( pointer20 ), + .pointer20_s( pointer20_s ), + .ch20_csr( ch20_csr ), + .ch20_txsz( ch20_txsz ), + .ch20_adr0( ch20_adr0 ), + .ch20_adr1( ch20_adr1 ), + .ch20_am0( ch20_am0 ), + .ch20_am1( ch20_am1 ), + .pointer21( pointer21 ), + .pointer21_s( pointer21_s ), + .ch21_csr( ch21_csr ), + .ch21_txsz( ch21_txsz ), + .ch21_adr0( ch21_adr0 ), + .ch21_adr1( ch21_adr1 ), + .ch21_am0( ch21_am0 ), + .ch21_am1( ch21_am1 ), + .pointer22( pointer22 ), + .pointer22_s( pointer22_s ), + .ch22_csr( ch22_csr ), + .ch22_txsz( ch22_txsz ), + .ch22_adr0( ch22_adr0 ), + .ch22_adr1( ch22_adr1 ), + .ch22_am0( ch22_am0 ), + .ch22_am1( ch22_am1 ), + .pointer23( pointer23 ), + .pointer23_s( pointer23_s ), + .ch23_csr( ch23_csr ), + .ch23_txsz( ch23_txsz ), + .ch23_adr0( ch23_adr0 ), + .ch23_adr1( ch23_adr1 ), + .ch23_am0( ch23_am0 ), + .ch23_am1( ch23_am1 ), + .pointer24( pointer24 ), + .pointer24_s( pointer24_s ), + .ch24_csr( ch24_csr ), + .ch24_txsz( ch24_txsz ), + .ch24_adr0( ch24_adr0 ), + .ch24_adr1( ch24_adr1 ), + .ch24_am0( ch24_am0 ), + .ch24_am1( ch24_am1 ), + .pointer25( pointer25 ), + .pointer25_s( pointer25_s ), + .ch25_csr( ch25_csr ), + .ch25_txsz( ch25_txsz ), + .ch25_adr0( ch25_adr0 ), + .ch25_adr1( ch25_adr1 ), + .ch25_am0( ch25_am0 ), + .ch25_am1( ch25_am1 ), + .pointer26( pointer26 ), + .pointer26_s( pointer26_s ), + .ch26_csr( ch26_csr ), + .ch26_txsz( ch26_txsz ), + .ch26_adr0( ch26_adr0 ), + .ch26_adr1( ch26_adr1 ), + .ch26_am0( ch26_am0 ), + .ch26_am1( ch26_am1 ), + .pointer27( pointer27 ), + .pointer27_s( pointer27_s ), + .ch27_csr( ch27_csr ), + .ch27_txsz( ch27_txsz ), + .ch27_adr0( ch27_adr0 ), + .ch27_adr1( ch27_adr1 ), + .ch27_am0( ch27_am0 ), + .ch27_am1( ch27_am1 ), + .pointer28( pointer28 ), + .pointer28_s( pointer28_s ), + .ch28_csr( ch28_csr ), + .ch28_txsz( ch28_txsz ), + .ch28_adr0( ch28_adr0 ), + .ch28_adr1( ch28_adr1 ), + .ch28_am0( ch28_am0 ), + .ch28_am1( ch28_am1 ), + .pointer29( pointer29 ), + .pointer29_s( pointer29_s ), + .ch29_csr( ch29_csr ), + .ch29_txsz( ch29_txsz ), + .ch29_adr0( ch29_adr0 ), + .ch29_adr1( ch29_adr1 ), + .ch29_am0( ch29_am0 ), + .ch29_am1( ch29_am1 ), + .pointer30( pointer30 ), + .pointer30_s( pointer30_s ), + .ch30_csr( ch30_csr ), + .ch30_txsz( ch30_txsz ), + .ch30_adr0( ch30_adr0 ), + .ch30_adr1( ch30_adr1 ), + .ch30_am0( ch30_am0 ), + .ch30_am1( ch30_am1 ), + + .ch_sel( ch_sel ), + .ndnr( ndnr ), + .de_start( de_start ), + .ndr( ndr ), + .csr( csr ), + .pointer( pointer ), + .txsz( txsz ), + .adr0( adr0 ), + .adr1( adr1 ), + .am0( am0 ), + .am1( am1 ), + .pointer_s( pointer_s ), + .next_ch( next_ch ), + .de_ack( de_ack ), + .dma_busy( dma_busy ) + ); + + +// DMA Engine +wb_dma_de u2( + .clk( clk_i ), + .rst( ~rst_i ), + .mast0_go( mast0_go ), + .mast0_we( mast0_we ), + .mast0_adr( mast0_adr ), + .mast0_din( mast0_dout ), + .mast0_dout( mast0_din ), + .mast0_err( mast0_err ), + .mast0_drdy( mast0_drdy ), + .mast0_wait( mast0_wait ), + .mast1_go( mast1_go ), + .mast1_we( mast1_we ), + .mast1_adr( mast1_adr ), + .mast1_din( mast1_dout ), + .mast1_dout( mast1_din ), + .mast1_err( mast1_err ), + .mast1_drdy( mast1_drdy ), + .mast1_wait( mast1_wait ), + .de_start( de_start ), + .nd( ndr ), + .csr( csr ), + .pointer( pointer ), + .pointer_s( pointer_s ), + .txsz( txsz ), + .adr0( adr0 ), + .adr1( adr1 ), + .am0( am0 ), + .am1( am1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .ptr_set( ptr_set ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .next_ch( next_ch ), + .de_ack( de_ack ), + .pause_req( pause_req ), + .paused( paused ), + .dma_abort( dma_abort ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ) + ); + +// Wishbone Interface 0 +wb_dma_wb_if #(rf_addr) u3( + .clk( clk_i ), + .rst( ~rst_i ), + .wbs_data_i( wb0s_data_i ), + .wbs_data_o( wb0s_data_o ), + .wb_addr_i( wb0_addr_i ), + .wb_sel_i( wb0_sel_i ), + .wb_we_i( wb0_we_i ), + .wb_cyc_i( wb0_cyc_i ), + .wb_stb_i( wb0_stb_i ), + .wb_ack_o( wb0_ack_o ), + .wb_err_o( wb0_err_o ), + .wb_rty_o( wb0_rty_o ), + .wbm_data_i( wb0m_data_i ), + .wbm_data_o( wb0m_data_o ), + .wb_addr_o( wb0_addr_o ), + .wb_sel_o( wb0_sel_o ), + .wb_we_o( wb0_we_o ), + .wb_cyc_o( wb0_cyc_o ), + .wb_stb_o( wb0_stb_o ), + .wb_ack_i( wb0_ack_i ), + .wb_err_i( wb0_err_i ), + .wb_rty_i( wb0_rty_i ), + .mast_go( mast0_go ), + .mast_we( mast0_we ), + .mast_adr( mast0_adr ), + .mast_din( mast0_din ), + .mast_dout( mast0_dout ), + .mast_err( mast0_err ), + .mast_drdy( mast0_drdy ), + .mast_wait( mast0_wait ), + .pt_sel_i( pt0_sel_i ), + .mast_pt_in( mast0_pt_in ), + .mast_pt_out( mast0_pt_out ), + .slv_adr( slv0_adr ), + .slv_din( slv0_din ), + .slv_dout( slv0_dout ), + .slv_re( slv0_re ), + .slv_we( slv0_we ), + .pt_sel_o( pt0_sel_o ), + .slv_pt_out( slv0_pt_out ), + .slv_pt_in( slv0_pt_in ) + ); + +// Wishbone Interface 1 +wb_dma_wb_if #(rf_addr) u4( + .clk( clk_i ), + .rst( ~rst_i ), + .wbs_data_i( wb1s_data_i ), + .wbs_data_o( wb1s_data_o ), + .wb_addr_i( wb1_addr_i ), + .wb_sel_i( wb1_sel_i ), + .wb_we_i( wb1_we_i ), + .wb_cyc_i( wb1_cyc_i ), + .wb_stb_i( wb1_stb_i ), + .wb_ack_o( wb1_ack_o ), + .wb_err_o( wb1_err_o ), + .wb_rty_o( wb1_rty_o ), + .wbm_data_i( wb1m_data_i ), + .wbm_data_o( wb1m_data_o ), + .wb_addr_o( wb1_addr_o ), + .wb_sel_o( wb1_sel_o ), + .wb_we_o( wb1_we_o ), + .wb_cyc_o( wb1_cyc_o ), + .wb_stb_o( wb1_stb_o ), + .wb_ack_i( wb1_ack_i ), + .wb_err_i( wb1_err_i ), + .wb_rty_i( wb1_rty_i ), + .mast_go( mast1_go ), + .mast_we( mast1_we ), + .mast_adr( mast1_adr ), + .mast_din( mast1_din ), + .mast_dout( mast1_dout ), + .mast_err( mast1_err ), + .mast_drdy( mast1_drdy ), + .mast_wait( mast1_wait ), + .pt_sel_i( pt1_sel_i ), + .mast_pt_in( mast1_pt_in ), + .mast_pt_out( mast1_pt_out ), + .slv_adr( slv1_adr ), + .slv_din( 32'h0 ), // Not Connected + .slv_dout( slv1_dout ), // Not Connected + .slv_re( slv1_re ), // Not Connected + .slv_we( slv1_we ), // Not Connected + .pt_sel_o( pt1_sel_o ), + .slv_pt_out( slv1_pt_out ), + .slv_pt_in( slv1_pt_in ) + ); + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_if.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_if.v new file mode 100644 index 000000000..4bc905d23 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_if.v @@ -0,0 +1,223 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_if.v,v 1.3 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_wb_if.v,v $ +// Revision 1.3 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.2 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:54 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_if(clk, rst, + + // Wishbone + wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + // Master + mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, + mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out, + + // Slave + slv_adr, slv_din, slv_dout, slv_re, slv_we, + pt_sel_o, slv_pt_out, slv_pt_in + + ); + +parameter rf_addr = 0; + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +// Slave Interface +input [31:0] wbs_data_i; +output [31:0] wbs_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// Master Interface +input [31:0] wbm_data_i; +output [31:0] wbm_data_o; +output [31:0] wb_addr_o; +output [3:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// -------------------------------------- +// MASTER INTERFACE +input mast_go; // Perform a Master Cycle (as long as this + // line is asserted) +input mast_we; // Read/Write +input [31:0] mast_adr; // Address for the transfer +input [31:0] mast_din; // Internal Input Data +output [31:0] mast_dout; // Internal Output Data +output mast_err; // Indicates an error has occurred + +output mast_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +input mast_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// Pass Through Interface +input pt_sel_i; // Pass Through Mode Selected +input [70:0] mast_pt_in; // Grouped WISHBONE inputs +output [34:0] mast_pt_out; // Grouped WISHBONE outputs + +// -------------------------------------- +// Slave INTERFACE + +// This is the register File Interface +output [31:0] slv_adr; // Slave Address +input [31:0] slv_din; // Slave Input Data +output [31:0] slv_dout; // Slave Output Data +output slv_re; // Slave Read Enable +output slv_we; // Slave Write Enable + +// Pass through Interface +output pt_sel_o; // Pass Through Mode Active +output [70:0] slv_pt_out; // Grouped WISHBONE out signals +input [34:0] slv_pt_in; // Grouped WISHBONE in signals + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +wb_dma_wb_mast u0( + .clk( clk ), + .rst( rst ), + .wb_data_i( wbs_data_i ), + .wb_data_o( wbs_data_o ), + .wb_addr_o( wb_addr_o ), + .wb_sel_o( wb_sel_o ), + .wb_we_o( wb_we_o ), + .wb_cyc_o( wb_cyc_o ), + .wb_stb_o( wb_stb_o ), + .wb_ack_i( wb_ack_i ), + .wb_err_i( wb_err_i ), + .wb_rty_i( wb_rty_i ), + .mast_go( mast_go ), + .mast_we( mast_we ), + .mast_adr( mast_adr ), + .mast_din( mast_din ), + .mast_dout( mast_dout ), + .mast_err( mast_err ), + .mast_drdy( mast_drdy ), + .mast_wait( mast_wait ), + .pt_sel( pt_sel_i ), + .mast_pt_in( mast_pt_in ), + .mast_pt_out( mast_pt_out ) + ); + + +wb_dma_wb_slv #(rf_addr) u1( + .clk( clk ), + .rst( rst ), + .wb_data_i( wbm_data_i ), + .wb_data_o( wbm_data_o ), + .wb_addr_i( wb_addr_i ), + .wb_sel_i( wb_sel_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( wb_ack_o ), + .wb_err_o( wb_err_o ), + .wb_rty_o( wb_rty_o ), + .slv_adr( slv_adr ), + .slv_din( slv_din ), + .slv_dout( slv_dout ), + .slv_re( slv_re ), + .slv_we( slv_we ), + .pt_sel( pt_sel_o ), + .slv_pt_out( slv_pt_out ), + .slv_pt_in( slv_pt_in ) + ); + + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_mast.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_mast.v new file mode 100644 index 000000000..fce62d23b --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_mast.v @@ -0,0 +1,170 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Master Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_mast.v,v 1.2 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_wb_mast.v,v $ +// Revision 1.2 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:05 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_mast(clk, rst, + + wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, + mast_drdy, mast_wait, + + pt_sel, mast_pt_in, mast_pt_out + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output [31:0] wb_addr_o; +output [3:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// -------------------------------------- +// INTERNAL DMA INTERFACE +input mast_go; // Perform a Master Cycle (as long as this + // line is asserted) +input mast_we; // Read/Write +input [31:0] mast_adr; // Address for the transfer +input [31:0] mast_din; // Internal Input Data +output [31:0] mast_dout; // Internal Output Data +output mast_err; // Indicates an error has occurred + +output mast_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +input mast_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// Pass Through Interface +input pt_sel; // Pass Through Mode Selected +input [70:0] mast_pt_in; // Grouped WISHBONE inputs +output [34:0] mast_pt_out; // Grouped WISHBONE outputs + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg mast_cyc, mast_stb; +reg mast_we_r; +reg [3:0] mast_be; +reg [31:0] mast_dout; + +//////////////////////////////////////////////////////////////////// +// +// Pass-Through Interface +// + +assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} = + pt_sel ? mast_pt_in : + {mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb}; + +assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i}; + +//////////////////////////////////////////////////////////////////// +// +// DMA Engine Interface +// + +always @(posedge clk) + if(wb_ack_i) mast_dout <= #1 wb_data_i; + +always @(posedge clk) + mast_be <= #1 4'hf; + +always @(posedge clk) + mast_we_r <= #1 mast_we; + +always @(posedge clk) + mast_cyc <= #1 mast_go; + +always @(posedge clk) + mast_stb <= #1 mast_go & !mast_wait; + +assign mast_drdy = wb_ack_i; +assign mast_err = wb_err_i; + +endmodule diff --git a/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_slv.v b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_slv.v new file mode 100644 index 000000000..b3f76e444 --- /dev/null +++ b/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/wb_dma_wb_slv.v @@ -0,0 +1,180 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Slave Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_slv.v,v 1.4 2002/02/01 01:54:45 rudi Exp $ +// +// $Date: 2002/02/01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_dma_wb_slv.v,v $ +// Revision 1.4 2002/02/01 01:54:45 rudi +// +// - Minor cleanup +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:59 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_slv(clk, rst, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + + // This is the register File Interface + slv_adr, slv_din, slv_dout, slv_re, slv_we, + + // Pass through Interface + pt_sel, slv_pt_out, slv_pt_in + + ); + +parameter rf_addr = 0; + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// This is the register File Interface +output [31:0] slv_adr; // Slave Address +input [31:0] slv_din; // Slave Input Data +output [31:0] slv_dout; // Slave Output Data +output slv_re; // Slave Read Enable +output slv_we; // Slave Write Enable + +// Pass through Interface +output pt_sel; // Pass Through Mode Active +output [70:0] slv_pt_out; // Grouped WISHBONE out signals +input [34:0] slv_pt_in; // Grouped WISHBONE in signals + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg slv_re, slv_we; +wire rf_sel; +reg rf_ack; +reg [31:0] slv_adr, slv_dout; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign rf_sel = `WDMA_REG_SEL ; + +//////////////////////////////////////////////////////////////////// +// +// Pass Through Logic +// + +//assign pt_sel = !rf_sel; +assign pt_sel = !rf_sel & wb_cyc_i; + +assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i}; +assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in : + {slv_din, rf_ack, 1'b0, 1'b0}; + +//////////////////////////////////////////////////////////////////// +// +// Register File Logic +// + +always @(posedge clk) + slv_adr <= #1 wb_addr_i; + +always @(posedge clk) + slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re; + +always @(posedge clk) + slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack; + +always @(posedge clk) + slv_dout <= #1 wb_data_i; + +always @(posedge clk) + rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v new file mode 100644 index 000000000..2e7d31076 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_16(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v new file mode 100644 index 000000000..b444bfa3a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_4(cout, sum, a, b, cin); +parameter size = 4; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v new file mode 100644 index 000000000..74a09005d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v @@ -0,0 +1,21 @@ +// Creating a scaleable adder + +module adder_6(cout, sum, a, b, cin); +parameter size = 6; /* declare a parameter. default required */ +output cout; +output [size-1:0] sum; // sum uses the size parameter +input cin; +input [size-1:0] a, b; // 'a' and 'b' use the size parameter + +assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v new file mode 100644 index 000000000..a34cfdc91 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v @@ -0,0 +1,49 @@ +///////////////////////////////////////// +// Functionality: Two 2-input AND with clocked +// and combinational outputs +// Each of which are controlled by different clocks +// Author: Xifan Tang +//////////////////////////////////////// + +`timescale 1ns / 1ps + +module and2_latch_2clock( + a0, + b0, + clk0, + a1, + b1, + clk1, + c0, + d0, + c1, + d1); + +input wire clk0; + +input wire a0; +input wire b0; +output wire c0; +output reg d0; + +input wire clk1; + +input wire a1; +input wire b1; +output wire c1; +output reg d1; + + +assign c0 = a0 & b0; + +always @(posedge clk0) begin + d0 <= c0; +end + +assign c1 = a1 & b1; + +always @(posedge clk1) begin + d1 <= c1; +end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v b/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v new file mode 100644 index 000000000..4b71607f6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and4/and4.v @@ -0,0 +1,22 @@ +///////////////////////////////////////// +// Functionality: 4-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and4( + a, + b, + c, + d, + e); + +input wire a; +input wire b; +input wire c; +input wire d; +output wire e; + +assign e = a & b & c & d; + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/blinking/blinking.v b/openfpga_flow/benchmarks/micro_benchmark/blinking/blinking.v new file mode 100644 index 000000000..b8587055c --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/blinking/blinking.v @@ -0,0 +1,17 @@ +// ------------------------------ +// Design Name: Blinking +// Functionality: 1-bit blinking +// ------------------------------ +module blinking( + clk, + out +); + +input clk; +output out; + + always @(posedge clk) begin + out = ~out; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v new file mode 100644 index 000000000..69a92ff92 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/config_loader/bitstream_loader.v @@ -0,0 +1,114 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 09:43:10 AM +// Design Name: +// Module Name: bitstream_loader +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module bitstream_loader( + input prog_clk, + input start, + output config_chain_head, + output reg done + ); + + parameter BITSTREAM_FILE=""; + parameter BITSTREAM_SIZE=6140; + + reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index; + + reg [13:0] bram_addr; + reg [3:0] bram_line_index; + + wire bram_output; + assign config_chain_head = bram_output; + + EFX_RAM_5K #( + .READ_WIDTH(1), + .WRITE_WIDTH(0), + + .INIT_0(256'h00000000000000000000000000000000000000000000007f00000000000000ff), + .INIT_1(256'h0000fff8ffffffff000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h00000003f8000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000078000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000), + ) + EFX_RAM_5K_inst ( + // Port A Data: 16-bit (each) output: Port A data + .WDATA(0), // Write data + .WADDR(0), // Write address + .WE(0), // Write enable + + .WCLK(0), + .WCLKE(0), + + .RDATA(bram_output), + .RADDR(bram_addr), + .RE(1'b1), + .RCLK(prog_clk) + ); + + + initial begin + bram_addr <= 0; + bram_line_index <= 0; + bitstream_index <= 0; + done <= 1'b0; + end + + always @(posedge prog_clk) begin + if (start && !done) begin + + bram_addr <= bram_addr + 1; + bitstream_index <= bitstream_index + 1; + end + if (bitstream_index == BITSTREAM_SIZE) begin + done <= 1'b1; + end + end + + +endmodule + + + + + + + + + \ No newline at end of file diff --git a/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v b/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v new file mode 100644 index 000000000..e3c20c2c1 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/config_loader/configuration_manager.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/05/2021 10:29:55 AM +// Design Name: +// Module Name: configuration_manager +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "clock_divider.v" +`include "pulse_generator.v" + +module configuration_manager( + input clk_in, + output prog_reset, + output prog_clk, + output ccff_head, + output configuration_done + ); + + parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk + parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times + + wire prog_clk_out; // prog_clk signal from clk_divider + wire ccff_head_out; + + assign ccff_head = ccff_head_out & ~prog_reset; + assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done + + // PRESET + // Programming reset will be enabled until START_CYCLE + reset_generator #( + .INITIAL_VALUE(1), + .ACTIVE_CYCLES(START_CYCLE) + ) prog_reset_generator( + .clk(~prog_clk), + .pulse(prog_reset) + ); + + + // PROG_CLK + // Divide pl_clk (50MHz) by 4096 (2^12) times + clock_divider #( + .CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE) + ) prog_clk_divider ( + .clk_in(clk_in), + .clk_out(prog_clk_out) + ); + + + // Instantiate bitstream loader + bitstream_loader loader ( + .prog_clk(prog_clk), + .config_chain_head(ccff_head_out), + .start(~prog_reset), + .done(configuration_done) + ); + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act deleted file mode 100644 index e0e56d449..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act +++ /dev/null @@ -1,22 +0,0 @@ -clk0 0.505000 0.204400 -rst0 0.491000 0.206000 -clk1 0.472000 0.204400 -rst1 0.501400 0.204600 -q1[0] 0.278800 0.557400 -q1[1] 0.240600 0.268800 -q1[2] 0.178200 0.120000 -q1[3] 0.098400 0.041600 -q0[0] 0.283400 0.566600 -q0[1] 0.246800 0.272000 -q0[2] 0.181000 0.122200 -q0[3] 0.093200 0.048800 -n34 0.178200 0.068356 -n38 0.098400 0.002698 -$abc$226$new_n22_ 0.880800 0.004943 -n42 0.283400 0.129291 -n46 0.246800 0.084119 -n50 0.181000 0.067113 -n54 0.093200 0.002644 -$abc$226$new_n27_ 0.883200 0.005398 -n26 0.278800 0.038636 -n30 0.240600 0.082416 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif deleted file mode 100644 index 0ae3c95a7..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif +++ /dev/null @@ -1,48 +0,0 @@ -# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021 -.model counter4bit_2clock -.inputs clk0 rst0 clk1 rst1 -.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \ -q1[2] q1[3] - -.latch n26 q1[0] re clk1 2 -.latch n30 q1[1] re clk1 2 -.latch n34 q1[2] re clk1 2 -.latch n38 q1[3] re clk1 2 -.latch n42 q0[0] re clk0 2 -.latch n46 q0[1] re clk0 2 -.latch n50 q0[2] re clk0 2 -.latch n54 q0[3] re clk0 2 - -.names q1[0] q1[1] rst1 q1[2] n34 --001 1 -0-01 1 -1100 1 -.names rst1 $abc$226$new_n22_ n38 -00 1 -.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names rst0 q0[0] n42 -00 1 -.names rst0 q0[1] q0[0] n46 -001 1 -010 1 -.names q0[1] q0[0] rst0 q0[2] n50 --001 1 -0-01 1 -1100 1 -.names rst0 $abc$226$new_n27_ n54 -00 1 -.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names q1[0] rst1 n26 -00 1 -.names rst1 q1[0] q1[1] n30 -001 1 -010 1 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v deleted file mode 100644 index 2b14fc540..000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v +++ /dev/null @@ -1,60 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */ - -module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] ); - wire _00_; - wire _01_; - input clk0; - input clk1; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - wire n54; - output \q0[0] ; - reg \q0[0] ; - output \q0[1] ; - reg \q0[1] ; - output \q0[2] ; - reg \q0[2] ; - output \q0[3] ; - reg \q0[3] ; - output \q1[0] ; - reg \q1[0] ; - output \q1[1] ; - reg \q1[1] ; - output \q1[2] ; - reg \q1[2] ; - output \q1[3] ; - reg \q1[3] ; - input rst0; - input rst1; - always @(posedge clk1) - \q1[0] <= n26; - always @(posedge clk1) - \q1[1] <= n30; - always @(posedge clk1) - \q1[2] <= n34; - always @(posedge clk1) - \q1[3] <= n38; - always @(posedge clk1) - \q0[0] <= n42; - always @(posedge clk1) - \q0[1] <= n46; - always @(posedge clk1) - \q0[2] <= n50; - always @(posedge clk1) - \q0[3] <= n54; - assign n38 = 4'h1 >> { _00_, rst1 }; - assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2] }; - assign n42 = 4'h1 >> { \q0[0] , rst0 }; - assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 }; - assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1] }; - assign n54 = 4'h1 >> { _01_, rst0 }; - assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2] }; - assign n26 = 4'h1 >> { rst1, \q1[0] }; - assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 }; - assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0] }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v new file mode 100644 index 000000000..4a3542eec --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + reset, + result +); + + input clk; + input reset; + output [127:0] result; + + reg [127:0] result; + + always @(posedge clk or posedge reset) + begin + if (reset) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v new file mode 100644 index 000000000..4d11e9e0b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, reset; + wire [127:0] result; + + counter DUT( + .clk(clk), + .reset(reset), + .result(result) + ); + + initial begin + #0 reset = 1'b1; clk = 1'b0; + #100 reset = 1'b0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v new file mode 100644 index 000000000..628ec4c08 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input resetb; + output [127:0] result; + + reg [127:0] result; + + always @(posedge clk or negedge resetb) + begin + if (~resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v new file mode 100644 index 000000000..c96557b4e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [127:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 reset = 1'b0; clk = 1'b0; + #100 reset = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v similarity index 85% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index 93f7dc07b..c1b5f2ee6 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -1,4 +1,4 @@ -module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); +module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); input clk0; input rst0; diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v similarity index 75% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v index 880b99088..9150f55b9 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v @@ -1,4 +1,4 @@ -module counter4bit_2clock_tb; +module counter_4bit_2clock_tb; reg clk0, rst0; wire [3:0] q0; @@ -6,12 +6,12 @@ module counter4bit_2clock_tb; reg clk1, rst1; wire [3:0] q1; - counter_2clock C_1( + counter_4bit_2clock C_1( clk0, q0, rst0); - counter_2clock C_1( + counter_4bit_2clock C_1( clk1, q1, rst1); diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v new file mode 100644 index 000000000..685b77577 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + reset, + result +); + + input clk; + input reset; + output [7:0] result; + + reg [7:0] result; + + always @(posedge clk or posedge reset) + begin + if (reset) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v new file mode 100644 index 000000000..93697ba6e --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, reset; + wire [7:0] result; + + counter DUT( + .clk(clk), + .reset(reset), + .result(result) + ); + + initial begin + #0 reset = 1'b1; clk = 1'b0; + #100 reset = 1'b0; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v new file mode 100644 index 000000000..3d929091d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input resetb; + output [7:0] result; + + reg [7:0] result; + + always @(posedge clk or negedge resetb) + begin + if (!resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v new file mode 100644 index 000000000..8813aa0c4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [7:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 resetb = 1'b0; clk = 1'b0; + #100 resetb = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_16k/dual_port_ram_16k.v b/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_16k/dual_port_ram_16k.v new file mode 100644 index 000000000..60f165ab0 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_16k/dual_port_ram_16k.v @@ -0,0 +1,58 @@ +//----------------------------------------------------- +// Design Name : dual_port_ram_16k +// File Name : dual_port_ram_16k.v +// Function : Dual port RAM 2048x8bit +// Coder : Xifan Tang +//----------------------------------------------------- + +module dual_port_ram_16k ( + input clk, + input wen, + input ren, + input [10:0] waddr, + input [10:0] raddr, + input [7:0] din, + output [7:0] dout +); + + dual_port_sram_16kb memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (din), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (dout) ); + +endmodule + +module dual_port_sram_16kb ( + input wclk, + input wen, + input [10:0] waddr, + input [7:0] data_in, + input rclk, + input ren, + input [10:0] raddr, + output [7:0] data_out +); + + reg [7:0] ram[2047:0]; + reg [7:0] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v b/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v new file mode 100644 index 000000000..c8bcc4e58 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v @@ -0,0 +1,58 @@ +//----------------------------------------------------- +// Design Name : dual_port_ram_1k +// File Name : dual_port_ram_1k.v +// Function : Dual port RAM 128x8bit +// Coder : Xifan Tang +//----------------------------------------------------- + +module dual_port_ram_1k ( + input clk, + input wen, + input ren, + input [6:0] waddr, + input [6:0] raddr, + input [7:0] din, + output [7:0] dout +); + + dual_port_sram_1kb memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (din), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (dout) ); + +endmodule + +module dual_port_sram_1kb ( + input wclk, + input wen, + input [6:0] waddr, + input [7:0] data_in, + input rclk, + input ren, + input [6:0] raddr, + output [7:0] data_out +); + + reg [7:0] ram[127:0]; + reg [7:0] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v b/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v new file mode 100644 index 000000000..65dc95d11 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v @@ -0,0 +1,97 @@ +// FIFO buffer implemented with synchronous dual-port block ram +// Reference: +// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/ +module fifo + #( parameter ADDRESS_WIDTH = 4, // number of words in ram + DATA_WIDTH = 4 // number of bits in word + ) + + // IO ports + ( + input wire clk, reset, + input wire read, write, + input wire [DATA_WIDTH-1:0] write_data, + output wire empty, full, + output wire [DATA_WIDTH-1:0] read_data + ); + + // internal signal declarations + reg [ADDRESS_WIDTH-1:0] write_address_reg, write_address_next, write_address_after; + reg [ADDRESS_WIDTH-1:0] read_address_reg, read_address_next, read_address_after; + reg full_reg, empty_reg, full_next, empty_next; + wire write_en; + + // write enable is asserted when write input is asserted and FIFO isn't full + assign write_en = write & ~full_reg; + + // instantiate synchronous block ram + sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram + (.clk(clk), .write_en(write_en), .write_address(write_address_reg), + .read_address(read_address_reg), .write_data_in(write_data), + .write_data_out(), .read_data_out(read_data)); + + // register for address pointers, full/empty status + always @(posedge clk, posedge reset) + if (reset) + begin + write_address_reg <= 0; + read_address_reg <= 0; + full_reg <= 1'b0; + empty_reg <= 1'b1; + end + else + begin + write_address_reg <= write_address_next; + read_address_reg <= read_address_next; + full_reg <= full_next; + empty_reg <= empty_next; + end + + // next-state logic for address index values after read/write operations + always @* + begin + write_address_after = write_address_reg + 1; + read_address_after = read_address_reg + 1; + end + + // next-state logic for address pointers + always @* + begin + // defaults + write_address_next = write_address_reg; + read_address_next = read_address_reg; + full_next = full_reg; + empty_next = empty_reg; + + // if read input asserted and FIFO isn't empty + if(read && ~empty_reg && ~write) + begin + read_address_next = read_address_after; // read address moves forward + full_next = 1'b0; // FIFO isn't full if a read occured + + if (read_address_after == write_address_reg) // if read address caught up with write address, + empty_next = 1'b1; // FIFO is empty + end + + // if write input asserted and FIFO isn't full + else if(write && ~full_reg && ~read) + begin + write_address_next = write_address_after; // write address moves forward + empty_next = 1'b0; // FIFO isn't empty if write occured + + if (write_address_after == read_address_reg) // if write address caught up with read address + full_next = 1'b1; // FIFO is full + end + + // if write and read are asserted + else if(write && read) + begin + write_address_next = write_address_after; // write address moves forward + read_address_next = read_address_after; // read address moves forward + end + end + + // assign full/empty status to output ports + assign full = full_reg; + assign empty = empty_reg; +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/sync_dual_port_ram.v b/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/sync_dual_port_ram.v new file mode 100644 index 000000000..bd1de2b4b --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/sync_dual_port_ram.v @@ -0,0 +1,35 @@ +// Synchronous dual-port block ram +// Reference: +// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/ +module sync_dual_port_ram + #( parameter ADDRESS_WIDTH = 4, // number of words in ram + DATA_WIDTH = 4 // number of bits in word + ) + + // IO ports + ( + input wire clk, // clk for synchronous read/write + input wire write_en, // signal to enable synchronous write + input wire [ADDRESS_WIDTH-1:0] read_address, write_address, // inputs for dual port addresses + input wire [DATA_WIDTH-1:0] write_data_in, // input for data to write to ram + output wire [DATA_WIDTH-1:0] read_data_out, write_data_out // outputs for dual data ports + ); + + // internal signal declarations + reg [DATA_WIDTH-1:0] ram [2**ADDRESS_WIDTH-1:0]; // ADDRESS_WIDTH x DATA_WIDTH RAM declaration + reg [ADDRESS_WIDTH-1:0] read_address_reg, write_address_reg; // dual port address declarations + + // synchronous write and address update + always @(posedge clk) + begin + if (write_en) // if write enabled + ram[write_address] <= write_data_in; // write data to ram and write_address + + read_address_reg <= read_address; // store read_address to reg + write_address_reg <= write_address; // store write_address to reg + end + + // assignments for two data out ports + assign read_data_out = ram[read_address_reg]; + assign write_data_out = ram[write_address_reg]; +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v new file mode 100644 index 000000000..ccbade6c0 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 12-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_12(a, b, c, out); +parameter DATA_WIDTH = 12; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v new file mode 100644 index 000000000..3fc2270e5 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 16-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_16(a, b, c, out); +parameter DATA_WIDTH = 16; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v new file mode 100644 index 000000000..74a935e8d --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 18-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_18(a, b, c, out); +parameter DATA_WIDTH = 18; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v new file mode 100644 index 000000000..457a94deb --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 2-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_2(a, b, c, out); +parameter DATA_WIDTH = 2; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v new file mode 100644 index 000000000..f7be3eff9 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 20-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_20(a, b, c, out); +parameter DATA_WIDTH = 20; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_32/mac_32.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_32/mac_32.v new file mode 100644 index 000000000..e22fd596c --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_32/mac_32.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 32-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_32(a, b, c, out); +parameter DATA_WIDTH = 32; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v new file mode 100644 index 000000000..669bc4747 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 36-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_36(a, b, c, out); +parameter DATA_WIDTH = 4; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v new file mode 100644 index 000000000..c07495eb5 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 4-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_4(a, b, c, out); +parameter DATA_WIDTH = 4; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v new file mode 100644 index 000000000..1909c2d30 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 6-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_6(a, b, c, out); +parameter DATA_WIDTH = 6; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v new file mode 100644 index 000000000..8175f6ca6 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 8-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_8(a, b, c, out); +parameter DATA_WIDTH = 8; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v new file mode 100644 index 000000000..05df02fac --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v @@ -0,0 +1,25 @@ +//------------------------------------------------------- +// Functionality: +// - A 8-bit multiply-acculumate circuit +// - A 9-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_8_9(a, b, c, out); +parameter DATA_WIDTH = 18; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out[8:0] = a[8:0] * b[8:0] + c[8:0]; +assign out[17:9] = a[17:9] * b[17:9] + c[17:9]; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v new file mode 100644 index 000000000..664df33f4 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v @@ -0,0 +1,22 @@ +//------------------------------------------------------- +// Functionality: A 9-bit multiply-acculumate circuit +// Author: Xifan Tang +//------------------------------------------------------- + +module mac_9(a, b, c, out); +parameter DATA_WIDTH = 9; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b, c; +output [DATA_WIDTH - 1 : 0] out; + +assign out = a * b + c; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act b/openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.act similarity index 100% rename from openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act rename to openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.act diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif b/openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.blif similarity index 100% rename from openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif rename to openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.blif diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v b/openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.v similarity index 100% rename from openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v rename to openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder.v diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v b/openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v similarity index 100% rename from openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/pipelined_8bit_adder/pipelined_8bit_adder_formal_random_top_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v new file mode 100644 index 000000000..3cb3f9899 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -0,0 +1,50 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:25:29 PM +// Design Name: +// Module Name: clk_divider +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + +module clock_divider ( + input clk_in, + output reg clk_out + ); + + parameter CLK_DIVIDER_SIZE=8; + + reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; + +`ifdef VIVADO_SYNTHESIS + initial begin + clkdiv_counter <= 0; + clk_out <= 0; + end +`endif + + // Divide pl_clk (50MHz) to 1MHz + always @(posedge clk_in) begin + if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin + clk_out <= ~clk_out; + end + clkdiv_counter <= clkdiv_counter +1; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v new file mode 100644 index 000000000..1f092e6a0 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -0,0 +1,82 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 03:37:44 PM +// Design Name: +// Module Name: pulse_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: A simple pulse generator with configurable initial values and waiting cycles +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + +module pulse_generator( + input clk_in, + input repeated, // Specify if the pulse should be generated repeatedly + output reg pulse + ); + + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + parameter PULSE_WIDTH=1; // Define the length of the pulse width + parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter + + reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES + reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter; + reg pulse_start; + reg pulse_end; + +`ifdef VIVADO_SYNTHESIS + initial begin + pulse <= INITIAL_VALUE; + pulse_start <= 1'b0; + pulse_end <= 1'b0; + wait_cycle_counter <= 0; + pulse_width_counter <= 0; + end +`endif + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + if (wait_cycle_counter == WAIT_CYCLES) begin + pulse_start <= 1'b1; + end + if (~pulse_start) begin + wait_cycle_counter <= wait_cycle_counter + 1; + end + end + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk_in) begin + pulse <= INITIAL_VALUE; + if (pulse_start && ~pulse_end) begin + // Reach the pulse width limit, stop counting + if (pulse_width_counter < PULSE_WIDTH) begin + pulse <= ~INITIAL_VALUE; + if (~repeated) begin + pulse_end = 1'b1; + end + end + // When pulse ends, flip to initial value + if (pulse_end) begin + pulse <= INITIAL_VALUE; + end + pulse_width_counter <= pulse_width_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v new file mode 100644 index 000000000..bbb73e440 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v @@ -0,0 +1,53 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05/03/2021 04:52:18 PM +// Design Name: +// Module Name: reset_generator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +// Uncomment if using Vivado to synthesize the design. This will enable the initial block +// If using Yosys, initial blocks are not supported, and cannot be included. +// `define VIVADO_SYNTHESIS + +module reset_generator( + input clk, + output reg pulse + ); + + parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value + parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied + + reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter; + +`ifdef VIVADO_SYNTHESIS + initial begin + clkdiv_counter <= 0; + active_cycle_counter <= 0; + pulse <= INITIAL_VALUE; + end +`endif + + // Wait a number of clock cycles, hold the initial value + always @(posedge clk) begin + if (active_cycle_counter == ACTIVE_CYCLES) begin + pulse <= ~pulse; + end else begin + active_cycle_counter <= active_cycle_counter + 1; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.act similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.act diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.blif similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.blif diff --git a/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.v similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k4_N4/K4N4_test_modes.v diff --git a/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.act similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.act diff --git a/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.blif similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.blif diff --git a/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v b/openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.v similarity index 100% rename from openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v rename to openfpga_flow/benchmarks/micro_benchmark/test_modes/k6_N10/K6N10_test_modes.v diff --git a/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v b/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v new file mode 100644 index 000000000..bd86b9bcc --- /dev/null +++ b/openfpga_flow/benchmarks/quicklogic_tests/shift_reg_8192/rtl/shift_reg_8192.v @@ -0,0 +1,24 @@ +//-----------------------------------------------------// +// Design Name : Shift_reg +// File Name : Shift_reg_8192.v +// Function : Shift register +//------------------------------------------------------// + + +module shift_reg_8192 #( parameter size = 8191 ) (shift_in, clk, shift_out); + + // Port Declaration + input shift_in; + input clk; + output shift_out; + + reg [ size:0 ] shift; // shift register + + always @ (posedge clk) + begin + shift = { shift[size-1:0] , shift_in } ; + end + + assign shift_out = shift[size]; + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v new file mode 100755 index 000000000..c42c26267 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v @@ -0,0 +1,5709 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0111 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 12'b010000000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 4'b0111 + +module LU32PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 8'b01000000 +`define BLOCKN 8'b01000000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 7'b0100000 +`define MEMBLOCKN 7'b0100000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0111 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 4'b0111 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 7'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 7'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 7'b0; + ram_addr <= 7'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>6)<<5; + mem_N <= Ndivk<<6; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 7 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 7'b0100000 +`define PEWIDTH 4'b0101 +`define BLOCKWIDTH 4'b0111 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define TOPSIZEWIDTH 5'b01100 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multA8; +wire[`PRECISION-1:0] multA9; +wire[`PRECISION-1:0] multA10; +wire[`PRECISION-1:0] multA11; +wire[`PRECISION-1:0] multA12; +wire[`PRECISION-1:0] multA13; +wire[`PRECISION-1:0] multA14; +wire[`PRECISION-1:0] multA15; +wire[`PRECISION-1:0] multA16; +wire[`PRECISION-1:0] multA17; +wire[`PRECISION-1:0] multA18; +wire[`PRECISION-1:0] multA19; +wire[`PRECISION-1:0] multA20; +wire[`PRECISION-1:0] multA21; +wire[`PRECISION-1:0] multA22; +wire[`PRECISION-1:0] multA23; +wire[`PRECISION-1:0] multA24; +wire[`PRECISION-1:0] multA25; +wire[`PRECISION-1:0] multA26; +wire[`PRECISION-1:0] multA27; +wire[`PRECISION-1:0] multA28; +wire[`PRECISION-1:0] multA29; +wire[`PRECISION-1:0] multA30; +wire[`PRECISION-1:0] multA31; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] multResult8; +wire[`PRECISION-1:0] multResult9; +wire[`PRECISION-1:0] multResult10; +wire[`PRECISION-1:0] multResult11; +wire[`PRECISION-1:0] multResult12; +wire[`PRECISION-1:0] multResult13; +wire[`PRECISION-1:0] multResult14; +wire[`PRECISION-1:0] multResult15; +wire[`PRECISION-1:0] multResult16; +wire[`PRECISION-1:0] multResult17; +wire[`PRECISION-1:0] multResult18; +wire[`PRECISION-1:0] multResult19; +wire[`PRECISION-1:0] multResult20; +wire[`PRECISION-1:0] multResult21; +wire[`PRECISION-1:0] multResult22; +wire[`PRECISION-1:0] multResult23; +wire[`PRECISION-1:0] multResult24; +wire[`PRECISION-1:0] multResult25; +wire[`PRECISION-1:0] multResult26; +wire[`PRECISION-1:0] multResult27; +wire[`PRECISION-1:0] multResult28; +wire[`PRECISION-1:0] multResult29; +wire[`PRECISION-1:0] multResult30; +wire[`PRECISION-1:0] multResult31; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addA8; +wire[`PRECISION-1:0] addA9; +wire[`PRECISION-1:0] addA10; +wire[`PRECISION-1:0] addA11; +wire[`PRECISION-1:0] addA12; +wire[`PRECISION-1:0] addA13; +wire[`PRECISION-1:0] addA14; +wire[`PRECISION-1:0] addA15; +wire[`PRECISION-1:0] addA16; +wire[`PRECISION-1:0] addA17; +wire[`PRECISION-1:0] addA18; +wire[`PRECISION-1:0] addA19; +wire[`PRECISION-1:0] addA20; +wire[`PRECISION-1:0] addA21; +wire[`PRECISION-1:0] addA22; +wire[`PRECISION-1:0] addA23; +wire[`PRECISION-1:0] addA24; +wire[`PRECISION-1:0] addA25; +wire[`PRECISION-1:0] addA26; +wire[`PRECISION-1:0] addA27; +wire[`PRECISION-1:0] addA28; +wire[`PRECISION-1:0] addA29; +wire[`PRECISION-1:0] addA30; +wire[`PRECISION-1:0] addA31; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`PRECISION-1:0] addResult8; +wire[`PRECISION-1:0] addResult9; +wire[`PRECISION-1:0] addResult10; +wire[`PRECISION-1:0] addResult11; +wire[`PRECISION-1:0] addResult12; +wire[`PRECISION-1:0] addResult13; +wire[`PRECISION-1:0] addResult14; +wire[`PRECISION-1:0] addResult15; +wire[`PRECISION-1:0] addResult16; +wire[`PRECISION-1:0] addResult17; +wire[`PRECISION-1:0] addResult18; +wire[`PRECISION-1:0] addResult19; +wire[`PRECISION-1:0] addResult20; +wire[`PRECISION-1:0] addResult21; +wire[`PRECISION-1:0] addResult22; +wire[`PRECISION-1:0] addResult23; +wire[`PRECISION-1:0] addResult24; +wire[`PRECISION-1:0] addResult25; +wire[`PRECISION-1:0] addResult26; +wire[`PRECISION-1:0] addResult27; +wire[`PRECISION-1:0] addResult28; +wire[`PRECISION-1:0] addResult29; +wire[`PRECISION-1:0] addResult30; +wire[`PRECISION-1:0] addResult31; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); +mult_add PE8 (clk, multA8, multOperand, addA8, multResult8, addResult8); +mult_add PE9 (clk, multA9, multOperand, addA9, multResult9, addResult9); +mult_add PE10 (clk, multA10, multOperand, addA10, multResult10, addResult10); +mult_add PE11 (clk, multA11, multOperand, addA11, multResult11, addResult11); +mult_add PE12 (clk, multA12, multOperand, addA12, multResult12, addResult12); +mult_add PE13 (clk, multA13, multOperand, addA13, multResult13, addResult13); +mult_add PE14 (clk, multA14, multOperand, addA14, multResult14, addResult14); +mult_add PE15 (clk, multA15, multOperand, addA15, multResult15, addResult15); +mult_add PE16 (clk, multA16, multOperand, addA16, multResult16, addResult16); +mult_add PE17 (clk, multA17, multOperand, addA17, multResult17, addResult17); +mult_add PE18 (clk, multA18, multOperand, addA18, multResult18, addResult18); +mult_add PE19 (clk, multA19, multOperand, addA19, multResult19, addResult19); +mult_add PE20 (clk, multA20, multOperand, addA20, multResult20, addResult20); +mult_add PE21 (clk, multA21, multOperand, addA21, multResult21, addResult21); +mult_add PE22 (clk, multA22, multOperand, addA22, multResult22, addResult22); +mult_add PE23 (clk, multA23, multOperand, addA23, multResult23, addResult23); +mult_add PE24 (clk, multA24, multOperand, addA24, multResult24, addResult24); +mult_add PE25 (clk, multA25, multOperand, addA25, multResult25, addResult25); +mult_add PE26 (clk, multA26, multOperand, addA26, multResult26, addResult26); +mult_add PE27 (clk, multA27, multOperand, addA27, multResult27, addResult27); +mult_add PE28 (clk, multA28, multOperand, addA28, multResult28, addResult28); +mult_add PE29 (clk, multA29, multOperand, addA29, multResult29, addResult29); +mult_add PE30 (clk, multA30, multOperand, addA30, multResult30, addResult30); +mult_add PE31 (clk, multA31, multOperand, addA31, multResult31, addResult31); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[1023:992]; + 1: + topWriteDataLU = curReadDataLU[991:960]; + 2: + topWriteDataLU = curReadDataLU[959:928]; + 3: + topWriteDataLU = curReadDataLU[927:896]; + 4: + topWriteDataLU = curReadDataLU[895:864]; + 5: + topWriteDataLU = curReadDataLU[863:832]; + 6: + topWriteDataLU = curReadDataLU[831:800]; + 7: + topWriteDataLU = curReadDataLU[799:768]; + 8: + topWriteDataLU = curReadDataLU[767:736]; + 9: + topWriteDataLU = curReadDataLU[735:704]; + 10: + topWriteDataLU = curReadDataLU[703:672]; + 11: + topWriteDataLU = curReadDataLU[671:640]; + 12: + topWriteDataLU = curReadDataLU[639:608]; + 13: + topWriteDataLU = curReadDataLU[607:576]; + 14: + topWriteDataLU = curReadDataLU[575:544]; + 15: + topWriteDataLU = curReadDataLU[543:512]; + 16: + topWriteDataLU = curReadDataLU[511:480]; + 17: + topWriteDataLU = curReadDataLU[479:448]; + 18: + topWriteDataLU = curReadDataLU[447:416]; + 19: + topWriteDataLU = curReadDataLU[415:384]; + 20: + topWriteDataLU = curReadDataLU[383:352]; + 21: + topWriteDataLU = curReadDataLU[351:320]; + 22: + topWriteDataLU = curReadDataLU[319:288]; + 23: + topWriteDataLU = curReadDataLU[287:256]; + 24: + topWriteDataLU = curReadDataLU[255:224]; + 25: + topWriteDataLU = curReadDataLU[223:192]; + 26: + topWriteDataLU = curReadDataLU[191:160]; + 27: + topWriteDataLU = curReadDataLU[159:128]; + 28: + topWriteDataLU = curReadDataLU[127:96]; + 29: + topWriteDataLU = curReadDataLU[95:64]; + 30: + topWriteDataLU = curReadDataLU[63:32]; + 31: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult31; + 1: + topWriteDataLU = addResult30; + 2: + topWriteDataLU = addResult29; + 3: + topWriteDataLU = addResult28; + 4: + topWriteDataLU = addResult27; + 5: + topWriteDataLU = addResult26; + 6: + topWriteDataLU = addResult25; + 7: + topWriteDataLU = addResult24; + 8: + topWriteDataLU = addResult23; + 9: + topWriteDataLU = addResult22; + 10: + topWriteDataLU = addResult21; + 11: + topWriteDataLU = addResult20; + 12: + topWriteDataLU = addResult19; + 13: + topWriteDataLU = addResult18; + 14: + topWriteDataLU = addResult17; + 15: + topWriteDataLU = addResult16; + 16: + topWriteDataLU = addResult15; + 17: + topWriteDataLU = addResult14; + 18: + topWriteDataLU = addResult13; + 19: + topWriteDataLU = addResult12; + 20: + topWriteDataLU = addResult11; + 21: + topWriteDataLU = addResult10; + 22: + topWriteDataLU = addResult9; + 23: + topWriteDataLU = addResult8; + 24: + topWriteDataLU = addResult7; + 25: + topWriteDataLU = addResult6; + 26: + topWriteDataLU = addResult5; + 27: + topWriteDataLU = addResult4; + 28: + topWriteDataLU = addResult3; + 29: + topWriteDataLU = addResult2; + 30: + topWriteDataLU = addResult1; + 31: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; +assign multA8 = leftReadDataLU[287:256]; +assign multA9 = leftReadDataLU[319:288]; +assign multA10 = leftReadDataLU[351:320]; +assign multA11 = leftReadDataLU[383:352]; +assign multA12 = leftReadDataLU[415:384]; +assign multA13 = leftReadDataLU[447:416]; +assign multA14 = leftReadDataLU[479:448]; +assign multA15 = leftReadDataLU[511:480]; +assign multA16 = leftReadDataLU[543:512]; +assign multA17 = leftReadDataLU[575:544]; +assign multA18 = leftReadDataLU[607:576]; +assign multA19 = leftReadDataLU[639:608]; +assign multA20 = leftReadDataLU[671:640]; +assign multA21 = leftReadDataLU[703:672]; +assign multA22 = leftReadDataLU[735:704]; +assign multA23 = leftReadDataLU[767:736]; +assign multA24 = leftReadDataLU[799:768]; +assign multA25 = leftReadDataLU[831:800]; +assign multA26 = leftReadDataLU[863:832]; +assign multA27 = leftReadDataLU[895:864]; +assign multA28 = leftReadDataLU[927:896]; +assign multA29 = leftReadDataLU[959:928]; +assign multA30 = leftReadDataLU[991:960]; +assign multA31 = leftReadDataLU[1023:992]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; +assign addA8 = curReadDataLU[287:256]; +assign addA9 = curReadDataLU[319:288]; +assign addA10 = curReadDataLU[351:320]; +assign addA11 = curReadDataLU[383:352]; +assign addA12 = curReadDataLU[415:384]; +assign addA13 = curReadDataLU[447:416]; +assign addA14 = curReadDataLU[479:448]; +assign addA15 = curReadDataLU[511:480]; +assign addA16 = curReadDataLU[543:512]; +assign addA17 = curReadDataLU[575:544]; +assign addA18 = curReadDataLU[607:576]; +assign addA19 = curReadDataLU[639:608]; +assign addA20 = curReadDataLU[671:640]; +assign addA21 = curReadDataLU[703:672]; +assign addA22 = curReadDataLU[735:704]; +assign addA23 = curReadDataLU[767:736]; +assign addA24 = curReadDataLU[799:768]; +assign addA25 = curReadDataLU[831:800]; +assign addA26 = curReadDataLU[863:832]; +assign addA27 = curReadDataLU[895:864]; +assign addA28 = curReadDataLU[927:896]; +assign addA29 = curReadDataLU[959:928]; +assign addA30 = curReadDataLU[991:960]; +assign addA31 = curReadDataLU[1023:992]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign rcWriteData[287:256] = (curWriteSel == 0) ? multResult8 : addResult8; +assign rcWriteData[319:288] = (curWriteSel == 0) ? multResult9 : addResult9; +assign rcWriteData[351:320] = (curWriteSel == 0) ? multResult10 : addResult10; +assign rcWriteData[383:352] = (curWriteSel == 0) ? multResult11 : addResult11; +assign rcWriteData[415:384] = (curWriteSel == 0) ? multResult12 : addResult12; +assign rcWriteData[447:416] = (curWriteSel == 0) ? multResult13 : addResult13; +assign rcWriteData[479:448] = (curWriteSel == 0) ? multResult14 : addResult14; +assign rcWriteData[511:480] = (curWriteSel == 0) ? multResult15 : addResult15; +assign rcWriteData[543:512] = (curWriteSel == 0) ? multResult16 : addResult16; +assign rcWriteData[575:544] = (curWriteSel == 0) ? multResult17 : addResult17; +assign rcWriteData[607:576] = (curWriteSel == 0) ? multResult18 : addResult18; +assign rcWriteData[639:608] = (curWriteSel == 0) ? multResult19 : addResult19; +assign rcWriteData[671:640] = (curWriteSel == 0) ? multResult20 : addResult20; +assign rcWriteData[703:672] = (curWriteSel == 0) ? multResult21 : addResult21; +assign rcWriteData[735:704] = (curWriteSel == 0) ? multResult22 : addResult22; +assign rcWriteData[767:736] = (curWriteSel == 0) ? multResult23 : addResult23; +assign rcWriteData[799:768] = (curWriteSel == 0) ? multResult24 : addResult24; +assign rcWriteData[831:800] = (curWriteSel == 0) ? multResult25 : addResult25; +assign rcWriteData[863:832] = (curWriteSel == 0) ? multResult26 : addResult26; +assign rcWriteData[895:864] = (curWriteSel == 0) ? multResult27 : addResult27; +assign rcWriteData[927:896] = (curWriteSel == 0) ? multResult28 : addResult28; +assign rcWriteData[959:928] = (curWriteSel == 0) ? multResult29 : addResult29; +assign rcWriteData[991:960] = (curWriteSel == 0) ? multResult30 : addResult30; +assign rcWriteData[1023:992] = (curWriteSel == 0) ? multResult31 : addResult31; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[7-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[128-1:0] curWriteByteEn; +output[7-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[128-1:0] leftWriteByteEn; +output[7-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[12-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[5-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[7-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[7-1:0] i1, j; +reg[12-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[7-1:0] diagIdx, leftIdx, msIdx; +reg[5-1:0] imodk, i1modk; +reg[7-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[128-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[128-1:0] curWriteByteEn; +reg[7-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[128-1:0] leftWriteByteEn; +reg[7-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[12-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[5-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[7-1:0] counter; +reg[6-1:0] divCounter; + +reg[128-1:0]writeByteEnDelay0; +reg[128-1:0]writeByteEnDelay1; +reg[128-1:0]writeByteEnDelay2; +reg[128-1:0]writeByteEnDelay3; +reg[128-1:0]writeByteEnDelay4; +reg[128-1:0]writeByteEnDelay5; +reg[128-1:0]writeByteEnDelay6; +reg[128-1:0]writeByteEnDelay7; +reg[128-1:0]writeByteEnDelay8; +reg[128-1:0]writeByteEnDelay9; +reg[128-1:0]writeByteEnDelay10; +reg[128-1:0]writeByteEnDelay11; +reg[128-1:0]writeByteEnDelay12; +reg[128-1:0]writeByteEnDelay13; +reg[128-1:0]writeByteEnDelay14; +reg[128-1:0]writeByteEnDelay15; +reg[128-1:0]writeByteEnDelay16; +reg[128-1:0]writeByteEnDelay17; +reg[128-1:0]writeByteEnDelay18; +reg[128-1:0]writeByteEnDelay19; +reg[128-1:0]writeByteEnDelay20; +reg[128-1:0]writeByteEnDelay21; +reg[128-1:0]writeByteEnDelay22; +reg[128-1:0]writeByteEnDelay23; +reg[128-1:0]writeByteEnDelay24; +reg[128-1:0]writeByteEnDelay25; +reg[128-1:0]writeByteEnDelay26; +reg[128-1:0]writeByteEnDelay27; +reg[128-1:0]writeByteEnDelay28; +reg[128-1:0]writeByteEnDelay29; +reg[128-1:0]writeByteEnDelay30; +reg[128-1:0]writeByteEnDelay31; + +reg[7-1:0]curWriteAddrDelay0; +reg[7-1:0]curWriteAddrDelay1; +reg[7-1:0]curWriteAddrDelay2; +reg[7-1:0]curWriteAddrDelay3; +reg[7-1:0]curWriteAddrDelay4; +reg[7-1:0]curWriteAddrDelay5; +reg[7-1:0]curWriteAddrDelay6; +reg[7-1:0]curWriteAddrDelay7; +reg[7-1:0]curWriteAddrDelay8; +reg[7-1:0]curWriteAddrDelay9; +reg[7-1:0]curWriteAddrDelay10; +reg[7-1:0]curWriteAddrDelay11; +reg[7-1:0]curWriteAddrDelay12; +reg[7-1:0]curWriteAddrDelay13; +reg[7-1:0]curWriteAddrDelay14; +reg[7-1:0]curWriteAddrDelay15; +reg[7-1:0]curWriteAddrDelay16; +reg[7-1:0]curWriteAddrDelay17; +reg[7-1:0]curWriteAddrDelay18; +reg[7-1:0]curWriteAddrDelay19; +reg[7-1:0]curWriteAddrDelay20; +reg[7-1:0]curWriteAddrDelay21; +reg[7-1:0]curWriteAddrDelay22; +reg[7-1:0]curWriteAddrDelay23; +reg[7-1:0]curWriteAddrDelay24; +reg[7-1:0]curWriteAddrDelay25; +reg[7-1:0]curWriteAddrDelay26; +reg[7-1:0]curWriteAddrDelay27; +reg[7-1:0]curWriteAddrDelay28; +reg[7-1:0]curWriteAddrDelay29; +reg[7-1:0]curWriteAddrDelay30; +reg[7-1:0]curWriteAddrDelay31; + +reg[7-1:0]curReadAddrDelay0; +reg[7-1:0]curReadAddrDelay1; +reg[7-1:0]curReadAddrDelay2; +reg[7-1:0]curReadAddrDelay3; +reg[7-1:0]curReadAddrDelay4; +reg[7-1:0]curReadAddrDelay5; +reg[7-1:0]curReadAddrDelay6; +reg[7-1:0]curReadAddrDelay7; +reg[7-1:0]curReadAddrDelay8; +reg[7-1:0]curReadAddrDelay9; +reg[7-1:0]curReadAddrDelay10; +reg[7-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[7-1:0]leftReadAddrDelay0; +reg[12-1:0]topWriteAddrDelay0; +reg[12-1:0]topWriteAddrDelay1; +reg[12-1:0]topWriteAddrDelay2; +reg[12-1:0]topWriteAddrDelay3; +reg[12-1:0]topWriteAddrDelay4; +reg[12-1:0]topWriteAddrDelay5; +reg[12-1:0]topWriteAddrDelay6; +reg[12-1:0]topWriteAddrDelay7; +reg[12-1:0]topWriteAddrDelay8; +reg[12-1:0]topWriteAddrDelay9; +reg[12-1:0]topWriteAddrDelay10; +reg[12-1:0]topWriteAddrDelay11; +reg[12-1:0]topWriteAddrDelay12; +reg[12-1:0]topWriteAddrDelay13; +reg[12-1:0]topWriteAddrDelay14; +reg[12-1:0]topWriteAddrDelay15; +reg[12-1:0]topWriteAddrDelay16; +reg[12-1:0]topWriteAddrDelay17; +reg[12-1:0]topWriteAddrDelay18; +reg[12-1:0]topWriteAddrDelay19; +reg[12-1:0]topWriteAddrDelay20; +reg[12-1:0]topWriteAddrDelay21; +reg[12-1:0]topWriteAddrDelay22; +reg[12-1:0]topWriteAddrDelay23; +reg[12-1:0]topWriteAddrDelay24; +reg[12-1:0]topWriteAddrDelay25; +reg[12-1:0]topWriteAddrDelay26; +reg[12-1:0]topWriteAddrDelay27; +reg[12-1:0]topWriteAddrDelay28; +reg[12-1:0]topWriteAddrDelay29; +reg[12-1:0]topWriteAddrDelay30; +reg[12-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[5-1:0]topWriteSelDelay0; +reg[5-1:0]topWriteSelDelay1; +reg[5-1:0]topWriteSelDelay2; +reg[5-1:0]topWriteSelDelay3; +reg[5-1:0]topWriteSelDelay4; +reg[5-1:0]topWriteSelDelay5; +reg[5-1:0]topWriteSelDelay6; +reg[5-1:0]topWriteSelDelay7; +reg[5-1:0]topWriteSelDelay8; +reg[5-1:0]topWriteSelDelay9; +reg[5-1:0]topWriteSelDelay10; +reg[5-1:0]topWriteSelDelay11; +reg[5-1:0]topWriteSelDelay12; +reg[5-1:0]topWriteSelDelay13; +reg[5-1:0]topWriteSelDelay14; +reg[5-1:0]topWriteSelDelay15; +reg[5-1:0]topWriteSelDelay16; +reg[5-1:0]topWriteSelDelay17; +reg[5-1:0]topWriteSelDelay18; +reg[5-1:0]topWriteSelDelay19; +reg[5-1:0]topWriteSelDelay20; +reg[5-1:0]topWriteSelDelay21; +reg[5-1:0]topWriteSelDelay22; +reg[5-1:0]topWriteSelDelay23; +reg[5-1:0]topWriteSelDelay24; +reg[5-1:0]topWriteSelDelay25; +reg[5-1:0]topWriteSelDelay26; +reg[5-1:0]topWriteSelDelay27; +reg[5-1:0]topWriteSelDelay28; +reg[5-1:0]topWriteSelDelay29; +reg[5-1:0]topWriteSelDelay30; +reg[5-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [7-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+32-1)>>5; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 32-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 7'b0000000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 32-1 && mode == 2'b00) || (i1modk == 32-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 7'b0000000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 32-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 7'b0000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 5'b00000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 32-1) + imodk <= 5'b00000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 5'b00001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 32-1) + i1modk <= 5'b00000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 12'b000000000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 12'b000000000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 7'b0000001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 7'b0000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 7'b0000000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 32-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >7'b0000000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 5'b00000: begin + i1modkByteEn <= ~(128'b0) >> (5'b00000<<2'b10); + end + 5'b00001: begin + i1modkByteEn <= ~(128'b0) >> (5'b00001<<2'b10); + end + 5'b00010: begin + i1modkByteEn <= ~(128'b0) >> (5'b00010<<2'b10); + end + 5'b00011: begin + i1modkByteEn <= ~(128'b0) >> (5'b00011<<2'b10); + end + 5'b00100: begin + i1modkByteEn <= ~(128'b0) >> (5'b00100<<2'b10); + end + 5'b00101: begin + i1modkByteEn <= ~(128'b0) >> (5'b00101<<2'b10); + end + 5'b00110: begin + i1modkByteEn <= ~(128'b0) >> (5'b00110<<2'b10); + end + 5'b00111: begin + i1modkByteEn <= ~(128'b0) >> (5'b00111<<2'b10); + end + 5'b01000: begin + i1modkByteEn <= ~(128'b0) >> (5'b01000<<2'b10); + end + 5'b01001: begin + i1modkByteEn <= ~(128'b0) >> (5'b01001<<2'b10); + end + 5'b01010: begin + i1modkByteEn <= ~(128'b0) >> (5'b01010<<2'b10); + end + 5'b01011: begin + i1modkByteEn <= ~(128'b0) >> (5'b01011<<2'b10); + end + 5'b01100: begin + i1modkByteEn <= ~(128'b0) >> (5'b01100<<2'b10); + end + 5'b01101: begin + i1modkByteEn <= ~(128'b0) >> (5'b01101<<2'b10); + end + 5'b01110: begin + i1modkByteEn <= ~(128'b0) >> (5'b01110<<2'b10); + end + 5'b01111: begin + i1modkByteEn <= ~(128'b0) >> (5'b01111<<2'b10); + end + 5'b10000: begin + i1modkByteEn <= ~(128'b0) >> (5'b10000<<2'b10); + end + 5'b10001: begin + i1modkByteEn <= ~(128'b0) >> (5'b10001<<2'b10); + end + 5'b10010: begin + i1modkByteEn <= ~(128'b0) >> (5'b10010<<2'b10); + end + 5'b10011: begin + i1modkByteEn <= ~(128'b0) >> (5'b10011<<2'b10); + end + 5'b10100: begin + i1modkByteEn <= ~(128'b0) >> (5'b10100<<2'b10); + end + 5'b10101: begin + i1modkByteEn <= ~(128'b0) >> (5'b10101<<2'b10); + end + 5'b10110: begin + i1modkByteEn <= ~(128'b0) >> (5'b10110<<2'b10); + end + 5'b10111: begin + i1modkByteEn <= ~(128'b0) >> (5'b10111<<2'b10); + end + 5'b11000: begin + i1modkByteEn <= ~(128'b0) >> (5'b11000<<2'b10); + end + 5'b11001: begin + i1modkByteEn <= ~(128'b0) >> (5'b11001<<2'b10); + end + 5'b11010: begin + i1modkByteEn <= ~(128'b0) >> (5'b11010<<2'b10); + end + 5'b11011: begin + i1modkByteEn <= ~(128'b0) >> (5'b11011<<2'b10); + end + 5'b11100: begin + i1modkByteEn <= ~(128'b0) >> (5'b11100<<2'b10); + end + 5'b11101: begin + i1modkByteEn <= ~(128'b0) >> (5'b11101<<2'b10); + end + 5'b11110: begin + i1modkByteEn <= ~(128'b0) >> (5'b11110<<2'b10); + end + 5'b11111: begin + i1modkByteEn <= ~(128'b0) >> (5'b11111<<2'b10); + end + default: begin + i1modkByteEn <= ~(128'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 128'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 4096, TOPSIZEWIDTH = 12, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [12-1:0] rdaddress; + input [12-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram_4096x32 inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 256 +`define rFIFOSIZEWIDTH 8 +`define rFIFOOUTPUTWIDTH 1024 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 12'b010000000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 5'b01000 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 4'b0111 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 12'b010000000000 +`define DATANUMBYTES 9'b010000000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define RATIO 6'b010000 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [6:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [4:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[1023:960]; +assign mem_data[63:0] = ram_read_dataw[1023:960]; +assign ram_write_dataw[127:64] = rdata[959:896]; +assign mem_data[127:64] = ram_read_dataw[959:896]; +assign ram_write_dataw[191:128] = rdata[895:832]; +assign mem_data[191:128] = ram_read_dataw[895:832]; +assign ram_write_dataw[255:192] = rdata[831:768]; +assign mem_data[255:192] = ram_read_dataw[831:768]; +assign ram_write_dataw[319:256] = rdata[767:704]; +assign mem_data[319:256] = ram_read_dataw[767:704]; +assign ram_write_dataw[383:320] = rdata[703:640]; +assign mem_data[383:320] = ram_read_dataw[703:640]; +assign ram_write_dataw[447:384] = rdata[639:576]; +assign mem_data[447:384] = ram_read_dataw[639:576]; +assign ram_write_dataw[511:448] = rdata[575:512]; +assign mem_data[511:448] = ram_read_dataw[575:512]; +assign ram_write_dataw[575:512] = rdata[511:448]; +assign mem_data[575:512] = ram_read_dataw[511:448]; +assign ram_write_dataw[639:576] = rdata[447:384]; +assign mem_data[639:576] = ram_read_dataw[447:384]; +assign ram_write_dataw[703:640] = rdata[383:320]; +assign mem_data[703:640] = ram_read_dataw[383:320]; +assign ram_write_dataw[767:704] = rdata[319:256]; +assign mem_data[767:704] = ram_read_dataw[319:256]; +assign ram_write_dataw[831:768] = rdata[255:192]; +assign mem_data[831:768] = ram_read_dataw[255:192]; +assign ram_write_dataw[895:832] = rdata[191:128]; +assign mem_data[895:832] = ram_read_dataw[191:128]; +assign ram_write_dataw[959:896] = rdata[127:64]; +assign mem_data[959:896] = ram_read_dataw[127:64]; +assign ram_write_dataw[1023:960] = rdata[63:0]; +assign mem_data[1023:960] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[1023:0]; +assign ram_read_dataw[1023:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[3:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 9'b000000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +else if (counter == 4) + q[319:256] <= data_ram; +else if (counter == 5) + q[383:320] <= data_ram; +else if (counter == 6) + q[447:384] <= data_ram; +else if (counter == 7) + q[511:448] <= data_ram; +else if (counter == 8) + q[575:512] <= data_ram; +else if (counter == 9) + q[639:576] <= data_ram; +else if (counter == 10) + q[703:640] <= data_ram; +else if (counter == 11) + q[767:704] <= data_ram; +else if (counter == 12) + q[831:768] <= data_ram; +else if (counter == 13) + q[895:832] <= data_ram; +else if (counter == 14) + q[959:896] <= data_ram; +else if (counter == 15) + q[1023:960] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram_rfifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[3:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 1024'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +else if(counter == 4) + q <= data_ram[319:256]; +else if(counter == 5) + q <= data_ram[383:320]; +else if(counter == 6) + q <= data_ram[447:384]; +else if(counter == 7) + q <= data_ram[511:448]; +else if(counter == 8) + q <= data_ram[575:512]; +else if(counter == 9) + q <= data_ram[639:576]; +else if(counter == 10) + q <= data_ram[703:640]; +else if(counter == 11) + q <= data_ram[767:704]; +else if(counter == 12) + q <= data_ram[831:768]; +else if(counter == 13) + q <= data_ram[895:832]; +else if(counter == 14) + q <= data_ram[959:896]; +else if(counter == 15) + q <= data_ram[1023:960]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram_wfifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 7'b0000000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram_afifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram_mfifo ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule + +//--------------------------------------- +// A dual-port RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram ( + input clk, + input we1, + input we2, + input [`rRAMSIZEWIDTH - 1 : 0] addr1, + input [`RAMWIDTH - 1 : 0] data1, + output [`RAMWIDTH - 1 : 0] out1, + input [`rRAMSIZEWIDTH - 1 : 0] addr2, + input [`RAMWIDTH - 1 : 0] data2, + output [`RAMWIDTH - 1 : 0] out2 +); + reg [`RAMWIDTH - 1 : 0] ram[2**`rRAMSIZEWIDTH - 1 : 0]; + reg [`RAMWIDTH - 1 : 0] data_out1; + reg [`RAMWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 4096x32 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_4096x32 ( + input clk, + input we1, + input we2, + input [12 - 1 : 0] addr1, + input [32 - 1 : 0] data1, + output [32 - 1 : 0] out1, + input [12 - 1 : 0] addr2, + input [32 - 1 : 0] data2, + output [32 - 1 : 0] out2 +); + reg [32 - 1 : 0] ram[2**12 - 1 : 0]; + reg [32 - 1 : 0] data_out1; + reg [32 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM rFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_rfifo ( + input clk, + input we1, + input we2, + input [`rFIFOSIZEWIDTH - 1 : 0] addr1, + input [`rFIFOINPUTWIDTH - 1 : 0] data1, + output [`rFIFOINPUTWIDTH - 1 : 0] out1, + input [`rFIFOSIZEWIDTH - 1 : 0] addr2, + input [`rFIFOINPUTWIDTH - 1 : 0] data2, + output [`rFIFOINPUTWIDTH - 1 : 0] out2 +); + reg [`rFIFOINPUTWIDTH - 1 : 0] ram[2**`rFIFOSIZEWIDTH - 1 : 0]; + reg [`rFIFOINPUTWIDTH - 1 : 0] data_out1; + reg [`rFIFOINPUTWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM wFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_wfifo ( + input clk, + input we1, + input we2, + input [`wFIFOSIZEWIDTH - 1 : 0] addr1, + input [`wFIFOINPUTWIDTH - 1 : 0] data1, + output [`wFIFOINPUTWIDTH - 1 : 0] out1, + input [`wFIFOSIZEWIDTH - 1 : 0] addr2, + input [`wFIFOINPUTWIDTH - 1 : 0] data2, + output [`wFIFOINPUTWIDTH - 1 : 0] out2 +); + reg [`wFIFOINPUTWIDTH - 1 : 0] ram[2**`wFIFOSIZEWIDTH - 1 : 0]; + reg [`wFIFOINPUTWIDTH - 1 : 0] data_out1; + reg [`wFIFOINPUTWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM wFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_afifo ( + input clk, + input we1, + input we2, + input [`aFIFOSIZEWIDTH - 1 : 0] addr1, + input [`aFIFOWIDTH - 1 : 0] data1, + output [`aFIFOWIDTH - 1 : 0] out1, + input [`aFIFOSIZEWIDTH - 1 : 0] addr2, + input [`aFIFOWIDTH - 1 : 0] data2, + output [`aFIFOWIDTH - 1 : 0] out2 +); + reg [`aFIFOWIDTH - 1 : 0] ram[2**`aFIFOSIZEWIDTH - 1 : 0]; + reg [`aFIFOWIDTH - 1 : 0] data_out1; + reg [`aFIFOWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM mFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_mfifo ( + input clk, + input we1, + input we2, + input [`mFIFOSIZEWIDTH - 1 : 0] addr1, + input [`mFIFOWIDTH - 1 : 0] data1, + output [`mFIFOWIDTH - 1 : 0] out1, + input [`mFIFOSIZEWIDTH - 1 : 0] addr2, + input [`mFIFOWIDTH - 1 : 0] data2, + output [`mFIFOWIDTH - 1 : 0] out2 +); + reg [`mFIFOWIDTH - 1 : 0] ram[2**`mFIFOSIZEWIDTH - 1 : 0]; + reg [`mFIFOWIDTH - 1 : 0] data_out1; + reg [`mFIFOWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v new file mode 100755 index 000000000..c5d441b7c --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v @@ -0,0 +1,6009 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 5'b01000 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 13'b0100000000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 5'b01000 + +module LU64PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 9'b010000000 +`define BLOCKN 9'b010000000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 8'b01000000 +`define MEMBLOCKN 8'b01000000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 5'b01000 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 8'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 8'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 8'b0; + ram_addr <= 8'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>7)<<6; + mem_N <= Ndivk<<7; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 8 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 8'b01000000 +`define PEWIDTH 4'b0110 +`define BLOCKWIDTH 5'b01000 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define TOPSIZEWIDTH 5'b01110 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multA8; +wire[`PRECISION-1:0] multA9; +wire[`PRECISION-1:0] multA10; +wire[`PRECISION-1:0] multA11; +wire[`PRECISION-1:0] multA12; +wire[`PRECISION-1:0] multA13; +wire[`PRECISION-1:0] multA14; +wire[`PRECISION-1:0] multA15; +wire[`PRECISION-1:0] multA16; +wire[`PRECISION-1:0] multA17; +wire[`PRECISION-1:0] multA18; +wire[`PRECISION-1:0] multA19; +wire[`PRECISION-1:0] multA20; +wire[`PRECISION-1:0] multA21; +wire[`PRECISION-1:0] multA22; +wire[`PRECISION-1:0] multA23; +wire[`PRECISION-1:0] multA24; +wire[`PRECISION-1:0] multA25; +wire[`PRECISION-1:0] multA26; +wire[`PRECISION-1:0] multA27; +wire[`PRECISION-1:0] multA28; +wire[`PRECISION-1:0] multA29; +wire[`PRECISION-1:0] multA30; +wire[`PRECISION-1:0] multA31; +wire[`PRECISION-1:0] multA32; +wire[`PRECISION-1:0] multA33; +wire[`PRECISION-1:0] multA34; +wire[`PRECISION-1:0] multA35; +wire[`PRECISION-1:0] multA36; +wire[`PRECISION-1:0] multA37; +wire[`PRECISION-1:0] multA38; +wire[`PRECISION-1:0] multA39; +wire[`PRECISION-1:0] multA40; +wire[`PRECISION-1:0] multA41; +wire[`PRECISION-1:0] multA42; +wire[`PRECISION-1:0] multA43; +wire[`PRECISION-1:0] multA44; +wire[`PRECISION-1:0] multA45; +wire[`PRECISION-1:0] multA46; +wire[`PRECISION-1:0] multA47; +wire[`PRECISION-1:0] multA48; +wire[`PRECISION-1:0] multA49; +wire[`PRECISION-1:0] multA50; +wire[`PRECISION-1:0] multA51; +wire[`PRECISION-1:0] multA52; +wire[`PRECISION-1:0] multA53; +wire[`PRECISION-1:0] multA54; +wire[`PRECISION-1:0] multA55; +wire[`PRECISION-1:0] multA56; +wire[`PRECISION-1:0] multA57; +wire[`PRECISION-1:0] multA58; +wire[`PRECISION-1:0] multA59; +wire[`PRECISION-1:0] multA60; +wire[`PRECISION-1:0] multA61; +wire[`PRECISION-1:0] multA62; +wire[`PRECISION-1:0] multA63; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] multResult8; +wire[`PRECISION-1:0] multResult9; +wire[`PRECISION-1:0] multResult10; +wire[`PRECISION-1:0] multResult11; +wire[`PRECISION-1:0] multResult12; +wire[`PRECISION-1:0] multResult13; +wire[`PRECISION-1:0] multResult14; +wire[`PRECISION-1:0] multResult15; +wire[`PRECISION-1:0] multResult16; +wire[`PRECISION-1:0] multResult17; +wire[`PRECISION-1:0] multResult18; +wire[`PRECISION-1:0] multResult19; +wire[`PRECISION-1:0] multResult20; +wire[`PRECISION-1:0] multResult21; +wire[`PRECISION-1:0] multResult22; +wire[`PRECISION-1:0] multResult23; +wire[`PRECISION-1:0] multResult24; +wire[`PRECISION-1:0] multResult25; +wire[`PRECISION-1:0] multResult26; +wire[`PRECISION-1:0] multResult27; +wire[`PRECISION-1:0] multResult28; +wire[`PRECISION-1:0] multResult29; +wire[`PRECISION-1:0] multResult30; +wire[`PRECISION-1:0] multResult31; +wire[`PRECISION-1:0] multResult32; +wire[`PRECISION-1:0] multResult33; +wire[`PRECISION-1:0] multResult34; +wire[`PRECISION-1:0] multResult35; +wire[`PRECISION-1:0] multResult36; +wire[`PRECISION-1:0] multResult37; +wire[`PRECISION-1:0] multResult38; +wire[`PRECISION-1:0] multResult39; +wire[`PRECISION-1:0] multResult40; +wire[`PRECISION-1:0] multResult41; +wire[`PRECISION-1:0] multResult42; +wire[`PRECISION-1:0] multResult43; +wire[`PRECISION-1:0] multResult44; +wire[`PRECISION-1:0] multResult45; +wire[`PRECISION-1:0] multResult46; +wire[`PRECISION-1:0] multResult47; +wire[`PRECISION-1:0] multResult48; +wire[`PRECISION-1:0] multResult49; +wire[`PRECISION-1:0] multResult50; +wire[`PRECISION-1:0] multResult51; +wire[`PRECISION-1:0] multResult52; +wire[`PRECISION-1:0] multResult53; +wire[`PRECISION-1:0] multResult54; +wire[`PRECISION-1:0] multResult55; +wire[`PRECISION-1:0] multResult56; +wire[`PRECISION-1:0] multResult57; +wire[`PRECISION-1:0] multResult58; +wire[`PRECISION-1:0] multResult59; +wire[`PRECISION-1:0] multResult60; +wire[`PRECISION-1:0] multResult61; +wire[`PRECISION-1:0] multResult62; +wire[`PRECISION-1:0] multResult63; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addA8; +wire[`PRECISION-1:0] addA9; +wire[`PRECISION-1:0] addA10; +wire[`PRECISION-1:0] addA11; +wire[`PRECISION-1:0] addA12; +wire[`PRECISION-1:0] addA13; +wire[`PRECISION-1:0] addA14; +wire[`PRECISION-1:0] addA15; +wire[`PRECISION-1:0] addA16; +wire[`PRECISION-1:0] addA17; +wire[`PRECISION-1:0] addA18; +wire[`PRECISION-1:0] addA19; +wire[`PRECISION-1:0] addA20; +wire[`PRECISION-1:0] addA21; +wire[`PRECISION-1:0] addA22; +wire[`PRECISION-1:0] addA23; +wire[`PRECISION-1:0] addA24; +wire[`PRECISION-1:0] addA25; +wire[`PRECISION-1:0] addA26; +wire[`PRECISION-1:0] addA27; +wire[`PRECISION-1:0] addA28; +wire[`PRECISION-1:0] addA29; +wire[`PRECISION-1:0] addA30; +wire[`PRECISION-1:0] addA31; +wire[`PRECISION-1:0] addA32; +wire[`PRECISION-1:0] addA33; +wire[`PRECISION-1:0] addA34; +wire[`PRECISION-1:0] addA35; +wire[`PRECISION-1:0] addA36; +wire[`PRECISION-1:0] addA37; +wire[`PRECISION-1:0] addA38; +wire[`PRECISION-1:0] addA39; +wire[`PRECISION-1:0] addA40; +wire[`PRECISION-1:0] addA41; +wire[`PRECISION-1:0] addA42; +wire[`PRECISION-1:0] addA43; +wire[`PRECISION-1:0] addA44; +wire[`PRECISION-1:0] addA45; +wire[`PRECISION-1:0] addA46; +wire[`PRECISION-1:0] addA47; +wire[`PRECISION-1:0] addA48; +wire[`PRECISION-1:0] addA49; +wire[`PRECISION-1:0] addA50; +wire[`PRECISION-1:0] addA51; +wire[`PRECISION-1:0] addA52; +wire[`PRECISION-1:0] addA53; +wire[`PRECISION-1:0] addA54; +wire[`PRECISION-1:0] addA55; +wire[`PRECISION-1:0] addA56; +wire[`PRECISION-1:0] addA57; +wire[`PRECISION-1:0] addA58; +wire[`PRECISION-1:0] addA59; +wire[`PRECISION-1:0] addA60; +wire[`PRECISION-1:0] addA61; +wire[`PRECISION-1:0] addA62; +wire[`PRECISION-1:0] addA63; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`PRECISION-1:0] addResult8; +wire[`PRECISION-1:0] addResult9; +wire[`PRECISION-1:0] addResult10; +wire[`PRECISION-1:0] addResult11; +wire[`PRECISION-1:0] addResult12; +wire[`PRECISION-1:0] addResult13; +wire[`PRECISION-1:0] addResult14; +wire[`PRECISION-1:0] addResult15; +wire[`PRECISION-1:0] addResult16; +wire[`PRECISION-1:0] addResult17; +wire[`PRECISION-1:0] addResult18; +wire[`PRECISION-1:0] addResult19; +wire[`PRECISION-1:0] addResult20; +wire[`PRECISION-1:0] addResult21; +wire[`PRECISION-1:0] addResult22; +wire[`PRECISION-1:0] addResult23; +wire[`PRECISION-1:0] addResult24; +wire[`PRECISION-1:0] addResult25; +wire[`PRECISION-1:0] addResult26; +wire[`PRECISION-1:0] addResult27; +wire[`PRECISION-1:0] addResult28; +wire[`PRECISION-1:0] addResult29; +wire[`PRECISION-1:0] addResult30; +wire[`PRECISION-1:0] addResult31; +wire[`PRECISION-1:0] addResult32; +wire[`PRECISION-1:0] addResult33; +wire[`PRECISION-1:0] addResult34; +wire[`PRECISION-1:0] addResult35; +wire[`PRECISION-1:0] addResult36; +wire[`PRECISION-1:0] addResult37; +wire[`PRECISION-1:0] addResult38; +wire[`PRECISION-1:0] addResult39; +wire[`PRECISION-1:0] addResult40; +wire[`PRECISION-1:0] addResult41; +wire[`PRECISION-1:0] addResult42; +wire[`PRECISION-1:0] addResult43; +wire[`PRECISION-1:0] addResult44; +wire[`PRECISION-1:0] addResult45; +wire[`PRECISION-1:0] addResult46; +wire[`PRECISION-1:0] addResult47; +wire[`PRECISION-1:0] addResult48; +wire[`PRECISION-1:0] addResult49; +wire[`PRECISION-1:0] addResult50; +wire[`PRECISION-1:0] addResult51; +wire[`PRECISION-1:0] addResult52; +wire[`PRECISION-1:0] addResult53; +wire[`PRECISION-1:0] addResult54; +wire[`PRECISION-1:0] addResult55; +wire[`PRECISION-1:0] addResult56; +wire[`PRECISION-1:0] addResult57; +wire[`PRECISION-1:0] addResult58; +wire[`PRECISION-1:0] addResult59; +wire[`PRECISION-1:0] addResult60; +wire[`PRECISION-1:0] addResult61; +wire[`PRECISION-1:0] addResult62; +wire[`PRECISION-1:0] addResult63; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); +mult_add PE8 (clk, multA8, multOperand, addA8, multResult8, addResult8); +mult_add PE9 (clk, multA9, multOperand, addA9, multResult9, addResult9); +mult_add PE10 (clk, multA10, multOperand, addA10, multResult10, addResult10); +mult_add PE11 (clk, multA11, multOperand, addA11, multResult11, addResult11); +mult_add PE12 (clk, multA12, multOperand, addA12, multResult12, addResult12); +mult_add PE13 (clk, multA13, multOperand, addA13, multResult13, addResult13); +mult_add PE14 (clk, multA14, multOperand, addA14, multResult14, addResult14); +mult_add PE15 (clk, multA15, multOperand, addA15, multResult15, addResult15); +mult_add PE16 (clk, multA16, multOperand, addA16, multResult16, addResult16); +mult_add PE17 (clk, multA17, multOperand, addA17, multResult17, addResult17); +mult_add PE18 (clk, multA18, multOperand, addA18, multResult18, addResult18); +mult_add PE19 (clk, multA19, multOperand, addA19, multResult19, addResult19); +mult_add PE20 (clk, multA20, multOperand, addA20, multResult20, addResult20); +mult_add PE21 (clk, multA21, multOperand, addA21, multResult21, addResult21); +mult_add PE22 (clk, multA22, multOperand, addA22, multResult22, addResult22); +mult_add PE23 (clk, multA23, multOperand, addA23, multResult23, addResult23); +mult_add PE24 (clk, multA24, multOperand, addA24, multResult24, addResult24); +mult_add PE25 (clk, multA25, multOperand, addA25, multResult25, addResult25); +mult_add PE26 (clk, multA26, multOperand, addA26, multResult26, addResult26); +mult_add PE27 (clk, multA27, multOperand, addA27, multResult27, addResult27); +mult_add PE28 (clk, multA28, multOperand, addA28, multResult28, addResult28); +mult_add PE29 (clk, multA29, multOperand, addA29, multResult29, addResult29); +mult_add PE30 (clk, multA30, multOperand, addA30, multResult30, addResult30); +mult_add PE31 (clk, multA31, multOperand, addA31, multResult31, addResult31); +mult_add PE32 (clk, multA32, multOperand, addA32, multResult32, addResult32); +mult_add PE33 (clk, multA33, multOperand, addA33, multResult33, addResult33); +mult_add PE34 (clk, multA34, multOperand, addA34, multResult34, addResult34); +mult_add PE35 (clk, multA35, multOperand, addA35, multResult35, addResult35); +mult_add PE36 (clk, multA36, multOperand, addA36, multResult36, addResult36); +mult_add PE37 (clk, multA37, multOperand, addA37, multResult37, addResult37); +mult_add PE38 (clk, multA38, multOperand, addA38, multResult38, addResult38); +mult_add PE39 (clk, multA39, multOperand, addA39, multResult39, addResult39); +mult_add PE40 (clk, multA40, multOperand, addA40, multResult40, addResult40); +mult_add PE41 (clk, multA41, multOperand, addA41, multResult41, addResult41); +mult_add PE42 (clk, multA42, multOperand, addA42, multResult42, addResult42); +mult_add PE43 (clk, multA43, multOperand, addA43, multResult43, addResult43); +mult_add PE44 (clk, multA44, multOperand, addA44, multResult44, addResult44); +mult_add PE45 (clk, multA45, multOperand, addA45, multResult45, addResult45); +mult_add PE46 (clk, multA46, multOperand, addA46, multResult46, addResult46); +mult_add PE47 (clk, multA47, multOperand, addA47, multResult47, addResult47); +mult_add PE48 (clk, multA48, multOperand, addA48, multResult48, addResult48); +mult_add PE49 (clk, multA49, multOperand, addA49, multResult49, addResult49); +mult_add PE50 (clk, multA50, multOperand, addA50, multResult50, addResult50); +mult_add PE51 (clk, multA51, multOperand, addA51, multResult51, addResult51); +mult_add PE52 (clk, multA52, multOperand, addA52, multResult52, addResult52); +mult_add PE53 (clk, multA53, multOperand, addA53, multResult53, addResult53); +mult_add PE54 (clk, multA54, multOperand, addA54, multResult54, addResult54); +mult_add PE55 (clk, multA55, multOperand, addA55, multResult55, addResult55); +mult_add PE56 (clk, multA56, multOperand, addA56, multResult56, addResult56); +mult_add PE57 (clk, multA57, multOperand, addA57, multResult57, addResult57); +mult_add PE58 (clk, multA58, multOperand, addA58, multResult58, addResult58); +mult_add PE59 (clk, multA59, multOperand, addA59, multResult59, addResult59); +mult_add PE60 (clk, multA60, multOperand, addA60, multResult60, addResult60); +mult_add PE61 (clk, multA61, multOperand, addA61, multResult61, addResult61); +mult_add PE62 (clk, multA62, multOperand, addA62, multResult62, addResult62); +mult_add PE63 (clk, multA63, multOperand, addA63, multResult63, addResult63); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult63 or addResult62 or addResult61 or addResult60 or addResult59 or addResult58 or addResult57 or addResult56 or addResult55 or addResult54 or addResult53 or addResult52 or addResult51 or addResult50 or addResult49 or addResult48 or addResult47 or addResult46 or addResult45 or addResult44 or addResult43 or addResult42 or addResult41 or addResult40 or addResult39 or addResult38 or addResult37 or addResult36 or addResult35 or addResult34 or addResult33 or addResult32 or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[2047:2016]; + 1: + topWriteDataLU = curReadDataLU[2015:1984]; + 2: + topWriteDataLU = curReadDataLU[1983:1952]; + 3: + topWriteDataLU = curReadDataLU[1951:1920]; + 4: + topWriteDataLU = curReadDataLU[1919:1888]; + 5: + topWriteDataLU = curReadDataLU[1887:1856]; + 6: + topWriteDataLU = curReadDataLU[1855:1824]; + 7: + topWriteDataLU = curReadDataLU[1823:1792]; + 8: + topWriteDataLU = curReadDataLU[1791:1760]; + 9: + topWriteDataLU = curReadDataLU[1759:1728]; + 10: + topWriteDataLU = curReadDataLU[1727:1696]; + 11: + topWriteDataLU = curReadDataLU[1695:1664]; + 12: + topWriteDataLU = curReadDataLU[1663:1632]; + 13: + topWriteDataLU = curReadDataLU[1631:1600]; + 14: + topWriteDataLU = curReadDataLU[1599:1568]; + 15: + topWriteDataLU = curReadDataLU[1567:1536]; + 16: + topWriteDataLU = curReadDataLU[1535:1504]; + 17: + topWriteDataLU = curReadDataLU[1503:1472]; + 18: + topWriteDataLU = curReadDataLU[1471:1440]; + 19: + topWriteDataLU = curReadDataLU[1439:1408]; + 20: + topWriteDataLU = curReadDataLU[1407:1376]; + 21: + topWriteDataLU = curReadDataLU[1375:1344]; + 22: + topWriteDataLU = curReadDataLU[1343:1312]; + 23: + topWriteDataLU = curReadDataLU[1311:1280]; + 24: + topWriteDataLU = curReadDataLU[1279:1248]; + 25: + topWriteDataLU = curReadDataLU[1247:1216]; + 26: + topWriteDataLU = curReadDataLU[1215:1184]; + 27: + topWriteDataLU = curReadDataLU[1183:1152]; + 28: + topWriteDataLU = curReadDataLU[1151:1120]; + 29: + topWriteDataLU = curReadDataLU[1119:1088]; + 30: + topWriteDataLU = curReadDataLU[1087:1056]; + 31: + topWriteDataLU = curReadDataLU[1055:1024]; + 32: + topWriteDataLU = curReadDataLU[1023:992]; + 33: + topWriteDataLU = curReadDataLU[991:960]; + 34: + topWriteDataLU = curReadDataLU[959:928]; + 35: + topWriteDataLU = curReadDataLU[927:896]; + 36: + topWriteDataLU = curReadDataLU[895:864]; + 37: + topWriteDataLU = curReadDataLU[863:832]; + 38: + topWriteDataLU = curReadDataLU[831:800]; + 39: + topWriteDataLU = curReadDataLU[799:768]; + 40: + topWriteDataLU = curReadDataLU[767:736]; + 41: + topWriteDataLU = curReadDataLU[735:704]; + 42: + topWriteDataLU = curReadDataLU[703:672]; + 43: + topWriteDataLU = curReadDataLU[671:640]; + 44: + topWriteDataLU = curReadDataLU[639:608]; + 45: + topWriteDataLU = curReadDataLU[607:576]; + 46: + topWriteDataLU = curReadDataLU[575:544]; + 47: + topWriteDataLU = curReadDataLU[543:512]; + 48: + topWriteDataLU = curReadDataLU[511:480]; + 49: + topWriteDataLU = curReadDataLU[479:448]; + 50: + topWriteDataLU = curReadDataLU[447:416]; + 51: + topWriteDataLU = curReadDataLU[415:384]; + 52: + topWriteDataLU = curReadDataLU[383:352]; + 53: + topWriteDataLU = curReadDataLU[351:320]; + 54: + topWriteDataLU = curReadDataLU[319:288]; + 55: + topWriteDataLU = curReadDataLU[287:256]; + 56: + topWriteDataLU = curReadDataLU[255:224]; + 57: + topWriteDataLU = curReadDataLU[223:192]; + 58: + topWriteDataLU = curReadDataLU[191:160]; + 59: + topWriteDataLU = curReadDataLU[159:128]; + 60: + topWriteDataLU = curReadDataLU[127:96]; + 61: + topWriteDataLU = curReadDataLU[95:64]; + 62: + topWriteDataLU = curReadDataLU[63:32]; + 63: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult63; + 1: + topWriteDataLU = addResult62; + 2: + topWriteDataLU = addResult61; + 3: + topWriteDataLU = addResult60; + 4: + topWriteDataLU = addResult59; + 5: + topWriteDataLU = addResult58; + 6: + topWriteDataLU = addResult57; + 7: + topWriteDataLU = addResult56; + 8: + topWriteDataLU = addResult55; + 9: + topWriteDataLU = addResult54; + 10: + topWriteDataLU = addResult53; + 11: + topWriteDataLU = addResult52; + 12: + topWriteDataLU = addResult51; + 13: + topWriteDataLU = addResult50; + 14: + topWriteDataLU = addResult49; + 15: + topWriteDataLU = addResult48; + 16: + topWriteDataLU = addResult47; + 17: + topWriteDataLU = addResult46; + 18: + topWriteDataLU = addResult45; + 19: + topWriteDataLU = addResult44; + 20: + topWriteDataLU = addResult43; + 21: + topWriteDataLU = addResult42; + 22: + topWriteDataLU = addResult41; + 23: + topWriteDataLU = addResult40; + 24: + topWriteDataLU = addResult39; + 25: + topWriteDataLU = addResult38; + 26: + topWriteDataLU = addResult37; + 27: + topWriteDataLU = addResult36; + 28: + topWriteDataLU = addResult35; + 29: + topWriteDataLU = addResult34; + 30: + topWriteDataLU = addResult33; + 31: + topWriteDataLU = addResult32; + 32: + topWriteDataLU = addResult31; + 33: + topWriteDataLU = addResult30; + 34: + topWriteDataLU = addResult29; + 35: + topWriteDataLU = addResult28; + 36: + topWriteDataLU = addResult27; + 37: + topWriteDataLU = addResult26; + 38: + topWriteDataLU = addResult25; + 39: + topWriteDataLU = addResult24; + 40: + topWriteDataLU = addResult23; + 41: + topWriteDataLU = addResult22; + 42: + topWriteDataLU = addResult21; + 43: + topWriteDataLU = addResult20; + 44: + topWriteDataLU = addResult19; + 45: + topWriteDataLU = addResult18; + 46: + topWriteDataLU = addResult17; + 47: + topWriteDataLU = addResult16; + 48: + topWriteDataLU = addResult15; + 49: + topWriteDataLU = addResult14; + 50: + topWriteDataLU = addResult13; + 51: + topWriteDataLU = addResult12; + 52: + topWriteDataLU = addResult11; + 53: + topWriteDataLU = addResult10; + 54: + topWriteDataLU = addResult9; + 55: + topWriteDataLU = addResult8; + 56: + topWriteDataLU = addResult7; + 57: + topWriteDataLU = addResult6; + 58: + topWriteDataLU = addResult5; + 59: + topWriteDataLU = addResult4; + 60: + topWriteDataLU = addResult3; + 61: + topWriteDataLU = addResult2; + 62: + topWriteDataLU = addResult1; + 63: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; +assign multA8 = leftReadDataLU[287:256]; +assign multA9 = leftReadDataLU[319:288]; +assign multA10 = leftReadDataLU[351:320]; +assign multA11 = leftReadDataLU[383:352]; +assign multA12 = leftReadDataLU[415:384]; +assign multA13 = leftReadDataLU[447:416]; +assign multA14 = leftReadDataLU[479:448]; +assign multA15 = leftReadDataLU[511:480]; +assign multA16 = leftReadDataLU[543:512]; +assign multA17 = leftReadDataLU[575:544]; +assign multA18 = leftReadDataLU[607:576]; +assign multA19 = leftReadDataLU[639:608]; +assign multA20 = leftReadDataLU[671:640]; +assign multA21 = leftReadDataLU[703:672]; +assign multA22 = leftReadDataLU[735:704]; +assign multA23 = leftReadDataLU[767:736]; +assign multA24 = leftReadDataLU[799:768]; +assign multA25 = leftReadDataLU[831:800]; +assign multA26 = leftReadDataLU[863:832]; +assign multA27 = leftReadDataLU[895:864]; +assign multA28 = leftReadDataLU[927:896]; +assign multA29 = leftReadDataLU[959:928]; +assign multA30 = leftReadDataLU[991:960]; +assign multA31 = leftReadDataLU[1023:992]; +assign multA32 = leftReadDataLU[1055:1024]; +assign multA33 = leftReadDataLU[1087:1056]; +assign multA34 = leftReadDataLU[1119:1088]; +assign multA35 = leftReadDataLU[1151:1120]; +assign multA36 = leftReadDataLU[1183:1152]; +assign multA37 = leftReadDataLU[1215:1184]; +assign multA38 = leftReadDataLU[1247:1216]; +assign multA39 = leftReadDataLU[1279:1248]; +assign multA40 = leftReadDataLU[1311:1280]; +assign multA41 = leftReadDataLU[1343:1312]; +assign multA42 = leftReadDataLU[1375:1344]; +assign multA43 = leftReadDataLU[1407:1376]; +assign multA44 = leftReadDataLU[1439:1408]; +assign multA45 = leftReadDataLU[1471:1440]; +assign multA46 = leftReadDataLU[1503:1472]; +assign multA47 = leftReadDataLU[1535:1504]; +assign multA48 = leftReadDataLU[1567:1536]; +assign multA49 = leftReadDataLU[1599:1568]; +assign multA50 = leftReadDataLU[1631:1600]; +assign multA51 = leftReadDataLU[1663:1632]; +assign multA52 = leftReadDataLU[1695:1664]; +assign multA53 = leftReadDataLU[1727:1696]; +assign multA54 = leftReadDataLU[1759:1728]; +assign multA55 = leftReadDataLU[1791:1760]; +assign multA56 = leftReadDataLU[1823:1792]; +assign multA57 = leftReadDataLU[1855:1824]; +assign multA58 = leftReadDataLU[1887:1856]; +assign multA59 = leftReadDataLU[1919:1888]; +assign multA60 = leftReadDataLU[1951:1920]; +assign multA61 = leftReadDataLU[1983:1952]; +assign multA62 = leftReadDataLU[2015:1984]; +assign multA63 = leftReadDataLU[2047:2016]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; +assign addA8 = curReadDataLU[287:256]; +assign addA9 = curReadDataLU[319:288]; +assign addA10 = curReadDataLU[351:320]; +assign addA11 = curReadDataLU[383:352]; +assign addA12 = curReadDataLU[415:384]; +assign addA13 = curReadDataLU[447:416]; +assign addA14 = curReadDataLU[479:448]; +assign addA15 = curReadDataLU[511:480]; +assign addA16 = curReadDataLU[543:512]; +assign addA17 = curReadDataLU[575:544]; +assign addA18 = curReadDataLU[607:576]; +assign addA19 = curReadDataLU[639:608]; +assign addA20 = curReadDataLU[671:640]; +assign addA21 = curReadDataLU[703:672]; +assign addA22 = curReadDataLU[735:704]; +assign addA23 = curReadDataLU[767:736]; +assign addA24 = curReadDataLU[799:768]; +assign addA25 = curReadDataLU[831:800]; +assign addA26 = curReadDataLU[863:832]; +assign addA27 = curReadDataLU[895:864]; +assign addA28 = curReadDataLU[927:896]; +assign addA29 = curReadDataLU[959:928]; +assign addA30 = curReadDataLU[991:960]; +assign addA31 = curReadDataLU[1023:992]; +assign addA32 = curReadDataLU[1055:1024]; +assign addA33 = curReadDataLU[1087:1056]; +assign addA34 = curReadDataLU[1119:1088]; +assign addA35 = curReadDataLU[1151:1120]; +assign addA36 = curReadDataLU[1183:1152]; +assign addA37 = curReadDataLU[1215:1184]; +assign addA38 = curReadDataLU[1247:1216]; +assign addA39 = curReadDataLU[1279:1248]; +assign addA40 = curReadDataLU[1311:1280]; +assign addA41 = curReadDataLU[1343:1312]; +assign addA42 = curReadDataLU[1375:1344]; +assign addA43 = curReadDataLU[1407:1376]; +assign addA44 = curReadDataLU[1439:1408]; +assign addA45 = curReadDataLU[1471:1440]; +assign addA46 = curReadDataLU[1503:1472]; +assign addA47 = curReadDataLU[1535:1504]; +assign addA48 = curReadDataLU[1567:1536]; +assign addA49 = curReadDataLU[1599:1568]; +assign addA50 = curReadDataLU[1631:1600]; +assign addA51 = curReadDataLU[1663:1632]; +assign addA52 = curReadDataLU[1695:1664]; +assign addA53 = curReadDataLU[1727:1696]; +assign addA54 = curReadDataLU[1759:1728]; +assign addA55 = curReadDataLU[1791:1760]; +assign addA56 = curReadDataLU[1823:1792]; +assign addA57 = curReadDataLU[1855:1824]; +assign addA58 = curReadDataLU[1887:1856]; +assign addA59 = curReadDataLU[1919:1888]; +assign addA60 = curReadDataLU[1951:1920]; +assign addA61 = curReadDataLU[1983:1952]; +assign addA62 = curReadDataLU[2015:1984]; +assign addA63 = curReadDataLU[2047:2016]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign rcWriteData[287:256] = (curWriteSel == 0) ? multResult8 : addResult8; +assign rcWriteData[319:288] = (curWriteSel == 0) ? multResult9 : addResult9; +assign rcWriteData[351:320] = (curWriteSel == 0) ? multResult10 : addResult10; +assign rcWriteData[383:352] = (curWriteSel == 0) ? multResult11 : addResult11; +assign rcWriteData[415:384] = (curWriteSel == 0) ? multResult12 : addResult12; +assign rcWriteData[447:416] = (curWriteSel == 0) ? multResult13 : addResult13; +assign rcWriteData[479:448] = (curWriteSel == 0) ? multResult14 : addResult14; +assign rcWriteData[511:480] = (curWriteSel == 0) ? multResult15 : addResult15; +assign rcWriteData[543:512] = (curWriteSel == 0) ? multResult16 : addResult16; +assign rcWriteData[575:544] = (curWriteSel == 0) ? multResult17 : addResult17; +assign rcWriteData[607:576] = (curWriteSel == 0) ? multResult18 : addResult18; +assign rcWriteData[639:608] = (curWriteSel == 0) ? multResult19 : addResult19; +assign rcWriteData[671:640] = (curWriteSel == 0) ? multResult20 : addResult20; +assign rcWriteData[703:672] = (curWriteSel == 0) ? multResult21 : addResult21; +assign rcWriteData[735:704] = (curWriteSel == 0) ? multResult22 : addResult22; +assign rcWriteData[767:736] = (curWriteSel == 0) ? multResult23 : addResult23; +assign rcWriteData[799:768] = (curWriteSel == 0) ? multResult24 : addResult24; +assign rcWriteData[831:800] = (curWriteSel == 0) ? multResult25 : addResult25; +assign rcWriteData[863:832] = (curWriteSel == 0) ? multResult26 : addResult26; +assign rcWriteData[895:864] = (curWriteSel == 0) ? multResult27 : addResult27; +assign rcWriteData[927:896] = (curWriteSel == 0) ? multResult28 : addResult28; +assign rcWriteData[959:928] = (curWriteSel == 0) ? multResult29 : addResult29; +assign rcWriteData[991:960] = (curWriteSel == 0) ? multResult30 : addResult30; +assign rcWriteData[1023:992] = (curWriteSel == 0) ? multResult31 : addResult31; +assign rcWriteData[1055:1024] = (curWriteSel == 0) ? multResult32 : addResult32; +assign rcWriteData[1087:1056] = (curWriteSel == 0) ? multResult33 : addResult33; +assign rcWriteData[1119:1088] = (curWriteSel == 0) ? multResult34 : addResult34; +assign rcWriteData[1151:1120] = (curWriteSel == 0) ? multResult35 : addResult35; +assign rcWriteData[1183:1152] = (curWriteSel == 0) ? multResult36 : addResult36; +assign rcWriteData[1215:1184] = (curWriteSel == 0) ? multResult37 : addResult37; +assign rcWriteData[1247:1216] = (curWriteSel == 0) ? multResult38 : addResult38; +assign rcWriteData[1279:1248] = (curWriteSel == 0) ? multResult39 : addResult39; +assign rcWriteData[1311:1280] = (curWriteSel == 0) ? multResult40 : addResult40; +assign rcWriteData[1343:1312] = (curWriteSel == 0) ? multResult41 : addResult41; +assign rcWriteData[1375:1344] = (curWriteSel == 0) ? multResult42 : addResult42; +assign rcWriteData[1407:1376] = (curWriteSel == 0) ? multResult43 : addResult43; +assign rcWriteData[1439:1408] = (curWriteSel == 0) ? multResult44 : addResult44; +assign rcWriteData[1471:1440] = (curWriteSel == 0) ? multResult45 : addResult45; +assign rcWriteData[1503:1472] = (curWriteSel == 0) ? multResult46 : addResult46; +assign rcWriteData[1535:1504] = (curWriteSel == 0) ? multResult47 : addResult47; +assign rcWriteData[1567:1536] = (curWriteSel == 0) ? multResult48 : addResult48; +assign rcWriteData[1599:1568] = (curWriteSel == 0) ? multResult49 : addResult49; +assign rcWriteData[1631:1600] = (curWriteSel == 0) ? multResult50 : addResult50; +assign rcWriteData[1663:1632] = (curWriteSel == 0) ? multResult51 : addResult51; +assign rcWriteData[1695:1664] = (curWriteSel == 0) ? multResult52 : addResult52; +assign rcWriteData[1727:1696] = (curWriteSel == 0) ? multResult53 : addResult53; +assign rcWriteData[1759:1728] = (curWriteSel == 0) ? multResult54 : addResult54; +assign rcWriteData[1791:1760] = (curWriteSel == 0) ? multResult55 : addResult55; +assign rcWriteData[1823:1792] = (curWriteSel == 0) ? multResult56 : addResult56; +assign rcWriteData[1855:1824] = (curWriteSel == 0) ? multResult57 : addResult57; +assign rcWriteData[1887:1856] = (curWriteSel == 0) ? multResult58 : addResult58; +assign rcWriteData[1919:1888] = (curWriteSel == 0) ? multResult59 : addResult59; +assign rcWriteData[1951:1920] = (curWriteSel == 0) ? multResult60 : addResult60; +assign rcWriteData[1983:1952] = (curWriteSel == 0) ? multResult61 : addResult61; +assign rcWriteData[2015:1984] = (curWriteSel == 0) ? multResult62 : addResult62; +assign rcWriteData[2047:2016] = (curWriteSel == 0) ? multResult63 : addResult63; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[8-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[256-1:0] curWriteByteEn; +output[8-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[256-1:0] leftWriteByteEn; +output[8-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[14-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[6-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[8-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[8-1:0] i1, j; +reg[14-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[8-1:0] diagIdx, leftIdx, msIdx; +reg[6-1:0] imodk, i1modk; +reg[8-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[256-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[256-1:0] curWriteByteEn; +reg[8-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[256-1:0] leftWriteByteEn; +reg[8-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[14-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[6-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[8-1:0] counter; +reg[6-1:0] divCounter; + +reg[256-1:0]writeByteEnDelay0; +reg[256-1:0]writeByteEnDelay1; +reg[256-1:0]writeByteEnDelay2; +reg[256-1:0]writeByteEnDelay3; +reg[256-1:0]writeByteEnDelay4; +reg[256-1:0]writeByteEnDelay5; +reg[256-1:0]writeByteEnDelay6; +reg[256-1:0]writeByteEnDelay7; +reg[256-1:0]writeByteEnDelay8; +reg[256-1:0]writeByteEnDelay9; +reg[256-1:0]writeByteEnDelay10; +reg[256-1:0]writeByteEnDelay11; +reg[256-1:0]writeByteEnDelay12; +reg[256-1:0]writeByteEnDelay13; +reg[256-1:0]writeByteEnDelay14; +reg[256-1:0]writeByteEnDelay15; +reg[256-1:0]writeByteEnDelay16; +reg[256-1:0]writeByteEnDelay17; +reg[256-1:0]writeByteEnDelay18; +reg[256-1:0]writeByteEnDelay19; +reg[256-1:0]writeByteEnDelay20; +reg[256-1:0]writeByteEnDelay21; +reg[256-1:0]writeByteEnDelay22; +reg[256-1:0]writeByteEnDelay23; +reg[256-1:0]writeByteEnDelay24; +reg[256-1:0]writeByteEnDelay25; +reg[256-1:0]writeByteEnDelay26; +reg[256-1:0]writeByteEnDelay27; +reg[256-1:0]writeByteEnDelay28; +reg[256-1:0]writeByteEnDelay29; +reg[256-1:0]writeByteEnDelay30; +reg[256-1:0]writeByteEnDelay31; + +reg[8-1:0]curWriteAddrDelay0; +reg[8-1:0]curWriteAddrDelay1; +reg[8-1:0]curWriteAddrDelay2; +reg[8-1:0]curWriteAddrDelay3; +reg[8-1:0]curWriteAddrDelay4; +reg[8-1:0]curWriteAddrDelay5; +reg[8-1:0]curWriteAddrDelay6; +reg[8-1:0]curWriteAddrDelay7; +reg[8-1:0]curWriteAddrDelay8; +reg[8-1:0]curWriteAddrDelay9; +reg[8-1:0]curWriteAddrDelay10; +reg[8-1:0]curWriteAddrDelay11; +reg[8-1:0]curWriteAddrDelay12; +reg[8-1:0]curWriteAddrDelay13; +reg[8-1:0]curWriteAddrDelay14; +reg[8-1:0]curWriteAddrDelay15; +reg[8-1:0]curWriteAddrDelay16; +reg[8-1:0]curWriteAddrDelay17; +reg[8-1:0]curWriteAddrDelay18; +reg[8-1:0]curWriteAddrDelay19; +reg[8-1:0]curWriteAddrDelay20; +reg[8-1:0]curWriteAddrDelay21; +reg[8-1:0]curWriteAddrDelay22; +reg[8-1:0]curWriteAddrDelay23; +reg[8-1:0]curWriteAddrDelay24; +reg[8-1:0]curWriteAddrDelay25; +reg[8-1:0]curWriteAddrDelay26; +reg[8-1:0]curWriteAddrDelay27; +reg[8-1:0]curWriteAddrDelay28; +reg[8-1:0]curWriteAddrDelay29; +reg[8-1:0]curWriteAddrDelay30; +reg[8-1:0]curWriteAddrDelay31; + +reg[8-1:0]curReadAddrDelay0; +reg[8-1:0]curReadAddrDelay1; +reg[8-1:0]curReadAddrDelay2; +reg[8-1:0]curReadAddrDelay3; +reg[8-1:0]curReadAddrDelay4; +reg[8-1:0]curReadAddrDelay5; +reg[8-1:0]curReadAddrDelay6; +reg[8-1:0]curReadAddrDelay7; +reg[8-1:0]curReadAddrDelay8; +reg[8-1:0]curReadAddrDelay9; +reg[8-1:0]curReadAddrDelay10; +reg[8-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[8-1:0]leftReadAddrDelay0; +reg[14-1:0]topWriteAddrDelay0; +reg[14-1:0]topWriteAddrDelay1; +reg[14-1:0]topWriteAddrDelay2; +reg[14-1:0]topWriteAddrDelay3; +reg[14-1:0]topWriteAddrDelay4; +reg[14-1:0]topWriteAddrDelay5; +reg[14-1:0]topWriteAddrDelay6; +reg[14-1:0]topWriteAddrDelay7; +reg[14-1:0]topWriteAddrDelay8; +reg[14-1:0]topWriteAddrDelay9; +reg[14-1:0]topWriteAddrDelay10; +reg[14-1:0]topWriteAddrDelay11; +reg[14-1:0]topWriteAddrDelay12; +reg[14-1:0]topWriteAddrDelay13; +reg[14-1:0]topWriteAddrDelay14; +reg[14-1:0]topWriteAddrDelay15; +reg[14-1:0]topWriteAddrDelay16; +reg[14-1:0]topWriteAddrDelay17; +reg[14-1:0]topWriteAddrDelay18; +reg[14-1:0]topWriteAddrDelay19; +reg[14-1:0]topWriteAddrDelay20; +reg[14-1:0]topWriteAddrDelay21; +reg[14-1:0]topWriteAddrDelay22; +reg[14-1:0]topWriteAddrDelay23; +reg[14-1:0]topWriteAddrDelay24; +reg[14-1:0]topWriteAddrDelay25; +reg[14-1:0]topWriteAddrDelay26; +reg[14-1:0]topWriteAddrDelay27; +reg[14-1:0]topWriteAddrDelay28; +reg[14-1:0]topWriteAddrDelay29; +reg[14-1:0]topWriteAddrDelay30; +reg[14-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[6-1:0]topWriteSelDelay0; +reg[6-1:0]topWriteSelDelay1; +reg[6-1:0]topWriteSelDelay2; +reg[6-1:0]topWriteSelDelay3; +reg[6-1:0]topWriteSelDelay4; +reg[6-1:0]topWriteSelDelay5; +reg[6-1:0]topWriteSelDelay6; +reg[6-1:0]topWriteSelDelay7; +reg[6-1:0]topWriteSelDelay8; +reg[6-1:0]topWriteSelDelay9; +reg[6-1:0]topWriteSelDelay10; +reg[6-1:0]topWriteSelDelay11; +reg[6-1:0]topWriteSelDelay12; +reg[6-1:0]topWriteSelDelay13; +reg[6-1:0]topWriteSelDelay14; +reg[6-1:0]topWriteSelDelay15; +reg[6-1:0]topWriteSelDelay16; +reg[6-1:0]topWriteSelDelay17; +reg[6-1:0]topWriteSelDelay18; +reg[6-1:0]topWriteSelDelay19; +reg[6-1:0]topWriteSelDelay20; +reg[6-1:0]topWriteSelDelay21; +reg[6-1:0]topWriteSelDelay22; +reg[6-1:0]topWriteSelDelay23; +reg[6-1:0]topWriteSelDelay24; +reg[6-1:0]topWriteSelDelay25; +reg[6-1:0]topWriteSelDelay26; +reg[6-1:0]topWriteSelDelay27; +reg[6-1:0]topWriteSelDelay28; +reg[6-1:0]topWriteSelDelay29; +reg[6-1:0]topWriteSelDelay30; +reg[6-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [8-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+64-1)>>6; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 64-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 8'b00000000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 64-1 && mode == 2'b00) || (i1modk == 64-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 8'b00000000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 64-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 8'b00000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 6'b000000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 64-1) + imodk <= 6'b000000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 6'b000001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 64-1) + i1modk <= 6'b000000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 14'b00000000000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 14'b00000000000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 8'b00000001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 8'b00000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 8'b00000000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 64-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >8'b00000000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 6'b000000: begin + i1modkByteEn <= ~(256'b0) >> (6'b000000<<2'b10); + end + 6'b000001: begin + i1modkByteEn <= ~(256'b0) >> (6'b000001<<2'b10); + end + 6'b000010: begin + i1modkByteEn <= ~(256'b0) >> (6'b000010<<2'b10); + end + 6'b000011: begin + i1modkByteEn <= ~(256'b0) >> (6'b000011<<2'b10); + end + 6'b000100: begin + i1modkByteEn <= ~(256'b0) >> (6'b000100<<2'b10); + end + 6'b000101: begin + i1modkByteEn <= ~(256'b0) >> (6'b000101<<2'b10); + end + 6'b000110: begin + i1modkByteEn <= ~(256'b0) >> (6'b000110<<2'b10); + end + 6'b000111: begin + i1modkByteEn <= ~(256'b0) >> (6'b000111<<2'b10); + end + 6'b001000: begin + i1modkByteEn <= ~(256'b0) >> (6'b001000<<2'b10); + end + 6'b001001: begin + i1modkByteEn <= ~(256'b0) >> (6'b001001<<2'b10); + end + 6'b001010: begin + i1modkByteEn <= ~(256'b0) >> (6'b001010<<2'b10); + end + 6'b001011: begin + i1modkByteEn <= ~(256'b0) >> (6'b001011<<2'b10); + end + 6'b001100: begin + i1modkByteEn <= ~(256'b0) >> (6'b001100<<2'b10); + end + 6'b001101: begin + i1modkByteEn <= ~(256'b0) >> (6'b001101<<2'b10); + end + 6'b001110: begin + i1modkByteEn <= ~(256'b0) >> (6'b001110<<2'b10); + end + 6'b001111: begin + i1modkByteEn <= ~(256'b0) >> (6'b001111<<2'b10); + end + 6'b010000: begin + i1modkByteEn <= ~(256'b0) >> (6'b010000<<2'b10); + end + 6'b010001: begin + i1modkByteEn <= ~(256'b0) >> (6'b010001<<2'b10); + end + 6'b010010: begin + i1modkByteEn <= ~(256'b0) >> (6'b010010<<2'b10); + end + 6'b010011: begin + i1modkByteEn <= ~(256'b0) >> (6'b010011<<2'b10); + end + 6'b010100: begin + i1modkByteEn <= ~(256'b0) >> (6'b010100<<2'b10); + end + 6'b010101: begin + i1modkByteEn <= ~(256'b0) >> (6'b010101<<2'b10); + end + 6'b010110: begin + i1modkByteEn <= ~(256'b0) >> (6'b010110<<2'b10); + end + 6'b010111: begin + i1modkByteEn <= ~(256'b0) >> (6'b010111<<2'b10); + end + 6'b011000: begin + i1modkByteEn <= ~(256'b0) >> (6'b011000<<2'b10); + end + 6'b011001: begin + i1modkByteEn <= ~(256'b0) >> (6'b011001<<2'b10); + end + 6'b011010: begin + i1modkByteEn <= ~(256'b0) >> (6'b011010<<2'b10); + end + 6'b011011: begin + i1modkByteEn <= ~(256'b0) >> (6'b011011<<2'b10); + end + 6'b011100: begin + i1modkByteEn <= ~(256'b0) >> (6'b011100<<2'b10); + end + 6'b011101: begin + i1modkByteEn <= ~(256'b0) >> (6'b011101<<2'b10); + end + 6'b011110: begin + i1modkByteEn <= ~(256'b0) >> (6'b011110<<2'b10); + end + 6'b011111: begin + i1modkByteEn <= ~(256'b0) >> (6'b011111<<2'b10); + end + 6'b100000: begin + i1modkByteEn <= ~(256'b0) >> (6'b100000<<2'b10); + end + 6'b100001: begin + i1modkByteEn <= ~(256'b0) >> (6'b100001<<2'b10); + end + 6'b100010: begin + i1modkByteEn <= ~(256'b0) >> (6'b100010<<2'b10); + end + 6'b100011: begin + i1modkByteEn <= ~(256'b0) >> (6'b100011<<2'b10); + end + 6'b100100: begin + i1modkByteEn <= ~(256'b0) >> (6'b100100<<2'b10); + end + 6'b100101: begin + i1modkByteEn <= ~(256'b0) >> (6'b100101<<2'b10); + end + 6'b100110: begin + i1modkByteEn <= ~(256'b0) >> (6'b100110<<2'b10); + end + 6'b100111: begin + i1modkByteEn <= ~(256'b0) >> (6'b100111<<2'b10); + end + 6'b101000: begin + i1modkByteEn <= ~(256'b0) >> (6'b101000<<2'b10); + end + 6'b101001: begin + i1modkByteEn <= ~(256'b0) >> (6'b101001<<2'b10); + end + 6'b101010: begin + i1modkByteEn <= ~(256'b0) >> (6'b101010<<2'b10); + end + 6'b101011: begin + i1modkByteEn <= ~(256'b0) >> (6'b101011<<2'b10); + end + 6'b101100: begin + i1modkByteEn <= ~(256'b0) >> (6'b101100<<2'b10); + end + 6'b101101: begin + i1modkByteEn <= ~(256'b0) >> (6'b101101<<2'b10); + end + 6'b101110: begin + i1modkByteEn <= ~(256'b0) >> (6'b101110<<2'b10); + end + 6'b101111: begin + i1modkByteEn <= ~(256'b0) >> (6'b101111<<2'b10); + end + 6'b110000: begin + i1modkByteEn <= ~(256'b0) >> (6'b110000<<2'b10); + end + 6'b110001: begin + i1modkByteEn <= ~(256'b0) >> (6'b110001<<2'b10); + end + 6'b110010: begin + i1modkByteEn <= ~(256'b0) >> (6'b110010<<2'b10); + end + 6'b110011: begin + i1modkByteEn <= ~(256'b0) >> (6'b110011<<2'b10); + end + 6'b110100: begin + i1modkByteEn <= ~(256'b0) >> (6'b110100<<2'b10); + end + 6'b110101: begin + i1modkByteEn <= ~(256'b0) >> (6'b110101<<2'b10); + end + 6'b110110: begin + i1modkByteEn <= ~(256'b0) >> (6'b110110<<2'b10); + end + 6'b110111: begin + i1modkByteEn <= ~(256'b0) >> (6'b110111<<2'b10); + end + 6'b111000: begin + i1modkByteEn <= ~(256'b0) >> (6'b111000<<2'b10); + end + 6'b111001: begin + i1modkByteEn <= ~(256'b0) >> (6'b111001<<2'b10); + end + 6'b111010: begin + i1modkByteEn <= ~(256'b0) >> (6'b111010<<2'b10); + end + 6'b111011: begin + i1modkByteEn <= ~(256'b0) >> (6'b111011<<2'b10); + end + 6'b111100: begin + i1modkByteEn <= ~(256'b0) >> (6'b111100<<2'b10); + end + 6'b111101: begin + i1modkByteEn <= ~(256'b0) >> (6'b111101<<2'b10); + end + 6'b111110: begin + i1modkByteEn <= ~(256'b0) >> (6'b111110<<2'b10); + end + 6'b111111: begin + i1modkByteEn <= ~(256'b0) >> (6'b111111<<2'b10); + end + default: begin + i1modkByteEn <= ~(256'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 16384, TOPSIZEWIDTH = 14, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [14-1:0] rdaddress; + input [14-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 512 +`define rFIFOSIZEWIDTH 9 +`define rFIFOOUTPUTWIDTH 2048 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 13'b0100000000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 5'b01001 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 5'b01000 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 13'b0100000000000 +`define DATANUMBYTES 10'b0100000000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define RATIO 7'b0100000 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [7:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [5:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[2047:1984]; +assign mem_data[63:0] = ram_read_dataw[2047:1984]; +assign ram_write_dataw[127:64] = rdata[1983:1920]; +assign mem_data[127:64] = ram_read_dataw[1983:1920]; +assign ram_write_dataw[191:128] = rdata[1919:1856]; +assign mem_data[191:128] = ram_read_dataw[1919:1856]; +assign ram_write_dataw[255:192] = rdata[1855:1792]; +assign mem_data[255:192] = ram_read_dataw[1855:1792]; +assign ram_write_dataw[319:256] = rdata[1791:1728]; +assign mem_data[319:256] = ram_read_dataw[1791:1728]; +assign ram_write_dataw[383:320] = rdata[1727:1664]; +assign mem_data[383:320] = ram_read_dataw[1727:1664]; +assign ram_write_dataw[447:384] = rdata[1663:1600]; +assign mem_data[447:384] = ram_read_dataw[1663:1600]; +assign ram_write_dataw[511:448] = rdata[1599:1536]; +assign mem_data[511:448] = ram_read_dataw[1599:1536]; +assign ram_write_dataw[575:512] = rdata[1535:1472]; +assign mem_data[575:512] = ram_read_dataw[1535:1472]; +assign ram_write_dataw[639:576] = rdata[1471:1408]; +assign mem_data[639:576] = ram_read_dataw[1471:1408]; +assign ram_write_dataw[703:640] = rdata[1407:1344]; +assign mem_data[703:640] = ram_read_dataw[1407:1344]; +assign ram_write_dataw[767:704] = rdata[1343:1280]; +assign mem_data[767:704] = ram_read_dataw[1343:1280]; +assign ram_write_dataw[831:768] = rdata[1279:1216]; +assign mem_data[831:768] = ram_read_dataw[1279:1216]; +assign ram_write_dataw[895:832] = rdata[1215:1152]; +assign mem_data[895:832] = ram_read_dataw[1215:1152]; +assign ram_write_dataw[959:896] = rdata[1151:1088]; +assign mem_data[959:896] = ram_read_dataw[1151:1088]; +assign ram_write_dataw[1023:960] = rdata[1087:1024]; +assign mem_data[1023:960] = ram_read_dataw[1087:1024]; +assign ram_write_dataw[1087:1024] = rdata[1023:960]; +assign mem_data[1087:1024] = ram_read_dataw[1023:960]; +assign ram_write_dataw[1151:1088] = rdata[959:896]; +assign mem_data[1151:1088] = ram_read_dataw[959:896]; +assign ram_write_dataw[1215:1152] = rdata[895:832]; +assign mem_data[1215:1152] = ram_read_dataw[895:832]; +assign ram_write_dataw[1279:1216] = rdata[831:768]; +assign mem_data[1279:1216] = ram_read_dataw[831:768]; +assign ram_write_dataw[1343:1280] = rdata[767:704]; +assign mem_data[1343:1280] = ram_read_dataw[767:704]; +assign ram_write_dataw[1407:1344] = rdata[703:640]; +assign mem_data[1407:1344] = ram_read_dataw[703:640]; +assign ram_write_dataw[1471:1408] = rdata[639:576]; +assign mem_data[1471:1408] = ram_read_dataw[639:576]; +assign ram_write_dataw[1535:1472] = rdata[575:512]; +assign mem_data[1535:1472] = ram_read_dataw[575:512]; +assign ram_write_dataw[1599:1536] = rdata[511:448]; +assign mem_data[1599:1536] = ram_read_dataw[511:448]; +assign ram_write_dataw[1663:1600] = rdata[447:384]; +assign mem_data[1663:1600] = ram_read_dataw[447:384]; +assign ram_write_dataw[1727:1664] = rdata[383:320]; +assign mem_data[1727:1664] = ram_read_dataw[383:320]; +assign ram_write_dataw[1791:1728] = rdata[319:256]; +assign mem_data[1791:1728] = ram_read_dataw[319:256]; +assign ram_write_dataw[1855:1792] = rdata[255:192]; +assign mem_data[1855:1792] = ram_read_dataw[255:192]; +assign ram_write_dataw[1919:1856] = rdata[191:128]; +assign mem_data[1919:1856] = ram_read_dataw[191:128]; +assign ram_write_dataw[1983:1920] = rdata[127:64]; +assign mem_data[1983:1920] = ram_read_dataw[127:64]; +assign ram_write_dataw[2047:1984] = rdata[63:0]; +assign mem_data[2047:1984] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[2047:0]; +assign ram_read_dataw[2047:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[4:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 10'b0000000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +else if (counter == 4) + q[319:256] <= data_ram; +else if (counter == 5) + q[383:320] <= data_ram; +else if (counter == 6) + q[447:384] <= data_ram; +else if (counter == 7) + q[511:448] <= data_ram; +else if (counter == 8) + q[575:512] <= data_ram; +else if (counter == 9) + q[639:576] <= data_ram; +else if (counter == 10) + q[703:640] <= data_ram; +else if (counter == 11) + q[767:704] <= data_ram; +else if (counter == 12) + q[831:768] <= data_ram; +else if (counter == 13) + q[895:832] <= data_ram; +else if (counter == 14) + q[959:896] <= data_ram; +else if (counter == 15) + q[1023:960] <= data_ram; +else if (counter == 16) + q[1087:1024] <= data_ram; +else if (counter == 17) + q[1151:1088] <= data_ram; +else if (counter == 18) + q[1215:1152] <= data_ram; +else if (counter == 19) + q[1279:1216] <= data_ram; +else if (counter == 20) + q[1343:1280] <= data_ram; +else if (counter == 21) + q[1407:1344] <= data_ram; +else if (counter == 22) + q[1471:1408] <= data_ram; +else if (counter == 23) + q[1535:1472] <= data_ram; +else if (counter == 24) + q[1599:1536] <= data_ram; +else if (counter == 25) + q[1663:1600] <= data_ram; +else if (counter == 26) + q[1727:1664] <= data_ram; +else if (counter == 27) + q[1791:1728] <= data_ram; +else if (counter == 28) + q[1855:1792] <= data_ram; +else if (counter == 29) + q[1919:1856] <= data_ram; +else if (counter == 30) + q[1983:1920] <= data_ram; +else if (counter == 31) + q[2047:1984] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[4:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 2048'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +else if(counter == 4) + q <= data_ram[319:256]; +else if(counter == 5) + q <= data_ram[383:320]; +else if(counter == 6) + q <= data_ram[447:384]; +else if(counter == 7) + q <= data_ram[511:448]; +else if(counter == 8) + q <= data_ram[575:512]; +else if(counter == 9) + q <= data_ram[639:576]; +else if(counter == 10) + q <= data_ram[703:640]; +else if(counter == 11) + q <= data_ram[767:704]; +else if(counter == 12) + q <= data_ram[831:768]; +else if(counter == 13) + q <= data_ram[895:832]; +else if(counter == 14) + q <= data_ram[959:896]; +else if(counter == 15) + q <= data_ram[1023:960]; +else if(counter == 16) + q <= data_ram[1087:1024]; +else if(counter == 17) + q <= data_ram[1151:1088]; +else if(counter == 18) + q <= data_ram[1215:1152]; +else if(counter == 19) + q <= data_ram[1279:1216]; +else if(counter == 20) + q <= data_ram[1343:1280]; +else if(counter == 21) + q <= data_ram[1407:1344]; +else if(counter == 22) + q <= data_ram[1471:1408]; +else if(counter == 23) + q <= data_ram[1535:1472]; +else if(counter == 24) + q <= data_ram[1599:1536]; +else if(counter == 25) + q <= data_ram[1663:1600]; +else if(counter == 26) + q <= data_ram[1727:1664]; +else if(counter == 27) + q <= data_ram[1791:1728]; +else if(counter == 28) + q <= data_ram[1855:1792]; +else if(counter == 29) + q <= data_ram[1919:1856]; +else if(counter == 30) + q <= data_ram[1983:1920]; +else if(counter == 31) + q <= data_ram[2047:1984]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 8'b00000000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v new file mode 100755 index 000000000..489ecaa78 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v @@ -0,0 +1,5277 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0101 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 10'b0100000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 4'b0101 + +module LU8PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 6'b010000 +`define BLOCKN 6'b010000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 5'b01000 +`define MEMBLOCKN 5'b01000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0101 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 4'b0101 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 5'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 5'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 5'b0; + ram_addr <= 5'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>4)<<3; + mem_N <= Ndivk<<4; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 5 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 5'b01000 +`define PEWIDTH 3'b011 +`define BLOCKWIDTH 4'b0101 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define TOPSIZEWIDTH 5'b01000 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[255:224]; + 1: + topWriteDataLU = curReadDataLU[223:192]; + 2: + topWriteDataLU = curReadDataLU[191:160]; + 3: + topWriteDataLU = curReadDataLU[159:128]; + 4: + topWriteDataLU = curReadDataLU[127:96]; + 5: + topWriteDataLU = curReadDataLU[95:64]; + 6: + topWriteDataLU = curReadDataLU[63:32]; + 7: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult7; + 1: + topWriteDataLU = addResult6; + 2: + topWriteDataLU = addResult5; + 3: + topWriteDataLU = addResult4; + 4: + topWriteDataLU = addResult3; + 5: + topWriteDataLU = addResult2; + 6: + topWriteDataLU = addResult1; + 7: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[5-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[32-1:0] curWriteByteEn; +output[5-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[32-1:0] leftWriteByteEn; +output[5-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[8-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[3-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[5-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[5-1:0] i1, j; +reg[8-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[5-1:0] diagIdx, leftIdx, msIdx; +reg[3-1:0] imodk, i1modk; +reg[5-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[32-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[32-1:0] curWriteByteEn; +reg[5-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[32-1:0] leftWriteByteEn; +reg[5-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[8-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[3-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[5-1:0] counter; +reg[6-1:0] divCounter; + +reg[32-1:0]writeByteEnDelay0; +reg[32-1:0]writeByteEnDelay1; +reg[32-1:0]writeByteEnDelay2; +reg[32-1:0]writeByteEnDelay3; +reg[32-1:0]writeByteEnDelay4; +reg[32-1:0]writeByteEnDelay5; +reg[32-1:0]writeByteEnDelay6; +reg[32-1:0]writeByteEnDelay7; +reg[32-1:0]writeByteEnDelay8; +reg[32-1:0]writeByteEnDelay9; +reg[32-1:0]writeByteEnDelay10; +reg[32-1:0]writeByteEnDelay11; +reg[32-1:0]writeByteEnDelay12; +reg[32-1:0]writeByteEnDelay13; +reg[32-1:0]writeByteEnDelay14; +reg[32-1:0]writeByteEnDelay15; +reg[32-1:0]writeByteEnDelay16; +reg[32-1:0]writeByteEnDelay17; +reg[32-1:0]writeByteEnDelay18; +reg[32-1:0]writeByteEnDelay19; +reg[32-1:0]writeByteEnDelay20; +reg[32-1:0]writeByteEnDelay21; +reg[32-1:0]writeByteEnDelay22; +reg[32-1:0]writeByteEnDelay23; +reg[32-1:0]writeByteEnDelay24; +reg[32-1:0]writeByteEnDelay25; +reg[32-1:0]writeByteEnDelay26; +reg[32-1:0]writeByteEnDelay27; +reg[32-1:0]writeByteEnDelay28; +reg[32-1:0]writeByteEnDelay29; +reg[32-1:0]writeByteEnDelay30; +reg[32-1:0]writeByteEnDelay31; + +reg[5-1:0]curWriteAddrDelay0; +reg[5-1:0]curWriteAddrDelay1; +reg[5-1:0]curWriteAddrDelay2; +reg[5-1:0]curWriteAddrDelay3; +reg[5-1:0]curWriteAddrDelay4; +reg[5-1:0]curWriteAddrDelay5; +reg[5-1:0]curWriteAddrDelay6; +reg[5-1:0]curWriteAddrDelay7; +reg[5-1:0]curWriteAddrDelay8; +reg[5-1:0]curWriteAddrDelay9; +reg[5-1:0]curWriteAddrDelay10; +reg[5-1:0]curWriteAddrDelay11; +reg[5-1:0]curWriteAddrDelay12; +reg[5-1:0]curWriteAddrDelay13; +reg[5-1:0]curWriteAddrDelay14; +reg[5-1:0]curWriteAddrDelay15; +reg[5-1:0]curWriteAddrDelay16; +reg[5-1:0]curWriteAddrDelay17; +reg[5-1:0]curWriteAddrDelay18; +reg[5-1:0]curWriteAddrDelay19; +reg[5-1:0]curWriteAddrDelay20; +reg[5-1:0]curWriteAddrDelay21; +reg[5-1:0]curWriteAddrDelay22; +reg[5-1:0]curWriteAddrDelay23; +reg[5-1:0]curWriteAddrDelay24; +reg[5-1:0]curWriteAddrDelay25; +reg[5-1:0]curWriteAddrDelay26; +reg[5-1:0]curWriteAddrDelay27; +reg[5-1:0]curWriteAddrDelay28; +reg[5-1:0]curWriteAddrDelay29; +reg[5-1:0]curWriteAddrDelay30; +reg[5-1:0]curWriteAddrDelay31; + +reg[5-1:0]curReadAddrDelay0; +reg[5-1:0]curReadAddrDelay1; +reg[5-1:0]curReadAddrDelay2; +reg[5-1:0]curReadAddrDelay3; +reg[5-1:0]curReadAddrDelay4; +reg[5-1:0]curReadAddrDelay5; +reg[5-1:0]curReadAddrDelay6; +reg[5-1:0]curReadAddrDelay7; +reg[5-1:0]curReadAddrDelay8; +reg[5-1:0]curReadAddrDelay9; +reg[5-1:0]curReadAddrDelay10; +reg[5-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[5-1:0]leftReadAddrDelay0; +reg[8-1:0]topWriteAddrDelay0; +reg[8-1:0]topWriteAddrDelay1; +reg[8-1:0]topWriteAddrDelay2; +reg[8-1:0]topWriteAddrDelay3; +reg[8-1:0]topWriteAddrDelay4; +reg[8-1:0]topWriteAddrDelay5; +reg[8-1:0]topWriteAddrDelay6; +reg[8-1:0]topWriteAddrDelay7; +reg[8-1:0]topWriteAddrDelay8; +reg[8-1:0]topWriteAddrDelay9; +reg[8-1:0]topWriteAddrDelay10; +reg[8-1:0]topWriteAddrDelay11; +reg[8-1:0]topWriteAddrDelay12; +reg[8-1:0]topWriteAddrDelay13; +reg[8-1:0]topWriteAddrDelay14; +reg[8-1:0]topWriteAddrDelay15; +reg[8-1:0]topWriteAddrDelay16; +reg[8-1:0]topWriteAddrDelay17; +reg[8-1:0]topWriteAddrDelay18; +reg[8-1:0]topWriteAddrDelay19; +reg[8-1:0]topWriteAddrDelay20; +reg[8-1:0]topWriteAddrDelay21; +reg[8-1:0]topWriteAddrDelay22; +reg[8-1:0]topWriteAddrDelay23; +reg[8-1:0]topWriteAddrDelay24; +reg[8-1:0]topWriteAddrDelay25; +reg[8-1:0]topWriteAddrDelay26; +reg[8-1:0]topWriteAddrDelay27; +reg[8-1:0]topWriteAddrDelay28; +reg[8-1:0]topWriteAddrDelay29; +reg[8-1:0]topWriteAddrDelay30; +reg[8-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[3-1:0]topWriteSelDelay0; +reg[3-1:0]topWriteSelDelay1; +reg[3-1:0]topWriteSelDelay2; +reg[3-1:0]topWriteSelDelay3; +reg[3-1:0]topWriteSelDelay4; +reg[3-1:0]topWriteSelDelay5; +reg[3-1:0]topWriteSelDelay6; +reg[3-1:0]topWriteSelDelay7; +reg[3-1:0]topWriteSelDelay8; +reg[3-1:0]topWriteSelDelay9; +reg[3-1:0]topWriteSelDelay10; +reg[3-1:0]topWriteSelDelay11; +reg[3-1:0]topWriteSelDelay12; +reg[3-1:0]topWriteSelDelay13; +reg[3-1:0]topWriteSelDelay14; +reg[3-1:0]topWriteSelDelay15; +reg[3-1:0]topWriteSelDelay16; +reg[3-1:0]topWriteSelDelay17; +reg[3-1:0]topWriteSelDelay18; +reg[3-1:0]topWriteSelDelay19; +reg[3-1:0]topWriteSelDelay20; +reg[3-1:0]topWriteSelDelay21; +reg[3-1:0]topWriteSelDelay22; +reg[3-1:0]topWriteSelDelay23; +reg[3-1:0]topWriteSelDelay24; +reg[3-1:0]topWriteSelDelay25; +reg[3-1:0]topWriteSelDelay26; +reg[3-1:0]topWriteSelDelay27; +reg[3-1:0]topWriteSelDelay28; +reg[3-1:0]topWriteSelDelay29; +reg[3-1:0]topWriteSelDelay30; +reg[3-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [5-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+8-1)>>3; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 8-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 5'b00000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 8-1 && mode == 2'b00) || (i1modk == 8-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 5'b00000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 8-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 5'b00000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 3'b000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 8-1) + imodk <= 3'b000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 3'b001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 8-1) + i1modk <= 3'b000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 8'b00000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 8'b00000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 5'b00001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 5'b00000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 5'b00000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 8-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >5'b00000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 3'b000: begin + i1modkByteEn <= ~(32'b0) >> (3'b000<<2'b10); + end + 3'b001: begin + i1modkByteEn <= ~(32'b0) >> (3'b001<<2'b10); + end + 3'b010: begin + i1modkByteEn <= ~(32'b0) >> (3'b010<<2'b10); + end + 3'b011: begin + i1modkByteEn <= ~(32'b0) >> (3'b011<<2'b10); + end + 3'b100: begin + i1modkByteEn <= ~(32'b0) >> (3'b100<<2'b10); + end + 3'b101: begin + i1modkByteEn <= ~(32'b0) >> (3'b101<<2'b10); + end + 3'b110: begin + i1modkByteEn <= ~(32'b0) >> (3'b110<<2'b10); + end + 3'b111: begin + i1modkByteEn <= ~(32'b0) >> (3'b111<<2'b10); + end + default: begin + i1modkByteEn <= ~(32'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 32'b11111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 256, TOPSIZEWIDTH = 8, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [8-1:0] rdaddress; + input [8-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram_256x32 inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 64 +`define rFIFOSIZEWIDTH 6 +`define rFIFOOUTPUTWIDTH 256 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 10'b0100000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 4'b0110 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 4'b0101 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 10'b0100000000 +`define DATANUMBYTES 7'b0100000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define RATIO 4'b0100 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [4:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [2:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[255:192]; +assign mem_data[63:0] = ram_read_dataw[255:192]; +assign ram_write_dataw[127:64] = rdata[191:128]; +assign mem_data[127:64] = ram_read_dataw[191:128]; +assign ram_write_dataw[191:128] = rdata[127:64]; +assign mem_data[191:128] = ram_read_dataw[127:64]; +assign ram_write_dataw[255:192] = rdata[63:0]; +assign mem_data[255:192] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[255:0]; +assign ram_read_dataw[255:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[1:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 7'b0000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram_rfifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[1:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 256'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram_wfifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 5'b00000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram_afifo ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram_mfifo ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule + +//--------------------------------------- +// A dual-port RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram ( + input clk, + input we1, + input we2, + input [`rRAMSIZEWIDTH - 1 : 0] addr1, + input [`RAMWIDTH - 1 : 0] data1, + output [`RAMWIDTH - 1 : 0] out1, + input [`rRAMSIZEWIDTH - 1 : 0] addr2, + input [`RAMWIDTH - 1 : 0] data2, + output [`RAMWIDTH - 1 : 0] out2 +); + reg [`RAMWIDTH - 1 : 0] ram[2**`rRAMSIZEWIDTH - 1 : 0]; + reg [`RAMWIDTH - 1 : 0] data_out1; + reg [`RAMWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 256x32 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_256x32 ( + input clk, + input we1, + input we2, + input [8 - 1 : 0] addr1, + input [32 - 1 : 0] data1, + output [32 - 1 : 0] out1, + input [8- 1 : 0] addr2, + input [32 - 1 : 0] data2, + output [32 - 1 : 0] out2 +); + reg [32 - 1 : 0] ram[2**8 - 1 : 0]; + reg [32 - 1 : 0] data_out1; + reg [32 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM rFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_rfifo ( + input clk, + input we1, + input we2, + input [`rFIFOSIZEWIDTH - 1 : 0] addr1, + input [`rFIFOINPUTWIDTH - 1 : 0] data1, + output [`rFIFOINPUTWIDTH - 1 : 0] out1, + input [`rFIFOSIZEWIDTH - 1 : 0] addr2, + input [`rFIFOINPUTWIDTH - 1 : 0] data2, + output [`rFIFOINPUTWIDTH - 1 : 0] out2 +); + reg [`rFIFOINPUTWIDTH - 1 : 0] ram[2**`rFIFOSIZEWIDTH - 1 : 0]; + reg [`rFIFOINPUTWIDTH - 1 : 0] data_out1; + reg [`rFIFOINPUTWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM wFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_wfifo ( + input clk, + input we1, + input we2, + input [`wFIFOSIZEWIDTH - 1 : 0] addr1, + input [`wFIFOINPUTWIDTH - 1 : 0] data1, + output [`wFIFOINPUTWIDTH - 1 : 0] out1, + input [`wFIFOSIZEWIDTH - 1 : 0] addr2, + input [`wFIFOINPUTWIDTH - 1 : 0] data2, + output [`wFIFOINPUTWIDTH - 1 : 0] out2 +); + reg [`wFIFOINPUTWIDTH - 1 : 0] ram[2**`wFIFOSIZEWIDTH - 1 : 0]; + reg [`wFIFOINPUTWIDTH - 1 : 0] data_out1; + reg [`wFIFOINPUTWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM wFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_afifo ( + input clk, + input we1, + input we2, + input [`aFIFOSIZEWIDTH - 1 : 0] addr1, + input [`aFIFOWIDTH - 1 : 0] data1, + output [`aFIFOWIDTH - 1 : 0] out1, + input [`aFIFOSIZEWIDTH - 1 : 0] addr2, + input [`aFIFOWIDTH - 1 : 0] data2, + output [`aFIFOWIDTH - 1 : 0] out2 +); + reg [`aFIFOWIDTH - 1 : 0] ram[2**`aFIFOSIZEWIDTH - 1 : 0]; + reg [`aFIFOWIDTH - 1 : 0] data_out1; + reg [`aFIFOWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM mFIFO +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_mfifo ( + input clk, + input we1, + input we2, + input [`mFIFOSIZEWIDTH - 1 : 0] addr1, + input [`mFIFOWIDTH - 1 : 0] data1, + output [`mFIFOWIDTH - 1 : 0] out1, + input [`mFIFOSIZEWIDTH - 1 : 0] addr2, + input [`mFIFOWIDTH - 1 : 0] data2, + output [`mFIFOWIDTH - 1 : 0] out2 +); + reg [`mFIFOWIDTH - 1 : 0] ram[2**`mFIFOSIZEWIDTH - 1 : 0]; + reg [`mFIFOWIDTH - 1 : 0] data_out1; + reg [`mFIFOWIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v b/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v new file mode 100644 index 000000000..c290fc893 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v @@ -0,0 +1,8210 @@ + + +module single_port_ram_21_8( + clk, + data, + we, + addr, + out + ); +`define ADDR_WIDTH_21_8 8 +`define DATA_WIDTH_21_8 21 + + input clk; + input [`DATA_WIDTH_21_8-1:0] data; + input we; + input [`ADDR_WIDTH_21_8-1:0] addr; + + + output [`DATA_WIDTH_21_8-1:0] out; + reg [`DATA_WIDTH_21_8-1:0] out; + + reg [`DATA_WIDTH_21_8-1:0] RAM[255:0]; + + always @ (posedge clk) + begin + if (we) + begin + RAM[addr] <= data; + out <= RAM[addr]; + end + end + +endmodule + + + +module single_port_ram_128_8( + clk, + data, + we, + addr, + out + ); +`define ADDR_WIDTH_128_8 8 +`define DATA_WIDTH_128_8 128 + + input clk; + input [`DATA_WIDTH_128_8-1:0] data; + input we; + input [`ADDR_WIDTH_128_8-1:0] addr; + + + output [`DATA_WIDTH_128_8-1:0] out; + reg [`DATA_WIDTH_128_8-1:0] out; + + reg [`DATA_WIDTH_128_8-1:0] RAM[255:0]; + + always @ (posedge clk) + begin + if (we) + begin + RAM[addr] <= data; + out <= RAM[addr]; + end + end + +endmodule + + + +module a25_icache + + + ( + i_clk, + i_core_stall, + o_stall, + + i_select, + i_address, + i_address_nxt, + i_cache_enable, + i_cache_flush, + o_read_data, + + o_wb_req, + i_wb_read_data, + i_wb_ready + ); + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + +`ifndef _A25_CONFIG_DEFINES +`define _A25_CONFIG_DEFINES + + + +`define A25_ICACHE_WAYS 4 +`define A25_DCACHE_WAYS 4 + +`endif + +parameter CACHE_LINES = 256; + +// This cannot be changed without some major surgeory on +// this module +parameter CACHE_WORDS_PER_LINE = 4; + + +parameter WAYS = `A25_ICACHE_WAYS; + + +parameter CACHE_ADDR_WIDTH = 8; // = 8 +parameter WORD_SEL_WIDTH = 2; // = 2 +parameter TAG_ADDR_WIDTH = 20; // = 20 +parameter TAG_WIDTH = 21; // = 21, including Valid flag +parameter CACHE_LINE_WIDTH = 128; // = 128 +parameter TAG_ADDR32_LSB = 12; // = 12 +parameter CACHE_ADDR32_MSB = 11; // = 11 +parameter CACHE_ADDR32_LSB = 4; // = 4 +parameter WORD_SEL_MSB = 3; // = 3 +parameter WORD_SEL_LSB = 2; // = 2 +// --------------------------------------------------------- + + +input i_clk; +input i_core_stall; +output o_stall; + +// Read / Write requests from core +input i_select; +input [31:0] i_address; // registered address from execute +input [31:0] i_address_nxt; // un-registered version of address from execute stage +input i_cache_enable; // from co-processor 15 configuration register +input i_cache_flush; // from co-processor 15 register + +output [127:0] o_read_data; + +// WB Read Request +output o_wb_req; // Read Request +input [127:0] i_wb_read_data; +input i_wb_ready; + + +// One-hot encoded +localparam C_INIT = 0, + C_CORE = 1, + C_FILL = 2, + C_INVA = 3, + C_STATES = 4; + +localparam [3:0] CS_INIT = 4'd0, + CS_IDLE = 4'd1, + CS_FILL0 = 4'd2, + CS_FILL1 = 4'd3, + CS_FILL2 = 4'd4, + CS_FILL3 = 4'd5, + CS_FILL4 = 4'd6, + CS_FILL_COMPLETE = 4'd7, + CS_TURN_AROUND = 4'd8, + CS_WRITE_HIT1 = 4'd9, + CS_EX_DELETE = 4'd10; + +//reg o_wb_req; //jing+ +//reg o_stall; //jing+ +//reg [127:0] o_read_data; //jing+ + +reg [3:0] c_state = 4'd1 ; // c_state = CS_IDLE +reg [C_STATES-1:0] source_sel = 4'b10; //1'd1 << C_CORE +reg [CACHE_ADDR_WIDTH:0] init_count = 9'd0; + +wire [TAG_WIDTH-1:0] tag_rdata_way0; +wire [TAG_WIDTH-1:0] tag_rdata_way1; +wire [TAG_WIDTH-1:0] tag_rdata_way2; +wire [TAG_WIDTH-1:0] tag_rdata_way3; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way0; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way1; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way2; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way3; +wire [WAYS-1:0] data_wenable_way; +wire [WAYS-1:0] data_hit_way; +wire [WAYS-1:0] tag_wenable_way; +reg [WAYS-1:0] select_way = 4'd0; +wire [WAYS-1:0] next_way; +reg [WAYS-1:0] valid_bits_r = 4'd0; + +reg [3:0] random_num = 4'hf; + +wire [CACHE_ADDR_WIDTH-1:0] tag_address; +wire [TAG_WIDTH-1:0] tag_wdata; +wire tag_wenable; + +wire [CACHE_ADDR_WIDTH-1:0] data_address; +wire [31:0] write_data_word; + +wire idle_hit; +reg read_miss; //jing +wire read_miss_fill; +wire invalid_read; +wire fill_state; + +reg [31:0] miss_address = 32'd0; +wire [CACHE_LINE_WIDTH-1:0] hit_rdata; + +wire cache_busy_stall; +wire read_stall; + +wire enable; +wire [CACHE_ADDR_WIDTH-1:0] address; +wire [31:0] address_c; +reg [31:0] address_r = 32'd0; + +reg [31:0] wb_address = 32'd0; +wire wb_hit; //jing - add wire -> reg +wire read_buf_hit; //jing - add wire -> reg +reg [127:0] read_buf_data_r; +reg [31:0] read_buf_addr_r; +reg read_buf_valid_r; +//genvar i; + +// ====================================== +// Address to use for cache access +// ====================================== +// If currently stalled then the address for the next +// cycle will be the same as it is in the current cycle +// +assign address_c = i_core_stall ? i_address : + i_address_nxt; + +assign address = address_c[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB]; + + +// ====================================== +// Outputs +// ====================================== +assign o_read_data = wb_hit ? i_wb_read_data : + read_buf_hit ? read_buf_data_r : + hit_rdata ; + + +// Don't allow the cache to stall the wb i/f for an exclusive access +// The cache needs a couple of cycles to flush a potential copy of the exclusive +// address, but the wb can do the access in parallel. So there is no +// stall in the state CS_EX_DELETE, even though the cache is out of action. +// This works fine as long as the wb is stalling the core +//assign o_stall = read_stall || cache_busy_stall; +always @ ( posedge i_clk ) + o_stall <= read_stall || cache_busy_stall; + +assign o_wb_req = read_miss && c_state == CS_IDLE; + + +// ====================================== +// Read Buffer +// ====================================== +always@(posedge i_clk) + if ( i_cache_flush ) + read_buf_valid_r <= 1'd0; + else if (i_wb_ready && c_state == CS_FILL3) + begin + read_buf_data_r <= i_wb_read_data; + read_buf_addr_r <= miss_address; + read_buf_valid_r <= 1'd1; + end + else if (o_wb_req) + read_buf_valid_r <= 1'd0; + + +assign read_buf_hit = read_buf_valid_r && i_address[31:4] == read_buf_addr_r[31:4]; + +// ====================================== +// Cache State Machine +// ====================================== + +// Little State Machine to Flush Tag RAMS +always @ ( posedge i_clk ) + if ( i_cache_flush ) + begin + c_state <= CS_INIT; + source_sel <= 4'd1; //1'd1 << C_INIT + init_count <= 9'd0; + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache Flush"); + `endif + end + else + case ( c_state ) + CS_INIT : + if ( init_count < CACHE_LINES ) + begin + init_count <= init_count + 1'd1; + source_sel <= 4'b1; //1'd1 << C_INIT + end + else + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + CS_IDLE : + begin + source_sel <= 4'b10; //1'd1 << C_CORE + + if ( read_miss ) + c_state <= CS_FILL3; + end + + + CS_FILL3 : + begin + // Pick a way to write the cache update into + // Either pick one of the invalid caches, or if all are valid, then pick + // one randomly + select_way <= next_way; + random_num <= {random_num[2], random_num[1], random_num[0], + random_num[3]^random_num[2]}; + + // third read of burst of 4 + // wb read request asserted, wait for ack + if ( i_wb_ready ) + begin + c_state <= CS_FILL_COMPLETE; + end + end + + + // Write the read fetch data in this cycle + CS_FILL_COMPLETE : + begin + // Back to normal cache operations, but + // use physical address for first read as + // address moved before the stall was asserted for the read_miss + // However don't use it if its a non-cached address! + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + + // Ignore the tag read data in this cycle + // Wait 1 cycle to pre-read the cache and return to normal operation + CS_TURN_AROUND : + begin + c_state <= CS_IDLE; + end + + endcase + + +// ====================================== +// Miss Address +// ====================================== +always @ ( posedge i_clk ) + if ( c_state == CS_IDLE ) + miss_address <= i_address; + + +always @ ( posedge i_clk ) + address_r <= address_c; + +assign invalid_read = address_r != i_address; + + +always @(posedge i_clk) + if ( o_wb_req ) + wb_address <= i_address; + else if ( i_wb_ready && fill_state ) + wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0}; + +assign fill_state = c_state == CS_FILL3; +assign wb_hit = i_address == wb_address && i_wb_ready && fill_state; + +assign tag_address = read_miss_fill ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] : + address ; + + +assign data_address = read_miss_fill ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + address ; + + +assign tag_wdata = read_miss_fill ? {1'd1, miss_address[31:12]} : // [31:TAG_ADDR32_LSB] + 21'd0 ; // {TAG_WIDTH{1'd0}} TAG_WIDTH =21 + + +assign read_miss_fill = c_state == CS_FILL3 && i_wb_ready; + + + +assign tag_wenable = read_miss_fill ? 1'd1 : + source_sel[C_INVA] ? 1'd1 : + source_sel[C_FILL] ? 1'd1 : + source_sel[C_INIT] ? 1'd1 : + source_sel[C_CORE] ? 1'd0 : + 1'd0 ; + + +assign enable = i_select && i_cache_enable; + +assign idle_hit = |data_hit_way; + +assign read_miss = enable && !idle_hit && !invalid_read; + +assign read_stall = (i_select && i_cache_enable) && !(|data_hit_way) && !wb_hit && !read_buf_hit; +//assign read_stall = enable && !idle_hit && !wb_hit && !read_buf_hit; + +assign cache_busy_stall = (c_state == CS_TURN_AROUND && enable && !read_buf_hit) || c_state == CS_INIT; + + +// ====================================== +// Instantiate RAMS +// ====================================== + +//generate +// for ( i=0; i reg +reg cache_stall; //jing- add wire -> reg +//reg o_fetch_stall; //jing+ +wire [127:0] cache_read_data128; +wire [31:0] cache_read_data; +wire sel_cache; +wire uncached_instruction_read; +wire address_cachable; +wire icache_wb_req; +wire wait_wb; +reg wb_req_r = 1'd0; +wire [31:0] wb_rdata32; + + + +// e.g. 24 for 32MBytes, 26 for 128MBytes +localparam MAIN_MSB = 26; + +// e.g. 13 for 4k words +localparam BOOT_MSB = 13; + +localparam MAIN_BASE = 32'h00000000; /* Main Memory */ +localparam BOOT_BASE = 32'h00000000; /* Cachable Boot Memory */ +localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */ +localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */ +localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */ +localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */ +localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */ +localparam HIBOOT_BASE = 32'h28000000; /* Uncachable Boot Memory */ +localparam TEST_BASE = 16'hf000; /* Test Module */ + + +assign address_cachable = ( + ( i_iaddress >= 32'h00000000 && i_iaddress < 32'h7fff) + || ( + (i_iaddress >= MAIN_BASE && i_iaddress < (MAIN_BASE + 32'hfffffff)) + && !( (i_iaddress >= BOOT_BASE && i_iaddress < (BOOT_BASE + 32'h7fff)) + ||(i_iaddress[31:14] == HIBOOT_BASE>>(14))) + ) + ) + && ((i_iaddress[25:21] == 5'b00000) ? i_cacheable_area[0] : + (i_iaddress[25:21] == 5'b00001) ? i_cacheable_area[1] : + (i_iaddress[25:21] == 5'b00010) ? i_cacheable_area[2] : + (i_iaddress[25:21] == 5'b00011) ? i_cacheable_area[3] : + (i_iaddress[25:21] == 5'b00100) ? i_cacheable_area[4] : + (i_iaddress[25:21] == 5'b00101) ? i_cacheable_area[5] : + (i_iaddress[25:21] == 5'b00110) ? i_cacheable_area[6] : + (i_iaddress[25:21] == 5'b00111) ? i_cacheable_area[7] : + (i_iaddress[25:21] == 5'b01000) ? i_cacheable_area[8] : + (i_iaddress[25:21] == 5'b01001) ? i_cacheable_area[9] : + (i_iaddress[25:21] == 5'b01010) ? i_cacheable_area[10] : + (i_iaddress[25:21] == 5'b01011) ? i_cacheable_area[11] : + (i_iaddress[25:21] == 5'b01100) ? i_cacheable_area[12] : + (i_iaddress[25:21] == 5'b01101) ? i_cacheable_area[13] : + (i_iaddress[25:21] == 5'b01110) ? i_cacheable_area[14] : + (i_iaddress[25:21] == 5'b01111) ? i_cacheable_area[15] : + (i_iaddress[25:21] == 5'b10000) ? i_cacheable_area[16] : + (i_iaddress[25:21] == 5'b10001) ? i_cacheable_area[17] : + (i_iaddress[25:21] == 5'b10010) ? i_cacheable_area[18] : + (i_iaddress[25:21] == 5'b10011) ? i_cacheable_area[19] : + (i_iaddress[25:21] == 5'b10100) ? i_cacheable_area[20] : + (i_iaddress[25:21] == 5'b10101) ? i_cacheable_area[21] : + (i_iaddress[25:21] == 5'b10110) ? i_cacheable_area[22] : + (i_iaddress[25:21] == 5'b10111) ? i_cacheable_area[23] : + (i_iaddress[25:21] == 5'b11000) ? i_cacheable_area[24] : + (i_iaddress[25:21] == 5'b11001) ? i_cacheable_area[25] : + (i_iaddress[25:21] == 5'b11010) ? i_cacheable_area[26] : + (i_iaddress[25:21] == 5'b11011) ? i_cacheable_area[27] : + (i_iaddress[25:21] == 5'b11100) ? i_cacheable_area[28] : + (i_iaddress[25:21] == 5'b11101) ? i_cacheable_area[29] : + (i_iaddress[25:21] == 5'b11110) ? i_cacheable_area[30] : + i_cacheable_area[31] ); + +//i_cacheable_area[i_iaddress[25:21]]; + +assign sel_cache = address_cachable && i_iaddress_valid && i_cache_enable; + +// Don't start wishbone transfers when the cache is stalling the core +// The cache stalls the core during its initialization sequence +assign uncached_instruction_read = !sel_cache && i_iaddress_valid && !cache_stall; + +// Return read data either from the wishbone bus or the cache +assign cache_read_data = i_iaddress[3:2] == 2'd0 ? cache_read_data128[ 31: 0] : + i_iaddress[3:2] == 2'd1 ? cache_read_data128[ 63:32] : + i_iaddress[3:2] == 2'd2 ? cache_read_data128[ 95:64] : + cache_read_data128[127:96] ; + +assign wb_rdata32 = i_iaddress[3:2] == 2'd0 ? i_wb_read_data[ 31: 0] : + i_iaddress[3:2] == 2'd1 ? i_wb_read_data[ 63:32] : + i_iaddress[3:2] == 2'd2 ? i_wb_read_data[ 95:64] : + i_wb_read_data[127:96] ; + +assign o_fetch_instruction = sel_cache ? cache_read_data : + uncached_instruction_read ? wb_rdata32 : + 32'hffeeddcc ; + +// Stall the instruction decode and execute stages of the core +// when the fetch stage needs more than 1 cycle to return the requested +// read data + +assign o_fetch_stall = !i_system_rdy || wait_wb || cache_stall; + +assign o_wb_address = i_iaddress; +assign o_wb_req = icache_wb_req || uncached_instruction_read; + +assign wait_wb = (o_wb_req || wb_req_r) && !i_wb_ready; + +always @(posedge i_clk) + wb_req_r <= o_wb_req && !i_wb_ready; + +assign core_stall = o_fetch_stall || i_mem_stall || i_exec_stall || i_conflict; + +// ====================================== +// L1 Instruction Cache +// ====================================== +a25_icache u_cache ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + .o_stall ( cache_stall ), + + .i_select ( sel_cache ), + .i_address ( i_iaddress ), + .i_address_nxt ( i_iaddress_nxt ), + .i_cache_enable ( i_cache_enable ), + .i_cache_flush ( i_cache_flush ), + .o_read_data ( cache_read_data128 ), + + .o_wb_req ( icache_wb_req ), + .i_wb_read_data ( i_wb_read_data ), + .i_wb_ready ( i_wb_ready ) +); + + +endmodule + + + + +module a25_decode( + i_clk, + i_fetch_instruction, + i_core_stall, + i_irq, + i_firq, + i_dabt, + i_iabt, + i_adex, + i_execute_iaddress, + // i_execute_daddress, + i_abt_status, + i_execute_status_bits, + i_multiply_done, + + + o_imm32, + o_imm_shift_amount, + o_shift_imm_zero, + o_condition, + o_decode_exclusive, + o_decode_iaccess, + o_decode_daccess, + o_status_bits_mode, + o_status_bits_irq_mask, + o_status_bits_firq_mask, + + o_rm_sel, + o_rs_sel, + o_load_rd, + + o_rn_sel, + o_barrel_shift_amount_sel, + o_barrel_shift_data_sel, + o_barrel_shift_function, + o_alu_function, + o_multiply_function, + o_interrupt_vector_sel, + o_iaddress_sel, + o_daddress_sel, + o_pc_sel, + o_byte_enable_sel, + o_status_bits_sel, + o_reg_write_sel, + o_user_mode_regs_store_nxt, + o_firq_not_user_mode, + + o_write_data_wen, + o_base_address_wen, + + o_pc_wen, + o_reg_bank_wen, + o_status_bits_flags_wen, + o_status_bits_mode_wen, + o_status_bits_irq_mask_wen, + o_status_bits_firq_mask_wen, + + o_copro_opcode1, + o_copro_opcode2, + o_copro_crn, + o_copro_crm, + o_copro_num, + o_copro_operation, + + o_copro_write_data_wen, + o_iabt_trigger, + o_iabt_address, + o_iabt_status, + o_dabt_trigger, + o_dabt_address, + o_dabt_status, + o_conflict, + o_rn_use_read, + o_rm_use_read, + o_rs_use_read, + o_rd_use_read +); + +/************************* IO Declarations *********************/ +input i_clk; +input [31:0] i_fetch_instruction; +input i_core_stall; // stall all stages of the Amber core at the same time +input i_irq; // interrupt request +input i_firq; // Fast interrupt request +input i_dabt; // data abort interrupt request +input i_iabt; // instruction pre-fetch abort flag +input i_adex; // Address Exception +input [31:0] i_execute_iaddress; // Registered instruction address output by execute stage +//input [31:0] i_execute_daddress; // Registered instruction address output by execute stage +input [7:0] i_abt_status; // Abort status +input [31:0] i_execute_status_bits; // current status bits values in execute stage +input i_multiply_done; // multiply unit is nearly done + + +// -------------------------------------------------- +// Control signals to execute stage +// -------------------------------------------------- +output [31:0] o_imm32; +output [4:0] o_imm_shift_amount; +output o_shift_imm_zero; +output [3:0] o_condition; // 4'he = al +output o_decode_exclusive; // exclusive access request ( swap instruction ) +output o_decode_iaccess; // Indicates an instruction access +output o_decode_daccess; // Indicates a data access +output [1:0] o_status_bits_mode; // SVC +output o_status_bits_irq_mask; +output o_status_bits_firq_mask; + +output [3:0] o_rm_sel; +output [3:0] o_rs_sel; +output [7:0] o_load_rd; // [7] load flags with PC + // [6] load status bits with PC + // [5] Write into User Mode register + // [4] zero-extend load + // [3:0] destination register, Rd +output [3:0] o_rn_sel; +output [1:0] o_barrel_shift_amount_sel; +output [1:0] o_barrel_shift_data_sel; +output [1:0] o_barrel_shift_function; +output [8:0] o_alu_function; +output [1:0] o_multiply_function; +output [2:0] o_interrupt_vector_sel; +output [3:0] o_iaddress_sel; +output [3:0] o_daddress_sel; +output [2:0] o_pc_sel; +output [1:0] o_byte_enable_sel; // byte, halfword or word write +output [2:0] o_status_bits_sel; +output [2:0] o_reg_write_sel; +output o_user_mode_regs_store_nxt; +output o_firq_not_user_mode; + +output o_write_data_wen; +output o_base_address_wen; // save ldm base address register + // in case of data abort +output o_pc_wen; +output [14:0] o_reg_bank_wen; +output o_status_bits_flags_wen; +output o_status_bits_mode_wen; +output o_status_bits_irq_mask_wen; +output o_status_bits_firq_mask_wen; + +// -------------------------------------------------- +// Co-Processor interface +// -------------------------------------------------- +output [2:0] o_copro_opcode1; +output [2:0] o_copro_opcode2; +output [3:0] o_copro_crn; +output [3:0] o_copro_crm; +output [3:0] o_copro_num; +output [1:0] o_copro_operation; // 0 = no operation, + // 1 = Move to Amber Core Register from Coprocessor + // 2 = Move to Coprocessor from Amber Core Register +output o_copro_write_data_wen; +output o_iabt_trigger; +output [31:0] o_iabt_address; +output [7:0] o_iabt_status; +output o_dabt_trigger; +output [31:0] o_dabt_address; +output [7:0] o_dabt_status; +output o_conflict; +output o_rn_use_read; +output o_rm_use_read; +output o_rs_use_read; +output o_rd_use_read; + + + + +/*********************** Signal Declarations *******************/ + +reg [31:0] o_imm32 = 32'd0; +reg [4:0] o_imm_shift_amount = 5'd0; +reg o_shift_imm_zero = 1'd0; +reg [3:0] o_condition = 4'he; // 4'he = al +reg o_decode_exclusive = 1'd0; // exclusive access request ( swap instruction ) +reg o_decode_iaccess = 1'd1; // Indicates an instruction access +reg o_decode_daccess = 1'd0; // Indicates a data access +reg [1:0] o_status_bits_mode = 2'b11; // SVC +reg o_status_bits_irq_mask = 1'd1; +reg o_status_bits_firq_mask = 1'd1; + +reg [3:0] o_rm_sel = 4'd0; +reg [3:0] o_rs_sel = 4'd0; +reg [7:0] o_load_rd = 8'd0; // [7] load flags with PC + +reg [3:0] o_rn_sel = 4'd0; +reg [1:0] o_barrel_shift_amount_sel = 2'd0; +reg [1:0] o_barrel_shift_data_sel = 2'd0; +reg [1:0] o_barrel_shift_function = 2'd0; +reg [8:0] o_alu_function = 9'd0; +reg [1:0] o_multiply_function = 2'd0; +reg [2:0] o_interrupt_vector_sel = 3'd0; +reg [3:0] o_iaddress_sel = 4'd2; +reg [3:0] o_daddress_sel = 4'd2; +reg [2:0] o_pc_sel = 3'd2; +reg [1:0] o_byte_enable_sel = 2'd0; // byte, halfword or word write +reg [2:0] o_status_bits_sel = 3'd0; +reg [2:0] o_reg_write_sel; +reg o_user_mode_regs_store_nxt; +reg o_firq_not_user_mode; + +reg o_write_data_wen = 1'd0; +reg o_base_address_wen = 1'd0; // save ldm base address register + // in case of data abort +reg o_pc_wen = 1'd1; +reg [14:0] o_reg_bank_wen = 15'd0; +reg o_status_bits_flags_wen = 1'd0; +reg o_status_bits_mode_wen = 1'd0; +reg o_status_bits_irq_mask_wen = 1'd0; +reg o_status_bits_firq_mask_wen = 1'd0; + +// -------------------------------------------------- +// Co-Processor interface +// -------------------------------------------------- +reg [2:0] o_copro_opcode1 = 3'd0; +reg [2:0] o_copro_opcode2 = 3'd0; +reg [3:0] o_copro_crn = 4'd0; +reg [3:0] o_copro_crm = 4'd0; +reg [3:0] o_copro_num = 4'd0; +reg [1:0] o_copro_operation = 2'd0; // 0 = no operation, + // 1 = Move to Amber Core Register from Coprocessor + // 2 = Move to Coprocessor from Amber Core Register +reg o_copro_write_data_wen = 1'd0; +reg o_rn_use_read; +reg o_rm_use_read; +reg o_rs_use_read; +reg o_rd_use_read; + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + +localparam [4:0] RST_WAIT1 = 5'd0, + RST_WAIT2 = 5'd1, + INT_WAIT1 = 5'd2, + INT_WAIT2 = 5'd3, + EXECUTE = 5'd4, + PRE_FETCH_EXEC = 5'd5, // Execute the Pre-Fetched Instruction + MEM_WAIT1 = 5'd6, // conditionally decode current instruction, in case + // previous instruction does not execute in S2 + MEM_WAIT2 = 5'd7, + PC_STALL1 = 5'd8, // Program Counter altered + // conditionally decude current instruction, in case + // previous instruction does not execute in S2 + PC_STALL2 = 5'd9, + MTRANS_EXEC1 = 5'd10, + MTRANS_EXEC2 = 5'd11, + MTRANS_ABORT = 5'd12, + MULT_PROC1 = 5'd13, // first cycle, save pre fetch instruction + MULT_PROC2 = 5'd14, // do multiplication + MULT_STORE = 5'd15, // save RdLo + MULT_ACCUMU = 5'd16, // Accumulate add lower 32 bits + SWAP_WRITE = 5'd17, + SWAP_WAIT1 = 5'd18, + SWAP_WAIT2 = 5'd19, + COPRO_WAIT = 5'd20; + + +// ======================================================== +// Internal signals +// ======================================================== +wire [31:0] instruction; +wire [3:0] type; // regop, mem access etc. +wire instruction_iabt; // abort flag, follows the instruction +wire instruction_adex; // address exception flag, follows the instruction +wire [31:0] instruction_address; // instruction virtual address, follows + // the instruction +wire [7:0] instruction_iabt_status; // abort status, follows the instruction +wire [1:0] instruction_sel; +wire [3:0] opcode; +wire [7:0] imm8; +wire [31:0] offset12; +wire [31:0] offset24; +wire [4:0] shift_imm; + +wire opcode_compare; +wire mem_op; +wire load_op; +wire store_op; +wire write_pc; +wire current_write_pc; +reg load_pc_nxt; +reg load_pc_r = 1'd0; +wire immediate_shift_op; +wire rds_use_rs; +wire branch; +wire mem_op_pre_indexed; +wire mem_op_post_indexed; + +// Flop inputs +wire [31:0] imm32_nxt; +wire [4:0] imm_shift_amount_nxt; +wire shift_imm_zero_nxt; +wire [3:0] condition_nxt; +reg decode_exclusive_nxt; +reg decode_iaccess_nxt; +reg decode_daccess_nxt; + +reg [1:0] barrel_shift_function_nxt; +wire [8:0] alu_function_nxt; +reg [1:0] multiply_function_nxt; +reg [1:0] status_bits_mode_nxt; +reg status_bits_irq_mask_nxt; +reg status_bits_firq_mask_nxt; + +wire [3:0] rm_sel_nxt; +wire [3:0] rs_sel_nxt; + +wire [3:0] rn_sel_nxt; +reg [1:0] barrel_shift_amount_sel_nxt; +reg [1:0] barrel_shift_data_sel_nxt; +reg [3:0] iaddress_sel_nxt; +reg [3:0] daddress_sel_nxt; +reg [2:0] pc_sel_nxt; +reg [1:0] byte_enable_sel_nxt; +reg [2:0] status_bits_sel_nxt; +reg [2:0] reg_write_sel_nxt; +wire firq_not_user_mode_nxt; + +// ALU Function signals +reg alu_swap_sel_nxt; +reg alu_not_sel_nxt; +reg [1:0] alu_cin_sel_nxt; +reg alu_cout_sel_nxt; +reg [3:0] alu_out_sel_nxt; + +reg write_data_wen_nxt; +reg copro_write_data_wen_nxt; +reg base_address_wen_nxt; +reg pc_wen_nxt; +reg [14:0] reg_bank_wen_nxt; +reg status_bits_flags_wen_nxt; +reg status_bits_mode_wen_nxt; +reg status_bits_irq_mask_wen_nxt; +reg status_bits_firq_mask_wen_nxt; + +reg saved_current_instruction_wen; // saved load instruction +reg pre_fetch_instruction_wen; // pre-fetch instruction + +reg [4:0] control_state = 5'd0; //RST_WAIT1 +reg [4:0] control_state_nxt; + + +wire dabt; +reg dabt_reg = 1'd0; +reg dabt_reg_d1; +reg iabt_reg = 1'd0; +reg adex_reg = 1'd0; +reg [31:0] fetch_address_r = 32'd0; +reg [7:0] abt_status_reg = 8'd0; +reg [31:0] fetch_instruction_r = 32'd0; +reg [3:0] fetch_instruction_type_r = 4'd0; +reg [31:0] saved_current_instruction = 32'd0; +reg [3:0] saved_current_instruction_type = 4'd0; +reg saved_current_instruction_iabt = 1'd0; // access abort flag +reg saved_current_instruction_adex = 1'd0; // address exception +reg [31:0] saved_current_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] saved_current_instruction_iabt_status = 8'd0; // status of abort instruction +reg [31:0] pre_fetch_instruction = 32'd0; +reg [3:0] pre_fetch_instruction_type = 4'd0; +reg pre_fetch_instruction_iabt = 1'd0; // access abort flag +reg pre_fetch_instruction_adex = 1'd0; // address exception +reg [31:0] pre_fetch_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] pre_fetch_instruction_iabt_status = 8'd0; // status of abort instruction +reg [31:0] hold_instruction = 32'd0; +reg [3:0] hold_instruction_type = 4'd0; +reg hold_instruction_iabt = 1'd0; // access abort flag +reg hold_instruction_adex = 1'd0; // address exception +reg [31:0] hold_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] hold_instruction_iabt_status = 8'd0; // status of abort instruction + +wire instruction_valid; +wire instruction_execute; +reg instruction_execute_r = 1'd0; + +reg [3:0] mtrans_reg1; // the current register being accessed as part of stm/ldm +reg [3:0] mtrans_reg2; // the next register being accessed as part of stm/ldm +reg [31:0] mtrans_instruction_nxt; +wire [15:0] mtrans_reg2_mask; + +wire [31:0] mtrans_base_reg_change; +wire [4:0] mtrans_num_registers; +wire use_saved_current_instruction; +wire use_hold_instruction; +wire use_pre_fetch_instruction; +wire interrupt; +wire interrupt_or_conflict; +wire [1:0] interrupt_mode; +wire [2:0] next_interrupt; +reg irq = 1'd0; +reg firq = 1'd0; +wire firq_request; +wire irq_request; +wire swi_request; +wire und_request; +wire dabt_request; +reg [1:0] copro_operation_nxt; +reg restore_base_address = 1'd0; +reg restore_base_address_nxt; + +wire regop_set_flags; + +wire [7:0] load_rd_nxt; +wire load_rd_byte; +wire ldm_user_mode; +wire ldm_status_bits; +wire ldm_flags; +wire [6:0] load_rd_d1_nxt; +reg [6:0] load_rd_d1 = 7'd0; // MSB is the valid bit + +wire rn_valid; +wire rm_valid; +wire rs_valid; +wire rd_valid; +wire stm_valid; +wire rn_conflict1; +wire rn_conflict2; +wire rm_conflict1; +wire rm_conflict2; +wire rs_conflict1; +wire rs_conflict2; +wire rd_conflict1; +wire rd_conflict2; +wire stm_conflict1a; +wire stm_conflict1b; +wire stm_conflict2a; +wire stm_conflict2b; +wire conflict1; // Register conflict1 with ldr operation +wire conflict2; // Register conflict1 with ldr operation +wire conflict; // Register conflict1 with ldr operation +reg conflict_r = 1'd0; +reg rn_conflict1_r = 1'd0; +reg rm_conflict1_r = 1'd0; +reg rs_conflict1_r = 1'd0; +reg rd_conflict1_r = 1'd0; +wire [11:0] i_fetch; + +// ======================================================== +// Instruction Abort and Data Abort outputs +// ======================================================== + + +assign o_iabt_trigger = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1; +assign o_iabt_address = instruction_address; +assign o_iabt_status = instruction_iabt_status; + +assign o_dabt_trigger = dabt_reg && !dabt_reg_d1; +assign o_dabt_address = fetch_address_r; +assign o_dabt_status = abt_status_reg; + + +// ======================================================== +// Instruction Decode +// ======================================================== + +// for instructions that take more than one cycle +// the instruction is saved in the 'saved_mem_instruction' +// register and then that register is used for the rest of +// the execution of the instruction. +// But if the instruction does not execute because of the +// condition, then need to select the next instruction to +// decode +assign use_saved_current_instruction = instruction_execute && + ( control_state == MEM_WAIT1 || + control_state == MEM_WAIT2 || + control_state == MTRANS_EXEC1 || + control_state == MTRANS_EXEC2 || + control_state == MTRANS_ABORT || + control_state == MULT_PROC1 || + control_state == MULT_PROC2 || + control_state == MULT_ACCUMU || + control_state == MULT_STORE || + control_state == INT_WAIT1 || + control_state == INT_WAIT2 || + control_state == SWAP_WRITE || + control_state == SWAP_WAIT1 || + control_state == SWAP_WAIT2 || + control_state == COPRO_WAIT ); + +assign use_hold_instruction = conflict_r; + +assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC; + + +assign instruction_sel = use_hold_instruction ? 2'd3 : // hold_instruction + use_saved_current_instruction ? 2'd1 : // saved_current_instruction + use_pre_fetch_instruction ? 2'd2 : // pre_fetch_instruction + 2'd0 ; // fetch_instruction_r + +assign instruction = instruction_sel == 2'd0 ? fetch_instruction_r : + instruction_sel == 2'd1 ? saved_current_instruction : + instruction_sel == 2'd3 ? hold_instruction : + pre_fetch_instruction ; + +assign type = instruction_sel == 2'd0 ? fetch_instruction_type_r : + instruction_sel == 2'd1 ? saved_current_instruction_type : + instruction_sel == 2'd3 ? hold_instruction_type : + pre_fetch_instruction_type ; + +// abort flag +assign instruction_iabt = instruction_sel == 2'd0 ? iabt_reg : + instruction_sel == 2'd1 ? saved_current_instruction_iabt : + instruction_sel == 2'd3 ? hold_instruction_iabt : + pre_fetch_instruction_iabt ; + +assign instruction_address = instruction_sel == 2'd0 ? fetch_address_r : + instruction_sel == 2'd1 ? saved_current_instruction_address : + instruction_sel == 2'd3 ? hold_instruction_address : + pre_fetch_instruction_address ; + +assign instruction_iabt_status = instruction_sel == 2'd0 ? abt_status_reg : + instruction_sel == 2'd1 ? saved_current_instruction_iabt_status : + instruction_sel == 2'd3 ? hold_instruction_iabt_status : + pre_fetch_instruction_iabt_status ; + +// instruction address exception +assign instruction_adex = instruction_sel == 2'd0 ? adex_reg : + instruction_sel == 2'd1 ? saved_current_instruction_adex : + instruction_sel == 2'd3 ? hold_instruction_adex : + pre_fetch_instruction_adex ; + + +// ======================================================== +// Fixed fields within the instruction +// ======================================================== + +assign opcode = instruction[24:21]; +assign condition_nxt = instruction[31:28]; + +assign rm_sel_nxt = instruction[3:0]; +assign rn_sel_nxt = branch ? 4'd15 : instruction[19:16]; // Use PC to calculate branch destination +assign rs_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory + type == MTRANS ? mtrans_reg1 : + branch ? 4'd15 : // Update the PC + rds_use_rs ? instruction[11:8] : + instruction[15:12] ; + +// Load from memory into registers +assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; +assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; +assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; +assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22]; +assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt}; + + + // MSB indicates valid dirty target register +assign load_rd_d1_nxt = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]}; +assign shift_imm = instruction[11:7]; +assign offset12 = { 20'h0, instruction[11:0]}; +assign offset24 = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend +assign imm8 = instruction[7:0]; + +assign immediate_shift_op = instruction[25]; +assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) || + (type == MULT && + (control_state == MULT_PROC1 || + control_state == MULT_PROC2 || +// instruction_valid && !interrupt )) ; +// remove the '!conflict' term from the interrupt logic used here +// to break a combinational loop + (instruction_valid && !interrupt_or_conflict))) ; + + +assign branch = type == BRANCH; +assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ; +assign mem_op = type == TRANS; +assign load_op = mem_op && instruction[20]; +assign store_op = mem_op && !instruction[20]; +assign write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_r || load_pc_nxt; +assign current_write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_nxt; +assign regop_set_flags = type == REGOP && instruction[20]; + +assign mem_op_pre_indexed = instruction[24] && instruction[21]; +assign mem_op_post_indexed = !instruction[24]; + +assign imm32_nxt = // add 0 to Rm + type == MULT ? { 32'd0 } : //MULT = 4'h1, + + // 4 x number of registers + type == MTRANS ? { mtrans_base_reg_change } : //MTRANS = 4'h4 + type == BRANCH ? { offset24 } : //BRANCH = 4'h5 + type == TRANS ? { offset12 } : //TRANS = 4'h3 + instruction[11:8] == 4'h0 ? { 24'd0, imm8[7:0] } : + instruction[11:8] == 4'h1 ? { imm8[1:0], 24'd0, imm8[7:2] } : + instruction[11:8] == 4'h2 ? { imm8[3:0], 24'd0, imm8[7:4] } : + instruction[11:8] == 4'h3 ? { imm8[5:0], 24'd0, imm8[7:6] } : + instruction[11:8] == 4'h4 ? { imm8[7:0], 24'd0 } : + instruction[11:8] == 4'h5 ? { 2'd0, imm8[7:0], 22'd0 } : + instruction[11:8] == 4'h6 ? { 4'd0, imm8[7:0], 20'd0 } : + instruction[11:8] == 4'h7 ? { 6'd0, imm8[7:0], 18'd0 } : + instruction[11:8] == 4'h8 ? { 8'd0, imm8[7:0], 16'd0 } : + instruction[11:8] == 4'h9 ? { 10'd0, imm8[7:0], 14'd0 } : + instruction[11:8] == 4'ha ? { 12'd0, imm8[7:0], 12'd0 } : + instruction[11:8] == 4'hb ? { 14'd0, imm8[7:0], 10'd0 } : + instruction[11:8] == 4'hc ? { 16'd0, imm8[7:0], 8'd0 } : + instruction[11:8] == 4'hd ? { 18'd0, imm8[7:0], 6'd0 } : + instruction[11:8] == 4'he ? { 20'd0, imm8[7:0], 4'd0 } : + { 22'd0, imm8[7:0],2'd0 } ; + + +assign imm_shift_amount_nxt = shift_imm ; + + // This signal is encoded in the decode stage because + // it is on the critical path in the execute stage +assign shift_imm_zero_nxt = imm_shift_amount_nxt == 5'd0 && // immediate amount = 0 + barrel_shift_amount_sel_nxt == 2'd2; // shift immediate amount + +assign alu_function_nxt = { alu_swap_sel_nxt, + alu_not_sel_nxt, + alu_cin_sel_nxt, + alu_cout_sel_nxt, + alu_out_sel_nxt }; + +// ======================================================== +// Register Conflict Detection +// ======================================================== +assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS; +assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op); +assign rs_valid = rds_use_rs; +assign rd_valid = (type == TRANS && store_op) || (type == REGOP || type == SWAP); +assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction + + +assign rn_conflict1 = instruction_execute && rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rn_conflict2 = instruction_execute_r && rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] ); +assign rm_conflict1 = instruction_execute && rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rm_conflict2 = instruction_execute_r && rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] ); +assign rs_conflict1 = instruction_execute && rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rs_conflict2 = instruction_execute_r && rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] ); +assign rd_conflict1 = instruction_execute && rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] ); +assign rd_conflict2 = instruction_execute_r && rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] ); + +assign stm_conflict1a = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] ); +assign stm_conflict1b = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] ); +assign stm_conflict2a = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] ); +assign stm_conflict2b = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] ); + +assign conflict1 = instruction_valid && + (rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 || + stm_conflict1a || stm_conflict1b); + +assign conflict2 = instruction_valid && (stm_conflict2a || stm_conflict2b); + +assign conflict = conflict1 || conflict2; + + +always @( posedge i_clk ) + if ( !i_core_stall ) + begin + conflict_r <= conflict; + instruction_execute_r <= instruction_execute; + rn_conflict1_r <= rn_conflict1 && instruction_execute; + rm_conflict1_r <= rm_conflict1 && instruction_execute; + rs_conflict1_r <= rs_conflict1 && instruction_execute; + rd_conflict1_r <= rd_conflict1 && instruction_execute; + o_rn_use_read <= instruction_valid && ( rn_conflict1_r || rn_conflict2 ); + o_rm_use_read <= instruction_valid && ( rm_conflict1_r || rm_conflict2 ); + o_rs_use_read <= instruction_valid && ( rs_conflict1_r || rs_conflict2 ); + o_rd_use_read <= instruction_valid && ( rd_conflict1_r || rd_conflict2 ); + end + +assign o_conflict = conflict; + + +// ======================================================== +// MTRANS Operations +// ======================================================== + + // Bit 15 = r15 + // Bit 0 = r0 + // In ldm and stm instructions r0 is loaded or stored first +always @* + + if (instruction[0] == 1'b1) mtrans_reg1 = 4'h0; + else if (instruction[1:0] == 2'b10) mtrans_reg1 = 4'h1; + else if (instruction[2:0] == 3'b100) mtrans_reg1 = 4'h2; + else if (instruction[3:0] == 4'b1000) mtrans_reg1 = 4'h3; + else if (instruction[4:0] == 5'b10000) mtrans_reg1 = 4'h4; + else if (instruction[5:0] == 6'b100000) mtrans_reg1 = 4'h5; + else if (instruction[6:0] == 7'b1000000) mtrans_reg1 = 4'h6; + else if (instruction[7:0] == 8'b10000000) mtrans_reg1 = 4'h7; + else if (instruction[8:0] == 9'b100000000) mtrans_reg1 = 4'h8; + else if (instruction[9:0] == 10'b1000000000) mtrans_reg1 = 4'h9; + else if (instruction[10:0] == 11'b10000000000) mtrans_reg1 = 4'ha; + else if (instruction[11:0] == 12'b100000000000) mtrans_reg1 = 4'hb; + else if (instruction[12:0] == 13'b1000000000000) mtrans_reg1 = 4'hc; + else if (instruction[13:0] == 14'b10000000000000) mtrans_reg1 = 4'hd; + else if (instruction[14:0] == 15'b100000000000000) mtrans_reg1 = 4'he; + else mtrans_reg1 = 4'hf; + +// casez ( instruction[15:0] ) +// 16'b???????????????1 : mtrans_reg1 = 4'h0 ; +// 16'b??????????????10 : mtrans_reg1 = 4'h1 ; +// 16'b?????????????100 : mtrans_reg1 = 4'h2 ; +// 16'b????????????1000 : mtrans_reg1 = 4'h3 ; +// 16'b???????????10000 : mtrans_reg1 = 4'h4 ; +// 16'b??????????100000 : mtrans_reg1 = 4'h5 ; +// 16'b?????????1000000 : mtrans_reg1 = 4'h6 ; +// 16'b????????10000000 : mtrans_reg1 = 4'h7 ; +// 16'b???????100000000 : mtrans_reg1 = 4'h8 ; +// 16'b??????1000000000 : mtrans_reg1 = 4'h9 ; +// 16'b?????10000000000 : mtrans_reg1 = 4'ha ; +// 16'b????100000000000 : mtrans_reg1 = 4'hb ; +// 16'b???1000000000000 : mtrans_reg1 = 4'hc ; +// 16'b??10000000000000 : mtrans_reg1 = 4'hd ; +// 16'b?100000000000000 : mtrans_reg1 = 4'he ; +// default : mtrans_reg1 = 4'hf ; +// endcase + + + +//assign mtrans_reg2_mask = 1'd1< 4'd2 )) + decode_iaccess_nxt = 1'd0; + + else if ( control_state == MTRANS_EXEC2 && ( mtrans_num_registers > 4'd2 )) + decode_iaccess_nxt = 1'd0; + + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + decode_iaccess_nxt = 1'd0; + + else + decode_iaccess_nxt = 1'd1; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == CORTRANS && !und_request ) + begin + if ( instruction[20] ) + copro_operation_nxt = 2'd1; + else + copro_operation_nxt = 2'd0; + end + else + copro_operation_nxt = 2'd0; + end + + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && !instruction[20]) + copro_operation_nxt = 2'd2; + + else + copro_operation_nxt = 2'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && (load_op && instruction[15:12] == 4'd15)) + saved_current_instruction_wen = 1'd1; + else if ( type == MTRANS ) + saved_current_instruction_wen = 1'd1; + else if ( type == MULT ) + saved_current_instruction_wen = 1'd1; + else if ( type == SWAP ) + saved_current_instruction_wen = 1'd1; + else if ( type == CORTRANS && !und_request ) + saved_current_instruction_wen = 1'd1; + else + saved_current_instruction_wen = 1'd0; + end + + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + saved_current_instruction_wen = 1'd1; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute &&( instruction[20] && mtrans_reg1 == 4'd15 )) + saved_current_instruction_wen = 1'd1; + + else if ( control_state == MTRANS_EXEC2 && ( instruction[20] && mtrans_reg1 == 4'd15 )) + saved_current_instruction_wen = 1'd1; + + else + saved_current_instruction_wen = 1'd0; + end + +always @* + begin + if ( control_state == MEM_WAIT1 && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == MTRANS_EXEC1 && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else + pre_fetch_instruction_wen = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MTRANS) + // restore_base_address_nxt <= instruction[20] && + // (instruction[15:0] & (1'd1 << instruction[19:16])); + restore_base_address_nxt = instruction[20] && + (instruction[15:0] & ( + instruction[19:16] == 4'h1 ? 16'b10: + instruction[19:16] == 4'h2 ? 16'b100: + instruction[19:16] == 4'h3 ? 16'b1000: + instruction[19:16] == 4'h4 ? 16'b10000: + instruction[19:16] == 4'h5 ? 16'b100000: + instruction[19:16] == 4'h6 ? 16'b1000000: + instruction[19:16] == 4'h7 ? 16'b10000000: + instruction[19:16] == 4'h8 ? 16'b100000000: + instruction[19:16] == 4'h9 ? 16'b1000000000: + instruction[19:16] == 4'ha ? 16'b10000000000: + instruction[19:16] == 4'hb ? 16'b100000000000: + instruction[19:16] == 4'hc ? 16'b1000000000000: + instruction[19:16] == 4'hd ? 16'b10000000000000: + instruction[19:16] == 4'he ? 16'b100000000000000: + instruction[19:16] == 4'hf ? 16'b1000000000000000: + 16'b1)); + else + restore_base_address_nxt = restore_base_address; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP ) + begin + if ( !immediate_shift_op && instruction[4] ) + barrel_shift_amount_sel_nxt = 2'd1; + else if ( !immediate_shift_op && !instruction[4] ) + barrel_shift_amount_sel_nxt = 2'd2; + else + barrel_shift_amount_sel_nxt = 2'd0; + end + else if ( mem_op && ( type == TRANS && instruction[25] && shift_imm != 5'd0 ) ) + barrel_shift_amount_sel_nxt = 2'd2; + else + barrel_shift_amount_sel_nxt = 2'd0; + end + else + barrel_shift_amount_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if(type == REGOP && !immediate_shift_op) + barrel_shift_data_sel_nxt = 2'd2; + + else if (mem_op && instruction[25] && type == TRANS) + barrel_shift_data_sel_nxt = 2'd2; + else if ( type == SWAP ) + barrel_shift_data_sel_nxt = 2'd2; + else + barrel_shift_data_sel_nxt = 2'd0; + end + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + barrel_shift_data_sel_nxt = 2'd2; + else + barrel_shift_data_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !immediate_shift_op) + barrel_shift_function_nxt = instruction[6:5]; + else if ( mem_op && type == TRANS && instruction[25] && shift_imm != 5'd0 ) + barrel_shift_function_nxt = instruction[6:5]; + else + barrel_shift_function_nxt = 2'd0; + end + else + barrel_shift_function_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MULT) + begin + multiply_function_nxt[0] = 1'd1; + if( instruction[21] ) + multiply_function_nxt[1] = 1'd1; + else + multiply_function_nxt[1] = 1'd0; + end + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_PROC2 ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_STORE ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_ACCUMU ) + multiply_function_nxt = o_multiply_function; + else + multiply_function_nxt = 2'd0; + end + + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15) + iaddress_sel_nxt = 4'd1; + else if ( type == BRANCH ) + iaddress_sel_nxt = 4'd1; + else if ( type == MTRANS && mtrans_num_registers > 4'd1) + iaddress_sel_nxt = 4'd3; + else if ( type == CORTRANS && !und_request ) + iaddress_sel_nxt = 4'd3; + else if ( type == SWI || und_request ) + iaddress_sel_nxt = 4'd2; + else + iaddress_sel_nxt = 4'd0; + + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + iaddress_sel_nxt = 4'd2; + + else if ( control_state == MEM_WAIT1 && !conflict &&instruction_execute) + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && mtrans_num_registers != 4'd1) + + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MTRANS_EXEC2 && mtrans_num_registers > 4'd1) + iaddress_sel_nxt = 4'd3; + else if ( control_state == MULT_PROC2 ) + iaddress_sel_nxt = 4'd3; + else if ( control_state == MULT_ACCUMU ) + iaddress_sel_nxt = 4'd3; + else if ( control_state == SWAP_WAIT1 && instruction_execute) + iaddress_sel_nxt = 4'd3; + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15) + iaddress_sel_nxt = 4'd3; + else + iaddress_sel_nxt = 4'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op ) + begin + if ( mem_op_post_indexed ) + daddress_sel_nxt = 4'd4; // Rn + else + daddress_sel_nxt = 4'd1; // alu out + end + else if ( type == MTRANS ) + if ( instruction[23] ) + begin + if ( instruction[24] ) // increment before + daddress_sel_nxt = 4'd7; // Rn + 4 + else + daddress_sel_nxt = 4'd4; // Rn + end + else + begin + if ( !instruction[24] ) // decrement after + daddress_sel_nxt = 4'd6; // alu out + 4 + else + daddress_sel_nxt = 4'd1; // alu out + end + else if ( type == SWAP ) + daddress_sel_nxt = 4'd4; + else + daddress_sel_nxt = 4'd0; + end + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute ) + daddress_sel_nxt = 4'd5; + else if ( control_state == MTRANS_EXEC2 ) + daddress_sel_nxt = 4'd5; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + daddress_sel_nxt = 4'd4; + else + daddress_sel_nxt = 4'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15 ) + pc_sel_nxt = 3'd1; + else if ( mem_op && (mem_op_pre_indexed || mem_op_post_indexed) && rn_sel_nxt == 4'd15 ) + pc_sel_nxt = 3'd1; + else if ( type == BRANCH ) + pc_sel_nxt = 3'd1; + else if ( type == SWI || und_request ) + pc_sel_nxt = 3'd2; + else + pc_sel_nxt = 3'd0; + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + pc_sel_nxt = 3'd2; + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + pc_sel_nxt = 3'd3; + + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15 ) + + pc_sel_nxt = 3'd3; + else + pc_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && ( load_op && instruction[15:12] == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( type == MTRANS && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else + load_pc_nxt = 1'd0; + end + else if ( control_state == MEM_WAIT1 && !conflict && instruction_execute) + load_pc_nxt = load_pc_r; + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + load_pc_nxt = load_pc_r; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + load_pc_nxt = load_pc_r; + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15 ) + load_pc_nxt = load_pc_r; + else + load_pc_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && store_op && type == TRANS && instruction[22] ) + byte_enable_sel_nxt = 2'd1; + else + byte_enable_sel_nxt = 2'd0; + end + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict && instruction[22]) + byte_enable_sel_nxt = 2'd1; + else + byte_enable_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags && instruction[15:12] == 4'd15) + status_bits_sel_nxt = 3'd1; + else if ( control_state == MULT_STORE && instruction[20]) + status_bits_sel_nxt = 3'd4; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] == 4'd15 ) + status_bits_sel_nxt = 3'd3; + else + status_bits_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == BRANCH && instruction[24] ) + reg_write_sel_nxt = 3'd1; + else if ( type == SWI || und_request ) + reg_write_sel_nxt = 3'd1; + else + reg_write_sel_nxt = 3'd0; + + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + begin + if ( next_interrupt == 3'd4 ) + reg_write_sel_nxt = 3'd7; + else + reg_write_sel_nxt = 3'd1; + end + else if ( control_state == MTRANS_ABORT && restore_base_address ) + reg_write_sel_nxt = 3'd6; + else if ( control_state == MULT_STORE ) + reg_write_sel_nxt = 3'd2; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20]) + reg_write_sel_nxt = 3'd5; + else + reg_write_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MTRANS && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else + o_user_mode_regs_store_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + begin + if ( opcode == RSB ) + alu_swap_sel_nxt = 1'd1; + else if ( opcode == RSC ) + alu_swap_sel_nxt = 1'd1; + else + alu_swap_sel_nxt = 1'd0; + end + else + alu_swap_sel_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == SUB || opcode == CMP ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == SBC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == RSB ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == RSC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == BIC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == MVN ) + alu_not_sel_nxt = 1'd1; + else + alu_not_sel_nxt = 1'd0; + end + else if ( mem_op && !instruction[23]) + alu_not_sel_nxt = 1'd1; + else if ( type == MTRANS && !instruction[23]) + alu_not_sel_nxt = 1'd1; + else + alu_not_sel_nxt = 1'd0; + end + else + alu_not_sel_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == ADC ) + alu_cin_sel_nxt = 2'd2; + else if ( opcode == SUB || opcode == CMP ) + alu_cin_sel_nxt = 2'd1; + else if ( opcode == SBC ) + alu_cin_sel_nxt = 2'd2; + else if ( opcode == RSB ) + alu_cin_sel_nxt = 2'd1; + else if ( opcode == RSC ) + alu_cin_sel_nxt = 2'd2; + else + alu_cin_sel_nxt = 2'd0; + end + else if ( mem_op && !instruction[23]) + alu_cin_sel_nxt = 2'd1; + else if ( type == MTRANS && !instruction[23]) + alu_cin_sel_nxt = 2'd1; + else + alu_cin_sel_nxt = 2'd0; + end + else + alu_cin_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + begin + if ( opcode == AND || opcode == TST ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == EOR || opcode == TEQ ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == ORR ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == BIC ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == MOV ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == MVN ) + alu_cout_sel_nxt = 1'd1; + else + alu_cout_sel_nxt = 1'd0; + end + else + alu_cout_sel_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == ADD || opcode == CMN ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == ADC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == SUB || opcode == CMP ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == SBC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == RSB ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == RSC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == AND || opcode == TST ) + alu_out_sel_nxt = 4'd8; + else if ( opcode == EOR || opcode == TEQ ) + alu_out_sel_nxt = 4'd6; + else if ( opcode == ORR ) + alu_out_sel_nxt = 4'd7; + else if ( opcode == BIC ) + alu_out_sel_nxt = 4'd8; + else + alu_out_sel_nxt = 4'd0; + end + else if ( mem_op ) + alu_out_sel_nxt = 4'd1; + else if ( type == BRANCH ) + alu_out_sel_nxt = 4'd1; + else if ( type == MTRANS ) + alu_out_sel_nxt = 4'd1; + else + alu_out_sel_nxt = 4'd0; + end + else + alu_out_sel_nxt = 4'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && store_op ) + write_data_wen_nxt = 1'd1; + else if ( type == MTRANS && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else + write_data_wen_nxt = 1'd0; + end + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + write_data_wen_nxt = 1'd1; + else + write_data_wen_nxt = 1'd0; + end + +always @* + begin + if(instruction_valid && !interrupt && !conflict && (type == CORTRANS && !und_request) && ! instruction[20]) + copro_write_data_wen_nxt = 1'd1; + else + copro_write_data_wen_nxt = 1'd0; + end + +always @* + begin + if(instruction_valid && !interrupt && !conflict && type == MTRANS) + base_address_wen_nxt = 1'd1; + else + base_address_wen_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op &&(load_op && instruction[15:12] == 4'd15) ) + pc_wen_nxt = 1'd0; + else if ( type == MTRANS ) + begin + if ( mtrans_num_registers > 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( type == MULT ) + pc_wen_nxt = 1'd0; + else if ( type == SWAP ) + pc_wen_nxt = 1'd0; + else if ( type == CORTRANS && !und_request ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MEM_WAIT1 && !conflict && instruction_execute) + pc_wen_nxt = 1'd0; + else if ( control_state == MEM_WAIT2 && !dabt) + pc_wen_nxt = 1'd0; + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute ) + begin + if ( mtrans_num_registers != 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MTRANS_EXEC2 ) + begin + if ( mtrans_num_registers > 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + pc_wen_nxt = 1'd0; + else if ( control_state == MULT_PROC2 ) + pc_wen_nxt = 1'd0; + else if ( control_state == MULT_ACCUMU ) + pc_wen_nxt = 1'd0; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict && instruction_execute) + pc_wen_nxt = 1'd0; + else if ( control_state == SWAP_WAIT1 &&instruction_execute ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !opcode_compare && instruction[15:12] != 4'd15) + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + else if ( mem_op && ( mem_op_pre_indexed || mem_op_post_indexed ) && rn_sel_nxt != 4'd15) + // reg_bank_wen_nxt = decode ( rn_sel_nxt ); + reg_bank_wen_nxt = rn_sel_nxt == 4'h0 ? 15'h0001: + rn_sel_nxt == 4'h1 ? 15'h0002: + rn_sel_nxt == 4'h2 ? 15'h0004: + rn_sel_nxt == 4'h3 ? 15'h0008: + rn_sel_nxt == 4'h4 ? 15'h0010: + rn_sel_nxt == 4'h5 ? 15'h0020: + rn_sel_nxt == 4'h6 ? 15'h0040: + rn_sel_nxt == 4'h7 ? 15'h0080: + rn_sel_nxt == 4'h8 ? 15'h0100: + rn_sel_nxt == 4'h9 ? 15'h0200: + rn_sel_nxt == 4'ha ? 15'h0400: + rn_sel_nxt == 4'hb ? 15'h0800: + rn_sel_nxt == 4'hc ? 15'h1000: + rn_sel_nxt == 4'hd ? 15'h2000: + rn_sel_nxt == 4'he ? 15'h4000: + 15'h0000; + else if ( type == BRANCH && instruction[24]) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else if ( type == MTRANS && instruction[21] ) + //reg_bank_wen_nxt = decode (rn_sel_nxt); + reg_bank_wen_nxt = rn_sel_nxt == 4'h0 ? 15'h0001: + rn_sel_nxt == 4'h1 ? 15'h0002: + rn_sel_nxt == 4'h2 ? 15'h0004: + rn_sel_nxt == 4'h3 ? 15'h0008: + rn_sel_nxt == 4'h4 ? 15'h0010: + rn_sel_nxt == 4'h5 ? 15'h0020: + rn_sel_nxt == 4'h6 ? 15'h0040: + rn_sel_nxt == 4'h7 ? 15'h0080: + rn_sel_nxt == 4'h8 ? 15'h0100: + rn_sel_nxt == 4'h9 ? 15'h0200: + rn_sel_nxt == 4'ha ? 15'h0400: + rn_sel_nxt == 4'hb ? 15'h0800: + rn_sel_nxt == 4'hc ? 15'h1000: + rn_sel_nxt == 4'hd ? 15'h2000: + rn_sel_nxt == 4'he ? 15'h4000: + 15'h0000; + else if ( type == SWI || und_request ) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else + reg_bank_wen_nxt = 15'h0; + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else if ( control_state == MTRANS_ABORT && restore_base_address) + //reg_bank_wen_nxt = decode ( instruction[19:16] ); + reg_bank_wen_nxt = instruction[19:16] == 4'h0 ? 15'h0001: + instruction[19:16] == 4'h1 ? 15'h0002: + instruction[19:16] == 4'h2 ? 15'h0004: + instruction[19:16] == 4'h3 ? 15'h0008: + instruction[19:16] == 4'h4 ? 15'h0010: + instruction[19:16] == 4'h5 ? 15'h0020: + instruction[19:16] == 4'h6 ? 15'h0040: + instruction[19:16] == 4'h7 ? 15'h0080: + instruction[19:16] == 4'h8 ? 15'h0100: + instruction[19:16] == 4'h9 ? 15'h0200: + instruction[19:16] == 4'ha ? 15'h0400: + instruction[19:16] == 4'hb ? 15'h0800: + instruction[19:16] == 4'hc ? 15'h1000: + instruction[19:16] == 4'hd ? 15'h2000: + instruction[19:16] == 4'he ? 15'h4000: + 15'h0000; + else if ( control_state == MULT_STORE ) + begin + if ( type == MULT ) + //reg_bank_wen_nxt = decode ( instruction[19:16] ); + reg_bank_wen_nxt = instruction[19:16] == 4'h0 ? 15'h0001: + instruction[19:16] == 4'h1 ? 15'h0002: + instruction[19:16] == 4'h2 ? 15'h0004: + instruction[19:16] == 4'h3 ? 15'h0008: + instruction[19:16] == 4'h4 ? 15'h0010: + instruction[19:16] == 4'h5 ? 15'h0020: + instruction[19:16] == 4'h6 ? 15'h0040: + instruction[19:16] == 4'h7 ? 15'h0080: + instruction[19:16] == 4'h8 ? 15'h0100: + instruction[19:16] == 4'h9 ? 15'h0200: + instruction[19:16] == 4'ha ? 15'h0400: + instruction[19:16] == 4'hb ? 15'h0800: + instruction[19:16] == 4'hc ? 15'h1000: + instruction[19:16] == 4'hd ? 15'h2000: + instruction[19:16] == 4'he ? 15'h4000: + 15'h0000; + else + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + end + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] != 4'd15) + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + else + reg_bank_wen_nxt = 15'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags) + status_bits_flags_wen_nxt = 1'd1; + else if ( control_state == MULT_STORE && instruction[20]) + status_bits_flags_wen_nxt = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] == 4'd15) + status_bits_flags_wen_nxt = 1'd1; + else + status_bits_flags_wen_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict) + begin + if ( type == SWI || und_request ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else if ( regop_set_flags && instruction[15:12] == 4'd15 && (i_execute_status_bits[1:0] != USR) ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else + begin + status_bits_mode_wen_nxt = 1'd0; + status_bits_irq_mask_wen_nxt = 1'd0; + end + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else + begin + status_bits_mode_wen_nxt = 1'd0; + status_bits_irq_mask_wen_nxt = 1'd0; + end + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + status_bits_firq_mask_wen_nxt = 1'd1; + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 && next_interrupt == 3'd2 ) + status_bits_firq_mask_wen_nxt = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + status_bits_firq_mask_wen_nxt = 1'd1; + else + status_bits_firq_mask_wen_nxt = 1'd0; + end + + + +// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq +// This pre-encodes the firq_s3 signal thats used in u_register_bank +// assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ; + +assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ; + + +// ======================================================== +// Next State Logic +// ======================================================== + +// this replicates the current value of the execute signal in the execute stage +//assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] ); +assign instruction_execute = ( o_condition == AL ) || + ( o_condition == EQ && i_execute_status_bits[30] ) || + ( o_condition == NE && !i_execute_status_bits[30] ) || + ( o_condition == CS && i_execute_status_bits[29] ) || + ( o_condition == CC && !i_execute_status_bits[29] ) || + ( o_condition == MI && i_execute_status_bits[31] ) || + ( o_condition == PL && !i_execute_status_bits[31] ) || + ( o_condition == VS && i_execute_status_bits[28] ) || + ( o_condition == VC && !i_execute_status_bits[28] ) || + ( o_condition == HI && i_execute_status_bits[29] && !i_execute_status_bits[30] ) || + ( o_condition == LS && (!i_execute_status_bits[29] || i_execute_status_bits[30]) ) || + + ( o_condition == GE && i_execute_status_bits[31] == i_execute_status_bits[28] ) || + ( o_condition == LT && i_execute_status_bits[31] != i_execute_status_bits[28] ) || + + ( o_condition == GT && !i_execute_status_bits[30] && i_execute_status_bits[31] == i_execute_status_bits[28] ) || + ( o_condition == LE && (i_execute_status_bits[30] || i_execute_status_bits[31] != i_execute_status_bits[28]) ) ; + + +// First state of executing a new instruction +// Its complex because of conditional execution of multi-cycle instructions +assign instruction_valid = ((control_state == EXECUTE || control_state == PRE_FETCH_EXEC) || + // when last instruction was multi-cycle instruction but did not execute + // because condition was false then act like you're in the execute state + (!instruction_execute && (control_state == PC_STALL1 || + control_state == MEM_WAIT1 || + control_state == COPRO_WAIT || + control_state == SWAP_WRITE || + control_state == MULT_PROC1 || + control_state == MTRANS_EXEC1 ) )); + + + +always @* + begin + // default is to hold the current state +// control_state_nxt <= control_state; + + // Note: The order is important here + + if ( instruction_valid ) + begin + + if ( interrupt && !conflict ) + control_state_nxt = INT_WAIT1; + else + begin + if ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC + control_state_nxt = MEM_WAIT1; + + else if ( type == MTRANS && !conflict && mtrans_num_registers != 5'd0 && mtrans_num_registers != 5'd1 ) + control_state_nxt = MTRANS_EXEC1; + + else if ( type == MULT && !conflict ) + control_state_nxt = MULT_PROC1; + + else if ( type == SWAP && !conflict ) + control_state_nxt = SWAP_WRITE; + + else if ( type == CORTRANS && !und_request && !conflict ) + control_state_nxt = COPRO_WAIT; + else + begin + if ( load_op && instruction[15:12] == 4'd15 ) + control_state_nxt = MEM_WAIT1; + else + begin + if( current_write_pc ) + control_state_nxt = PC_STALL1; + else + control_state_nxt = EXECUTE; + end + end + end + + end + + else + begin + if ( control_state == RST_WAIT1 ) control_state_nxt = RST_WAIT2; + else if ( control_state == RST_WAIT2 ) control_state_nxt = EXECUTE; + else if ( control_state == INT_WAIT1 ) control_state_nxt = INT_WAIT2; + else if ( control_state == INT_WAIT2 ) control_state_nxt = EXECUTE; + else if ( control_state == COPRO_WAIT ) control_state_nxt = PRE_FETCH_EXEC; + else if ( control_state == PC_STALL1 ) control_state_nxt = PC_STALL2; + else if ( control_state == PC_STALL2 ) control_state_nxt = EXECUTE; + else if ( control_state == SWAP_WRITE ) control_state_nxt = SWAP_WAIT1; + else if ( control_state == SWAP_WAIT1 ) control_state_nxt = SWAP_WAIT2; + else if ( control_state == MULT_STORE ) control_state_nxt = PRE_FETCH_EXEC; + else if ( control_state == MTRANS_ABORT ) control_state_nxt = PRE_FETCH_EXEC; + + else if ( control_state == MEM_WAIT1 ) control_state_nxt = MEM_WAIT2; + + else if ( control_state == MEM_WAIT2 || control_state == SWAP_WAIT2 ) + begin + if ( write_pc ) // writing to the PC!! + control_state_nxt = PC_STALL1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + else if ( control_state == MTRANS_EXEC1 ) + begin + if ( mtrans_instruction_nxt[15:0] != 16'd0 ) + control_state_nxt = MTRANS_EXEC2; + else // if the register list holds a single register + begin + if ( dabt ) // data abort + control_state_nxt = MTRANS_ABORT; + else if ( write_pc ) // writing to the PC!! + control_state_nxt = MEM_WAIT1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + end + + // Stay in State MTRANS_EXEC2 until the full list of registers to + // load or store has been processed + + else if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 ) + begin + if ( dabt ) // data abort + control_state_nxt = MTRANS_ABORT; + else if ( write_pc ) // writing to the PC!! + control_state_nxt = MEM_WAIT1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + + else if ( control_state == MULT_PROC1 ) + begin + if (!instruction_execute) + control_state_nxt = PRE_FETCH_EXEC; + else + control_state_nxt = MULT_PROC2; + end + + else if ( control_state == MULT_PROC2 ) + begin + if ( i_multiply_done ) + begin + if ( o_multiply_function[1] ) // Accumulate ? + control_state_nxt = MULT_ACCUMU; + else + control_state_nxt = MULT_STORE; + end + else + control_state_nxt = control_state; + end + + + else if ( control_state == MULT_ACCUMU ) + begin + control_state_nxt = MULT_STORE; + end + + + else //jing + control_state_nxt = control_state; + end + + end + + +assign i_fetch = {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}; //jing +// ======================================================== +// Register Update +// ======================================================== +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if (!conflict) + begin + fetch_instruction_r <= i_fetch_instruction; +// fetch_instruction_type_r <= instruction_type(i_fetch_instruction); + + fetch_instruction_type_r <= + ( +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}[11:6] == 12'b00010?001001 ? SWAP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b000000??1001 ? MULT: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}[11:10] = 12'b00?????????? ? REGOP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b01?????????? ? TRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b100????????? ? MTRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b101????????? ? BRANCH: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b110????????? ? CODTRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b1110???????0 ? COREGOP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b1110???????1 ? CORTRANS: +// SWI + + (i_fetch[11:7] == 5'b00010 && i_fetch[5:0] == 6'b001001)? SWAP: + (i_fetch[11:6] == 6'b000000 && i_fetch[3:0] == 4'b1001 )? MULT: + i_fetch[11:10] == 2'b00 ? REGOP: + i_fetch[11:10] == 2'b01 ? TRANS: + i_fetch[11:9] == 3'b100 ? MTRANS: + i_fetch[11:9] == 3'b101 ? BRANCH: + i_fetch[11:9] == 3'b110 ? CODTRANS: + (i_fetch[11:8] == 4'b1110 && i_fetch[0] == 1'b0 )? COREGOP: + (i_fetch[11:8] == 4'b1110 && i_fetch[0] == 1'b1 )? CORTRANS: + SWI); + + fetch_address_r <= i_execute_iaddress; + iabt_reg <= i_iabt; + adex_reg <= i_adex; + abt_status_reg <= i_abt_status; + end + + o_status_bits_mode <= status_bits_mode_nxt; + o_status_bits_irq_mask <= status_bits_irq_mask_nxt; + o_status_bits_firq_mask <= status_bits_firq_mask_nxt; + o_imm32 <= imm32_nxt; + o_imm_shift_amount <= imm_shift_amount_nxt; + o_shift_imm_zero <= shift_imm_zero_nxt; + + // when have an interrupt, execute the interrupt operation + // unconditionally in the execute stage + // ensures that status_bits register gets updated correctly + // Likewise when in middle of multi-cycle instructions + // execute them unconditionally + o_condition <= instruction_valid && !interrupt ? condition_nxt : AL; + o_decode_exclusive <= decode_exclusive_nxt; + o_decode_iaccess <= decode_iaccess_nxt; + o_decode_daccess <= decode_daccess_nxt; + + o_rm_sel <= rm_sel_nxt; + o_rs_sel <= rs_sel_nxt; + o_load_rd <= load_rd_nxt; + load_rd_d1 <= load_rd_d1_nxt; + load_pc_r <= load_pc_nxt; + o_rn_sel <= rn_sel_nxt; + o_barrel_shift_amount_sel <= barrel_shift_amount_sel_nxt; + o_barrel_shift_data_sel <= barrel_shift_data_sel_nxt; + o_barrel_shift_function <= barrel_shift_function_nxt; + o_alu_function <= alu_function_nxt; + o_multiply_function <= multiply_function_nxt; + o_interrupt_vector_sel <= next_interrupt; + o_iaddress_sel <= iaddress_sel_nxt; + o_daddress_sel <= daddress_sel_nxt; + o_pc_sel <= pc_sel_nxt; + o_byte_enable_sel <= byte_enable_sel_nxt; + o_status_bits_sel <= status_bits_sel_nxt; + o_reg_write_sel <= reg_write_sel_nxt; + o_firq_not_user_mode <= firq_not_user_mode_nxt; + o_write_data_wen <= write_data_wen_nxt; + o_base_address_wen <= base_address_wen_nxt; + o_pc_wen <= pc_wen_nxt; + o_reg_bank_wen <= reg_bank_wen_nxt; + o_status_bits_flags_wen <= status_bits_flags_wen_nxt; + o_status_bits_mode_wen <= status_bits_mode_wen_nxt; + o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt; + o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt; + + o_copro_opcode1 <= instruction[23:21]; + o_copro_opcode2 <= instruction[7:5]; + o_copro_crn <= instruction[19:16]; + o_copro_crm <= instruction[3:0]; + o_copro_num <= instruction[11:8]; + o_copro_operation <= copro_operation_nxt; + o_copro_write_data_wen <= copro_write_data_wen_nxt; + restore_base_address <= restore_base_address_nxt; + control_state <= control_state_nxt; + end + + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + // sometimes this is a pre-fetch instruction + // e.g. two ldr instructions in a row. The second ldr will be saved + // to the pre-fetch instruction register + // then when its decoded, a copy is saved to the saved_current_instruction + // register + if ( type == MTRANS ) + begin + saved_current_instruction <= mtrans_instruction_nxt; + saved_current_instruction_type <= type; + saved_current_instruction_iabt <= instruction_iabt; + saved_current_instruction_adex <= instruction_adex; + saved_current_instruction_address <= instruction_address; + saved_current_instruction_iabt_status <= instruction_iabt_status; + end + else if ( saved_current_instruction_wen ) + begin + saved_current_instruction <= instruction; + saved_current_instruction_type <= type; + saved_current_instruction_iabt <= instruction_iabt; + saved_current_instruction_adex <= instruction_adex; + saved_current_instruction_address <= instruction_address; + saved_current_instruction_iabt_status <= instruction_iabt_status; + end + + if ( pre_fetch_instruction_wen ) + begin + pre_fetch_instruction <= fetch_instruction_r; + pre_fetch_instruction_type <= fetch_instruction_type_r; + pre_fetch_instruction_iabt <= iabt_reg; + pre_fetch_instruction_adex <= adex_reg; + pre_fetch_instruction_address <= fetch_address_r; + pre_fetch_instruction_iabt_status <= abt_status_reg; + end + + + // TODO possible to use saved_current_instruction instead and save some regs? + hold_instruction <= instruction; + hold_instruction_type <= type; + hold_instruction_iabt <= instruction_iabt; + hold_instruction_adex <= instruction_adex; + hold_instruction_address <= instruction_address; + hold_instruction_iabt_status <= instruction_iabt_status; + end + + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + irq <= i_irq; + firq <= i_firq; + + if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC ) + begin + dabt_reg <= 1'd0; + end + else + begin + dabt_reg <= dabt_reg || i_dabt; + end + + dabt_reg_d1 <= dabt_reg; + end + +assign dabt = dabt_reg || i_dabt; + + +// ======================================================== +// Decompiler for debugging core - not synthesizable +// ======================================================== +//synopsys translate_off + +//`include "a25/debug_functions.v" + +/*a25_decompile u_decompile ( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_instruction ( instruction ), + .i_instruction_valid ( instruction_valid &&!conflict ), + .i_instruction_execute ( instruction_execute ), + .i_instruction_address ( instruction_address ), + .i_interrupt ( {3{interrupt}} & next_interrupt ), + .i_interrupt_state ( control_state == INT_WAIT2 ), + .i_instruction_undefined ( und_request ), + .i_pc_sel ( o_pc_sel ), + .i_pc_wen ( o_pc_wen ) +); +*/ + +wire [(15*8)-1:0] xCONTROL_STATE; +wire [(15*8)-1:0] xMODE; +wire [( 8*8)-1:0] xTYPE; + +assign xCONTROL_STATE = + control_state == RST_WAIT1 ? "RST_WAIT1" : + control_state == RST_WAIT2 ? "RST_WAIT2" : + + + control_state == INT_WAIT1 ? "INT_WAIT1" : + control_state == INT_WAIT2 ? "INT_WAIT2" : + control_state == EXECUTE ? "EXECUTE" : + control_state == PRE_FETCH_EXEC ? "PRE_FETCH_EXEC" : + control_state == MEM_WAIT1 ? "MEM_WAIT1" : + control_state == MEM_WAIT2 ? "MEM_WAIT2" : + control_state == PC_STALL1 ? "PC_STALL1" : + control_state == PC_STALL2 ? "PC_STALL2" : + control_state == MTRANS_EXEC1 ? "MTRANS_EXEC1" : + control_state == MTRANS_EXEC2 ? "MTRANS_EXEC2" : + control_state == MTRANS_ABORT ? "MTRANS_ABORT" : + control_state == MULT_PROC1 ? "MULT_PROC1" : + control_state == MULT_PROC2 ? "MULT_PROC2" : + control_state == MULT_STORE ? "MULT_STORE" : + control_state == MULT_ACCUMU ? "MULT_ACCUMU" : + control_state == SWAP_WRITE ? "SWAP_WRITE" : + control_state == SWAP_WAIT1 ? "SWAP_WAIT1" : + control_state == SWAP_WAIT2 ? "SWAP_WAIT2" : + "COPRO_WAIT" ; + +//assign xMODE = mode_name ( o_status_bits_mode ); + +//assign xMODE = o_status_bits_mode == USR ? "User " : +// o_status_bits_mode == SVC ? "Supervisor " : +// o_status_bits_mode == IRQ ? "Interrupt " : +// "Fast_Interrupt" ; + +assign xTYPE = + type == REGOP ? "REGOP" : + type == MULT ? "MULT" : + type == SWAP ? "SWAP" : + type == TRANS ? "TRANS" : + type == MTRANS ? "MTRANS" : + type == BRANCH ? "BRANCH" : + type == CODTRANS ? "CODTRANS" : + type == COREGOP ? "COREGOP" : + type == CORTRANS ? "CORTRANS" : + "SWI" ; + + +/*always @( posedge i_clk ) + if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx))) + begin + `TB_ERROR_MESSAGE + $display("Instruction with x's =%08h", instruction); + end +*/ +//synopsys translate_on + +endmodule + + + +module a25_shifter_quick +( + +i_in, +i_carry_in, +i_shift_amount, +i_shift_imm_zero, +i_function, + +o_out, +o_carry_out + +); + +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + // MSB is carry out +wire [32:0] lsl_out; +wire [32:0] lsr_out; +wire [32:0] asr_out; +wire [32:0] ror_out; + + +// Logical shift right zero is redundant as it is the same as logical shift left zero, so +// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow +// lsr #32 to be specified. + +// lsl #0 is a special case, where the shifter carry out is the old value of the status flags +// C flag. The contents of Rm are used directly as the second operand. + + // only gives the correct result if the shift value is < 4 + assign lsl_out = i_shift_imm_zero ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 2'd1 ? {i_in[31], i_in[30: 0], 1'd0} : + i_shift_amount == 2'd2 ? {i_in[30], i_in[29: 0], 2'd0} : + {i_in[29], i_in[28: 0], 3'd0} ; // 3 + +// The form of the shift field which might be expected to correspond to LSR #0 is used +// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. + + // only gives the correct result if the shift value is < 4 + assign lsr_out = i_shift_imm_zero ? {i_in[31], 32'd0 } : + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], 1'd0, i_in[31: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], 2'd0, i_in[31: 2]} : + {i_in[ 2], 3'd0, i_in[31: 3]} ; // 3 + +// The form of the shift field which might be expected to give ASR #0 is used to encode +// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is +// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to +// the value of bit 31 of Rm. + + // only gives the correct result if the shift value is < 4 + assign asr_out = i_shift_imm_zero ? {i_in[31], {32{i_in[31]}} } : + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} : + {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} ; // 3 + + // only gives the correct result if the shift value is < 4 + assign ror_out = i_shift_imm_zero ? {i_in[ 0], i_carry_in, i_in[31: 1]} : // RXR, (ROR w/ imm 0) + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], i_in[ 0], i_in[31: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} : + {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} ; // 3 + +assign {o_carry_out, o_out} = i_function == LSL ? lsl_out : + i_function == LSR ? lsr_out : + i_function == ASR ? asr_out : + ror_out ; + +endmodule + + + +module a25_shifter_full +( + +i_in, +i_carry_in, +i_shift_amount, +i_shift_imm_zero, +i_function, + +o_out, +o_carry_out + +); + +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + // MSB is carry out +wire [32:0] lsl_out; +wire [32:0] lsr_out; +wire [32:0] asr_out; +wire [32:0] ror_out; + + +// Logical shift right zero is redundant as it is the same as logical shift left zero, so +// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow +// lsr #32 to be specified. + +// lsl #0 is a special case, where the shifter carry out is the old value of the status flags +// C flag. The contents of Rm are used directly as the second operand. + + assign lsl_out = i_shift_imm_zero ? {i_carry_in, i_in } : // fall through case + + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[31], i_in[30: 0], 1'd0} : + i_shift_amount == 8'd2 ? {i_in[30], i_in[29: 0], 2'd0} : + i_shift_amount == 8'd3 ? {i_in[29], i_in[28: 0], 3'd0} : + i_shift_amount == 8'd4 ? {i_in[28], i_in[27: 0], 4'd0} : + i_shift_amount == 8'd5 ? {i_in[27], i_in[26: 0], 5'd0} : + i_shift_amount == 8'd6 ? {i_in[26], i_in[25: 0], 6'd0} : + i_shift_amount == 8'd7 ? {i_in[25], i_in[24: 0], 7'd0} : + i_shift_amount == 8'd8 ? {i_in[24], i_in[23: 0], 8'd0} : + i_shift_amount == 8'd9 ? {i_in[23], i_in[22: 0], 9'd0} : + i_shift_amount == 8'd10 ? {i_in[22], i_in[21: 0], 10'd0} : + i_shift_amount == 8'd11 ? {i_in[21], i_in[20: 0], 11'd0} : + + i_shift_amount == 8'd12 ? {i_in[20], i_in[19: 0], 12'd0} : + i_shift_amount == 8'd13 ? {i_in[19], i_in[18: 0], 13'd0} : + i_shift_amount == 8'd14 ? {i_in[18], i_in[17: 0], 14'd0} : + i_shift_amount == 8'd15 ? {i_in[17], i_in[16: 0], 15'd0} : + i_shift_amount == 8'd16 ? {i_in[16], i_in[15: 0], 16'd0} : + i_shift_amount == 8'd17 ? {i_in[15], i_in[14: 0], 17'd0} : + i_shift_amount == 8'd18 ? {i_in[14], i_in[13: 0], 18'd0} : + i_shift_amount == 8'd19 ? {i_in[13], i_in[12: 0], 19'd0} : + i_shift_amount == 8'd20 ? {i_in[12], i_in[11: 0], 20'd0} : + i_shift_amount == 8'd21 ? {i_in[11], i_in[10: 0], 21'd0} : + + i_shift_amount == 8'd22 ? {i_in[10], i_in[ 9: 0], 22'd0} : + i_shift_amount == 8'd23 ? {i_in[ 9], i_in[ 8: 0], 23'd0} : + i_shift_amount == 8'd24 ? {i_in[ 8], i_in[ 7: 0], 24'd0} : + i_shift_amount == 8'd25 ? {i_in[ 7], i_in[ 6: 0], 25'd0} : + i_shift_amount == 8'd26 ? {i_in[ 6], i_in[ 5: 0], 26'd0} : + i_shift_amount == 8'd27 ? {i_in[ 5], i_in[ 4: 0], 27'd0} : + i_shift_amount == 8'd28 ? {i_in[ 4], i_in[ 3: 0], 28'd0} : + i_shift_amount == 8'd29 ? {i_in[ 3], i_in[ 2: 0], 29'd0} : + i_shift_amount == 8'd30 ? {i_in[ 2], i_in[ 1: 0], 30'd0} : + i_shift_amount == 8'd31 ? {i_in[ 1], i_in[ 0: 0], 31'd0} : + i_shift_amount == 8'd32 ? {i_in[ 0], 32'd0 } : // 32 + {1'd0, 32'd0 } ; // > 32 + + +// The form of the shift field which might be expected to correspond to LSR #0 is used +// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. + + // carry out, < -------- out ----------> + assign lsr_out = i_shift_imm_zero ? {i_in[31], 32'd0 } : + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[ 0], 1'd0, i_in[31: 1]} : + i_shift_amount == 8'd2 ? {i_in[ 1], 2'd0, i_in[31: 2]} : + i_shift_amount == 8'd3 ? {i_in[ 2], 3'd0, i_in[31: 3]} : + i_shift_amount == 8'd4 ? {i_in[ 3], 4'd0, i_in[31: 4]} : + i_shift_amount == 8'd5 ? {i_in[ 4], 5'd0, i_in[31: 5]} : + i_shift_amount == 8'd6 ? {i_in[ 5], 6'd0, i_in[31: 6]} : + i_shift_amount == 8'd7 ? {i_in[ 6], 7'd0, i_in[31: 7]} : + i_shift_amount == 8'd8 ? {i_in[ 7], 8'd0, i_in[31: 8]} : + i_shift_amount == 8'd9 ? {i_in[ 8], 9'd0, i_in[31: 9]} : + + i_shift_amount == 8'd10 ? {i_in[ 9], 10'd0, i_in[31:10]} : + i_shift_amount == 8'd11 ? {i_in[10], 11'd0, i_in[31:11]} : + i_shift_amount == 8'd12 ? {i_in[11], 12'd0, i_in[31:12]} : + i_shift_amount == 8'd13 ? {i_in[12], 13'd0, i_in[31:13]} : + i_shift_amount == 8'd14 ? {i_in[13], 14'd0, i_in[31:14]} : + i_shift_amount == 8'd15 ? {i_in[14], 15'd0, i_in[31:15]} : + i_shift_amount == 8'd16 ? {i_in[15], 16'd0, i_in[31:16]} : + i_shift_amount == 8'd17 ? {i_in[16], 17'd0, i_in[31:17]} : + i_shift_amount == 8'd18 ? {i_in[17], 18'd0, i_in[31:18]} : + i_shift_amount == 8'd19 ? {i_in[18], 19'd0, i_in[31:19]} : + + i_shift_amount == 8'd20 ? {i_in[19], 20'd0, i_in[31:20]} : + i_shift_amount == 8'd21 ? {i_in[20], 21'd0, i_in[31:21]} : + i_shift_amount == 8'd22 ? {i_in[21], 22'd0, i_in[31:22]} : + i_shift_amount == 8'd23 ? {i_in[22], 23'd0, i_in[31:23]} : + i_shift_amount == 8'd24 ? {i_in[23], 24'd0, i_in[31:24]} : + i_shift_amount == 8'd25 ? {i_in[24], 25'd0, i_in[31:25]} : + i_shift_amount == 8'd26 ? {i_in[25], 26'd0, i_in[31:26]} : + i_shift_amount == 8'd27 ? {i_in[26], 27'd0, i_in[31:27]} : + i_shift_amount == 8'd28 ? {i_in[27], 28'd0, i_in[31:28]} : + i_shift_amount == 8'd29 ? {i_in[28], 29'd0, i_in[31:29]} : + + i_shift_amount == 8'd30 ? {i_in[29], 30'd0, i_in[31:30]} : + i_shift_amount == 8'd31 ? {i_in[30], 31'd0, i_in[31 ]} : + i_shift_amount == 8'd32 ? {i_in[31], 32'd0 } : + {1'd0, 32'd0 } ; // > 32 + +// The form of the shift field which might be expected to give ASR #0 is used to encode +// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is +// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to +// the value of bit 31 of Rm. + + // carry out, < -------- out ----------> + assign asr_out = i_shift_imm_zero ? {i_in[31], {32{i_in[31]}} } : + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} : + i_shift_amount == 8'd2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} : + i_shift_amount == 8'd3 ? {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} : + i_shift_amount == 8'd4 ? {i_in[ 3], { 5{i_in[31]}}, i_in[30: 4]} : + i_shift_amount == 8'd5 ? {i_in[ 4], { 6{i_in[31]}}, i_in[30: 5]} : + i_shift_amount == 8'd6 ? {i_in[ 5], { 7{i_in[31]}}, i_in[30: 6]} : + i_shift_amount == 8'd7 ? {i_in[ 6], { 8{i_in[31]}}, i_in[30: 7]} : + i_shift_amount == 8'd8 ? {i_in[ 7], { 9{i_in[31]}}, i_in[30: 8]} : + i_shift_amount == 8'd9 ? {i_in[ 8], {10{i_in[31]}}, i_in[30: 9]} : + + i_shift_amount == 8'd10 ? {i_in[ 9], {11{i_in[31]}}, i_in[30:10]} : + i_shift_amount == 8'd11 ? {i_in[10], {12{i_in[31]}}, i_in[30:11]} : + i_shift_amount == 8'd12 ? {i_in[11], {13{i_in[31]}}, i_in[30:12]} : + i_shift_amount == 8'd13 ? {i_in[12], {14{i_in[31]}}, i_in[30:13]} : + i_shift_amount == 8'd14 ? {i_in[13], {15{i_in[31]}}, i_in[30:14]} : + i_shift_amount == 8'd15 ? {i_in[14], {16{i_in[31]}}, i_in[30:15]} : + i_shift_amount == 8'd16 ? {i_in[15], {17{i_in[31]}}, i_in[30:16]} : + i_shift_amount == 8'd17 ? {i_in[16], {18{i_in[31]}}, i_in[30:17]} : + i_shift_amount == 8'd18 ? {i_in[17], {19{i_in[31]}}, i_in[30:18]} : + i_shift_amount == 8'd19 ? {i_in[18], {20{i_in[31]}}, i_in[30:19]} : + + i_shift_amount == 8'd20 ? {i_in[19], {21{i_in[31]}}, i_in[30:20]} : + i_shift_amount == 8'd21 ? {i_in[20], {22{i_in[31]}}, i_in[30:21]} : + i_shift_amount == 8'd22 ? {i_in[21], {23{i_in[31]}}, i_in[30:22]} : + i_shift_amount == 8'd23 ? {i_in[22], {24{i_in[31]}}, i_in[30:23]} : + i_shift_amount == 8'd24 ? {i_in[23], {25{i_in[31]}}, i_in[30:24]} : + i_shift_amount == 8'd25 ? {i_in[24], {26{i_in[31]}}, i_in[30:25]} : + i_shift_amount == 8'd26 ? {i_in[25], {27{i_in[31]}}, i_in[30:26]} : + i_shift_amount == 8'd27 ? {i_in[26], {28{i_in[31]}}, i_in[30:27]} : + i_shift_amount == 8'd28 ? {i_in[27], {29{i_in[31]}}, i_in[30:28]} : + i_shift_amount == 8'd29 ? {i_in[28], {30{i_in[31]}}, i_in[30:29]} : + i_shift_amount == 8'd30 ? {i_in[29], {31{i_in[31]}}, i_in[30 ]} : + i_shift_amount == 8'd31 ? {i_in[30], {32{i_in[31]}} } : + {i_in[31], {32{i_in[31]}} } ; // >= 32 + + + // carry out, < ------- out ---------> + assign ror_out = i_shift_imm_zero ? {i_in[ 0], i_carry_in, i_in[31: 1]} : // RXR, (ROR w/ imm 0) + + i_shift_amount[7:0] == 8'd0 ? {i_carry_in, i_in } : // fall through case + + i_shift_amount[4:0] == 5'd0 ? {i_in[31], i_in } : // Rs > 31 + i_shift_amount[4:0] == 5'd1 ? {i_in[ 0], i_in[ 0], i_in[31: 1]} : + i_shift_amount[4:0] == 5'd2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} : + i_shift_amount[4:0] == 5'd3 ? {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} : + i_shift_amount[4:0] == 5'd4 ? {i_in[ 3], i_in[ 3: 0], i_in[31: 4]} : + i_shift_amount[4:0] == 5'd5 ? {i_in[ 4], i_in[ 4: 0], i_in[31: 5]} : + i_shift_amount[4:0] == 5'd6 ? {i_in[ 5], i_in[ 5: 0], i_in[31: 6]} : + i_shift_amount[4:0] == 5'd7 ? {i_in[ 6], i_in[ 6: 0], i_in[31: 7]} : + i_shift_amount[4:0] == 5'd8 ? {i_in[ 7], i_in[ 7: 0], i_in[31: 8]} : + i_shift_amount[4:0] == 5'd9 ? {i_in[ 8], i_in[ 8: 0], i_in[31: 9]} : + + i_shift_amount[4:0] == 5'd10 ? {i_in[ 9], i_in[ 9: 0], i_in[31:10]} : + i_shift_amount[4:0] == 5'd11 ? {i_in[10], i_in[10: 0], i_in[31:11]} : + i_shift_amount[4:0] == 5'd12 ? {i_in[11], i_in[11: 0], i_in[31:12]} : + i_shift_amount[4:0] == 5'd13 ? {i_in[12], i_in[12: 0], i_in[31:13]} : + i_shift_amount[4:0] == 5'd14 ? {i_in[13], i_in[13: 0], i_in[31:14]} : + i_shift_amount[4:0] == 5'd15 ? {i_in[14], i_in[14: 0], i_in[31:15]} : + i_shift_amount[4:0] == 5'd16 ? {i_in[15], i_in[15: 0], i_in[31:16]} : + i_shift_amount[4:0] == 5'd17 ? {i_in[16], i_in[16: 0], i_in[31:17]} : + i_shift_amount[4:0] == 5'd18 ? {i_in[17], i_in[17: 0], i_in[31:18]} : + i_shift_amount[4:0] == 5'd19 ? {i_in[18], i_in[18: 0], i_in[31:19]} : + + i_shift_amount[4:0] == 5'd20 ? {i_in[19], i_in[19: 0], i_in[31:20]} : + i_shift_amount[4:0] == 5'd21 ? {i_in[20], i_in[20: 0], i_in[31:21]} : + i_shift_amount[4:0] == 5'd22 ? {i_in[21], i_in[21: 0], i_in[31:22]} : + i_shift_amount[4:0] == 5'd23 ? {i_in[22], i_in[22: 0], i_in[31:23]} : + i_shift_amount[4:0] == 5'd24 ? {i_in[23], i_in[23: 0], i_in[31:24]} : + i_shift_amount[4:0] == 5'd25 ? {i_in[24], i_in[24: 0], i_in[31:25]} : + i_shift_amount[4:0] == 5'd26 ? {i_in[25], i_in[25: 0], i_in[31:26]} : + i_shift_amount[4:0] == 5'd27 ? {i_in[26], i_in[26: 0], i_in[31:27]} : + i_shift_amount[4:0] == 5'd28 ? {i_in[27], i_in[27: 0], i_in[31:28]} : + i_shift_amount[4:0] == 5'd29 ? {i_in[28], i_in[28: 0], i_in[31:29]} : + + i_shift_amount[4:0] == 5'd30 ? {i_in[29], i_in[29: 0], i_in[31:30]} : + {i_in[30], i_in[30: 0], i_in[31:31]} ; + +assign {o_carry_out, o_out} = i_function == LSL ? lsl_out : + i_function == LSR ? lsr_out : + i_function == ASR ? asr_out : + ror_out ; + +endmodule + + +module a25_barrel_shift ( + + i_clk, + i_in, + i_carry_in, + i_shift_amount, + i_shift_imm_zero, + i_function, + + o_out, + o_carry_out, + o_stall + +); + +/************************* IO Declarations *********************/ +input i_clk; +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; +output o_stall; + +/************************* IO Declarations *********************/ +wire [31:0] quick_out; +wire quick_carry_out; +wire [31:0] full_out; +wire full_carry_out; +reg [31:0] full_out_r = 32'd0; +reg full_carry_out_r = 1'd0; +reg use_quick_r = 1'd1; + + +assign o_stall = (|i_shift_amount[7:2]) & use_quick_r; +assign o_out = use_quick_r ? quick_out : full_out_r; +assign o_carry_out = use_quick_r ? quick_carry_out : full_carry_out_r; + + +// Capture the result from the full barrel shifter in case the +// quick shifter gives the wrong value +always @(posedge i_clk) + begin + full_out_r <= full_out; + full_carry_out_r <= full_carry_out; + use_quick_r <= !o_stall; + end + +// Full barrel shifter +a25_shifter_full u_shifter_full ( + .i_in ( i_in ), + .i_carry_in ( i_carry_in ), + .i_shift_amount ( i_shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_function ), + .o_out ( full_out ), + .o_carry_out ( full_carry_out ) +); + + + +// Quick barrel shifter +a25_shifter_quick u_shifter_quick ( + .i_in ( i_in ), + .i_carry_in ( i_carry_in ), + .i_shift_amount ( i_shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_function ), + .o_out ( quick_out ), + .o_carry_out ( quick_carry_out ) +); + +endmodule + + + + + +module a25_register_bank ( + + i_clk, + i_core_stall, + i_mem_stall, + + i_mode_idec, + + i_mode_exec, + + i_mode_rds_exec, + + i_firq_not_user_mode, + i_rm_sel, + i_rs_sel, + i_rn_sel, + + i_pc_wen, + i_reg_bank_wen, + + i_pc, + i_reg, + + i_wb_read_data, + i_wb_read_data_valid, + i_wb_read_data_rd, + i_wb_mode, + + i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + + o_rm, + o_rs, + o_rd, + o_rn, + o_pc + + ); + +//`include "a25/a25_localparams.v" +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + +//`include "a25/a25_functions.v" + +input i_clk; +input i_core_stall; +input i_mem_stall; + +input [1:0] i_mode_idec; // user, supervisor, irq_idec, firq_idec etc. + // Used for register writes +input [1:0] i_mode_exec; // 1 periods delayed from i_mode_idec + // Used for register reads +input [3:0] i_mode_rds_exec; // Use one-hot version specifically for rds, + // includes i_user_mode_regs_store +input i_firq_not_user_mode; +input [3:0] i_rm_sel; +input [3:0] i_rs_sel; +input [3:0] i_rn_sel; + +input i_pc_wen; +input [14:0] i_reg_bank_wen; + +input [23:0] i_pc; // program counter [25:2] +input [31:0] i_reg; + +input [31:0] i_wb_read_data; +input i_wb_read_data_valid; +input [3:0] i_wb_read_data_rd; +input [1:0] i_wb_mode; + +input [3:0] i_status_bits_flags; +input i_status_bits_irq_mask; +input i_status_bits_firq_mask; + +output [31:0] o_rm; +output [31:0] o_rs; +output [31:0] o_rd; +output [31:0] o_rn; +output [31:0] o_pc; + +reg [31:0] o_rs; // +reg [31:0] o_rd; // + +// User Mode Registers +reg [31:0] r0 = 32'hdeadbeef; +reg [31:0] r1 = 32'hdeadbeef; +reg [31:0] r2 = 32'hdeadbeef; +reg [31:0] r3 = 32'hdeadbeef; +reg [31:0] r4 = 32'hdeadbeef; +reg [31:0] r5 = 32'hdeadbeef; +reg [31:0] r6 = 32'hdeadbeef; +reg [31:0] r7 = 32'hdeadbeef; +reg [31:0] r8 = 32'hdeadbeef; +reg [31:0] r9 = 32'hdeadbeef; +reg [31:0] r10 = 32'hdeadbeef; +reg [31:0] r11 = 32'hdeadbeef; +reg [31:0] r12 = 32'hdeadbeef; +reg [31:0] r13 = 32'hdeadbeef; +reg [31:0] r14 = 32'hdeadbeef; +reg [23:0] r15 = 24'hc0ffee; + +wire [31:0] r0_out; +wire [31:0] r1_out; +wire [31:0] r2_out; +wire [31:0] r3_out; +wire [31:0] r4_out; +wire [31:0] r5_out; +wire [31:0] r6_out; +wire [31:0] r7_out; +wire [31:0] r8_out; +wire [31:0] r9_out; +wire [31:0] r10_out; +wire [31:0] r11_out; +wire [31:0] r12_out; +wire [31:0] r13_out; +wire [31:0] r14_out; +wire [31:0] r15_out_rm; +wire [31:0] r15_out_rm_nxt; +wire [31:0] r15_out_rn; + +wire [31:0] r8_rds; +wire [31:0] r9_rds; +wire [31:0] r10_rds; +wire [31:0] r11_rds; +wire [31:0] r12_rds; +wire [31:0] r13_rds; +wire [31:0] r14_rds; + +// Supervisor Mode Registers +reg [31:0] r13_svc = 32'hdeadbeef; +reg [31:0] r14_svc = 32'hdeadbeef; + +// Interrupt Mode Registers +reg [31:0] r13_irq = 32'hdeadbeef; +reg [31:0] r14_irq = 32'hdeadbeef; + +// Fast Interrupt Mode Registers +reg [31:0] r8_firq = 32'hdeadbeef; +reg [31:0] r9_firq = 32'hdeadbeef; +reg [31:0] r10_firq = 32'hdeadbeef; +reg [31:0] r11_firq = 32'hdeadbeef; +reg [31:0] r12_firq = 32'hdeadbeef; +reg [31:0] r13_firq = 32'hdeadbeef; +reg [31:0] r14_firq = 32'hdeadbeef; + +wire usr_exec; +wire svc_exec; +wire irq_exec; +wire firq_exec; + +wire usr_idec; +wire svc_idec; +wire irq_idec; +wire firq_idec; +wire [14:0] read_data_wen; +wire [14:0] reg_bank_wen_c; +wire pc_wen_c; +wire pc_dmem_wen; + +reg [14:0] decode; //jingjing + + + // Write Enables from execute stage +assign usr_idec = i_mode_idec == USR; +assign svc_idec = i_mode_idec == SVC; +assign irq_idec = i_mode_idec == IRQ; + +// pre-encoded in decode stage to speed up long path +assign firq_idec = i_firq_not_user_mode; + + // Read Enables from stage 1 (fetch) +assign usr_exec = i_mode_exec == USR; +assign svc_exec = i_mode_exec == SVC; +assign irq_exec = i_mode_exec == IRQ; +assign firq_exec = i_mode_exec == FIRQ; + +always @* +case(i_wb_read_data_rd) + 4'h0 : decode = 15'h0001 ; + 4'h1 : decode = 15'h0002 ; + 4'h2 : decode = 15'h0004 ; + 4'h3 : decode = 15'h0008 ; + 4'h4 : decode = 15'h0010 ; + 4'h5 : decode = 15'h0020 ; + 4'h6 : decode = 15'h0040 ; + 4'h7 : decode = 15'h0080 ; + 4'h8 : decode = 15'h0100 ; + 4'h9 : decode = 15'h0200 ; + 4'ha : decode = 15'h0400 ; + 4'hb : decode = 15'h0800 ; + 4'hc : decode = 15'h1000 ; + 4'hd : decode = 15'h2000 ; + 4'he : decode = 15'h4000 ; + default: decode = 15'h0000 ; +endcase + + +/* i_wb_read_data_rd == 4'h0 ? 15'h0001 : + i_wb_read_data_rd == 4'h1 ? 15'h0002 : + i_wb_read_data_rd == 4'h2 ? 15'h0004 : + i_wb_read_data_rd == 4'h3 ? 15'h0008 : + i_wb_read_data_rd == 4'h4 ? 15'h0010 : + i_wb_read_data_rd == 4'h5 ? 15'h0020 : + + i_wb_read_data_rd == 4'h6 ? 15'h0040 : + i_wb_read_data_rd == 4'h7 ? 15'h0080 : + i_wb_read_data_rd == 4'h8 ? 15'h0100 : + i_wb_read_data_rd == 4'h9 ? 15'h0200 : + i_wb_read_data_rd == 4'ha ? 15'h0400 : + i_wb_read_data_rd == 4'hb ? 15'h0800 : + i_wb_read_data_rd == 4'hc ? 15'h1000 : + i_wb_read_data_rd == 4'hd ? 15'h2000 : + i_wb_read_data_rd == 4'he ? 15'h4000 : + default: 15'h0000 ; +*/ +//& decode (i_wb_read_data_rd); +assign read_data_wen = {15{i_wb_read_data_valid & ~i_mem_stall}} + & decode; + + + +assign reg_bank_wen_c = {15{~i_core_stall}} & i_reg_bank_wen; +assign pc_wen_c = ~i_core_stall & i_pc_wen; +assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_read_data_rd == 4'd15; + + +// ======================================================== +// Register Update +// ======================================================== + + +always @ ( posedge i_clk ) + begin + // these registers are used in all modes + r0 <= reg_bank_wen_c[0 ] ? i_reg : read_data_wen[0 ] ? i_wb_read_data : r0; + r1 <= reg_bank_wen_c[1 ] ? i_reg : read_data_wen[1 ] ? i_wb_read_data : r1; + r2 <= reg_bank_wen_c[2 ] ? i_reg : read_data_wen[2 ] ? i_wb_read_data : r2; + r3 <= reg_bank_wen_c[3 ] ? i_reg : read_data_wen[3 ] ? i_wb_read_data : r3; + r4 <= reg_bank_wen_c[4 ] ? i_reg : read_data_wen[4 ] ? i_wb_read_data : r4; + r5 <= reg_bank_wen_c[5 ] ? i_reg : read_data_wen[5 ] ? i_wb_read_data : r5; + r6 <= reg_bank_wen_c[6 ] ? i_reg : read_data_wen[6 ] ? i_wb_read_data : r6; + r7 <= reg_bank_wen_c[7 ] ? i_reg : read_data_wen[7 ] ? i_wb_read_data : r7; + + // these registers are used in all modes, except fast irq + r8 <= reg_bank_wen_c[8 ] && !firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode != FIRQ ? i_wb_read_data : r8; + r9 <= reg_bank_wen_c[9 ] && !firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode != FIRQ ? i_wb_read_data : r9; + r10 <= reg_bank_wen_c[10] && !firq_idec ? i_reg : read_data_wen[10] && i_wb_mode != FIRQ ? i_wb_read_data : r10; + r11 <= reg_bank_wen_c[11] && !firq_idec ? i_reg : read_data_wen[11] && i_wb_mode != FIRQ ? i_wb_read_data : r11; + r12 <= reg_bank_wen_c[12] && !firq_idec ? i_reg : read_data_wen[12] && i_wb_mode != FIRQ ? i_wb_read_data : r12; + + // these registers are used in fast irq mode + r8_firq <= reg_bank_wen_c[8 ] && firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode == FIRQ ? i_wb_read_data : r8_firq; + r9_firq <= reg_bank_wen_c[9 ] && firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode == FIRQ ? i_wb_read_data : r9_firq; + r10_firq <= reg_bank_wen_c[10] && firq_idec ? i_reg : read_data_wen[10] && i_wb_mode == FIRQ ? i_wb_read_data : r10_firq; + r11_firq <= reg_bank_wen_c[11] && firq_idec ? i_reg : read_data_wen[11] && i_wb_mode == FIRQ ? i_wb_read_data : r11_firq; + r12_firq <= reg_bank_wen_c[12] && firq_idec ? i_reg : read_data_wen[12] && i_wb_mode == FIRQ ? i_wb_read_data : r12_firq; + + // these registers are used in user mode + r13 <= reg_bank_wen_c[13] && usr_idec ? i_reg : read_data_wen[13] && i_wb_mode == USR ? i_wb_read_data : r13; + r14 <= reg_bank_wen_c[14] && usr_idec ? i_reg : read_data_wen[14] && i_wb_mode == USR ? i_wb_read_data : r14; + + // these registers are used in supervisor mode + r13_svc <= reg_bank_wen_c[13] && svc_idec ? i_reg : read_data_wen[13] && i_wb_mode == SVC ? i_wb_read_data : r13_svc; + r14_svc <= reg_bank_wen_c[14] && svc_idec ? i_reg : read_data_wen[14] && i_wb_mode == SVC ? i_wb_read_data : r14_svc; + + // these registers are used in irq mode + r13_irq <= reg_bank_wen_c[13] && irq_idec ? i_reg : read_data_wen[13] && i_wb_mode == IRQ ? i_wb_read_data : r13_irq; + r14_irq <= (reg_bank_wen_c[14] && irq_idec) ? i_reg : read_data_wen[14] && i_wb_mode == IRQ ? i_wb_read_data : r14_irq; + + // these registers are used in fast irq mode + r13_firq <= reg_bank_wen_c[13] && firq_idec ? i_reg : read_data_wen[13] && i_wb_mode == FIRQ ? i_wb_read_data : r13_firq; + r14_firq <= reg_bank_wen_c[14] && firq_idec ? i_reg : read_data_wen[14] && i_wb_mode == FIRQ ? i_wb_read_data : r14_firq; + + // these registers are used in all modes + r15 <= pc_wen_c ? i_pc : pc_dmem_wen ? i_wb_read_data[25:2] : r15; + + end + + +// ======================================================== +// Register Read based on Mode +// ======================================================== +assign r0_out = r0; +assign r1_out = r1; +assign r2_out = r2; +assign r3_out = r3; +assign r4_out = r4; +assign r5_out = r5; +assign r6_out = r6; +assign r7_out = r7; + +assign r8_out = firq_exec ? r8_firq : r8; +assign r9_out = firq_exec ? r9_firq : r9; +assign r10_out = firq_exec ? r10_firq : r10; +assign r11_out = firq_exec ? r11_firq : r11; +assign r12_out = firq_exec ? r12_firq : r12; + +assign r13_out = usr_exec ? r13 : + svc_exec ? r13_svc : + irq_exec ? r13_irq : + r13_firq ; + +assign r14_out = usr_exec ? r14 : + svc_exec ? r14_svc : + irq_exec ? r14_irq : + r14_firq ; + + +assign r15_out_rm = { i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + r15, + i_mode_exec}; + +assign r15_out_rm_nxt = { i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + i_pc, + i_mode_exec}; + +assign r15_out_rn = {6'd0, r15, 2'd0}; + + +// rds outputs +assign r8_rds = i_mode_rds_exec[OH_FIRQ] ? r8_firq : r8; +assign r9_rds = i_mode_rds_exec[OH_FIRQ] ? r9_firq : r9; +assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10; +assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11; +assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12; + +assign r13_rds = i_mode_rds_exec[OH_USR] ? r13 : + i_mode_rds_exec[OH_SVC] ? r13_svc : + i_mode_rds_exec[OH_IRQ] ? r13_irq : + r13_firq ; + +assign r14_rds = i_mode_rds_exec[OH_USR] ? r14 : + i_mode_rds_exec[OH_SVC] ? r14_svc : + i_mode_rds_exec[OH_IRQ] ? r14_irq : + r14_firq ; + + +// ======================================================== +// Program Counter out +// ======================================================== +assign o_pc = r15_out_rn; + +// ======================================================== +// Rm Selector +// ======================================================== +assign o_rm = i_rm_sel == 4'd0 ? r0_out : + i_rm_sel == 4'd1 ? r1_out : + i_rm_sel == 4'd2 ? r2_out : + i_rm_sel == 4'd3 ? r3_out : + i_rm_sel == 4'd4 ? r4_out : + i_rm_sel == 4'd5 ? r5_out : + i_rm_sel == 4'd6 ? r6_out : + i_rm_sel == 4'd7 ? r7_out : + i_rm_sel == 4'd8 ? r8_out : + i_rm_sel == 4'd9 ? r9_out : + i_rm_sel == 4'd10 ? r10_out : + i_rm_sel == 4'd11 ? r11_out : + i_rm_sel == 4'd12 ? r12_out : + i_rm_sel == 4'd13 ? r13_out : + i_rm_sel == 4'd14 ? r14_out : + r15_out_rm ; + + +// ======================================================== +// Rds Selector +// ======================================================== +always @* + case ( i_rs_sel ) + 4'd0 : o_rs = r0_out ; + 4'd1 : o_rs = r1_out ; + 4'd2 : o_rs = r2_out ; + 4'd3 : o_rs = r3_out ; + 4'd4 : o_rs = r4_out ; + 4'd5 : o_rs = r5_out ; + 4'd6 : o_rs = r6_out ; + 4'd7 : o_rs = r7_out ; + 4'd8 : o_rs = r8_rds ; + 4'd9 : o_rs = r9_rds ; + 4'd10 : o_rs = r10_rds ; + 4'd11 : o_rs = r11_rds ; + 4'd12 : o_rs = r12_rds ; + 4'd13 : o_rs = r13_rds ; + 4'd14 : o_rs = r14_rds ; + default: o_rs = r15_out_rn ; + endcase + + + +// ======================================================== +// Rd Selector +// ======================================================== + +always @* + case ( i_rs_sel ) + 4'd0 : o_rd = r0_out ; + 4'd1 : o_rd = r1_out ; + 4'd2 : o_rd = r2_out ; + 4'd3 : o_rd = r3_out ; + 4'd4 : o_rd = r4_out ; + 4'd5 : o_rd = r5_out ; + 4'd6 : o_rd = r6_out ; + 4'd7 : o_rd = r7_out ; + 4'd8 : o_rd = r8_rds ; + 4'd9 : o_rd = r9_rds ; + 4'd10 : o_rd = r10_rds ; + 4'd11 : o_rd = r11_rds ; + 4'd12 : o_rd = r12_rds ; + 4'd13 : o_rd = r13_rds ; + 4'd14 : o_rd = r14_rds ; + default: o_rd = r15_out_rm_nxt ; + endcase + + +// ======================================================== +// Rn Selector +// ======================================================== +assign o_rn = i_rn_sel == 4'd0 ? r0_out : + i_rn_sel == 4'd1 ? r1_out : + i_rn_sel == 4'd2 ? r2_out : + i_rn_sel == 4'd3 ? r3_out : + i_rn_sel == 4'd4 ? r4_out : + i_rn_sel == 4'd5 ? r5_out : + i_rn_sel == 4'd6 ? r6_out : + i_rn_sel == 4'd7 ? r7_out : + i_rn_sel == 4'd8 ? r8_out : + i_rn_sel == 4'd9 ? r9_out : + i_rn_sel == 4'd10 ? r10_out : + i_rn_sel == 4'd11 ? r11_out : + i_rn_sel == 4'd12 ? r12_out : + i_rn_sel == 4'd13 ? r13_out : + i_rn_sel == 4'd14 ? r14_out : + r15_out_rn ; + + +endmodule + + +module a25_multiply ( + i_clk, + i_core_stall, + + i_a_in, + i_b_in, + i_function, + i_execute, + + o_out, + o_flags, + o_done + ); + +input i_clk; +input i_core_stall; + +input [31:0] i_a_in; // Rds +input [31:0] i_b_in; // Rm +input [1:0] i_function; +input i_execute; + +output [31:0] o_out; +output [1:0] o_flags; // [1] = N, [0] = Z +output o_done; // goes high 2 cycles before completion + +reg o_done = 1'd0; +wire enable; +wire accumulate; +wire [33:0] multiplier; +wire [33:0] multiplier_bar; +wire [33:0] sum; +wire [33:0] sum34_b; + +reg [5:0] count = 6'd0; +reg [5:0] count_nxt; +reg [67:0] product = 68'd0; +reg [67:0] product_nxt; +reg [1:0] flags_nxt; +wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition + + +assign enable = i_function[0]; +assign accumulate = i_function[1]; + +assign multiplier = { 2'd0, i_a_in} ; +assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ; + +assign sum34_b = product[1:0] == 2'b01 ? multiplier : + product[1:0] == 2'b10 ? multiplier_bar : + 34'd0 ; + + + // ----------------------------------- + // 34-bit adder - booth multiplication + // ----------------------------------- + assign sum = product[67:34] + sum34_b; + + // ------------------------------------ + // 33-bit adder - accumulate operations + // ------------------------------------ + assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in}; + + // assign count_nxt = count; + +always @* + begin + + + // update Negative and Zero flags + // Use registered value of product so this adds an extra cycle + // but this avoids having the 64-bit zero comparator on the + // main adder path + flags_nxt = { product[32], product[32:1] == 32'd0 }; + + + if ( count == 6'd0 ) + product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ; + else if ( count <= 6'd33 ) + product_nxt = { sum[33], sum, product[33:1]} ; + else if ( count == 6'd34 && accumulate ) + begin + // Note that bit 0 is not part of the product. It is used during the booth + // multiplication algorithm + product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate + end + else + product_nxt = product; + + + // Multiplication state counter + if (count == 6'd0) // start + count_nxt = enable ? 6'd1 : 6'd0; + else if ((count == 6'd34 && !accumulate) || // MUL + (count == 6'd35 && accumulate) ) // MLA + count_nxt = 6'd0; + else + count_nxt = count + 1'd1; + end + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + count <= i_execute ? count_nxt : count; + product <= i_execute ? product_nxt : product; + o_done <= i_execute ? count == 6'd31 : o_done; + end + +// Outputs +assign o_out = product[32:1]; +assign o_flags = flags_nxt; + +endmodule + + + + +module a25_alu ( + + i_a_in, + i_b_in, + i_barrel_shift_carry, + i_status_bits_carry, + i_function, + o_out, + o_flags +); + +/************************* IO Declarations *********************/ +input [31:0] i_a_in; +input [31:0] i_b_in; +input i_barrel_shift_carry; +input i_status_bits_carry; +input [8:0] i_function; + +output [31:0] o_out; +output [3:0] o_flags; + +/*********************** Signal Declarations *******************/ +wire [31:0] a; +wire [31:0] b; +wire [31:0] b_not; +wire [31:0] and_out; +wire [31:0] or_out; +wire [31:0] xor_out; +wire [31:0] sign_ex8_out; +wire [31:0] sign_ex_16_out; +wire [31:0] zero_ex8_out; +wire [31:0] zero_ex_16_out; +wire [32:0] fadder_out; +wire swap_sel; +wire not_sel; +wire [1:0] cin_sel; +wire cout_sel; +wire [3:0] out_sel; +wire carry_in; +wire carry_out; +wire overflow_out; +wire fadder_carry_out; + +assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function; + + +assign a = (swap_sel ) ? i_b_in : i_a_in ; + +// ======================================================== +// B Select +// ======================================================== +assign b = (swap_sel ) ? i_a_in : i_b_in ; + +// ======================================================== +// Not Select +// ======================================================== +assign b_not = (not_sel ) ? ~b : b ; + +// ======================================================== +// Cin Select +// ======================================================== +assign carry_in = (cin_sel==2'd0 ) ? 1'd0 : + (cin_sel==2'd1 ) ? 1'd1 : + i_status_bits_carry ; // add with carry + +// ======================================================== +// Cout Select +// ======================================================== +assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out : + i_barrel_shift_carry ; + +// For non-addition/subtractions that incorporate a shift +// operation, C is set to the last bit +// shifted out of the value by the shifter. + + +// ======================================================== +// Overflow out +// ======================================================== +// Only assert the overflow flag when using the adder +assign overflow_out = out_sel == 4'd1 && + // overflow if adding two positive numbers and get a negative number + ( (!a[31] && !b_not[31] && fadder_out[31]) || + // or adding two negative numbers and get a positive number + (a[31] && b_not[31] && !fadder_out[31]) ); + + +// ======================================================== +// ALU Operations +// ======================================================== + + +assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in}; + + +assign fadder_carry_out = fadder_out[32]; +assign and_out = a & b_not; +assign or_out = a | b_not; +assign xor_out = a ^ b_not; +assign zero_ex8_out = {24'd0, b_not[7:0]}; +assign zero_ex_16_out = {16'd0, b_not[15:0]}; +assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]}; +assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]}; + +// ======================================================== +// Out Select +// ======================================================== +assign o_out = out_sel == 4'd0 ? b_not : + out_sel == 4'd1 ? fadder_out[31:0] : + out_sel == 4'd2 ? zero_ex_16_out : + out_sel == 4'd3 ? zero_ex8_out : + out_sel == 4'd4 ? sign_ex_16_out : + out_sel == 4'd5 ? sign_ex8_out : + out_sel == 4'd6 ? xor_out : + out_sel == 4'd7 ? or_out : + and_out ; + +assign o_flags = { o_out[31], // negative + |o_out == 1'd0, // zero + carry_out, // carry + overflow_out // overflow + }; + + +endmodule + + +module a25_execute ( + +i_clk, +i_core_stall, +i_mem_stall, +o_exec_stall, + +i_wb_read_data, +i_wb_read_data_valid, +i_wb_load_rd, + +i_copro_read_data, +i_decode_iaccess, +i_decode_daccess, +i_decode_load_rd, + +o_copro_write_data, +o_write_data, +o_iaddress, +o_iaddress_nxt, + +o_iaddress_valid, +o_daddress, +o_daddress_nxt, + +o_daddress_valid, +o_adex, +o_priviledged, +o_exclusive, +o_write_enable, +o_byte_enable, +o_exec_load_rd, +o_status_bits, +o_multiply_done, + +i_status_bits_mode, +i_status_bits_irq_mask, +i_status_bits_firq_mask, +i_imm32, +i_imm_shift_amount, +i_shift_imm_zero, +i_condition, +i_decode_exclusive, + +i_rm_sel, +i_rs_sel, +i_rn_sel, +i_barrel_shift_amount_sel, +i_barrel_shift_data_sel, +i_barrel_shift_function, +i_alu_function, +i_multiply_function, +i_interrupt_vector_sel, +i_iaddress_sel, +i_daddress_sel, +i_pc_sel, +i_byte_enable_sel, +i_status_bits_sel, +i_reg_write_sel, +i_user_mode_regs_store_nxt, +i_firq_not_user_mode, + +i_write_data_wen, +i_base_address_wen, +i_pc_wen, +i_reg_bank_wen, +i_status_bits_flags_wen, +i_status_bits_mode_wen, +i_status_bits_irq_mask_wen, +i_status_bits_firq_mask_wen, +i_copro_write_data_wen, +i_conflict, +i_rn_use_read, +i_rm_use_read, +i_rs_use_read, +i_rd_use_read +); + + +//`include "a25/a25_localparams.v" + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 6'b0, //0 + OH_IRQ = 6'b1, //1 + OH_FIRQ = 6'b10, //2 + OH_SVC = 6'b11; //3 + + +//`include "a25/a25_functions.v" + +input i_clk; +input i_core_stall; // stall all stages of the Amber core at the same time +input i_mem_stall; // data memory access stalls +output o_exec_stall; // stall the core pipeline + +input [31:0] i_wb_read_data; // data reads +input i_wb_read_data_valid; // read data is valid +input [10:0] i_wb_load_rd; // Rd for data reads + +input [31:0] i_copro_read_data; // From Co-Processor, to either Register + // or Memory +input i_decode_iaccess; // Indicates an instruction access +input i_decode_daccess; // Indicates a data access +input [7:0] i_decode_load_rd; // The destination register for a load instruction + +output [31:0] o_copro_write_data; +output [31:0] o_write_data; +output [31:0] o_iaddress; +output [31:0] o_iaddress_nxt; // un-registered version of address to the + // cache rams address ports +output o_iaddress_valid; // High when instruction address is valid +output [31:0] o_daddress; // Address to data cache +output [31:0] o_daddress_nxt; // un-registered version of address to the + // cache rams address ports +output o_daddress_valid; // High when data address is valid +output o_adex; // Address Exception +output o_priviledged; // Priviledged access +output o_exclusive; // swap access +output o_write_enable; +output [3:0] o_byte_enable; +output [8:0] o_exec_load_rd; // The destination register for a load instruction +output [31:0] o_status_bits; // Full PC will all status bits, but PC part zero'ed out +output o_multiply_done; + + +// -------------------------------------------------- +// Control signals from Instruction Decode stage +// -------------------------------------------------- +input [1:0] i_status_bits_mode; +input i_status_bits_irq_mask; +input i_status_bits_firq_mask; +input [31:0] i_imm32; +input [4:0] i_imm_shift_amount; +input i_shift_imm_zero; +input [3:0] i_condition; +input i_decode_exclusive; // swap access + +input [3:0] i_rm_sel; +input [3:0] i_rs_sel; +input [3:0] i_rn_sel; +input [1:0] i_barrel_shift_amount_sel; +input [1:0] i_barrel_shift_data_sel; +input [1:0] i_barrel_shift_function; +input [8:0] i_alu_function; +input [1:0] i_multiply_function; +input [2:0] i_interrupt_vector_sel; +input [3:0] i_iaddress_sel; +input [3:0] i_daddress_sel; +input [2:0] i_pc_sel; +input [1:0] i_byte_enable_sel; +input [2:0] i_status_bits_sel; +input [2:0] i_reg_write_sel; +input i_user_mode_regs_store_nxt; +input i_firq_not_user_mode; + +input i_write_data_wen; +input i_base_address_wen; // save LDM base address register, + // in case of data abort +input i_pc_wen; +input [14:0] i_reg_bank_wen; +input i_status_bits_flags_wen; +input i_status_bits_mode_wen; +input i_status_bits_irq_mask_wen; +input i_status_bits_firq_mask_wen; +input i_copro_write_data_wen; +input i_conflict; +input i_rn_use_read; +input i_rm_use_read; +input i_rs_use_read; +input i_rd_use_read; + + + +reg [31:0] o_copro_write_data = 32'd0; +reg [31:0] o_write_data = 32'd0; +reg [31:0] o_iaddress = 32'hdeaddead; + +reg o_iaddress_valid = 1'd0; // High when instruction address is valid +reg [31:0] o_daddress = 32'h0; // Address to data cache + +reg o_daddress_valid = 1'd0; // High when data address is valid +reg o_adex = 1'd0; // Address Exception +reg o_priviledged = 1'd0; // Priviledged access +reg o_exclusive = 1'd0; // swap access +reg o_write_enable = 1'd0; +reg [3:0] o_byte_enable = 4'd0; +reg [8:0] o_exec_load_rd = 9'd0; // The destination register for a load instruction + + +// ======================================================== +// Internal signals +// ======================================================== +wire [31:0] write_data_nxt; +wire [3:0] byte_enable_nxt; +wire [31:0] pc_plus4; +wire [31:0] pc_minus4; +wire [31:0] daddress_plus4; +wire [31:0] alu_plus4; +wire [31:0] rn_plus4; +wire [31:0] alu_out; +wire [3:0] alu_flags; +wire [31:0] rm; +wire [31:0] rs; +wire [31:0] rd; +wire [31:0] rn; +wire [31:0] reg_bank_rn; +wire [31:0] reg_bank_rm; +wire [31:0] reg_bank_rs; +wire [31:0] reg_bank_rd; +wire [31:0] pc; +wire [31:0] pc_nxt; +wire [31:0] interrupt_vector; +wire [7:0] shift_amount; +wire [31:0] barrel_shift_in; +wire [31:0] barrel_shift_out; +wire barrel_shift_carry; +wire barrel_shift_stall; + +wire [3:0] status_bits_flags_nxt; +reg [3:0] status_bits_flags = 4'd0; +wire [1:0] status_bits_mode_nxt; +reg [1:0] status_bits_mode = 2'b11; //SVC = 2'b11 + // one-hot encoded rs select +wire [3:0] status_bits_mode_rds_oh_nxt; + +//reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC; +reg [3:0] status_bits_mode_rds_oh = 4'b1000; +wire status_bits_mode_rds_oh_update; +wire status_bits_irq_mask_nxt; +reg status_bits_irq_mask = 1'd1; +wire status_bits_firq_mask_nxt; +reg status_bits_firq_mask = 1'd1; +wire [8:0] exec_load_rd_nxt; + +wire execute; // high when condition execution is true +wire [31:0] reg_write_nxt; +wire pc_wen; +wire [14:0] reg_bank_wen; +wire [31:0] multiply_out; +wire [1:0] multiply_flags; +reg [31:0] base_address = 32'd0; // Saves base address during LDM instruction in + // case of data abort +wire [31:0] read_data_filtered1; +wire [31:0] read_data_filtered; +wire [31:0] read_data_filtered_c; +reg [31:0] read_data_filtered_r = 32'd0; +reg [3:0] load_rd_r = 4'd0; +wire [3:0] load_rd_c; + +wire write_enable_nxt; +wire daddress_valid_nxt; +wire iaddress_valid_nxt; +wire priviledged_nxt; +wire priviledged_update; +wire iaddress_update; +wire daddress_update; +wire base_address_update; +wire write_data_update; +wire copro_write_data_update; +wire byte_enable_update; +wire exec_load_rd_update; +wire write_enable_update; +wire exclusive_update; +wire status_bits_flags_update; +wire status_bits_mode_update; +wire status_bits_irq_mask_update; +wire status_bits_firq_mask_update; + +wire [31:0] alu_out_pc_filtered; +wire adex_nxt; +wire [31:0] save_int_pc; +wire [31:0] save_int_pc_m4; +wire ldm_flags; +wire ldm_status_bits; + + +// ======================================================== +// Status Bits in PC register +// ======================================================== +wire [1:0] status_bits_mode_out; +wire [3:0] pc_dmem_wen; //jing + + +assign status_bits_mode_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && !ldm_status_bits) ? + alu_out[1:0] : status_bits_mode ; + +assign o_status_bits = { status_bits_flags, // 31:28 + status_bits_irq_mask, // 7 27 + status_bits_firq_mask, // 6 26 + 24'd0, // 25:2 + status_bits_mode_out }; // 1:0 = mode + + +// ======================================================== +// Status Bits Select +// ======================================================== +assign ldm_flags = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[8]; +assign ldm_status_bits = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7]; + + +assign status_bits_flags_nxt = ldm_flags ? read_data_filtered[31:28] : + i_status_bits_sel == 3'd0 ? alu_flags : + i_status_bits_sel == 3'd1 ? alu_out [31:28] : + i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] : + // 4 = update status_bits_flags after a multiply operation + { multiply_flags, status_bits_flags[1:0] } ; + +assign status_bits_mode_nxt = ldm_status_bits ? read_data_filtered [1:0] : + i_status_bits_sel == 3'd0 ? i_status_bits_mode : + i_status_bits_sel == 3'd1 ? alu_out [1:0] : + i_copro_read_data [1:0] ; + + +// Used for the Rds output of register_bank - this special version of +// status_bits_mode speeds up the critical path from status_bits_mode through the +// register_bank, barrel_shifter and alu. It moves a mux needed for the +// i_user_mode_regs_store_nxt signal back into the previous stage - +// so its really part of the decode stage even though the logic is right here +// In addition the signal is one-hot encoded to further speed up the logic + +//assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR : +// status_bits_mode_update ? oh_status_bits_mode(status_bits_mode_nxt) : +// oh_status_bits_mode(status_bits_mode) ; + + +assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 4'b0001 : //1'd1 << OH_USR + status_bits_mode_update ? ( status_bits_mode_nxt == SVC ? 4'b1000 : //1'd1 << OH_SVC + status_bits_mode_nxt == IRQ ? 4'b0010 : //1'd1 << OH_IRQ + status_bits_mode_nxt == FIRQ ? 4'b0100 : //1'd1 << OH_FIRQ + 4'b0001 ): //1'd1 << OH_USR + + ( status_bits_mode == SVC ? 4'b1000 : //1'd1 << OH_SVC + status_bits_mode == IRQ ? 4'b0010 : //1'd1 << OH_IRQ + status_bits_mode == FIRQ ? 4'b0100 : //1'd1 << OH_FIRQ + 4'b0001 ); //1'd1 << OH_USR + +assign status_bits_irq_mask_nxt = ldm_status_bits ? read_data_filtered [27] : + i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask : + i_status_bits_sel == 3'd1 ? alu_out [27] : + i_copro_read_data [27] ; + +assign status_bits_firq_mask_nxt = ldm_status_bits ? read_data_filtered [26] : + i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask : + i_status_bits_sel == 3'd1 ? alu_out [26] : + i_copro_read_data [26] ; +// ======================================================== +// Adders +// ======================================================== +assign pc_plus4 = pc + 32'd4; +assign pc_minus4 = pc - 32'd4; +assign daddress_plus4 = o_daddress + 32'd4; +assign alu_plus4 = alu_out + 32'd4; +assign rn_plus4 = rn + 32'd4; + +// ======================================================== +// Barrel Shift Amount Select +// ======================================================== +// An immediate shift value of 0 is translated into 32 +assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 : + i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] : + {3'd0, i_imm_shift_amount } ; + + +// ======================================================== +// Barrel Shift Data Select +// ======================================================== +assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32 : rm ; + + +// ======================================================== +// Interrupt vector Select +// ======================================================== + +assign interrupt_vector = // Reset vector + (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 : + // Data abort interrupt vector + (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 : + // Fast interrupt vector + (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c : + // Regular interrupt vector + (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 : + // Prefetch abort interrupt vector + (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c : + // Undefined instruction interrupt vector + (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 : + // Software (SWI) interrupt vector + (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 : + // Default is the address exception interrupt + 32'h00000014 ; + + +// ======================================================== +// Address Select +// ======================================================== + +assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15; +//always @( posedge i_clk ) +// pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15; + +// If rd is the pc, then seperate the address bits from the status bits for +// generating the next address to fetch +//assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? pcf(alu_out) : alu_out; + +assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? {6'd0, alu_out[25:2], 2'd0} : alu_out; + +// if current instruction does not execute because it does not meet the condition +// then address advances to next instruction +assign o_iaddress_nxt = (pc_dmem_wen) ? {6'd0, read_data_filtered[25:2], 2'd0} : + (!execute) ? pc_plus4 : + (i_iaddress_sel == 4'd0) ? pc_plus4 : + (i_iaddress_sel == 4'd1) ? alu_out_pc_filtered : + (i_iaddress_sel == 4'd2) ? interrupt_vector : + pc ; + +// if current instruction does not execute because it does not meet the condition +// then address advances to next instruction +assign o_daddress_nxt = (i_daddress_sel == 4'd1) ? alu_out_pc_filtered : + (i_daddress_sel == 4'd2) ? interrupt_vector : + (i_daddress_sel == 4'd4) ? rn : + (i_daddress_sel == 4'd5) ? daddress_plus4 : // MTRANS address incrementer + (i_daddress_sel == 4'd6) ? alu_plus4 : // MTRANS decrement after + rn_plus4 ; // MTRANS increment before + +// Data accesses use 32-bit address space, but instruction +// accesses are restricted to 26 bit space +assign adex_nxt = |o_iaddress_nxt[31:26] && i_decode_iaccess; + + +// ======================================================== +// Filter Read Data +// ======================================================== +// mem_load_rd[10:9]-> shift ROR bytes +// mem_load_rd[8] -> load flags with PC +// mem_load_rd[7] -> load status bits with PC +// mem_load_rd[6:5] -> Write into this Mode registers +// mem_load_rd[4] -> zero_extend byte +// mem_load_rd[3:0] -> Destination Register +assign read_data_filtered1 = i_wb_load_rd[10:9] == 2'd0 ? i_wb_read_data : + i_wb_load_rd[10:9] == 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} : + i_wb_load_rd[10:9] == 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} : + {i_wb_read_data[23:0], i_wb_read_data[31:24]} ; + +assign read_data_filtered = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ; + + +// ======================================================== +// Program Counter Select +// ======================================================== +// If current instruction does not execute because it does not meet the condition +// then PC advances to next instruction +assign pc_nxt = (!execute) ? pc_plus4 : + i_pc_sel == 3'd0 ? pc_plus4 : + i_pc_sel == 3'd1 ? alu_out : + i_pc_sel == 3'd2 ? interrupt_vector : + i_pc_sel == 3'd3 ? {6'd0, read_data_filtered[25:2], 2'd0} : + pc_minus4 ; + + +// ======================================================== +// Register Write Select +// ======================================================== + +assign save_int_pc = { status_bits_flags, + status_bits_irq_mask, + status_bits_firq_mask, + pc[25:2], + status_bits_mode }; + + +assign save_int_pc_m4 = { status_bits_flags, + status_bits_irq_mask, + status_bits_firq_mask, + pc_minus4[25:2], + status_bits_mode }; + + +assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out : + // save pc to lr on an interrupt + i_reg_write_sel == 3'd1 ? save_int_pc_m4 : + // to update Rd at the end of Multiplication + i_reg_write_sel == 3'd2 ? multiply_out : + i_reg_write_sel == 3'd3 ? o_status_bits : + i_reg_write_sel == 3'd5 ? i_copro_read_data : // mrc + i_reg_write_sel == 3'd6 ? base_address : + save_int_pc ; + + +// ======================================================== +// Byte Enable Select +// ======================================================== +assign byte_enable_nxt = i_byte_enable_sel == 2'd0 ? 4'b1111 : // word write + i_byte_enable_sel == 2'd2 ? // halfword write + ( o_daddress_nxt[1] == 1'd0 ? 4'b0011 : + 4'b1100 ) : + + o_daddress_nxt[1:0] == 2'd0 ? 4'b0001 : // byte write + o_daddress_nxt[1:0] == 2'd1 ? 4'b0010 : + o_daddress_nxt[1:0] == 2'd2 ? 4'b0100 : + 4'b1000 ; + + +// ======================================================== +// Write Data Select +// ======================================================== +assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd : + {rd[7:0],rd[7:0],rd[7:0],rd[7:0]} ; + + +// ======================================================== +// Conditional Execution +// ======================================================== +//assign execute = conditional_execute ( i_condition, status_bits_flags ); + +assign execute = ( i_condition == AL ) || + ( i_condition == EQ && status_bits_flags[2] ) || + ( i_condition == NE && !status_bits_flags[2] ) || + ( i_condition == CS && status_bits_flags[1] ) || + ( i_condition == CC && !status_bits_flags[1] ) || + ( i_condition == MI && status_bits_flags[3] ) || + ( i_condition == PL && !status_bits_flags[3] ) || + ( i_condition == VS && status_bits_flags[0] ) || + ( i_condition == VC && !status_bits_flags[0] ) || + ( i_condition == HI && status_bits_flags[1] && !status_bits_flags[2] ) || + ( i_condition == LS && (!status_bits_flags[1] || status_bits_flags[2]) ) || + ( i_condition == GE && status_bits_flags[3] == status_bits_flags[0] ) || + ( i_condition == LT && status_bits_flags[3] != status_bits_flags[0] ) || + ( i_condition == GT && !status_bits_flags[2] && status_bits_flags[3] == status_bits_flags[0] ) || + ( i_condition == LE && (status_bits_flags[2] || status_bits_flags[3] != status_bits_flags[0])) ; + + +// allow the PC to increment to the next instruction when current +// instruction does not execute +assign pc_wen = (i_pc_wen || !execute) && !i_conflict; + +// only update register bank if current instruction executes +//assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen}; + assign reg_bank_wen = execute ==1'd1? {15'b111111111111111 & i_reg_bank_wen} : + {15'b0 & i_reg_bank_wen}; + +// ======================================================== +// Priviledged output flag +// ======================================================== +// Need to look at status_bits_mode_nxt so switch to priviledged mode +// at the same time as assert interrupt vector address + +assign priviledged_nxt = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ; + + +// ======================================================== +// Write Enable +// ======================================================== +// This must be de-asserted when execute is fault + +assign write_enable_nxt = execute && i_write_data_wen; + + +// ======================================================== +// Address Valid +// ======================================================== +assign daddress_valid_nxt = execute && i_decode_daccess && !i_core_stall; + +// For some multi-cycle instructions, the stream of instrution +// reads can be paused. However if the instruction does not execute +// then the read stream must not be interrupted. +assign iaddress_valid_nxt = i_decode_iaccess || !execute; + +// ======================================================== +// Use read value from data memory instead of from register +// ======================================================== +assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn; +assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm; +assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs; +assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd; + + +always@( posedge i_clk ) + if ( i_wb_read_data_valid ) + begin + read_data_filtered_r <= read_data_filtered; + load_rd_r <= i_wb_load_rd[3:0]; + end + +assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r; +assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r; + + +// ======================================================== +// Set mode for the destination registers of a mem read +// ======================================================== +// The mode is either user mode, or the current mode +assign exec_load_rd_nxt = { i_decode_load_rd[7:6], + i_decode_load_rd[5] ? USR : status_bits_mode, // 1 bit -> 2 bits + i_decode_load_rd[4:0] }; + + +// ======================================================== +// Register Update +// ======================================================== +assign o_exec_stall = barrel_shift_stall; + +assign daddress_update = !i_core_stall; +assign exec_load_rd_update = !i_core_stall && execute; +assign priviledged_update = !i_core_stall; +assign exclusive_update = !i_core_stall && execute; +assign write_enable_update = !i_core_stall; +assign write_data_update = !i_core_stall && execute && i_write_data_wen; +assign byte_enable_update = !i_core_stall && execute && i_write_data_wen; + +assign iaddress_update = pc_dmem_wen || (!i_core_stall && !i_conflict); +assign copro_write_data_update = !i_core_stall && execute && i_copro_write_data_wen; + +assign base_address_update = !i_core_stall && execute && i_base_address_wen; +assign status_bits_flags_update = ldm_flags || (!i_core_stall && execute && i_status_bits_flags_wen); +assign status_bits_mode_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_mode_wen); +assign status_bits_mode_rds_oh_update = !i_core_stall; +assign status_bits_irq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_irq_mask_wen); +assign status_bits_firq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_firq_mask_wen); + + +always @( posedge i_clk ) + begin + o_daddress <= daddress_update ? o_daddress_nxt : o_daddress; + o_daddress_valid <= daddress_update ? daddress_valid_nxt : o_daddress_valid; + o_exec_load_rd <= exec_load_rd_update ? exec_load_rd_nxt : o_exec_load_rd; + o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged; + o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive; + o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable; + o_write_data <= write_data_update ? write_data_nxt : o_write_data; + o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable; + o_iaddress <= iaddress_update ? o_iaddress_nxt : o_iaddress; + o_iaddress_valid <= iaddress_update ? iaddress_valid_nxt : o_iaddress_valid; + o_adex <= iaddress_update ? adex_nxt : o_adex; + o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data; + + base_address <= base_address_update ? rn : base_address; + + status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags; + status_bits_mode <= status_bits_mode_update ? status_bits_mode_nxt : status_bits_mode; + status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh; + status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask; + status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask; + end + + +// ======================================================== +// Instantiate Barrel Shift +// ======================================================== +a25_barrel_shift u_barrel_shift ( + .i_clk ( i_clk ), + .i_in ( barrel_shift_in ), + .i_carry_in ( status_bits_flags[1] ), + .i_shift_amount ( shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_barrel_shift_function ), + + .o_out ( barrel_shift_out ), + .o_carry_out ( barrel_shift_carry ), + .o_stall ( barrel_shift_stall ) +); + + +// ======================================================== +// Instantiate ALU +// ======================================================== +a25_alu u_alu ( + .i_a_in ( rn ), + .i_b_in ( barrel_shift_out ), + .i_barrel_shift_carry ( barrel_shift_carry ), + .i_status_bits_carry ( status_bits_flags[1] ), + .i_function ( i_alu_function ), + + .o_out ( alu_out ), + .o_flags ( alu_flags ) +); + + +// ======================================================== +// Instantiate Booth 64-bit Multiplier-Accumulator +// ======================================================== +a25_multiply u_multiply ( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_a_in ( rs ), + .i_b_in ( rm ), + .i_function ( i_multiply_function ), + .i_execute ( execute ), + .o_out ( multiply_out ), + .o_flags ( multiply_flags ), // [1] = N, [0] = Z + .o_done ( o_multiply_done ) +); + + +// ======================================================== +// Instantiate Register Bank +// ======================================================== +a25_register_bank u_register_bank( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_mem_stall ( i_mem_stall ), + .i_mode_idec ( i_status_bits_mode ), + .i_mode_exec ( status_bits_mode ), + .i_mode_rds_exec ( status_bits_mode_rds_oh ), + + // pre-encoded in decode stage to speed up long path + .i_firq_not_user_mode ( i_firq_not_user_mode ), + .i_rm_sel ( i_rm_sel ), + .i_rs_sel ( i_rs_sel ), + .i_rn_sel ( i_rn_sel ), + .i_pc_wen ( pc_wen ), + .i_reg_bank_wen ( reg_bank_wen ), + .i_pc ( pc_nxt[25:2] ), + .i_reg ( reg_write_nxt ), + + + + .i_wb_read_data ( read_data_filtered ), + .i_wb_read_data_valid ( i_wb_read_data_valid ), + .i_wb_read_data_rd ( i_wb_load_rd[3:0] ), + .i_wb_mode ( i_wb_load_rd[6:5] ), + + .i_status_bits_flags ( status_bits_flags ), + .i_status_bits_irq_mask ( status_bits_irq_mask ), + .i_status_bits_firq_mask ( status_bits_firq_mask ), + + + + // use one-hot version for speed, combine with i_user_mode_regs_store + + + .o_rm ( reg_bank_rm ), + .o_rs ( reg_bank_rs ), + .o_rd ( reg_bank_rd ), + .o_rn ( reg_bank_rn ), + .o_pc ( pc ) +); + + + +// ======================================================== +// Debug - non-synthesizable code +// ======================================================== +//synopsys translate_off + +wire [(2*8)-1:0] xCONDITION; +wire [(4*8)-1:0] xMODE; + +assign xCONDITION = i_condition == EQ ? "EQ" : + i_condition == NE ? "NE" : + i_condition == CS ? "CS" : + i_condition == CC ? "CC" : + i_condition == MI ? "MI" : + i_condition == PL ? "PL" : + i_condition == VS ? "VS" : + i_condition == VC ? "VC" : + i_condition == HI ? "HI" : + i_condition == LS ? "LS" : + i_condition == GE ? "GE" : + i_condition == LT ? "LT" : + i_condition == GT ? "GT" : + i_condition == LE ? "LE" : + i_condition == AL ? "AL" : + "NV " ; + +assign xMODE = status_bits_mode == SVC ? "SVC" : + status_bits_mode == IRQ ? "IRQ" : + status_bits_mode == FIRQ ? "FIRQ" : + "USR" ; + + +//synopsys translate_on + +endmodule + + +module a25_dcache + + ( + i_clk, + i_request, + i_exclusive, + i_write_data, + i_write_enable, + i_address, + i_address_nxt, + i_byte_enable, + i_cache_enable, + i_cache_flush, + i_fetch_stall, + i_exec_stall, + i_wb_cached_rdata, + i_wb_cached_ready, + + o_read_data, + o_stall, + o_wb_cached_req + ); + + + +`ifndef _A25_CONFIG_DEFINES +`define _A25_CONFIG_DEFINES + +// Cache Ways +// Changing this parameter is the recommended +// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported. +// +// 2 ways -> 8KB cache +// 3 ways -> 12KB cache +// 4 ways -> 16KB cache +// 8 ways -> 32KB cache +// +// e.g. if both caches have 8 ways, the total is 32KB icache + 32KB dcache = 64KB + +`define A25_ICACHE_WAYS 4 +`define A25_DCACHE_WAYS 4 + + +// -------------------------------------------------------------------- +// Debug switches +// -------------------------------------------------------------------- + +// Enable the decompiler. The default output file is amber.dis +//`define A25_DECOMPILE + +// Co-processor 15 debug. Registers in here control the cache +//`define A25_COPRO15_DEBUG + +// Cache debug +//`define A25_CACHE_DEBUG + +// -------------------------------------------------------------------- + + +// -------------------------------------------------------------------- +// File Names +// -------------------------------------------------------------------- +//`ifndef A25_DECOMPILE_FILE +// `define A25_DECOMPILE_FILE "amber.dis" +//`endif + +`endif +// --------------------------------------------------------- +// Cache Configuration + +// Limited to Linux 4k page sizes -> 256 lines +parameter CACHE_LINES = 256; + +// This cannot be changed without some major surgeory on +// this module +parameter CACHE_WORDS_PER_LINE = 4; + +// Changing this parameter is the recommended +// way to change the overall cache size; 2, 4 and 8 ways are supported. +// 2 ways -> 8KB cache +// 4 ways -> 16KB cache +// 8 ways -> 32KB cache +parameter WAYS = `A25_DCACHE_WAYS; //4 + +// derived configuration parameters +//parameter CACHE_ADDR_WIDTH = log2 ( CACHE_LINES ); // = 8 +//parameter WORD_SEL_WIDTH = log2 ( CACHE_WORDS_PER_LINE ); // = 2 +//parameter TAG_ADDR_WIDTH = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2; // = 20 +//parameter TAG_WIDTH = TAG_ADDR_WIDTH + 1; // = 21, including Valid flag +//parameter CACHE_LINE_WIDTH = CACHE_WORDS_PER_LINE * 32; // = 128 +//parameter TAG_ADDR32_LSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2; // = 12 +//parameter CACHE_ADDR32_MSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1; // = 11 +//parameter CACHE_ADDR32_LSB = WORD_SEL_WIDTH + 2; // = 4 +//parameter WORD_SEL_MSB = WORD_SEL_WIDTH + 2 - 1; // = 3 +//parameter WORD_SEL_LSB = 2; // = 2 +// --------------------------------------------------------- + +parameter CACHE_ADDR_WIDTH = 8; // = 8 +parameter WORD_SEL_WIDTH = 2; // = 2 +parameter TAG_ADDR_WIDTH = 20; // = 20 +parameter TAG_WIDTH = 21; // = 21, including Valid flag +parameter CACHE_LINE_WIDTH = 128; // = 128 +parameter TAG_ADDR32_LSB = 12; // = 12 +parameter CACHE_ADDR32_MSB = 11; // = 11 +parameter CACHE_ADDR32_LSB = 4; // = 4 +parameter WORD_SEL_MSB = 3; // = 3 +parameter WORD_SEL_LSB = 2; // = 2 + + +input i_clk; // Read / Write requests from core +input i_request; +input i_exclusive; // exclusive access, part of swap instruction +input [31:0] i_write_data; +input i_write_enable; // write request from execute stage +input [31:0] i_address; // registered address from execute +input [31:0] i_address_nxt; // un-registered version of address from execute stage +input [3:0] i_byte_enable; +input i_cache_enable; // from co-processor 15 configuration register +input i_cache_flush; // from co-processor 15 register + +output [31:0] o_read_data; +input i_fetch_stall; +input i_exec_stall; +output o_stall; + +// WB Read Request +output o_wb_cached_req; // Read Request +input [127:0] i_wb_cached_rdata; // wb bus +input i_wb_cached_ready; // wb_stb && !wb_ack + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + +// One-hot encoded +localparam C_INIT = 0, + C_CORE = 1, + C_FILL = 2, + C_INVA = 3, + C_STATES = 4; + +localparam [3:0] CS_INIT = 4'd0, + CS_IDLE = 4'd1, + CS_FILL = 4'd2, + CS_FILL_COMPLETE = 4'd3, + CS_TURN_AROUND = 4'd4, + CS_WRITE_HIT = 4'd5, + CS_WRITE_HIT_WAIT_WB = 4'd6, + CS_WRITE_MISS_WAIT_WB = 4'd7, + CS_EX_DELETE = 4'd8; + + +reg [3:0] c_state = CS_IDLE; +//reg [C_STATES-1:0] source_sel = 4'd1 << C_CORE; +reg [C_STATES-1:0] source_sel = 4'b10; +reg [CACHE_ADDR_WIDTH:0] init_count = 9'd0; + +wire [TAG_WIDTH-1:0] tag_rdata_way0; +wire [TAG_WIDTH-1:0] tag_rdata_way1; +wire [TAG_WIDTH-1:0] tag_rdata_way2; +wire [TAG_WIDTH-1:0] tag_rdata_way3; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way0; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way1; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way2; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way3; +wire [WAYS-1:0] data_wenable_way; +wire [WAYS-1:0] data_hit_way; +reg [WAYS-1:0] data_hit_way_r = 4'd0; +wire [WAYS-1:0] tag_wenable_way; +reg [WAYS-1:0] select_way = 4'd0; +wire [WAYS-1:0] next_way; +reg [WAYS-1:0] valid_bits_r = 4'd0; + +reg [3:0] random_num = 4'hf; + +wire [CACHE_ADDR_WIDTH-1:0] tag_address; +wire [TAG_WIDTH-1:0] tag_wdata; +wire tag_wenable; + +wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata; +wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata; +reg [CACHE_LINE_WIDTH-1:0] data_wdata_r = 128'd0; +wire [CACHE_LINE_WIDTH-1:0] consecutive_write_wdata; +wire [CACHE_LINE_WIDTH-1:0] data_wdata; +wire [CACHE_ADDR_WIDTH-1:0] data_address; +wire [31:0] write_data_word; + +wire idle_hit; +wire read_miss; +wire write_miss; +wire write_hit; +wire consecutive_write; +wire fill_state; + +reg [31:0] miss_address = 32'd0; +wire [CACHE_LINE_WIDTH-1:0] hit_rdata; + +wire read_stall; +wire write_stall; +wire cache_busy_stall; +wire core_stall; +wire write_state; + +wire request_pulse; +wire request_hold; +reg request_r = 1'd0; +wire [CACHE_ADDR_WIDTH-1:0] address; +reg [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = 128'd0; + +wire exclusive_access; +wire ex_read_hit; +reg ex_read_hit_r = 1'd0; +reg [WAYS-1:0] ex_read_hit_way = 4'd0; +reg [CACHE_ADDR_WIDTH-1:0] ex_read_address; +wire ex_read_hit_clear; +wire ex_read_cache_busy; + +reg [31:0] wb_address = 32'd0; +//wire rbuf_hit = 1'd0; +wire wb_hit; +wire [127:0] read_data128; +//genvar i; + + +// ====================================== +// Address to use for cache access +// ====================================== +// If currently stalled then the address for the next +// cycle will be the same as it is in the current cycle +// +assign core_stall = i_fetch_stall || i_exec_stall || o_stall; + +assign address = core_stall ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ; + +// ====================================== +// Outputs +// ====================================== + +assign read_data128 = wb_hit ? i_wb_cached_rdata : hit_rdata; + +assign o_read_data = i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? read_data128 [31:0] : + i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? read_data128 [63:32] : + i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? read_data128 [95:64] : + read_data128 [127:96] ; + +// Don't allow the cache to stall the wb i/f for an exclusive access +// The cache needs a couple of cycles to flush a potential copy of the exclusive +// address, but the wb can do the access in parallel. So there is no +// stall in the state CS_EX_DELETE, even though the cache is out of action. +// This works fine as long as the wb is stalling the core +assign o_stall = request_hold && ( read_stall || write_stall || cache_busy_stall || ex_read_cache_busy ); + +assign o_wb_cached_req = ( (read_miss || write_miss || write_hit) && c_state == CS_IDLE ) || consecutive_write; + + +// ====================================== +// Cache State Machine +// ====================================== + +// Little State Machine to Flush Tag RAMS +always @ ( posedge i_clk ) + if ( i_cache_flush ) + begin + c_state <= CS_INIT; + source_sel <= 4'b1; //1'd1 << C_INIT + init_count <= 9'd0; + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache Flush"); + `endif + end + else + case ( c_state ) + CS_INIT : + if ( init_count < CACHE_LINES ) + begin + init_count <= init_count + 1'd1; + source_sel <= 4'b1; //1'd1 << C_INIT + end + else + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + CS_IDLE : + begin + if ( ex_read_hit || ex_read_hit_r ) + begin + select_way <= data_hit_way | ex_read_hit_way; + c_state <= CS_EX_DELETE; + source_sel <= 4'b1000; //1'd1 << C_INVA + end + else if ( read_miss ) + begin + c_state <= CS_FILL; + source_sel <= 4'b10; //1'd1 << C_CORE + end + else if ( write_hit ) + begin + source_sel <= 4'b10; //1'd1 << C_CORE + if ( i_wb_cached_ready ) + c_state <= CS_WRITE_HIT; + + else + c_state <= CS_WRITE_HIT_WAIT_WB; + end + else if ( write_miss && !i_wb_cached_ready ) + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_WRITE_MISS_WAIT_WB; + end + end + + + CS_FILL : + // third read of burst of 4 + // wb read request asserted, wait for ack + if ( i_wb_cached_ready ) + begin + c_state <= CS_FILL_COMPLETE; + source_sel <= 4'b100; //1'd1 << C_FILL + + // Pick a way to write the cache update into + // Either pick one of the invalid caches, or if all are valid, then pick + // one randomly + + select_way <= next_way; + random_num <= {random_num[2], random_num[1], random_num[0], + random_num[3]^random_num[2]}; + end + + + // Write the read fetch data in this cycle + CS_FILL_COMPLETE : + begin + // Back to normal cache operations, but + // use physical address for first read as + // address moved before the stall was asserted for the read_miss + // However don't use it if its a non-cached address! + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + + // Ignore the tag read data in this cycle + // Wait 1 cycle to pre-read the cache and return to normal operation + CS_TURN_AROUND : + begin + c_state <= CS_IDLE; + end + + + // Flush the entry matching an exclusive access + CS_EX_DELETE: + begin + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache deleted Locked entry"); + `endif + c_state <= CS_TURN_AROUND; + source_sel <= 4'b10; //1'd1 << C_CORE + end + + + CS_WRITE_HIT: + if ( !consecutive_write ) + c_state <= CS_IDLE; + + + CS_WRITE_HIT_WAIT_WB: + // wait for an ack on the wb bus to complete the write + if ( i_wb_cached_ready ) + c_state <= CS_IDLE; + + + CS_WRITE_MISS_WAIT_WB: + // wait for an ack on the wb bus to complete the write + if ( i_wb_cached_ready ) + c_state <= CS_IDLE; + + endcase + + +// ====================================== +// Capture WB Block Read - burst of 4 words +// ====================================== +always @ ( posedge i_clk ) + if ( i_wb_cached_ready ) + wb_rdata_burst <= i_wb_cached_rdata; + + + +// ====================================== +// Miss Address +// ====================================== +always @ ( posedge i_clk ) + if ( o_wb_cached_req || write_hit ) + miss_address <= i_address; + +always @ ( posedge i_clk ) + if ( write_hit ) + begin + data_hit_way_r <= data_hit_way; + end + +always @ ( posedge i_clk ) + if ( write_hit || consecutive_write ) + begin + data_wdata_r <= data_wdata; + end + +assign consecutive_write = miss_address[31:4] == i_address[31:4] && + i_write_enable && + c_state == CS_WRITE_HIT && + request_pulse; + + +always @(posedge i_clk) + if ( o_wb_cached_req ) + wb_address <= i_address; + else if ( i_wb_cached_ready && fill_state ) + wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0}; + +assign fill_state = c_state == CS_FILL ; +assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state; + + +// ====================================== +// Hold Requests +// ====================================== +always @(posedge i_clk) + request_r <= (request_pulse || request_r) && o_stall; + +assign request_hold = request_pulse || request_r; + + +// ====================================== +// Remember Read-Modify-Write Hit +// ====================================== +assign ex_read_hit_clear = c_state == CS_EX_DELETE; + +always @ ( posedge i_clk ) + if ( ex_read_hit_clear ) + begin + ex_read_hit_r <= 1'd0; + ex_read_hit_way <= 4'd0; + end + else if ( ex_read_hit ) + begin + + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display ("Exclusive access cache hit address 0x%08h", i_address); + `endif + + ex_read_hit_r <= 1'd1; + ex_read_hit_way <= data_hit_way; + end + else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r ) + ex_read_hit_way <= select_way; + + +always @ (posedge i_clk) + if ( ex_read_hit ) + ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB]; + + +assign tag_address = source_sel[C_FILL] ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_INVA] ? ex_read_address : + source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] : + source_sel[C_CORE] ? address : + {CACHE_ADDR_WIDTH{1'd0}} ; + + +assign data_address = consecutive_write ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + write_hit ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_CORE] ? address : + {CACHE_ADDR_WIDTH{1'd0}} ; + + +assign tag_wdata = source_sel[C_FILL] ? {1'd1, miss_address[31:12]} : // [31:TAG_ADDR32_LSB] + {TAG_WIDTH{1'd0}} ; + + + // Data comes in off the WB bus in wrap4 with the missed data word first +assign data_wdata = write_hit && c_state == CS_IDLE ? write_hit_wdata : + consecutive_write ? consecutive_write_wdata : + read_miss_wdata ; + +assign read_miss_wdata = wb_rdata_burst; + + +assign write_hit_wdata = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word } : + i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0] } : + i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0] } : + { write_data_word, hit_rdata[95:0] } ; +wire [31:0] con_read_data_word; +wire [31:0] con_write_data_word; + +assign consecutive_write_wdata = + i_address[3:2] == 2'd0 ? {data_wdata_r[127:32], con_write_data_word } : + i_address[3:2] == 2'd1 ? {data_wdata_r[127:64], con_write_data_word, data_wdata_r[31:0] } : + i_address[3:2] == 2'd2 ? {data_wdata_r[127:96], con_write_data_word, data_wdata_r[63:0] } : + { con_write_data_word, data_wdata_r[95:0] } ; +assign con_read_data_word = + i_address[3:2] == 2'd0 ? data_wdata_r[ 31: 0] : + i_address[3:2] == 2'd1 ? data_wdata_r[ 63: 32] : + i_address[3:2] == 2'd2 ? data_wdata_r[ 95: 64] : + data_wdata_r[127: 96] ; + + +assign con_write_data_word = + i_byte_enable == 4'b0001 ? { con_read_data_word[31: 8], i_write_data[ 7: 0] } : + i_byte_enable == 4'b0010 ? { con_read_data_word[31:16], i_write_data[15: 8], con_read_data_word[ 7:0]} : + i_byte_enable == 4'b0100 ? { con_read_data_word[31:24], i_write_data[23:16], con_read_data_word[15:0]} : + i_byte_enable == 4'b1000 ? { i_write_data[31:24], con_read_data_word[23:0]} : + i_byte_enable == 4'b0011 ? { con_read_data_word[31:16], i_write_data[15: 0] } : + i_byte_enable == 4'b1100 ? { i_write_data[31:16], con_read_data_word[15:0]} : + i_write_data ; + + + + +// Use Byte Enables +assign write_data_word = i_byte_enable == 4'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0] } : + i_byte_enable == 4'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} : + i_byte_enable == 4'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} : + i_byte_enable == 4'b1000 ? { i_write_data[31:24], o_read_data[23:0]} : + i_byte_enable == 4'b0011 ? { o_read_data[31:16], i_write_data[15: 0] } : + i_byte_enable == 4'b1100 ? { i_write_data[31:16], o_read_data[15:0]} : + i_write_data ; + + +assign tag_wenable = source_sel[C_INVA] ? 1'd1 : + source_sel[C_FILL] ? 1'd1 : + source_sel[C_INIT] ? 1'd1 : + source_sel[C_CORE] ? 1'd0 : + 1'd0 ; + + +assign request_pulse = i_request && i_cache_enable; + +assign exclusive_access = i_exclusive && i_cache_enable; + + +//always@(posedge i_clk) +// idle_hit <= |data_hit_way; + +assign idle_hit = |data_hit_way; + +assign write_hit = request_hold && i_write_enable && idle_hit; + +assign write_miss = request_hold && i_write_enable && !idle_hit && !consecutive_write; + +assign read_miss = request_hold && !idle_hit && !i_write_enable; + + // Exclusive read idle_hit +assign ex_read_hit = exclusive_access && !i_write_enable && idle_hit; + + // Added to fix rare swap bug which occurs when the cache starts + // a fill just as the swap instruction starts to execute. The cache + // fails to check for a read idle_hit on the swap read cycle. + // This signal stalls the core in that case until after the + // fill has completed. +assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE; + + // Need to stall for a write miss to wait for the current wb + // read miss access to complete. Also for a write idle_hit, need + // to stall for 1 cycle while the data cache is being written to +assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT || + c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB; + +assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready); + +//assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable; + +assign read_stall = request_hold && !idle_hit && !wb_hit && !i_write_enable; + +assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT || +// (fill_state && !rbuf_hit && !wb_hit) || + (fill_state && !wb_hit) || + (c_state == CS_WRITE_HIT && !consecutive_write); + + +// ====================================== +// Instantiate RAMS +// ====================================== + +//generate +// for ( i=0; i 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 3 ) begin : check_hit_3ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 4 ) begin : check_hit_4ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + + data_hit_way[2] + data_hit_way[3] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 8 ) begin : check_hit_8ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + + data_hit_way[2] + data_hit_way[3] + + data_hit_way[4] + data_hit_way[5] + + data_hit_way[6] + data_hit_way[7] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else begin : check_hit_nways + + initial + begin + ` + $display("Unsupported number of ways %0d", WAYS); + $display("Set A25_DCACHE_WAYS in a25_config_defines.v to either 2,3,4 or 8"); + end + +end +endgenerate +*/ + +//synopsys translate_on + +endmodule + + + +module a25_mem( + i_clk, + i_fetch_stall, + i_exec_stall, + o_mem_stall, + + i_daddress, + i_daddress_valid, + i_daddress_nxt, + i_write_data, + i_write_enable, + i_exclusive, + i_byte_enable, + i_exec_load_rd, + i_cache_enable, + i_cache_flush, + i_cacheable_area, + + o_mem_read_data, + o_mem_read_data_valid, + o_mem_load_rd, + + o_wb_cached_req, + o_wb_uncached_req, + o_wb_write, + o_wb_byte_enable, + o_wb_write_data, + o_wb_address, + i_wb_uncached_rdata, + i_wb_cached_rdata, + i_wb_cached_ready, + i_wb_uncached_ready + ); + + + +input i_clk; +input i_fetch_stall; // Fetch stage asserting stall +input i_exec_stall; // Execute stage asserting stall +output o_mem_stall; // Mem stage asserting stall + +input [31:0] i_daddress; +input i_daddress_valid; +input [31:0] i_daddress_nxt; // un-registered version of address to the cache rams +input [31:0] i_write_data; +input i_write_enable; +input i_exclusive; // high for read part of swap access +input [3:0] i_byte_enable; +input [8:0] i_exec_load_rd; // The destination register for a load instruction +input i_cache_enable; // cache enable +input i_cache_flush; // cache flush +input [31:0] i_cacheable_area; // each bit corresponds to 2MB address space + +output [31:0] o_mem_read_data; +output o_mem_read_data_valid; +output [10:0] o_mem_load_rd; // The destination register for a load instruction + +// Wishbone accesses +output o_wb_cached_req; // Cached Request +output o_wb_uncached_req; // Unached Request +output o_wb_write; // Read=0, Write=1 +output [15:0] o_wb_byte_enable; // byte eable +output [127:0] o_wb_write_data; +output [31:0] o_wb_address; // wb bus +input [127:0] i_wb_uncached_rdata; // wb bus +input [127:0] i_wb_cached_rdata; // wb bus +input i_wb_cached_ready; // wishbone access complete and read data valid +input i_wb_uncached_ready; // wishbone access complete and read data valid + +wire [31:0] cache_read_data; +wire address_cachable; +wire sel_cache_p; +wire sel_cache; +wire cached_wb_req; +wire uncached_data_access; +wire uncached_data_access_p; +wire cache_stall; +wire uncached_wb_wait; +reg uncached_wb_req_r = 1'd0; +reg uncached_wb_stop_r = 1'd0; +reg cached_wb_stop_r = 1'd0; +wire daddress_valid_p; // pulse +reg [31:0] mem_read_data_r = 32'd0; +reg mem_read_data_valid_r = 1'd0; +reg [10:0] mem_load_rd_r = 11'd0; +wire [10:0] mem_load_rd_c; +wire [31:0] mem_read_data_c; +wire mem_read_data_valid_c; +reg mem_stall_r = 1'd0; +wire use_mem_reg; +reg fetch_only_stall_r = 1'd0; +wire fetch_only_stall; +wire void_output; +wire wb_stop; +reg daddress_valid_stop_r = 1'd0; +wire [31:0] wb_rdata32; + +// ====================================== +// Memory Decode +// ====================================== + +//assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]]; +//in_cachable_mem = in_loboot_mem ( address ) || in_main_mem ( address ) ; + + +// e.g. 24 for 32MBytes, 26 for 128MBytes +localparam MAIN_MSB = 26; + +// e.g. 13 for 4k words +localparam BOOT_MSB = 13; + +localparam MAIN_BASE = 32'h00000000; /* Main Memory */ +localparam BOOT_BASE = 32'h00000000; /* Cachable Boot Memory */ +localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */ +localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */ +localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */ +localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */ +localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */ +localparam HIBOOT_BASE = 32'h28000000; /* Uncachable Boot Memory */ +localparam TEST_BASE = 16'hf000; /* Test Module */ + + + +//function in_loboot_mem; +// input [31:0] address; +//begin +//in_loboot_mem = (address >= BOOT_BASE && +// address < (BOOT_BASE + 2**(BOOT_MSB+1)-1)); +//end +//endfunction + + +//function in_hiboot_mem; +// input [31:0] address; +//begin +//in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]); +// = (address[31:14] == HIBOOT_BASE>>(BOOT_MSB+1)); fixed + +//end +//endfunction + + +//function in_boot_mem; +// input [31:0] address; +//begin +//in_boot_mem = in_loboot_mem(address) || in_hiboot_mem(address); +//end +//endfunction + + +//function in_main_mem; +// input [31:0] address; +//begin +//in_main_mem = (address >= MAIN_BASE && +// address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) && +// !in_boot_mem ( address ); +//end +//endfunction + + +// UART 0 address space +//function in_uart0; +// input [31:0] address; +//begin +// in_uart0 = address [31:16] == AMBER_UART0_BASE; +//end +//endfunction + + +// UART 1 address space +//function in_uart1; +// input [31:0] address; +//begin +// in_uart1 = address [31:16] == AMBER_UART1_BASE; +//end +//endfunction + + +// Interrupt Controller address space +//function in_ic; +// input [31:0] address; +//begin +// in_ic = address [31:16] == AMBER_IC_BASE; +//end +//endfunction + + +// Timer Module address space +//function in_tm; +// input [31:0] address; +//begin +// in_tm = address [31:16] == AMBER_TM_BASE; +//end +//endfunction + + +// Test module +//function in_test; +// input [31:0] address; +//begin +// in_test = address [31:16] == TEST_BASE; +//end +//endfunction + + +// Ethernet MAC +//function in_ethmac; +// input [31:0] address; +//begin +// in_ethmac = address [31:16] == ETHMAC_BASE; +//end +//endfunction + + +// Used in fetch.v and l2cache.v to allow accesses to these addresses +// to be cached +//function in_cachable_mem; +// input [31:0] address; +//begin +// in_cachable_mem = in_loboot_mem ( address ) || +// in_main_mem ( address ) ; +//end +//endfunction + + + +assign address_cachable = ( + (i_daddress >= BOOT_BASE && i_daddress < (BOOT_BASE + 32'h7fff)) // in_loboot_mem ( address ) + || ( + (i_daddress >= MAIN_BASE && i_daddress < (MAIN_BASE + 32'hfffffff)) + && !( (i_daddress >= BOOT_BASE && i_daddress < (BOOT_BASE + 32'h7fff)) + ||(i_daddress[31:14] == HIBOOT_BASE>>(14))) + ) + ) + && ((i_daddress[25:21] == 5'b00000) ? i_cacheable_area[0] : + (i_daddress[25:21] == 5'b00001) ? i_cacheable_area[1] : + (i_daddress[25:21] == 5'b00010) ? i_cacheable_area[2] : + (i_daddress[25:21] == 5'b00011) ? i_cacheable_area[3] : + (i_daddress[25:21] == 5'b00100) ? i_cacheable_area[4] : + (i_daddress[25:21] == 5'b00101) ? i_cacheable_area[5] : + (i_daddress[25:21] == 5'b00110) ? i_cacheable_area[6] : + (i_daddress[25:21] == 5'b00111) ? i_cacheable_area[7] : + (i_daddress[25:21] == 5'b01000) ? i_cacheable_area[8] : + (i_daddress[25:21] == 5'b01001) ? i_cacheable_area[9] : + (i_daddress[25:21] == 5'b01010) ? i_cacheable_area[10] : + (i_daddress[25:21] == 5'b01011) ? i_cacheable_area[11] : + (i_daddress[25:21] == 5'b01100) ? i_cacheable_area[12] : + (i_daddress[25:21] == 5'b01101) ? i_cacheable_area[13] : + (i_daddress[25:21] == 5'b01110) ? i_cacheable_area[14] : + (i_daddress[25:21] == 5'b01111) ? i_cacheable_area[15] : + (i_daddress[25:21] == 5'b10000) ? i_cacheable_area[16] : + (i_daddress[25:21] == 5'b10001) ? i_cacheable_area[17] : + (i_daddress[25:21] == 5'b10010) ? i_cacheable_area[18] : + (i_daddress[25:21] == 5'b10011) ? i_cacheable_area[19] : + (i_daddress[25:21] == 5'b10100) ? i_cacheable_area[20] : + (i_daddress[25:21] == 5'b10101) ? i_cacheable_area[21] : + (i_daddress[25:21] == 5'b10110) ? i_cacheable_area[22] : + (i_daddress[25:21] == 5'b10111) ? i_cacheable_area[23] : + (i_daddress[25:21] == 5'b11000) ? i_cacheable_area[24] : + (i_daddress[25:21] == 5'b11001) ? i_cacheable_area[25] : + (i_daddress[25:21] == 5'b11010) ? i_cacheable_area[26] : + (i_daddress[25:21] == 5'b11011) ? i_cacheable_area[27] : + (i_daddress[25:21] == 5'b11100) ? i_cacheable_area[28] : + (i_daddress[25:21] == 5'b11101) ? i_cacheable_area[29] : + (i_daddress[25:21] == 5'b11110) ? i_cacheable_area[30] : + i_cacheable_area[31] ); + +//i_cacheable_area[i_daddress[25:21]]; +assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive; +assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive; +assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall; +assign uncached_data_access_p = daddress_valid_p && !sel_cache; + +assign use_mem_reg = wb_stop && !mem_stall_r; +assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c; +assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c; +assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c); + + +// Return read data either from the wishbone bus or the cache +assign wb_rdata32 = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] : + i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] : + i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] : + i_wb_uncached_rdata[127:96] ; + +assign mem_read_data_c = sel_cache ? cache_read_data : + uncached_data_access ? wb_rdata32 : + 32'h76543210 ; + +assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd}; +assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall; + +assign o_mem_stall = uncached_wb_wait || cache_stall; + +// Request wishbone access +assign o_wb_byte_enable = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable } : + i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable, 4'd0} : + i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable, 8'd0} : + { i_byte_enable, 12'd0} ; + +assign o_wb_write = i_write_enable; +assign o_wb_address = {i_daddress[31:2], 2'd0}; +assign o_wb_write_data = {4{i_write_data}}; +assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req; +assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p; + +assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready; + +always @( posedge i_clk ) + begin + uncached_wb_req_r <= (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready; + end + +assign fetch_only_stall = i_fetch_stall && !o_mem_stall; + +always @( posedge i_clk ) + fetch_only_stall_r <= fetch_only_stall; + +assign void_output = (fetch_only_stall_r && fetch_only_stall) || (fetch_only_stall_r && mem_read_data_valid_r); + + +// pulse this signal +assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r; + +always @( posedge i_clk ) + begin + uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall); + cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall); + daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall); + // hold this until the mem access completes + mem_stall_r <= o_mem_stall; + end + + +assign wb_stop = uncached_wb_stop_r || cached_wb_stop_r; + +always @( posedge i_clk ) + if ( !wb_stop || o_mem_stall ) + begin + mem_read_data_r <= mem_read_data_c; + mem_load_rd_r <= mem_load_rd_c; + mem_read_data_valid_r <= mem_read_data_valid_c; + end + + +// ====================================== +// L1 Data Cache +// ====================================== +a25_dcache u_dcache ( + .i_clk ( i_clk ), + .i_request ( sel_cache_p ), + .i_exclusive ( i_exclusive ), + .i_write_data ( i_write_data ), + .i_write_enable ( i_write_enable ), + .i_address ( i_daddress ), + .i_address_nxt ( i_daddress_nxt ), + .i_byte_enable ( i_byte_enable ), + .i_cache_enable ( i_cache_enable ), + .i_cache_flush ( i_cache_flush ), + .i_fetch_stall ( i_fetch_stall ), + .i_exec_stall ( i_exec_stall ), + .i_wb_cached_rdata ( i_wb_cached_rdata ), + .i_wb_cached_ready ( i_wb_cached_ready ), + + .o_read_data ( cache_read_data ), + .o_stall ( cache_stall ), + .o_wb_cached_req ( cached_wb_req ) + +); + + + +endmodule + + + + +module a25_write_back( + i_clk, + i_mem_stall, + + i_mem_read_data, + i_mem_read_data_valid, + i_mem_load_rd, + + o_wb_read_data, + o_wb_read_data_valid, + o_wb_load_rd, + + i_daddress, +// i_daddress_valid + ); + +input i_clk; +input i_mem_stall; // Mem stage asserting stall + +input [31:0] i_mem_read_data; // data reads +input i_mem_read_data_valid; // read data is valid +input [10:0] i_mem_load_rd; // Rd for data reads + +output [31:0] o_wb_read_data; // data reads +output o_wb_read_data_valid; // read data is valid +output [10:0] o_wb_load_rd; // Rd for data reads + +input [31:0] i_daddress; +//input i_daddress_valid; + +reg [31:0] mem_read_data_r = 32'd0; // Register read data from Data Cache +reg mem_read_data_valid_r = 1'd0; // Register read data from Data Cache +reg [10:0] mem_load_rd_r = 11'd0; // Register the Rd value for loads + +assign o_wb_read_data = mem_read_data_r; +assign o_wb_read_data_valid = mem_read_data_valid_r; +assign o_wb_load_rd = mem_load_rd_r; + + +always @( posedge i_clk ) + if ( !i_mem_stall ) + begin + mem_read_data_r <= i_mem_read_data; + mem_read_data_valid_r <= i_mem_read_data_valid; + mem_load_rd_r <= i_mem_load_rd; + end + + +// Used by a25_decompile.v, so simulation only +//synopsys translate_off +reg [31:0] daddress_r = 32'd0; // Register read data from Data Cache +always @( posedge i_clk ) + if ( !i_mem_stall ) + daddress_r <= i_daddress; +//synopsys translate_on + +endmodule + + + + module a25_wishbone_buf ( + i_clk, + +// Core side + i_req, + i_write, + i_wdata, + i_be, + i_addr, + o_rdata, + o_ack, + +// Wishbone side + o_valid, + i_accepted, + o_write, + o_wdata, + o_be, + o_addr, + i_rdata, + i_rdata_valid + ); + +input i_clk; + +// Core side +input i_req; +input i_write; +input [127:0] i_wdata; +input [15:0] i_be; +input [31:0] i_addr; +output [127:0] o_rdata; +output o_ack; + +// Wishbone side +output o_valid; +input i_accepted; +output o_write; +output [127:0] o_wdata; +output [15:0] o_be; +output [31:0] o_addr; +input [127:0] i_rdata; +input i_rdata_valid; + +// ---------------------------------------------------- +// Signals +// ---------------------------------------------------- +reg [1:0] wbuf_used_r = 2'd0; +//reg [31:0] wbuf_addr_r [1:0]; +reg [31:0] wbuf_addr_r0; +reg [31:0] wbuf_addr_r1; +//reg [127:0] wbuf_wdata_r [1:0]; +reg [127:0] wbuf_wdata_r0; +reg [127:0] wbuf_wdata_r1; +//reg [15:0] wbuf_be_r [1:0]; +reg [15:0] wbuf_be_r0; +reg [15:0] wbuf_be_r1; +reg [1:0] wbuf_write_r = 2'd0; +reg wbuf_wp_r = 1'd0; // write buf write pointer +reg wbuf_rp_r = 1'd0; // write buf read pointer +reg busy_reading_r = 1'd0; +reg wait_rdata_valid_r = 1'd0; +wire in_wreq; +reg ack_owed_r = 1'd0; +reg push; //wire to reg +reg pop; //wire to reg + +// ---------------------------------------------------- +// Access Buffer +// ---------------------------------------------------- +assign in_wreq = i_req && i_write; +assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted)); +assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0; + +always @(posedge i_clk) + if (push && pop) + wbuf_used_r <= wbuf_used_r; + else if (push) + wbuf_used_r <= wbuf_used_r + 1'd1; + else if (pop) + wbuf_used_r <= wbuf_used_r - 1'd1; + +always @(posedge i_clk) + if (push && in_wreq && !o_ack) + ack_owed_r <= 1'd1; + else if (!i_req && o_ack) + ack_owed_r <= 1'd0; + +always @(posedge i_clk) + if (push) + begin + if ( wbuf_wp_r == 1'd0) + begin + wbuf_wdata_r0 <= i_wdata; + wbuf_addr_r0 <= i_addr; + wbuf_be_r0 <= i_write ? i_be : 16'hffff; + wbuf_write_r [0] <= i_write; + end + + + else if ( wbuf_wp_r == 1'd1) + begin + wbuf_wdata_r1 <= i_wdata; + wbuf_addr_r1 <= i_addr; + wbuf_be_r1 <= i_write ? i_be : 16'hffff; + wbuf_write_r [1] <= i_write; + end + + wbuf_wp_r <= !wbuf_wp_r; + end + +always @(posedge i_clk) + if (pop) + wbuf_rp_r <= !wbuf_rp_r; + + +// ---------------------------------------------------- +// Output logic +// ---------------------------------------------------- +//assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata; +assign o_wdata = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_wdata_r0 : wbuf_wdata_r1 ) : i_wdata; + +//assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write; +assign o_write = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_write_r[0] : wbuf_write_r[1]) : i_write; + +//assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr; +assign o_addr = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_addr_r0 : wbuf_addr_r1 ) : i_addr; + +//assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff; +assign o_be = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_be_r0 : wbuf_be_r1) : i_write ? i_be : 16'hffff; + +assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop); + +assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r; + +assign o_rdata = i_rdata; + + +always@(posedge i_clk) + if (o_valid && !o_write) + busy_reading_r <= 1'd1; + else if (i_rdata_valid) + busy_reading_r <= 1'd0; + +always@(posedge i_clk) + if (o_valid && !o_write && i_accepted) + wait_rdata_valid_r <= 1'd1; + else if (i_rdata_valid) + wait_rdata_valid_r <= 1'd0; +endmodule + + + +module a25_wishbone( + i_clk, + + i_port0_req, + o_port0_ack, + i_port0_write, + i_port0_wdata, + i_port0_be, + i_port0_addr, + o_port0_rdata, + + i_port1_req, + o_port1_ack, + i_port1_write, + i_port1_wdata, + i_port1_be, + i_port1_addr, + o_port1_rdata, + + i_port2_req, + o_port2_ack, + i_port2_write, + i_port2_wdata, + i_port2_be, + i_port2_addr, + o_port2_rdata, + + + o_wb_adr, + o_wb_sel, + o_wb_we, + o_wb_dat, + o_wb_cyc, + o_wb_stb, + i_wb_dat, + i_wb_ack +// i_wb_err + ); + + +// ---------------------------------------------------- +// Parameters +// ---------------------------------------------------- +localparam WBUF = 3; + +input i_clk; + + +// Port 0 - dcache uncached +input i_port0_req; +output o_port0_ack; +input i_port0_write; +input [127:0] i_port0_wdata; +input [15:0] i_port0_be; +input [31:0] i_port0_addr; +output [127:0] o_port0_rdata; + +// Port 1 - dcache cached +input i_port1_req; +output o_port1_ack; +input i_port1_write; +input [127:0] i_port1_wdata; +input [15:0] i_port1_be; +input [31:0] i_port1_addr; +output [127:0] o_port1_rdata; + +// Port 2 - instruction cache accesses, read only +input i_port2_req; +output o_port2_ack; +input i_port2_write; +input [127:0] i_port2_wdata; +input [15:0] i_port2_be; +input [31:0] i_port2_addr; +output [127:0] o_port2_rdata; + + +// 128-bit Wishbone Bus +output [31:0] o_wb_adr; +output [15:0] o_wb_sel; +output o_wb_we; +output [127:0] o_wb_dat; +output o_wb_cyc; +output o_wb_stb; +input [127:0] i_wb_dat; +input i_wb_ack; +//input i_wb_err; + +// ---------------------------------------------------- +// Signals +// ---------------------------------------------------- + +reg o_wb_adr = 32'd0; +reg o_wb_sel = 16'd0; +reg o_wb_we = 1'd0; +reg o_wb_dat = 128'd0; +reg o_wb_cyc = 1'd0; +reg o_wb_stb = 1'd0; +wire [WBUF-1:0] wbuf_valid; +wire [WBUF-1:0] wbuf_accepted; +wire [WBUF-1:0] wbuf_write; +//wire [127:0] wbuf_wdata [WBUF-1:0]; +//wire [15:0] wbuf_be [WBUF-1:0]; +//wire [31:0] wbuf_addr [WBUF-1:0]; +wire [127:0] wbuf_wdata0; +wire [127:0] wbuf_wdata1; +wire [127:0] wbuf_wdata2; +wire [15:0] wbuf_be0; +wire [15:0] wbuf_be1; +wire [15:0] wbuf_be2; +wire [31:0] wbuf_addr0; +wire [31:0] wbuf_addr1; +wire [31:0] wbuf_addr2; +wire [WBUF-1:0] wbuf_rdata_valid; +wire new_access; +reg [WBUF-1:0] serving_port = 3'd0; + + +// ---------------------------------------------------- +// Instantiate the write buffers +// ---------------------------------------------------- + +a25_wishbone_buf u_wishbone_buf_p0 ( + .i_clk ( i_clk ), + + .i_req ( i_port0_req ), + .i_write ( i_port0_write ), + .i_wdata ( i_port0_wdata ), + .i_be ( i_port0_be ), + .i_addr ( i_port0_addr ), + .o_rdata ( o_port0_rdata ), + .o_ack ( o_port0_ack ), + + .o_valid ( wbuf_valid [0] ), + .i_accepted ( wbuf_accepted [0] ), + .o_write ( wbuf_write [0] ), + .o_wdata ( wbuf_wdata0 ), + .o_be ( wbuf_be0 ), + .o_addr ( wbuf_addr0 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [0] ) + ); + + +a25_wishbone_buf u_wishbone_buf_p1 ( + .i_clk ( i_clk ), + + .i_req ( i_port1_req ), + .i_write ( i_port1_write ), + .i_wdata ( i_port1_wdata ), + .i_be ( i_port1_be ), + .i_addr ( i_port1_addr ), + .o_rdata ( o_port1_rdata ), + .o_ack ( o_port1_ack ), + + .o_valid ( wbuf_valid [1] ), + .i_accepted ( wbuf_accepted [1] ), + .o_write ( wbuf_write [1] ), + .o_wdata ( wbuf_wdata1 ), + .o_be ( wbuf_be1 ), + .o_addr ( wbuf_addr1 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [1] ) + ); + + +a25_wishbone_buf u_wishbone_buf_p2 ( + .i_clk ( i_clk ), + + .i_req ( i_port2_req ), + .i_write ( i_port2_write ), + .i_wdata ( i_port2_wdata ), + .i_be ( i_port2_be ), + .i_addr ( i_port2_addr ), + .o_rdata ( o_port2_rdata ), + .o_ack ( o_port2_ack ), + + .o_valid ( wbuf_valid [2] ), + .i_accepted ( wbuf_accepted [2] ), + .o_write ( wbuf_write [2] ), + .o_wdata ( wbuf_wdata2 ), + .o_be ( wbuf_be2 ), + .o_addr ( wbuf_addr2 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [2] ) + ); + + +assign new_access = !o_wb_stb || i_wb_ack; + +assign wbuf_accepted[0] = new_access && wbuf_valid[0]; +assign wbuf_accepted[1] = new_access && !wbuf_valid[0] && wbuf_valid[1]; +assign wbuf_accepted[2] = new_access && !wbuf_valid[0] && !wbuf_valid[1] && wbuf_valid[2]; + +//always @(posedge i_clk) +// begin + +// wbuf_accepted[0] <= new_access && wbuf_valid[0]; + +// wbuf_accepted[1] <= new_access && !wbuf_valid[0] && wbuf_valid[1]; + +// wbuf_accepted[2] <= new_access && !wbuf_valid[0] && !wbuf_valid[1] && wbuf_valid[2]; + +// end + + +always @(posedge i_clk) + begin + if (new_access) + begin + if (wbuf_valid[0]) + begin + o_wb_adr <= wbuf_addr0; + o_wb_sel <= wbuf_be0; + o_wb_we <= wbuf_write[0]; + o_wb_dat <= wbuf_wdata0; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b001; + end + else if (wbuf_valid[1]) + begin + // o_wb_adr <= wbuf_addr [1]; + // o_wb_sel <= wbuf_be [1]; + // o_wb_we <= wbuf_write[1]; + // o_wb_dat <= wbuf_wdata[1]; + o_wb_adr <= wbuf_addr1; + o_wb_sel <= wbuf_be1; + o_wb_we <= wbuf_write[1]; + o_wb_dat <= wbuf_wdata1; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b010; + end + else if (wbuf_valid[2]) + begin + // o_wb_adr <= wbuf_addr [2]; + // o_wb_sel <= wbuf_be [2]; + // o_wb_we <= wbuf_write[2]; + // o_wb_dat <= wbuf_wdata[2]; + o_wb_adr <= wbuf_addr2; + o_wb_sel <= wbuf_be2; + o_wb_we <= wbuf_write[2]; + o_wb_dat <= wbuf_wdata2; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b100; + end + else + begin + o_wb_cyc <= 1'd0; + o_wb_stb <= 1'd0; + + // Don't need to change these values because they are ignored + // when stb is low, but it makes for a cleaner waveform, at the expense of a few gates + o_wb_we <= 1'd0; + o_wb_adr <= 32'd0; + o_wb_dat <= 128'd0; + + serving_port <= 3'b000; + end + end + end + + +assign {wbuf_rdata_valid[2], wbuf_rdata_valid[1], wbuf_rdata_valid[0]} = {3{i_wb_ack & ~ o_wb_we}} & serving_port; + + +endmodule + + + + + + +module a25_coprocessor( + i_clk, + i_core_stall, +// i_copro_opcode1, +// i_copro_opcode2, + i_copro_crn, +// i_copro_crm, +// i_copro_num, + i_copro_operation, + i_copro_write_data, + i_fault, + i_fault_status, + i_fault_address, + o_copro_read_data, + o_cache_enable, + o_cache_flush, + o_cacheable_area + ); + +/************************* IO Declarations *********************/ +input i_clk; +input i_core_stall; // stall all stages of the Amber core at the same time +//input [2:0] i_copro_opcode1; +//input [2:0] i_copro_opcode2; +input [3:0] i_copro_crn; // Register Number +//input [3:0] i_copro_crm; +//input [3:0] i_copro_num; +input [1:0] i_copro_operation; +input [31:0] i_copro_write_data; + +input i_fault; // high to latch the fault address and status +input [7:0] i_fault_status; +input [31:0] i_fault_address; // the address that caused the fault + +output [31:0] o_copro_read_data; +output o_cache_enable; +output o_cache_flush; +output [31:0] o_cacheable_area; + +/*********************** Signal Declarations *******************/ +reg [31:0] o_copro_read_data; +// Bit 0 - Cache on(1)/off +// Bit 1 - Shared (1) or seperate User/Supervisor address space +// Bit 2 - address monitor mode(1) +reg [2:0] cache_control = 3'b000; + +// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable +// Bit 1 - next 2MB region etc. +reg [31:0] cacheable_area = 32'h0; + +// Marks memory regions as read only so writes are ignored by the cache +// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable +// Bit 1 - next 2MB region etc. +reg [31:0] updateable_area = 32'h0; + +// Accesses to a region with a flag set in this register cause the +// cache to flush +// Bit 0 - 2MB memory from 0 to 0x01fffff +// Bit 1 - next 2MB region etc. +reg [31:0] disruptive_area = 32'h0; + + +reg [7:0] fault_status = 8'd0; +reg [31:0] fault_address = 32'b0; // the address that caused the fault + +wire copro15_reg1_write; + + +// --------------------------- +// Outputs +// --------------------------- +assign o_cache_enable = cache_control[0]; +assign o_cache_flush = copro15_reg1_write; +assign o_cacheable_area = cacheable_area; + +// --------------------------- +// Capture an access fault address and status +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if ( i_fault ) + begin + + fault_status <= i_fault_status; + fault_address <= i_fault_address; + end + end + + +// --------------------------- +// Register Writes +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if ( i_copro_operation == 2'd2 ) + case ( i_copro_crn ) + 4'd2: cache_control <= i_copro_write_data[2:0]; + 4'd3: cacheable_area <= i_copro_write_data[31:0]; + 4'd4: updateable_area <= i_copro_write_data[31:0]; + 4'd5: disruptive_area <= i_copro_write_data[31:0]; + default: cache_control <=cache_control; + endcase + end + +// Flush the cache +assign copro15_reg1_write = !i_core_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1; + + +// --------------------------- +// Register Reads +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + case ( i_copro_crn ) + // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision + 4'd0: o_copro_read_data <= 32'h41560300; + 4'd2: o_copro_read_data <= {29'd0, cache_control}; + 4'd3: o_copro_read_data <= cacheable_area; + 4'd4: o_copro_read_data <= updateable_area; + 4'd5: o_copro_read_data <= disruptive_area; + 4'd6: o_copro_read_data <= {24'd0, fault_status }; + 4'd7: o_copro_read_data <= fault_address; + default: o_copro_read_data <= 32'd0; + endcase + + +endmodule + + + + + + module arm_core( + i_clk, + i_irq, + i_firq, + i_system_rdy, + i_wb_dat, + i_wb_ack, + i_wb_err, + + +//decode + +//coprocessor +// cache_enable, // Enabel the cache +// cache_flush, // Flush the cache +// cacheable_area, +//execute + +//wishbone + + +//write_back + + + + o_wb_adr, + o_wb_sel, + o_wb_we, + o_wb_dat, + o_wb_cyc, + o_wb_stb + ); + +input i_clk; + +input i_irq; // Interrupt request, active high +input i_firq; // Fast Interrupt request, active high + +input i_system_rdy; // Amber is stalled when this is low + +// Wishbone Master I/F +output [31:0] o_wb_adr; +output [15:0] o_wb_sel; +output o_wb_we; +input [127:0] i_wb_dat; +output [127:0] o_wb_dat; +output o_wb_cyc; +output o_wb_stb; +input i_wb_ack; //Used to terminate read and write accesses +input i_wb_err; + + +//decode + + +//coprocessor + +//input cache_enable; // Enabel the cache +//input cache_flush; // Flush the cache +//input [31:0] cacheable_area; + +//execute + + +//wishbone + + +//write_back + + + +wire [31:0] execute_iaddress; +wire execute_iaddress_valid; +wire [31:0] execute_iaddress_nxt; // un-registered version of execute_address + // to the instruction cache rams +wire [31:0] execute_daddress; +wire execute_daddress_valid; +wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress + // to the data cache rams +wire [31:0] write_data; +wire write_enable; +wire [31:0] fetch_instruction; +wire decode_exclusive; +wire decode_iaccess; +wire decode_daccess; +wire [3:0] byte_enable; +wire exclusive; // swap access +wire cache_enable; // Enabel the cache +wire cache_flush; // Flush the cache +wire [31:0] cacheable_area; + +wire fetch_stall; +wire mem_stall; +wire exec_stall; +wire core_stall; + +wire [1:0] status_bits_mode; +wire status_bits_irq_mask; +wire status_bits_firq_mask; +wire status_bits_flags_wen; +wire status_bits_mode_wen; +wire status_bits_irq_mask_wen; +wire status_bits_firq_mask_wen; +wire [31:0] execute_status_bits; + +wire [31:0] imm32; +wire [4:0] imm_shift_amount; +wire shift_imm_zero; +wire [3:0] condition; + +wire [3:0] rm_sel; +wire [3:0] rs_sel; +wire [7:0] decode_load_rd; +wire [8:0] exec_load_rd; +wire [3:0] rn_sel; +wire [1:0] barrel_shift_amount_sel; +wire [1:0] barrel_shift_data_sel; +wire [1:0] barrel_shift_function; +wire [8:0] alu_function; +wire [1:0] multiply_function; +wire [2:0] interrupt_vector_sel; +wire [3:0] iaddress_sel; +wire [3:0] daddress_sel; +wire [2:0] pc_sel; +wire [1:0] byte_enable_sel; +wire [2:0] status_bits_sel; +wire [2:0] reg_write_sel; +wire user_mode_regs_store_nxt; +wire firq_not_user_mode; + +wire write_data_wen; +wire copro_write_data_wen; +wire base_address_wen; +wire pc_wen; +wire [14:0] reg_bank_wen; + +wire [2:0] copro_opcode1; +wire [2:0] copro_opcode2; +wire [3:0] copro_crn; +wire [3:0] copro_crm; +wire [3:0] copro_num; +wire [1:0] copro_operation; +wire [31:0] copro_read_data; +wire [31:0] copro_write_data; +wire multiply_done; + +wire decode_fault; +wire iabt_trigger; +wire dabt_trigger; + +wire [7:0] decode_fault_status; +wire [7:0] iabt_fault_status; +wire [7:0] dabt_fault_status; + +wire [31:0] decode_fault_address; +wire [31:0] iabt_fault_address; +wire [31:0] dabt_fault_address; + +wire adex; + +wire [31:0] mem_read_data; +wire mem_read_data_valid; +wire [10:0] mem_load_rd; + +wire [31:0] wb_read_data; +wire wb_read_data_valid; +wire [10:0] wb_load_rd; + +wire dcache_wb_cached_req; +wire dcache_wb_uncached_req; +wire dcache_wb_write; +wire [15:0] dcache_wb_byte_enable; +wire [31:0] dcache_wb_address; +wire [127:0] dcache_wb_cached_rdata; +wire [127:0] dcache_wb_write_data; +wire dcache_wb_cached_ready; +wire dcache_wb_uncached_ready; +wire [31:0] icache_wb_address; +wire icache_wb_req; +wire [31:0] icache_wb_adr; +wire [127:0] icache_wb_read_data; +wire icache_wb_ready; + +wire conflict; +wire rn_use_read; +wire rm_use_read; +wire rs_use_read; +wire rd_use_read; +//jing+ +wire priviledged; +wire [127:0] port0_rdata; + +// data abort has priority +assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status; +assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address; +assign decode_fault = dabt_trigger | iabt_trigger; + +assign core_stall = fetch_stall || mem_stall || exec_stall; + + +// ====================================== +// Fetch Stage +// ====================================== +a25_fetch u_fetch ( + .i_clk ( i_clk ), + .i_mem_stall ( mem_stall ), + .i_exec_stall ( exec_stall ), + .i_conflict ( conflict ), + .o_fetch_stall ( fetch_stall ), + .i_system_rdy ( i_system_rdy ), + + // .i_iaddress ( {execute_iaddress[31:2], 2'd0} ), + .i_iaddress ( execute_iaddress ), + .i_iaddress_valid ( execute_iaddress_valid ), + .i_iaddress_nxt ( execute_iaddress_nxt ), + .o_fetch_instruction ( fetch_instruction ), + .i_cache_enable ( cache_enable ), + .i_cache_flush ( cache_flush ), + .i_cacheable_area ( cacheable_area ), + + .o_wb_req ( icache_wb_req ), + .o_wb_address ( icache_wb_address ), + .i_wb_read_data ( icache_wb_read_data ), + .i_wb_ready ( icache_wb_ready ) +); + + +// ====================================== +// Decode Stage +// ====================================== +a25_decode u_decode ( + .i_clk ( i_clk ), + .i_fetch_instruction ( fetch_instruction ), + .i_core_stall ( core_stall ), + .i_irq ( i_irq ), + .i_firq ( i_firq ), + .i_dabt ( 1'd0 ), + .i_iabt ( 1'd0 ), + .i_adex ( adex ), + + // Instruction fetch or data read signals + + .i_execute_iaddress ( execute_iaddress ), + // .i_execute_daddress ( execute_daddress ), + .i_abt_status ( 8'd0 ), + .i_execute_status_bits ( execute_status_bits ), + .i_multiply_done ( multiply_done ), + + .o_imm32 ( imm32 ), + .o_imm_shift_amount ( imm_shift_amount ), + .o_shift_imm_zero ( shift_imm_zero ), + .o_condition ( condition ), + .o_decode_exclusive ( decode_exclusive ), + .o_decode_iaccess ( decode_iaccess ), + .o_decode_daccess ( decode_daccess ), + .o_status_bits_mode ( status_bits_mode ), + .o_status_bits_irq_mask ( status_bits_irq_mask ), + .o_status_bits_firq_mask ( status_bits_firq_mask ), + + .o_rm_sel ( rm_sel ), + .o_rs_sel ( rs_sel ), + .o_load_rd ( decode_load_rd ), + + .o_rn_sel ( rn_sel ), + .o_barrel_shift_amount_sel ( barrel_shift_amount_sel ), + .o_barrel_shift_data_sel ( barrel_shift_data_sel ), + .o_barrel_shift_function ( barrel_shift_function ), + .o_alu_function ( alu_function ), + .o_multiply_function ( multiply_function ), + .o_interrupt_vector_sel ( interrupt_vector_sel ), + .o_iaddress_sel ( iaddress_sel ), + .o_daddress_sel ( daddress_sel ), + .o_pc_sel ( pc_sel ), + .o_byte_enable_sel ( byte_enable_sel ), + .o_status_bits_sel ( status_bits_sel ), + .o_reg_write_sel ( reg_write_sel ), + .o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), + .o_firq_not_user_mode ( firq_not_user_mode ), + .o_write_data_wen ( write_data_wen ), + .o_base_address_wen ( base_address_wen ), + .o_pc_wen ( pc_wen ), + .o_reg_bank_wen ( reg_bank_wen ), + .o_status_bits_flags_wen ( status_bits_flags_wen ), + .o_status_bits_mode_wen ( status_bits_mode_wen ), + .o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ), + .o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ), + + .o_copro_opcode1 ( copro_opcode1 ), + .o_copro_opcode2 ( copro_opcode2 ), + .o_copro_crn ( copro_crn ), + .o_copro_crm ( copro_crm ), + .o_copro_num ( copro_num ), + .o_copro_operation ( copro_operation ), + .o_copro_write_data_wen ( copro_write_data_wen ), + + .o_iabt_trigger ( iabt_trigger ), + .o_iabt_address ( iabt_fault_address ), + .o_iabt_status ( iabt_fault_status ), + .o_dabt_trigger ( dabt_trigger ), + .o_dabt_address ( dabt_fault_address ), + .o_dabt_status ( dabt_fault_status ), + + .o_conflict ( conflict ), + .o_rn_use_read ( rn_use_read ), + .o_rm_use_read ( rm_use_read ), + .o_rs_use_read ( rs_use_read ), + .o_rd_use_read ( rd_use_read ) +); + +// ====================================== +// Execute Stage +// ====================================== +a25_execute u_execute ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + .i_mem_stall ( mem_stall ), + .o_exec_stall ( exec_stall ), + + .i_wb_read_data ( wb_read_data ), + .i_wb_read_data_valid ( wb_read_data_valid ), + .i_wb_load_rd ( wb_load_rd ), + + .i_copro_read_data ( copro_read_data ), + .i_decode_iaccess ( decode_iaccess ), + .i_decode_daccess ( decode_daccess ), + .i_decode_load_rd ( decode_load_rd ), + .o_copro_write_data ( copro_write_data ), + .o_write_data ( write_data ), + .o_iaddress ( execute_iaddress ), + .o_iaddress_nxt ( execute_iaddress_nxt ), + .o_iaddress_valid ( execute_iaddress_valid ), + .o_daddress ( execute_daddress ), + .o_daddress_nxt ( execute_daddress_nxt ), + .o_daddress_valid ( execute_daddress_valid ), + + .o_adex ( adex ), + .o_priviledged ( priviledged ), + .o_exclusive ( exclusive ), + .o_write_enable ( write_enable ), + .o_byte_enable ( byte_enable ), + .o_exec_load_rd ( exec_load_rd ), + .o_status_bits ( execute_status_bits ), + .o_multiply_done ( multiply_done ), + + .i_status_bits_mode ( status_bits_mode ), + .i_status_bits_irq_mask ( status_bits_irq_mask ), + .i_status_bits_firq_mask ( status_bits_firq_mask ), + .i_imm32 ( imm32 ), + .i_imm_shift_amount ( imm_shift_amount ), + .i_shift_imm_zero ( shift_imm_zero ), + .i_condition ( condition ), + .i_decode_exclusive ( decode_exclusive ), + + .i_rm_sel ( rm_sel ), + .i_rs_sel ( rs_sel ), + + .i_rn_sel ( rn_sel ), + .i_barrel_shift_amount_sel ( barrel_shift_amount_sel ), + .i_barrel_shift_data_sel ( barrel_shift_data_sel ), + .i_barrel_shift_function ( barrel_shift_function ), + .i_alu_function ( alu_function ), + .i_multiply_function ( multiply_function ), + .i_interrupt_vector_sel ( interrupt_vector_sel ), + .i_iaddress_sel ( iaddress_sel ), + .i_daddress_sel ( daddress_sel ), + .i_pc_sel ( pc_sel ), + .i_byte_enable_sel ( byte_enable_sel ), + .i_status_bits_sel ( status_bits_sel ), + .i_reg_write_sel ( reg_write_sel ), + .i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), + .i_firq_not_user_mode ( firq_not_user_mode ), + .i_write_data_wen ( write_data_wen ), + .i_base_address_wen ( base_address_wen ), + .i_pc_wen ( pc_wen ), + .i_reg_bank_wen ( reg_bank_wen ), + .i_status_bits_flags_wen ( status_bits_flags_wen ), + .i_status_bits_mode_wen ( status_bits_mode_wen ), + .i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ), + .i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ), + .i_copro_write_data_wen ( copro_write_data_wen ), + .i_conflict ( conflict ), + .i_rn_use_read ( rn_use_read ), + .i_rm_use_read ( rm_use_read ), + .i_rs_use_read ( rs_use_read ), + .i_rd_use_read ( rd_use_read ) +); + + + +// ====================================== +// Memory access stage with data cache +// ====================================== +a25_mem u_mem ( + .i_clk ( i_clk ), + .i_fetch_stall ( fetch_stall ), + .i_exec_stall ( exec_stall ), + .o_mem_stall ( mem_stall ), + + .i_daddress ( execute_daddress ), + .i_daddress_valid ( execute_daddress_valid ), + .i_daddress_nxt ( execute_daddress_nxt ), + .i_write_data ( write_data ), + .i_write_enable ( write_enable ), + .i_exclusive ( exclusive ), + .i_byte_enable ( byte_enable ), + .i_exec_load_rd ( exec_load_rd ), + .i_cache_enable ( cache_enable ), + .i_cache_flush ( cache_flush ), + .i_cacheable_area ( cacheable_area ), + + .o_mem_read_data ( mem_read_data ), + .o_mem_read_data_valid ( mem_read_data_valid ), + .o_mem_load_rd ( mem_load_rd ), + + .o_wb_cached_req ( dcache_wb_cached_req ), + .o_wb_uncached_req ( dcache_wb_uncached_req ), + .o_wb_write ( dcache_wb_write ), + .o_wb_byte_enable ( dcache_wb_byte_enable ), + .o_wb_write_data ( dcache_wb_write_data ), + .o_wb_address ( dcache_wb_address ), + .i_wb_uncached_rdata ( dcache_wb_cached_rdata ), + .i_wb_cached_rdata ( dcache_wb_cached_rdata ), + .i_wb_cached_ready ( dcache_wb_cached_ready ), + .i_wb_uncached_ready ( dcache_wb_uncached_ready ) + +); + +// ====================================== +// Write back stage with data cache +// ====================================== +a25_write_back u_write_back ( + .i_clk ( i_clk ), + .i_mem_stall ( mem_stall ), + + .i_mem_read_data ( mem_read_data ), + .i_mem_read_data_valid ( mem_read_data_valid ), + .i_mem_load_rd ( mem_load_rd ), + + .o_wb_read_data ( wb_read_data ), + .o_wb_read_data_valid ( wb_read_data_valid ), + .o_wb_load_rd ( wb_load_rd ), + .i_daddress ( execute_daddress ) +// .i_daddress_valid ( execute_daddress_valid ) +); + + +// ====================================== +// Wishbone Master I/F +// ====================================== +a25_wishbone u_wishbone ( + // CPU Side + .i_clk ( i_clk ), + + // Port 0 - dcache uncached + .i_port0_req ( dcache_wb_uncached_req ), + .o_port0_ack ( dcache_wb_uncached_ready ), + .i_port0_write ( dcache_wb_write ), + .i_port0_wdata ( dcache_wb_write_data ), + .i_port0_be ( dcache_wb_byte_enable ), + .i_port0_addr ( dcache_wb_address ), + .o_port0_rdata ( port0_rdata ), //output [127:0] o_port0_rdata + + // Port 1 - dcache cached + .i_port1_req ( dcache_wb_cached_req ), + .o_port1_ack ( dcache_wb_cached_ready ), + .i_port1_write ( dcache_wb_write ), + .i_port1_wdata ( dcache_wb_write_data ), + .i_port1_be ( dcache_wb_byte_enable ), + .i_port1_addr ( dcache_wb_address ), + .o_port1_rdata ( dcache_wb_cached_rdata ), + + // Port 2 - instruction cache accesses, read only + .i_port2_req ( icache_wb_req ), + .o_port2_ack ( icache_wb_ready ), + .i_port2_write ( 1'd0 ), + .i_port2_wdata ( 128'd0 ), + .i_port2_be ( 16'd0 ), + .i_port2_addr ( icache_wb_address ), + .o_port2_rdata ( icache_wb_read_data ), + + // Wishbone + .o_wb_adr ( o_wb_adr ), + .o_wb_sel ( o_wb_sel ), + .o_wb_we ( o_wb_we ), + .o_wb_dat ( o_wb_dat ), + .o_wb_cyc ( o_wb_cyc ), + .o_wb_stb ( o_wb_stb ), + .i_wb_dat ( i_wb_dat ), + .i_wb_ack ( i_wb_ack ) +// .i_wb_err ( i_wb_err ) +); + +// ====================================== +// Co-Processor #15 +// ====================================== +a25_coprocessor u_coprocessor ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + +// .i_copro_opcode1 ( copro_opcode1 ), +// .i_copro_opcode2 ( copro_opcode2 ), + .i_copro_crn ( copro_crn ), +// .i_copro_crm ( copro_crm ), +// .i_copro_num ( copro_num ), + .i_copro_operation ( copro_operation ), + .i_copro_write_data ( copro_write_data ), + + .i_fault ( decode_fault ), + .i_fault_status ( decode_fault_status ), + .i_fault_address ( decode_fault_address ), + + .o_copro_read_data ( copro_read_data ), + .o_cache_enable ( cache_enable ), + .o_cache_flush ( cache_flush ), + .o_cacheable_area ( cacheable_area ) +); + + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/bgm.v b/openfpga_flow/benchmarks/vtr_benchmark/bgm.v new file mode 100755 index 000000000..dbb32256a --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/bgm.v @@ -0,0 +1,2659 @@ +// DEFINES +`define BITS 32 // Bit width of the operands +`define NumPath 34 + +module bgm(clock, + reset, + sigma_a, + sigma_b, + sigma_c, + Fn, + dw_x, + dw_y, + dw_z, + dt, + Fn_out +); + +// SIGNAL DECLARATIONS +input clock; +input reset; + +input [`BITS-1:0] sigma_a; +input [`BITS-1:0] sigma_b; +input [`BITS-1:0] sigma_c; +input [`BITS-1:0] Fn; +input [`BITS-1:0] dw_x; +input [`BITS-1:0] dw_y; +input [`BITS-1:0] dw_z; +input [`BITS-1:0] dt; + +output [`BITS-1:0] Fn_out; + +wire [`BITS-1:0] x0; +wire [`BITS-1:0] x1; +wire [`BITS-1:0] x2; +wire [`BITS-1:0] x3; +wire [`BITS-1:0] x4; +wire [`BITS-1:0] x5; +wire [`BITS-1:0] x6; +wire [`BITS-1:0] x7; +wire [`BITS-1:0] x8; +wire [`BITS-1:0] x9; +wire [`BITS-1:0] x10; + +wire [`BITS-1:0] a0; +wire [`BITS-1:0] a1; +wire [`BITS-1:0] a2; +wire [`BITS-1:0] a3; +wire [`BITS-1:0] a4; +wire [`BITS-1:0] a5; +wire [`BITS-1:0] a6; +wire [`BITS-1:0] a7; +wire [`BITS-1:0] a8; + +wire [`BITS-1:0] Fn_out; +wire [`BITS-1:0] Fn_delay_chain; +wire [`BITS-1:0] Fn_delay_chain_delay5; + +wire [`BITS-1:0] dw_x_delay; +wire [`BITS-1:0] dw_y_delay; +wire [`BITS-1:0] dw_z_delay; +wire [`BITS-1:0] sigma_a_delay; +wire [`BITS-1:0] sigma_b_delay; +wire [`BITS-1:0] sigma_c_delay; + +wire [`BITS-1:0] fifo_out1; +wire [`BITS-1:0] fifo_out2; +wire [`BITS-1:0] fifo_out3; + +wire [`BITS-1:0] a4_delay5; +/* +delay44 delay_u1(clock, dw_x, dw_x_delay); +delay44 delay_u2(clock, dw_y, dw_y_delay); +delay44 delay_u3(clock, dw_z, dw_z_delay); +delay44 delay_u4(clock, sigma_a, sigma_a_delay); +delay44 delay_u5(clock, sigma_b, sigma_b_delay); +delay44 delay_u6(clock, sigma_c, sigma_c_delay); + +fifo fifo_1(clock, a0, fifo_out1); +fifo fifo_2(clock, a1, fifo_out2); +fifo fifo_3(clock, a2, fifo_out3); +*/ + +delay5 delay_u1(clock, dw_x, dw_x_delay); +delay5 delay_u2(clock, dw_y, dw_y_delay); +delay5 delay_u3(clock, dw_z, dw_z_delay); +delay5 delay_u4(clock, sigma_a, sigma_a_delay); +delay5 delay_u5(clock, sigma_b, sigma_b_delay); +delay5 delay_u6(clock, sigma_c, sigma_c_delay); + +delay5 fifo_1(clock, a0, fifo_out1); +delay5 fifo_2(clock, a1, fifo_out2); +delay5 fifo_3(clock, a2, fifo_out3); + + + +//assign x0 = Fn * sigma_a; +wire [7:0] x0_control; +fpu_mul x0_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_a), + .out(x0), + .control(x0_control) +); + +//assign x1 = Fn * sigma_b; +wire [7:0] x1_control; +fpu_mul x1_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_b), + .out(x1), + .control(x1_control) +); + + +//assign x2 = Fn * sigma_c; +wire [7:0] x2_control; +fpu_mul x2_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_c), + .out(x2), + .control(x2_control) +); + +//assign a0 = x0 + fifo_out1; +wire [7:0] a0_control; +fpu_add a0_add +( + .clk(clock), + .opa(x0), + .opb(fifo_out1), + .out(a0), + .control(a0_control) +); + + +//assign a1 = x1 + fifo_out2; +wire [7:0] a1_control; +fpu_add a1_add +( + .clk(clock), + .opa(x1), + .opb(fifo_out2), + .out(a1), + .control(a1_control) +); + +//assign a2 = x2 + fifo_out3; +wire [7:0] a2_control; +fpu_add a2_add +( + .clk(clock), + .opa(x2), + .opb(fifo_out3), + .out(a2), + .control(a2_control) +); + +//assign x3 = dw_x_delay * sigma_a_delay; +wire [7:0] x3_control; +fpu_mul x3_mul +( + .clk(clock), + .opa(dw_x_delay), + .opb(sigma_a_delay), + .out(x3), + .control(x3_control) +); + + +//assign x4 = a0 * sigma_a_delay; +wire [7:0] x4_control; +fpu_mul x4_mul +( + .clk(clock), + .opa(a0), + .opb(sigma_a_delay), + .out(x4), + .control(x4_control) +); + + +//assign x5 = dw_y_delay * sigma_b_delay; +wire [7:0] x5_control; +fpu_mul x5_mul +( + .clk(clock), + .opa(dw_y_delay), + .opb(sigma_b_delay), + .out(x5), + .control(x5_control) +); + +//assign x6 = a1 * sigma_b_delay; +wire [7:0] x6_control; +fpu_mul x6_mul +( + .clk(clock), + .opa(a1), + .opb(sigma_b_delay), + .out(x6), + .control(x6_control) +); + +//assign x7 = dw_z_delay * sigma_c_delay; +wire [7:0] x7_control; +fpu_mul x7_mul +( + .clk(clock), + .opa(dw_z_delay), + .opb(sigma_c_delay), + .out(x7), + .control(x7_control) +); + +//assign x8 = a2 * sigma_c_delay; +wire [7:0] x8_control; +fpu_mul x8_mul +( + .clk(clock), + .opa(a2), + .opb(sigma_c_delay), + .out(x8), + .control(x8_control) +); + +//assign a3 = x3 + x5; +wire [7:0] a3_control; +fpu_add a3_add +( + .clk(clock), + .opa(x3), + .opb(x5), + .out(a3), + .control(a3_control) +); + +//assign a4 = a3 + x7; +wire [7:0] a4_control; +fpu_add a4_add +( + .clk(clock), + .opa(a3), + .opb(x7), + .out(a4), + .control(a4_control) +); + + +//assign a5 = x4 + x6; +wire [7:0] a5_control; +fpu_add a5_add +( + .clk(clock), + .opa(x4), + .opb(x6), + .out(a5), + .control(a5_control) +); + +//assign a6 = a5 + x8; +wire [7:0] a6_control; +fpu_add a6_add +( + .clk(clock), + .opa(a5), + .opb(x8), + .out(a6), + .control(a6_control) +); + +delay5 delay_a5(clock, a4, a4_delay5); + +//assign x9 = dt * a6; +wire [7:0] x9_control; +fpu_mul x9_mul +( + .clk(clock), + .opa(dt), + .opb(a6), + .out(x9), + .control(x9_control) +); + +//assign a7 = a4_delay5 + x9; +wire [7:0] a7_control; +fpu_add a7_add +( + .clk(clock), + .opa(a4_delay5), + .opb(x9), + .out(a7), + .control(a7_control) +); + + +//delay_chain delay_Fn(clock, Fn, Fn_delay_chain); +delay5 delay_Fn(clock, Fn, Fn_delay_chain); +delay5 delay_Fn_delay5(clock, Fn_delay_chain, Fn_delay_chain_delay5); + +//assign x10 = a7 * Fn_delay_chain; +wire [7:0] x10_control; +fpu_mul x10_mul +( + .clk(clock), + .opa(a7), + .opb(Fn_delay_chain), + .out(x10), + .control(x10_control) +); + +//assign a8 = Fn_delay_chain_delay5 + x10; +wire [7:0] a8_control; +fpu_add a8_add +( + .clk(clock), + .opa(Fn_delay_chain_delay5), + .opb(x10), + .out(a8), + .control(a8_control) +); + +assign Fn_out = a8; + + +endmodule + + + +/* +module fifo(clock, fifo_in, fifo_out); + input clock; + input [`BITS-1:0] fifo_in; + output [`BITS-1:0] fifo_out; + wire [`BITS-1:0] fifo_out; + + reg [`BITS-1:0] freg1; + + reg [`BITS-1:0] freg2; + reg [`BITS-1:0] freg3; + reg [`BITS-1:0] freg4; + reg [`BITS-1:0] freg5; + reg [`BITS-1:0] freg6; + reg [`BITS-1:0] freg7; + reg [`BITS-1:0] freg8; + reg [`BITS-1:0] freg9; + reg [`BITS-1:0] freg10; + reg [`BITS-1:0] freg11; + reg [`BITS-1:0] freg12; + reg [`BITS-1:0] freg13; + reg [`BITS-1:0] freg14; + reg [`BITS-1:0] freg15; + reg [`BITS-1:0] freg16; + reg [`BITS-1:0] freg17; + reg [`BITS-1:0] freg18; + reg [`BITS-1:0] freg19; + reg [`BITS-1:0] freg20; + reg [`BITS-1:0] freg21; + reg [`BITS-1:0] freg22; + reg [`BITS-1:0] freg23; + reg [`BITS-1:0] freg24; + reg [`BITS-1:0] freg25; + reg [`BITS-1:0] freg26; + reg [`BITS-1:0] freg27; + reg [`BITS-1:0] freg28; + reg [`BITS-1:0] freg29; + reg [`BITS-1:0] freg30; + reg [`BITS-1:0] freg31; + reg [`BITS-1:0] freg32; + reg [`BITS-1:0] freg33; + reg [`BITS-1:0] freg34; + + assign fifo_out = freg34; + + always @(posedge clock) + begin + freg1 <= fifo_in; + + freg2 <= freg1; + freg3 <= freg2; + freg4 <= freg3; + freg5 <= freg4; + freg6 <= freg5; + freg7 <= freg6; + freg8 <= freg7; + freg9 <= freg8; + freg10 <= freg9; + freg11 <= freg10; + freg12 <= freg11; + freg13 <= freg12; + freg14 <= freg13; + freg15 <= freg14; + freg16 <= freg15; + freg17 <= freg16; + freg18 <= freg17; + freg19 <= freg18; + freg20 <= freg19; + freg21 <= freg20; + freg22 <= freg21; + freg23 <= freg22; + freg24 <= freg23; + freg25 <= freg24; + freg26 <= freg25; + freg27 <= freg26; + freg28 <= freg27; + freg29 <= freg28; + freg30 <= freg29; + freg31 <= freg30; + freg32 <= freg31; + freg33 <= freg32; + freg34 <= freg33; + + end +endmodule +*/ + +module delay5 (clock, d5_delay_in, d5_delay_out); + input clock; + input [`BITS-1:0] d5_delay_in; + output [`BITS-1:0] d5_delay_out; + + //FIFO delay + reg [`BITS-1:0] d5_reg1; +/* + reg [`BITS-1:0] d5_reg2; + reg [`BITS-1:0] d5_reg3; + reg [`BITS-1:0] d5_reg4; + reg [`BITS-1:0] d5_reg5; + reg [`BITS-1:0] d5_reg6; +*/ + + assign d5_delay_out = d5_reg1; + + always @(posedge clock) + begin + d5_reg1 <= d5_delay_in; +/* + d5_reg2 <= d5_reg1; + d5_reg3 <= d5_reg2; + d5_reg4 <= d5_reg3; + d5_reg5 <= d5_reg4; + d5_reg6 <= d5_reg5; +*/ + end +endmodule + +/* +module delay44 (clock, delay_in, delay_out); + input clock; + input [`BITS-1:0] delay_in; + output [`BITS-1:0] delay_out; +// wire [`BITS-1:0] delay_out; + + //FIFO delay + wire [`BITS-1:0] fifo_out; + + //multiplier delay + wire [`BITS-1:0] delay5_dout1; + + //adder delay + wire [`BITS-1:0] delay5_dout2; + + fifo fifo_delay(clock, delay_in , fifo_out); + delay5 delay_d1(clock, fifo_out, delay5_dout1); + delay5 delay_d2(clock, delay5_dout1, delay5_dout2); + + assign delay_out = delay5_dout2; +// always @(posedge clock) +// begin +// fifo_out <= delay_in; +// delay5_dout1 <= fifo_out; +// delay5_dout2 <= delay5_dout1; +// end + +endmodule +*/ + +/* +module delay_chain (clock, delay_in, delay_out); + input clock; + input [`BITS-1:0] delay_in; + output [`BITS-1:0] delay_out; +// wire [`BITS-1:0] delay_out; + + wire [`BITS-1:0] delay44_out; + wire [`BITS-1:0] delay5_out1; + wire [`BITS-1:0] delay5_out2; + wire [`BITS-1:0] delay5_out3; + wire [`BITS-1:0] delay5_out4; + + delay44 delay_c1(clock, delay_in, delay44_out); + delay5 delay_c2(clock, delay44_out, delay5_out1); + delay5 delay_c3(clock, delay5_out1, delay5_out2); + delay5 delay_c4(clock, delay5_out2, delay5_out3); + delay5 delay_c5(clock, delay5_out3, delay5_out4); + + assign delay_out = delay5_out4; +endmodule +*/ + + +module fpu_mul( +clk, +//rmode, +opa, opb, out, +control +/* +inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero +*/ +); +input clk; +//input [1:0] rmode; +input [31:0] opa, opb; +output [31:0] out; +output [7:0] control; +/* +output inf, snan, qnan; +output ine; +output overflow, underflow; +output zero; +output div_by_zero; +*/ + + + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires +// +reg [2:0] fpu_op; +reg zero; +reg [31:0] opa_r, opb_r; // Input operand registers +reg [31:0] out; // Output register +reg div_by_zero; // Divide by zero output register +wire signa, signb; // alias to opX sign +wire sign_fasu; // sign output +wire [26:0] fracta, fractb; // Fraction Outputs from EQU block +wire [7:0] exp_fasu; // Exponent output from EQU block +reg [7:0] exp_r; // Exponent output (registerd) +wire [26:0] fract_out_d; // fraction output +wire co; // carry output +reg [27:0] fract_out_q; // fraction output (registerd) +wire [30:0] out_d; // Intermediate final result output +wire overflow_d, underflow_d;// Overflow/Underflow Indicators +reg overflow, underflow; // Output registers for Overflow & Underflow +reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN +reg ine; // Output Registers for INE +reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode + rmode_r3; +reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration + fpu_op_r3; +wire mul_inf, div_inf; +wire mul_00, div_00; +/* +parameter INF = 31'h7f800000; +parameter QNAN = 31'h7fc00001; +parameter SNAN = 31'h7f800001; + +*/ +wire [1:0] rmode; +assign rmode = 2'b00; + +wire [30:0] INF; +assign INF = 31'h7f800000; +wire [30:0] QNAN; +assign QNAN = 31'h7fc00001; +wire [30:0] SNAN; +assign SNAN = 31'h7f800001; + +// start output_reg +reg [31:0] out_o1; +reg inf_o1, snan_o1, qnan_o1; +reg ine_o1; +reg overflow_o1, underflow_o1; +reg zero_o1; +reg div_by_zero_o1; +// end output_reg + +wire [7:0] contorl; +assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero}; + +//////////////////////////////////////////////////////////////////////// +// +// Input Registers +// + +always @(posedge clk) begin + fpu_op[2:0] <= 3'b010; +end + +always @(posedge clk) + opa_r <= opa; + +always @(posedge clk) + opb_r <= opb; + +always @(posedge clk) + rmode_r1 <= rmode; + +always @(posedge clk) + rmode_r2 <= rmode_r1; + +always @(posedge clk) + rmode_r3 <= rmode_r2; + +always @(posedge clk) + fpu_op_r1 <= fpu_op; + +always @(posedge clk) + fpu_op_r2 <= fpu_op_r1; + +always @(posedge clk) + fpu_op_r3 <= fpu_op_r2; + +//////////////////////////////////////////////////////////////////////// +// +// Exceptions block +// +wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; +wire opa_00, opb_00; +wire opa_inf, opb_inf; +wire opa_dn, opb_dn; + +except u0( .clk(clk), + .opa(opa_r[30:0]), .opb(opb_r[30:0]), + .inf(inf_d), .ind(ind_d), + .qnan(qnan_d), .snan(snan_d), + .opa_nan(opa_nan), .opb_nan(opb_nan), + .opa_00(opa_00), .opb_00(opb_00), + .opa_inf(opa_inf), .opb_inf(opb_inf), + .opa_dn(opa_dn), .opb_dn(opb_dn) + ); + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize block +// - Adjusts the numbers to equal exponents and sorts them +// - determine result sign +// - determine actual operation to perform (add or sub) +// + +wire nan_sign_d, result_zero_sign_d; +reg sign_fasu_r; +wire [7:0] exp_mul; +wire sign_mul; +reg sign_mul_r; +wire [23:0] fracta_mul, fractb_mul; +wire inf_mul; +reg inf_mul_r; +wire [1:0] exp_ovf; +reg [1:0] exp_ovf_r; +wire sign_exe; +reg sign_exe_r; +wire [2:0] underflow_fmul_d; + +pre_norm_fmul u2( + .clk(clk), + .fpu_op(fpu_op_r1), + .opa(opa_r), .opb(opb_r), + .fracta(fracta_mul), + .fractb(fractb_mul), + .exp_out(exp_mul), // FMUL exponent output (registered) + .sign(sign_mul), // FMUL sign output (registered) + .sign_exe(sign_exe), // FMUL exception sign output (registered) + .inf(inf_mul), // FMUL inf output (registered) + .exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered) + .underflow(underflow_fmul_d) + ); + +always @(posedge clk) + sign_mul_r <= sign_mul; + +always @(posedge clk) + sign_exe_r <= sign_exe; + +always @(posedge clk) + inf_mul_r <= inf_mul; + +always @(posedge clk) + exp_ovf_r <= exp_ovf; + + +//////////////////////////////////////////////////////////////////////// +// +// Mul +// +wire [47:0] prod; + +mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod)); + + +//////////////////////////////////////////////////////////////////////// +// +// Normalize Result +// +wire ine_d; +reg [47:0] fract_denorm; +wire [47:0] fract_div; +wire sign_d; +reg sign; +reg [30:0] opa_r1; +reg [47:0] fract_i2f; +reg opas_r1, opas_r2; +wire f2i_out_sign; + +always @(posedge clk) // Exponent must be once cycle delayed + exp_r <= exp_mul; + +always @(posedge clk) + opa_r1 <= opa_r[30:0]; + +//always @(fpu_op_r3 or prod) +always @(prod) + fract_denorm = prod; + +always @(posedge clk) + opas_r1 <= opa_r[31]; + +always @(posedge clk) + opas_r2 <= opas_r1; + +assign sign_d = sign_mul; + +always @(posedge clk) + sign <= (rmode_r2==2'h3) ? !sign_d : sign_d; + +wire or_result; +assign or_result = mul_00 | div_00; +post_norm u4( +//.clk(clk), // System Clock + .fpu_op(fpu_op_r3), // Floating Point Operation + .opas(opas_r2), // OPA Sign + .sign(sign), // Sign of the result + .rmode(rmode_r3), // Rounding mode + .fract_in(fract_denorm), // Fraction Input + .exp_in(exp_r), // Exponent Input + .exp_ovf(exp_ovf_r), // Exponent Overflow + .opa_dn(opa_dn), // Operand A Denormalized + .opb_dn(opb_dn), // Operand A Denormalized + .rem_00(1'b0), // Diveide Remainder is zero + .div_opa_ldz(5'b00000), // Divide opa leading zeros count +// .output_zero(mul_00 | div_00), // Force output to Zero + .output_zero(or_result), // Force output to Zero + .out(out_d), // Normalized output (un-registered) + .ine(ine_d), // Result Inexact output (un-registered) + .overflow(overflow_d), // Overflow output (un-registered) + .underflow(underflow_d), // Underflow output (un-registered) + .f2i_out_sign(f2i_out_sign) // F2I Output Sign + ); + +//////////////////////////////////////////////////////////////////////// +// +// FPU Outputs +// +wire [30:0] out_fixed; +wire output_zero_fasu; +wire output_zero_fdiv; +wire output_zero_fmul; +reg inf_mul2; +wire overflow_fasu; +wire overflow_fmul; +wire overflow_fdiv; +wire inf_fmul; +wire sign_mul_final; +wire out_d_00; +wire sign_div_final; +wire ine_mul, ine_mula, ine_div, ine_fasu; +wire underflow_fasu, underflow_fmul, underflow_fdiv; +wire underflow_fmul1; +reg [2:0] underflow_fmul_r; +reg opa_nan_r; + + + +always @(posedge clk) + inf_mul2 <= exp_mul == 8'hff; + + +// Force pre-set values for non numerical output +assign mul_inf = (fpu_op_r3==3'b010) & (inf_mul_r | inf_mul2) & (rmode_r3==2'h0); +assign div_inf = (fpu_op_r3==3'b011) & (opb_00 | opa_inf); + +assign mul_00 = (fpu_op_r3==3'b010) & (opa_00 | opb_00); +assign div_00 = (fpu_op_r3==3'b011) & (opa_00 | opb_inf); + +assign out_fixed = + ( (qnan_d | snan_d) | + (opa_inf & opb_00)| + (opb_inf & opa_00 ) + ) ? QNAN : INF; + +always @(posedge clk) + out_o1[30:0] <= (mul_inf | div_inf | inf_d | snan_d | qnan_d) ? out_fixed : out_d; + +assign out_d_00 = !(|out_d); + +assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf))) ? !sign_mul_r : sign_mul_r; + +assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00); + +always @(posedge clk) +// out_o1[31] <= !(snan_d | qnan_d) ? sign_mul_final : nan_sign_d ; + out_o1[31] <= !(snan_d | qnan_d) & sign_mul_final; + +// Exception Outputs +assign ine_mula = ((inf_mul_r | inf_mul2 | opa_inf | opb_inf) & (rmode_r3==2'h1) & + !((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3[1]); + +assign ine_mul = (ine_mula | ine_d | inf_fmul | out_d_00 | overflow_d | underflow_d) & + !opa_00 & !opb_00 & !(snan_d | qnan_d | inf_d); + +always @(posedge clk) + ine_o1 <= ine_mul; + + +assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d | qnan_d); + +always @(posedge clk) + overflow_o1 <= overflow_fmul; + +always @(posedge clk) + underflow_fmul_r <= underflow_fmul_d; + +wire out_d_compare1; +assign out_d_compare1 = (out_d[30:23]==8'b0); + +wire out_d_compare2; +assign out_d_compare2 = (out_d[22:0]==23'b0); +/* +assign underflow_fmul1 = underflow_fmul_r[0] | + (underflow_fmul_r[1] & underflow_d ) | + ((opa_dn | opb_dn) & out_d_00 & (prod!=0) & sign) | + (underflow_fmul_r[2] & ((out_d[30:23]==8'b0) | (out_d[22:0]==23'b0))); +*/ +assign underflow_fmul1 = underflow_fmul_r[0] | + (underflow_fmul_r[1] & underflow_d ) | + ((opa_dn | opb_dn) & out_d_00 & (prod!=48'b0) & sign) | + (underflow_fmul_r[2] & (out_d_compare1 | out_d_compare2)); + + +assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r); +/* +always @(posedge clk) +begin + underflow_o1 <= 1'b0; + snan_o1 <= 1'b0; + qnan_o1 <= 1'b0; + inf_fmul <= 1'b0; + inf_o1 <= 1'b0; + zero_o1 <= 1'b0; + opa_nan_r <= 1'b0; + div_by_zero_o1 <= 1'b0; +end +assign output_zero_fmul = 1'b0; +*/ + + +always @(posedge clk) + underflow_o1 <= underflow_fmul; + +always @(posedge clk) + snan_o1 <= snan_d; + +// Status Outputs +always @(posedge clk) + qnan_o1 <= ( snan_d | qnan_d | + (((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010) + ); + +assign inf_fmul = (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) & + !((opa_inf & opb_00) | (opb_inf & opa_00 )) & + fpu_op_r3==3'b010; + +always @(posedge clk) +/* + inf_o1 <= fpu_op_r3[2] ? 1'b0 : + (!(qnan_d | snan_d) & + ( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul) + ); +*/ + inf_o1 <= !fpu_op_r3[2] & (!(qnan_d | snan_d) & + ( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul) + ); + +assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) & + !(inf_mul_r | inf_mul2 | opa_inf | opb_inf | snan_d | qnan_d) & + !(opa_inf & opb_00) & !(opb_inf & opa_00); + +always @(posedge clk) + zero_o1 <= output_zero_fmul; + +always @(posedge clk) + opa_nan_r <= (!opa_nan) & (fpu_op_r2==3'b011) ; + +always @(posedge clk) + div_by_zero_o1 <= opa_nan_r & !opa_00 & !opa_inf & opb_00; + + +// output register +always @(posedge clk) +begin + qnan <= qnan_o1; + out <= out_o1; + inf <= inf_o1; + snan <= snan_o1; + //qnan <= qnan_o1; + ine <= ine_o1; + overflow <= overflow_o1; + underflow <= underflow_o1; + zero <= zero_o1; + div_by_zero <= div_by_zero_o1; +end +endmodule + + +//--------------------------------------------------------------------------------- +module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan, + opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn); +input clk; +input [30:0] opa, opb; +output inf, ind, qnan, snan, opa_nan, opb_nan; +output opa_00, opb_00; +output opa_inf, opb_inf; +output opa_dn; +output opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +reg expa_ff, infa_f_r, qnan_r_a, snan_r_a; +reg expb_ff, infb_f_r, qnan_r_b, snan_r_b; +reg inf, ind, qnan, snan; // Output registers +reg opa_nan, opb_nan; +reg expa_00, expb_00, fracta_00, fractb_00; +reg opa_00, opb_00; +reg opa_inf, opb_inf; +reg opa_dn, opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Determine if any of the input operators is a INF or NAN or any other special number +// + +always @(posedge clk) + expa_ff <= &expa; + +always @(posedge clk) + expb_ff <= &expb; + +always @(posedge clk) + infa_f_r <= !(|fracta); + +always @(posedge clk) + infb_f_r <= !(|fractb); + +always @(posedge clk) + qnan_r_a <= fracta[22]; + +always @(posedge clk) + snan_r_a <= !fracta[22] & |fracta[21:0]; + +always @(posedge clk) + qnan_r_b <= fractb[22]; + +always @(posedge clk) + snan_r_b <= !fractb[22] & |fractb[21:0]; + +always @(posedge clk) + ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r); + +always @(posedge clk) + inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r); + +always @(posedge clk) + qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b); + +always @(posedge clk) + snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b); + +always @(posedge clk) + opa_nan <= &expa & (|fracta[22:0]); + +always @(posedge clk) + opb_nan <= &expb & (|fractb[22:0]); + +always @(posedge clk) + opa_inf <= (expa_ff & infa_f_r); + +always @(posedge clk) + opb_inf <= (expb_ff & infb_f_r); + +always @(posedge clk) + expa_00 <= !(|expa); + +always @(posedge clk) + expb_00 <= !(|expb); + +always @(posedge clk) + fracta_00 <= !(|fracta); + +always @(posedge clk) + fractb_00 <= !(|fractb); + +always @(posedge clk) + opa_00 <= expa_00 & fracta_00; + +always @(posedge clk) + opb_00 <= expb_00 & fractb_00; + +always @(posedge clk) + opa_dn <= expa_00; + +always @(posedge clk) + opb_dn <= expb_00; + +endmodule + + + + +//--------------------------------------------------------------------------------- +module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign, + sign_exe, inf, exp_ovf, underflow); +input clk; +input [2:0] fpu_op; +input [31:0] opa, opb; +output [23:0] fracta, fractb; +output [7:0] exp_out; +output sign, sign_exe; +output inf; +output [1:0] exp_ovf; +output [2:0] underflow; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +reg [7:0] exp_out; +wire signa, signb; +reg sign, sign_d; +reg sign_exe; +reg inf; +wire [1:0] exp_ovf_d; +reg [1:0] exp_ovf; +wire [7:0] expa, expb; +wire [7:0] exp_tmp1, exp_tmp2; +wire co1, co2; +wire expa_dn, expb_dn; +wire [7:0] exp_out_a; +wire opa_00, opb_00, fracta_00, fractb_00; +wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5; +wire [2:0] underflow_d; +reg [2:0] underflow; +wire op_div; +wire [7:0] exp_out_mul, exp_out_div; + +assign op_div = (fpu_op == 3'b011); +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; + +//////////////////////////////////////////////////////////////////////// +// +// Calculate Exponenet +// + +assign expa_dn = !(|expa); +assign expb_dn = !(|expb); +assign opa_00 = !(|opa[30:0]); +assign opb_00 = !(|opb[30:0]); +assign fracta_00 = !(|opa[22:0]); +assign fractb_00 = !(|opb[22:0]); + +assign fracta[22:0] = opa[22:0]; +assign fractb[22:0] = opb[22:0]; +assign fracta[23:23] = !expa_dn; +assign fractb[23:23] = !expb_dn; +//assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit +//assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit + +assign {co1,exp_tmp1} = op_div ? ({1'b0,expa[7:0]} - {1'b0,expb[7:0]}) : ({1'b0,expa[7:0]} + {1'b0,expb[7:0]}); +assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 9'h07f) : ({co1,exp_tmp1} - 9'h07f); +assign exp_tmp3 = exp_tmp2 + 8'h01; +assign exp_tmp4 = 8'h7f - exp_tmp1; +assign exp_tmp5 = op_div ? (exp_tmp4+8'h01) : (exp_tmp4-8'h01); + + +always@(posedge clk) + exp_out <= op_div ? exp_out_div : exp_out_mul; + +assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2; +assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2; +assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4; +assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]); +assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2); + +always @(posedge clk) + exp_ovf <= exp_ovf_d; + +assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn); +assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) | + (expa_dn & !fracta_00) | (expb_dn & !fractb_00); +assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f); + +always @(posedge clk) + underflow <= underflow_d; + +always @(posedge clk) + inf <= op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ; + + +//////////////////////////////////////////////////////////////////////// +// +// Determine sign for the output +// + +// sign: 0=Posetive Number; 1=Negative Number +always @(signa or signb) + case({signa, signb}) // synopsys full_case parallel_case + 2'b00: sign_d = 0; + 2'b01: sign_d = 1; + 2'b10: sign_d = 1; + 2'b11: sign_d = 0; + endcase + +always @(posedge clk) + sign <= sign_d; + +always @(posedge clk) + sign_exe <= signa & signb; + +endmodule + +//---------------------------------------------------------------------------- +//////////////////////////////////////////////////////////////////////// +// +// Multiply +// + +module mul_r2(clk, opa, opb, prod); +input clk; +input [23:0] opa, opb; +output [47:0] prod; + +reg [47:0] prod1, prod; + +always @(posedge clk) + prod1 <= opa * opb; + +always @(posedge clk) + prod <= prod1; + +endmodule + + + +//---------------------------------------------------------------------------- + + +module post_norm( fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf, + opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out, + ine, overflow, underflow, f2i_out_sign); + input [2:0] fpu_op; + input opas; + input sign; + input [1:0] rmode; + input [47:0] fract_in; + input [7:0] exp_in; + input [1:0] exp_ovf; + input opa_dn, opb_dn; + input rem_00; + input [4:0] div_opa_ldz; + input output_zero; + output [30:0] out; + output ine; + output overflow, underflow; + output f2i_out_sign; + + //////////////////////////////////////////////////////////////////////// + // + // Local Wires and registers + // + + wire [22:0] fract_out; + wire [7:0] exp_out; + wire [30:0] out; + wire exp_out1_co, overflow, underflow; + wire [22:0] fract_out_final; + reg [22:0] fract_out_rnd; + wire [8:0] exp_next_mi; + wire dn; + wire exp_rnd_adj; + wire [7:0] exp_out_final; + reg [7:0] exp_out_rnd; + wire op_dn; + + wire op_mul; + wire op_div; + wire op_i2f; + wire op_f2i; + + + //reg [5:0] fi_ldz; + wire [5:0] fi_ldz; + + wire g, r, s; + wire round, round2, round2a, round2_fasu, round2_fmul; + wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a; + wire [22:0] fract_out_rnd0, fract_out_rnd1, fract_out_rnd2, fract_out_rnd2a; + wire exp_rnd_adj0, exp_rnd_adj2a; + wire r_sign; + wire ovf0, ovf1; + wire [23:0] fract_out_pl1; + wire [7:0] exp_out_pl1, exp_out_mi1; + wire exp_out_00, exp_out_fe, exp_out_ff, exp_in_00, exp_in_ff; + wire exp_out_final_ff, fract_out_7fffff; + wire [24:0] fract_trunc; + wire [7:0] exp_out1; + wire grs_sel; + wire fract_out_00, fract_in_00; + wire shft_co; + wire [8:0] exp_in_pl1, exp_in_mi1; + wire [47:0] fract_in_shftr; + wire [47:0] fract_in_shftl; + + // for block shifter + wire [47:0] fract_in_shftr_1; + wire [47:0] fract_in_shftl_1; + // end for block shifter + + wire [7:0] exp_div; + wire [7:0] shft2; + wire [7:0] exp_out1_mi1; + wire div_dn; + wire div_nr; + wire grs_sel_div; + + wire div_inf; + wire [6:0] fi_ldz_2a; + wire [7:0] fi_ldz_2; + wire [7:0] div_shft1, div_shft2, div_shft3, div_shft4; + wire div_shft1_co; + wire [8:0] div_exp1; + wire [7:0] div_exp2, div_exp3; + wire left_right, lr_mul, lr_div; + wire [7:0] shift_right, shftr_mul, shftr_div; + wire [7:0] shift_left, shftl_mul, shftl_div; + wire [7:0] fasu_shift; + wire [7:0] exp_fix_div; + + wire [7:0] exp_fix_diva, exp_fix_divb; + wire [5:0] fi_ldz_mi1; + wire [5:0] fi_ldz_mi22; + wire exp_zero; + wire [6:0] ldz_all; + wire [7:0] ldz_dif; + + wire [8:0] div_scht1a; + wire [7:0] f2i_shft; + wire [55:0] exp_f2i_1; + wire f2i_zero, f2i_max; + wire [7:0] f2i_emin; + wire [7:0] conv_shft; + wire [7:0] exp_i2f, exp_f2i, conv_exp; + wire round2_f2i; + + + assign op_mul = fpu_op[2:0]==3'b010; + assign op_div = fpu_op[2:0]==3'b011; + assign op_i2f = fpu_op[2:0]==3'b100; + assign op_f2i = fpu_op[2:0]==3'b101; + assign op_dn = opa_dn | opb_dn; + + pri_encoder u6( + .fract_in (fract_in), + .fi_ldz (fi_ldz) + ); + + // --------------------------------------------------------------------- + // Normalize + + wire exp_in_80; + wire rmode_00, rmode_01, rmode_10, rmode_11; + + // Misc common signals + assign exp_in_ff = &exp_in; + assign exp_in_00 = !(|exp_in); + assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]); + assign exp_out_ff = &exp_out; + assign exp_out_00 = !(|exp_out); + assign exp_out_fe = &exp_out[7:1] & !exp_out[0]; + assign exp_out_final_ff = &exp_out_final; + + assign fract_out_7fffff = &fract_out; + assign fract_out_00 = !(|fract_out); + assign fract_in_00 = !(|fract_in); + + assign rmode_00 = (rmode==2'b00); + assign rmode_01 = (rmode==2'b01); + assign rmode_10 = (rmode==2'b10); + assign rmode_11 = (rmode==2'b11); + + // Fasu Output will be denormalized ... + assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) ); + + // --------------------------------------------------------------------- + // Fraction Normalization + wire[7:0] f2i_emax; + assign f2i_emax = 8'h9d; + //parameter f2i_emax = 8'h9d; + + // Incremented fraction for rounding + assign fract_out_pl1 = {1'b0, fract_out} + 24'h000001; + + // Special Signals for f2i + assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f; + assign f2i_zero = (!opas & (exp_inf2i_emax)) | (opas & (exp_inf2i_emax)) | (opas & (exp_in8'h16); + + assign f2i_shft = exp_in-8'h7d; + + // Select shifting direction + assign left_right = op_div ? lr_div : op_mul ? lr_mul :1'b1; + + assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1'b1 : + (op_dn & exp_ovf[1]) ? 1'b0 : + (op_dn & div_shft1_co) ? 1'b0 : + (op_dn & exp_out_00) ? 1'b1 : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? 1'b1 : + exp_ovf[1] ? 1'b0 : + 1'b1; + assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1'b1 : + ( exp_ovf[1] | exp_in_00 ) ? 1'b0 : + 1'b1; + + // Select Left and Right shift value + assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h02 : exp_in_pl1[7:0]) : {2'h0, fi_ldz}; + assign shift_right = op_div ? shftr_div : shftr_mul; + + assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz}; + + assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift; + + assign shftl_mul = (shft_co | + (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz}; + + assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] : + {2'h0, fi_ldz}; + assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 : + (op_dn & div_shft1_co) ? div_shft4 : div_shft2; + // Do the actual shifting + //assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0]; + //assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<>shift_right[5:0]; + + + b_left_shifter u7( + .shift_in (fract_in), + .shift_value (shift_left[5:0]), + .shift_out (fract_in_shftl_1) + ); + + assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 48'b0 : fract_in_shftl_1; // fract_in<f2i_emax) ? 1'b0 : opas) : + ((exp_inf2i_emax) ? 1'b1 : opas); + + assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 8'h00) : (8'h9e-{2'b0, fi_ldz}); + + //assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<8'hfe) )) ? div_exp2 : + (opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 8'h00 : + exp_out1_mi1; + + assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f); + + // --------------------------------------------------------------------- + // Round + + // Extract rounding (GRS) bits + assign grs_sel_div = op_div & (exp_ovf[1] | div_dn | exp_out1_co | exp_out_00); + + assign g = grs_sel_div ? fract_out[0] : fract_out[0]; + assign r = grs_sel_div ? (fract_trunc[24] & !div_nr) : fract_trunc[24]; + assign s = grs_sel_div ? |fract_trunc[24:0] : (|fract_trunc[23:0] | (fract_trunc[24] & op_div)); + + // Round to nearest even + assign round = (g & r) | (r & s) ; + assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out}; + assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out; + assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i; + + // round to zero + assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out; + assign exp_fix_div = (fi_ldz>6'd22) ? exp_fix_diva : exp_fix_divb; + assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) : (exp_out_ff & !op_f2i) ? exp_in : exp_out; + assign ovf1 = exp_out_ff & !dn; + + // round to +inf (UP) and -inf (DOWN) + assign r_sign = sign; + + assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff); + assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a)); + + assign round2_fmul = !r_sign & + ( + (exp_ovf[1] & !fract_in_00 & + ( ((!exp_out1_co | op_dn) & (r | s | (!rem_00 & op_div) )) | fract_out_00 | (!op_dn & !op_div)) + ) | + ( + (r | s | (!rem_00 & op_div)) & ( + (!exp_ovf[1] & (exp_in_80 | !exp_ovf[0])) | op_div | + ( exp_ovf[1] & !exp_ovf[0] & exp_out1_co) + ) + ) + ); + + //assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc)); + wire temp_fract_in; + assign temp_fract_in = |fract_in[23:0]; + assign round2_f2i = rmode_10 & (( temp_fract_in & !opas & (exp_in<8'h80 )) | (|fract_trunc)); + + assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu; + + assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out}; + assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out; + + assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a; + assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a; + + + // Choose rounding mode + + always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2) + case(rmode) // synopsys full_case parallel_case + 2'b00: exp_out_rnd = exp_out_rnd0; + 2'b01: exp_out_rnd = exp_out_rnd1; + 2'b10: exp_out_rnd = exp_out_rnd2; + 2'b11: exp_out_rnd = exp_out_rnd2; + endcase + + always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2) + case (rmode) // synopsys full_case parallel_case + 2'b00: fract_out_rnd = fract_out_rnd0; + 2'b01: fract_out_rnd = fract_out_rnd1; + 2'b10: fract_out_rnd = fract_out_rnd2; + 2'b11: fract_out_rnd = fract_out_rnd2; + endcase + + // --------------------------------------------------------------------- + // Final Output Mux + // Fix Output for denormalized and special numbers + wire max_num, inf_out; + + assign max_num = ( !rmode_00 & (op_mul | op_div ) & ( + ( exp_ovf[1] & exp_ovf[0]) | + (!exp_ovf[1] & !exp_ovf[0] & exp_in_ff & (fi_ldz_2<8'd24) & (exp_out!=8'hfe) ) + ) + ) | + + ( op_div & ( + ( rmode_01 & ( div_inf | + (exp_out_ff & !exp_ovf[1] ) | + (exp_ovf[1] & exp_ovf[0] ) + ) + ) | + + ( rmode[1] & !exp_ovf[1] & ( + ( exp_ovf[0] & exp_in_ff & r_sign & fract_in[47] + ) | + + ( r_sign & ( + (fract_in[47] & div_inf) | + (exp_in[7] & !exp_out_rnd[7] & !exp_in_80 & exp_out!=8'h7f ) | + (exp_in[7] & exp_out_rnd[7] & r_sign & exp_out_ff & op_dn & + div_exp1>9'h0fe ) + ) + ) | + + ( exp_in_00 & r_sign & ( + div_inf | + (r_sign & exp_out_ff & fi_ldz_2<8'h18) + ) + ) + ) + ) + ) + ); + + + assign inf_out = (rmode[1] & (op_mul | op_div) & !r_sign & ( (exp_in_ff & !op_div) | + (exp_ovf[1] & exp_ovf[0] & (exp_in_00 | exp_in[7]) ) + ) + ) | (div_inf & op_div & ( + rmode_00 | + (rmode[1] & !exp_in_ff & !exp_ovf[1] & !exp_ovf[0] & !r_sign ) | + (rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign) + ) + ) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 8'd24) & (exp_out_rnd!=8'hfe) ); + + assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h000000 : + (max_num | (f2i_max & op_f2i) ) ? 23'h7fffff : + fract_out_rnd; + + assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 : + ((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff : + max_num ? 8'hfe : + exp_out_rnd; + + + // --------------------------------------------------------------------- + // Pack Result + + assign out = {exp_out_final, fract_out_final}; + + // --------------------------------------------------------------------- + // Exceptions + wire underflow_fmul; + wire overflow_fdiv; + wire undeflow_div; + + wire z; + assign z = shft_co | ( exp_ovf[1] | exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00)); + + assign underflow_fmul = ( (|fract_trunc) & z & !exp_in_ff ) | + (fract_out_00 & !fract_in_00 & exp_ovf[1]); + + + assign undeflow_div = !(exp_ovf[1] & exp_ovf[0] & rmode_00) & !inf_out & !max_num & exp_out_final!=8'hff & ( + + ((|fract_trunc) & !opb_dn & ( + ( op_dn & !exp_ovf[1] & exp_ovf[0]) | + ( op_dn & exp_ovf[1]) | + ( op_dn & div_shft1_co) | + exp_out_00 | + exp_ovf[1] + ) + + ) | + + ( exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & exp_in>8'h16 & fi_ldz<6'd23) | + ( op_dn & exp_in<8'd23 & fi_ldz<6'd23 & !rem_00) | + ( !op_dn & (exp_in[7]==exp_div[7]) & !rem_00) | + ( !op_dn & exp_in_00 & (exp_div[7:1]==7'h7f) ) | + ( !op_dn & exp_in<8'h7f & exp_in>8'h20 ) + ) + ) | + + (!exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & fi_ldz<6'd23 & exp_out_00) | + ( exp_in_00 & !rem_00) | + ( !op_dn & ldz_all<7'd23 & exp_in==8'h01 & exp_out_00 & !rem_00) + ) + ) + + ); + + assign underflow = op_div ? undeflow_div : op_mul ? underflow_fmul : (!fract_in[47] & exp_out1_co) & !dn; + + assign overflow_fdiv = inf_out | + (!rmode_00 & max_num) | + (exp_in[7] & op_dn & exp_out_ff) | + (exp_ovf[0] & (exp_ovf[1] | exp_out_ff) ); + + assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1); + + wire f2i_ine; + assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) | + (|fract_trunc) | + (f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) | + (f2i_max & rmode_11 & (exp_in<8'h80)); + + + + assign ine = op_f2i ? f2i_ine : + op_i2f ? (|fract_trunc) : + ((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00)); +endmodule + +//------------------------------------------------------------------------------------- + +module pri_encoder ( fract_in, fi_ldz ); + +input [47:0] fract_in; +output [5:0] fi_ldz; +reg [5:0] fi_ldz_r0; + +assign fi_ldz = fi_ldz_r0; + +always @(fract_in) +begin + if (fract_in[47:47] == 1'b1) + fi_ldz_r0 = 6'd1; + else if (fract_in[47:46] == 2'b01) + fi_ldz_r0 = 6'd2; + else if (fract_in[47:45] == 3'b001) + fi_ldz_r0 = 6'd3; + else if (fract_in[47:44] == 4'b0001) + fi_ldz_r0 = 6'd4; + else if (fract_in[47:43] == 5'b00001) + fi_ldz_r0 = 6'd5; + else if (fract_in[47:42] == 6'b000001) + fi_ldz_r0 = 6'd6; + else if (fract_in[47:41] == 7'b0000001) + fi_ldz_r0 = 6'd7; + else if (fract_in[47:40] == 8'b00000001) + fi_ldz_r0 = 6'd8; + else if (fract_in[47:39] == 9'b000000001) + fi_ldz_r0 = 6'd9; + else if (fract_in[47:38] == 10'b0000000001) + fi_ldz_r0 = 6'd10; + else if (fract_in[47:37] == 11'b00000000001) + fi_ldz_r0 = 6'd11; + else if (fract_in[47:36] == 12'b000000000001) + fi_ldz_r0 = 6'd12; + else if (fract_in[47:35] == 13'b0000000000001) + fi_ldz_r0 = 6'd13; + else if (fract_in[47:34] == 14'b00000000000001) + fi_ldz_r0 = 6'd14; + else if (fract_in[47:33] == 15'b000000000000001) + fi_ldz_r0 = 6'd15; + else if (fract_in[47:32] == 16'b0000000000000001) + fi_ldz_r0 = 6'd16; + else if (fract_in[47:31] == 17'b00000000000000001) + fi_ldz_r0 = 6'd17; + else if (fract_in[47:30] == 18'b000000000000000001) + fi_ldz_r0 = 6'd18; + else if (fract_in[47:29] == 19'b0000000000000000001) + fi_ldz_r0 = 6'd19; + else if (fract_in[47:28] == 20'b00000000000000000001) + fi_ldz_r0 = 6'd20; + else if (fract_in[47:27] == 21'b000000000000000000001) + fi_ldz_r0 = 6'd21; + else if (fract_in[47:26] == 22'b0000000000000000000001) + fi_ldz_r0 = 6'd22; + else if (fract_in[47:25] == 23'b00000000000000000000001) + fi_ldz_r0 = 6'd23; + else if (fract_in[47:24] == 24'b000000000000000000000001) + fi_ldz_r0 = 6'd24; + else if (fract_in[47:23] == 25'b0000000000000000000000001) + fi_ldz_r0 = 6'd25; + else if (fract_in[47:22] == 26'b00000000000000000000000001) + fi_ldz_r0 = 6'd26; + else if (fract_in[47:21] == 27'b000000000000000000000000001) + fi_ldz_r0 = 6'd27; + else if (fract_in[47:20] == 28'b0000000000000000000000000001) + fi_ldz_r0 = 6'd28; + else if (fract_in[47:19] == 29'b00000000000000000000000000001) + fi_ldz_r0 = 6'd29; + else if (fract_in[47:18] == 30'b000000000000000000000000000001) + fi_ldz_r0 = 6'd30; + else if (fract_in[47:17] == 31'b0000000000000000000000000000001) + fi_ldz_r0 = 6'd31; + else if (fract_in[47:16] == 32'b00000000000000000000000000000001) + fi_ldz_r0 = 6'd32; + else if (fract_in[47:15] == 33'b000000000000000000000000000000001) + fi_ldz_r0 = 6'd33; + else if (fract_in[47:14] == 34'b0000000000000000000000000000000001) + fi_ldz_r0 = 6'd34; + else if (fract_in[47:13] == 35'b00000000000000000000000000000000001) + fi_ldz_r0 = 6'd35; + else if (fract_in[47:12] == 36'b000000000000000000000000000000000001) + fi_ldz_r0 = 6'd36; + else if (fract_in[47:11] == 37'b0000000000000000000000000000000000001) + fi_ldz_r0 = 6'd37; + else if (fract_in[47:10] == 38'b00000000000000000000000000000000000001) + fi_ldz_r0 = 6'd38; + else if (fract_in[47:9] == 39'b000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd39; + else if (fract_in[47:8] == 40'b0000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd40; + else if (fract_in[47:7] == 41'b00000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd41; + else if (fract_in[47:6] == 42'b000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd42; + else if (fract_in[47:5] == 43'b0000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd43; + else if (fract_in[47:4] == 44'b00000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd44; + else if (fract_in[47:3] == 45'b000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd45; + else if (fract_in[47:2] == 46'b0000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd46; + else if (fract_in[47:1] == 47'b00000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd47; + else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd48; + else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000000) + fi_ldz_r0 = 6'd48; +end + +endmodule + + +module b_right_shifter ( + shift_in, + shift_value, + shift_out +); + +input [47:0] shift_in; +input [5:0] shift_value; +output [47:0] shift_out; +reg [47:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in >> 1; + 6'b000010: shift_out = shift_in >> 2; + 6'b000011: shift_out = shift_in >> 3; + 6'b000100: shift_out = shift_in >> 4; + 6'b000101: shift_out = shift_in >> 5; + 6'b000110: shift_out = shift_in >> 6; + 6'b000111: shift_out = shift_in >> 7; + 6'b001000: shift_out = shift_in >> 8; + 6'b001001: shift_out = shift_in >> 9; + 6'b001010: shift_out = shift_in >> 10; + 6'b001011: shift_out = shift_in >> 11; + 6'b001100: shift_out = shift_in >> 12; + 6'b001101: shift_out = shift_in >> 13; + 6'b001110: shift_out = shift_in >> 14; + 6'b001111: shift_out = shift_in >> 15; + 6'b010000: shift_out = shift_in >> 16; + 6'b010001: shift_out = shift_in >> 17; + 6'b010010: shift_out = shift_in >> 18; + 6'b010011: shift_out = shift_in >> 19; + 6'b010100: shift_out = shift_in >> 20; + 6'b010101: shift_out = shift_in >> 21; + 6'b010110: shift_out = shift_in >> 22; + 6'b010111: shift_out = shift_in >> 23; + 6'b011000: shift_out = shift_in >> 24; + 6'b011001: shift_out = shift_in >> 25; + 6'b011010: shift_out = shift_in >> 26; + 6'b011011: shift_out = shift_in >> 27; + 6'b011100: shift_out = shift_in >> 28; + 6'b011101: shift_out = shift_in >> 29; + 6'b011110: shift_out = shift_in >> 30; + 6'b011111: shift_out = shift_in >> 31; + 6'b100000: shift_out = shift_in >> 32; + 6'b100001: shift_out = shift_in >> 33; + 6'b100010: shift_out = shift_in >> 34; + 6'b100011: shift_out = shift_in >> 35; + 6'b100100: shift_out = shift_in >> 36; + 6'b100101: shift_out = shift_in >> 37; + 6'b100110: shift_out = shift_in >> 38; + 6'b100111: shift_out = shift_in >> 39; + 6'b101000: shift_out = shift_in >> 40; + 6'b101001: shift_out = shift_in >> 41; + 6'b101010: shift_out = shift_in >> 42; + 6'b101011: shift_out = shift_in >> 43; + 6'b101100: shift_out = shift_in >> 44; + 6'b101101: shift_out = shift_in >> 45; + 6'b101110: shift_out = shift_in >> 46; + 6'b101111: shift_out = shift_in >> 47; + 6'b110000: shift_out = shift_in >> 48; + + endcase +end + +//assign shift_out = shift_in >> shift_value; + +endmodule + +module b_left_shifter ( + shift_in, + shift_value, + shift_out +); + +input [47:0] shift_in; +input [5:0] shift_value; +output [47:0] shift_out; +reg [47:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in << 1; + 6'b000010: shift_out = shift_in << 2; + 6'b000011: shift_out = shift_in << 3; + 6'b000100: shift_out = shift_in << 4; + 6'b000101: shift_out = shift_in << 5; + 6'b000110: shift_out = shift_in << 6; + 6'b000111: shift_out = shift_in << 7; + 6'b001000: shift_out = shift_in << 8; + 6'b001001: shift_out = shift_in << 9; + 6'b001010: shift_out = shift_in << 10; + 6'b001011: shift_out = shift_in << 11; + 6'b001100: shift_out = shift_in << 12; + 6'b001101: shift_out = shift_in << 13; + 6'b001110: shift_out = shift_in << 14; + 6'b001111: shift_out = shift_in << 15; + 6'b010000: shift_out = shift_in << 16; + 6'b010001: shift_out = shift_in << 17; + 6'b010010: shift_out = shift_in << 18; + 6'b010011: shift_out = shift_in << 19; + 6'b010100: shift_out = shift_in << 20; + 6'b010101: shift_out = shift_in << 21; + 6'b010110: shift_out = shift_in << 22; + 6'b010111: shift_out = shift_in << 23; + 6'b011000: shift_out = shift_in << 24; + 6'b011001: shift_out = shift_in << 25; + 6'b011010: shift_out = shift_in << 26; + 6'b011011: shift_out = shift_in << 27; + 6'b011100: shift_out = shift_in << 28; + 6'b011101: shift_out = shift_in << 29; + 6'b011110: shift_out = shift_in << 30; + 6'b011111: shift_out = shift_in << 31; + 6'b100000: shift_out = shift_in << 32; + 6'b100001: shift_out = shift_in << 33; + 6'b100010: shift_out = shift_in << 34; + 6'b100011: shift_out = shift_in << 35; + 6'b100100: shift_out = shift_in << 36; + 6'b100101: shift_out = shift_in << 37; + 6'b100110: shift_out = shift_in << 38; + 6'b100111: shift_out = shift_in << 39; + 6'b101000: shift_out = shift_in << 40; + 6'b101001: shift_out = shift_in << 41; + 6'b101010: shift_out = shift_in << 42; + 6'b101011: shift_out = shift_in << 43; + 6'b101100: shift_out = shift_in << 44; + 6'b101101: shift_out = shift_in << 45; + 6'b101110: shift_out = shift_in << 46; + 6'b101111: shift_out = shift_in << 47; + 6'b110000: shift_out = shift_in << 48; + + endcase +end + +endmodule + + +module b_left_shifter_new ( + shift_in, + shift_value, + shift_out +); + +input [55:0] shift_in; +input [5:0] shift_value; +output [55:0] shift_out; +reg [55:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in << 1; + 6'b000010: shift_out = shift_in << 2; + 6'b000011: shift_out = shift_in << 3; + 6'b000100: shift_out = shift_in << 4; + 6'b000101: shift_out = shift_in << 5; + 6'b000110: shift_out = shift_in << 6; + 6'b000111: shift_out = shift_in << 7; + 6'b001000: shift_out = shift_in << 8; + 6'b001001: shift_out = shift_in << 9; + 6'b001010: shift_out = shift_in << 10; + 6'b001011: shift_out = shift_in << 11; + 6'b001100: shift_out = shift_in << 12; + 6'b001101: shift_out = shift_in << 13; + 6'b001110: shift_out = shift_in << 14; + 6'b001111: shift_out = shift_in << 15; + 6'b010000: shift_out = shift_in << 16; + 6'b010001: shift_out = shift_in << 17; + 6'b010010: shift_out = shift_in << 18; + 6'b010011: shift_out = shift_in << 19; + 6'b010100: shift_out = shift_in << 20; + 6'b010101: shift_out = shift_in << 21; + 6'b010110: shift_out = shift_in << 22; + 6'b010111: shift_out = shift_in << 23; + 6'b011000: shift_out = shift_in << 24; + 6'b011001: shift_out = shift_in << 25; + 6'b011010: shift_out = shift_in << 26; + 6'b011011: shift_out = shift_in << 27; + 6'b011100: shift_out = shift_in << 28; + 6'b011101: shift_out = shift_in << 29; + 6'b011110: shift_out = shift_in << 30; + 6'b011111: shift_out = shift_in << 31; + 6'b100000: shift_out = shift_in << 32; + 6'b100001: shift_out = shift_in << 33; + 6'b100010: shift_out = shift_in << 34; + 6'b100011: shift_out = shift_in << 35; + 6'b100100: shift_out = shift_in << 36; + 6'b100101: shift_out = shift_in << 37; + 6'b100110: shift_out = shift_in << 38; + 6'b100111: shift_out = shift_in << 39; + 6'b101000: shift_out = shift_in << 40; + 6'b101001: shift_out = shift_in << 41; + 6'b101010: shift_out = shift_in << 42; + 6'b101011: shift_out = shift_in << 43; + 6'b101100: shift_out = shift_in << 44; + 6'b101101: shift_out = shift_in << 45; + 6'b101110: shift_out = shift_in << 46; + 6'b101111: shift_out = shift_in << 47; + 6'b110000: shift_out = shift_in << 48; + 6'b110001: shift_out = shift_in << 49; + 6'b110010: shift_out = shift_in << 50; + 6'b110011: shift_out = shift_in << 51; + 6'b110100: shift_out = shift_in << 52; + 6'b110101: shift_out = shift_in << 53; + 6'b110110: shift_out = shift_in << 54; + 6'b110111: shift_out = shift_in << 55; + 6'b111000: shift_out = shift_in << 56; + endcase +end + +endmodule + +module fpu_add( clk, +//rmode, +opa, opb, out, +control +//inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero +); + input clk; + //input [1:0] rmode; + //input [2:0] fpu_op; + input [31:0] opa, opb; + output [31:0] out; + /* + output inf, snan, qnan; + output ine; + output overflow, underflow; + output zero; + output div_by_zero; + */ + output [7:0] control; + /* + parameter INF = 31'h7f800000; + parameter QNAN = 31'h7fc00001; + parameter SNAN = 31'h7f800001; + + */ + + wire [30:0] INF; + assign INF = 31'h7f800000; + wire [30:0] QNAN; + assign QNAN = 31'h7fc00001; + wire [30:0] SNAN; + assign SNAN = 31'h7f800001; + + //////////////////////////////////////////////////////////////////////// + // + // Local Wires + // + reg [2:0] fpu_op; + reg zero; + reg [31:0] opa_r, opb_r; // Input operand registers + reg [31:0] out; // Output register + reg div_by_zero; // Divide by zero output register + // wire signa, signb; // alias to opX sign + wire sign_fasu; // sign output + wire [26:0] fracta, fractb; // Fraction Outputs from EQU block + wire [7:0] exp_fasu; // Exponent output from EQU block + reg [7:0] exp_r; // Exponent output (registerd) + wire [26:0] fract_out_d; // fraction output + // wire co; // carry output + reg [27:0] fract_out_q; // fraction output (registerd) + wire [30:0] out_d; // Intermediate final result output + wire overflow_d, underflow_d;// Overflow/Underflow Indicators + reg overflow, underflow; // Output registers for Overflow & Underflow + reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN + reg ine; // Output Registers for INE + reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode + rmode_r3; + reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration + fpu_op_r3; + // wire mul_inf, div_inf; + // wire mul_00, div_00; + + + // start output_reg + reg [31:0] out_o1; + reg inf_o1, snan_o1, qnan_o1; + reg ine_o1; + reg overflow_o1, underflow_o1; + reg zero_o1; + reg div_by_zero_o1; + // end output_reg + wire [7:0] contorl; + assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero}; + wire [1:0] rmode; + assign rmode= 2'b00; + + + always@(posedge clk) + begin + fpu_op[2:0] <= 3'b000; + end + //////////////////////////////////////////////////////////////////////// + // + // Input Registers + // + + always @(posedge clk) + opa_r <= opa; + + always @(posedge clk) + opb_r <= opb; + + always @(posedge clk) + rmode_r1 <= rmode; + + always @(posedge clk) + rmode_r2 <= rmode_r1; + + always @(posedge clk) + rmode_r3 <= rmode_r2; + + always @(posedge clk) + fpu_op_r1 <= fpu_op; + + always @(posedge clk) + fpu_op_r2 <= fpu_op_r1; + + always @(posedge clk) + fpu_op_r3 <= fpu_op_r2; + + //////////////////////////////////////////////////////////////////////// + // + // Exceptions block + // + wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; + wire opa_00, opb_00; + wire opa_inf, opb_inf; + wire opa_dn, opb_dn; + + except u0( .clk(clk), + .opa(opa_r), .opb(opb_r), + .inf(inf_d), .ind(ind_d), + .qnan(qnan_d), .snan(snan_d), + .opa_nan(opa_nan), .opb_nan(opb_nan), + .opa_00(opa_00), .opb_00(opb_00), + .opa_inf(opa_inf), .opb_inf(opb_inf), + .opa_dn(opa_dn), .opb_dn(opb_dn) + ); + + //////////////////////////////////////////////////////////////////////// + // + // Pre-Normalize block + // - Adjusts the numbers to equal exponents and sorts them + // - determine result sign + // - determine actual operation to perform (add or sub) + // + + wire nan_sign_d, result_zero_sign_d; + reg sign_fasu_r; + wire fasu_op; + + wire add_input; + assign add_input=!fpu_op_r1[0]; + pre_norm u1(.clk(clk), // System Clock + .rmode(rmode_r2), // Roundin Mode + // .add(!fpu_op_r1[0]), // Add/Sub Input + .add(add_input), + .opa(opa_r), .opb(opb_r), // Registered OP Inputs + .opa_nan(opa_nan), // OpA is a NAN indicator + .opb_nan(opb_nan), // OpB is a NAN indicator + .fracta_out(fracta), // Equalized and sorted fraction + .fractb_out(fractb), // outputs (Registered) + .exp_dn_out(exp_fasu), // Selected exponent output (registered); + .sign(sign_fasu), // Encoded output Sign (registered) + .nan_sign(nan_sign_d), // Output Sign for NANs (registered) + .result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered) + .fasu_op(fasu_op) // Actual fasu operation output (registered) + ); + + always @(posedge clk) + sign_fasu_r <= sign_fasu; + + wire co_d; + //////////////////////////////////////////////////////////////////////// + // + // Add/Sub + // + + add_sub27 u3( + .add(fasu_op), // Add/Sub + .opa(fracta), // Fraction A input + .opb(fractb), // Fraction B Input + .sum(fract_out_d), // SUM output + .co(co_d) ); // Carry Output + + always @(posedge clk) + fract_out_q <= {co_d, fract_out_d}; + + + //////////////////////////////////////////////////////////////////////// + // + // Normalize Result + // + wire ine_d; + //reg [47:0] fract_denorm; + wire [47:0] fract_denorm; + + wire sign_d; + reg sign; + reg [30:0] opa_r1; + reg [47:0] fract_i2f; + reg opas_r1, opas_r2; + wire f2i_out_sign; + + always @(posedge clk) // Exponent must be once cycle delayed + exp_r <= exp_fasu; + + + always @(posedge clk) + opa_r1 <= opa_r[30:0]; + + //always @(fpu_op_r3 or fract_out_q) + assign fract_denorm = {fract_out_q, 20'h0}; + + + always @(posedge clk) + opas_r1 <= opa_r[31]; + + always @(posedge clk) + opas_r2 <= opas_r1; + + assign sign_d = sign_fasu; + + always @(posedge clk) + sign <= (rmode_r2==2'h3) ? !sign_d : sign_d; + + post_norm u4( + //.clk(clk), // System Clock + .fpu_op(fpu_op_r3), // Floating Point Operation + .opas(opas_r2), // OPA Sign + .sign(sign), // Sign of the result + .rmode(rmode_r3), // Rounding mode + .fract_in(fract_denorm), // Fraction Input + .exp_in(exp_r), // Exponent Input + .exp_ovf(2'b00), // Exponent Overflow + .opa_dn(opa_dn), // Operand A Denormalized + .opb_dn(opb_dn), // Operand A Denormalized + .rem_00(1'b0), // Diveide Remainder is zero + .div_opa_ldz(5'b00000), // Divide opa leading zeros count + .output_zero(1'b0), // Force output to Zero + .out(out_d), // Normalized output (un-registered) + .ine(ine_d), // Result Inexact output (un-registered) + .overflow(overflow_d), // Overflow output (un-registered) + .underflow(underflow_d), // Underflow output (un-registered) + .f2i_out_sign(f2i_out_sign) // F2I Output Sign + ); + + //////////////////////////////////////////////////////////////////////// + // + // FPU Outputs + // + reg fasu_op_r1, fasu_op_r2; + wire [30:0] out_fixed; + wire output_zero_fasu; + wire overflow_fasu; + wire out_d_00; + wire ine_fasu; + wire underflow_fasu; + reg opa_nan_r; + + + always @(posedge clk) + fasu_op_r1 <= fasu_op; + + always @(posedge clk) + fasu_op_r2 <= fasu_op_r1; + + + // Force pre-set values for non numerical output + + assign out_fixed = ( (qnan_d | snan_d) | + (ind_d & !fasu_op_r2) ) ? QNAN : INF; + + always @(posedge clk) + out_o1[30:0] <= (inf_d | snan_d | qnan_d) ? out_fixed : out_d; + + + assign out_d_00 = !(|out_d); + + always @(posedge clk) + out_o1[31] <= (snan_d | qnan_d | ind_d) ? nan_sign_d : + output_zero_fasu ? result_zero_sign_d : + sign_fasu_r; + + assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d); + + always @(posedge clk) + ine_o1 <= ine_fasu ; + + + assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d); + + always @(posedge clk) + overflow_o1 <= overflow_fasu ; + + assign underflow_fasu = underflow_d & !(inf_d | snan_d | qnan_d); + + always @(posedge clk) + underflow_o1 <= underflow_fasu ; + + always @(posedge clk) + snan_o1 <= snan_d; + + + + // Status Outputs + always @(posedge clk) + qnan_o1 <= ( snan_d | qnan_d | (ind_d & !fasu_op_r2) ); + + always @(posedge clk) + inf_o1 <= (!(qnan_d | snan_d) & (( (&out_d[30:23]) & !(|out_d[22:0] ) ) | (inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) )); + + assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d); + + always @(posedge clk) + zero_o1 <= output_zero_fasu ; + + always @(posedge clk) + opa_nan_r <= !opa_nan & fpu_op_r2==3'b011; + + always @(posedge clk) + div_by_zero_o1 <= 1'b0; + + // output register + always @(posedge clk) + begin + qnan <= qnan_o1; + out <= out_o1; + inf <= inf_o1; + snan <= snan_o1; + //qnan <= qnan_o1; + ine <= ine_o1; + overflow <= overflow_o1; + underflow <= underflow_o1; + zero <= zero_o1; + div_by_zero <= div_by_zero_o1; + end + +endmodule + + + + +//--------------------------------------------------------------------------------- +module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out, + fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign, + fasu_op); +input clk; +input [1:0] rmode; +input add; +input [31:0] opa, opb; +input opa_nan, opb_nan; +output [26:0] fracta_out, fractb_out; +output [7:0] exp_dn_out; +output sign; +output nan_sign, result_zero_sign; +output fasu_op; // Operation Output + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire signa, signb; // alias to opX sign +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +wire expa_lt_expb; // expa is larger than expb indicator +wire fractb_lt_fracta; // fractb is larger than fracta indicator +reg [7:0] exp_dn_out; // de normalized exponent output +wire [7:0] exp_small, exp_large; +wire [7:0] exp_diff; // Numeric difference of the two exponents +wire [22:0] adj_op; // Fraction adjustment: input +wire [26:0] adj_op_tmp; +wire [26:0] adj_op_out; // Fraction adjustment: output +wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing +wire [26:0] fracta_s, fractb_s; // Fraction Sorting out +reg [26:0] fracta_out, fractb_out; // Fraction Output +reg sign, sign_d; // Sign Output +reg add_d; // operation (add/sub) +reg fasu_op; // operation (add/sub) register +wire expa_dn, expb_dn; +reg sticky; +reg result_zero_sign; +reg add_r, signa_r, signb_r; +wire [4:0] exp_diff_sft; +wire exp_lt_27; +wire op_dn; +wire [26:0] adj_op_out_sft; +reg fracta_lt_fractb, fracta_eq_fractb; +wire nan_sign1; +reg nan_sign; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize exponents (and fractions) +// + +assign expa_lt_expb = expa > expb; // expa is larger than expb + +// --------------------------------------------------------------------- +// Normalize + +assign expa_dn = !(|expa); // opa denormalized +assign expb_dn = !(|expb); // opb denormalized + +// --------------------------------------------------------------------- +// Calculate the difference between the smaller and larger exponent + +wire [7:0] exp_diff1, exp_diff1a, exp_diff2; + +assign exp_small = expa_lt_expb ? expb : expa; +assign exp_large = expa_lt_expb ? expa : expb; +assign exp_diff1 = exp_large - exp_small; +assign exp_diff1a = exp_diff1-8'h01; +assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1; +assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2; + +always @(posedge clk) // If numbers are equal we should return zero + exp_dn_out <= (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large; + +// --------------------------------------------------------------------- +// Adjust the smaller fraction + + +assign op_dn = expa_lt_expb ? expb_dn : expa_dn; +assign adj_op = expa_lt_expb ? fractb : fracta; +wire temp1; +assign temp1 = ~op_dn; +//assign adj_op_tmp[26:0] = {~op_dn, adj_op, 3'b000}; // recover hidden bit (op_dn) +assign adj_op_tmp[26:0] = {temp1, adj_op, 3'b000}; // recover hidden bit (op_dn) + +// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right +assign exp_lt_27 = exp_diff > 8'd27; +assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0]; + +//assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft; +b_right_shifter_new u7( + .shift_in(adj_op_tmp), + .shift_value(exp_diff_sft), + .shift_out(adj_op_out_sft) +); + +wire temp2; +assign temp2 = adj_op_out_sft[0] | sticky; +//assign adj_op_out[26:0] = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky }; +assign adj_op_out[26:0] = {adj_op_out_sft[26:1], temp2 }; + + +// --------------------------------------------------------------------- +// Get truncated portion (sticky bit) + +always @(exp_diff_sft or adj_op_tmp) + case(exp_diff_sft) // synopsys full_case parallel_case + 5'd00: sticky = 1'h0; + 5'd01: sticky = adj_op_tmp[0]; + 5'd02: sticky = |adj_op_tmp[01:0]; + 5'd03: sticky = |adj_op_tmp[02:0]; + 5'd04: sticky = |adj_op_tmp[03:0]; + 5'd05: sticky = |adj_op_tmp[04:0]; + 5'd06: sticky = |adj_op_tmp[05:0]; + 5'd07: sticky = |adj_op_tmp[06:0]; + 5'd08: sticky = |adj_op_tmp[07:0]; + 5'd09: sticky = |adj_op_tmp[08:0]; + 5'd10: sticky = |adj_op_tmp[09:0]; + 5'd11: sticky = |adj_op_tmp[10:0]; + 5'd12: sticky = |adj_op_tmp[11:0]; + 5'd13: sticky = |adj_op_tmp[12:0]; + 5'd14: sticky = |adj_op_tmp[13:0]; + 5'd15: sticky = |adj_op_tmp[14:0]; + 5'd16: sticky = |adj_op_tmp[15:0]; + 5'd17: sticky = |adj_op_tmp[16:0]; + 5'd18: sticky = |adj_op_tmp[17:0]; + 5'd19: sticky = |adj_op_tmp[18:0]; + 5'd20: sticky = |adj_op_tmp[19:0]; + 5'd21: sticky = |adj_op_tmp[20:0]; + 5'd22: sticky = |adj_op_tmp[21:0]; + 5'd23: sticky = |adj_op_tmp[22:0]; + 5'd24: sticky = |adj_op_tmp[23:0]; + 5'd25: sticky = |adj_op_tmp[24:0]; + 5'd26: sticky = |adj_op_tmp[25:0]; + 5'd27: sticky = |adj_op_tmp[26:0]; + endcase + +// --------------------------------------------------------------------- +// Select operands for add/sub (recover hidden bit) + +assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out; +assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0}; + +// --------------------------------------------------------------------- +// Sort operands (for sub only) + +assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta +assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n; +assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n; + +always @(posedge clk) + fracta_out <= fracta_s; + +always @(posedge clk) + fractb_out <= fractb_s; + +// --------------------------------------------------------------------- +// Determine sign for the output + +// sign: 0=Positive Number; 1=Negative Number +always @(signa or signb or add or fractb_lt_fracta) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b001: sign_d = 0; + 3'b011: sign_d = fractb_lt_fracta; + 3'b101: sign_d = !fractb_lt_fracta; + 3'b111: sign_d = 1; + + // Sub + 3'b000: sign_d = fractb_lt_fracta; + 3'b010: sign_d = 0; + 3'b100: sign_d = 1; + 3'b110: sign_d = !fractb_lt_fracta; + endcase + +always @(posedge clk) + sign <= sign_d; + +// Fix sign for ZERO result +always @(posedge clk) + signa_r <= signa; + +always @(posedge clk) + signb_r <= signb; + +always @(posedge clk) + add_r <= add; + +always @(posedge clk) + result_zero_sign <= ( add_r & signa_r & signb_r) | + (!add_r & signa_r & !signb_r) | + ( add_r & (signa_r | signb_r) & (rmode==3)) | + (!add_r & (signa_r == signb_r) & (rmode==3)); + +// Fix sign for NAN result +always @(posedge clk) + fracta_lt_fractb <= fracta < fractb; + +always @(posedge clk) + fracta_eq_fractb <= fracta == fractb; + +assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r; + +always @(posedge clk) + nan_sign <= (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r; + +//////////////////////////////////////////////////////////////////////// +// +// Decode Add/Sub operation +// + +// add: 1=Add; 0=Subtract +always @(signa or signb or add) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b001: add_d = 1; + 3'b011: add_d = 0; + 3'b101: add_d = 0; + 3'b111: add_d = 1; + + // Sub + 3'b000: add_d = 0; + 3'b010: add_d = 1; + 3'b100: add_d = 1; + 3'b110: add_d = 0; + endcase + +always @(posedge clk) + fasu_op <= add_d; + +endmodule + +module b_right_shifter_new ( + shift_in, + shift_value, + shift_out +); + +input [26:0] shift_in; +input [4:0] shift_value; +output [26:0] shift_out; +reg [26:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 5'b00000: shift_out = shift_in; + 5'b00001: shift_out = shift_in >> 1; + 5'b00010: shift_out = shift_in >> 2; + 5'b00011: shift_out = shift_in >> 3; + 5'b00100: shift_out = shift_in >> 4; + 5'b00101: shift_out = shift_in >> 5; + 5'b00110: shift_out = shift_in >> 6; + 5'b00111: shift_out = shift_in >> 7; + 5'b01000: shift_out = shift_in >> 8; + 5'b01001: shift_out = shift_in >> 9; + 5'b01010: shift_out = shift_in >> 10; + 5'b01011: shift_out = shift_in >> 11; + 5'b01100: shift_out = shift_in >> 12; + 5'b01101: shift_out = shift_in >> 13; + 5'b01110: shift_out = shift_in >> 14; + 5'b01111: shift_out = shift_in >> 15; + 5'b10000: shift_out = shift_in >> 16; + 5'b10001: shift_out = shift_in >> 17; + 5'b10010: shift_out = shift_in >> 18; + 5'b10011: shift_out = shift_in >> 19; + 5'b10100: shift_out = shift_in >> 20; + 5'b10101: shift_out = shift_in >> 21; + 5'b10110: shift_out = shift_in >> 22; + 5'b10111: shift_out = shift_in >> 23; + 5'b11000: shift_out = shift_in >> 24; + 5'b11001: shift_out = shift_in >> 25; + 5'b11010: shift_out = shift_in >> 26; + 5'b11011: shift_out = shift_in >> 27; + endcase +end + + +endmodule + +//---------------------------------------------------------------------------- + + + +//////////////////////////////////////////////////////////////////////// +// +// Add/Sub +// + +module add_sub27(add, opa, opb, sum, co); +input add; +input [26:0] opa, opb; +output [26:0] sum; +output co; + + + +assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb}); + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v b/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v new file mode 100755 index 000000000..e7b836533 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v @@ -0,0 +1,1617 @@ +//************************************************************************** +// author: Alexander Bochem +// date: 07.05.2010 +//************************************************************************** +//input: RLE encoded pixel data +//output: blob attributes merged with bounding box criteria +// +//description: +// - read RLE encoded pixel data from input fifo +// - merge Runs based on bounding box criteria +// - write Blobs attributes to output fifo +//************************************************************************** +//change: 13.05.2010 +// condition checks in state CHECK_PIXEL implemented to merge adjacent +// runs into BLOB containers +// +// 15.05.2010 +// included BLOB_RANGE and CONT_RANGE for adjacency check +// eliminates multiple detection of BLOBs +// +// 26.05.2010 +// extended to detect up to six BLOBs +// +// 27.05.2010 +// add average X and Y edge to output for +// threshold adjustment +// +// 29.05.2010 +// include collecting data for center of mass method in RLE merging process +// change module name to RLE_BlobMerging +// +// 31.05.2010 +// include computation for center of mass +//************************************************************************** + +`define LSB_X 1'b0 +`define MSB_X 4'b1010 +`define LSB_Y 4'b1011 +`define MSB_Y 5'b10101 +`define LSB_RunLength 5'b10110 +`define MSB_RunLength 5'b11111 +`define LSB_RunSumValues 6'b100000 +`define MSB_RunSumValues 6'b11111 +`define LSB_RunSumXpositions 7'b1000000 +`define MSB_RunSumXpositions 7'b1011111 +`define LSB_RunSumYpositions 7'b1100000 +`define MSB_RunSumYpositions 7'b1111111 +`define LSB_EOFflag 1'b0 +`define MSB_EOFflag 5'b11111 +`define CONT_RANGE 5'b01010 +`define BLOB_RANGE 5'b01010 + + +`define FALSE 1'b0 +`define TRUE 1'b1 +`define INIT 5'b00000 +`define IDLE 5'b00001 +`define CHECK_CONDITIONS 5'b00010 +`define WRITE_FIFO 5'b00011 +`define WAIT_FIFO 5'b00100 +`define COMPUTE_CENTER 5'b00101 +`define VALIDATE_CHECK_ADJACENT_CONTAINER 5'b00110 +`define READ_FIFO 5'b00111 +`define CONFIG_WRITE 5'b01000 +`define WRITE_WAIT 5'b01001 +`define SELECT_EMPTY_CONTAINER 5'b01010 +`define CHECK_ADJACENT_CONTAINTER 5'b01011 +`define CHECK_CONT_ADJACENCY 5'b01100 +`define MERGE_CONTAINER 5'b01101 +`define WRITE_BLOB_0 4'b0000 +`define WRITE_BLOB_1 4'b0001 +`define WRITE_BLOB_2 4'b0010 +`define WRITE_BLOB_3 4'b0011 +`define WRITE_BLOB_4 4'b0100 +`define WRITE_BLOB_5 4'b0101 +`define EOF 32'b00000000000000000000000000000000 +`define MERGE_CONT_1_2 5'b01110 +`define MERGE_CONT_1_3 5'b01111 +`define MERGE_CONT_1_4 5'b10000 +`define MERGE_CONT_1_5 5'b10001 +`define MERGE_CONT_2_3 5'b10010 +`define MERGE_CONT_2_4 5'b10011 +`define MERGE_CONT_2_5 5'b10100 +`define MERGE_CONT_3_4 5'b10101 +`define MERGE_CONT_3_5 5'b10110 +`define MERGE_CONT_4_5 5'b10111 +`define MERGE_CONT_1_6 5'b11000 +`define MERGE_CONT_2_6 5'b11001 +`define MERGE_CONT_3_6 5'b11010 +`define MERGE_CONT_4_6 5'b11011 +`define MERGE_CONT_5_6 5'b11100 + + + +module RLE_BlobMerging(clk, +//iCOMclock, + iReset, + iReadFifoEmpty, + iReadFifoData, + iWriteFifoFull, + oReadFifoRequest, + oWriteBlobData, + oWriteRequest, + oAvgSizeXaxis, + oAvgSizeYaxis +); + + input clk; //module clock + //input iCOMclock; //clock for COM sub-module + input iReset; //module reset signal + input iReadFifoEmpty; //fifo empty signal from input fifo + input [127:0]iReadFifoData; //data bus from input fifo [32b y-w., 32b x-w., 32 pixel-w.,10b length, 11b Y, 11b X] + input iWriteFifoFull; //fifo full signal from output fifo + + output oReadFifoRequest; //read request to input fifo + output [75:0]oWriteBlobData; //data bus to output fifo [10b index, 11b bb y, 11b bb x, 11b com y, 11b com x, 11b len y, 11b len x] + output oWriteRequest; //write request to output fifo + output [10:0] oAvgSizeXaxis; //average size of X axis for detected BLOBs + output [10:0] oAvgSizeYaxis; //average size of Y axis for detected BLOBs + + reg oReadFifoRequest; //read request to input fifo + reg [75:0]oWriteBlobData; //data bus to output fifo [10b index, 11b bb y, 11b bb x, 11b com y, 11b com x, 11b len y, 11b len x] + reg oWriteRequest; //write request to output fifo + reg [10:0] oAvgSizeXaxis; //average size of X axis for detected BLOBs + reg [10:0] oAvgSizeYaxis; //average size of Y axis for detected BLOBs + +/* +parameter LSB_X=0, MSB_X=10; //start and end bit for x coordiante +parameter LSB_Y=11, MSB_Y=21; //start and end bit for y coordiante +parameter LSB_RunLength=22, MSB_RunLength=31; //start and end bit for RUN length +parameter LSB_RunSumValues=32, MSB_RunSumValues=63; +parameter LSB_RunSumXpositions=64, MSB_RunSumXpositions=95; +parameter LSB_RunSumYpositions=96, MSB_RunSumYpositions=127; +parameter LSB_EOFflag=0, MSB_EOFflag=31;//start and end bit for EOF flag +parameter CONT_RANGE = 5'd10; +parameter BLOB_RANGE = 5'd10; +parameter MIN_X=11'd0, MAX_X=11'd640, MIN_Y=11'd0, MAX_Y=11'd480; +parameter COM_DELAY_TIME=3'd5; +*/ + +//internal registers +reg [17:0] checkResult; //each flage represents one result of conditional checks +reg [9:0] run_length; //temporary store the length of a detected run +reg [10:0] run_start_x; //temporary store starting X position of run +reg [10:0] run_start_y; //temporary store starting Y position of run +reg [31:0] run_sum_x_positions; //temporary store weighted sum of x positions in run +reg [31:0] run_sum_y_positions; //temporary store weighted sum of y postions in run +reg [31:0] run_sum_values; //temporary store sum of weights in run +reg [3:0] write_result_pointer; +reg [4:0] state; +reg RunAdded; +reg [14:0] ContainerAdjacentResult; +reg [3:0] countDetectedBlobs; +reg [10:0] avgSizeXaxis; +reg [10:0] avgSizeYaxis; +reg enableCOMcomputation; //flag enables sub-modules for center point computation with COM +reg [3:0] delayCounterCOM; //counts up to COM_DELAY_TIME to allow sub-module finish computation + +//BLOB containers +//CONTAINER 1 +reg[10:0] blob1minX, blob1minY, blob1maxX, blob1maxY; //bounding box attributes +reg [10:0] blob1X_bb_center, blob1Y_bb_center; //center points for bounding box attributes +reg [35:0] blob1X_com_center, blob1Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_1; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_1; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_1; //number of pixels belonging to BLOB +reg blob1empty; //flag information if container is empty + +//CONTAINER 2 +reg[10:0] blob2minX, blob2minY, blob2maxX, blob2maxY; //bounding box attributes +reg [10:0] blob2X_bb_center, blob2Y_bb_center; //center points for bounding box attributes +reg [35:0] blob2X_com_center, blob2Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_2; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_2; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_2; //number of pixels belonging to BLOB +reg blob2empty; //flag information if container is empty + +//CONTAINER 3 +reg[10:0] blob3minX, blob3minY, blob3maxX, blob3maxY; //bounding box attributes +reg [10:0] blob3X_bb_center, blob3Y_bb_center; //center points for bounding box attributes +reg [35:0] blob3X_com_center, blob3Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_3; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_3; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_3; //number of pixels belonging to BLOB +reg blob3empty; //flag information if container is empty + +//CONTAINER 4 +reg[10:0] blob4minX, blob4minY, blob4maxX, blob4maxY; //bounding box attributes +reg [10:0] blob4X_bb_center, blob4Y_bb_center; //center points for bounding box attributes +reg [35:0] blob4X_com_center, blob4Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_4; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_4; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_4; //number of pixels belonging to BLOB +reg blob4empty; //flag information if container is empty + +//CONTAINER 5 +reg[10:0] blob5minX, blob5minY, blob5maxX, blob5maxY; //bounding box attributes +reg [10:0] blob5X_bb_center, blob5Y_bb_center; //center points for bounding box attributes +reg [35:0] blob5X_com_center, blob5Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_5; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_5; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_5; //number of pixels belonging to BLOB +reg blob5empty; //flag information if container is empty + +//CONTAINER 6 +reg[10:0] blob6minX, blob6minY, blob6maxX, blob6maxY; //bounding box attributes +reg [10:0] blob6X_bb_center, blob6Y_bb_center; //center points for bounding box attributes +reg [35:0] blob6X_com_center, blob6Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_6; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_6; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_6; //number of pixels belonging to BLOB +reg blob6empty; //flag information if container is empty + +//divider varaible + +//reg [49:0]divider_res_x; +wire [10:0]divider_res_x; +//reg [49:0]divider_rem_x; +wire [10:0]divider_rem_x; + +wire [10:0]divider_res_y; +//reg [49:0]divider_res_y; +wire [10:0]divider_rem_y; +//reg [49:0]divider_rem_y; + +wire [10:0] ex_avgSizeXaxis; +//reg [49:0] ex_avgSizeXaxis; +assign ex_avgSizeXaxis = avgSizeXaxis; + +wire [10:0]ex_avgSizeYaxis; +//reg [49:0]ex_avgSizeYaxis; +assign ex_avgSizeYaxis = avgSizeYaxis; + + +wire [3:0]ex_countDetectedBlobs; +//reg [49:0]ex_countDetectedBlobs; +assign ex_countDetectedBlobs = countDetectedBlobs; +//implement the divider +divider inst_x ( + .opa(ex_avgSizeXaxis), + .opb(ex_countDetectedBlobs), + .quo(divider_res_x), + .rem(divider_rem_x)); + +divider inst_y ( + .opa(ex_avgSizeYaxis), + .opb(ex_countDetectedBlobs), + .quo(divider_res_y), + .rem(divider_rem_y)); + +//read RLE encoded pixel data from input fifo and merge adjacent runs to blobs +//compute blobs center points, on EOF flag +//store center points to output fifo, if EOF flag is read from Fifo +always@(posedge clk) begin + + //reset internal registers on reset signal + if(iReset) begin + state <= `INIT; + end + else begin + //module state machine + case(state) + + //intialize internal register + `INIT: begin + checkResult <= 18'b000000000000000000; + run_length <= 10'b0000000000; + run_start_x <= 11'b00000000000; + run_start_y <= 11'b00000000000; + + RunAdded <= `FALSE; + + //set defaults for CONTAINER 1 + blob1maxX <= 11'b00000000000; + blob1minX <= 11'b00000000000; + blob1maxY <= 11'b00000000000; + blob1minY <= 11'b00000000000; +// sumBLOB_Xpositions_1=0; +// sumBLOB_Ypositions_1=0; +// sumBLOB_Pixels_1=0; + blob1empty <= `TRUE; + + //set defaults for CONTAINER 2 + blob2maxX <= 11'b00000000000; + blob2minX <= 11'b00000000000; + blob2maxY <= 11'b00000000000; + blob2minY <= 11'b00000000000; +// sumBLOB_Xpositions_2=0; +// sumBLOB_Ypositions_2=0; +// sumBLOB_Pixels_2=0; + blob2empty <= `TRUE; + + //set defaults for CONTAINER 3 + blob3maxX <= 11'b00000000000; + blob3minX <= 11'b00000000000; + blob3maxY <= 11'b00000000000; + blob3minY <= 11'b00000000000; +// sumBLOB_Xpositions_3=0; +// sumBLOB_Ypositions_3=0; +// sumBLOB_Pixels_3=0; + blob3empty <= `TRUE; + + //set defaults for CONTAINER 4 + blob4maxX <= 11'b00000000000; + blob4minX <= 11'b00000000000; + blob4maxY <= 11'b00000000000; + blob4minY <= 11'b00000000000; +// sumBLOB_Xpositions_4=0; +// sumBLOB_Ypositions_4=0; +// sumBLOB_Pixels_4=0; + blob4empty <= `TRUE; + + + //set defaults for CONTAINER 5 + blob5maxX <= 11'b00000000000; + blob5minX <= 11'b00000000000; + blob5maxY <= 11'b00000000000; + blob5minY <= 11'b00000000000; +// sumBLOB_Xpositions_5=0; +// sumBLOB_Ypositions_5=0; +// sumBLOB_Pixels_5=0; + blob5empty <= `TRUE; + + //set defaults for CONTAINER 6 + blob6maxX <= 11'b00000000000; + blob6minX <= 11'b00000000000; + blob6maxY <= 11'b00000000000; + blob6minY <= 11'b00000000000; +// sumBLOB_Xpositions_6<=0; +// sumBLOB_Ypositions_6<=0; +// sumBLOB_Pixels_6<=0; + blob6empty <= `TRUE; + + + blob1X_com_center <= 35'b00000000000000000000000000000000000; + blob1Y_com_center <= 35'b00000000000000000000000000000000000; + blob2X_com_center <= 35'b00000000000000000000000000000000000; + blob2Y_com_center <= 35'b00000000000000000000000000000000000; + blob3X_com_center <= 35'b00000000000000000000000000000000000; + blob3Y_com_center <= 35'b00000000000000000000000000000000000; + blob4X_com_center <= 35'b00000000000000000000000000000000000; + blob4Y_com_center <= 35'b00000000000000000000000000000000000; + blob5X_com_center <= 35'b00000000000000000000000000000000000; + blob5Y_com_center <= 35'b00000000000000000000000000000000000; + blob6X_com_center <= 35'b00000000000000000000000000000000000; + blob6Y_com_center <= 35'b00000000000000000000000000000000000; + //blob4X_com_center + //blob4X_com_center + + + avgSizeXaxis<=11'b00000000000; + avgSizeYaxis<=11'b00000000000; + countDetectedBlobs<=4'b0000; + enableCOMcomputation<=`FALSE; + + state <= `IDLE; + end + + //read run data from input fifo + `IDLE: begin + if(!iReadFifoEmpty) begin + oReadFifoRequest <= `TRUE; + state <= `READ_FIFO; + end + else begin + state <= `IDLE; + end + end + + //receive data from input fifo + `READ_FIFO: begin + oReadFifoRequest <= `FALSE; + + //check for EOF flag + if(iReadFifoData[`MSB_EOFflag:`LSB_EOFflag]==`EOF)begin + write_result_pointer<=4'b0000; + + //start center point computation for COM + enableCOMcomputation<=`TRUE; + delayCounterCOM<=4'b0000; //reset delay time counter + + state <= `COMPUTE_CENTER; + end + else begin + run_length <= iReadFifoData[31:22]; + run_start_x <= iReadFifoData[10:0]; + run_start_y <= iReadFifoData[21:11]; + run_sum_x_positions <= iReadFifoData[95:64]; + run_sum_y_positions <= iReadFifoData[127:96]; + run_sum_values <= iReadFifoData[63:32]; + checkResult <= 18'b000000000000000000; + RunAdded <= `FALSE; + state <= `CHECK_CONDITIONS; + end + end + + //perform condition checks + `CHECK_CONDITIONS: begin + + //check which BLOB containers are empty + checkResult[0] <= blob1empty; + checkResult[3] <= blob2empty; + checkResult[6] <= blob3empty; + checkResult[9] <= blob4empty; + checkResult[12] <= blob5empty; + checkResult[15] <= blob6empty; + + + //check if run is adjacent on X values to blob 1 container + if( (((run_start_x+`BLOB_RANGE) >= blob1minX) & (run_start_x <= (blob1maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob1minX) & ((run_start_x+run_length) <= (blob1maxX+`BLOB_RANGE)) ) begin + checkResult[1] <= `TRUE; + end + //check if run is adjacent on X values to blob 2 container +// if( ((run_start_x+`BLOB_RANGE) >= blob2minX) & (run_start_x <= blob2maxX) & +// ((run_start_x+run_length) >= blob2minX) & ((run_start_x+run_length) <= (blob2maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob2minX) & (run_start_x <= (blob2maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob2minX) & ((run_start_x+run_length) <= (blob2maxX+`BLOB_RANGE)) ) begin + checkResult[4] <= `TRUE; + end + //check if run is adjacent on X values to blob 3 container +// if( ((run_start_x+`BLOB_RANGE) >= blob3minX) & (run_start_x <= blob3maxX) & +// ((run_start_x+run_length) >= blob3minX) & ((run_start_x+run_length) <= (blob3maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob3minX) & (run_start_x <= (blob3maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob3minX) & ((run_start_x+run_length) <= (blob3maxX+`BLOB_RANGE)) ) begin + checkResult[7] <= `TRUE; + end + //check if run is adjacent on X values to blob 4 container +// if( ((run_start_x+`BLOB_RANGE) >= blob4minX) & (run_start_x <= blob4maxX) & +// ((run_start_x+run_length) >= blob4minX) & ((run_start_x+run_length) <= (blob4maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob4minX) & (run_start_x <= (blob4maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob4minX) & ((run_start_x+run_length) <= (blob4maxX+`BLOB_RANGE)) ) begin + checkResult[10] <= `TRUE; + end + //check if run is adjacent on X values to blob 5 container +// if( ((run_start_x+`BLOB_RANGE) >= blob5minX) & (run_start_x <= blob5maxX) & +// ((run_start_x+run_length) >= blob5minX) & ((run_start_x+run_length) <= (blob5maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob5minX) & (run_start_x <= (blob5maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob5minX) & ((run_start_x+run_length) <= (blob5maxX+`BLOB_RANGE)) ) begin + checkResult[13] <= `TRUE; + end + + //check if run is adjacent on X values to blob 6 container + if( (((run_start_x+`BLOB_RANGE) >= blob6minX) & (run_start_x <= (blob6maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob6minX) & ((run_start_x+run_length) <= (blob6maxX+`BLOB_RANGE)) ) begin + checkResult[16] <= `TRUE; + end + + //check if run is adjacent on Y values to blob 1 container + if( (run_start_y == (blob1maxY +1)) || (run_start_y == blob1maxY) ) begin + checkResult[2] <= `TRUE; + end + //check if run is adjacent on Y values to blob 2 container + if( (run_start_y == (blob2maxY +1)) || (run_start_y == blob2maxY) ) begin + checkResult[5] <= `TRUE; + end + //check if run is adjacent on Y values to blob 3 container + if( (run_start_y == (blob3maxY +1)) || (run_start_y == blob3maxY) ) begin + checkResult[8] <= `TRUE; + end + //check if run is adjacent on Y values to blob 4 container + if( (run_start_y == (blob4maxY +1)) || (run_start_y == blob4maxY) ) begin + checkResult[11] <= `TRUE; + end + //check if run is adjacent on Y values to blob 5 container + if( (run_start_y == (blob5maxY +1)) || (run_start_y == blob5maxY) ) begin + checkResult[14] <= `TRUE; + end + //check if run is adjacent on Y values to blob 5 container + if( (run_start_y == (blob6maxY +1)) || (run_start_y == blob6maxY) ) begin + checkResult[17] <= `TRUE; + end + + state <= `CHECK_ADJACENT_CONTAINTER; + end + + //validate results from condition check for adjacency + `CHECK_ADJACENT_CONTAINTER: begin + + if( + ((~checkResult[0])&checkResult[1]&checkResult[2]) + || ((~checkResult[3])&checkResult[4]&checkResult[5]) + || ((~checkResult[6])&checkResult[7]&checkResult[8]) + || ((~checkResult[9])&checkResult[10]&checkResult[11]) + || ((~checkResult[12])&checkResult[13]&checkResult[14]) + || ((~checkResult[15])&checkResult[16]&checkResult[17]) + ) + begin + RunAdded <= `TRUE; + end + + //run adjacent to container 1 + if( (~checkResult[0])&checkResult[1]&checkResult[2] ) + begin + if(run_start_x < blob1minX) blob1minX <= run_start_x; + if((run_start_x+run_length) > blob1maxX) blob1maxX <= (run_start_x+run_length); + if(blob1maxY < run_start_y) blob1maxY <= run_start_y; + end + + //run adjacent to container 2 + if( (~checkResult[3])&checkResult[4]&checkResult[5] ) + begin + if(run_start_x < blob2minX) blob2minX <= run_start_x; + if((run_start_x+run_length) > blob2maxX) blob2maxX <= (run_start_x+run_length); + if(blob2maxY < run_start_y) blob2maxY <= run_start_y; + end + + //run adjacent to container 3 + if( (~checkResult[6])&checkResult[7]&checkResult[8] ) + begin + if(run_start_x < blob3minX) blob3minX <= run_start_x; + if((run_start_x+run_length) > blob3maxX) blob3maxX <= (run_start_x+run_length); + if(blob3maxY < run_start_y) blob3maxY <= run_start_y; + end + + //run adjacent to container 4 + if( (~checkResult[9])&checkResult[10]&checkResult[11] ) + begin + if(run_start_x < blob4minX) blob4minX <= run_start_x; + if((run_start_x+run_length) > blob4maxX) blob4maxX <= (run_start_x+run_length); + if(blob4maxY < run_start_y) blob4maxY <= run_start_y; + end + + //run adjacent to container 5 + if( (~checkResult[12])&checkResult[13]&checkResult[14] ) + begin + if(run_start_x < blob5minX) blob5minX <= run_start_x; + if((run_start_x+run_length) > blob5maxX) blob5maxX <= (run_start_x+run_length); + if(blob5maxY < run_start_y) blob5maxY <= run_start_y; + end + + //run adjacent to container 6 + if( (~checkResult[15])&checkResult[16]&checkResult[17] ) + begin + if(run_start_x < blob6minX) blob6minX <= run_start_x; + if((run_start_x+run_length) > blob6maxX) blob6maxX <= (run_start_x+run_length); + if(blob6maxY < run_start_y) blob6maxY <= run_start_y; + end + + //read next run from input fifo + state <= `VALIDATE_CHECK_ADJACENT_CONTAINER; + end + + //check if run could be added to container + `VALIDATE_CHECK_ADJACENT_CONTAINER: begin + //if run has been added, continue with next run + if(RunAdded) begin + state <= `CHECK_CONT_ADJACENCY; + end + //if run not adjacent, put into empty container + else begin + state <= `SELECT_EMPTY_CONTAINER; + end + end + + //if run was not adjacent, add to new container + `SELECT_EMPTY_CONTAINER: begin + + //first cont empty + if( checkResult[0] ) begin + blob1minX <= run_start_x; + blob1maxX <= run_start_x+run_length; + blob1minY <= run_start_y; + blob1maxY <= run_start_y; + +// sumBLOB_Xpositions_1<=run_sum_x_positions; +// sumBLOB_Ypositions_1<=run_sum_y_positions; +// sumBLOB_Pixels_1<=run_sum_values; + + blob1empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 2 is empty + //second cont empty + else if( checkResult[3]) begin + blob2minX <= run_start_x; + blob2maxX <= run_start_x+run_length; + blob2minY <= run_start_y; + blob2maxY <= run_start_y; + +// sumBLOB_Xpositions_2<=run_sum_x_positions; +// sumBLOB_Ypositions_2<=run_sum_y_positions; +// sumBLOB_Pixels_2<=run_sum_values; + + blob2empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 3 is empty + //third cont empty + if( checkResult[6]) begin + blob3minX <= run_start_x; + blob3maxX <= run_start_x+run_length; + blob3minY <= run_start_y; + blob3maxY <= run_start_y; + +// sumBLOB_Xpositions_3<=run_sum_x_positions; +// sumBLOB_Ypositions_3<=run_sum_y_positions; +// sumBLOB_Pixels_3<=run_sum_values; + + blob3empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 4 is empty + //fourth cont empty + else if( checkResult[9])begin + blob4minX <= run_start_x; + blob4maxX <= run_start_x+run_length; + blob4minY <= run_start_y; + blob4maxY <= run_start_y; + +// sumBLOB_Xpositions_4<=run_sum_x_positions; +// sumBLOB_Ypositions_4<=run_sum_y_positions; +// sumBLOB_Pixels_4<=run_sum_values; + + blob4empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 5 is empty + //fifth cont empty + else if( checkResult[12]) begin + blob5minX <= run_start_x; + blob5maxX <= run_start_x+run_length; + blob5minY <= run_start_y; + blob5maxY <= run_start_y; + +// sumBLOB_Xpositions_5<=run_sum_x_positions; +// sumBLOB_Ypositions_5<=run_sum_y_positions; +// sumBLOB_Pixels_5<=run_sum_values; + + blob5empty<=`FALSE; + end + + else if( checkResult[15]) begin + blob6minX <= run_start_x; + blob6maxX <= run_start_x+run_length; + blob6minY <= run_start_y; + blob6maxY <= run_start_y; + +// sumBLOB_Xpositions_6<=run_sum_x_positions; +// sumBLOB_Ypositions_6<=run_sum_y_positions; +// sumBLOB_Pixels_6<=run_sum_values; + + blob6empty<=`FALSE; + end + + state <= `CHECK_CONT_ADJACENCY; + end + + //compute center points for non-empty containers + //center point computation with BB and COM + `COMPUTE_CENTER: begin + //compute center point for blob in Container 1 + blob1X_bb_center <= ((blob1minX + blob1maxX)>>1'b1); + blob1Y_bb_center <= ((blob1minY + blob1maxY)>>1'b1); + //compute center point for blob in Container 2 + blob2X_bb_center <= ((blob2minX + blob2maxX)>>1'b1); + blob2Y_bb_center <= ((blob2minY + blob2maxY)>>1'b1); + //compute center point for blob in Container 3 + blob3X_bb_center <= ((blob3minX + blob3maxX)>>1'b1); + blob3Y_bb_center <= ((blob3minY + blob3maxY)>>1'b1); + //compute center point for blob in Container 4 + blob4X_bb_center <= ((blob4minX + blob4maxX)>>1'b1); + blob4Y_bb_center <= ((blob4minY + blob4maxY)>>1'b1); + //compute center point for blob in Container 5 + blob5X_bb_center <= ((blob5minX + blob5maxX)>>1'b1); + blob5Y_bb_center <= ((blob5minY + blob5maxY)>>1'b1); + //compute center point for blob in Container 6 + blob6X_bb_center <= ((blob6minX + blob6maxX)>>1'b1); + blob6Y_bb_center <= ((blob6minY + blob6maxY)>>1'b1); + + //increase delay time counter for COM computation + //delayCounterCOM<=delayCounterCOM+3'd1; + + state<=`CONFIG_WRITE; + end + + `CONFIG_WRITE: begin + //increase delay time counter for COM computation + //delayCounterCOM<=delayCounterCOM+3'd1; + + //if(delayCounterCOM > COM_DELAY_TIME) begin + //selector for write progress + case(write_result_pointer) + + `WRITE_BLOB_0: begin + //if(blob1empty==`FALSE && blob1Y > 1) begin + if(blob1empty==`FALSE) begin + //oWriteBlobData={10'd1, blob1Y, blob1X,(blob1maxY-blob1minY),(blob1maxX-blob1minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob1Y_bb_center; + oWriteBlobData[31:21]<=blob1X_bb_center; + oWriteBlobData[42:32]<=blob1Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob1X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob1maxY-blob1minY); + oWriteBlobData[75:65]<=(blob1maxX-blob1minX); + avgSizeYaxis<=(blob1maxY-blob1minY); + avgSizeXaxis<=(blob1maxX-blob1minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_1: begin + //if(blob2empty==`FALSE && blob2Y > 1) begin + if(blob2empty==`FALSE) begin + //oWriteBlobData={10'd2, blob2Y, blob2X,(blob2maxY-blob2minY),(blob2maxX-blob2minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob2Y_bb_center; + oWriteBlobData[31:21]<=blob2X_bb_center; + oWriteBlobData[42:32]<=blob2Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob2X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob2maxY-blob2minY); + oWriteBlobData[75:65]<=(blob2maxX-blob2minX); + avgSizeYaxis<=avgSizeYaxis+(blob2maxY-blob2minY); + avgSizeXaxis<=avgSizeXaxis+(blob2maxX-blob2minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+4'b0001; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_2: begin + //if(blob3empty==`FALSE && blob3Y > 1) begin + if(blob3empty==`FALSE) begin + //oWriteBlobData={10'd3, blob3Y, blob3X,(blob3maxY-blob3minY),(blob3maxX-blob3minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob3Y_bb_center; + oWriteBlobData[31:21]<=blob3X_bb_center; + oWriteBlobData[42:32]<=blob3Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob3X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob3maxY-blob3minY); + oWriteBlobData[75:65]<=(blob3maxX-blob3minX); + avgSizeYaxis<=avgSizeYaxis+(blob3maxY-blob3minY); + avgSizeXaxis<=avgSizeXaxis+(blob3maxX-blob3minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+4'b0001; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_3: begin + //if(blob4empty==`FALSE && blob4Y > 1) begin + if(blob4empty==`FALSE) begin + //oWriteBlobData={10'd4, blob4Y, blob4X,(blob4maxY-blob4minY),(blob4maxX-blob4minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob4Y_bb_center; + oWriteBlobData[31:21]<=blob4X_bb_center; + oWriteBlobData[42:32]<=blob4Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob4X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob4maxY-blob4minY); + oWriteBlobData[75:65]<=(blob4maxX-blob4minX); + avgSizeYaxis<=avgSizeYaxis+(blob4maxY-blob4minY); + avgSizeXaxis<=avgSizeXaxis+(blob4maxX-blob4minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_4: begin + //if(blob5empty==`FALSE && blob5Y > 1) begin + if(blob5empty==`FALSE) begin + //oWriteBlobData={10'd5, blob5Y, blob5X,(blob5maxY-blob5minY),(blob5maxX-blob5minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob5Y_bb_center; + oWriteBlobData[31:21]<=blob5X_bb_center; + oWriteBlobData[42:32]<=blob5Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob5X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob5maxY-blob5minY); + oWriteBlobData[75:65]<=(blob5maxX-blob5minX); + avgSizeYaxis<=avgSizeYaxis+(blob5maxY-blob5minY); + avgSizeXaxis<=avgSizeXaxis+(blob5maxX-blob5minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_5: begin + //if(blob6empty==`FALSE && blob6Y > 1) begin + if(blob6empty==`FALSE) begin + //oWriteBlobData={10'd6, blob6Y, blob6X,(blob6maxY-blob6minY),(blob6maxX-blob6minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob6Y_bb_center; + oWriteBlobData[31:21]<=blob6X_bb_center; + oWriteBlobData[42:32]<=blob6Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob6X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob6maxY-blob6minY); + oWriteBlobData[75:65]<=(blob6maxX-blob6minX); + + avgSizeYaxis<=avgSizeYaxis+(blob6maxY-blob6minY); + avgSizeXaxis<=avgSizeXaxis+(blob6maxX-blob6minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + default: begin + oAvgSizeXaxis<=divider_res_x; + oAvgSizeYaxis<=divider_res_y; + //oWriteBlobData<=32'h00000000; + oWriteBlobData<=0; + state<=`INIT;//continue processing pixel from new frame + end + //NO DEFAULT(DIVIDER, CONG) + endcase + //end + //end + + end + + + + `WRITE_FIFO: begin + if(!iWriteFifoFull) begin + oWriteRequest<=`TRUE; + state<=`WRITE_WAIT; + end + end + + `WRITE_WAIT: begin + oWriteRequest<=`FALSE; + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + + `CHECK_CONT_ADJACENCY: begin +//MERGE TO CONTAINER 1 + if(blob2empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob2minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob2maxY) < `CONT_RANGE)) begin + + if( ((blob2minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob2maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[0]<=`TRUE; + end + end + end + if(blob3empty==`FALSE && blob1empty==`FALSE) begin + //check adjacency on Y axis + if( ((blob3minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob3minY) < `CONT_RANGE) || + ((blob3minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob3minY) < `CONT_RANGE) || + ((blob3maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob3maxY) < `CONT_RANGE) || + ((blob3maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob3maxY) < `CONT_RANGE)) begin + + if( ((blob3minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob3minX) < `CONT_RANGE) || + ((blob3minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob3minX) < `CONT_RANGE) || + ((blob3maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob3maxX) < `CONT_RANGE) || + ((blob3maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob3maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[1]<=`TRUE; + end + end + end + if(blob4empty==`FALSE && blob1empty==`FALSE) begin + //check adjacency on Y axis + //Merge Container 1 and 4 if adjacent + //check adjacency on Y axis + if( ((blob4minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[2]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob5minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[3]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob6minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob6minY) < `CONT_RANGE) || + ((blob6minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob6minY) < `CONT_RANGE) || + ((blob6maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob6maxY) < `CONT_RANGE) || + ((blob6maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob6maxY) < `CONT_RANGE)) begin + + if( ((blob6minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob6minX) < `CONT_RANGE) || + ((blob6minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob6minX) < `CONT_RANGE) || + ((blob6maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob6maxX) < `CONT_RANGE) || + ((blob6maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob6maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[10]<=`TRUE; + end + end + end + +//MERGE TO CONTAINER 2 + if(blob3empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[4]<=`TRUE; + end + end + end + if(blob4empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob4minY) < `CONT_RANGE) || ((blob4minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob4maxY) < `CONT_RANGE) || ((blob4maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob4minY) < `CONT_RANGE) || ((blob4minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob4maxY) < `CONT_RANGE) || ((blob4maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob4minX) < `CONT_RANGE) || ((blob4minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob4maxX) < `CONT_RANGE) || ((blob4maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob4minX) < `CONT_RANGE) || ((blob4minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob4maxX) < `CONT_RANGE) || ((blob4maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[5]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[6]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[11]<=`TRUE; + end + end + end + +//MERGE CONTAINER 3 + if(blob4empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob4minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[7]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob5minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[8]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob6minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob6minY) < `CONT_RANGE) || + ((blob6minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob6minY) < `CONT_RANGE) || + ((blob6maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob6maxY) < `CONT_RANGE) || + ((blob6maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob6maxY) < `CONT_RANGE)) begin + + if( ((blob6minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob6minX) < `CONT_RANGE) || + ((blob6minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob6minX) < `CONT_RANGE) || + ((blob6maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob6maxX) < `CONT_RANGE) || + ((blob6maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob6maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[12]<=`TRUE; + end + end + end + +//MERGE CONTAINER 4 + if(blob5empty==`FALSE && blob4empty==`FALSE) begin + if( ((blob4minY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[9]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob4empty==`FALSE) begin + if( ((blob4minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[13]<=`TRUE; + end + end + end +//MERGE CONTAINER 5 + if(blob6empty==`FALSE && blob5empty==`FALSE) begin + if( ((blob5minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[14]<=`TRUE; + end + end + end + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONTAINER: begin + if(ContainerAdjacentResult>0) begin + + if(ContainerAdjacentResult[14]==1'b1) begin + state<= `MERGE_CONT_5_6; + end + else if(ContainerAdjacentResult[13]==1'b1) begin + state<= `MERGE_CONT_4_6; + end + else if(ContainerAdjacentResult[9]==1'b1) begin + state<= `MERGE_CONT_4_5; + end + else if(ContainerAdjacentResult[12]==1'b1) begin + state<= `MERGE_CONT_3_6; + end + else if(ContainerAdjacentResult[8]==1'b1) begin + state<= `MERGE_CONT_3_5; + end + else if(ContainerAdjacentResult[7]==1'b1) begin + state<= `MERGE_CONT_3_4; + end + else if(ContainerAdjacentResult[11]==1'b1) begin + state<= `MERGE_CONT_2_6; + end + else if(ContainerAdjacentResult[6]==1'b1) begin + state<= `MERGE_CONT_2_5; + end + else if(ContainerAdjacentResult[5]==1'b1) begin + state<= `MERGE_CONT_2_4; + end + else if(ContainerAdjacentResult[4]==1'b1) begin + state<= `MERGE_CONT_2_3; + end + else if(ContainerAdjacentResult[10]==1'b1) begin + state<= `MERGE_CONT_1_6; + end + else if(ContainerAdjacentResult[3]==1'b1) begin + state<= `MERGE_CONT_1_5; + end + else if(ContainerAdjacentResult[2]==1'b1) begin + state<= `MERGE_CONT_1_4; + end + else if(ContainerAdjacentResult[1]==1'b1) begin + state<= `MERGE_CONT_1_3; + end + else if(ContainerAdjacentResult[0]==1'b1) begin + state<= `MERGE_CONT_1_2; + end + + + end + else begin + state<=`IDLE; + end + end + + `MERGE_CONT_1_2: begin + if(blob2maxX > blob1maxX) blob1maxX <= blob2maxX; + if(blob2maxY > blob1maxY) blob1maxY <= blob2maxY; + if(blob2minX < blob1minX) blob1minX <= blob2minX; + if(blob2minY < blob1minY) blob1minY <= blob2minY; + ContainerAdjacentResult[0]<=`FALSE; + blob2empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_3: begin + if(blob3maxX > blob1maxX) blob1maxX <= blob3maxX; + if(blob3maxY > blob1maxY) blob1maxY <= blob3maxY; + if(blob3minX < blob1minX) blob1minX <= blob3minX; + if(blob3minY < blob1minY) blob1minY <= blob3minY; + ContainerAdjacentResult[1]<=`FALSE; + blob3empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_4: begin + if(blob4maxX > blob1maxX) blob1maxX <= blob4maxX; + if(blob4maxY > blob1maxY) blob1maxY <= blob4maxY; + if(blob4minX < blob1minX) blob1minX <= blob4minX; + if(blob4minY < blob1minY) blob1minY <= blob4minY; + ContainerAdjacentResult[2]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_5: begin + if(blob5maxX > blob1maxX) blob1maxX <= blob5maxX; + if(blob5maxY > blob1maxY) blob1maxY <= blob5maxY; + if(blob5minX < blob1minX) blob1minX <= blob5minX; + if(blob5minY < blob1minY) blob1minY <= blob5minY; + ContainerAdjacentResult[3]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_6: begin + if(blob6maxX > blob1maxX) blob1maxX <= blob6maxX; + if(blob6maxY > blob1maxY) blob1maxY <= blob6maxY; + if(blob6minX < blob1minX) blob1minX <= blob6minX; + if(blob6minY < blob1minY) blob1minY <= blob6minY; + ContainerAdjacentResult[10]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_3: begin + if(blob3maxX > blob2maxX) blob2maxX <= blob3maxX; + if(blob3maxY > blob2maxY) blob2maxY <= blob3maxY; + if(blob3minX < blob2minX) blob2minX <= blob3minX; + if(blob3minY < blob2minY) blob2minY <= blob3minY; + ContainerAdjacentResult[4]<=`FALSE; + blob3empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_4: begin + if(blob4maxX > blob2maxX) blob2maxX <= blob4maxX; + if(blob4maxY > blob2maxY) blob2maxY <= blob4maxY; + if(blob4minX < blob2minX) blob2minX <= blob4minX; + if(blob4minY < blob2minY) blob2minY <= blob4minY; + ContainerAdjacentResult[5]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_5: begin + if(blob5maxX > blob2maxX) blob2maxX <= blob5maxX; + if(blob5maxY > blob2maxY) blob2maxY <= blob5maxY; + if(blob5minX < blob2minX) blob2minX <= blob5minX; + if(blob5minY < blob2minY) blob2minY <= blob5minY; + ContainerAdjacentResult[6]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_6: begin + if(blob6maxX > blob2maxX) blob2maxX <= blob6maxX; + if(blob6maxY > blob2maxY) blob2maxY <= blob6maxY; + if(blob6minX < blob2minX) blob2minX <= blob6minX; + if(blob6minY < blob2minY) blob2minY <= blob6minY; + ContainerAdjacentResult[11]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_4: begin + if(blob4maxX > blob3maxX) blob3maxX <= blob4maxX; + if(blob4maxY > blob3maxY) blob3maxY <= blob4maxY; + if(blob4minX < blob3minX) blob3minX <= blob4minX; + if(blob4minY < blob3minY) blob3minY <= blob4minY; + ContainerAdjacentResult[7]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_5: begin + if(blob5maxX > blob3maxX) blob3maxX <= blob5maxX; + if(blob5maxY > blob3maxY) blob3maxY <= blob5maxY; + if(blob5minX < blob3minX) blob3minX <= blob5minX; + if(blob5minY < blob3minY) blob3minY <= blob5minY; + ContainerAdjacentResult[8]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_6: begin + if(blob6maxX > blob3maxX) blob3maxX <= blob6maxX; + if(blob6maxY > blob3maxY) blob3maxY <= blob6maxY; + if(blob6minX < blob3minX) blob3minX <= blob6minX; + if(blob6minY < blob3minY) blob3minY <= blob6minY; + ContainerAdjacentResult[12]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_4_5: begin + if(blob5maxX > blob4maxX) blob4maxX <= blob5maxX; + if(blob5maxY > blob4maxY) blob4maxY <= blob5maxY; + if(blob5minX < blob4minX) blob4minX <= blob5minX; + if(blob5minY < blob4minY) blob4minY <= blob5minY; + ContainerAdjacentResult[9]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_4_6: begin + if(blob6maxX > blob4maxX) blob4maxX <= blob6maxX; + if(blob6maxY > blob4maxY) blob4maxY <= blob6maxY; + if(blob6minX < blob4minX) blob4minX <= blob6minX; + if(blob6minY < blob4minY) blob4minY <= blob6minY; + ContainerAdjacentResult[13]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_5_6: begin + if(blob6maxX > blob5maxX) blob5maxX <= blob6maxX; + if(blob6maxY > blob5maxY) blob5maxY <= blob6maxY; + if(blob6minX < blob5minX) blob5minX <= blob6minX; + if(blob6minY < blob5minY) blob5minY <= blob6minY; + ContainerAdjacentResult[14]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + endcase + end +end + + +//perform center of mass computation +//delay of 1 clock tick +//CenterOfMass BlobCenterComputation1( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_1), +// .inSumPosX(sumBLOB_Xpositions_1), +// .inSumPosY(sumBLOB_Ypositions_1), +// .outBlobXcenter(blob1X_com_center), +// .outBlobYcenter(blob1Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation2( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_2), +// .inSumPosX(sumBLOB_Xpositions_2), +// .inSumPosY(sumBLOB_Ypositions_2), +// .outBlobXcenter(blob2X_com_center), +// .outBlobYcenter(blob2Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation3( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_3), +// .inSumPosX(sumBLOB_Xpositions_3), +// .inSumPosY(sumBLOB_Ypositions_3), +// .outBlobXcenter(blob3X_com_center), +// .outBlobYcenter(blob3Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation4( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_4), +// .inSumPosX(sumBLOB_Xpositions_4), +// .inSumPosY(sumBLOB_Ypositions_4), +// .outBlobXcenter(blob4X_com_center), +// .outBlobYcenter(blob4Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation5( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_5), +// .inSumPosX(sumBLOB_Xpositions_5), +// .inSumPosY(sumBLOB_Ypositions_5), +// .outBlobXcenter(blob5X_com_center), +// .outBlobYcenter(blob5Y_com_center)); +// +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation6( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_6), +// .inSumPosX(sumBLOB_Xpositions_6), +// .inSumPosY(sumBLOB_Ypositions_6), +// .outBlobXcenter(blob6X_com_center), +// .outBlobYcenter(blob6Y_com_center)); + +endmodule + + +module divider(//clk, + opa, opb, quo, rem + //testy , testy2, testy_diff, dividend_test + ); + input [10:0] opa; + input [3:0] opb; + output [10:0] quo, rem; + //input clk; +//output [49:0] testy; +//output [49:0] testy2; +//output [49:0] testy_diff; +//output [49:0] dividend_test; + + +//assign testy_diff = diff27; +//assign testy = quotient26; +//assign testy2 = divider_copy26; +//assign dividend_test = dividend_copy26; + + + + reg [10:0] quo, rem; + +// """"""""| +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 0 Difference is negative: copy dividend and put 0 in quotient. +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 00 Difference is negative: copy dividend and put 0 in quotient. +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 001 Difference is positive: use difference and put 1 in quotient. +// quotient (numbers above) + + reg [10:0] quotient0; + reg [10:0] dividend_copy0, diff0; + reg [10:0] divider_copy0; + wire [10:0] remainder0; + + reg [10:0] quotient1; + reg [10:0] dividend_copy1, diff1; + reg [10:0] divider_copy1; + wire [10:0] remainder1; + + reg [10:0] quotient2; + reg [10:0] dividend_copy2, diff2; + reg [10:0] divider_copy2; + wire [10:0] remainder2; + + reg [10:0] quotient3; + reg [10:0] dividend_copy3, diff3; + reg [10:0] divider_copy3; + wire [10:0] remainder3; + + reg [10:0] quotient4; + reg [10:0] dividend_copy4, diff4; + reg [10:0] divider_copy4; + wire [10:0] remainder4; + + reg [10:0] quotient5; + reg [10:0] dividend_copy5, diff5; + reg [10:0] divider_copy5; + wire [10:0] remainder5; + + reg [10:0] quotient6; + reg [10:0] dividend_copy6, diff6; + reg [10:0] divider_copy6; + wire [10:0] remainder6; + + reg [10:0] quotient7; + reg [10:0] dividend_copy7, diff7; + reg [10:0] divider_copy7; + wire [10:0] remainder7; + + reg [10:0] quotient8; + reg [10:0] dividend_copy8, diff8; + reg [10:0] divider_copy8; + wire [10:0] remainder8; + +always @ (opa or opb) +begin +//stage initial + quotient0 = 11'b00000000000; + dividend_copy0 = opa; + divider_copy0 = {opb,7'b0000000}; + + //stage1 + diff1 = dividend_copy0 - divider_copy0; + quotient1 [10:1] = quotient0[9:0] ; + if (!diff1[10]) // if diff1[10] == 0 (diff is positive, use difference ) + begin + dividend_copy1 = diff1; + quotient1[0] = 1'b1; + end +else // diff was negative, use old dividend +begin +dividend_copy1 = dividend_copy0; + quotient1[0] = 1'b0; + +end + divider_copy1 = (divider_copy0 >> 1); +//stage2 + diff2 = dividend_copy1 - divider_copy1; + quotient2[10:1] = quotient1 [9:0] ; + if (!diff2[10]) + begin + dividend_copy2 = diff2; + quotient2[0] = 1'b1; + end + else +begin +dividend_copy2 = dividend_copy1; + quotient2[0] = 1'b0; + +end + divider_copy2 = divider_copy1 >> 1; + + //stage3 + diff3 = dividend_copy2 - divider_copy2; + quotient3[10:1] = quotient2 [9:0] ; + if (!diff3[10]) + begin + dividend_copy3 = diff3; + quotient3[0] = 1'b1; + end + else +begin +dividend_copy3 = dividend_copy2; + quotient3[0] = 1'b0; + +end + divider_copy3 = divider_copy2 >> 1; + + //stage4 + diff4 = dividend_copy3 - divider_copy3; + quotient4[10:1] = quotient3 [9:0] ; + if (!diff4[10]) + begin + dividend_copy4 = diff4; + quotient4[0] = 1'b1; + end + else +begin +dividend_copy4 = dividend_copy3; + quotient4[0] = 1'b0; + +end + divider_copy4 = divider_copy3 >> 1; + //stage5 + diff5 = dividend_copy4 - divider_copy4; + quotient5[10:1] = quotient4 [9:0] ; + if (!diff5[10]) + begin + dividend_copy5 = diff5; + quotient5[0] = 1'b1; + end + else +begin +dividend_copy5 = dividend_copy4; + quotient5[0] = 1'b0; + +end + divider_copy5 = divider_copy4 >> 1; + //stage6 + diff6 = dividend_copy5 - divider_copy5; + quotient6[10:1] = quotient5 [9:0] ; + if (!diff6[10]) + begin + dividend_copy6 = diff6; + quotient6[0] = 1'b1; + end + else +begin +dividend_copy6 = dividend_copy5; + quotient6[0] = 1'b0; + +end + divider_copy6 = divider_copy5>> 1; + + //stage7 + diff7 = dividend_copy6 - divider_copy6; + quotient7[10:1] = quotient6 [9:0] ; + if (!diff7[10]) + begin + dividend_copy7 = diff7; + quotient7[0] = 1'b1; + end + else +begin +dividend_copy7 = dividend_copy6; + quotient7[0] = 1'b0; + +end + divider_copy7 = divider_copy6>> 1; + //stage8 + diff8 = dividend_copy7 - divider_copy7; + quotient8[10:1] = quotient7 [9:0] ; + if (!diff8[10]) + begin + dividend_copy8 = diff8; + quotient8[0] = 1'b1; + end + else +begin +dividend_copy8 = dividend_copy7; + quotient8[0] = 1'b0; + +end + divider_copy8 = divider_copy7>> 1; + +quo = quotient8; +rem = dividend_copy8; + +end + + //integer i; + + /* +always @(opa,opb) +begin + for (i=-1; i<8; i=i+1) +begin +if (i==-1) +begin + // initialization +quotient = 10'd0; +dividend_copy = opa; +divider_copy = {opb,7'd0}; +end +else +begin +diff = dividend_copy - divider_copy; +quotient = quotient ; + +if( !diff[10] ) +begin +dividend_copy = diff; +quotient[0] = 1'd1; +end +divider_copy = divider_copy >> 1; +end +end +end +*/ + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v b/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v new file mode 100755 index 000000000..0a2dd03ce --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v @@ -0,0 +1,2846 @@ + module paj_boundtop_hierarchy_no_mem (triIDvalid, triID, wanttriID, raydata, rayaddr, raywe, resultready, resultdata, globalreset, want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, pglobalreset, tm3_clk_v0, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource, input1); + + + output triIDvalid; + wire triIDvalid; + output[15:0] triID; + wire[15:0] triID; + input wanttriID; + output[31:0] raydata; + wire[31:0] raydata; + output[3:0] rayaddr; + wire[3:0] rayaddr; + output[2:0] raywe; + wire[2:0] raywe; + input resultready; + input[31:0] resultdata; + output globalreset; + wire globalreset; + output want_braddr; + wire want_braddr; + input braddr_ready; + input[9:0] braddrin; + output want_brdata; + wire want_brdata; + input brdata_ready; + input[31:0] brdatain; + output want_addr2; + wire want_addr2; + input addr2_ready; + input[17:0] addr2in; + output want_data2; + wire want_data2; + input data2_ready; + input[63:0] data2in; + input pglobalreset; + input tm3_clk_v0; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input[1:0] raygroup01; + input raygroupvalid01; + output busy01; + wire busy01; + input[1:0] raygroup10; + input raygroupvalid10; + output busy10; + wire busy10; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + input rgAddrValid; + output rgDone; + wire rgDone; + output[31:0] rgResultData; + wire[31:0] rgResultData; + output rgResultReady; + wire rgResultReady; + output[1:0] rgResultSource; + wire[1:0] rgResultSource; + input input1; + wire raygroupwe; + wire raygroupwe01; + wire raygroupwe10; + wire[1:0] raygroupout; + wire[1:0] raygroupout01; + wire[1:0] raygroupout10; + wire[1:0] raygroupid; + wire[1:0] raygroupid01; + wire[1:0] raygroupid10; + reg[1:0] oldresultid; + wire[1:0] resultid; + wire[31:0] t1i; + wire[31:0] t2i; + wire[31:0] t3i; + wire[15:0] u1i; + wire[15:0] u2i; + wire[15:0] u3i; + wire[15:0] v1i; + wire[15:0] v2i; + wire[15:0] v3i; + wire[15:0] id1i; + wire[15:0] id2i; + wire[15:0] id3i; + wire hit1i; + wire hit2i; + wire hit3i; + wire newresult; + wire write; + reg reset; + wire reset01; + wire reset10; + wire[103:0] peekdata; + reg[103:0] peeklatch; + wire commit01; + wire commit10; + wire[1:0] baseaddress01; + wire[1:0] baseaddress10; + wire[1:0] done; + wire cntreset; + wire cntreset01; + wire cntreset10; + wire passCTS01; + wire passCTS10; + wire triIDvalid01; + wire triIDvalid10; + wire[15:0] triID01; + wire[15:0] triID10; + reg[9:0] boundNodeID; + wire[9:0] BoundNodeID01; + wire[9:0] BoundNodeID10; + wire enablenear; + wire enablenear01; + wire enablenear10; + wire ack01; + wire ack10; + wire empty01; + wire dataready01; + wire empty10; + wire dataready10; + wire lhreset01; + wire lhreset10; + wire[9:0] boundnodeIDout01; + wire[9:0] boundnodeIDout10; + wire[1:0] level01; + wire[1:0] level10; + wire[2:0] hitmask01; + wire[2:0] hitmask10; + // Offset Block Ram Read Signals + wire[9:0] ostaddr; + wire[9:0] addrind01; + wire[9:0] addrind10; + wire ostaddrvalid; + wire addrindvalid01; + wire addrindvalid10; + wire ostdatavalid; + wire[31:0] ostdata; + // Tri List Ram Read Signals + wire[17:0] tladdr; + wire[17:0] tladdr01; + wire[17:0] tladdr10; + wire tladdrvalid; + wire tladdrvalid01; + wire tladdrvalid10; + wire tldatavalid; +wire[63:0] tldata; + // Final Result Signals + wire[31:0] t1_01; + wire[31:0] t2_01; + wire[31:0] t3_01; + wire[31:0] t1_10; + wire[31:0] t2_10; + wire[31:0] t3_10; + wire[15:0] v1_01; + wire[15:0] v2_01; + wire[15:0] v3_01; + wire[15:0] v1_10; + wire[15:0] v2_10; + wire[15:0] v3_10; + wire[15:0] u1_01; + wire[15:0] u2_01; + wire[15:0] u3_01; + wire[15:0] u1_10; + wire[15:0] u2_10; + wire[15:0] u3_10; + wire[15:0] id1_01; + wire[15:0] id2_01; + wire[15:0] id3_01; + wire[15:0] id1_10; + wire[15:0] id2_10; + wire[15:0] id3_10; + wire hit1_01; + wire hit2_01; + wire hit3_01; + wire hit1_10; + wire hit2_10; + wire hit3_10; + wire bcvalid01; + wire bcvalid10; + wire[2:0] peekoffset1a; + wire[2:0] peekoffset1b; + wire[2:0] peekoffset0a; + wire[2:0] peekoffset0b; + wire[2:0] peekoffset2a; + wire[2:0] peekoffset2b; + wire[4:0] peekaddressa; + wire[4:0] peekaddressb; + wire doutput; + wire dack; + wire[4:0] state01; + wire[4:0] state10; + wire[2:0] junk1; + wire[2:0] junk1b; + wire junk2; + wire junk2a; + wire[1:0] junk3; + wire[1:0] junk4; + wire[13:0] debugcount01; + wire[13:0] debugcount10; + wire[1:0] debugsubcount01; + wire[1:0] debugsubcount10; + wire[2:0] statesram; + + onlyonecycle oc (input1, doutput, pglobalreset, tm3_clk_v0); + // Real Stuff Starts Here + assign ostaddr = addrind01 | addrind10 ; + assign ostaddrvalid = addrindvalid01 | addrindvalid10 ; + + vblockramcontroller offsettable(want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, ostaddr, ostaddrvalid, ostdata, ostdatavalid, pglobalreset, tm3_clk_v0); + assign tladdr = tladdr01 | tladdr10 ; + assign tladdrvalid = tladdrvalid01 | tladdrvalid10 ; + sramcontroller trilist (want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, tladdr, tladdrvalid, tldata, tldatavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, pglobalreset, tm3_clk_v0, statesram); + resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); + rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); + boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01); + boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01); + resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); + +assign raygroupout = raygroupout01 | raygroupout10 ; + assign raygroupwe = raygroupwe01 | raygroupwe10 ; + assign raygroupid = raygroupid01 | raygroupid10 ; + assign triIDvalid = triIDvalid01 | triIDvalid10 ; + assign enablenear = enablenear01 | enablenear10 ; + assign triID = triID01 | triID10 ; + assign cntreset = cntreset01 | cntreset10 ; + + // reset <= reset01 or reset10; + always @(BoundNodeID01 or BoundNodeID10 or resultid) + begin + if (resultid == 2'b01) + begin + boundNodeID = BoundNodeID01 ; + end + else if (resultid == 2'b10) + begin + boundNodeID = BoundNodeID10 ; + end + else + begin + boundNodeID = 10'b0000000000 ; + end + end + assign write = ((newresult == 1'b1) & (resultid != 0) & ((hit1i == 1'b1) | (hit2i == 1'b1) | (hit3i == 1'b1))) ? 1'b1 : 1'b0 ; + + sortedstack st(t1i, {hit3i, hit2i, hit1i, boundNodeID}, write, reset, peekdata, pglobalreset, tm3_clk_v0); + assign commit01 = (done == 2'b01) ? 1'b1 : 1'b0 ; + assign commit10 = (done == 2'b10) ? 1'b1 : 1'b0 ; + assign dack = doutput | ack01 ; + listhandler lh01 (peeklatch, commit01, hitmask01, dack, boundnodeIDout01, level01, empty01, dataready01, lhreset01, pglobalreset, tm3_clk_v0, peekoffset0a, peekoffset1a, peekoffset2a, junk2a, junk4); + listhandler lh02 (peeklatch, commit10, hitmask10, ack10, boundnodeIDout10, level10, empty10, dataready10, lhreset10, pglobalreset, tm3_clk_v0, junk1, junk1b, peekoffset2b, junk2, junk3); + + always @(posedge tm3_clk_v0) + begin + if (pglobalreset == 1'b1) + begin + peeklatch <= 0; + reset <= 1'b0 ; + oldresultid <= 2'b00 ; + end + else + begin + oldresultid <= resultid ; + // The reset is only for debugging + if (resultid != oldresultid) + begin + reset <= 1'b1 ; + end + else + begin + reset <= 1'b0 ; + end + if (done != 0) + begin + peeklatch <= peekdata ; + end + end + end + + resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); + endmodule + + + + + + + + + + + + + + +module resulttransmit (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + input hit01a; + input hit01b; + + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[15:0] u01a; + input[15:0] u01b; + input[15:0] u01c; + input[15:0] v01a; + input[15:0] v01b; + input[15:0] v01c; + input[15:0] u10a; + input[15:0] u10b; + + input[15:0] u10c; + input[15:0] v10a; + input[15:0] v10b; + input[15:0] v10c; + output[31:0] rgResultData; + reg[31:0] rgResultData; + output rgResultReady; + reg rgResultReady; + output[1:0] rgResultSource; + reg[1:0] rgResultSource; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + reg hit01al; + reg hit01bl; + reg hit01cl; + reg hit10al; + reg hit10bl; + reg hit10cl; + reg pending01; + reg pending10; + reg valid01d; + reg valid10d; + +reg[31:0] temp_rgResultData; + reg temp_rgResultReady; + reg[1:0] temp_rgResultSource; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + rgResultData <= 32'b00000000000000000000000000000000 ; + rgResultSource <= 2'b00 ; + + rgResultReady <= 1'b0 ; + end + else + begin + valid01d <= valid01 ; + valid10d <= valid10 ; + if (valid01 == 1'b1) + begin + pending01 <= 1'b1 ; + end + if (valid01d == 1'b1) + begin + hit01al <= hit01a ; + hit01bl <= hit01b ; + hit01cl <= hit01c ; + end + if (valid10 == 1'b1) + begin + pending10 <= 1'b1 ; + end + if (valid10d == 1'b1) + begin + hit10al <= hit10a ; + hit10bl <= hit10b ; + hit10cl <= hit10c ; + end + state <= next_state ; + + rgResultData <= temp_rgResultData; + rgResultReady <= temp_rgResultReady; + rgResultSource <= temp_rgResultSource; + end + end + + always @(state or pending01 or pending10) + begin + case (state) + 0 : + begin + if (pending01 == 1'b1) + begin + next_state = 1 ; + end + else if (pending10 == 1'b1) + begin + next_state = 5 ; + end + else + + begin + next_state = 0 ; + end + end + 1 : + begin + next_state = 2 ; + temp_rgResultData = {id01a, id01b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b01 ; + end + 2 : + begin + next_state = 3 ; + temp_rgResultData = {13'b0000000000000, hit01al, hit01bl, hit01cl, id01c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + + 3 : + begin + next_state = 4 ; + temp_rgResultData = {8'b00000000, u01a[15:8], u01b[15:8], u01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 4 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v01a[15:8], v01b[15:8], v01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 5 : + begin + next_state = 6 ; + temp_rgResultData = {id10a, id10b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b10 ; + end + 6 : + begin + next_state = 7 ; + temp_rgResultData = {13'b0000000000000, hit10al, hit10bl, hit10cl, id10c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 7 : + begin + next_state = 8 ; + temp_rgResultData = {8'b00000000, u10a[15:8], u10b[15:8], u10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 8 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v10a[15:8], v10b[15:8], v10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + default: + begin + temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; + end + endcase + end + endmodule + + + + + + + + + + + + + + + + + + + + + + + + + +module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygroup, validraygroup, busy, triIDvalid, triID, wanttriID, l0reset, baseaddress, newdata, boundNodeIDout, resultID, hitmask, ldataready, lempty, llevel, lboundNodeID, lack, lhreset, addrind, addrindvalid, dataind, dataindvalid, tladdr, tladdrvalid, tldata, tldatavalid, t1in, t2in, t3in, u1in, u2in, u3in, v1in, v2in, v3in, id1in, id2in, id3in, hit1in, hit2in, hit3in, t1, t2, t3, u1, u2, u3, v1, v2, v3, id1, id2, id3, hit1, hit2, hit3, bcvalid, done, resetcnt, passCTSout, passCTSin, globalreset, clk, statepeek, debugsubcount, debugcount); + + output[1:0] raygroupout; + wire[1:0] raygroupout; + output raygroupwe; + reg raygroupwe; + output[1:0] raygroupid; + reg[1:0] raygroupid; + output enablenear; + reg enablenear; + input[1:0] raygroup; + input validraygroup; + output busy; + reg busy; + reg temp_busy; + output triIDvalid; + reg triIDvalid; + output[15:0] triID; + reg[15:0] triID; + input wanttriID; + output l0reset; + reg l0reset; + output[1:0] baseaddress; + reg[1:0] baseaddress; + input newdata; + output[9:0] boundNodeIDout; + reg[9:0] boundNodeIDout; + input[1:0] resultID; + output[2:0] hitmask; + reg[2:0] hitmask; + input ldataready; + input lempty; + input[1:0] llevel; + input[9:0] lboundNodeID; + output lack; + reg lack; + output lhreset; + reg lhreset; + output[9:0] addrind; + reg[9:0] addrind; + output addrindvalid; + reg addrindvalid; + input[31:0] dataind; + input dataindvalid; + output[17:0] tladdr; + reg[17:0] tladdr; + output tladdrvalid; + reg tladdrvalid; + input[63:0] tldata; + input tldatavalid; + input[31:0] t1in; + input[31:0] t2in; + input[31:0] t3in; + input[15:0] u1in; + input[15:0] u2in; + input[15:0] u3in; + input[15:0] v1in; + input[15:0] v2in; + input[15:0] v3in; + input[15:0] id1in; + input[15:0] id2in; + input[15:0] id3in; + input hit1in; + input hit2in; + input hit3in; + output[31:0] t1; + reg[31:0] t1; + output[31:0] t2; + reg[31:0] t2; + output[31:0] t3; + reg[31:0] t3; + output[15:0] u1; + reg[15:0] u1; + output[15:0] u2; + reg[15:0] u2; + output[15:0] u3; + reg[15:0] u3; + output[15:0] v1; + reg[15:0] v1; + output[15:0] v2; + reg[15:0] v2; + output[15:0] v3; + reg[15:0] v3; + output[15:0] id1; + reg[15:0] id1; + output[15:0] id2; + reg[15:0] id2; + output[15:0] id3; + reg[15:0] id3; + output hit1; + reg hit1; + output hit2; + reg hit2; + output hit3; + reg hit3; + output bcvalid; + reg bcvalid; + input[1:0] done; + output resetcnt; + reg resetcnt; + output passCTSout; + reg passCTSout; + input passCTSin; + input globalreset; + input clk; + output[4:0] statepeek; + reg[4:0] statepeek; + output[1:0] debugsubcount; + wire[1:0] debugsubcount; + output[13:0] debugcount; + wire[13:0] debugcount; + + reg[4:0] state; + reg[4:0] next_state; + reg cts; + reg[11:0] addr; + reg[11:0] startAddr; + reg[2:0] resetcount; + reg[1:0] raygroupoutl; + // Leaf Node Signals + reg[13:0] count; + reg[63:0] triDatalatch; + reg[1:0] subcount; + reg[1:0] maskcount; + + reg[4:0] temp_statepeek; + reg [1:0]temp_raygroupoutl ; + reg temp_cts ; + reg temp_passCTSout ; + reg [2:0]temp_resetcount ; + reg temp_l0reset ; + reg [11:0]temp_addr ; + reg [11:0]temp_startAddr ; + reg [9:0]temp_boundNodeIDout ; + reg [1:0]temp_baseaddress ; + reg [2:0]temp_hitmask ; + reg temp_hit1 ; + reg temp_hit2 ; + reg temp_hit3 ; + reg temp_triIDvalid ; + reg [15:0]temp_triID ; + reg temp_lack ; + reg [9:0]temp_addrind ; + reg temp_addrindvalid ; + reg temp_tladdrvalid ; + reg [17:0]temp_tladdr ; + reg [13:0]temp_count ; + reg [1:0]temp_subcount ; + reg [1:0]temp_maskcount ; + reg [63:0]temp_triDatalatch ; + reg [31:0]temp_t1 ; + reg [15:0]temp_u1 ; + reg [15:0]temp_v1 ; + reg [15:0]temp_id1 ; + reg [31:0]temp_t2 ; + reg [15:0]temp_u2 ; + reg [15:0]temp_v2 ; + reg [15:0]temp_id2 ; + reg [31:0]temp_t3 ; + reg [15:0]temp_u3 ; + reg [15:0]temp_v3 ; + reg [15:0]temp_id3 ; + + assign debugsubcount = subcount ; + assign debugcount = count ; + assign raygroupout = (cts == 1'b1 & state != 8 & state != 19 & state != 1) ? raygroupoutl : 2'b00 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + raygroupoutl <= 0; + cts <= 1'b0 ; + passCTSout <= 1'b0 ; + addr <= 0; + startAddr <= 0; + boundNodeIDout <= 0; + resetcount <= 0; + hitmask <= 1; + lack <= 1'b0 ; + baseaddress <= 0; + l0reset <= 1'b0 ; + resetcnt <= 1'b0 ; + triIDvalid <= 1'b0 ; + triID <= 0; + addrind <= 0; + addrindvalid <= 1'b0 ; + tladdrvalid <= 1'b0 ; + tladdr <= 0; + triDatalatch <= 0; + maskcount <= 0; + subcount <= 0; + count <= 0; + hit1 <= 1'b0 ; + hit2 <= 1'b0 ; + hit3 <= 1'b0 ; + t1 <= 0; + t2 <= 0; + t3 <= 0; + u1 <= 0; + u2 <= 0; + u3 <= 0; + v1 <= 0; + v2 <= 0; + v3 <= 0; + id1 <= 0; + id2 <= 0; + id3 <= 0; + busy <= 1'b0 ; + end + else + begin + state <= next_state ; + busy <= temp_busy; + if ((done == 2'b00) | (state == 15 & newdata == 1'b1 & resultID == 2'b00)) + begin + resetcnt <= 1'b1 ; + end + else + begin + resetcnt <= 1'b0 ; + end + + statepeek <= temp_statepeek; + raygroupoutl <= temp_raygroupoutl ; + cts <= temp_cts ; + passCTSout <= temp_passCTSout ; + resetcount <= temp_resetcount ; + l0reset <= temp_l0reset ; + addr <= temp_addr ; + startAddr <= temp_startAddr ; + boundNodeIDout <= temp_boundNodeIDout ; + baseaddress <= temp_baseaddress ; + hitmask <= temp_hitmask ; + hit1 <= temp_hit1 ; + hit2 <= temp_hit2 ; + hit3 <= temp_hit3 ; + triIDvalid <= temp_triIDvalid ; + triID <= temp_triID ; + lack <= temp_lack ; + addrind <= temp_addrind ; + addrindvalid <= temp_addrindvalid ; + tladdr <= temp_tladdr ; + tladdrvalid <= temp_tladdrvalid ; + count <= temp_count ; + subcount <= temp_subcount ; + maskcount <= temp_maskcount ; + triDatalatch <= temp_triDatalatch ; + t1 <= temp_t1 ; + u1 <= temp_u1 ; + v1 <= temp_v1 ; + id1 <= temp_id1 ; + t2 <= temp_t2 ; + u2 <= temp_u2 ; + v2 <= temp_v2 ; + id2 <= temp_id2 ; + t3 <= temp_t3 ; + u3 <= temp_u3 ; + v3 <= temp_v3 ; + id3 <= temp_id3 ; + end + end + + + + always @* + begin + case (state) + 0 : + begin + raygroupid = 0; + enablenear = 1'b0 ; + raygroupwe = 1'b0 ; + bcvalid = 1'b0 ; + + lhreset = 1'b1 ; + if (validraygroup == 1'b1 & cts == 1'b1) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (validraygroup == 1'b1 & cts == 1'b0) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else if (validraygroup == 1'b0 & passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00001 ; + // + temp_raygroupoutl = raygroup ; + if (validraygroup == 1'b1 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + else if (validraygroup == 1'b0 & cts == 1'b1 & passCTSin == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + + end + 1 : + begin + if ((passCTSin == cts) & (cts == 1'b1)) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == cts) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00010 ; + // + if (passCTSin == cts) + begin + temp_passCTSout = 1'b0 ; + end + + end + 2 : + begin + if (wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00011 ; + // + temp_resetcount = 3'b100 ; + temp_l0reset = 1'b1 ; + temp_addr = 0; + temp_startAddr = 0; + temp_boundNodeIDout = 0; + temp_baseaddress = 0; + temp_hitmask = 1; + temp_hit1 = 1'b0 ; + temp_hit2 = 1'b0 ; + temp_hit3 = 1'b0 ; + end + 3 : + begin + if ((addr - startAddr >= 1) & (addr - startAddr != 49)) + begin + raygroupid = 2'b00 ; + end + next_state = 4 ; + temp_busy = 1'b1 ; + if (resetcount == 5) + begin + raygroupwe = 1'b1 ; + end + enablenear = 1'b1 ; + temp_statepeek = 5'b00100 ; + // + if ((addr - startAddr != 48) & (addr - startAddr != 49)) + begin + temp_triIDvalid = 1'b1 ; + end + temp_triID = {4'b0000, addr} ; + end + 4 : + begin + if (addr - startAddr == 49) + begin + next_state = 6 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 5 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00101 ; + end + 5 : + begin + next_state = 3 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b00111 ; + // + temp_addr = addr + 1 ; + if (resetcount == 5) + begin + temp_resetcount = 3'b000 ; + end + else + begin + temp_resetcount = resetcount + 1 ; + end + + end + 6 : + begin + if (passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 7; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + next_state = 8; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 6; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b1 & cts == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + + end + 7 : + begin + if (passCTSin == 0) + begin + next_state = 6; + temp_busy = 1'b1 ; + end + else + begin + next_state = 7; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b0) + begin + temp_passCTSout = 1'b0 ; + end + + end + 8 : + begin + if (passCTSin == 1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 8 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01010 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + end + 9 : + begin + if (lempty == 1'b1) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + else if (ldataready == 1'b1 & llevel == 2'b10) + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + else if (ldataready == 1'b1 & wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01011 ; + // + temp_resetcount = 3'b100 ; + temp_baseaddress = llevel + 1 ; + // boundNodeIDout = (lBoundNodeID+1)(6 downto 0) & "000"; + //boundNodeIDout = {(lboundNodeID + 1)[6:0], 3'b000} ; + temp_boundNodeIDout = {lboundNodeID[6:0], 3'b000} ; + // temp_addr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //temp_addr = (({(lboundNodeID + 1)[7:0], 4'b0000}) + ({(lboundNodeID + 1)[6:1], 5'b00000}))[11:0] ; + temp_addr = (({lboundNodeID[7:0], 4'b0000}) + ({lboundNodeID[6:1], 5'b00000})); + // startaddr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //startAddr = (({(lboundNodeID + 1), 4'b0000}) + ({(lboundNodeID + 1), 5'b00000})) ; + temp_startAddr = (({lboundNodeID, 4'b0000}) + ({lboundNodeID, 5'b00000})) ; + if (ldataready == 1'b1 & (wanttriID == 1'b1 | llevel == 2'b10)) + begin + temp_lack = 1'b1 ; + temp_l0reset = 1'b1 ; + end + + if (ldataready == 1'b1 & llevel == 2'b10) + begin + temp_addrind = lboundNodeID - 72 ; + temp_addrindvalid = 1'b1 ; + end + end + 10 : + begin + if (dataindvalid == 1'b1) + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01100 ; + // + + temp_tladdr = dataind[17:0] ; + temp_count = dataind[31:18] ; + if (dataindvalid == 1'b1) + begin + temp_addrindvalid = 1'b0 ; + temp_tladdrvalid = 1'b1 ; + end + + end + 11 : + begin + if (count == 0 | count == 1) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else if (wanttriID == 1'b1 & tldatavalid == 1'b1) + begin + next_state = 12 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01101 ; + // + + temp_triDatalatch = tldata ; + temp_subcount = 2'b10 ; + temp_maskcount = 2'b00 ; + if ((wanttriID == 1'b1 & tldatavalid == 1'b1) | (count == 0 | count == 1)) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + end + + end + 12 : + begin + if (count != 0) + begin + next_state = 13 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + if (subcount == 2'b01) + begin + raygroupid = 2'b00 ; + end + else + begin + raygroupid = 2'b00 ; + end + enablenear = 1'b0 ; + if (subcount == 2'b01 | count == 0) + begin + raygroupwe = 1'b1 ; + end + + temp_statepeek = 5'b01110 ; + // + + if (maskcount == 2'b11) + begin + // triID = triDataLatch(15 downto 0); + temp_triID = triDatalatch[15:0] ; + end + else if (maskcount == 2'b10) + begin + // triID = triDataLatch(31 downto 16); + temp_triID = triDatalatch[31:16] ; + end + else if (maskcount == 2'b01) + begin + // triID = triDataLatch(47 downto 32); + temp_triID = triDatalatch[47:32] ; + end + else + begin + // triID = triDataLatch(63 downto 48); + temp_triID = triDatalatch[63:48] ; + end + if (count != 0) + begin + temp_count = count - 1 ; + if (count != 1) + begin + temp_triIDvalid = 1'b1 ; + end + + if (maskcount == 2'b01) + begin + temp_tladdrvalid = 1'b1 ; + end + end + + end + 13 : + begin + next_state = 14 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b01111 ; + end + 14 : + begin + next_state = 12 ; + temp_busy = 1'b1 ; + temp_statepeek = 5'b10000 ; + // + + if (subcount != 0) + begin + temp_subcount = subcount - 1 ; + end + if (maskcount == 2'b11) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + temp_triDatalatch = tldata ; + end + temp_maskcount = maskcount + 1 ; + + end + 15 : + begin + if ((newdata == 1'b0 | resultID != 2'b00) & cts == 1'b1 & passCTSin == 1'b1) + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + else if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10001 ; + // + temp_tladdr = 0; + temp_tladdrvalid = 0; + if ((newdata == 0) | (resultID < 2'b00) & (passCTSin == 1)) + begin + temp_cts = 0; + temp_passCTSout = 1; + end + + end + 16 : + begin + if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == 1'b0) + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10010 ; + // + if ((passCTSin == 0) & ((newdata == 0) | (resultID == 1))) + begin + temp_passCTSout = 0; + end + + end + 17 : + begin + if (passCTSin == 1'b0) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10011 ; + // + if (passCTSin == 0) + begin + temp_passCTSout = 0; + end + + + end + 18 : + begin + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else if (cts == 1'b1 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + temp_statepeek = 5'b10100 ; + // + + + + if (hit1in == 1'b1 & (hitmask[0]) == 1'b1) + begin + temp_t1 = t1in; + temp_u1 = u1in; + temp_v1 = v1in; + temp_id1 = id1in; + temp_hit1 = 1'b1; + temp_hitmask[0] = 1'b0 ; + end + if (hit2in == 1'b1 & (hitmask[1]) == 1'b1) + begin + temp_t2 = t2in ; + temp_u2 = u2in ; + temp_v2 = v2in ; + temp_id2 = id2in ; + temp_hit2 = 1'b1 ; + temp_hitmask[1] = 1'b0 ; + end + if (hit3in == 1'b1 & (hitmask[2]) == 1'b1) + begin + temp_t3 = t3in ; + temp_u3 = u3in ; + temp_v3 = v3in ; + temp_id3 = id3in ; + temp_hit3 = 1'b1 ; + temp_hitmask[2] = 1'b0 ; + end + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + temp_passCTSout = 1'b1 ; + temp_cts = 1'b1 ; + end + + end + 19 : + begin + if (passCTSin == 1'b0) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10101 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + + end + endcase + end +endmodule + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg[0:0] count; + reg[0:0] temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(state or trigger or count) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + end + endcase + end + endmodule + + + + + + + + + + + module vblockramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, globalreset, clk); + + + output want_addr; + reg want_addr; + input addr_ready; + input[10 - 1:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[32 - 1:0] datain; + + input[10 - 1:0] addr; + input addrvalid; + output[32 - 1:0] data; + reg[32 - 1:0] data; + output datavalid; + reg datavalid; + input globalreset; + input clk; + + reg[2:0] state; + reg[2:0] next_state; + reg[10 - 1:0] waddr; + wire[10 - 1:0] saddr; + wire[32 - 1:0] dataout; + reg we; +reg [32 - 1:0]temp_data; +reg [10 - 1:0]temp_waddr ; +reg temp_datavalid; + + assign saddr = (state != 0) ? waddr : addr ; + + spramblock ramblock(we, saddr, datain, dataout, clk); + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + waddr <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + + begin + state <= next_state ; + data <= temp_data; + waddr <= temp_waddr ; + datavalid <= temp_datavalid; + end + end + + always @(state or addr_ready or data_ready or addrvalid or datavalid) + + begin + case (state) + 0 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + end + else + begin + next_state = 0 ; + end + if (addr_ready == 1'b1) + begin + temp_waddr = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + + end + + end + 5 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + + temp_data = dataout ; + + temp_datavalid = 1'b1 ; + + end + 1 : + begin + we = 1'b0 ; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + + end + end + 2 : + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + we = 1'b1 ; + + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + if (data_ready == 1'b1) + begin + temp_waddr = waddr + 1 ; + end + + end + 3 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + begin + next_state = 3 ; + + end + else + begin + next_state = 2 ; + end + end + 4 : + begin + we = 1'b0 ; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + + end + else + begin + next_state = 0 ; + end + end + endcase + end + endmodule + //----------------------------------------------------- + // Single Ported Ram Modual w/Registered Output -- + // - Synpify should infer ram from the coding style -- + // - Depth is the number of bits of address -- + // the true depth is 2**depth -- + + //----------------------------------------------------- + + //modifying this to black box ram implementation + + + module spramblock (we, addr, datain, dataout, clk); + + input we; + input[10 - 1:0] addr; + input[32 - 1:0] datain; + output[32 - 1:0] dataout; + wire[32 - 1:0] dataout; + input clk; + + + + +single_port_ram new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + +//--------------------------------------- +// A single-port 1024x32bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [9:0] addr, + input [31:0] data, + output [31:0] out ); + + reg [31:0] ram[1023:0]; + reg [31:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule + + + + + + + module sramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk, statepeek); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input[17:0] addr; + input addrvalid; + + output[63:0] data; + reg[63:0] data; + reg[63:0] temp_data; + output datavalid; + reg datavalid; + reg temp_datavalid; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + reg[2:0] temp_statepeek; + + reg[2:0] state; + reg[2:0] next_state; + reg[17:0] waddress; + reg[17:0] temp_waddress; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + + begin + state <= 0 ; + waddress <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + begin + state <= next_state ; + statepeek <= temp_statepeek; + data <=temp_data; + datavalid <=temp_datavalid; + waddress <= temp_waddress; + end + end + + always @(state or addr_ready or data_ready or waddress or datain or addrvalid or + datavalid or addr) + begin + case (state) + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + + tm3_sram_addr = {1'b0, addr} ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_oe = 2'b01 ; + end + + else + begin + next_state = 0 ; + end + + temp_statepeek = 3'b001 ; + if (addr_ready == 1'b1) + begin + temp_waddress = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + end + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + + temp_statepeek = 3'b010 ; + end + 2 : + begin + tm3_sram_oe = 2'b11 ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + tm3_sram_addr = {1'b0, waddress} ; + tm3_sram_data_xhdl0 = datain ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + + tm3_sram_we = 8'b00000000 ; + tm3_sram_adsp = 1'b0 ; + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b011 ; + if (data_ready == 1'b1) + + begin + temp_waddress = waddress + 1 ; + end + + end + 3 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + + begin + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b100 ; + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + + begin + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + temp_statepeek = 3'b101 ; + end + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + temp_statepeek = 3'b110 ; + temp_data = tm3_sram_data_in ; + temp_datavalid = 1'b1 ; + + end + + + endcase + end + endmodule + + + + + + + + + + + + + +module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, id3b, hit1b, hit2b, hit3b, resultID, newdata, resultready, resultdata, globalreset, clk); + + output[31:0] t1b; + reg[31:0] t1b; + output[31:0] t2b; + reg[31:0] t2b; + output[31:0] t3b; + reg[31:0] t3b; + output[15:0] u1b; + reg[15:0] u1b; + output[15:0] u2b; + reg[15:0] u2b; + + output[15:0] u3b; + reg[15:0] u3b; + output[15:0] v1b; + reg[15:0] v1b; + output[15:0] v2b; + reg[15:0] v2b; + output[15:0] v3b; + reg[15:0] v3b; + output[15:0] id1b; + reg[15:0] id1b; + output[15:0] id2b; + reg[15:0] id2b; + + output[15:0] id3b; + reg[15:0] id3b; + output hit1b; + reg hit1b; + output hit2b; + reg hit2b; + output hit3b; + reg hit3b; + output[1:0] resultID; + reg[1:0] resultID; + output newdata; + reg newdata; + + reg[31:0] temp_t1b; + reg[31:0] temp_t2b; + reg[31:0] temp_t3b; + reg[15:0] temp_u1b; + reg[15:0] temp_u2b; + reg[15:0] temp_u3b; + reg[15:0] temp_v1b; + reg[15:0] temp_v2b; + reg[15:0] temp_v3b; + reg[15:0] temp_id1b; + reg[15:0] temp_id2b; + reg[15:0] temp_id3b; + reg temp_hit1b; + reg temp_hit2b; + reg temp_hit3b; + reg[1:0] temp_resultID; + reg temp_newdata; + + input resultready; + input[31:0] resultdata; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + t1b <= 0; + t2b <= 0; + t3b <= 0; + u1b <= 0; + u2b <= 0; + u3b <= 0; + v1b <= 0; + + v2b <= 0; + v3b <= 0; + id1b <= 0; + id2b <= 0; + id3b <= 0; + hit1b <= 1'b0 ; + hit2b <= 1'b0 ; + hit3b <= 1'b0 ; + resultID <= 0; + newdata <= 1'b0 ; + end + else + begin + state <= next_state ; + + t1b <= temp_t1b; + newdata <= temp_newdata; + u1b <= temp_u1b; + v1b <= temp_v1b; + id1b <= temp_id1b; + hit1b <= temp_hit1b; + resultID <= temp_resultID; + t2b <= temp_t2b; + u2b <= temp_u2b; + id2b <= temp_id2b; + t3b <= temp_t3b; + u3b <= temp_u3b; + v3b <= temp_v3b; + id3b <= temp_id3b; + hit3b <= temp_hit3b; + v2b <= temp_v2b; + hit2b <= temp_hit2b; + end + end + + always @(state or resultready) + begin + case (state) + 0 : + begin + + if (resultready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_newdata = 1'b0 ; + if (resultready == 1'b1) + begin + temp_t1b = resultdata ; + end + + end + 1 : + begin + next_state = 2 ; + temp_newdata = 1'b0 ; + temp_u1b = resultdata[31:16] ; + temp_v1b = resultdata[15:0] ; + end + 2 : + begin + next_state = 3 ; + temp_newdata = 1'b0 ; + temp_id1b = resultdata[15:0] ; + temp_hit1b = resultdata[16] ; + temp_resultID = resultdata[18:17] ; + end + 3 : + begin + + next_state = 4 ; + temp_newdata = 1'b0 ; + temp_t2b = resultdata ; + end + 4 : + begin + next_state = 5 ; + temp_newdata = 1'b0 ; + temp_u2b = resultdata[31:16] ; + temp_v2b = resultdata[15:0] ; + end + 5 : + begin + next_state = 6 ; + temp_newdata = 1'b0 ; + temp_id2b = resultdata[15:0] ; + temp_hit2b = resultdata[16] ; + end + 6 : + begin + + next_state = 7 ; + temp_newdata = 1'b0 ; + temp_t3b = resultdata ; + end + 7 : + begin + next_state = 8 ; + temp_newdata = 1'b0 ; + temp_u3b = resultdata[31:16] ; + temp_v3b = resultdata[15:0] ; + end + 8 : + begin + next_state = 0 ; + temp_id3b = resultdata[15:0] ; + temp_hit3b = resultdata[16] ; + temp_newdata = 1'b1 ; + end + endcase + end + + endmodule + module rayinterface (raygroup, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, globalreset, clk); + + input[1:0] raygroup; + input raygroupwe; + input[1:0] raygroupid; + input enablenear; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + + input rgAddrValid; + output rgDone; + reg rgDone; + output[31:0] raydata; + reg[31:0] raydata; + output[3:0] rayaddr; + reg[3:0] rayaddr; + output[2:0] raywe; + reg[2:0] raywe; + input globalreset; + input clk; + + + reg[31:0] rgDatal; + reg[3:0] rgAddrl; + reg[2:0] rgWEl; + reg rgAddrValidl; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + raydata <= 0; + rayaddr <= 0; + raywe <= 0; + + rgDone <= 1'b0 ; + rgDatal <= 0; + rgAddrl <= 0; + rgWEl <= 0; + rgAddrValidl <= 1'b0 ; + end + else + begin + rgDatal <= rgData ; // Latch interchip signals + rgAddrl <= rgAddr ; // To Meet Timing + rgWEl <= rgWE ; + + rgAddrValidl <= rgAddrValid ; + + if (raygroupwe == 1'b1) + begin + raydata[0] <= enablenear ; + raydata[31:1] <= 0; + raywe <= 3'b111 ; + rayaddr <= {raygroupid, raygroup} ; + if (rgAddrValidl == 1'b0) + rgDone <= 1'b0 ; + end + else if (rgAddrValidl == 1'b1 & rgDone == 1'b0) + begin + raydata <= rgDatal ; + raywe <= rgWEl ; + rayaddr <= rgAddrl ; + rgDone <= 1'b1 ; + end + else + begin + raywe <= 0; + end + end + end + endmodule + + + + +module sortedstack (keyin, datain, write, reset, peekdata, globalreset, clk); + + input[32 - 1:0] keyin; + input[13 - 1:0] datain; + input write; + input reset; + output[13 * 8 - 1:0] peekdata; + + wire[13 * 8 - 1:0] peekdata; + wire big_reset; + input globalreset; + input clk; + + reg[32 - 1:0] key0; + reg[32 - 1:0] key1; + reg[32 - 1:0] key2; + reg[32 - 1:0] key3; + reg[32 - 1:0] key4; + reg[32 - 1:0] key5; + reg[32 - 1:0] key6; + reg[32 - 1:0] key7; + reg[13 - 1:0] data0; + reg[13 - 1:0] data1; + reg[13 - 1:0] data2; + reg[13 - 1:0] data3; + reg[13 - 1:0] data4; + reg[13 - 1:0] data5; + reg[13 - 1:0] data6; + reg[13 - 1:0] data7; + reg full0; + reg full1; + reg full2; + reg full3; + reg full4; + reg full5; + reg full6; + reg full7; + reg[2:0] location; + + assign peekdata[(0 + 1) * (13) - 1:0 * (13)] = ((full0) == 1'b1) ? data0 : 0; + assign peekdata[(1 + 1) * (13) - 1:1 * (13)] = ((full1) == 1'b1) ? data1 : 0; + assign peekdata[(2 + 1) * (13) - 1:2 * (13)] = ((full2) == 1'b1) ? data2 : 0; + assign peekdata[(3 + 1) * (13) - 1:3 * (13)] = ((full3) == 1'b1) ? data3 : 0; + assign peekdata[(4 + 1) * (13) - 1:4 * (13)] = ((full4) == 1'b1) ? data4 : 0; + assign peekdata[(5 + 1) * (13) - 1:5 * (13)] = ((full5) == 1'b1) ? data5 : 0; + assign peekdata[(6 + 1) * (13) - 1:6 * (13)] = ((full6) == 1'b1) ? data6 : 0; + assign peekdata[(7 + 1) * (13) - 1:7 * (13)] = ((full7) == 1'b1) ? data7 : 0; + + // Select the proper insertion point + always @(keyin or key0 or key1 or key2 or key3 or key4 or key5 or key6 or key7 or full0 or full1 or full2 or full3 or full4 or full5 or full6 or full7) + begin + +/* PAJ -- changed for loops */ + if ((keyin < key0) | ((full0) == 1'b0)) + begin + location = 0 ; + end + else if ((keyin < key1) | ((full1) == 1'b0)) + begin + location = 1 ; + end + else if ((keyin < key2) | ((full2) == 1'b0)) + begin + location = 2 ; + end + else if ((keyin < key3) | ((full3) == 1'b0)) + begin + location = 3 ; + end + else if ((keyin < key4) | ((full4) == 1'b0)) + begin + location = 4 ; + end + else if ((keyin < key5) | ((full5) == 1'b0)) + begin + location = 5 ; + end + else if ((keyin < key6) | ((full6) == 1'b0)) + begin + location = 6 ; + end + else + begin + location = 7; + end + end + + assign big_reset = globalreset | reset; + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + full0 <= 1'b0 ; + key0 <= 0; + data0 <= 0; + full1 <= 1'b0 ; + key1 <= 0; + data1 <= 0; + full2 <= 1'b0 ; + key2 <= 0; + data2 <= 0; + full3 <= 1'b0 ; + key3 <= 0; + data3 <= 0; + full4 <= 1'b0 ; + key4 <= 0; + data4 <= 0; + full5 <= 1'b0 ; + key5 <= 0; + data5 <= 0; + full6 <= 1'b0 ; + key6 <= 0; + data6 <= 0; + full7 <= 1'b0 ; + key7 <= 0; + data7 <= 0; + end + else + begin + if (write == 1'b1) + begin + if (location == 0) + begin + key0 <= keyin; + data0 <= datain; + full0 <= 1'b1; + key1 <= key0; + data1 <= data0; + full1 <= full0; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 1) + begin + key1 <= keyin; + data1 <= datain; + full1 <= 1'b1; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key2 <= keyin; + data2 <= datain; + full2 <= 1'b1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key3 <= keyin; + data3 <= datain; + full3 <= 1'b1; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 4) + begin + key4 <= keyin; + data4 <= datain; + full4 <= 1'b1; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 5) + begin + key5 <= keyin; + data5 <= datain; + full5 <= 1'b1; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 6) + begin + key6 <= keyin; + data6 <= datain; + full6 <= 1'b1; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 7) + begin + key7 <= keyin; + data7 <= datain; + full7 <= 1'b1; + end + end + end +end +endmodule + + + + +module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty, dataready, reset, globalreset, clk, peekoffset0, peekoffset1, peekoffset2, peekhit, peekstate); + + input[8 * 13 - 1:0] dataarrayin; + input commit; + input[2:0] hitmask; + input ack; + output[9:0] boundnodeID; + wire[9:0] boundnodeID; + output[1:0] level; + wire[1:0] level; + + output empty; + wire empty; + output dataready; + wire dataready; + input reset; + input globalreset; + input clk; + output[2:0] peekoffset0; + wire[2:0] peekoffset0; + output[2:0] peekoffset1; + wire[2:0] peekoffset1; + output[2:0] peekoffset2; + + wire[2:0] peekoffset2; + output peekhit; + wire peekhit; + output[1:0] peekstate; + reg[1:0] peekstate; + reg[1:0] temp_peekstate; + + reg[1:0] next_state; + reg[1:0] state; + reg[1:0] readlevel; + + reg[1:0] writelevel; + reg[2:0] offset0; + reg[2:0] offset1; + reg[2:0] offset2; + reg[4:0] address; + reg we; + reg[12:0] datain; + wire[12:0] dataout; + reg[2:0] lvempty; + reg busy; + reg temp_busy; + reg[2:0] temp_lvempty; + reg[1:0] temp_readlevel; + reg[1:0] temp_writelevel; + reg[2:0] temp_offset0; + reg[2:0] temp_offset1; + reg[2:0] temp_offset2; + + // Debug Stuff + + assign peekoffset0 = offset0 ; + assign peekoffset1 = offset1 ; + assign peekoffset2 = offset2 ; + assign peekhit = ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) ? 1'b1 : 1'b0 ; + + // Real Code + + spram ram(we, dataout, datain, clk); + + assign level = readlevel ; + assign boundnodeID = dataout[9:0] ; + + assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; + assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; + + always @(offset0 or offset1 or offset2 or address) + begin + address[4:3] = readlevel ; + + if (address[4:3] == 2'b00) + begin + address[2:0] = offset0 ; + end + else if (address[4:3] == 2'b01) + begin + + address[2:0] = offset1 ; + end + else if (address[4:3] == 2'b10) + begin + address[2:0] = offset2 ; + end + else + begin + address[2:0] = 0; + end + end + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + lvempty <= 1; + busy <= 1'b0 ; + readlevel <= 2'b00 ; + writelevel <= 2'b00 ; + offset0 <= 3'b000 ; + offset1 <= 3'b000 ; + offset2 <= 3'b000 ; + + end + else + begin + state <= next_state ; + peekstate <= temp_peekstate ; + busy <= temp_busy; + lvempty <= temp_lvempty; + readlevel <= temp_readlevel; + writelevel <= temp_writelevel; + offset0 <= temp_offset0; + offset1 <= temp_offset1; + offset2 <= temp_offset2; + + end + end + + always @(state or commit or ack or address or dataarrayin or reset or dataready or + empty) + begin + + case (state) + 2'b00 : + begin + we = 1'b0 ; + datain = 0; + if (reset == 1'b1) + begin + next_state = 0 ; + end + else if (commit == 1'b1) + begin + next_state = 1 ; + end + else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + temp_peekstate = 2'b01 ; + + if (reset == 1'b1) + begin + temp_busy = 1'b0 ; + temp_lvempty = 1; + temp_readlevel = 2'b00 ; + + temp_writelevel = 2'b00 ; + temp_offset0 = 3'b000 ; + temp_offset1 = 3'b000 ; + temp_offset2 = 3'b000 ; + end + else if (commit == 1'b1) + begin + temp_busy = 1'b1 ; + if (writelevel == 2'b00) + begin + temp_offset0 = 3'b000 ; + end + + else if (writelevel == 2'b01) + begin + temp_offset1 = 3'b000 ; + end + else if (writelevel == 2'b10) + begin + temp_offset2 = 3'b000 ; + end + temp_readlevel = writelevel ; + end + + else if (ack == 1'b1) + begin + temp_writelevel = readlevel + 1 ; + temp_busy = 1'b1 ; // This will ensure that align skips one + end + + end + 2'b01 : + begin +/* PAJ -- Unrolled loop */ + if (address[2:0] == 0) + begin + datain = dataarrayin[(1) * 13 - 1:0 * 13] ; + end + else if ( address[2:0] == 1) + begin + datain = dataarrayin[(2) * 13 - 1:1 * 13] ; + end + else if ( address[2:0] ==2) + begin + datain = dataarrayin[(3) * 13 - 1:2 * 13] ; + end + else if ( address[2:0] ==3) + begin + datain = dataarrayin[(4) * 13 - 1:3 * 13] ; + end + else if ( address[2:0] ==4) + begin + datain = dataarrayin[(5) * 13 - 1:4 * 13] ; + end + else if ( address[2:0] ==5) + begin + datain = dataarrayin[(6) * 13 - 1:5 * 13] ; + end + else if ( address[2:0] ==6) + begin + datain = dataarrayin[(7) * 13 - 1:6 * 13] ; + end + else if ( address[2:0] ==7) + begin + datain = dataarrayin[(8) * 13 - 1:7 * 13] ; + end + + + we = 1'b1 ; + if (address[2:0] == 3'b111) + begin + next_state = 2 ; + + end + else + begin + next_state = 1 ; + end + temp_peekstate = 2'b10 ; + + if (readlevel == 2'b00) + begin + temp_offset0 = offset0 + 1 ; + end + + else if (readlevel == 2'b01) + begin + temp_offset1 = offset1 + 1 ; + end + else if (readlevel == 2'b10) + begin + temp_offset2 = offset2 + 1 ; + end + if (address[2:0] == 3'b111) + begin + temp_busy = 1'b0 ; + end + + if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) + begin + if (readlevel == 2'b00) + begin + temp_lvempty[0] = 1'b0 ; + end + else if (readlevel == 2'b01) + begin + temp_lvempty[1] = 1'b0 ; + end + else if (readlevel == 2'b10) + begin + + temp_lvempty[2] = 1'b0 ; + end + end + + end + 2'b10 : + begin + if (empty == 1'b0 & dataready == 1'b0) + begin + next_state = 2 ; + end + else + next_state = 0 ; + + temp_peekstate = 2'b11 ; + temp_busy = 1'b0 ; + if (empty == 1'b0 & dataready == 1'b0) + begin + if (readlevel == 2'b00) + begin + if (offset0 == 3'b111) + begin + temp_lvempty[0] = 1'b1 ; + end + else + begin + temp_offset0 = offset0 + 1 ; + end + end + else if (readlevel == 2'b01) + begin + if (offset1 == 3'b111) + begin + temp_lvempty[1] = 1'b1 ; + temp_readlevel = 2'b00 ; + end + else + begin + temp_offset1 = offset1 + 1 ; + end + end + else if (readlevel == 2'b10) + begin + if (offset2 == 3'b111) + begin + temp_lvempty[2] = 1'b1 ; + if ((lvempty[1]) == 1'b1) + begin + temp_readlevel = 2'b00 ; + end + else + begin + temp_readlevel = 2'b01 ; + end + end + else + begin + temp_offset2 = offset2 + 1 ; + end + end + end + end + endcase +end +endmodule + + + + module spram (we, dataout, datain, clk); + + input we; + output[13 - 1:0] dataout; + wire[13 - 1:0] dataout; + input[13 - 1:0] datain; + input clk; + reg[13 - 1:0] temp_reg; + + reg[13 - 1:0] mem1; + reg[13 - 1:0] mem2; + + assign dataout = mem2 ; + + always @(posedge clk) + begin + temp_reg <= 0; + if (we == 1'b1) + begin + mem1 <= datain + temp_reg; + mem2 <= mem1; + end + end + endmodule + module resultcounter (resultID, newresult, done, reset, globalreset, clk); + + input[1:0] resultID; + input newresult; + output[1:0] done; + wire[1:0] done; + input reset; + input globalreset; + input clk; + + wire big_reset; + + reg[3:0] count; + reg[1:0] curr; + + assign done = (count == 0) ? curr : 2'b00 ; + assign big_reset = globalreset | reset; + + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + count <= 4'b1000 ; + curr <= 0; + end + else + begin + if ((resultID != 0) & (newresult == 1'b1) & (count != 0)) + begin + count <= count - 1 ; + curr <= resultID ; + end + end + end + endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v b/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v new file mode 100755 index 000000000..327e10fe2 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v @@ -0,0 +1,317 @@ + + +`define MEMORY_CONTROLLER_TAGS 1 +`define MEMORY_CONTROLLER_TAG_SIZE 1 +`define TAG__str 1'b0 +`define MEMORY_CONTROLLER_ADDR_SIZE 32 +`define MEMORY_CONTROLLER_DATA_SIZE 32 + + +module memory_controller +( + clk, + memory_controller_address, + memory_controller_write_enable, + memory_controller_in, + memory_controller_out +); +input clk; +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +input memory_controller_write_enable; +input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + + +reg [4:0] str_address; +reg str_write_enable; +reg [7:0] str_in; +wire [7:0] str_out; + +single_port_ram _str ( + .clk( clk ), + .addr( str_address ), + .we( str_write_enable ), + .data( str_in ), + .out( str_out ) +); + + +wire tag; + +//must use all wires inside module..... +assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in; +reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; +always @(posedge clk) + prevTag <= tag; +always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in) +begin + +case(tag) + + 1'b0: + begin + str_address = memory_controller_address[5-1+0:0]; + str_write_enable = memory_controller_write_enable; + str_in[8-1:0] = memory_controller_in[8-1:0]; + end +endcase + +case(prevTag) + + 1'b0: + memory_controller_out = str_out; +endcase +end + +endmodule + + +module memset + ( + clk, + reset, + start, + finish, + return_val, + m, + c, + n, + memory_controller_write_enable, + memory_controller_address, + memory_controller_in, + memory_controller_out + ); + +output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +input clk; +input reset; +input start; + +output finish; +reg finish; + +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m; +input [31:0] c; +input [31:0] n; + +output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; + +output memory_controller_write_enable; +reg memory_controller_write_enable; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + +reg [3:0] cur_state; + +/* +parameter Wait = 4'd0; +parameter entry = 4'd1; +parameter entry_1 = 4'd2; +parameter entry_2 = 4'd3; +parameter bb = 4'd4; +parameter bb_1 = 4'd5; +parameter bb1 = 4'd6; +parameter bb1_1 = 4'd7; +parameter bb_nph = 4'd8; +parameter bb2 = 4'd9; +parameter bb2_1 = 4'd10; +parameter bb2_2 = 4'd11; +parameter bb2_3 = 4'd12; +parameter bb2_4 = 4'd13; +parameter bb4 = 4'd14; +*/ + +memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out); + + +reg [31:0] indvar; +reg var1; +reg [31:0] tmp; +reg [31:0] tmp8; +reg var2; +reg [31:0] var0; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07; +reg [31:0] indvar_next; +reg exitcond; + +always @(posedge clk) +if (reset) + cur_state <= 4'b0000; +else +case(cur_state) + 4'b0000: + begin + finish <= 1'b0; + if (start == 1'b1) + cur_state <= 4'b0001; + else + cur_state <= 4'b0000; + end + 4'b0001: + begin + + + + var0 <= n & 32'b00000000000000000000000000000011; + + cur_state <= 4'b0010; + end + 4'b0010: + begin + + var1 <= 1'b0; + var0 <= 32'b00000000000000000000000000000000; + + cur_state <= 4'b0011; + end + 4'b0011: + begin + + + if (|var1) begin + cur_state <= 4'b0110; + end + else + begin + + cur_state <= 4'b0100; + end + end + 4'b0100: + begin + + cur_state <= 4'b0101; + end + 4'b0101: + begin + cur_state <= 4'b0110; + end + 4'b0110: + begin + + var2 <= | (n [31:4]); + + cur_state <= 4'b0111; + end + 4'b0111: + begin + + if (|var2) + begin + cur_state <= 4'b1110; + end + else + begin + cur_state <= 4'b1000; + end + end + 4'b1000: + begin + + tmp <= n ; + + indvar <= 32'b00000000000000000000000000000000; + cur_state <= 4'b1001; + end + 4'b1001: + begin + + cur_state <= 4'b1010; + end + 4'b1010: + begin + tmp8 <= indvar; + indvar_next <= indvar; + cur_state <= 4'b1011; + end + 4'b1011: + begin + + scevgep <= (m & tmp8); + + exitcond <= (indvar_next == tmp); + + cur_state <= 4'b1100; + end + 4'b1100: + begin + + s_07 <= scevgep; + + cur_state <= 4'b1101; + end + 4'b1101: + + begin + + + if (exitcond) + begin + cur_state <= 4'b1110; + end + else + begin + indvar <= indvar_next; + cur_state <= 4'b1001; + end + end + + + 4'b1110: + begin + + return_val <= m; + finish <= 1'b1; + cur_state <= 4'b0000; + end +endcase + +always @(cur_state) +begin + + case(cur_state) + 4'b1101: + begin + memory_controller_address = s_07; + memory_controller_write_enable = 1'b1; + memory_controller_in = c; + end + endcase +end + +endmodule + +//--------------------------------------- +// A single-port 32x8bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [4:0] addr, + input [7:0] data, + output [7:0] out ); + + reg [7:0] ram[31:0]; + reg [7:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v b/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v new file mode 100755 index 000000000..b4033369c --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v @@ -0,0 +1,56 @@ + module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, clk, reset); + input[31:0] Xinport; + input[31:0] Yinport; + input[31:0] Uinport; + input[31:0] Aport; + input[31:0] DXport; + input clk; + input reset; + output[31:0] Xoutport; + output[31:0] Youtport; + output[31:0] Uoutport; + reg[31:0] Xoutport; + reg[31:0] Youtport; + reg[31:0] Uoutport; + + reg[31:0] x_var; + reg[31:0] y_var; + reg[31:0] u_var; + wire[31:0] temp; + reg looping; + +assign temp = u_var * DXport; + always @(posedge clk) + begin + if (reset == 1'b1) + begin + looping <= 1'b0; + x_var <= 0; + y_var <= 0; + u_var <= 0; + end + else + if (looping == 1'b0) + begin + x_var <= Xinport; + y_var <= Yinport; + u_var <= Uinport; + looping <= 1'b1; + end + else if (x_var < Aport) + begin + u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var); + y_var <= y_var + temp;//(u_var * DXport); + x_var <= x_var + DXport; + looping <= looping; + end + else + begin + Xoutport <= x_var ; + Youtport <= y_var ; + Uoutport <= u_var ; + looping <= 1'b0; + end + end + endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v b/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v new file mode 100755 index 000000000..f88fab260 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v @@ -0,0 +1,63 @@ + +/*-------------------------------------------------------------------------- +-------------------------------------------------------------------------- +-- File Name : diffeq.v +-- Author(s) : P. Sridhar +-- Affiliation : Laboratory for Digital Design Environments +-- Department of Electrical & Computer Engineering +-- University of Cincinnati +-- Date Created : June 1991. +-- Introduction : Behavioral description of a differential equation +-- solver written in a synthesizable subset of VHDL. +-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ. +-- Obtained from the Highlevel Synthesis Workshop +-- Repository. +-- +-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati. +-- Date Modified : Sept, 91. +-- +-- Disclaimer : This comes with absolutely no guarantees of any +-- kind (just stating the obvious ...) +-- +-- Acknowledgement : The Distributed Synthesis Systems research at +-- the Laboratory for Digital Design Environments, +-- University of Cincinnati, is sponsored in part +-- by the Defense Advanced Research Projects Agency +-- under order number 7056 monitored by the Federal +-- Bureau of Investigation under contract number +-- J-FBI-89-094. +-- +-------------------------------------------------------------------------- +-------------------------------------------------------------------------*/ +module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset); + +input clk; +input reset; +input [31:0]aport; +input [31:0]dxport; +output [31:0]xport; +output [31:0]yport; +output [31:0]uport; +reg [31:0]xport; +reg [31:0]yport; +reg [31:0]uport; +wire [31:0]temp; + +assign temp = uport * dxport; +always @(posedge clk ) +begin + if (reset == 1'b1) + begin + xport <= 0; + yport <= 0; + uport <= 0; + end +else + if (xport < aport) + begin + xport <= xport + dxport; + yport <= yport + temp;//(uport * dxport); + uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport)); + end +end +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v b/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v new file mode 100644 index 000000000..70d0b1dcb --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v @@ -0,0 +1,1662 @@ +//////////////////////////////////////////////// +// Matrix multiplication design +// Multiplies 8x8 matrix (A) with another 8x8 matrix (B) +// to produce an 8x8 matrix (C). +// Data precision is IEEE floating point 16-bit (half precision) +// The architecture is systolic in nature (output stationary). +// 4 4x4 matmuls composed to make a larger 8x8 matmul. +// There is state machine for control and an APB +// interface for programming/configuring. +// Matrices are stores in RAM blocks. +/////////////////////////////////////////////// + +`timescale 1ns/1ns + +`define DWIDTH 16 +`define AWIDTH 10 +`define MEM_SIZE 1024 +`define DESIGN_SIZE 8 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 16 +`define REG_STDN_TPU_ADDR 32'h4 +`define REG_MATRIX_A_ADDR 32'he +`define REG_MATRIX_B_ADDR 32'h12 +`define REG_MATRIX_C_ADDR 32'h16 +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 + +module matrix_multiplication( + input clk, + input clk_mem, + input resetn, + input pe_resetn, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + input [7:0] bram_select, + input [`AWIDTH-1:0] bram_addr_ext, + output reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_ext, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_ext, + input [`MAT_MUL_SIZE-1:0] bram_we_ext +); + + + wire PCLK; + assign PCLK = clk; + reg start_reg; + reg clear_done_reg; + //Dummy register to sync all other invalid/unimplemented addresses + reg [`REG_DATAWIDTH-1:0] reg_dummy; + + reg [`AWIDTH-1:0] bram_addr_a_0_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_0_0_ext; + + reg [`AWIDTH-1:0] bram_addr_a_1_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_1_0_ext; + + reg [`AWIDTH-1:0] bram_addr_b_0_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_0_ext; + + reg [`AWIDTH-1:0] bram_addr_b_0_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_1_ext; + + reg [`AWIDTH-1:0] bram_addr_c_0_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_0_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_0_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_0_1_ext; + + reg [`AWIDTH-1:0] bram_addr_c_1_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_1_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_1_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_1_1_ext; + + wire [`AWIDTH-1:0] bram_addr_a_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0_0; + wire [`MASK_WIDTH-1:0] bram_we_a_0_0; + wire bram_en_a_0_0; + + wire [`AWIDTH-1:0] bram_addr_a_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1_0; + wire [`MASK_WIDTH-1:0] bram_we_a_1_0; + wire bram_en_a_1_0; + + wire [`AWIDTH-1:0] bram_addr_b_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_0; + wire [`MASK_WIDTH-1:0] bram_we_b_0_0; + wire bram_en_b_0_0; + + wire [`AWIDTH-1:0] bram_addr_b_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_1; + wire [`MASK_WIDTH-1:0] bram_we_b_0_1; + wire bram_en_b_0_1; + + wire [`AWIDTH-1:0] bram_addr_c_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_0_1; + wire [`MASK_WIDTH-1:0] bram_we_c_0_1; + wire bram_en_c_0_1; + + wire [`AWIDTH-1:0] bram_addr_c_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_1_1; + wire [`MASK_WIDTH-1:0] bram_we_c_1_1; + wire bram_en_c_1_1; + + always @* begin + case (bram_select) + + 0: begin + bram_addr_a_0_0_ext = bram_addr_ext; + bram_wdata_a_0_0_ext = bram_wdata_ext; + bram_we_a_0_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_a_0_0_ext; + end + + 1: begin + bram_addr_a_1_0_ext = bram_addr_ext; + bram_wdata_a_1_0_ext = bram_wdata_ext; + bram_we_a_1_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_a_1_0_ext; + end + + 2: begin + bram_addr_b_0_0_ext = bram_addr_ext; + bram_wdata_b_0_0_ext = bram_wdata_ext; + bram_we_b_0_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_b_0_0_ext; + end + + 3: begin + bram_addr_b_0_1_ext = bram_addr_ext; + bram_wdata_b_0_1_ext = bram_wdata_ext; + bram_we_b_0_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_b_0_1_ext; + end + + 4: begin + bram_addr_c_0_1_ext = bram_addr_ext; + bram_wdata_c_0_1_ext = bram_wdata_ext; + bram_we_c_0_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_c_0_1_ext; + end + + 5: begin + bram_addr_c_1_1_ext = bram_addr_ext; + bram_wdata_c_1_1_ext = bram_wdata_ext; + bram_we_c_1_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_c_1_1_ext; + end + + default: begin + bram_rdata_ext = 0; + end + endcase + end + +///////////////////////////////////////////////// +// BRAMs to store matrix A +///////////////////////////////////////////////// + +// BRAM matrix A 0_0 (bank0) +ram matrix_A_0_0( + .addr0(bram_addr_a_0_0), + .d0(bram_wdata_a_0_0), + .we0(bram_we_a_0_0), + .q0(bram_rdata_a_0_0), + .addr1(bram_addr_a_0_0_ext), + .d1(bram_wdata_a_0_0_ext), + .we1(bram_we_a_0_0_ext), + .q1(bram_rdata_a_0_0_ext), + .clk(clk_mem)); + +// BRAM matrix A 1_0 (bank1) +ram matrix_A_1_0( + .addr0(bram_addr_a_1_0), + .d0(bram_wdata_a_1_0), + .we0(bram_we_a_1_0), + .q0(bram_rdata_a_1_0), + .addr1(bram_addr_a_1_0_ext), + .d1(bram_wdata_a_1_0_ext), + .we1(bram_we_a_1_0_ext), + .q1(bram_rdata_a_1_0_ext), + .clk(clk_mem)); + +///////////////////////////////////////////////// +// BRAMs to store matrix B +///////////////////////////////////////////////// + +// BRAM matrix B 0_0 (bank0) +ram matrix_B_0_0( + .addr0(bram_addr_b_0_0), + .d0(bram_wdata_b_0_0), + .we0(bram_we_b_0_0), + .q0(bram_rdata_b_0_0), + .addr1(bram_addr_b_0_0_ext), + .d1(bram_wdata_b_0_0_ext), + .we1(bram_we_b_0_0_ext), + .q1(bram_rdata_b_0_0_ext), + .clk(clk_mem)); + +// BRAM matrix B 0_1 (bank1) +ram matrix_B_0_1( + .addr0(bram_addr_b_0_1), + .d0(bram_wdata_b_0_1), + .we0(bram_we_b_0_1), + .q0(bram_rdata_b_0_1), + .addr1(bram_addr_b_0_1_ext), + .d1(bram_wdata_b_0_1_ext), + .we1(bram_we_b_0_1_ext), + .q1(bram_rdata_b_0_1_ext), + .clk(clk_mem)); + +///////////////////////////////////////////////// +// BRAMs to store matrix C +///////////////////////////////////////////////// + + +// BRAM matrix C 0_1 (bank0) +ram matrix_C_0_1( + .addr0(bram_addr_c_0_1), + .d0(bram_wdata_c_0_1), + .we0(bram_we_c_0_1), + .q0(bram_rdata_c_0_1), + .addr1(bram_addr_c_0_1_ext), + .d1(bram_wdata_c_0_1_ext), + .we1(bram_we_c_0_1_ext), + .q1(bram_rdata_c_0_1_ext), + .clk(clk_mem)); + +// BRAM matrix C 1_1 (bank1) +ram matrix_C_1_1( + .addr0(bram_addr_c_1_1), + .d0(bram_wdata_c_1_1), + .we0(bram_we_c_1_1), + .q0(bram_rdata_c_1_1), + .addr1(bram_addr_c_1_1_ext), + .d1(bram_wdata_c_1_1_ext), + .we1(bram_we_c_1_1_ext), + .q1(bram_rdata_c_1_1_ext), + .clk(clk_mem)); + +reg start_mat_mul; +wire done_mat_mul; + +reg [3:0] state; + +//////////////////////////////////////////////////////////////// +// Control logic +//////////////////////////////////////////////////////////////// +always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 4'b0000; + start_mat_mul <= 1'b0; + end + else begin + case (state) + + 4'b0000: begin + start_mat_mul <= 1'b0; + if (start_reg == 1'b1) begin + state <= 4'b0001; + end else begin + state <= 4'b0000; + end + end + + 4'b0001: begin + start_mat_mul <= 1'b1; + state <= 4'b1010; + end + + 4'b1010: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + state <= 4'b1000; + end + else begin + state <= 4'b1010; + end + end + + 4'b1000: begin + if (clear_done_reg == 1'b1) begin + state <= 4'b0000; + end + else begin + state <= 4'b1000; + end + end + endcase +end +end + +reg [1:0] state_apb; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +reg [`AWIDTH-1:0] address_mat_a; +reg [`AWIDTH-1:0] address_mat_b; +reg [`AWIDTH-1:0] address_mat_c; +reg [`MASK_WIDTH-1:0] validity_mask_a_rows; +reg [`MASK_WIDTH-1:0] validity_mask_a_cols; +reg [`MASK_WIDTH-1:0] validity_mask_b_rows; +reg [`MASK_WIDTH-1:0] validity_mask_b_cols; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + +//////////////////////////////////////////////////////////////// +// Configuration logic +//////////////////////////////////////////////////////////////// +always @(posedge PCLK) begin + if (PRESETn == 0) begin + state_apb <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + address_stride_a <= `MAT_MUL_SIZE; + address_stride_b <= `MAT_MUL_SIZE; + address_stride_c <= `MAT_MUL_SIZE; + end + + else begin + case (state_apb) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + state_apb <= `W_ENABLE; + end + else begin + state_apb <= `R_ENABLE; + end + end + PREADY <= 0; + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_STDN_TPU_ADDR : begin + start_reg <= PWDATA[0]; + clear_done_reg <= PWDATA[31]; + end + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + default : reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + state_apb <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_STDN_TPU_ADDR : PRDATA <= {done_mat_mul, 30'b0, start_mat_mul}; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + state_apb <= `IDLE; + end + default: begin + state_apb <= `IDLE; + end + endcase + end +end + +wire reset; +assign reset = ~resetn; +wire pe_reset; +assign pe_reset = ~pe_resetn; + +wire c_data_0_1_available; +assign bram_en_c_0_1 = 1'b1; +assign bram_we_c_0_1 = (c_data_0_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + +wire c_data_1_1_available; +assign bram_en_c_1_1 = 1'b1; +assign bram_we_c_1_1 = (c_data_1_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_a_0_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_a_0_0 = 1'b1; +assign bram_we_a_0_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_a_1_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_a_1_0 = 1'b1; +assign bram_we_a_1_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_b_0_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b_0_0 = 1'b1; +assign bram_we_b_0_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_b_0_1 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b_0_1 = 1'b1; +assign bram_we_b_0_1 = {`MASK_WIDTH{1'b0}}; + + +///////////////////////////////////////////////// +// The 8x8 matmul instantiation +///////////////////////////////////////////////// + +matmul_8x8_systolic u_matmul_8x8_systolic ( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + + .a_data_0_0(bram_rdata_a_0_0), + .b_data_0_0(bram_rdata_b_0_0), + .a_addr_0_0(bram_addr_a_0_0), + .b_addr_0_0(bram_addr_b_0_0), + + .a_data_1_0(bram_rdata_a_1_0), + .b_data_0_1(bram_rdata_b_0_1), + .a_addr_1_0(bram_addr_a_1_0), + .b_addr_0_1(bram_addr_b_0_1), + + .c_data_0_1(bram_wdata_c_0_1), + .c_addr_0_1(bram_addr_c_0_1), + .c_data_0_1_available(c_data_0_1_available), + + .c_data_1_1(bram_wdata_c_1_1), + .c_addr_1_1(bram_addr_c_1_1), + .c_data_1_1_available(c_data_1_1_available), + + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols) +); +endmodule + +///////////////////////////////////////////////// +// The 8x8 matmul definition +///////////////////////////////////////////////// + +module matmul_8x8_systolic( + input clk, + input reset, + input pe_reset, + input start_mat_mul, + output done_mat_mul, + + input [`AWIDTH-1:0] address_mat_a, + input [`AWIDTH-1:0] address_mat_b, + input [`AWIDTH-1:0] address_mat_c, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_0, + output [`AWIDTH-1:0] a_addr_0_0, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_0, + output [`AWIDTH-1:0] b_addr_0_0, + + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_0, + output [`AWIDTH-1:0] a_addr_1_0, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_1, + output [`AWIDTH-1:0] b_addr_0_1, + + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_1, + output [`AWIDTH-1:0] c_addr_0_1, + output c_data_0_1_available, + + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_1, + output [`AWIDTH-1:0] c_addr_1_1, + output c_data_1_1_available, + + input [`MASK_WIDTH-1:0] validity_mask_a_rows, + input [`MASK_WIDTH-1:0] validity_mask_a_cols, + input [`MASK_WIDTH-1:0] validity_mask_b_rows, + input [`MASK_WIDTH-1:0] validity_mask_b_cols +); + + ///////////////////////////////////////////////// + // ORing all done signals + ///////////////////////////////////////////////// + wire done_mat_mul_0_0; + wire done_mat_mul_0_1; + wire done_mat_mul_1_0; + wire done_mat_mul_1_1; + + assign done_mat_mul = done_mat_mul_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_1_NC; + + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_1_NC; + ///////////////////////////////////////////////// + // Matmul 0_0 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_0_to_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_0_to_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_0_0_NC; + assign a_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_0_0_NC; + assign c_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_0_0_NC; + assign b_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_0_to_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_0_to_0_1_NC; + wire [`AWIDTH-1:0] c_addr_0_0_NC; + wire c_data_0_0_available_NC; + +matmul_4x4_systolic u_matmul_4x4_systolic_0_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_0_0), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_0_0), + .b_data(b_data_0_0), + .a_data_in(a_data_in_0_0_NC), + .b_data_in(b_data_in_0_0_NC), + .c_data_in(c_data_in_0_0_NC), + .c_data_out(c_data_0_0_to_0_1_NC), + .a_data_out(a_data_0_0_to_0_1), + .b_data_out(b_data_0_0_to_1_0), + .a_addr(a_addr_0_0), + .b_addr(b_addr_0_0), + .c_addr(c_addr_0_0_NC), + .c_data_available(c_data_0_0_available_NC), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd0), + .b_loc(8'd0) +); + + ///////////////////////////////////////////////// + // Matmul 0_1 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_1_to_0_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_1_to_1_1; + wire [`AWIDTH-1:0] a_addr_0_1_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_1_NC; + assign a_data_0_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_0_1_NC; + assign b_data_in_0_1_NC = 0; + +matmul_4x4_systolic u_matmul_4x4_systolic_0_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_0_1), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_0_1_NC), + .b_data(b_data_0_1), + .a_data_in(a_data_0_0_to_0_1), + .b_data_in(b_data_in_0_1_NC), + .c_data_in(c_data_0_0_to_0_1), + .c_data_out(c_data_0_1), + .a_data_out(a_data_0_1_to_0_2), + .b_data_out(b_data_0_1_to_1_1), + .a_addr(a_addr_0_1_NC), + .b_addr(b_addr_0_1), + .c_addr(c_addr_0_1), + .c_data_available(c_data_0_1_available), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd0), + .b_loc(8'd1) +); + + ///////////////////////////////////////////////// + // Matmul 1_0 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_0_to_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_0_to_2_0; + wire [`AWIDTH-1:0] b_addr_1_0_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_0_NC; + assign b_data_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_1_0_NC; + assign a_data_in_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_1_0_NC; + assign c_data_in_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_0_to_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_0_to_1_1_NC; + wire [`AWIDTH-1:0] c_addr_1_0_NC; + wire c_data_1_0_available_NC; + +matmul_4x4_systolic u_matmul_4x4_systolic_1_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_1_0), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_1_0), + .b_data(b_data_1_0_NC), + .a_data_in(a_data_in_1_0_NC), + .b_data_in(b_data_0_0_to_1_0), + .c_data_in(c_data_in_1_0_NC), + .c_data_out(c_data_1_0_to_1_1_NC), + .a_data_out(a_data_1_0_to_1_1), + .b_data_out(b_data_1_0_to_2_0), + .a_addr(a_addr_1_0), + .b_addr(b_addr_1_0_NC), + .c_addr(c_addr_1_0_NC), + .c_data_available(c_data_1_0_available_NC), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd1), + .b_loc(8'd0) +); + + ///////////////////////////////////////////////// + // Matmul 1_1 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_1_to_1_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_1_to_2_1; + wire [`AWIDTH-1:0] a_addr_1_1_NC; + wire [`AWIDTH-1:0] b_addr_1_1_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_1_NC; + assign a_data_1_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_1_NC; + assign b_data_1_1_NC = 0; + +matmul_4x4_systolic u_matmul_4x4_systolic_1_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_1_1), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_1_1_NC), + .b_data(b_data_1_1_NC), + .a_data_in(a_data_1_0_to_1_1), + .b_data_in(b_data_0_1_to_1_1), + .c_data_in(c_data_1_0_to_1_1), + .c_data_out(c_data_1_1), + .a_data_out(a_data_1_1_to_1_2), + .b_data_out(b_data_1_1_to_2_1), + .a_addr(a_addr_1_1_NC), + .b_addr(b_addr_1_1_NC), + .c_addr(c_addr_1_1), + .c_data_available(c_data_1_1_available), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd1), + .b_loc(8'd1) +); + +endmodule + + +////////////////////////////////// +//Dual port RAM +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d0; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d1; +input [`MAT_MUL_SIZE-1:0] we0; +input [`MAT_MUL_SIZE-1:0] we1; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q0; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef VCS +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] q0; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] q1; +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +integer i; + +always @(posedge clk) +begin + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + +endmodule + + +////////////////////////////////////////////// +//4x4 systolic matrix multiplier +////////////////////////////////////////////// +module matmul_4x4_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, //Data values coming in from previous matmul - systolic connections + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out,//Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + final_mat_mul_size, + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; +assign clk_cnt_for_done = ((final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC) ; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end + + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b0_data(b0_data), +.b1_data_delayed_1(b1_data_delayed_1), +.b2_data_delayed_2(b2_data_delayed_2), +.b3_data_delayed_3(b3_data_delayed_3), +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), +.final_mat_mul_size(final_mat_mul_size), +.a_loc(a_loc), +.b_loc(b_loc) +); + + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +assign a0_data_in = a_data_in[`DWIDTH-1:0]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +assign b0_data_in = b_data_in[`DWIDTH-1:0]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +//If b_loc is 0, that means this matmul block is on the top-row of the +//final large matmul. In that case, b will take inputs from mem. +//If b_loc != 0, that means this matmul block is not on the top-row of the +//final large matmul. In that case, b will take inputs from the matmul on top +//of this one. +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; + +//If a_loc is 0, that means this matmul block is on the left-col of the +//final large matmul. In that case, a will take inputs from mem. +//If a_loc != 0, that means this matmul block is not on the left-col of the +//final large matmul. In that case, a will take inputs from the matmul on left +//of this one. +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; + +wire [`DWIDTH-1:0] matrixC00; +wire [`DWIDTH-1:0] matrixC01; +wire [`DWIDTH-1:0] matrixC02; +wire [`DWIDTH-1:0] matrixC03; +wire [`DWIDTH-1:0] matrixC10; +wire [`DWIDTH-1:0] matrixC11; +wire [`DWIDTH-1:0] matrixC12; +wire [`DWIDTH-1:0] matrixC13; +wire [`DWIDTH-1:0] matrixC20; +wire [`DWIDTH-1:0] matrixC21; +wire [`DWIDTH-1:0] matrixC22; +wire [`DWIDTH-1:0] matrixC23; +wire [`DWIDTH-1:0] matrixC30; +wire [`DWIDTH-1:0] matrixC31; +wire [`DWIDTH-1:0] matrixC32; +wire [`DWIDTH-1:0] matrixC33; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual processing elements +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.reset(reset), +.clk(clk), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33), +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +clk, +reset, +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33 +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC00; +input [`DWIDTH-1:0] matrixC01; +input [`DWIDTH-1:0] matrixC02; +input [`DWIDTH-1:0] matrixC03; +input [`DWIDTH-1:0] matrixC10; +input [`DWIDTH-1:0] matrixC11; +input [`DWIDTH-1:0] matrixC12; +input [`DWIDTH-1:0] matrixC13; +input [`DWIDTH-1:0] matrixC20; +input [`DWIDTH-1:0] matrixC21; +input [`DWIDTH-1:0] matrixC22; +input [`DWIDTH-1:0] matrixC23; +input [`DWIDTH-1:0] matrixC30; +input [`DWIDTH-1:0] matrixC31; +input [`DWIDTH-1:0] matrixC32; +input [`DWIDTH-1:0] matrixC33; + +wire row_latch_en; + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// + +assign row_latch_en = ((clk_cnt == ((final_mat_mul_size<<2) - final_mat_mul_size -1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_1; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_2; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_3; + +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col0; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col1; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col2; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col3; +assign col0 = {matrixC30, matrixC20, matrixC10, matrixC00}; +assign col1 = {matrixC31, matrixC21, matrixC11, matrixC01}; +assign col2 = {matrixC32, matrixC22, matrixC12, matrixC02}; +assign col3 = {matrixC33, matrixC23, matrixC13, matrixC03}; + +//If save_output_to_accum is asserted, that means we are not intending to shift +//out the outputs, because the outputs are still partial sums. +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = row_latch_en ; + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c; + c_data_out <= 0; + counter <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= col0; + c_data_out_1 <= col1; + c_data_out_2 <= col2; + c_data_out_3 <= col3; + counter <= counter + 1; + end + else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c; + c_data_out <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_addr <= c_addr - address_stride_c; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +a1_data_delayed_1, +a2_data_delayed_2, +a3_data_delayed_3, +b0_data, +b1_data_delayed_1, +b2_data_delayed_2, +b3_data_delayed_3, +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, +final_mat_mul_size, +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] b3_data_delayed_3; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [7:0] final_mat_mul_size; +input [7:0] a_loc; +input [7:0] b_loc; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= address_mat_a-address_stride_a; + a_mem_access <= 0; + end + + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= a_addr + address_stride_a; + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[`DWIDTH-1:0] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_1 <= a3_data; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= address_mat_b - address_stride_b; + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= b_addr + address_stride_b; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[`DWIDTH-1:0] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_1 <= b3_data; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +reset, +clk, +pe_reset, +a0, a1, a2, a3, +b0, b1, b2, b3, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33, +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +output [`DWIDTH-1:0] matrixC00; +output [`DWIDTH-1:0] matrixC01; +output [`DWIDTH-1:0] matrixC02; +output [`DWIDTH-1:0] matrixC03; +output [`DWIDTH-1:0] matrixC10; +output [`DWIDTH-1:0] matrixC11; +output [`DWIDTH-1:0] matrixC12; +output [`DWIDTH-1:0] matrixC13; +output [`DWIDTH-1:0] matrixC20; +output [`DWIDTH-1:0] matrixC21; +output [`DWIDTH-1:0] matrixC22; +output [`DWIDTH-1:0] matrixC23; +output [`DWIDTH-1:0] matrixC30; +output [`DWIDTH-1:0] matrixC31; +output [`DWIDTH-1:0] matrixC32; +output [`DWIDTH-1:0] matrixC33; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a00to01, a01to02, a02to03, a03to04; +wire [`DWIDTH-1:0] a10to11, a11to12, a12to13, a13to14; +wire [`DWIDTH-1:0] a20to21, a21to22, a22to23, a23to24; +wire [`DWIDTH-1:0] a30to31, a31to32, a32to33, a33to34; + +wire [`DWIDTH-1:0] b00to10, b10to20, b20to30, b30to40; +wire [`DWIDTH-1:0] b01to11, b11to21, b21to31, b31to41; +wire [`DWIDTH-1:0] b02to12, b12to22, b22to32, b32to42; +wire [`DWIDTH-1:0] b03to13, b13to23, b23to33, b33to43; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe00(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a00to01), .out_b(b00to10), .out_c(matrixC00)); +processing_element pe01(.reset(effective_rst), .clk(clk), .in_a(a00to01), .in_b(b1), .out_a(a01to02), .out_b(b01to11), .out_c(matrixC01)); +processing_element pe02(.reset(effective_rst), .clk(clk), .in_a(a01to02), .in_b(b2), .out_a(a02to03), .out_b(b02to12), .out_c(matrixC02)); +processing_element pe03(.reset(effective_rst), .clk(clk), .in_a(a02to03), .in_b(b3), .out_a(a03to04), .out_b(b03to13), .out_c(matrixC03)); + +processing_element pe10(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b00to10), .out_a(a10to11), .out_b(b10to20), .out_c(matrixC10)); +processing_element pe11(.reset(effective_rst), .clk(clk), .in_a(a10to11), .in_b(b01to11), .out_a(a11to12), .out_b(b11to21), .out_c(matrixC11)); +processing_element pe12(.reset(effective_rst), .clk(clk), .in_a(a11to12), .in_b(b02to12), .out_a(a12to13), .out_b(b12to22), .out_c(matrixC12)); +processing_element pe13(.reset(effective_rst), .clk(clk), .in_a(a12to13), .in_b(b03to13), .out_a(a13to14), .out_b(b13to23), .out_c(matrixC13)); + +processing_element pe20(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b10to20), .out_a(a20to21), .out_b(b20to30), .out_c(matrixC20)); +processing_element pe21(.reset(effective_rst), .clk(clk), .in_a(a20to21), .in_b(b11to21), .out_a(a21to22), .out_b(b21to31), .out_c(matrixC21)); +processing_element pe22(.reset(effective_rst), .clk(clk), .in_a(a21to22), .in_b(b12to22), .out_a(a22to23), .out_b(b22to32), .out_c(matrixC22)); +processing_element pe23(.reset(effective_rst), .clk(clk), .in_a(a22to23), .in_b(b13to23), .out_a(a23to24), .out_b(b23to33), .out_c(matrixC23)); + +processing_element pe30(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b20to30), .out_a(a30to31), .out_b(b30to40), .out_c(matrixC30)); +processing_element pe31(.reset(effective_rst), .clk(clk), .in_a(a30to31), .in_b(b21to31), .out_a(a31to32), .out_b(b31to41), .out_c(matrixC31)); +processing_element pe32(.reset(effective_rst), .clk(clk), .in_a(a31to32), .in_b(b22to32), .out_a(a32to33), .out_b(b32to42), .out_c(matrixC32)); +processing_element pe33(.reset(effective_rst), .clk(clk), .in_a(a32to33), .in_b(b23to33), .out_a(a33to34), .out_b(b33to43), .out_c(matrixC33)); + +assign a_data_out = {a33to34,a23to24,a13to14,a03to04}; +assign b_data_out = {b33to43,b32to42,b31to41,b30to40}; + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + //This is an instantiation of a module that is defined in the arch file. + //It's a mode of the DSP slice (floating point 16-bit multiply and accumulate). + mac_fp u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mcml.v b/openfpga_flow/benchmarks/vtr_benchmark/mcml.v new file mode 100755 index 000000000..1cbe22670 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mcml.v @@ -0,0 +1,25022 @@ + +// Skeleton +// Reads constants and instantiates all modules used by the hardware components + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +`define TRIG_WIDTH 5'b01010 //10; +`define PIPELINE_DEPTH_UPPER_LIMIT 10'b0100000000 //256; +`define ABSORB_ADDR_WIDTH 6'b010000 //16; +`define ABSORB_WORD_WIDTH 7'b01000000 //64; +`define WSCALE 22'b0111010100101111111111 //1919999; + +//From Roulette +//`define BIT_WIDTH 7'b0100000 +//`define LAYER_WIDTH 6'b000011 +`define LEFTSHIFT 6'b000011 // 2^3=8=1/0.125 where 0.125 = CHANCE of roulette +`define INTCHANCE 32'b00100000000000000000000000000000 //Based on 32 bit rand num generator +`define MIN_WEIGHT 9'b011001000 + +// From Boundary +`define BIT_WIDTH 7'b0100000 +`define LAYER_WIDTH 6'b000011 +`define INTMAX 32'b01111111111111111111111111111111 +`define INTMIN 32'b10000000000000000000000000000000 +`define DIVIDER_LATENCY 6'b011110 +`define FINAL_LATENCY 6'b011100 +`define MULT_LATENCY 1'b1 +`define ASPECT_RATIO 6'b000111 +`define TOTAL_LATENCY 7'b0111100 + +//From Move +//`define BIT_WIDTH 6'b100000 +//`define LAYER_WIDTH 6'b000011 +`define LOGSCALEFACTOR 6'b000101 +`define MAXLOG 32'b10110001011100100001011111110111 //Based on 32 bit unsigned rand num generator +`define CONST_MOVE_AMOUNT 15'b110000110101000 //Used for testing purposes only +`define MUTMAX_BITS 6'b001111 + +//From Hop +//`define BIT_WIDTH 6'b100000 +//`define LAYER_WIDTH 6'b000011 +//`define INTMAX 32'b01111111111111111111111111111111 +//`define INTMIN 32'b10000000000000000000000000000000 + +//From LogCalc +//`define BIT_WIDTH 7'b0100000 +`define MANTISSA_PRECISION 6'b001010 +`define LOG2_BIT_WIDTH 6'b000110 +`define LOG2 28'b0101100010111001000010111111 + +//From DropSpinWrapper +`define NR 10'b0100000000 +`define NZ 10'b0100000000 + +`define NR_EXP 5'b01000 //meaning `NR=2^`NR_exp or 2^8=256 +`define RGRID_SCLAE_EXP 6'b010101 //2^21 = RGRID_SCALE +`define ZGRID_SCLAE_EXP 6'b010101 //2^21 = ZGRID_SCALE + + +//`define BIT_WIDTH 7'b0100000 +`define BIT_WIDTH_2 8'b01000000 +`define WORD_WIDTH 8'b01000000 +`define ADDR_WIDTH 6'b010000 //256x256=2^8*2^8=2^16 + + +//From scatterer: +`define DIV 6'b010100//20; +`define SQRT 5'b01010 //10; +`define LAT 7'b0100101 //DIV + SQRT + 7; +`define INTMAX_2 {32'h3FFFFFFF,32'h00000001} +//`define INTMAX 32'b01111111111111111111111111111111//2147483647; +//`define INTMIN 32'b10000000000000000000000000000001//-2147483647; +`define INTMAXMinus3 32'b01111111111111111111111111111100//2147483644; +`define negINTMAXPlus3 32'b10000000000000000000000000000100//-2147483644; + +//From Reflector: +`define INTMAX_2_ref {32'h3FFFFFFF,32'hFFFFFFFF} + + +module mcml ( + reset, + clk, + + constants, + read_constants, + + result, + inc_result, + + calc_in_progress + ); + +// Total number of constants +//parameter LAST_CONSTANT = 104; +//parameter NUM_FRESNELS = 128; +//parameter NUM_TRIG_ELS = 1024; +//parameter ABSORB_ADDR_WIDTH=16; +//parameter ABSORB_WORD_WIDTH=64; +//parameter BIT_WIDTH = 32; + +input reset; +input clk; +input [31:0] constants; +input read_constants; +input inc_result; + +output calc_in_progress; +output [31:0] result; +reg calc_in_progress; +reg [31:0] result; + + +//integer i; + +wire [31:0] mem_fres_up, mem_fres_down, mem_sint, mem_cost; + +// photon calculator + +wire reset; + +// Scatterer Reflector memory look-up +wire [12:0] tindex; +wire [9:0] fresIndex; + +// DeadOrAlive Module (nothing) + +// Final results +wire [16-1:0] absorb_rdaddress, absorb_wraddress; +wire absorb_wren; +wire [64-1:0] absorb_data; +wire [64-1:0] absorb_q; + +// Flag when final results ready +wire done; +reg enable; +reg reset_calculator; + +// Combinational drivers +//reg [31:0] c_const[104 - 1:0]; +reg [31:0] c_const__103; +reg [31:0] c_const__102; +reg [31:0] c_const__101; +reg [31:0] c_const__100; +reg [31:0] c_const__99; +reg [31:0] c_const__98; +reg [31:0] c_const__97; +reg [31:0] c_const__96; +reg [31:0] c_const__95; +reg [31:0] c_const__94; +reg [31:0] c_const__93; +reg [31:0] c_const__92; +reg [31:0] c_const__91; +reg [31:0] c_const__90; +reg [31:0] c_const__89; +reg [31:0] c_const__88; +reg [31:0] c_const__87; +reg [31:0] c_const__86; +reg [31:0] c_const__85; +reg [31:0] c_const__84; +reg [31:0] c_const__83; +reg [31:0] c_const__82; +reg [31:0] c_const__81; +reg [31:0] c_const__80; +reg [31:0] c_const__79; +reg [31:0] c_const__78; +reg [31:0] c_const__77; +reg [31:0] c_const__76; +reg [31:0] c_const__75; +reg [31:0] c_const__74; +reg [31:0] c_const__73; +reg [31:0] c_const__72; +reg [31:0] c_const__71; +reg [31:0] c_const__70; +reg [31:0] c_const__69; +reg [31:0] c_const__68; +reg [31:0] c_const__67; +reg [31:0] c_const__66; +reg [31:0] c_const__65; +reg [31:0] c_const__64; +reg [31:0] c_const__63; +reg [31:0] c_const__62; +reg [31:0] c_const__61; +reg [31:0] c_const__60; +reg [31:0] c_const__59; +reg [31:0] c_const__58; +reg [31:0] c_const__57; +reg [31:0] c_const__56; +reg [31:0] c_const__55; +reg [31:0] c_const__54; +reg [31:0] c_const__53; +reg [31:0] c_const__52; +reg [31:0] c_const__51; +reg [31:0] c_const__50; +reg [31:0] c_const__49; +reg [31:0] c_const__48; +reg [31:0] c_const__47; +reg [31:0] c_const__46; +reg [31:0] c_const__45; +reg [31:0] c_const__44; +reg [31:0] c_const__43; +reg [31:0] c_const__42; +reg [31:0] c_const__41; +reg [31:0] c_const__40; +reg [31:0] c_const__39; +reg [31:0] c_const__38; +reg [31:0] c_const__37; +reg [31:0] c_const__36; +reg [31:0] c_const__35; +reg [31:0] c_const__34; +reg [31:0] c_const__33; +reg [31:0] c_const__32; +reg [31:0] c_const__31; +reg [31:0] c_const__30; +reg [31:0] c_const__29; +reg [31:0] c_const__28; +reg [31:0] c_const__27; +reg [31:0] c_const__26; +reg [31:0] c_const__25; +reg [31:0] c_const__24; +reg [31:0] c_const__23; +reg [31:0] c_const__22; +reg [31:0] c_const__21; +reg [31:0] c_const__20; +reg [31:0] c_const__19; +reg [31:0] c_const__18; +reg [31:0] c_const__17; +reg [31:0] c_const__16; +reg [31:0] c_const__15; +reg [31:0] c_const__14; +reg [31:0] c_const__13; +reg [31:0] c_const__12; +reg [31:0] c_const__11; +reg [31:0] c_const__10; +reg [31:0] c_const__9; +reg [31:0] c_const__8; +reg [31:0] c_const__7; +reg [31:0] c_const__6; +reg [31:0] c_const__5; +reg [31:0] c_const__4; +reg [31:0] c_const__3; +reg [31:0] c_const__2; +reg [31:0] c_const__1; +reg [31:0] c_const__0; + + +reg [12:0] c_counter; +reg c_toggle; + +reg [16-1:0] c_absorb_read_counter, c_absorb_write_counter; +reg [16-1:0] absorb_rdaddress_mux, absorb_wraddress_mux; +reg [64-1:0] absorb_data_mux; +reg absorb_wren_mux; + +reg [3:0] c_state; + +reg [31:0] c_result; +reg c_calc_in_progress; + +reg wren_fres_up, wren_fres_down, wren_sinp, wren_cosp, wren_sint, wren_cost; +reg [2:0] mem_layer; + +// Registered drivers +//reg [31:0] r_const[104 - 1:0]; +reg [31:0] r_const__103; +reg [31:0] r_const__102; +reg [31:0] r_const__101; +reg [31:0] r_const__100; +reg [31:0] r_const__99; +reg [31:0] r_const__98; +reg [31:0] r_const__97; +reg [31:0] r_const__96; +reg [31:0] r_const__95; +reg [31:0] r_const__94; +reg [31:0] r_const__93; +reg [31:0] r_const__92; +reg [31:0] r_const__91; +reg [31:0] r_const__90; +reg [31:0] r_const__89; +reg [31:0] r_const__88; +reg [31:0] r_const__87; +reg [31:0] r_const__86; +reg [31:0] r_const__85; +reg [31:0] r_const__84; +reg [31:0] r_const__83; +reg [31:0] r_const__82; +reg [31:0] r_const__81; +reg [31:0] r_const__80; +reg [31:0] r_const__79; +reg [31:0] r_const__78; +reg [31:0] r_const__77; +reg [31:0] r_const__76; +reg [31:0] r_const__75; +reg [31:0] r_const__74; +reg [31:0] r_const__73; +reg [31:0] r_const__72; +reg [31:0] r_const__71; +reg [31:0] r_const__70; +reg [31:0] r_const__69; +reg [31:0] r_const__68; +reg [31:0] r_const__67; +reg [31:0] r_const__66; +reg [31:0] r_const__65; +reg [31:0] r_const__64; +reg [31:0] r_const__63; +reg [31:0] r_const__62; +reg [31:0] r_const__61; +reg [31:0] r_const__60; +reg [31:0] r_const__59; +reg [31:0] r_const__58; +reg [31:0] r_const__57; +reg [31:0] r_const__56; +reg [31:0] r_const__55; +reg [31:0] r_const__54; +reg [31:0] r_const__53; +reg [31:0] r_const__52; +reg [31:0] r_const__51; +reg [31:0] r_const__50; +reg [31:0] r_const__49; +reg [31:0] r_const__48; +reg [31:0] r_const__47; +reg [31:0] r_const__46; +reg [31:0] r_const__45; +reg [31:0] r_const__44; +reg [31:0] r_const__43; +reg [31:0] r_const__42; +reg [31:0] r_const__41; +reg [31:0] r_const__40; +reg [31:0] r_const__39; +reg [31:0] r_const__38; +reg [31:0] r_const__37; +reg [31:0] r_const__36; +reg [31:0] r_const__35; +reg [31:0] r_const__34; +reg [31:0] r_const__33; +reg [31:0] r_const__32; +reg [31:0] r_const__31; +reg [31:0] r_const__30; +reg [31:0] r_const__29; +reg [31:0] r_const__28; +reg [31:0] r_const__27; +reg [31:0] r_const__26; +reg [31:0] r_const__25; +reg [31:0] r_const__24; +reg [31:0] r_const__23; +reg [31:0] r_const__22; +reg [31:0] r_const__21; +reg [31:0] r_const__20; +reg [31:0] r_const__19; +reg [31:0] r_const__18; +reg [31:0] r_const__17; +reg [31:0] r_const__16; +reg [31:0] r_const__15; +reg [31:0] r_const__14; +reg [31:0] r_const__13; +reg [31:0] r_const__12; +reg [31:0] r_const__11; +reg [31:0] r_const__10; +reg [31:0] r_const__9; +reg [31:0] r_const__8; +reg [31:0] r_const__7; +reg [31:0] r_const__6; +reg [31:0] r_const__5; +reg [31:0] r_const__4; +reg [31:0] r_const__3; +reg [31:0] r_const__2; +reg [31:0] r_const__1; +reg [31:0] r_const__0; + + + +reg [12:0] r_counter; +reg [16-1:0] r_absorb_read_counter; +reg [16-1:0] r_absorb_write_counter; +reg [3:0] r_state; +reg r_toggle; + +// Skeleton program states +parameter [3:0] ERROR_ST = 4'b0000, + READ1_ST = 4'b0001, + READ2_ST = 4'b0010, + READ3_ST = 4'b0011, + READ4_ST = 4'b0100, + READ5_ST = 4'b0101, + RESET_MEM_ST = 4'b0110, + CALC_ST = 4'b1000, + DONE1_ST = 4'b1001, + DONE2_ST = 4'b1010, + DONE3_ST = 4'b1011, + DONE4_ST = 4'b1100, + DONE5_ST = 4'b1101, + DONE6_ST = 4'b1110; + +// Instantiate lookup memories +dual_port_mem_zz u_fres_up(clk, constants, {3'b0, fresIndex}, {3'b0, mem_layer, r_counter[6:0]}, wren_fres_up, mem_fres_up); +dual_port_mem_yy u_fres_down(clk, constants, {3'b0, fresIndex}, {3'b0, mem_layer, r_counter[6:0]}, wren_fres_down, mem_fres_down); +dual_port_mem_xx u_sint(clk, constants, tindex, {mem_layer, r_counter[9:0]}, wren_sint, mem_sint); +dual_port_mem_ww u_cost(clk, constants, tindex, {mem_layer, r_counter[9:0]}, wren_cost, mem_cost); + +// Reduce size of absorption matrix +dual absorptionMatrix( .clk (clk), .data(absorb_data_mux[35:0]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[35:0])); +dual2 absorptionMatrix2( .clk (clk), .data(absorb_data_mux[53:36]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[53:36])); +dual3 absorptionMatrix3( .clk (clk), .data(absorb_data_mux[61:54]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[61:54])); + + + // + //peter m test since absorb_q not defined for 63:62 + assign absorb_q[63:62] = 2'b00; + + +PhotonCalculator u_calc ( + .clock(clk), .reset(reset_calculator), .enable(enable), + + // CONSTANTS + .total_photons(r_const__0), + + .randseed1(r_const__19), .randseed2(r_const__20), .randseed3(r_const__21), .randseed4(r_const__22), .randseed5(r_const__23), + + //Because it is in the module: + .initialWeight(32'b00000000000111010100101111111111), + + // Mover + .OneOver_MutMaxrad_0(r_const__32), .OneOver_MutMaxrad_1(r_const__33), .OneOver_MutMaxrad_2(r_const__34), .OneOver_MutMaxrad_3(r_const__35), .OneOver_MutMaxrad_4(r_const__36), .OneOver_MutMaxrad_5(r_const__37), + .OneOver_MutMaxdep_0(r_const__38), .OneOver_MutMaxdep_1(r_const__39), .OneOver_MutMaxdep_2(r_const__40), .OneOver_MutMaxdep_3(r_const__41), .OneOver_MutMaxdep_4(r_const__42), .OneOver_MutMaxdep_5(r_const__43), + .OneOver_Mut_0(r_const__26), .OneOver_Mut_1(r_const__27), .OneOver_Mut_2(r_const__28), .OneOver_Mut_3(r_const__29), .OneOver_Mut_4(r_const__30), .OneOver_Mut_5(r_const__31), + + // BoundaryChecker + .z1_0(r_const__50), .z1_1(r_const__51), .z1_2(r_const__52), .z1_3(r_const__53), .z1_4(r_const__54), .z1_5(r_const__55), + .z0_0(r_const__44), .z0_1(r_const__45), .z0_2(r_const__46), .z0_3(r_const__47), .z0_4(r_const__48), .z0_5(r_const__49), + .mut_0(32'b00000000000000000000000000000000), .mut_1(r_const__2), .mut_2(r_const__3), .mut_3(r_const__4), .mut_4(r_const__5), .mut_5(r_const__6), + .maxDepth_over_maxRadius(r_const__1), + + // Hop (no constants) + + // Scatterer Reflector Wrapper + .down_niOverNt_1(r_const__69), .down_niOverNt_2(r_const__70), .down_niOverNt_3(r_const__71), .down_niOverNt_4(r_const__72), .down_niOverNt_5(r_const__73), + .up_niOverNt_1(r_const__75), .up_niOverNt_2(r_const__76), .up_niOverNt_3(r_const__77), .up_niOverNt_4(r_const__78), .up_niOverNt_5(r_const__79), + .down_niOverNt_2_1({r_const__81,r_const__87}), .down_niOverNt_2_2({r_const__82,r_const__88}), .down_niOverNt_2_3({r_const__83,r_const__89}), .down_niOverNt_2_4({r_const__84,r_const__90}), .down_niOverNt_2_5({r_const__85,r_const__91}), + .up_niOverNt_2_1({r_const__93,r_const__99}), .up_niOverNt_2_2({r_const__94,r_const__100}), .up_niOverNt_2_3({r_const__95,r_const__101}), .up_niOverNt_2_4({r_const__96,r_const__102}), .up_niOverNt_2_5({r_const__97,r_const__103}), + .downCritAngle_0(r_const__7), .downCritAngle_1(r_const__8), .downCritAngle_2(r_const__9), .downCritAngle_3(r_const__10), .downCritAngle_4(r_const__11), + .upCritAngle_0(r_const__13), .upCritAngle_1(r_const__14), .upCritAngle_2(r_const__15), .upCritAngle_3(r_const__16), .upCritAngle_4(r_const__17), + .muaFraction1(r_const__57), .muaFraction2(r_const__58), .muaFraction3(r_const__59), .muaFraction4(r_const__60), .muaFraction5(r_const__61), + // Interface to memory look-up + // From Memories + .up_rFresnel(mem_fres_up), .down_rFresnel(mem_fres_down), .sint(mem_sint), .cost(mem_cost), + // To Memories + .tindex(tindex), .fresIndex(fresIndex), + + // DeadOrAlive (no Constants) + + // Absorber + .absorb_data(absorb_data), .absorb_rdaddress(absorb_rdaddress), .absorb_wraddress(absorb_wraddress), + .absorb_wren(absorb_wren), .absorb_q(absorb_q), + + // Done signal + .done(done) + ); + +// Mux to read the absorbtion array +always @(r_state or done or r_absorb_read_counter or r_absorb_write_counter or absorb_wraddress or absorb_data or absorb_rdaddress or absorb_data or absorb_wren ) +begin + if(r_state == RESET_MEM_ST) + begin + absorb_wren_mux = 1'b1; + absorb_data_mux = 64'b0; + absorb_rdaddress_mux = r_absorb_read_counter; + absorb_wraddress_mux = r_absorb_write_counter; + end + else if(done == 1'b1) + begin + absorb_rdaddress_mux = r_absorb_read_counter; + absorb_wraddress_mux = absorb_wraddress; + absorb_data_mux = absorb_data; + absorb_wren_mux = 1'b0; + end + else + begin + absorb_rdaddress_mux = absorb_rdaddress; + absorb_wraddress_mux = absorb_wraddress; + absorb_data_mux = absorb_data; + absorb_wren_mux = absorb_wren; + end +end + +// Skeleton SW/HW interface +// 1. Read constants +// 2. Wait for completion +// 3. Write data back +always @(r_state or r_absorb_read_counter or r_absorb_write_counter or result or r_toggle or r_counter or read_constants or constants or done + or inc_result or mem_cost or mem_sint or absorb_q + or r_const__103 + or r_const__102 + or r_const__101 + or r_const__100 + or r_const__99 + or r_const__98 + or r_const__97 + or r_const__96 + or r_const__95 + or r_const__94 + or r_const__93 + or r_const__92 + or r_const__91 + or r_const__90 + or r_const__89 + or r_const__88 + or r_const__87 + or r_const__86 + or r_const__85 + or r_const__84 + or r_const__83 + or r_const__82 + or r_const__81 + or r_const__80 + or r_const__79 + or r_const__78 + or r_const__77 + or r_const__76 + or r_const__75 + or r_const__74 + or r_const__73 + or r_const__72 + or r_const__71 + or r_const__70 + or r_const__69 + or r_const__68 + or r_const__67 + or r_const__66 + or r_const__65 + or r_const__64 + or r_const__63 + or r_const__62 + or r_const__61 + or r_const__60 + or r_const__59 + or r_const__58 + or r_const__57 + or r_const__56 + or r_const__55 + or r_const__54 + or r_const__53 + or r_const__52 + or r_const__51 + or r_const__50 + or r_const__49 + or r_const__48 + or r_const__47 + or r_const__46 + or r_const__45 + or r_const__44 + or r_const__43 + or r_const__42 + or r_const__41 + or r_const__40 + or r_const__39 + or r_const__38 + or r_const__37 + or r_const__36 + or r_const__35 + or r_const__34 + or r_const__33 + or r_const__32 + or r_const__31 + or r_const__30 + or r_const__29 + or r_const__28 + or r_const__27 + or r_const__26 + or r_const__25 + or r_const__24 + or r_const__23 + or r_const__22 + or r_const__21 + or r_const__20 + or r_const__19 + or r_const__18 + or r_const__17 + or r_const__16 + or r_const__15 + or r_const__14 + or r_const__13 + or r_const__12 + or r_const__11 + or r_const__10 + or r_const__9 + or r_const__8 + or r_const__7 + or r_const__6 + or r_const__5 + or r_const__4 + or r_const__3 + or r_const__2 + or r_const__1 + or r_const__0) begin + // Initialize data + //for(i = 0; i < 104; i = i + 1) begin + // c_const[i] = r_const[i]; + //end + begin +//c_const__103 = r_const__103; +c_const__102 = r_const__102; +c_const__101 = r_const__101; +c_const__100 = r_const__100; +c_const__99 = r_const__99; +c_const__98 = r_const__98; +c_const__97 = r_const__97; +c_const__96 = r_const__96; +c_const__95 = r_const__95; +c_const__94 = r_const__94; +c_const__93 = r_const__93; +c_const__92 = r_const__92; +c_const__91 = r_const__91; +c_const__90 = r_const__90; +c_const__89 = r_const__89; +c_const__88 = r_const__88; +c_const__87 = r_const__87; +c_const__86 = r_const__86; +c_const__85 = r_const__85; +c_const__84 = r_const__84; +c_const__83 = r_const__83; +c_const__82 = r_const__82; +c_const__81 = r_const__81; +c_const__80 = r_const__80; +c_const__79 = r_const__79; +c_const__78 = r_const__78; +c_const__77 = r_const__77; +c_const__76 = r_const__76; +c_const__75 = r_const__75; +c_const__74 = r_const__74; +c_const__73 = r_const__73; +c_const__72 = r_const__72; +c_const__71 = r_const__71; +c_const__70 = r_const__70; +c_const__69 = r_const__69; +c_const__68 = r_const__68; +c_const__67 = r_const__67; +c_const__66 = r_const__66; +c_const__65 = r_const__65; +c_const__64 = r_const__64; +c_const__63 = r_const__63; +c_const__62 = r_const__62; +c_const__61 = r_const__61; +c_const__60 = r_const__60; +c_const__59 = r_const__59; +c_const__58 = r_const__58; +c_const__57 = r_const__57; +c_const__56 = r_const__56; +c_const__55 = r_const__55; +c_const__54 = r_const__54; +c_const__53 = r_const__53; +c_const__52 = r_const__52; +c_const__51 = r_const__51; +c_const__50 = r_const__50; +c_const__49 = r_const__49; +c_const__48 = r_const__48; +c_const__47 = r_const__47; +c_const__46 = r_const__46; +c_const__45 = r_const__45; +c_const__44 = r_const__44; +c_const__43 = r_const__43; +c_const__42 = r_const__42; +c_const__41 = r_const__41; +c_const__40 = r_const__40; +c_const__39 = r_const__39; +c_const__38 = r_const__38; +c_const__37 = r_const__37; +c_const__36 = r_const__36; +c_const__35 = r_const__35; +c_const__34 = r_const__34; +c_const__33 = r_const__33; +c_const__32 = r_const__32; +c_const__31 = r_const__31; +c_const__30 = r_const__30; +c_const__29 = r_const__29; +c_const__28 = r_const__28; +c_const__27 = r_const__27; +c_const__26 = r_const__26; +c_const__25 = r_const__25; +c_const__24 = r_const__24; +c_const__23 = r_const__23; +c_const__22 = r_const__22; +c_const__21 = r_const__21; +c_const__20 = r_const__20; +c_const__19 = r_const__19; +c_const__18 = r_const__18; +c_const__17 = r_const__17; +c_const__16 = r_const__16; +c_const__15 = r_const__15; +c_const__14 = r_const__14; +c_const__13 = r_const__13; +c_const__12 = r_const__12; +c_const__11 = r_const__11; +c_const__10 = r_const__10; +c_const__9 = r_const__9; +c_const__8 = r_const__8; +c_const__7 = r_const__7; +c_const__6 = r_const__6; +c_const__5 = r_const__5; +c_const__4 = r_const__4; +c_const__3 = r_const__3; +c_const__2 = r_const__2; +c_const__1 = r_const__1; +c_const__0 = r_const__0; + end + /* + //honourary c_const__103 = r_const__103 + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; +*/ + // Determine next state and which data changes + case(r_state) + //ERROR_ST: + READ1_ST: + begin + if(read_constants) + begin + // peter m redoing this to a shift register r_const 104 will shift to r_const 103 etc etc + // if its in the read_constants state + // c_const[r_counter] = constants; + c_counter = r_counter + 13'b00000000000001; + c_const__103 = constants; + //pm preventing latches + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + end + else + begin + c_const__103 = r_const__103; + if(r_counter >= 104) + begin + c_counter = 13'b0000000000000; + c_state = READ2_ST; + //preventing latches + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + + end + else + begin + c_counter = r_counter; + c_state = r_state; + + //preventing latches + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + end + end + end + READ2_ST: + begin + mem_layer = r_counter[9:7]; + if(read_constants) + begin + wren_fres_up = 1'b1; + c_counter = r_counter + 13'b00000000000001; + //prevent latches + + c_const__103 = r_const__103; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + + end + else + begin + if(r_counter >= 5*128) + begin + c_counter = 13'b0000000000000; + c_state = READ3_ST; + + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + end + else + begin + c_counter = r_counter; + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + + end + end + end + READ3_ST: + begin + mem_layer = r_counter[9:7]; + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + + wren_fres_up = 1'b0; + + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + // mem_layer = r_counter[12:10]; + if(read_constants) + begin + wren_fres_down = 1'b1; + c_counter = r_counter + 13'b00000000000001; + c_state = r_state; + end + else + begin + if(r_counter >= 5*128) + begin + c_counter = 13'b0000000000000; + c_state = READ4_ST; + wren_fres_down = 1'b0; + end + else + begin + c_counter = r_counter; + c_state = r_state; + wren_fres_down = 1'b0; + end + end + end + READ4_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + //wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + if(read_constants) + begin + wren_cost = 1'b1; + c_counter = r_counter + 13'b00000000000001; + c_state = r_state; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000000000000000; + c_state = READ5_ST; + wren_cost = 1'b0; + end + else + begin + c_counter = r_counter; + c_state = r_state; + wren_cost = 1'b0; + end + end + end + READ5_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + //c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + //wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + if(read_constants) + begin + wren_sint = 1'b1; + c_counter = r_counter + 13'b00000000000000000000000001; + c_state = r_state; + c_absorb_read_counter = r_absorb_read_counter; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000000000000000; + c_absorb_read_counter = 16'b0000000000000000000000000; //use to be 13 bit. Error in odin + c_state = RESET_MEM_ST; + wren_sint = 1'b0; + end + else + begin + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_state = r_state; + wren_sint = 1'b0; + end + end + end + RESET_MEM_ST: + begin + c_const__103 = r_const__103; + // c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + //c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + //c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + + c_counter = r_counter; + + c_toggle = 1'b0; + c_calc_in_progress = 1'b1; + c_absorb_write_counter = r_absorb_write_counter + 16'b0000000000000001; + if(r_absorb_write_counter == 16'b1111111111111111) + begin + c_state = CALC_ST; + end + else + begin + c_state = r_state; + + end + end + CALC_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + //c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + if(done == 1'b0) + begin + c_calc_in_progress = 1'b1; + c_toggle = 1'b0; + c_counter = r_counter; + c_state = r_state; + + end + else + begin + c_toggle = 1'b0; + c_calc_in_progress = 1'b0; + c_state = DONE6_ST; + c_counter = 13'b0000000000000; + end + end + // DEBUG STATES BEGIN + + DONE1_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_result = r_const__103; + //original -c_result = {32'b0,r_const[r_counter]}; + if(inc_result) + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0000000000000; + c_state = DONE2_ST; + end + else + begin + c_counter = r_counter + 13'b0000000000001; + c_state = DONE1_ST; + end + end + + else + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0; + c_state = DONE2_ST; + end + else + begin + c_state = DONE1_ST; + c_counter = r_counter; + end + end + end + DONE2_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + //mem_layer = r_counter[12:10]; + + + mem_layer = r_counter[9:7]; + //c_result = {32'b00000000000000000000000000000000,mem_fres_up}; + c_result = 32'b0; + if(inc_result) + begin + c_counter = r_counter + 13'b0000000000001; + c_state = DONE1_ST; + end + else + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0000000000000; + c_state = DONE2_ST; + end + else + begin + c_counter = r_counter; + c_state = r_state; + end + end + end + DONE3_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + //mem_layer = r_counter[12:10]; + + + + + mem_layer = r_counter[9:7]; + //c_result = {32'b00000000000000000000000000000000,mem_fres_down}; + c_result = 32'b0; + + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b0000000000001; + c_state = DONE3_ST; + end + + else + begin + if(r_counter >= 13'b0001010000000) //5*128 = 640 + begin + c_counter = 13'b0000000000000; + c_state = DONE4_ST; + end + else + begin + c_counter = r_counter; + c_state = DONE3_ST; + end + + + + + end + end + DONE4_ST: + begin + + + + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + c_result = mem_cost; + + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b0000000000001; + c_state = DONE4_ST; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000; + c_state = DONE5_ST; + end + + else + begin + c_state = DONE4_ST; + c_counter = r_counter; + end + end + end + DONE5_ST: + begin + + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_result = mem_sint; + + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000; + c_state = DONE6_ST; + end + else + begin + c_state = DONE5_ST; + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b00000000000001; + end + else + begin + c_counter = r_counter; + end + end + end + + // DEBUG STATES END*/ + DONE6_ST: + begin + c_const__103 = r_const__103; + c_counter = r_counter; + //c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_state = DONE6_ST; + + + if(r_toggle == 1'b0) + begin + c_result = absorb_q[63:32]; + // c_state = r_state; + end + else + begin + c_result = absorb_q[31:0]; + // c_state = r_state; + end + + if(inc_result) + begin + if(r_toggle == 1'b0) + begin + c_toggle = 1'b1; + c_absorb_read_counter = r_absorb_read_counter ; + end + else + begin + c_toggle = 1'b0; + c_absorb_read_counter = r_absorb_read_counter + 16'b01; + end + end + else + begin + c_absorb_read_counter = r_absorb_read_counter; + c_toggle= r_toggle; + + end + // c_state = DONE6_ST; + end + + default: + begin + c_state = ERROR_ST; + c_const__103 = r_const__103; + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + // c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + end + endcase + end // FSM always + + + +// Latch Data +always @(posedge clk) + begin + if(reset) + begin + r_counter <= 13'b0000000000000000000000000; +r_const__103 <= 32'b00000000000000000000000000000000; +r_const__102 <= 32'b00000000000000000000000000000000; +r_const__101 <= 32'b00000000000000000000000000000000; +r_const__100 <= 32'b00000000000000000000000000000000; +r_const__99 <= 32'b00000000000000000000000000000000; +r_const__98 <= 32'b00000000000000000000000000000000; +r_const__97 <= 32'b00000000000000000000000000000000; +r_const__96 <= 32'b00000000000000000000000000000000; +r_const__95 <= 32'b00000000000000000000000000000000; +r_const__94 <= 32'b00000000000000000000000000000000; +r_const__93 <= 32'b00000000000000000000000000000000; +r_const__92 <= 32'b00000000000000000000000000000000; +r_const__91 <= 32'b00000000000000000000000000000000; +r_const__90 <= 32'b00000000000000000000000000000000; +r_const__89 <= 32'b00000000000000000000000000000000; +r_const__88 <= 32'b00000000000000000000000000000000; +r_const__87 <= 32'b00000000000000000000000000000000; +r_const__86 <= 32'b00000000000000000000000000000000; +r_const__85 <= 32'b00000000000000000000000000000000; +r_const__84 <= 32'b00000000000000000000000000000000; +r_const__83 <= 32'b00000000000000000000000000000000; +r_const__82 <= 32'b00000000000000000000000000000000; +r_const__81 <= 32'b00000000000000000000000000000000; +r_const__80 <= 32'b00000000000000000000000000000000; +r_const__79 <= 32'b00000000000000000000000000000000; +r_const__78 <= 32'b00000000000000000000000000000000; +r_const__77 <= 32'b00000000000000000000000000000000; +r_const__76 <= 32'b00000000000000000000000000000000; +r_const__75 <= 32'b00000000000000000000000000000000; +r_const__74 <= 32'b00000000000000000000000000000000; +r_const__73 <= 32'b00000000000000000000000000000000; +r_const__72 <= 32'b00000000000000000000000000000000; +r_const__71 <= 32'b00000000000000000000000000000000; +r_const__70 <= 32'b00000000000000000000000000000000; +r_const__69 <= 32'b00000000000000000000000000000000; +r_const__68 <= 32'b00000000000000000000000000000000; +r_const__67 <= 32'b00000000000000000000000000000000; +r_const__66 <= 32'b00000000000000000000000000000000; +r_const__65 <= 32'b00000000000000000000000000000000; +r_const__64 <= 32'b00000000000000000000000000000000; +r_const__63 <= 32'b00000000000000000000000000000000; +r_const__62 <= 32'b00000000000000000000000000000000; +r_const__61 <= 32'b00000000000000000000000000000000; +r_const__60 <= 32'b00000000000000000000000000000000; +r_const__59 <= 32'b00000000000000000000000000000000; +r_const__58 <= 32'b00000000000000000000000000000000; +r_const__57 <= 32'b00000000000000000000000000000000; +r_const__56 <= 32'b00000000000000000000000000000000; +r_const__55 <= 32'b00000000000000000000000000000000; +r_const__54 <= 32'b00000000000000000000000000000000; +r_const__53 <= 32'b00000000000000000000000000000000; +r_const__52 <= 32'b00000000000000000000000000000000; +r_const__51 <= 32'b00000000000000000000000000000000; +r_const__50 <= 32'b00000000000000000000000000000000; +r_const__49 <= 32'b00000000000000000000000000000000; +r_const__48 <= 32'b00000000000000000000000000000000; +r_const__47 <= 32'b00000000000000000000000000000000; +r_const__46 <= 32'b00000000000000000000000000000000; +r_const__45 <= 32'b00000000000000000000000000000000; +r_const__44 <= 32'b00000000000000000000000000000000; +r_const__43 <= 32'b00000000000000000000000000000000; +r_const__42 <= 32'b00000000000000000000000000000000; +r_const__41 <= 32'b00000000000000000000000000000000; +r_const__40 <= 32'b00000000000000000000000000000000; +r_const__39 <= 32'b00000000000000000000000000000000; +r_const__38 <= 32'b00000000000000000000000000000000; +r_const__37 <= 32'b00000000000000000000000000000000; +r_const__36 <= 32'b00000000000000000000000000000000; +r_const__35 <= 32'b00000000000000000000000000000000; +r_const__34 <= 32'b00000000000000000000000000000000; +r_const__33 <= 32'b00000000000000000000000000000000; +r_const__32 <= 32'b00000000000000000000000000000000; +r_const__31 <= 32'b00000000000000000000000000000000; +r_const__30 <= 32'b00000000000000000000000000000000; +r_const__29 <= 32'b00000000000000000000000000000000; +r_const__28 <= 32'b00000000000000000000000000000000; +r_const__27 <= 32'b00000000000000000000000000000000; +r_const__26 <= 32'b00000000000000000000000000000000; +r_const__25 <= 32'b00000000000000000000000000000000; +r_const__24 <= 32'b00000000000000000000000000000000; +r_const__23 <= 32'b00000000000000000000000000000000; +r_const__22 <= 32'b00000000000000000000000000000000; +r_const__21 <= 32'b00000000000000000000000000000000; +r_const__20 <= 32'b00000000000000000000000000000000; +r_const__19 <= 32'b00000000000000000000000000000000; +r_const__18 <= 32'b00000000000000000000000000000000; +r_const__17 <= 32'b00000000000000000000000000000000; +r_const__16 <= 32'b00000000000000000000000000000000; +r_const__15 <= 32'b00000000000000000000000000000000; +r_const__14 <= 32'b00000000000000000000000000000000; +r_const__13 <= 32'b00000000000000000000000000000000; +r_const__12 <= 32'b00000000000000000000000000000000; +r_const__11 <= 32'b00000000000000000000000000000000; +r_const__10 <= 32'b00000000000000000000000000000000; +r_const__9 <= 32'b00000000000000000000000000000000; +r_const__8 <= 32'b00000000000000000000000000000000; +r_const__7 <= 32'b00000000000000000000000000000000; +r_const__6 <= 32'b00000000000000000000000000000000; +r_const__5 <= 32'b00000000000000000000000000000000; +r_const__4 <= 32'b00000000000000000000000000000000; +r_const__3 <= 32'b00000000000000000000000000000000; +r_const__2 <= 32'b00000000000000000000000000000000; +r_const__1 <= 32'b00000000000000000000000000000000; +r_const__0 <= 32'b00000000000000000000000000000000; + + r_state <= READ1_ST; + result <= 32'b00000000000000000000000000000000; + calc_in_progress <= 1'b0; + r_absorb_read_counter <= 16'b0000000000000000; + enable <= 1'b0; + r_absorb_write_counter <= 16'b0000000000000000; + reset_calculator <= 1'b1; + r_toggle <= 1'b0; + end + else + begin + r_counter <= c_counter; + if (c_state == READ1_ST) + + //for(i = 0; i < 104; i = i + 1) begin + // r_const[i] <= c_const[i]; + //end + begin + + //shift register implementation for read-in constant state + +//first one is from counter +r_const__103 <= c_const__103; +// all others shift +r_const__102 <= r_const__103; +r_const__101 <= r_const__102; +r_const__100 <= r_const__101; +r_const__99 <= r_const__100; +r_const__98 <= r_const__99; +r_const__97 <= r_const__98; +r_const__96 <= r_const__97; +r_const__95 <= r_const__96; +r_const__94 <= r_const__95; +r_const__93 <= r_const__94; +r_const__92 <= r_const__93; +r_const__91 <= r_const__92; +r_const__90 <= r_const__91; +r_const__89 <= r_const__90; +r_const__88 <= r_const__89; +r_const__87 <= r_const__88; +r_const__86 <= r_const__87; +r_const__85 <= r_const__86; +r_const__84 <= r_const__85; +r_const__83 <= r_const__84; +r_const__82 <= r_const__83; +r_const__81 <= r_const__82; +r_const__80 <= r_const__81; +r_const__79 <= r_const__80; +r_const__78 <= r_const__79; +r_const__77 <= r_const__78; +r_const__76 <= r_const__77; +r_const__75 <= r_const__76; +r_const__74 <= r_const__75; +r_const__73 <= r_const__74; +r_const__72 <= r_const__73; +r_const__71 <= r_const__72; +r_const__70 <= r_const__71; +r_const__69 <= r_const__70; +r_const__68 <= r_const__69; +r_const__67 <= r_const__68; +r_const__66 <= r_const__67; +r_const__65 <= r_const__66; +r_const__64 <= r_const__65; +r_const__63 <= r_const__64; +r_const__62 <= r_const__63; +r_const__61 <= r_const__62; +r_const__60 <= r_const__61; +r_const__59 <= r_const__60; +r_const__58 <= r_const__59; +r_const__57 <= r_const__58; +r_const__56 <= r_const__57; +r_const__55 <= r_const__56; +r_const__54 <= r_const__55; +r_const__53 <= r_const__54; +r_const__52 <= r_const__53; +r_const__51 <= r_const__52; +r_const__50 <= r_const__51; +r_const__49 <= r_const__50; +r_const__48 <= r_const__49; +r_const__47 <= r_const__48; +r_const__46 <= r_const__47; +r_const__45 <= r_const__46; +r_const__44 <= r_const__45; +r_const__43 <= r_const__44; +r_const__42 <= r_const__43; +r_const__41 <= r_const__42; +r_const__40 <= r_const__41; +r_const__39 <= r_const__40; +r_const__38 <= r_const__39; +r_const__37 <= r_const__38; +r_const__36 <= r_const__37; +r_const__35 <= r_const__36; +r_const__34 <= r_const__35; +r_const__33 <= r_const__34; +r_const__32 <= r_const__33; +r_const__31 <= r_const__32; +r_const__30 <= r_const__31; +r_const__29 <= r_const__30; +r_const__28 <= r_const__29; +r_const__27 <= r_const__28; +r_const__26 <= r_const__27; +r_const__25 <= r_const__26; +r_const__24 <= r_const__25; +r_const__23 <= r_const__24; +r_const__22 <= r_const__23; +r_const__21 <= r_const__22; +r_const__20 <= r_const__21; +r_const__19 <= r_const__20; +r_const__18 <= r_const__19; +r_const__17 <= r_const__18; +r_const__16 <= r_const__17; +r_const__15 <= r_const__16; +r_const__14 <= r_const__15; +r_const__13 <= r_const__14; +r_const__12 <= r_const__13; +r_const__11 <= r_const__12; +r_const__10 <= r_const__11; +r_const__9 <= r_const__10; +r_const__8 <= r_const__9; +r_const__7 <= r_const__8; +r_const__6 <= r_const__7; +r_const__5 <= r_const__6; +r_const__4 <= r_const__5; +r_const__3 <= r_const__4; +r_const__2 <= r_const__3; +r_const__1 <= r_const__2; +r_const__0 <= r_const__1; +end +else +begin +//original code +r_const__103 <= c_const__103; +r_const__102 <= c_const__102; +r_const__101 <= c_const__101; +r_const__100 <= c_const__100; +r_const__99 <= c_const__99; +r_const__98 <= c_const__98; +r_const__97 <= c_const__97; +r_const__96 <= c_const__96; +r_const__95 <= c_const__95; +r_const__94 <= c_const__94; +r_const__93 <= c_const__93; +r_const__92 <= c_const__92; +r_const__91 <= c_const__91; +r_const__90 <= c_const__90; +r_const__89 <= c_const__89; +r_const__88 <= c_const__88; +r_const__87 <= c_const__87; +r_const__86 <= c_const__86; +r_const__85 <= c_const__85; +r_const__84 <= c_const__84; +r_const__83 <= c_const__83; +r_const__82 <= c_const__82; +r_const__81 <= c_const__81; +r_const__80 <= c_const__80; +r_const__79 <= c_const__79; +r_const__78 <= c_const__78; +r_const__77 <= c_const__77; +r_const__76 <= c_const__76; +r_const__75 <= c_const__75; +r_const__74 <= c_const__74; +r_const__73 <= c_const__73; +r_const__72 <= c_const__72; +r_const__71 <= c_const__71; +r_const__70 <= c_const__70; +r_const__69 <= c_const__69; +r_const__68 <= c_const__68; +r_const__67 <= c_const__67; +r_const__66 <= c_const__66; +r_const__65 <= c_const__65; +r_const__64 <= c_const__64; +r_const__63 <= c_const__63; +r_const__62 <= c_const__62; +r_const__61 <= c_const__61; +r_const__60 <= c_const__60; +r_const__59 <= c_const__59; +r_const__58 <= c_const__58; +r_const__57 <= c_const__57; +r_const__56 <= c_const__56; +r_const__55 <= c_const__55; +r_const__54 <= c_const__54; +r_const__53 <= c_const__53; +r_const__52 <= c_const__52; +r_const__51 <= c_const__51; +r_const__50 <= c_const__50; +r_const__49 <= c_const__49; +r_const__48 <= c_const__48; +r_const__47 <= c_const__47; +r_const__46 <= c_const__46; +r_const__45 <= c_const__45; +r_const__44 <= c_const__44; +r_const__43 <= c_const__43; +r_const__42 <= c_const__42; +r_const__41 <= c_const__41; +r_const__40 <= c_const__40; +r_const__39 <= c_const__39; +r_const__38 <= c_const__38; +r_const__37 <= c_const__37; +r_const__36 <= c_const__36; +r_const__35 <= c_const__35; +r_const__34 <= c_const__34; +r_const__33 <= c_const__33; +r_const__32 <= c_const__32; +r_const__31 <= c_const__31; +r_const__30 <= c_const__30; +r_const__29 <= c_const__29; +r_const__28 <= c_const__28; +r_const__27 <= c_const__27; +r_const__26 <= c_const__26; +r_const__25 <= c_const__25; +r_const__24 <= c_const__24; +r_const__23 <= c_const__23; +r_const__22 <= c_const__22; +r_const__21 <= c_const__21; +r_const__20 <= c_const__20; +r_const__19 <= c_const__19; +r_const__18 <= c_const__18; +r_const__17 <= c_const__17; +r_const__16 <= c_const__16; +r_const__15 <= c_const__15; +r_const__14 <= c_const__14; +r_const__13 <= c_const__13; +r_const__12 <= c_const__12; +r_const__11 <= c_const__11; +r_const__10 <= c_const__10; +r_const__9 <= c_const__9; +r_const__8 <= c_const__8; +r_const__7 <= c_const__7; +r_const__6 <= c_const__6; +r_const__5 <= c_const__5; +r_const__4 <= c_const__4; +r_const__3 <= c_const__3; +r_const__2 <= c_const__2; +r_const__1 <= c_const__1; +r_const__0 <= c_const__0; +end + + + + + r_state <= c_state; + result <= c_result; + calc_in_progress <= c_calc_in_progress; + r_absorb_read_counter <= c_absorb_read_counter; + r_absorb_write_counter <= c_absorb_write_counter; + r_toggle <= c_toggle; + //if(c_state == CALC_ST) + //begin + enable <= 1'b1; + //end + //else + //begin + // enable = 1'b0; + //end + if(c_state == RESET_MEM_ST) + begin + reset_calculator <= 1'b1; + end + else + begin + reset_calculator <= 1'b0; + end + end + end + +endmodule + + + + + + + +module dual_port_mem_zz (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram_8192x32 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_yy (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram_8192x32 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_xx (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram_8192x32 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_ww (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram_8192x32 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual (clk, data, rdaddress, wraddress , wren, q); + +// 36bit wide +// 16bit address + +input clk; +input[35:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [35:0] q; + + +wire const_zero; +wire [35:0] const_zero_data; +wire [35:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 36'b000000000000000000000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 36'b000000000000000000000000000000000000; + +dual_port_ram_65536x36 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual2 (clk, data, rdaddress, wraddress , wren, q); + +// 18bit wide +// 16bit address + +input clk; +input[17:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [17:0] q; + + +wire const_zero; +wire [17:0] const_zero_data; +wire [17:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 18'b000000000000000000; +//Comment out for don't care outputs +//assign dont_care_out = 18'b000000000000000000; + +dual_port_ram_65536x18 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual3 (clk, data, rdaddress, wraddress , wren, q); + +// 8bit wide +// 16bit address + +input clk; +input[7:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [7:0] q; + + +wire const_zero; +wire [7:0] const_zero_data; +wire [7:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 8'b00000000; +//Comment out for don't care outputs +//assign dont_care_out = 8'b00000000; + +dual_port_ram_65536x8 dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + + + + // Photon Calculator +// Note: Use the same random number for fresnel (reflect) as for scatterer because they are mutually exclusive blocks +// Also scatterer needs two + + +module PhotonCalculator ( + clock, reset, enable, + + // CONSTANTS + total_photons, + + randseed1, randseed2, randseed3, randseed4, randseed5, + + initialWeight, + + // Mover + OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5, + OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5, + OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5, + + // BoundaryChecker + z1_0, z1_1, z1_2, z1_3, z1_4, z1_5, + z0_0, z0_1, z0_2, z0_3, z0_4, z0_5, + mut_0, mut_1, mut_2, mut_3, mut_4, mut_5, + maxDepth_over_maxRadius, + + // Hop (no constants) + + // Scatterer Reflector Wrapper + down_niOverNt_1, down_niOverNt_2, down_niOverNt_3, down_niOverNt_4, down_niOverNt_5, + up_niOverNt_1, up_niOverNt_2, up_niOverNt_3, up_niOverNt_4, up_niOverNt_5, + down_niOverNt_2_1, down_niOverNt_2_2, down_niOverNt_2_3, down_niOverNt_2_4, down_niOverNt_2_5, + up_niOverNt_2_1, up_niOverNt_2_2, up_niOverNt_2_3, up_niOverNt_2_4, up_niOverNt_2_5, + downCritAngle_0, downCritAngle_1, downCritAngle_2, downCritAngle_3, downCritAngle_4, + upCritAngle_0, upCritAngle_1, upCritAngle_2, upCritAngle_3, upCritAngle_4, + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + // Interface to memory look-up + // From Memories + up_rFresnel, down_rFresnel, sint, cost, + // To Memories + tindex, fresIndex, + + // Roulette (no Constants) + + // Absorber + absorb_data, absorb_rdaddress, absorb_wraddress, + absorb_wren, absorb_q, + + // Done signal + done + ); +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter TRIG_WIDTH=10; +//parameter PIPELINE_DEPTH_UPPER_LIMIT = 256; +//parameter ABSORB_ADDR_WIDTH=16; +//parameter ABSORB_WORD_WIDTH=64; +//parameter WSCALE=1919999; + + +input clock, reset, enable; + +// CONSTANTS +input [`BIT_WIDTH-1:0] total_photons; + +input [`BIT_WIDTH-1:0] randseed1; +input [`BIT_WIDTH-1:0] randseed2; +input [`BIT_WIDTH-1:0] randseed3; +input [`BIT_WIDTH-1:0] randseed4; +input [`BIT_WIDTH-1:0] randseed5; + +input [`BIT_WIDTH-1:0] initialWeight; + +// Mover +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5; +input [`BIT_WIDTH-1:0] OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5; + +// BoundaryChecker +input [`BIT_WIDTH-1:0] z1_0, z1_1, z1_2, z1_3, z1_4, z1_5; +input [`BIT_WIDTH-1:0] z0_0, z0_1, z0_2, z0_3, z0_4, z0_5; +input [`BIT_WIDTH-1:0] mut_0, mut_1, mut_2, mut_3, mut_4, mut_5; +input [`BIT_WIDTH-1:0] maxDepth_over_maxRadius; + +// Hop (no constants) + +// Scatterer Reflector Absorber Wrapper +input [`BIT_WIDTH-1:0] down_niOverNt_1, down_niOverNt_2, down_niOverNt_3, down_niOverNt_4, down_niOverNt_5; +input [`BIT_WIDTH-1:0] up_niOverNt_1, up_niOverNt_2, up_niOverNt_3, up_niOverNt_4, up_niOverNt_5; +input [2*`BIT_WIDTH-1:0] down_niOverNt_2_1, down_niOverNt_2_2, down_niOverNt_2_3, down_niOverNt_2_4, down_niOverNt_2_5; +input [2*`BIT_WIDTH-1:0] up_niOverNt_2_1, up_niOverNt_2_2, up_niOverNt_2_3, up_niOverNt_2_4, up_niOverNt_2_5; +input [`BIT_WIDTH-1:0] downCritAngle_0, downCritAngle_1, downCritAngle_2, downCritAngle_3, downCritAngle_4; +input [`BIT_WIDTH-1:0] upCritAngle_0, upCritAngle_1, upCritAngle_2, upCritAngle_3, upCritAngle_4; +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + + // Memory look-up interface +input [`BIT_WIDTH-1:0] up_rFresnel; +input [`BIT_WIDTH-1:0] down_rFresnel; +input [`BIT_WIDTH-1:0] sint; +input [`BIT_WIDTH-1:0] cost; + //To Memories +output [12:0] tindex; +output [9:0] fresIndex; + +// Roulette Module (nothing) + +// Final results +output [`ABSORB_ADDR_WIDTH-1:0] absorb_rdaddress, absorb_wraddress; +output absorb_wren; +output [`ABSORB_WORD_WIDTH-1:0] absorb_data; +input [`ABSORB_WORD_WIDTH-1:0] absorb_q; + +// Flag when final results ready +output done; + + +// Local variables +// Wired nets +/*mover inputs*/ +reg [`BIT_WIDTH-1:0] x_moverMux; +reg [`BIT_WIDTH-1:0] y_moverMux; +reg [`BIT_WIDTH-1:0] z_moverMux; +reg [`BIT_WIDTH-1:0] ux_moverMux; +reg [`BIT_WIDTH-1:0] uy_moverMux; +reg [`BIT_WIDTH-1:0] uz_moverMux; +reg [`BIT_WIDTH-1:0] sz_moverMux; +reg [`BIT_WIDTH-1:0] sr_moverMux; +reg [`BIT_WIDTH-1:0] sleftz_moverMux; +reg [`BIT_WIDTH-1:0] sleftr_moverMux; +reg [`LAYER_WIDTH-1:0] layer_moverMux; +reg [`BIT_WIDTH-1:0] weight_moverMux; +reg dead_moverMux; + +/*mover outputs*/ +wire [`BIT_WIDTH-1:0] x_mover; +wire [`BIT_WIDTH-1:0] y_mover; +wire [`BIT_WIDTH-1:0] z_mover; +wire [`BIT_WIDTH-1:0] ux_mover; +wire [`BIT_WIDTH-1:0] uy_mover; +wire [`BIT_WIDTH-1:0] uz_mover; +wire [`BIT_WIDTH-1:0] sz_mover; +wire [`BIT_WIDTH-1:0] sr_mover; +wire [`BIT_WIDTH-1:0] sleftz_mover; +wire [`BIT_WIDTH-1:0] sleftr_mover; +wire [`LAYER_WIDTH-1:0] layer_mover; +wire [`BIT_WIDTH-1:0] weight_mover; +wire dead_mover; + +/*boundary checker outputs*/ +wire [`BIT_WIDTH-1:0] x_boundaryChecker; +wire [`BIT_WIDTH-1:0] y_boundaryChecker; +wire [`BIT_WIDTH-1:0] z_boundaryChecker; +wire [`BIT_WIDTH-1:0] ux_boundaryChecker; +wire [`BIT_WIDTH-1:0] uy_boundaryChecker; +wire [`BIT_WIDTH-1:0] uz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sr_boundaryChecker; +wire [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +wire [`LAYER_WIDTH-1:0] layer_boundaryChecker; +wire [`BIT_WIDTH-1:0] weight_boundaryChecker; +wire dead_boundaryChecker; +wire hit_boundaryChecker; + +/*hop outputs*/ +wire [`BIT_WIDTH-1:0] x_hop; +wire [`BIT_WIDTH-1:0] y_hop; +wire [`BIT_WIDTH-1:0] z_hop; +wire [`BIT_WIDTH-1:0] ux_hop; +wire [`BIT_WIDTH-1:0] uy_hop; +wire [`BIT_WIDTH-1:0] uz_hop; +wire [`BIT_WIDTH-1:0] sz_hop; +wire [`BIT_WIDTH-1:0] sr_hop; +wire [`BIT_WIDTH-1:0] sleftz_hop; +wire [`BIT_WIDTH-1:0] sleftr_hop; +wire [`LAYER_WIDTH-1:0] layer_hop; +wire [`BIT_WIDTH-1:0] weight_hop; +wire dead_hop; +wire hit_hop; + +/*Drop spin outputs*/ +wire [`BIT_WIDTH-1:0] x_dropSpin; +wire [`BIT_WIDTH-1:0] y_dropSpin; +wire [`BIT_WIDTH-1:0] z_dropSpin; +wire [`BIT_WIDTH-1:0] ux_dropSpin; +wire [`BIT_WIDTH-1:0] uy_dropSpin; +wire [`BIT_WIDTH-1:0] uz_dropSpin; +wire [`BIT_WIDTH-1:0] sz_dropSpin; +wire [`BIT_WIDTH-1:0] sr_dropSpin; +wire [`BIT_WIDTH-1:0] sleftz_dropSpin; +wire [`BIT_WIDTH-1:0] sleftr_dropSpin; +wire [`LAYER_WIDTH-1:0] layer_dropSpin; +wire [`BIT_WIDTH-1:0] weight_dropSpin; +wire dead_dropSpin; +//Had to add this one to avoid implicit net: +wire hit_dropSpin; + +/*Dead or Alive outputs*/ +wire [`BIT_WIDTH-1:0] x_Roulette; +wire [`BIT_WIDTH-1:0] y_Roulette; +wire [`BIT_WIDTH-1:0] z_Roulette; +wire [`BIT_WIDTH-1:0] ux_Roulette; +wire [`BIT_WIDTH-1:0] uy_Roulette; +wire [`BIT_WIDTH-1:0] uz_Roulette; +wire [`BIT_WIDTH-1:0] sz_Roulette; +wire [`BIT_WIDTH-1:0] sr_Roulette; +wire [`BIT_WIDTH-1:0] sleftz_Roulette; +wire [`BIT_WIDTH-1:0] sleftr_Roulette; +wire [`LAYER_WIDTH-1:0] layer_Roulette; +wire [`BIT_WIDTH-1:0] weight_Roulette; +wire dead_Roulette; + +// internals +wire [`BIT_WIDTH-1:0] rand1, rand2, rand3, rand4, rand5; +wire [`BIT_WIDTH-1:0] logrand; + +// Combinational Drivers +reg [`BIT_WIDTH-1:0] c_num_photons_left; +reg [`BIT_WIDTH-1:0] c_counter; +reg c_done; + +// Registered Drivers +reg r_done; +reg loadseed; +reg delay_loadseed; + + +reg [`BIT_WIDTH-1:0] r_num_photons_left; +reg [`BIT_WIDTH-1:0] r_counter; + +assign done = r_done; + +//Cannot be logic in instantiatino: +wire not_reset; +assign not_reset = ~reset; + +// Connect blocks +LogCalc log_u1(.clock(clock), .reset(reset), .enable(1'b1), .in_x(rand1), .log_x(logrand)); +rng rand_u1(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed1), .number_o(rand1)); +rng rand_u2(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed2), .number_o(rand2)); +rng rand_u3(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed3), .number_o(rand3)); +rng rand_u4(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed4), .number_o(rand4)); +rng rand_u5(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed5), .number_o(rand5)); + +Move mover( .clock(clock), .reset(reset), .enable(enable), + .x_moverMux(x_moverMux), .y_moverMux(y_moverMux), .z_moverMux(z_moverMux), + .ux_moverMux(ux_moverMux), .uy_moverMux(uy_moverMux), .uz_moverMux(uz_moverMux), + .sz_moverMux(sz_moverMux), .sr_moverMux(sr_moverMux), + .sleftz_moverMux(sleftz_moverMux), .sleftr_moverMux(sleftr_moverMux), + .layer_moverMux(layer_moverMux), .weight_moverMux(weight_moverMux), .dead_moverMux(dead_moverMux), + + .log_rand_num(logrand), + + //OUTPUTS + .x_mover(x_mover), .y_mover(y_mover), .z_mover(z_mover), + .ux_mover(ux_mover), .uy_mover(uy_mover), .uz_mover(uz_mover), + .sz_mover(sz_mover), .sr_mover(sr_mover), + .sleftz_mover(sleftz_mover), .sleftr_mover(sleftr_mover), + .layer_mover(layer_mover), .weight_mover(weight_mover), .dead_mover(dead_mover), + + // CONSTANTS + .OneOver_MutMaxrad_0(OneOver_MutMaxrad_0), .OneOver_MutMaxrad_1(OneOver_MutMaxrad_1), .OneOver_MutMaxrad_2(OneOver_MutMaxrad_2), .OneOver_MutMaxrad_3(OneOver_MutMaxrad_3), .OneOver_MutMaxrad_4(OneOver_MutMaxrad_4), .OneOver_MutMaxrad_5(OneOver_MutMaxrad_5), + .OneOver_MutMaxdep_0(OneOver_MutMaxdep_0), .OneOver_MutMaxdep_1(OneOver_MutMaxdep_1), .OneOver_MutMaxdep_2(OneOver_MutMaxdep_2), .OneOver_MutMaxdep_3(OneOver_MutMaxdep_3), .OneOver_MutMaxdep_4(OneOver_MutMaxdep_4), .OneOver_MutMaxdep_5(OneOver_MutMaxdep_5), + .OneOver_Mut_0(OneOver_Mut_0), .OneOver_Mut_1(OneOver_Mut_1), .OneOver_Mut_2(OneOver_Mut_2), .OneOver_Mut_3(OneOver_Mut_3), .OneOver_Mut_4(OneOver_Mut_4), .OneOver_Mut_5(OneOver_Mut_5) + ); + +Boundary boundaryChecker ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_mover(x_mover), .y_mover(y_mover), .z_mover(z_mover), + .ux_mover(ux_mover), .uy_mover(uy_mover), .uz_mover(uz_mover), + .sz_mover(sz_mover), .sr_mover(sr_mover), + .sleftz_mover(sleftz_mover), .sleftr_mover(sleftr_mover), + .layer_mover(layer_mover), .weight_mover(weight_mover), .dead_mover(dead_mover), + + //OUTPUTS + .x_boundaryChecker(x_boundaryChecker), .y_boundaryChecker(y_boundaryChecker), .z_boundaryChecker(z_boundaryChecker), + .ux_boundaryChecker(ux_boundaryChecker), .uy_boundaryChecker(uy_boundaryChecker), .uz_boundaryChecker(uz_boundaryChecker), + .sz_boundaryChecker(sz_boundaryChecker), .sr_boundaryChecker(sr_boundaryChecker), + .sleftz_boundaryChecker(sleftz_boundaryChecker), .sleftr_boundaryChecker(sleftr_boundaryChecker), + .layer_boundaryChecker(layer_boundaryChecker), .weight_boundaryChecker(weight_boundaryChecker), .dead_boundaryChecker(dead_boundaryChecker), .hit_boundaryChecker(hit_boundaryChecker), + + //CONSTANTS + .z1_0(z1_0), .z1_1(z1_1), .z1_2(z1_2), .z1_3(z1_3), .z1_4(z1_4), .z1_5(z1_5), + .z0_0(z0_0), .z0_1(z0_1), .z0_2(z0_2), .z0_3(z0_3), .z0_4(z0_4), .z0_5(z0_5), + .mut_0(mut_0), .mut_1(mut_1), .mut_2(mut_2), .mut_3(mut_3), .mut_4(mut_4), .mut_5(mut_5), + .maxDepth_over_maxRadius(maxDepth_over_maxRadius) + ); + +Hop hopper ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_boundaryChecker(x_boundaryChecker), .y_boundaryChecker(y_boundaryChecker), .z_boundaryChecker(z_boundaryChecker), + .ux_boundaryChecker(ux_boundaryChecker), .uy_boundaryChecker(uy_boundaryChecker), .uz_boundaryChecker(uz_boundaryChecker), + .sz_boundaryChecker(sz_boundaryChecker), .sr_boundaryChecker(sr_boundaryChecker), + .sleftz_boundaryChecker(sleftz_boundaryChecker), .sleftr_boundaryChecker(sleftr_boundaryChecker), + .layer_boundaryChecker(layer_boundaryChecker), .weight_boundaryChecker(weight_boundaryChecker), .dead_boundaryChecker(dead_boundaryChecker), + .hit_boundaryChecker(hit_boundaryChecker), + + //OUTPUTS + .x_hop(x_hop), .y_hop(y_hop), .z_hop(z_hop), + .ux_hop(ux_hop), .uy_hop(uy_hop), .uz_hop(uz_hop), + .sz_hop(sz_hop), .sr_hop(sr_hop), + .sleftz_hop(sleftz_hop), .sleftr_hop(sleftr_hop), + .layer_hop(layer_hop), .weight_hop(weight_hop), .dead_hop(dead_hop), .hit_hop(hit_hop) + ); + +Roulette Roulette ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_RouletteMux(x_dropSpin), .y_RouletteMux(y_dropSpin), .z_RouletteMux(z_dropSpin), + .ux_RouletteMux(ux_dropSpin), .uy_RouletteMux(uy_dropSpin), .uz_RouletteMux(uz_dropSpin), + .sz_RouletteMux(sz_dropSpin), .sr_RouletteMux(sr_dropSpin), + .sleftz_RouletteMux(sleftz_dropSpin), .sleftr_RouletteMux(sleftr_dropSpin), + .layer_RouletteMux(layer_dropSpin), .weight_absorber(weight_dropSpin), .dead_RouletteMux(dead_dropSpin), + .randnumber(rand4), + + //OUTPUTS + .x_Roulette(x_Roulette), .y_Roulette(y_Roulette), .z_Roulette(z_Roulette), + .ux_Roulette(ux_Roulette), .uy_Roulette(uy_Roulette), .uz_Roulette(uz_Roulette), + .sz_Roulette(sz_Roulette), .sr_Roulette(sr_Roulette), + .sleftz_Roulette(sleftz_Roulette), .sleftr_Roulette(sleftr_Roulette), + .layer_Roulette(layer_Roulette), .weight_Roulette(weight_Roulette), .dead_Roulette(dead_Roulette) + ); + + +DropSpinWrapper dropSpin ( + .clock(clock), .reset(reset), .enable(enable), + + //From Hopper Module + .i_x(x_hop), + .i_y(y_hop), + .i_z(z_hop), + .i_ux(ux_hop), + .i_uy(uy_hop), + .i_uz(uz_hop), + .i_sz(sz_hop), + .i_sr(sr_hop), + .i_sleftz(sleftz_hop), + .i_sleftr(sleftr_hop), + .i_weight(weight_hop), + .i_layer(layer_hop), + .i_dead(dead_hop), + .i_hit(hit_hop), + + //From System Register File (5 layers)- Absorber + .muaFraction1(muaFraction1), .muaFraction2(muaFraction2), .muaFraction3(muaFraction3), .muaFraction4(muaFraction4), .muaFraction5(muaFraction5), + + //From System Register File - ScattererReflector + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + // port to memory + .data(absorb_data), .rdaddress(absorb_rdaddress), .wraddress(absorb_wraddress), + .wren(absorb_wren), .q(absorb_q), + + //Generated by random number generators controlled by skeleton + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + .sint(sint), + .cost(cost), + .rand2(rand2), + .rand3(rand3), + .rand5(rand5), + //To Memories + .tindex(tindex), + .fresIndex(fresIndex), + + + + //To Roulette Module + .o_x(x_dropSpin), + .o_y(y_dropSpin), + .o_z(z_dropSpin), + .o_ux(ux_dropSpin), + .o_uy(uy_dropSpin), + .o_uz(uz_dropSpin), + .o_sz(sz_dropSpin), + .o_sr(sr_dropSpin), + .o_sleftz(sleftz_dropSpin), + .o_sleftr(sleftr_dropSpin), + .o_weight(weight_dropSpin), + .o_layer(layer_dropSpin), + .o_dead(dead_dropSpin), + .o_hit(hit_dropSpin) + + ); + +// Determine how many photons left +always @(r_num_photons_left or dead_Roulette or r_done or r_counter) +begin + //c_num_photons_left = r_num_photons_left; + //c_counter = 0; + + if(dead_Roulette == 1'b1 && r_done == 1'b0) + begin + if(r_num_photons_left > 0) + begin + c_num_photons_left = r_num_photons_left - 1; + c_counter = 0; + end + else + begin + c_counter = r_counter + 1; + c_num_photons_left = r_num_photons_left; + end + end + else + begin + c_num_photons_left = r_num_photons_left; + c_counter = 0; + end +end + +// Only state info is done +always @(r_done or r_counter) +begin + //c_done = r_done; + if(r_counter > `PIPELINE_DEPTH_UPPER_LIMIT) + begin + c_done = 1'b1; + end else begin + c_done = r_done; + end +end + +// Create mux to mover +always @(dead_Roulette or initialWeight or r_num_photons_left or x_Roulette or y_Roulette or z_Roulette or + ux_Roulette or uy_Roulette or uz_Roulette or sz_Roulette or sr_Roulette or sleftz_Roulette or + sleftr_Roulette or layer_Roulette or weight_Roulette or dead_Roulette) +begin + if(dead_Roulette) + begin + x_moverMux = 0; + y_moverMux = 0; + z_moverMux = 0; + ux_moverMux = 0; + uy_moverMux = 0; + uz_moverMux = 32'h7fffffff; + sz_moverMux = 0; + sr_moverMux = 0; + sleftz_moverMux = 0; + sleftr_moverMux = 0; + layer_moverMux = 3'b01; + weight_moverMux = initialWeight; + if(r_num_photons_left > 0) + begin + dead_moverMux = 1'b0; + end + else + begin + dead_moverMux = 1'b1; + end + end + else + begin + x_moverMux = x_Roulette; + y_moverMux = y_Roulette; + z_moverMux = z_Roulette; + ux_moverMux = ux_Roulette; + uy_moverMux = uy_Roulette; + uz_moverMux = uz_Roulette; + sz_moverMux = sz_Roulette; + sr_moverMux = sr_Roulette; + sleftz_moverMux = sleftz_Roulette; + sleftr_moverMux = sleftr_Roulette; + layer_moverMux = layer_Roulette; + weight_moverMux = weight_Roulette; + dead_moverMux = dead_Roulette; + end +end + +// register state +always @(posedge clock) +begin + if(reset) + begin + r_num_photons_left <= total_photons; + r_counter <= 1'b0; + r_done <= 1'b0; + delay_loadseed <= 1'b1; + loadseed <= 1'b1; + end + else + begin + if(enable) + begin + r_num_photons_left <= c_num_photons_left; + r_counter <= c_counter; + r_done <= c_done; + delay_loadseed <= 1'b0; + loadseed <= delay_loadseed; + end + end +end +endmodule + + +module Move( //INPUTS + clock, reset, enable, + x_moverMux, y_moverMux, z_moverMux, + ux_moverMux, uy_moverMux, uz_moverMux, + sz_moverMux, sr_moverMux, + sleftz_moverMux, sleftr_moverMux, + layer_moverMux, weight_moverMux, dead_moverMux, + + log_rand_num, + + //OUTPUTS + x_mover, y_mover, z_mover, + ux_mover, uy_mover, uz_mover, + sz_mover, sr_mover, + sleftz_mover, sleftr_mover, + layer_mover, weight_mover, dead_mover, + + // CONSTANTS + OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5, + OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5, + OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5 + ); + + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_moverMux; +input [`BIT_WIDTH-1:0] y_moverMux; +input [`BIT_WIDTH-1:0] z_moverMux; +input [`BIT_WIDTH-1:0] ux_moverMux; +input [`BIT_WIDTH-1:0] uy_moverMux; +input [`BIT_WIDTH-1:0] uz_moverMux; +input [`BIT_WIDTH-1:0] sz_moverMux; +input [`BIT_WIDTH-1:0] sr_moverMux; +input [`BIT_WIDTH-1:0] sleftz_moverMux; +input [`BIT_WIDTH-1:0] sleftr_moverMux; +input [`LAYER_WIDTH-1:0] layer_moverMux; +input [`BIT_WIDTH-1:0] weight_moverMux; +input dead_moverMux; + +output [`BIT_WIDTH-1:0] x_mover; +output [`BIT_WIDTH-1:0] y_mover; +output [`BIT_WIDTH-1:0] z_mover; +output [`BIT_WIDTH-1:0] ux_mover; +output [`BIT_WIDTH-1:0] uy_mover; +output [`BIT_WIDTH-1:0] uz_mover; +output [`BIT_WIDTH-1:0] sz_mover; +output [`BIT_WIDTH-1:0] sr_mover; +output [`BIT_WIDTH-1:0] sleftz_mover; +output [`BIT_WIDTH-1:0] sleftr_mover; +output [`LAYER_WIDTH-1:0]layer_mover; +output [`BIT_WIDTH-1:0] weight_mover; +output dead_mover; + + +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_0; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_1; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_2; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_3; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_4; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_5; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_0; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_1; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_2; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_3; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_4; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_5; +input [`BIT_WIDTH-1:0] OneOver_Mut_0; +input [`BIT_WIDTH-1:0] OneOver_Mut_1; +input [`BIT_WIDTH-1:0] OneOver_Mut_2; +input [`BIT_WIDTH-1:0] OneOver_Mut_3; +input [`BIT_WIDTH-1:0] OneOver_Mut_4; +input [`BIT_WIDTH-1:0] OneOver_Mut_5; +input [`BIT_WIDTH-1:0] log_rand_num; + +//------------Local Variables------------------------ +reg [`BIT_WIDTH-1:0] c_sr; +reg [`BIT_WIDTH-1:0] c_sz; +reg [2*`BIT_WIDTH-1:0] c_sr_big; +reg [2*`BIT_WIDTH-1:0] c_sz_big; +reg [`BIT_WIDTH-1:0] c_sleftr; +reg [`BIT_WIDTH-1:0] c_sleftz; + +//No signed regs, unsigned unecessary +//reg unsigned [`BIT_WIDTH-1:0] c_r_op0; +//reg unsigned [`BIT_WIDTH-1:0] c_r_op1; +//reg unsigned [`BIT_WIDTH-1:0] c_z_op0; +//reg unsigned [`BIT_WIDTH-1:0] c_z_op1; + +reg [`BIT_WIDTH-1:0] c_r_op0; +reg [`BIT_WIDTH-1:0] c_r_op1; +reg [`BIT_WIDTH-1:0] c_z_op0; +reg [`BIT_WIDTH-1:0] c_z_op1; + +// grab multiplexed constant +reg [`BIT_WIDTH-1:0] OneOver_MutMaxrad; +reg [`BIT_WIDTH-1:0] OneOver_MutMaxdep; +reg [`BIT_WIDTH-1:0] OneOver_Mut; + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_mover; +reg [`BIT_WIDTH-1:0] y_mover; +reg [`BIT_WIDTH-1:0] z_mover; +reg [`BIT_WIDTH-1:0] ux_mover; +reg [`BIT_WIDTH-1:0] uy_mover; +reg [`BIT_WIDTH-1:0] uz_mover; +reg [`BIT_WIDTH-1:0] sz_mover; +reg [`BIT_WIDTH-1:0] sr_mover; +reg [`BIT_WIDTH-1:0] sleftz_mover; +reg [`BIT_WIDTH-1:0] sleftr_mover; +reg [`LAYER_WIDTH-1:0]layer_mover; +reg [`BIT_WIDTH-1:0] weight_mover; +reg dead_mover; + + +//Need this to deal with 'unused' inputs for ODIN II +wire bigOr; +assign bigOr = sr_moverMux[0] | sr_moverMux[1] | sr_moverMux[2] | sr_moverMux[3] | sr_moverMux[4] | sr_moverMux[5] | + sr_moverMux[6] | sr_moverMux[7] | sr_moverMux[8] | sr_moverMux[9] | sr_moverMux[10] | sr_moverMux[11] | + sr_moverMux[12] | sr_moverMux[13] | sr_moverMux[14] | sr_moverMux[15] | sr_moverMux[16] | sr_moverMux[17] | + sr_moverMux[18] | sr_moverMux[19] | sr_moverMux[20] | sr_moverMux[21] | sr_moverMux[22] | sr_moverMux[23] | + sr_moverMux[24] | sr_moverMux[25] | sr_moverMux[26] | sr_moverMux[27] | sr_moverMux[28] | sr_moverMux[29] | + sr_moverMux[30] | sr_moverMux[31] | + sz_moverMux[0] | sz_moverMux[1] | sz_moverMux[2] | sz_moverMux[3] | sz_moverMux[4] | sz_moverMux[5] | + sz_moverMux[6] | sz_moverMux[7] | sz_moverMux[8] | sz_moverMux[9] | sz_moverMux[10] | sz_moverMux[11] | + sz_moverMux[12] | sz_moverMux[13] | sz_moverMux[14] | sz_moverMux[15] | sz_moverMux[16] | sz_moverMux[17] | + sz_moverMux[18] | sz_moverMux[19] | sz_moverMux[20] | sz_moverMux[21] | sz_moverMux[22] | sz_moverMux[23] | + sz_moverMux[24] | sz_moverMux[25] | sz_moverMux[26] | sz_moverMux[27] | sz_moverMux[28] | sz_moverMux[29] | + sz_moverMux[30] | sz_moverMux[31] | + 1'b1; +wire reset_new; +assign reset_new = reset & bigOr; + +// multiplex constants +always @(layer_moverMux or OneOver_MutMaxrad_0 or OneOver_MutMaxdep_0 or OneOver_Mut_0 or + OneOver_MutMaxrad_1 or OneOver_MutMaxdep_1 or OneOver_Mut_1 or + OneOver_MutMaxrad_2 or OneOver_MutMaxdep_2 or OneOver_Mut_2 or + OneOver_MutMaxrad_3 or OneOver_MutMaxdep_3 or OneOver_Mut_3 or + OneOver_MutMaxrad_4 or OneOver_MutMaxdep_4 or OneOver_Mut_4 or + OneOver_MutMaxrad_5 or OneOver_MutMaxdep_5 or OneOver_Mut_5) +begin +case(layer_moverMux) + 3'b000: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_0; + OneOver_MutMaxdep = OneOver_MutMaxdep_0; + OneOver_Mut = OneOver_Mut_0; + end + 3'b001: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_1; + OneOver_MutMaxdep = OneOver_MutMaxdep_1; + OneOver_Mut = OneOver_Mut_1; + end + 3'b010: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_2; + OneOver_MutMaxdep = OneOver_MutMaxdep_2; + OneOver_Mut = OneOver_Mut_2; + end + 3'b011: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_3; + OneOver_MutMaxdep = OneOver_MutMaxdep_3; + OneOver_Mut = OneOver_Mut_3; + end + 3'b100: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_4; + OneOver_MutMaxdep = OneOver_MutMaxdep_4; + OneOver_Mut = OneOver_Mut_4; + end + 3'b101: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_5; + OneOver_MutMaxdep = OneOver_MutMaxdep_5; + OneOver_Mut = OneOver_Mut_5; + end + default: + begin + OneOver_MutMaxrad = 0; + OneOver_MutMaxdep = 0; + OneOver_Mut = 0; + end +endcase +end + +// Determine move value +always @(sleftz_moverMux or log_rand_num or OneOver_MutMaxrad or OneOver_MutMaxdep or sleftr_moverMux or + OneOver_Mut) +begin + // Resource sharing for multipliers + if(sleftz_moverMux == 32'b0) + begin + c_r_op0 = `MAXLOG - log_rand_num; + c_r_op1 = OneOver_MutMaxrad; + c_z_op0 = `MAXLOG - log_rand_num; + c_z_op1 = OneOver_MutMaxdep; + end + else + begin + c_r_op0 = sleftr_moverMux; + c_r_op1 = OneOver_Mut; + c_z_op0 = sleftz_moverMux; + c_z_op1 = OneOver_Mut; + end +end + +// Determine move value +always @(sleftz_moverMux or c_r_op0 or c_r_op1 or c_z_op0 or c_z_op1 or sleftr_moverMux) +begin + c_sr_big = c_r_op0 * c_r_op1; + c_sz_big = c_z_op0 * c_z_op1; + if(sleftz_moverMux == 32'b0) + begin + c_sr = c_sr_big[2*`BIT_WIDTH - `LOGSCALEFACTOR - 1:`BIT_WIDTH - `LOGSCALEFACTOR]; + c_sz = c_sz_big[2*`BIT_WIDTH - `LOGSCALEFACTOR - 1:`BIT_WIDTH - `LOGSCALEFACTOR]; + + c_sleftr = sleftr_moverMux; + c_sleftz = 0; + + //c_sr = `CONST_MOVE_AMOUNT; + //c_sz = `CONST_MOVE_AMOUNT; + end + else + begin + c_sr = c_sr_big[2*`BIT_WIDTH - `MUTMAX_BITS - 1 - 1:`BIT_WIDTH - `MUTMAX_BITS - 1]; + c_sz = c_sz_big[2*`BIT_WIDTH - `MUTMAX_BITS - 1 - 1:`BIT_WIDTH - `MUTMAX_BITS - 1]; + + c_sleftz = 0; + c_sleftr = 0; + end +end + +// latch values +always @ (posedge clock) +begin + if (reset_new) + begin + // Photon variables + x_mover <= 0; + y_mover <= 0; + z_mover <= 0; + ux_mover <= 0; + uy_mover <= 0; + uz_mover <= 0; + sz_mover <= 0; + sr_mover <= 0; + sleftz_mover <= 0; + sleftr_mover <= 0; + layer_mover <= 0; + weight_mover <= 0; + dead_mover <= 1'b1; + end + else + begin + if(enable) + begin + // Photon variables + x_mover <= x_moverMux; + y_mover <= y_moverMux; + z_mover <= z_moverMux; + ux_mover <= ux_moverMux; + uy_mover <= uy_moverMux; + uz_mover <= uz_moverMux; + layer_mover <= layer_moverMux; + weight_mover <= weight_moverMux; + dead_mover <= dead_moverMux; + + sz_mover <= c_sz; + sr_mover <= c_sr; + sleftz_mover <= c_sleftz; + sleftr_mover <= c_sleftr; + end + end +end + +endmodule + + +module Boundary ( //INPUTS + clock, reset, enable, + x_mover, y_mover, z_mover, + ux_mover, uy_mover, uz_mover, + sz_mover, sr_mover, + sleftz_mover, sleftr_mover, + layer_mover, weight_mover, dead_mover, + + //OUTPUTS + x_boundaryChecker, y_boundaryChecker, z_boundaryChecker, + ux_boundaryChecker, uy_boundaryChecker, uz_boundaryChecker, + sz_boundaryChecker, sr_boundaryChecker, + sleftz_boundaryChecker, sleftr_boundaryChecker, + layer_boundaryChecker, weight_boundaryChecker, dead_boundaryChecker, hit_boundaryChecker, + + //CONSTANTS + z1_0, z1_1, z1_2, z1_3, z1_4, z1_5, + z0_0, z0_1, z0_2, z0_3, z0_4, z0_5, + mut_0, mut_1, mut_2, mut_3, mut_4, mut_5, + maxDepth_over_maxRadius + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter INTMAX=2147483647; +//parameter INTMIN=-2147483648; +//parameter DIVIDER_LATENCY=30; +//parameter FINAL_LATENCY=28; +//parameter MULT_LATENCY=1; +//parameter ASPECT_RATIO = 7; +//parameter TOTAL_LATENCY = `DIVIDER_LATENCY + `FINAL_LATENCY + `MULT_LATENCY + `MULT_LATENCY; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_mover; +input [`BIT_WIDTH-1:0] y_mover; +input [`BIT_WIDTH-1:0] z_mover; +input [`BIT_WIDTH-1:0] ux_mover; +input [`BIT_WIDTH-1:0] uy_mover; +input [`BIT_WIDTH-1:0] uz_mover; +input [`BIT_WIDTH-1:0] sz_mover; +input [`BIT_WIDTH-1:0] sr_mover; +input [`BIT_WIDTH-1:0] sleftz_mover; +input [`BIT_WIDTH-1:0] sleftr_mover; +input [`LAYER_WIDTH-1:0] layer_mover; +input [`BIT_WIDTH-1:0] weight_mover; +input dead_mover; + +output [`BIT_WIDTH-1:0] x_boundaryChecker; +output [`BIT_WIDTH-1:0] y_boundaryChecker; +output [`BIT_WIDTH-1:0] z_boundaryChecker; +output [`BIT_WIDTH-1:0] ux_boundaryChecker; +output [`BIT_WIDTH-1:0] uy_boundaryChecker; +output [`BIT_WIDTH-1:0] uz_boundaryChecker; +output [`BIT_WIDTH-1:0] sz_boundaryChecker; +output [`BIT_WIDTH-1:0] sr_boundaryChecker; +output [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +output [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +output [`LAYER_WIDTH-1:0]layer_boundaryChecker; +output [`BIT_WIDTH-1:0] weight_boundaryChecker; +output dead_boundaryChecker; +output hit_boundaryChecker; + +// Constants +input [`BIT_WIDTH-1:0] z1_0; +input [`BIT_WIDTH-1:0] z1_1; +input [`BIT_WIDTH-1:0] z1_2; +input [`BIT_WIDTH-1:0] z1_3; +input [`BIT_WIDTH-1:0] z1_4; +input [`BIT_WIDTH-1:0] z1_5; +input [`BIT_WIDTH-1:0] z0_0; +input [`BIT_WIDTH-1:0] z0_1; +input [`BIT_WIDTH-1:0] z0_2; +input [`BIT_WIDTH-1:0] z0_3; +input [`BIT_WIDTH-1:0] z0_4; +input [`BIT_WIDTH-1:0] z0_5; +input [`BIT_WIDTH-1:0] mut_0; +input [`BIT_WIDTH-1:0] mut_1; +input [`BIT_WIDTH-1:0] mut_2; +input [`BIT_WIDTH-1:0] mut_3; +input [`BIT_WIDTH-1:0] mut_4; +input [`BIT_WIDTH-1:0] mut_5; +input [`BIT_WIDTH-1:0] maxDepth_over_maxRadius; + + +//WIRES FOR CONNECTING REGISTERS +//reg [BIT_WIDTH-1:0] c_x [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_y [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_ux [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_uy [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_uz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sleftz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sleftr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_weight [TOTAL_LATENCY - 1:0]; +//reg [LAYER_WIDTH-1:0] c_layer [TOTAL_LATENCY - 1:0]; +//reg c_dead [TOTAL_LATENCY - 1:0]; +//reg c_hit [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_diff[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_dl_b[TOTAL_LATENCY - 1:0]; +//reg [2*BIT_WIDTH-1:0] c_numer[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z1[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z0[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_mut[TOTAL_LATENCY - 1:0]; + +//reg [BIT_WIDTH-1:0] r_x [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_y [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_ux [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_uy [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_uz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sleftz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sleftr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_weight [TOTAL_LATENCY - 1:0]; +//reg [LAYER_WIDTH-1:0] r_layer [TOTAL_LATENCY - 1:0]; +//reg r_dead [TOTAL_LATENCY - 1:0]; +//reg r_hit [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_diff[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_dl_b[TOTAL_LATENCY - 1:0]; +//reg [2*BIT_WIDTH-1:0] r_numer[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z1[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z0[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_mut[TOTAL_LATENCY - 1:0]; + + +//EXPANDED FOR ODIN +//reg [BIT_WIDTH-1:0] c_x [TOTAL_LATENCY - 1:0]; +reg [`BIT_WIDTH-1:0] c_x__0; +reg [`BIT_WIDTH-1:0] c_x__1; +reg [`BIT_WIDTH-1:0] c_x__2; +reg [`BIT_WIDTH-1:0] c_x__3; +reg [`BIT_WIDTH-1:0] c_x__4; +reg [`BIT_WIDTH-1:0] c_x__5; +reg [`BIT_WIDTH-1:0] c_x__6; +reg [`BIT_WIDTH-1:0] c_x__7; +reg [`BIT_WIDTH-1:0] c_x__8; +reg [`BIT_WIDTH-1:0] c_x__9; +reg [`BIT_WIDTH-1:0] c_x__10; +reg [`BIT_WIDTH-1:0] c_x__11; +reg [`BIT_WIDTH-1:0] c_x__12; +reg [`BIT_WIDTH-1:0] c_x__13; +reg [`BIT_WIDTH-1:0] c_x__14; +reg [`BIT_WIDTH-1:0] c_x__15; +reg [`BIT_WIDTH-1:0] c_x__16; +reg [`BIT_WIDTH-1:0] c_x__17; +reg [`BIT_WIDTH-1:0] c_x__18; +reg [`BIT_WIDTH-1:0] c_x__19; +reg [`BIT_WIDTH-1:0] c_x__20; +reg [`BIT_WIDTH-1:0] c_x__21; +reg [`BIT_WIDTH-1:0] c_x__22; +reg [`BIT_WIDTH-1:0] c_x__23; +reg [`BIT_WIDTH-1:0] c_x__24; +reg [`BIT_WIDTH-1:0] c_x__25; +reg [`BIT_WIDTH-1:0] c_x__26; +reg [`BIT_WIDTH-1:0] c_x__27; +reg [`BIT_WIDTH-1:0] c_x__28; +reg [`BIT_WIDTH-1:0] c_x__29; +reg [`BIT_WIDTH-1:0] c_x__30; +reg [`BIT_WIDTH-1:0] c_x__31; +reg [`BIT_WIDTH-1:0] c_x__32; +reg [`BIT_WIDTH-1:0] c_x__33; +reg [`BIT_WIDTH-1:0] c_x__34; +reg [`BIT_WIDTH-1:0] c_x__35; +reg [`BIT_WIDTH-1:0] c_x__36; +reg [`BIT_WIDTH-1:0] c_x__37; +reg [`BIT_WIDTH-1:0] c_x__38; +reg [`BIT_WIDTH-1:0] c_x__39; +reg [`BIT_WIDTH-1:0] c_x__40; +reg [`BIT_WIDTH-1:0] c_x__41; +reg [`BIT_WIDTH-1:0] c_x__42; +reg [`BIT_WIDTH-1:0] c_x__43; +reg [`BIT_WIDTH-1:0] c_x__44; +reg [`BIT_WIDTH-1:0] c_x__45; +reg [`BIT_WIDTH-1:0] c_x__46; +reg [`BIT_WIDTH-1:0] c_x__47; +reg [`BIT_WIDTH-1:0] c_x__48; +reg [`BIT_WIDTH-1:0] c_x__49; +reg [`BIT_WIDTH-1:0] c_x__50; +reg [`BIT_WIDTH-1:0] c_x__51; +reg [`BIT_WIDTH-1:0] c_x__52; +reg [`BIT_WIDTH-1:0] c_x__53; +reg [`BIT_WIDTH-1:0] c_x__54; +reg [`BIT_WIDTH-1:0] c_x__55; +reg [`BIT_WIDTH-1:0] c_x__56; +reg [`BIT_WIDTH-1:0] c_x__57; +reg [`BIT_WIDTH-1:0] c_x__58; +reg [`BIT_WIDTH-1:0] c_x__59; + +//reg [BIT_WIDTH-1:0] c_y [TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_y__0; +reg [`BIT_WIDTH-1:0] c_y__1; +reg [`BIT_WIDTH-1:0] c_y__2; +reg [`BIT_WIDTH-1:0] c_y__3; +reg [`BIT_WIDTH-1:0] c_y__4; +reg [`BIT_WIDTH-1:0] c_y__5; +reg [`BIT_WIDTH-1:0] c_y__6; +reg [`BIT_WIDTH-1:0] c_y__7; +reg [`BIT_WIDTH-1:0] c_y__8; +reg [`BIT_WIDTH-1:0] c_y__9; +reg [`BIT_WIDTH-1:0] c_y__10; +reg [`BIT_WIDTH-1:0] c_y__11; +reg [`BIT_WIDTH-1:0] c_y__12; +reg [`BIT_WIDTH-1:0] c_y__13; +reg [`BIT_WIDTH-1:0] c_y__14; +reg [`BIT_WIDTH-1:0] c_y__15; +reg [`BIT_WIDTH-1:0] c_y__16; +reg [`BIT_WIDTH-1:0] c_y__17; +reg [`BIT_WIDTH-1:0] c_y__18; +reg [`BIT_WIDTH-1:0] c_y__19; +reg [`BIT_WIDTH-1:0] c_y__20; +reg [`BIT_WIDTH-1:0] c_y__21; +reg [`BIT_WIDTH-1:0] c_y__22; +reg [`BIT_WIDTH-1:0] c_y__23; +reg [`BIT_WIDTH-1:0] c_y__24; +reg [`BIT_WIDTH-1:0] c_y__25; +reg [`BIT_WIDTH-1:0] c_y__26; +reg [`BIT_WIDTH-1:0] c_y__27; +reg [`BIT_WIDTH-1:0] c_y__28; +reg [`BIT_WIDTH-1:0] c_y__29; +reg [`BIT_WIDTH-1:0] c_y__30; +reg [`BIT_WIDTH-1:0] c_y__31; +reg [`BIT_WIDTH-1:0] c_y__32; +reg [`BIT_WIDTH-1:0] c_y__33; +reg [`BIT_WIDTH-1:0] c_y__34; +reg [`BIT_WIDTH-1:0] c_y__35; +reg [`BIT_WIDTH-1:0] c_y__36; +reg [`BIT_WIDTH-1:0] c_y__37; +reg [`BIT_WIDTH-1:0] c_y__38; +reg [`BIT_WIDTH-1:0] c_y__39; +reg [`BIT_WIDTH-1:0] c_y__40; +reg [`BIT_WIDTH-1:0] c_y__41; +reg [`BIT_WIDTH-1:0] c_y__42; +reg [`BIT_WIDTH-1:0] c_y__43; +reg [`BIT_WIDTH-1:0] c_y__44; +reg [`BIT_WIDTH-1:0] c_y__45; +reg [`BIT_WIDTH-1:0] c_y__46; +reg [`BIT_WIDTH-1:0] c_y__47; +reg [`BIT_WIDTH-1:0] c_y__48; +reg [`BIT_WIDTH-1:0] c_y__49; +reg [`BIT_WIDTH-1:0] c_y__50; +reg [`BIT_WIDTH-1:0] c_y__51; +reg [`BIT_WIDTH-1:0] c_y__52; +reg [`BIT_WIDTH-1:0] c_y__53; +reg [`BIT_WIDTH-1:0] c_y__54; +reg [`BIT_WIDTH-1:0] c_y__55; +reg [`BIT_WIDTH-1:0] c_y__56; +reg [`BIT_WIDTH-1:0] c_y__57; +reg [`BIT_WIDTH-1:0] c_y__58; +reg [`BIT_WIDTH-1:0] c_y__59; + + +//reg [BIT_WIDTH-1:0] c_z [TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z__0; +reg [`BIT_WIDTH-1:0] c_z__1; +reg [`BIT_WIDTH-1:0] c_z__2; +reg [`BIT_WIDTH-1:0] c_z__3; +reg [`BIT_WIDTH-1:0] c_z__4; +reg [`BIT_WIDTH-1:0] c_z__5; +reg [`BIT_WIDTH-1:0] c_z__6; +reg [`BIT_WIDTH-1:0] c_z__7; +reg [`BIT_WIDTH-1:0] c_z__8; +reg [`BIT_WIDTH-1:0] c_z__9; +reg [`BIT_WIDTH-1:0] c_z__10; +reg [`BIT_WIDTH-1:0] c_z__11; +reg [`BIT_WIDTH-1:0] c_z__12; +reg [`BIT_WIDTH-1:0] c_z__13; +reg [`BIT_WIDTH-1:0] c_z__14; +reg [`BIT_WIDTH-1:0] c_z__15; +reg [`BIT_WIDTH-1:0] c_z__16; +reg [`BIT_WIDTH-1:0] c_z__17; +reg [`BIT_WIDTH-1:0] c_z__18; +reg [`BIT_WIDTH-1:0] c_z__19; +reg [`BIT_WIDTH-1:0] c_z__20; +reg [`BIT_WIDTH-1:0] c_z__21; +reg [`BIT_WIDTH-1:0] c_z__22; +reg [`BIT_WIDTH-1:0] c_z__23; +reg [`BIT_WIDTH-1:0] c_z__24; +reg [`BIT_WIDTH-1:0] c_z__25; +reg [`BIT_WIDTH-1:0] c_z__26; +reg [`BIT_WIDTH-1:0] c_z__27; +reg [`BIT_WIDTH-1:0] c_z__28; +reg [`BIT_WIDTH-1:0] c_z__29; +reg [`BIT_WIDTH-1:0] c_z__30; +reg [`BIT_WIDTH-1:0] c_z__31; +reg [`BIT_WIDTH-1:0] c_z__32; +reg [`BIT_WIDTH-1:0] c_z__33; +reg [`BIT_WIDTH-1:0] c_z__34; +reg [`BIT_WIDTH-1:0] c_z__35; +reg [`BIT_WIDTH-1:0] c_z__36; +reg [`BIT_WIDTH-1:0] c_z__37; +reg [`BIT_WIDTH-1:0] c_z__38; +reg [`BIT_WIDTH-1:0] c_z__39; +reg [`BIT_WIDTH-1:0] c_z__40; +reg [`BIT_WIDTH-1:0] c_z__41; +reg [`BIT_WIDTH-1:0] c_z__42; +reg [`BIT_WIDTH-1:0] c_z__43; +reg [`BIT_WIDTH-1:0] c_z__44; +reg [`BIT_WIDTH-1:0] c_z__45; +reg [`BIT_WIDTH-1:0] c_z__46; +reg [`BIT_WIDTH-1:0] c_z__47; +reg [`BIT_WIDTH-1:0] c_z__48; +reg [`BIT_WIDTH-1:0] c_z__49; +reg [`BIT_WIDTH-1:0] c_z__50; +reg [`BIT_WIDTH-1:0] c_z__51; +reg [`BIT_WIDTH-1:0] c_z__52; +reg [`BIT_WIDTH-1:0] c_z__53; +reg [`BIT_WIDTH-1:0] c_z__54; +reg [`BIT_WIDTH-1:0] c_z__55; +reg [`BIT_WIDTH-1:0] c_z__56; +reg [`BIT_WIDTH-1:0] c_z__57; +reg [`BIT_WIDTH-1:0] c_z__58; +reg [`BIT_WIDTH-1:0] c_z__59; + + + +//reg [`BIT_WIDTH-1:0] c_ux [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_ux__0; +reg [`BIT_WIDTH-1:0] c_ux__1; +reg [`BIT_WIDTH-1:0] c_ux__2; +reg [`BIT_WIDTH-1:0] c_ux__3; +reg [`BIT_WIDTH-1:0] c_ux__4; +reg [`BIT_WIDTH-1:0] c_ux__5; +reg [`BIT_WIDTH-1:0] c_ux__6; +reg [`BIT_WIDTH-1:0] c_ux__7; +reg [`BIT_WIDTH-1:0] c_ux__8; +reg [`BIT_WIDTH-1:0] c_ux__9; +reg [`BIT_WIDTH-1:0] c_ux__10; +reg [`BIT_WIDTH-1:0] c_ux__11; +reg [`BIT_WIDTH-1:0] c_ux__12; +reg [`BIT_WIDTH-1:0] c_ux__13; +reg [`BIT_WIDTH-1:0] c_ux__14; +reg [`BIT_WIDTH-1:0] c_ux__15; +reg [`BIT_WIDTH-1:0] c_ux__16; +reg [`BIT_WIDTH-1:0] c_ux__17; +reg [`BIT_WIDTH-1:0] c_ux__18; +reg [`BIT_WIDTH-1:0] c_ux__19; +reg [`BIT_WIDTH-1:0] c_ux__20; +reg [`BIT_WIDTH-1:0] c_ux__21; +reg [`BIT_WIDTH-1:0] c_ux__22; +reg [`BIT_WIDTH-1:0] c_ux__23; +reg [`BIT_WIDTH-1:0] c_ux__24; +reg [`BIT_WIDTH-1:0] c_ux__25; +reg [`BIT_WIDTH-1:0] c_ux__26; +reg [`BIT_WIDTH-1:0] c_ux__27; +reg [`BIT_WIDTH-1:0] c_ux__28; +reg [`BIT_WIDTH-1:0] c_ux__29; +reg [`BIT_WIDTH-1:0] c_ux__30; +reg [`BIT_WIDTH-1:0] c_ux__31; +reg [`BIT_WIDTH-1:0] c_ux__32; +reg [`BIT_WIDTH-1:0] c_ux__33; +reg [`BIT_WIDTH-1:0] c_ux__34; +reg [`BIT_WIDTH-1:0] c_ux__35; +reg [`BIT_WIDTH-1:0] c_ux__36; +reg [`BIT_WIDTH-1:0] c_ux__37; +reg [`BIT_WIDTH-1:0] c_ux__38; +reg [`BIT_WIDTH-1:0] c_ux__39; +reg [`BIT_WIDTH-1:0] c_ux__40; +reg [`BIT_WIDTH-1:0] c_ux__41; +reg [`BIT_WIDTH-1:0] c_ux__42; +reg [`BIT_WIDTH-1:0] c_ux__43; +reg [`BIT_WIDTH-1:0] c_ux__44; +reg [`BIT_WIDTH-1:0] c_ux__45; +reg [`BIT_WIDTH-1:0] c_ux__46; +reg [`BIT_WIDTH-1:0] c_ux__47; +reg [`BIT_WIDTH-1:0] c_ux__48; +reg [`BIT_WIDTH-1:0] c_ux__49; +reg [`BIT_WIDTH-1:0] c_ux__50; +reg [`BIT_WIDTH-1:0] c_ux__51; +reg [`BIT_WIDTH-1:0] c_ux__52; +reg [`BIT_WIDTH-1:0] c_ux__53; +reg [`BIT_WIDTH-1:0] c_ux__54; +reg [`BIT_WIDTH-1:0] c_ux__55; +reg [`BIT_WIDTH-1:0] c_ux__56; +reg [`BIT_WIDTH-1:0] c_ux__57; +reg [`BIT_WIDTH-1:0] c_ux__58; +reg [`BIT_WIDTH-1:0] c_ux__59; +//reg [`BIT_WIDTH-1:0] c_uy [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_uy__0; +reg [`BIT_WIDTH-1:0] c_uy__1; +reg [`BIT_WIDTH-1:0] c_uy__2; +reg [`BIT_WIDTH-1:0] c_uy__3; +reg [`BIT_WIDTH-1:0] c_uy__4; +reg [`BIT_WIDTH-1:0] c_uy__5; +reg [`BIT_WIDTH-1:0] c_uy__6; +reg [`BIT_WIDTH-1:0] c_uy__7; +reg [`BIT_WIDTH-1:0] c_uy__8; +reg [`BIT_WIDTH-1:0] c_uy__9; +reg [`BIT_WIDTH-1:0] c_uy__10; +reg [`BIT_WIDTH-1:0] c_uy__11; +reg [`BIT_WIDTH-1:0] c_uy__12; +reg [`BIT_WIDTH-1:0] c_uy__13; +reg [`BIT_WIDTH-1:0] c_uy__14; +reg [`BIT_WIDTH-1:0] c_uy__15; +reg [`BIT_WIDTH-1:0] c_uy__16; +reg [`BIT_WIDTH-1:0] c_uy__17; +reg [`BIT_WIDTH-1:0] c_uy__18; +reg [`BIT_WIDTH-1:0] c_uy__19; +reg [`BIT_WIDTH-1:0] c_uy__20; +reg [`BIT_WIDTH-1:0] c_uy__21; +reg [`BIT_WIDTH-1:0] c_uy__22; +reg [`BIT_WIDTH-1:0] c_uy__23; +reg [`BIT_WIDTH-1:0] c_uy__24; +reg [`BIT_WIDTH-1:0] c_uy__25; +reg [`BIT_WIDTH-1:0] c_uy__26; +reg [`BIT_WIDTH-1:0] c_uy__27; +reg [`BIT_WIDTH-1:0] c_uy__28; +reg [`BIT_WIDTH-1:0] c_uy__29; +reg [`BIT_WIDTH-1:0] c_uy__30; +reg [`BIT_WIDTH-1:0] c_uy__31; +reg [`BIT_WIDTH-1:0] c_uy__32; +reg [`BIT_WIDTH-1:0] c_uy__33; +reg [`BIT_WIDTH-1:0] c_uy__34; +reg [`BIT_WIDTH-1:0] c_uy__35; +reg [`BIT_WIDTH-1:0] c_uy__36; +reg [`BIT_WIDTH-1:0] c_uy__37; +reg [`BIT_WIDTH-1:0] c_uy__38; +reg [`BIT_WIDTH-1:0] c_uy__39; +reg [`BIT_WIDTH-1:0] c_uy__40; +reg [`BIT_WIDTH-1:0] c_uy__41; +reg [`BIT_WIDTH-1:0] c_uy__42; +reg [`BIT_WIDTH-1:0] c_uy__43; +reg [`BIT_WIDTH-1:0] c_uy__44; +reg [`BIT_WIDTH-1:0] c_uy__45; +reg [`BIT_WIDTH-1:0] c_uy__46; +reg [`BIT_WIDTH-1:0] c_uy__47; +reg [`BIT_WIDTH-1:0] c_uy__48; +reg [`BIT_WIDTH-1:0] c_uy__49; +reg [`BIT_WIDTH-1:0] c_uy__50; +reg [`BIT_WIDTH-1:0] c_uy__51; +reg [`BIT_WIDTH-1:0] c_uy__52; +reg [`BIT_WIDTH-1:0] c_uy__53; +reg [`BIT_WIDTH-1:0] c_uy__54; +reg [`BIT_WIDTH-1:0] c_uy__55; +reg [`BIT_WIDTH-1:0] c_uy__56; +reg [`BIT_WIDTH-1:0] c_uy__57; +reg [`BIT_WIDTH-1:0] c_uy__58; +reg [`BIT_WIDTH-1:0] c_uy__59; +//reg [`BIT_WIDTH-1:0] c_uz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_uz__0; +reg [`BIT_WIDTH-1:0] c_uz__1; +reg [`BIT_WIDTH-1:0] c_uz__2; +reg [`BIT_WIDTH-1:0] c_uz__3; +reg [`BIT_WIDTH-1:0] c_uz__4; +reg [`BIT_WIDTH-1:0] c_uz__5; +reg [`BIT_WIDTH-1:0] c_uz__6; +reg [`BIT_WIDTH-1:0] c_uz__7; +reg [`BIT_WIDTH-1:0] c_uz__8; +reg [`BIT_WIDTH-1:0] c_uz__9; +reg [`BIT_WIDTH-1:0] c_uz__10; +reg [`BIT_WIDTH-1:0] c_uz__11; +reg [`BIT_WIDTH-1:0] c_uz__12; +reg [`BIT_WIDTH-1:0] c_uz__13; +reg [`BIT_WIDTH-1:0] c_uz__14; +reg [`BIT_WIDTH-1:0] c_uz__15; +reg [`BIT_WIDTH-1:0] c_uz__16; +reg [`BIT_WIDTH-1:0] c_uz__17; +reg [`BIT_WIDTH-1:0] c_uz__18; +reg [`BIT_WIDTH-1:0] c_uz__19; +reg [`BIT_WIDTH-1:0] c_uz__20; +reg [`BIT_WIDTH-1:0] c_uz__21; +reg [`BIT_WIDTH-1:0] c_uz__22; +reg [`BIT_WIDTH-1:0] c_uz__23; +reg [`BIT_WIDTH-1:0] c_uz__24; +reg [`BIT_WIDTH-1:0] c_uz__25; +reg [`BIT_WIDTH-1:0] c_uz__26; +reg [`BIT_WIDTH-1:0] c_uz__27; +reg [`BIT_WIDTH-1:0] c_uz__28; +reg [`BIT_WIDTH-1:0] c_uz__29; +reg [`BIT_WIDTH-1:0] c_uz__30; +reg [`BIT_WIDTH-1:0] c_uz__31; +reg [`BIT_WIDTH-1:0] c_uz__32; +reg [`BIT_WIDTH-1:0] c_uz__33; +reg [`BIT_WIDTH-1:0] c_uz__34; +reg [`BIT_WIDTH-1:0] c_uz__35; +reg [`BIT_WIDTH-1:0] c_uz__36; +reg [`BIT_WIDTH-1:0] c_uz__37; +reg [`BIT_WIDTH-1:0] c_uz__38; +reg [`BIT_WIDTH-1:0] c_uz__39; +reg [`BIT_WIDTH-1:0] c_uz__40; +reg [`BIT_WIDTH-1:0] c_uz__41; +reg [`BIT_WIDTH-1:0] c_uz__42; +reg [`BIT_WIDTH-1:0] c_uz__43; +reg [`BIT_WIDTH-1:0] c_uz__44; +reg [`BIT_WIDTH-1:0] c_uz__45; +reg [`BIT_WIDTH-1:0] c_uz__46; +reg [`BIT_WIDTH-1:0] c_uz__47; +reg [`BIT_WIDTH-1:0] c_uz__48; +reg [`BIT_WIDTH-1:0] c_uz__49; +reg [`BIT_WIDTH-1:0] c_uz__50; +reg [`BIT_WIDTH-1:0] c_uz__51; +reg [`BIT_WIDTH-1:0] c_uz__52; +reg [`BIT_WIDTH-1:0] c_uz__53; +reg [`BIT_WIDTH-1:0] c_uz__54; +reg [`BIT_WIDTH-1:0] c_uz__55; +reg [`BIT_WIDTH-1:0] c_uz__56; +reg [`BIT_WIDTH-1:0] c_uz__57; +reg [`BIT_WIDTH-1:0] c_uz__58; +reg [`BIT_WIDTH-1:0] c_uz__59; +//reg [`BIT_WIDTH-1:0] c_sz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sz__0; +reg [`BIT_WIDTH-1:0] c_sz__1; +reg [`BIT_WIDTH-1:0] c_sz__2; +reg [`BIT_WIDTH-1:0] c_sz__3; +reg [`BIT_WIDTH-1:0] c_sz__4; +reg [`BIT_WIDTH-1:0] c_sz__5; +reg [`BIT_WIDTH-1:0] c_sz__6; +reg [`BIT_WIDTH-1:0] c_sz__7; +reg [`BIT_WIDTH-1:0] c_sz__8; +reg [`BIT_WIDTH-1:0] c_sz__9; +reg [`BIT_WIDTH-1:0] c_sz__10; +reg [`BIT_WIDTH-1:0] c_sz__11; +reg [`BIT_WIDTH-1:0] c_sz__12; +reg [`BIT_WIDTH-1:0] c_sz__13; +reg [`BIT_WIDTH-1:0] c_sz__14; +reg [`BIT_WIDTH-1:0] c_sz__15; +reg [`BIT_WIDTH-1:0] c_sz__16; +reg [`BIT_WIDTH-1:0] c_sz__17; +reg [`BIT_WIDTH-1:0] c_sz__18; +reg [`BIT_WIDTH-1:0] c_sz__19; +reg [`BIT_WIDTH-1:0] c_sz__20; +reg [`BIT_WIDTH-1:0] c_sz__21; +reg [`BIT_WIDTH-1:0] c_sz__22; +reg [`BIT_WIDTH-1:0] c_sz__23; +reg [`BIT_WIDTH-1:0] c_sz__24; +reg [`BIT_WIDTH-1:0] c_sz__25; +reg [`BIT_WIDTH-1:0] c_sz__26; +reg [`BIT_WIDTH-1:0] c_sz__27; +reg [`BIT_WIDTH-1:0] c_sz__28; +reg [`BIT_WIDTH-1:0] c_sz__29; +reg [`BIT_WIDTH-1:0] c_sz__30; +reg [`BIT_WIDTH-1:0] c_sz__31; +reg [`BIT_WIDTH-1:0] c_sz__32; +reg [`BIT_WIDTH-1:0] c_sz__33; +reg [`BIT_WIDTH-1:0] c_sz__34; +reg [`BIT_WIDTH-1:0] c_sz__35; +reg [`BIT_WIDTH-1:0] c_sz__36; +reg [`BIT_WIDTH-1:0] c_sz__37; +reg [`BIT_WIDTH-1:0] c_sz__38; +reg [`BIT_WIDTH-1:0] c_sz__39; +reg [`BIT_WIDTH-1:0] c_sz__40; +reg [`BIT_WIDTH-1:0] c_sz__41; +reg [`BIT_WIDTH-1:0] c_sz__42; +reg [`BIT_WIDTH-1:0] c_sz__43; +reg [`BIT_WIDTH-1:0] c_sz__44; +reg [`BIT_WIDTH-1:0] c_sz__45; +reg [`BIT_WIDTH-1:0] c_sz__46; +reg [`BIT_WIDTH-1:0] c_sz__47; +reg [`BIT_WIDTH-1:0] c_sz__48; +reg [`BIT_WIDTH-1:0] c_sz__49; +reg [`BIT_WIDTH-1:0] c_sz__50; +reg [`BIT_WIDTH-1:0] c_sz__51; +reg [`BIT_WIDTH-1:0] c_sz__52; +reg [`BIT_WIDTH-1:0] c_sz__53; +reg [`BIT_WIDTH-1:0] c_sz__54; +reg [`BIT_WIDTH-1:0] c_sz__55; +reg [`BIT_WIDTH-1:0] c_sz__56; +reg [`BIT_WIDTH-1:0] c_sz__57; +reg [`BIT_WIDTH-1:0] c_sz__58; +reg [`BIT_WIDTH-1:0] c_sz__59; +//reg [`BIT_WIDTH-1:0] c_sr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sr__0; +reg [`BIT_WIDTH-1:0] c_sr__1; +reg [`BIT_WIDTH-1:0] c_sr__2; +reg [`BIT_WIDTH-1:0] c_sr__3; +reg [`BIT_WIDTH-1:0] c_sr__4; +reg [`BIT_WIDTH-1:0] c_sr__5; +reg [`BIT_WIDTH-1:0] c_sr__6; +reg [`BIT_WIDTH-1:0] c_sr__7; +reg [`BIT_WIDTH-1:0] c_sr__8; +reg [`BIT_WIDTH-1:0] c_sr__9; +reg [`BIT_WIDTH-1:0] c_sr__10; +reg [`BIT_WIDTH-1:0] c_sr__11; +reg [`BIT_WIDTH-1:0] c_sr__12; +reg [`BIT_WIDTH-1:0] c_sr__13; +reg [`BIT_WIDTH-1:0] c_sr__14; +reg [`BIT_WIDTH-1:0] c_sr__15; +reg [`BIT_WIDTH-1:0] c_sr__16; +reg [`BIT_WIDTH-1:0] c_sr__17; +reg [`BIT_WIDTH-1:0] c_sr__18; +reg [`BIT_WIDTH-1:0] c_sr__19; +reg [`BIT_WIDTH-1:0] c_sr__20; +reg [`BIT_WIDTH-1:0] c_sr__21; +reg [`BIT_WIDTH-1:0] c_sr__22; +reg [`BIT_WIDTH-1:0] c_sr__23; +reg [`BIT_WIDTH-1:0] c_sr__24; +reg [`BIT_WIDTH-1:0] c_sr__25; +reg [`BIT_WIDTH-1:0] c_sr__26; +reg [`BIT_WIDTH-1:0] c_sr__27; +reg [`BIT_WIDTH-1:0] c_sr__28; +reg [`BIT_WIDTH-1:0] c_sr__29; +reg [`BIT_WIDTH-1:0] c_sr__30; +reg [`BIT_WIDTH-1:0] c_sr__31; +reg [`BIT_WIDTH-1:0] c_sr__32; +reg [`BIT_WIDTH-1:0] c_sr__33; +reg [`BIT_WIDTH-1:0] c_sr__34; +reg [`BIT_WIDTH-1:0] c_sr__35; +reg [`BIT_WIDTH-1:0] c_sr__36; +reg [`BIT_WIDTH-1:0] c_sr__37; +reg [`BIT_WIDTH-1:0] c_sr__38; +reg [`BIT_WIDTH-1:0] c_sr__39; +reg [`BIT_WIDTH-1:0] c_sr__40; +reg [`BIT_WIDTH-1:0] c_sr__41; +reg [`BIT_WIDTH-1:0] c_sr__42; +reg [`BIT_WIDTH-1:0] c_sr__43; +reg [`BIT_WIDTH-1:0] c_sr__44; +reg [`BIT_WIDTH-1:0] c_sr__45; +reg [`BIT_WIDTH-1:0] c_sr__46; +reg [`BIT_WIDTH-1:0] c_sr__47; +reg [`BIT_WIDTH-1:0] c_sr__48; +reg [`BIT_WIDTH-1:0] c_sr__49; +reg [`BIT_WIDTH-1:0] c_sr__50; +reg [`BIT_WIDTH-1:0] c_sr__51; +reg [`BIT_WIDTH-1:0] c_sr__52; +reg [`BIT_WIDTH-1:0] c_sr__53; +reg [`BIT_WIDTH-1:0] c_sr__54; +reg [`BIT_WIDTH-1:0] c_sr__55; +reg [`BIT_WIDTH-1:0] c_sr__56; +reg [`BIT_WIDTH-1:0] c_sr__57; +reg [`BIT_WIDTH-1:0] c_sr__58; +reg [`BIT_WIDTH-1:0] c_sr__59; +//reg [`BIT_WIDTH-1:0] c_sleftz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sleftz__0; +reg [`BIT_WIDTH-1:0] c_sleftz__1; +reg [`BIT_WIDTH-1:0] c_sleftz__2; +reg [`BIT_WIDTH-1:0] c_sleftz__3; +reg [`BIT_WIDTH-1:0] c_sleftz__4; +reg [`BIT_WIDTH-1:0] c_sleftz__5; +reg [`BIT_WIDTH-1:0] c_sleftz__6; +reg [`BIT_WIDTH-1:0] c_sleftz__7; +reg [`BIT_WIDTH-1:0] c_sleftz__8; +reg [`BIT_WIDTH-1:0] c_sleftz__9; +reg [`BIT_WIDTH-1:0] c_sleftz__10; +reg [`BIT_WIDTH-1:0] c_sleftz__11; +reg [`BIT_WIDTH-1:0] c_sleftz__12; +reg [`BIT_WIDTH-1:0] c_sleftz__13; +reg [`BIT_WIDTH-1:0] c_sleftz__14; +reg [`BIT_WIDTH-1:0] c_sleftz__15; +reg [`BIT_WIDTH-1:0] c_sleftz__16; +reg [`BIT_WIDTH-1:0] c_sleftz__17; +reg [`BIT_WIDTH-1:0] c_sleftz__18; +reg [`BIT_WIDTH-1:0] c_sleftz__19; +reg [`BIT_WIDTH-1:0] c_sleftz__20; +reg [`BIT_WIDTH-1:0] c_sleftz__21; +reg [`BIT_WIDTH-1:0] c_sleftz__22; +reg [`BIT_WIDTH-1:0] c_sleftz__23; +reg [`BIT_WIDTH-1:0] c_sleftz__24; +reg [`BIT_WIDTH-1:0] c_sleftz__25; +reg [`BIT_WIDTH-1:0] c_sleftz__26; +reg [`BIT_WIDTH-1:0] c_sleftz__27; +reg [`BIT_WIDTH-1:0] c_sleftz__28; +reg [`BIT_WIDTH-1:0] c_sleftz__29; +reg [`BIT_WIDTH-1:0] c_sleftz__30; +reg [`BIT_WIDTH-1:0] c_sleftz__31; +reg [`BIT_WIDTH-1:0] c_sleftz__32; +reg [`BIT_WIDTH-1:0] c_sleftz__33; +reg [`BIT_WIDTH-1:0] c_sleftz__34; +reg [`BIT_WIDTH-1:0] c_sleftz__35; +reg [`BIT_WIDTH-1:0] c_sleftz__36; +reg [`BIT_WIDTH-1:0] c_sleftz__37; +reg [`BIT_WIDTH-1:0] c_sleftz__38; +reg [`BIT_WIDTH-1:0] c_sleftz__39; +reg [`BIT_WIDTH-1:0] c_sleftz__40; +reg [`BIT_WIDTH-1:0] c_sleftz__41; +reg [`BIT_WIDTH-1:0] c_sleftz__42; +reg [`BIT_WIDTH-1:0] c_sleftz__43; +reg [`BIT_WIDTH-1:0] c_sleftz__44; +reg [`BIT_WIDTH-1:0] c_sleftz__45; +reg [`BIT_WIDTH-1:0] c_sleftz__46; +reg [`BIT_WIDTH-1:0] c_sleftz__47; +reg [`BIT_WIDTH-1:0] c_sleftz__48; +reg [`BIT_WIDTH-1:0] c_sleftz__49; +reg [`BIT_WIDTH-1:0] c_sleftz__50; +reg [`BIT_WIDTH-1:0] c_sleftz__51; +reg [`BIT_WIDTH-1:0] c_sleftz__52; +reg [`BIT_WIDTH-1:0] c_sleftz__53; +reg [`BIT_WIDTH-1:0] c_sleftz__54; +reg [`BIT_WIDTH-1:0] c_sleftz__55; +reg [`BIT_WIDTH-1:0] c_sleftz__56; +reg [`BIT_WIDTH-1:0] c_sleftz__57; +reg [`BIT_WIDTH-1:0] c_sleftz__58; +reg [`BIT_WIDTH-1:0] c_sleftz__59; +//reg [`BIT_WIDTH-1:0] c_sleftr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sleftr__0; +reg [`BIT_WIDTH-1:0] c_sleftr__1; +reg [`BIT_WIDTH-1:0] c_sleftr__2; +reg [`BIT_WIDTH-1:0] c_sleftr__3; +reg [`BIT_WIDTH-1:0] c_sleftr__4; +reg [`BIT_WIDTH-1:0] c_sleftr__5; +reg [`BIT_WIDTH-1:0] c_sleftr__6; +reg [`BIT_WIDTH-1:0] c_sleftr__7; +reg [`BIT_WIDTH-1:0] c_sleftr__8; +reg [`BIT_WIDTH-1:0] c_sleftr__9; +reg [`BIT_WIDTH-1:0] c_sleftr__10; +reg [`BIT_WIDTH-1:0] c_sleftr__11; +reg [`BIT_WIDTH-1:0] c_sleftr__12; +reg [`BIT_WIDTH-1:0] c_sleftr__13; +reg [`BIT_WIDTH-1:0] c_sleftr__14; +reg [`BIT_WIDTH-1:0] c_sleftr__15; +reg [`BIT_WIDTH-1:0] c_sleftr__16; +reg [`BIT_WIDTH-1:0] c_sleftr__17; +reg [`BIT_WIDTH-1:0] c_sleftr__18; +reg [`BIT_WIDTH-1:0] c_sleftr__19; +reg [`BIT_WIDTH-1:0] c_sleftr__20; +reg [`BIT_WIDTH-1:0] c_sleftr__21; +reg [`BIT_WIDTH-1:0] c_sleftr__22; +reg [`BIT_WIDTH-1:0] c_sleftr__23; +reg [`BIT_WIDTH-1:0] c_sleftr__24; +reg [`BIT_WIDTH-1:0] c_sleftr__25; +reg [`BIT_WIDTH-1:0] c_sleftr__26; +reg [`BIT_WIDTH-1:0] c_sleftr__27; +reg [`BIT_WIDTH-1:0] c_sleftr__28; +reg [`BIT_WIDTH-1:0] c_sleftr__29; +reg [`BIT_WIDTH-1:0] c_sleftr__30; +reg [`BIT_WIDTH-1:0] c_sleftr__31; +reg [`BIT_WIDTH-1:0] c_sleftr__32; +reg [`BIT_WIDTH-1:0] c_sleftr__33; +reg [`BIT_WIDTH-1:0] c_sleftr__34; +reg [`BIT_WIDTH-1:0] c_sleftr__35; +reg [`BIT_WIDTH-1:0] c_sleftr__36; +reg [`BIT_WIDTH-1:0] c_sleftr__37; +reg [`BIT_WIDTH-1:0] c_sleftr__38; +reg [`BIT_WIDTH-1:0] c_sleftr__39; +reg [`BIT_WIDTH-1:0] c_sleftr__40; +reg [`BIT_WIDTH-1:0] c_sleftr__41; +reg [`BIT_WIDTH-1:0] c_sleftr__42; +reg [`BIT_WIDTH-1:0] c_sleftr__43; +reg [`BIT_WIDTH-1:0] c_sleftr__44; +reg [`BIT_WIDTH-1:0] c_sleftr__45; +reg [`BIT_WIDTH-1:0] c_sleftr__46; +reg [`BIT_WIDTH-1:0] c_sleftr__47; +reg [`BIT_WIDTH-1:0] c_sleftr__48; +reg [`BIT_WIDTH-1:0] c_sleftr__49; +reg [`BIT_WIDTH-1:0] c_sleftr__50; +reg [`BIT_WIDTH-1:0] c_sleftr__51; +reg [`BIT_WIDTH-1:0] c_sleftr__52; +reg [`BIT_WIDTH-1:0] c_sleftr__53; +reg [`BIT_WIDTH-1:0] c_sleftr__54; +reg [`BIT_WIDTH-1:0] c_sleftr__55; +reg [`BIT_WIDTH-1:0] c_sleftr__56; +reg [`BIT_WIDTH-1:0] c_sleftr__57; +reg [`BIT_WIDTH-1:0] c_sleftr__58; +reg [`BIT_WIDTH-1:0] c_sleftr__59; +//reg [`BIT_WIDTH-1:0] c_weight [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_weight__0; +reg [`BIT_WIDTH-1:0] c_weight__1; +reg [`BIT_WIDTH-1:0] c_weight__2; +reg [`BIT_WIDTH-1:0] c_weight__3; +reg [`BIT_WIDTH-1:0] c_weight__4; +reg [`BIT_WIDTH-1:0] c_weight__5; +reg [`BIT_WIDTH-1:0] c_weight__6; +reg [`BIT_WIDTH-1:0] c_weight__7; +reg [`BIT_WIDTH-1:0] c_weight__8; +reg [`BIT_WIDTH-1:0] c_weight__9; +reg [`BIT_WIDTH-1:0] c_weight__10; +reg [`BIT_WIDTH-1:0] c_weight__11; +reg [`BIT_WIDTH-1:0] c_weight__12; +reg [`BIT_WIDTH-1:0] c_weight__13; +reg [`BIT_WIDTH-1:0] c_weight__14; +reg [`BIT_WIDTH-1:0] c_weight__15; +reg [`BIT_WIDTH-1:0] c_weight__16; +reg [`BIT_WIDTH-1:0] c_weight__17; +reg [`BIT_WIDTH-1:0] c_weight__18; +reg [`BIT_WIDTH-1:0] c_weight__19; +reg [`BIT_WIDTH-1:0] c_weight__20; +reg [`BIT_WIDTH-1:0] c_weight__21; +reg [`BIT_WIDTH-1:0] c_weight__22; +reg [`BIT_WIDTH-1:0] c_weight__23; +reg [`BIT_WIDTH-1:0] c_weight__24; +reg [`BIT_WIDTH-1:0] c_weight__25; +reg [`BIT_WIDTH-1:0] c_weight__26; +reg [`BIT_WIDTH-1:0] c_weight__27; +reg [`BIT_WIDTH-1:0] c_weight__28; +reg [`BIT_WIDTH-1:0] c_weight__29; +reg [`BIT_WIDTH-1:0] c_weight__30; +reg [`BIT_WIDTH-1:0] c_weight__31; +reg [`BIT_WIDTH-1:0] c_weight__32; +reg [`BIT_WIDTH-1:0] c_weight__33; +reg [`BIT_WIDTH-1:0] c_weight__34; +reg [`BIT_WIDTH-1:0] c_weight__35; +reg [`BIT_WIDTH-1:0] c_weight__36; +reg [`BIT_WIDTH-1:0] c_weight__37; +reg [`BIT_WIDTH-1:0] c_weight__38; +reg [`BIT_WIDTH-1:0] c_weight__39; +reg [`BIT_WIDTH-1:0] c_weight__40; +reg [`BIT_WIDTH-1:0] c_weight__41; +reg [`BIT_WIDTH-1:0] c_weight__42; +reg [`BIT_WIDTH-1:0] c_weight__43; +reg [`BIT_WIDTH-1:0] c_weight__44; +reg [`BIT_WIDTH-1:0] c_weight__45; +reg [`BIT_WIDTH-1:0] c_weight__46; +reg [`BIT_WIDTH-1:0] c_weight__47; +reg [`BIT_WIDTH-1:0] c_weight__48; +reg [`BIT_WIDTH-1:0] c_weight__49; +reg [`BIT_WIDTH-1:0] c_weight__50; +reg [`BIT_WIDTH-1:0] c_weight__51; +reg [`BIT_WIDTH-1:0] c_weight__52; +reg [`BIT_WIDTH-1:0] c_weight__53; +reg [`BIT_WIDTH-1:0] c_weight__54; +reg [`BIT_WIDTH-1:0] c_weight__55; +reg [`BIT_WIDTH-1:0] c_weight__56; +reg [`BIT_WIDTH-1:0] c_weight__57; +reg [`BIT_WIDTH-1:0] c_weight__58; +reg [`BIT_WIDTH-1:0] c_weight__59; + +//reg [`LAYER_WIDTH-1:0] c_layer [TOTAL_LATENCY - 1:0]; + +reg [`LAYER_WIDTH-1:0] c_layer__0; +reg [`LAYER_WIDTH-1:0] c_layer__1; +reg [`LAYER_WIDTH-1:0] c_layer__2; +reg [`LAYER_WIDTH-1:0] c_layer__3; +reg [`LAYER_WIDTH-1:0] c_layer__4; +reg [`LAYER_WIDTH-1:0] c_layer__5; +reg [`LAYER_WIDTH-1:0] c_layer__6; +reg [`LAYER_WIDTH-1:0] c_layer__7; +reg [`LAYER_WIDTH-1:0] c_layer__8; +reg [`LAYER_WIDTH-1:0] c_layer__9; +reg [`LAYER_WIDTH-1:0] c_layer__10; +reg [`LAYER_WIDTH-1:0] c_layer__11; +reg [`LAYER_WIDTH-1:0] c_layer__12; +reg [`LAYER_WIDTH-1:0] c_layer__13; +reg [`LAYER_WIDTH-1:0] c_layer__14; +reg [`LAYER_WIDTH-1:0] c_layer__15; +reg [`LAYER_WIDTH-1:0] c_layer__16; +reg [`LAYER_WIDTH-1:0] c_layer__17; +reg [`LAYER_WIDTH-1:0] c_layer__18; +reg [`LAYER_WIDTH-1:0] c_layer__19; +reg [`LAYER_WIDTH-1:0] c_layer__20; +reg [`LAYER_WIDTH-1:0] c_layer__21; +reg [`LAYER_WIDTH-1:0] c_layer__22; +reg [`LAYER_WIDTH-1:0] c_layer__23; +reg [`LAYER_WIDTH-1:0] c_layer__24; +reg [`LAYER_WIDTH-1:0] c_layer__25; +reg [`LAYER_WIDTH-1:0] c_layer__26; +reg [`LAYER_WIDTH-1:0] c_layer__27; +reg [`LAYER_WIDTH-1:0] c_layer__28; +reg [`LAYER_WIDTH-1:0] c_layer__29; +reg [`LAYER_WIDTH-1:0] c_layer__30; +reg [`LAYER_WIDTH-1:0] c_layer__31; +reg [`LAYER_WIDTH-1:0] c_layer__32; +reg [`LAYER_WIDTH-1:0] c_layer__33; +reg [`LAYER_WIDTH-1:0] c_layer__34; +reg [`LAYER_WIDTH-1:0] c_layer__35; +reg [`LAYER_WIDTH-1:0] c_layer__36; +reg [`LAYER_WIDTH-1:0] c_layer__37; +reg [`LAYER_WIDTH-1:0] c_layer__38; +reg [`LAYER_WIDTH-1:0] c_layer__39; +reg [`LAYER_WIDTH-1:0] c_layer__40; +reg [`LAYER_WIDTH-1:0] c_layer__41; +reg [`LAYER_WIDTH-1:0] c_layer__42; +reg [`LAYER_WIDTH-1:0] c_layer__43; +reg [`LAYER_WIDTH-1:0] c_layer__44; +reg [`LAYER_WIDTH-1:0] c_layer__45; +reg [`LAYER_WIDTH-1:0] c_layer__46; +reg [`LAYER_WIDTH-1:0] c_layer__47; +reg [`LAYER_WIDTH-1:0] c_layer__48; +reg [`LAYER_WIDTH-1:0] c_layer__49; +reg [`LAYER_WIDTH-1:0] c_layer__50; +reg [`LAYER_WIDTH-1:0] c_layer__51; +reg [`LAYER_WIDTH-1:0] c_layer__52; +reg [`LAYER_WIDTH-1:0] c_layer__53; +reg [`LAYER_WIDTH-1:0] c_layer__54; +reg [`LAYER_WIDTH-1:0] c_layer__55; +reg [`LAYER_WIDTH-1:0] c_layer__56; +reg [`LAYER_WIDTH-1:0] c_layer__57; +reg [`LAYER_WIDTH-1:0] c_layer__58; +reg [`LAYER_WIDTH-1:0] c_layer__59; + + + +//reg c_dead [TOTAL_LATENCY - 1:0]; + +reg c_dead__0; +reg c_dead__1; +reg c_dead__2; +reg c_dead__3; +reg c_dead__4; +reg c_dead__5; +reg c_dead__6; +reg c_dead__7; +reg c_dead__8; +reg c_dead__9; +reg c_dead__10; +reg c_dead__11; +reg c_dead__12; +reg c_dead__13; +reg c_dead__14; +reg c_dead__15; +reg c_dead__16; +reg c_dead__17; +reg c_dead__18; +reg c_dead__19; +reg c_dead__20; +reg c_dead__21; +reg c_dead__22; +reg c_dead__23; +reg c_dead__24; +reg c_dead__25; +reg c_dead__26; +reg c_dead__27; +reg c_dead__28; +reg c_dead__29; +reg c_dead__30; +reg c_dead__31; +reg c_dead__32; +reg c_dead__33; +reg c_dead__34; +reg c_dead__35; +reg c_dead__36; +reg c_dead__37; +reg c_dead__38; +reg c_dead__39; +reg c_dead__40; +reg c_dead__41; +reg c_dead__42; +reg c_dead__43; +reg c_dead__44; +reg c_dead__45; +reg c_dead__46; +reg c_dead__47; +reg c_dead__48; +reg c_dead__49; +reg c_dead__50; +reg c_dead__51; +reg c_dead__52; +reg c_dead__53; +reg c_dead__54; +reg c_dead__55; +reg c_dead__56; +reg c_dead__57; +reg c_dead__58; +reg c_dead__59; + + +//reg c_hit [TOTAL_LATENCY - 1:0]; + +reg c_hit__0; +reg c_hit__1; +reg c_hit__2; +reg c_hit__3; +reg c_hit__4; +reg c_hit__5; +reg c_hit__6; +reg c_hit__7; +reg c_hit__8; +reg c_hit__9; +reg c_hit__10; +reg c_hit__11; +reg c_hit__12; +reg c_hit__13; +reg c_hit__14; +reg c_hit__15; +reg c_hit__16; +reg c_hit__17; +reg c_hit__18; +reg c_hit__19; +reg c_hit__20; +reg c_hit__21; +reg c_hit__22; +reg c_hit__23; +reg c_hit__24; +reg c_hit__25; +reg c_hit__26; +reg c_hit__27; +reg c_hit__28; +reg c_hit__29; +reg c_hit__30; +reg c_hit__31; +reg c_hit__32; +reg c_hit__33; +reg c_hit__34; +reg c_hit__35; +reg c_hit__36; +reg c_hit__37; +reg c_hit__38; +reg c_hit__39; +reg c_hit__40; +reg c_hit__41; +reg c_hit__42; +reg c_hit__43; +reg c_hit__44; +reg c_hit__45; +reg c_hit__46; +reg c_hit__47; +reg c_hit__48; +reg c_hit__49; +reg c_hit__50; +reg c_hit__51; +reg c_hit__52; +reg c_hit__53; +reg c_hit__54; +reg c_hit__55; +reg c_hit__56; +reg c_hit__57; +reg c_hit__58; +reg c_hit__59; + +//reg [`BIT_WIDTH-1:0] c_diff[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_diff__0; +reg [`BIT_WIDTH-1:0] c_diff__1; +reg [`BIT_WIDTH-1:0] c_diff__2; +reg [`BIT_WIDTH-1:0] c_diff__3; +reg [`BIT_WIDTH-1:0] c_diff__4; +reg [`BIT_WIDTH-1:0] c_diff__5; +reg [`BIT_WIDTH-1:0] c_diff__6; +reg [`BIT_WIDTH-1:0] c_diff__7; +reg [`BIT_WIDTH-1:0] c_diff__8; +reg [`BIT_WIDTH-1:0] c_diff__9; +reg [`BIT_WIDTH-1:0] c_diff__10; +reg [`BIT_WIDTH-1:0] c_diff__11; +reg [`BIT_WIDTH-1:0] c_diff__12; +reg [`BIT_WIDTH-1:0] c_diff__13; +reg [`BIT_WIDTH-1:0] c_diff__14; +reg [`BIT_WIDTH-1:0] c_diff__15; +reg [`BIT_WIDTH-1:0] c_diff__16; +reg [`BIT_WIDTH-1:0] c_diff__17; +reg [`BIT_WIDTH-1:0] c_diff__18; +reg [`BIT_WIDTH-1:0] c_diff__19; +reg [`BIT_WIDTH-1:0] c_diff__20; +reg [`BIT_WIDTH-1:0] c_diff__21; +reg [`BIT_WIDTH-1:0] c_diff__22; +reg [`BIT_WIDTH-1:0] c_diff__23; +reg [`BIT_WIDTH-1:0] c_diff__24; +reg [`BIT_WIDTH-1:0] c_diff__25; +reg [`BIT_WIDTH-1:0] c_diff__26; +reg [`BIT_WIDTH-1:0] c_diff__27; +reg [`BIT_WIDTH-1:0] c_diff__28; +reg [`BIT_WIDTH-1:0] c_diff__29; +reg [`BIT_WIDTH-1:0] c_diff__30; +reg [`BIT_WIDTH-1:0] c_diff__31; +reg [`BIT_WIDTH-1:0] c_diff__32; +reg [`BIT_WIDTH-1:0] c_diff__33; +reg [`BIT_WIDTH-1:0] c_diff__34; +reg [`BIT_WIDTH-1:0] c_diff__35; +reg [`BIT_WIDTH-1:0] c_diff__36; +reg [`BIT_WIDTH-1:0] c_diff__37; +reg [`BIT_WIDTH-1:0] c_diff__38; +reg [`BIT_WIDTH-1:0] c_diff__39; +reg [`BIT_WIDTH-1:0] c_diff__40; +reg [`BIT_WIDTH-1:0] c_diff__41; +reg [`BIT_WIDTH-1:0] c_diff__42; +reg [`BIT_WIDTH-1:0] c_diff__43; +reg [`BIT_WIDTH-1:0] c_diff__44; +reg [`BIT_WIDTH-1:0] c_diff__45; +reg [`BIT_WIDTH-1:0] c_diff__46; +reg [`BIT_WIDTH-1:0] c_diff__47; +reg [`BIT_WIDTH-1:0] c_diff__48; +reg [`BIT_WIDTH-1:0] c_diff__49; +reg [`BIT_WIDTH-1:0] c_diff__50; +reg [`BIT_WIDTH-1:0] c_diff__51; +reg [`BIT_WIDTH-1:0] c_diff__52; +reg [`BIT_WIDTH-1:0] c_diff__53; +reg [`BIT_WIDTH-1:0] c_diff__54; +reg [`BIT_WIDTH-1:0] c_diff__55; +reg [`BIT_WIDTH-1:0] c_diff__56; +reg [`BIT_WIDTH-1:0] c_diff__57; +reg [`BIT_WIDTH-1:0] c_diff__58; +reg [`BIT_WIDTH-1:0] c_diff__59; + + +//reg [`BIT_WIDTH-1:0] c_dl_b[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_dl_b__0; +reg [`BIT_WIDTH-1:0] c_dl_b__1; +reg [`BIT_WIDTH-1:0] c_dl_b__2; +reg [`BIT_WIDTH-1:0] c_dl_b__3; +reg [`BIT_WIDTH-1:0] c_dl_b__4; +reg [`BIT_WIDTH-1:0] c_dl_b__5; +reg [`BIT_WIDTH-1:0] c_dl_b__6; +reg [`BIT_WIDTH-1:0] c_dl_b__7; +reg [`BIT_WIDTH-1:0] c_dl_b__8; +reg [`BIT_WIDTH-1:0] c_dl_b__9; +reg [`BIT_WIDTH-1:0] c_dl_b__10; +reg [`BIT_WIDTH-1:0] c_dl_b__11; +reg [`BIT_WIDTH-1:0] c_dl_b__12; +reg [`BIT_WIDTH-1:0] c_dl_b__13; +reg [`BIT_WIDTH-1:0] c_dl_b__14; +reg [`BIT_WIDTH-1:0] c_dl_b__15; +reg [`BIT_WIDTH-1:0] c_dl_b__16; +reg [`BIT_WIDTH-1:0] c_dl_b__17; +reg [`BIT_WIDTH-1:0] c_dl_b__18; +reg [`BIT_WIDTH-1:0] c_dl_b__19; +reg [`BIT_WIDTH-1:0] c_dl_b__20; +reg [`BIT_WIDTH-1:0] c_dl_b__21; +reg [`BIT_WIDTH-1:0] c_dl_b__22; +reg [`BIT_WIDTH-1:0] c_dl_b__23; +reg [`BIT_WIDTH-1:0] c_dl_b__24; +reg [`BIT_WIDTH-1:0] c_dl_b__25; +reg [`BIT_WIDTH-1:0] c_dl_b__26; +reg [`BIT_WIDTH-1:0] c_dl_b__27; +reg [`BIT_WIDTH-1:0] c_dl_b__28; +reg [`BIT_WIDTH-1:0] c_dl_b__29; +reg [`BIT_WIDTH-1:0] c_dl_b__30; +reg [`BIT_WIDTH-1:0] c_dl_b__31; +reg [`BIT_WIDTH-1:0] c_dl_b__32; +reg [`BIT_WIDTH-1:0] c_dl_b__33; +reg [`BIT_WIDTH-1:0] c_dl_b__34; +reg [`BIT_WIDTH-1:0] c_dl_b__35; +reg [`BIT_WIDTH-1:0] c_dl_b__36; +reg [`BIT_WIDTH-1:0] c_dl_b__37; +reg [`BIT_WIDTH-1:0] c_dl_b__38; +reg [`BIT_WIDTH-1:0] c_dl_b__39; +reg [`BIT_WIDTH-1:0] c_dl_b__40; +reg [`BIT_WIDTH-1:0] c_dl_b__41; +reg [`BIT_WIDTH-1:0] c_dl_b__42; +reg [`BIT_WIDTH-1:0] c_dl_b__43; +reg [`BIT_WIDTH-1:0] c_dl_b__44; +reg [`BIT_WIDTH-1:0] c_dl_b__45; +reg [`BIT_WIDTH-1:0] c_dl_b__46; +reg [`BIT_WIDTH-1:0] c_dl_b__47; +reg [`BIT_WIDTH-1:0] c_dl_b__48; +reg [`BIT_WIDTH-1:0] c_dl_b__49; +reg [`BIT_WIDTH-1:0] c_dl_b__50; +reg [`BIT_WIDTH-1:0] c_dl_b__51; +reg [`BIT_WIDTH-1:0] c_dl_b__52; +reg [`BIT_WIDTH-1:0] c_dl_b__53; +reg [`BIT_WIDTH-1:0] c_dl_b__54; +reg [`BIT_WIDTH-1:0] c_dl_b__55; +reg [`BIT_WIDTH-1:0] c_dl_b__56; +reg [`BIT_WIDTH-1:0] c_dl_b__57; +reg [`BIT_WIDTH-1:0] c_dl_b__58; +reg [`BIT_WIDTH-1:0] c_dl_b__59; + + +//reg [2*`BIT_WIDTH-1:0] c_numer[TOTAL_LATENCY - 1:0]; + + +reg [2*`BIT_WIDTH-1:0] c_numer__0; +reg [2*`BIT_WIDTH-1:0] c_numer__1; +reg [2*`BIT_WIDTH-1:0] c_numer__2; +reg [2*`BIT_WIDTH-1:0] c_numer__3; +reg [2*`BIT_WIDTH-1:0] c_numer__4; +reg [2*`BIT_WIDTH-1:0] c_numer__5; +reg [2*`BIT_WIDTH-1:0] c_numer__6; +reg [2*`BIT_WIDTH-1:0] c_numer__7; +reg [2*`BIT_WIDTH-1:0] c_numer__8; +reg [2*`BIT_WIDTH-1:0] c_numer__9; +reg [2*`BIT_WIDTH-1:0] c_numer__10; +reg [2*`BIT_WIDTH-1:0] c_numer__11; +reg [2*`BIT_WIDTH-1:0] c_numer__12; +reg [2*`BIT_WIDTH-1:0] c_numer__13; +reg [2*`BIT_WIDTH-1:0] c_numer__14; +reg [2*`BIT_WIDTH-1:0] c_numer__15; +reg [2*`BIT_WIDTH-1:0] c_numer__16; +reg [2*`BIT_WIDTH-1:0] c_numer__17; +reg [2*`BIT_WIDTH-1:0] c_numer__18; +reg [2*`BIT_WIDTH-1:0] c_numer__19; +reg [2*`BIT_WIDTH-1:0] c_numer__20; +reg [2*`BIT_WIDTH-1:0] c_numer__21; +reg [2*`BIT_WIDTH-1:0] c_numer__22; +reg [2*`BIT_WIDTH-1:0] c_numer__23; +reg [2*`BIT_WIDTH-1:0] c_numer__24; +reg [2*`BIT_WIDTH-1:0] c_numer__25; +reg [2*`BIT_WIDTH-1:0] c_numer__26; +reg [2*`BIT_WIDTH-1:0] c_numer__27; +reg [2*`BIT_WIDTH-1:0] c_numer__28; +reg [2*`BIT_WIDTH-1:0] c_numer__29; +reg [2*`BIT_WIDTH-1:0] c_numer__30; +reg [2*`BIT_WIDTH-1:0] c_numer__31; +reg [2*`BIT_WIDTH-1:0] c_numer__32; +reg [2*`BIT_WIDTH-1:0] c_numer__33; +reg [2*`BIT_WIDTH-1:0] c_numer__34; +reg [2*`BIT_WIDTH-1:0] c_numer__35; +reg [2*`BIT_WIDTH-1:0] c_numer__36; +reg [2*`BIT_WIDTH-1:0] c_numer__37; +reg [2*`BIT_WIDTH-1:0] c_numer__38; +reg [2*`BIT_WIDTH-1:0] c_numer__39; +reg [2*`BIT_WIDTH-1:0] c_numer__40; +reg [2*`BIT_WIDTH-1:0] c_numer__41; +reg [2*`BIT_WIDTH-1:0] c_numer__42; +reg [2*`BIT_WIDTH-1:0] c_numer__43; +reg [2*`BIT_WIDTH-1:0] c_numer__44; +reg [2*`BIT_WIDTH-1:0] c_numer__45; +reg [2*`BIT_WIDTH-1:0] c_numer__46; +reg [2*`BIT_WIDTH-1:0] c_numer__47; +reg [2*`BIT_WIDTH-1:0] c_numer__48; +reg [2*`BIT_WIDTH-1:0] c_numer__49; +reg [2*`BIT_WIDTH-1:0] c_numer__50; +reg [2*`BIT_WIDTH-1:0] c_numer__51; +reg [2*`BIT_WIDTH-1:0] c_numer__52; +reg [2*`BIT_WIDTH-1:0] c_numer__53; +reg [2*`BIT_WIDTH-1:0] c_numer__54; +reg [2*`BIT_WIDTH-1:0] c_numer__55; +reg [2*`BIT_WIDTH-1:0] c_numer__56; +reg [2*`BIT_WIDTH-1:0] c_numer__57; +reg [2*`BIT_WIDTH-1:0] c_numer__58; +reg [2*`BIT_WIDTH-1:0] c_numer__59; + +//reg [`BIT_WIDTH-1:0] c_z1[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z1__0; +reg [`BIT_WIDTH-1:0] c_z1__1; +reg [`BIT_WIDTH-1:0] c_z1__2; +reg [`BIT_WIDTH-1:0] c_z1__3; +reg [`BIT_WIDTH-1:0] c_z1__4; +reg [`BIT_WIDTH-1:0] c_z1__5; +reg [`BIT_WIDTH-1:0] c_z1__6; +reg [`BIT_WIDTH-1:0] c_z1__7; +reg [`BIT_WIDTH-1:0] c_z1__8; +reg [`BIT_WIDTH-1:0] c_z1__9; +reg [`BIT_WIDTH-1:0] c_z1__10; +reg [`BIT_WIDTH-1:0] c_z1__11; +reg [`BIT_WIDTH-1:0] c_z1__12; +reg [`BIT_WIDTH-1:0] c_z1__13; +reg [`BIT_WIDTH-1:0] c_z1__14; +reg [`BIT_WIDTH-1:0] c_z1__15; +reg [`BIT_WIDTH-1:0] c_z1__16; +reg [`BIT_WIDTH-1:0] c_z1__17; +reg [`BIT_WIDTH-1:0] c_z1__18; +reg [`BIT_WIDTH-1:0] c_z1__19; +reg [`BIT_WIDTH-1:0] c_z1__20; +reg [`BIT_WIDTH-1:0] c_z1__21; +reg [`BIT_WIDTH-1:0] c_z1__22; +reg [`BIT_WIDTH-1:0] c_z1__23; +reg [`BIT_WIDTH-1:0] c_z1__24; +reg [`BIT_WIDTH-1:0] c_z1__25; +reg [`BIT_WIDTH-1:0] c_z1__26; +reg [`BIT_WIDTH-1:0] c_z1__27; +reg [`BIT_WIDTH-1:0] c_z1__28; +reg [`BIT_WIDTH-1:0] c_z1__29; +reg [`BIT_WIDTH-1:0] c_z1__30; +reg [`BIT_WIDTH-1:0] c_z1__31; +reg [`BIT_WIDTH-1:0] c_z1__32; +reg [`BIT_WIDTH-1:0] c_z1__33; +reg [`BIT_WIDTH-1:0] c_z1__34; +reg [`BIT_WIDTH-1:0] c_z1__35; +reg [`BIT_WIDTH-1:0] c_z1__36; +reg [`BIT_WIDTH-1:0] c_z1__37; +reg [`BIT_WIDTH-1:0] c_z1__38; +reg [`BIT_WIDTH-1:0] c_z1__39; +reg [`BIT_WIDTH-1:0] c_z1__40; +reg [`BIT_WIDTH-1:0] c_z1__41; +reg [`BIT_WIDTH-1:0] c_z1__42; +reg [`BIT_WIDTH-1:0] c_z1__43; +reg [`BIT_WIDTH-1:0] c_z1__44; +reg [`BIT_WIDTH-1:0] c_z1__45; +reg [`BIT_WIDTH-1:0] c_z1__46; +reg [`BIT_WIDTH-1:0] c_z1__47; +reg [`BIT_WIDTH-1:0] c_z1__48; +reg [`BIT_WIDTH-1:0] c_z1__49; +reg [`BIT_WIDTH-1:0] c_z1__50; +reg [`BIT_WIDTH-1:0] c_z1__51; +reg [`BIT_WIDTH-1:0] c_z1__52; +reg [`BIT_WIDTH-1:0] c_z1__53; +reg [`BIT_WIDTH-1:0] c_z1__54; +reg [`BIT_WIDTH-1:0] c_z1__55; +reg [`BIT_WIDTH-1:0] c_z1__56; +reg [`BIT_WIDTH-1:0] c_z1__57; +reg [`BIT_WIDTH-1:0] c_z1__58; +reg [`BIT_WIDTH-1:0] c_z1__59; + +//reg [`BIT_WIDTH-1:0] c_z0[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z0__0; +reg [`BIT_WIDTH-1:0] c_z0__1; +reg [`BIT_WIDTH-1:0] c_z0__2; +reg [`BIT_WIDTH-1:0] c_z0__3; +reg [`BIT_WIDTH-1:0] c_z0__4; +reg [`BIT_WIDTH-1:0] c_z0__5; +reg [`BIT_WIDTH-1:0] c_z0__6; +reg [`BIT_WIDTH-1:0] c_z0__7; +reg [`BIT_WIDTH-1:0] c_z0__8; +reg [`BIT_WIDTH-1:0] c_z0__9; +reg [`BIT_WIDTH-1:0] c_z0__10; +reg [`BIT_WIDTH-1:0] c_z0__11; +reg [`BIT_WIDTH-1:0] c_z0__12; +reg [`BIT_WIDTH-1:0] c_z0__13; +reg [`BIT_WIDTH-1:0] c_z0__14; +reg [`BIT_WIDTH-1:0] c_z0__15; +reg [`BIT_WIDTH-1:0] c_z0__16; +reg [`BIT_WIDTH-1:0] c_z0__17; +reg [`BIT_WIDTH-1:0] c_z0__18; +reg [`BIT_WIDTH-1:0] c_z0__19; +reg [`BIT_WIDTH-1:0] c_z0__20; +reg [`BIT_WIDTH-1:0] c_z0__21; +reg [`BIT_WIDTH-1:0] c_z0__22; +reg [`BIT_WIDTH-1:0] c_z0__23; +reg [`BIT_WIDTH-1:0] c_z0__24; +reg [`BIT_WIDTH-1:0] c_z0__25; +reg [`BIT_WIDTH-1:0] c_z0__26; +reg [`BIT_WIDTH-1:0] c_z0__27; +reg [`BIT_WIDTH-1:0] c_z0__28; +reg [`BIT_WIDTH-1:0] c_z0__29; +reg [`BIT_WIDTH-1:0] c_z0__30; +reg [`BIT_WIDTH-1:0] c_z0__31; +reg [`BIT_WIDTH-1:0] c_z0__32; +reg [`BIT_WIDTH-1:0] c_z0__33; +reg [`BIT_WIDTH-1:0] c_z0__34; +reg [`BIT_WIDTH-1:0] c_z0__35; +reg [`BIT_WIDTH-1:0] c_z0__36; +reg [`BIT_WIDTH-1:0] c_z0__37; +reg [`BIT_WIDTH-1:0] c_z0__38; +reg [`BIT_WIDTH-1:0] c_z0__39; +reg [`BIT_WIDTH-1:0] c_z0__40; +reg [`BIT_WIDTH-1:0] c_z0__41; +reg [`BIT_WIDTH-1:0] c_z0__42; +reg [`BIT_WIDTH-1:0] c_z0__43; +reg [`BIT_WIDTH-1:0] c_z0__44; +reg [`BIT_WIDTH-1:0] c_z0__45; +reg [`BIT_WIDTH-1:0] c_z0__46; +reg [`BIT_WIDTH-1:0] c_z0__47; +reg [`BIT_WIDTH-1:0] c_z0__48; +reg [`BIT_WIDTH-1:0] c_z0__49; +reg [`BIT_WIDTH-1:0] c_z0__50; +reg [`BIT_WIDTH-1:0] c_z0__51; +reg [`BIT_WIDTH-1:0] c_z0__52; +reg [`BIT_WIDTH-1:0] c_z0__53; +reg [`BIT_WIDTH-1:0] c_z0__54; +reg [`BIT_WIDTH-1:0] c_z0__55; +reg [`BIT_WIDTH-1:0] c_z0__56; +reg [`BIT_WIDTH-1:0] c_z0__57; +reg [`BIT_WIDTH-1:0] c_z0__58; +reg [`BIT_WIDTH-1:0] c_z0__59; + + + +//reg [`BIT_WIDTH-1:0] c_mut[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_mut__0; +reg [`BIT_WIDTH-1:0] c_mut__1; +reg [`BIT_WIDTH-1:0] c_mut__2; +reg [`BIT_WIDTH-1:0] c_mut__3; +reg [`BIT_WIDTH-1:0] c_mut__4; +reg [`BIT_WIDTH-1:0] c_mut__5; +reg [`BIT_WIDTH-1:0] c_mut__6; +reg [`BIT_WIDTH-1:0] c_mut__7; +reg [`BIT_WIDTH-1:0] c_mut__8; +reg [`BIT_WIDTH-1:0] c_mut__9; +reg [`BIT_WIDTH-1:0] c_mut__10; +reg [`BIT_WIDTH-1:0] c_mut__11; +reg [`BIT_WIDTH-1:0] c_mut__12; +reg [`BIT_WIDTH-1:0] c_mut__13; +reg [`BIT_WIDTH-1:0] c_mut__14; +reg [`BIT_WIDTH-1:0] c_mut__15; +reg [`BIT_WIDTH-1:0] c_mut__16; +reg [`BIT_WIDTH-1:0] c_mut__17; +reg [`BIT_WIDTH-1:0] c_mut__18; +reg [`BIT_WIDTH-1:0] c_mut__19; +reg [`BIT_WIDTH-1:0] c_mut__20; +reg [`BIT_WIDTH-1:0] c_mut__21; +reg [`BIT_WIDTH-1:0] c_mut__22; +reg [`BIT_WIDTH-1:0] c_mut__23; +reg [`BIT_WIDTH-1:0] c_mut__24; +reg [`BIT_WIDTH-1:0] c_mut__25; +reg [`BIT_WIDTH-1:0] c_mut__26; +reg [`BIT_WIDTH-1:0] c_mut__27; +reg [`BIT_WIDTH-1:0] c_mut__28; +reg [`BIT_WIDTH-1:0] c_mut__29; +reg [`BIT_WIDTH-1:0] c_mut__30; +reg [`BIT_WIDTH-1:0] c_mut__31; +reg [`BIT_WIDTH-1:0] c_mut__32; +reg [`BIT_WIDTH-1:0] c_mut__33; +reg [`BIT_WIDTH-1:0] c_mut__34; +reg [`BIT_WIDTH-1:0] c_mut__35; +reg [`BIT_WIDTH-1:0] c_mut__36; +reg [`BIT_WIDTH-1:0] c_mut__37; +reg [`BIT_WIDTH-1:0] c_mut__38; +reg [`BIT_WIDTH-1:0] c_mut__39; +reg [`BIT_WIDTH-1:0] c_mut__40; +reg [`BIT_WIDTH-1:0] c_mut__41; +reg [`BIT_WIDTH-1:0] c_mut__42; +reg [`BIT_WIDTH-1:0] c_mut__43; +reg [`BIT_WIDTH-1:0] c_mut__44; +reg [`BIT_WIDTH-1:0] c_mut__45; +reg [`BIT_WIDTH-1:0] c_mut__46; +reg [`BIT_WIDTH-1:0] c_mut__47; +reg [`BIT_WIDTH-1:0] c_mut__48; +reg [`BIT_WIDTH-1:0] c_mut__49; +reg [`BIT_WIDTH-1:0] c_mut__50; +reg [`BIT_WIDTH-1:0] c_mut__51; +reg [`BIT_WIDTH-1:0] c_mut__52; +reg [`BIT_WIDTH-1:0] c_mut__53; +reg [`BIT_WIDTH-1:0] c_mut__54; +reg [`BIT_WIDTH-1:0] c_mut__55; +reg [`BIT_WIDTH-1:0] c_mut__56; +reg [`BIT_WIDTH-1:0] c_mut__57; +reg [`BIT_WIDTH-1:0] c_mut__58; +reg [`BIT_WIDTH-1:0] c_mut__59; + + +//reg [`BIT_WIDTH-1:0] r_x [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_x__0; +reg [`BIT_WIDTH-1:0] r_x__1; +reg [`BIT_WIDTH-1:0] r_x__2; +reg [`BIT_WIDTH-1:0] r_x__3; +reg [`BIT_WIDTH-1:0] r_x__4; +reg [`BIT_WIDTH-1:0] r_x__5; +reg [`BIT_WIDTH-1:0] r_x__6; +reg [`BIT_WIDTH-1:0] r_x__7; +reg [`BIT_WIDTH-1:0] r_x__8; +reg [`BIT_WIDTH-1:0] r_x__9; +reg [`BIT_WIDTH-1:0] r_x__10; +reg [`BIT_WIDTH-1:0] r_x__11; +reg [`BIT_WIDTH-1:0] r_x__12; +reg [`BIT_WIDTH-1:0] r_x__13; +reg [`BIT_WIDTH-1:0] r_x__14; +reg [`BIT_WIDTH-1:0] r_x__15; +reg [`BIT_WIDTH-1:0] r_x__16; +reg [`BIT_WIDTH-1:0] r_x__17; +reg [`BIT_WIDTH-1:0] r_x__18; +reg [`BIT_WIDTH-1:0] r_x__19; +reg [`BIT_WIDTH-1:0] r_x__20; +reg [`BIT_WIDTH-1:0] r_x__21; +reg [`BIT_WIDTH-1:0] r_x__22; +reg [`BIT_WIDTH-1:0] r_x__23; +reg [`BIT_WIDTH-1:0] r_x__24; +reg [`BIT_WIDTH-1:0] r_x__25; +reg [`BIT_WIDTH-1:0] r_x__26; +reg [`BIT_WIDTH-1:0] r_x__27; +reg [`BIT_WIDTH-1:0] r_x__28; +reg [`BIT_WIDTH-1:0] r_x__29; +reg [`BIT_WIDTH-1:0] r_x__30; +reg [`BIT_WIDTH-1:0] r_x__31; +reg [`BIT_WIDTH-1:0] r_x__32; +reg [`BIT_WIDTH-1:0] r_x__33; +reg [`BIT_WIDTH-1:0] r_x__34; +reg [`BIT_WIDTH-1:0] r_x__35; +reg [`BIT_WIDTH-1:0] r_x__36; +reg [`BIT_WIDTH-1:0] r_x__37; +reg [`BIT_WIDTH-1:0] r_x__38; +reg [`BIT_WIDTH-1:0] r_x__39; +reg [`BIT_WIDTH-1:0] r_x__40; +reg [`BIT_WIDTH-1:0] r_x__41; +reg [`BIT_WIDTH-1:0] r_x__42; +reg [`BIT_WIDTH-1:0] r_x__43; +reg [`BIT_WIDTH-1:0] r_x__44; +reg [`BIT_WIDTH-1:0] r_x__45; +reg [`BIT_WIDTH-1:0] r_x__46; +reg [`BIT_WIDTH-1:0] r_x__47; +reg [`BIT_WIDTH-1:0] r_x__48; +reg [`BIT_WIDTH-1:0] r_x__49; +reg [`BIT_WIDTH-1:0] r_x__50; +reg [`BIT_WIDTH-1:0] r_x__51; +reg [`BIT_WIDTH-1:0] r_x__52; +reg [`BIT_WIDTH-1:0] r_x__53; +reg [`BIT_WIDTH-1:0] r_x__54; +reg [`BIT_WIDTH-1:0] r_x__55; +reg [`BIT_WIDTH-1:0] r_x__56; +reg [`BIT_WIDTH-1:0] r_x__57; +reg [`BIT_WIDTH-1:0] r_x__58; +reg [`BIT_WIDTH-1:0] r_x__59; + +//reg [`BIT_WIDTH-1:0] r_y [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_y__0; +reg [`BIT_WIDTH-1:0] r_y__1; +reg [`BIT_WIDTH-1:0] r_y__2; +reg [`BIT_WIDTH-1:0] r_y__3; +reg [`BIT_WIDTH-1:0] r_y__4; +reg [`BIT_WIDTH-1:0] r_y__5; +reg [`BIT_WIDTH-1:0] r_y__6; +reg [`BIT_WIDTH-1:0] r_y__7; +reg [`BIT_WIDTH-1:0] r_y__8; +reg [`BIT_WIDTH-1:0] r_y__9; +reg [`BIT_WIDTH-1:0] r_y__10; +reg [`BIT_WIDTH-1:0] r_y__11; +reg [`BIT_WIDTH-1:0] r_y__12; +reg [`BIT_WIDTH-1:0] r_y__13; +reg [`BIT_WIDTH-1:0] r_y__14; +reg [`BIT_WIDTH-1:0] r_y__15; +reg [`BIT_WIDTH-1:0] r_y__16; +reg [`BIT_WIDTH-1:0] r_y__17; +reg [`BIT_WIDTH-1:0] r_y__18; +reg [`BIT_WIDTH-1:0] r_y__19; +reg [`BIT_WIDTH-1:0] r_y__20; +reg [`BIT_WIDTH-1:0] r_y__21; +reg [`BIT_WIDTH-1:0] r_y__22; +reg [`BIT_WIDTH-1:0] r_y__23; +reg [`BIT_WIDTH-1:0] r_y__24; +reg [`BIT_WIDTH-1:0] r_y__25; +reg [`BIT_WIDTH-1:0] r_y__26; +reg [`BIT_WIDTH-1:0] r_y__27; +reg [`BIT_WIDTH-1:0] r_y__28; +reg [`BIT_WIDTH-1:0] r_y__29; +reg [`BIT_WIDTH-1:0] r_y__30; +reg [`BIT_WIDTH-1:0] r_y__31; +reg [`BIT_WIDTH-1:0] r_y__32; +reg [`BIT_WIDTH-1:0] r_y__33; +reg [`BIT_WIDTH-1:0] r_y__34; +reg [`BIT_WIDTH-1:0] r_y__35; +reg [`BIT_WIDTH-1:0] r_y__36; +reg [`BIT_WIDTH-1:0] r_y__37; +reg [`BIT_WIDTH-1:0] r_y__38; +reg [`BIT_WIDTH-1:0] r_y__39; +reg [`BIT_WIDTH-1:0] r_y__40; +reg [`BIT_WIDTH-1:0] r_y__41; +reg [`BIT_WIDTH-1:0] r_y__42; +reg [`BIT_WIDTH-1:0] r_y__43; +reg [`BIT_WIDTH-1:0] r_y__44; +reg [`BIT_WIDTH-1:0] r_y__45; +reg [`BIT_WIDTH-1:0] r_y__46; +reg [`BIT_WIDTH-1:0] r_y__47; +reg [`BIT_WIDTH-1:0] r_y__48; +reg [`BIT_WIDTH-1:0] r_y__49; +reg [`BIT_WIDTH-1:0] r_y__50; +reg [`BIT_WIDTH-1:0] r_y__51; +reg [`BIT_WIDTH-1:0] r_y__52; +reg [`BIT_WIDTH-1:0] r_y__53; +reg [`BIT_WIDTH-1:0] r_y__54; +reg [`BIT_WIDTH-1:0] r_y__55; +reg [`BIT_WIDTH-1:0] r_y__56; +reg [`BIT_WIDTH-1:0] r_y__57; +reg [`BIT_WIDTH-1:0] r_y__58; +reg [`BIT_WIDTH-1:0] r_y__59; + + + +//reg [`BIT_WIDTH-1:0] r_z [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z__0; +reg [`BIT_WIDTH-1:0] r_z__1; +reg [`BIT_WIDTH-1:0] r_z__2; +reg [`BIT_WIDTH-1:0] r_z__3; +reg [`BIT_WIDTH-1:0] r_z__4; +reg [`BIT_WIDTH-1:0] r_z__5; +reg [`BIT_WIDTH-1:0] r_z__6; +reg [`BIT_WIDTH-1:0] r_z__7; +reg [`BIT_WIDTH-1:0] r_z__8; +reg [`BIT_WIDTH-1:0] r_z__9; +reg [`BIT_WIDTH-1:0] r_z__10; +reg [`BIT_WIDTH-1:0] r_z__11; +reg [`BIT_WIDTH-1:0] r_z__12; +reg [`BIT_WIDTH-1:0] r_z__13; +reg [`BIT_WIDTH-1:0] r_z__14; +reg [`BIT_WIDTH-1:0] r_z__15; +reg [`BIT_WIDTH-1:0] r_z__16; +reg [`BIT_WIDTH-1:0] r_z__17; +reg [`BIT_WIDTH-1:0] r_z__18; +reg [`BIT_WIDTH-1:0] r_z__19; +reg [`BIT_WIDTH-1:0] r_z__20; +reg [`BIT_WIDTH-1:0] r_z__21; +reg [`BIT_WIDTH-1:0] r_z__22; +reg [`BIT_WIDTH-1:0] r_z__23; +reg [`BIT_WIDTH-1:0] r_z__24; +reg [`BIT_WIDTH-1:0] r_z__25; +reg [`BIT_WIDTH-1:0] r_z__26; +reg [`BIT_WIDTH-1:0] r_z__27; +reg [`BIT_WIDTH-1:0] r_z__28; +reg [`BIT_WIDTH-1:0] r_z__29; +reg [`BIT_WIDTH-1:0] r_z__30; +reg [`BIT_WIDTH-1:0] r_z__31; +reg [`BIT_WIDTH-1:0] r_z__32; +reg [`BIT_WIDTH-1:0] r_z__33; +reg [`BIT_WIDTH-1:0] r_z__34; +reg [`BIT_WIDTH-1:0] r_z__35; +reg [`BIT_WIDTH-1:0] r_z__36; +reg [`BIT_WIDTH-1:0] r_z__37; +reg [`BIT_WIDTH-1:0] r_z__38; +reg [`BIT_WIDTH-1:0] r_z__39; +reg [`BIT_WIDTH-1:0] r_z__40; +reg [`BIT_WIDTH-1:0] r_z__41; +reg [`BIT_WIDTH-1:0] r_z__42; +reg [`BIT_WIDTH-1:0] r_z__43; +reg [`BIT_WIDTH-1:0] r_z__44; +reg [`BIT_WIDTH-1:0] r_z__45; +reg [`BIT_WIDTH-1:0] r_z__46; +reg [`BIT_WIDTH-1:0] r_z__47; +reg [`BIT_WIDTH-1:0] r_z__48; +reg [`BIT_WIDTH-1:0] r_z__49; +reg [`BIT_WIDTH-1:0] r_z__50; +reg [`BIT_WIDTH-1:0] r_z__51; +reg [`BIT_WIDTH-1:0] r_z__52; +reg [`BIT_WIDTH-1:0] r_z__53; +reg [`BIT_WIDTH-1:0] r_z__54; +reg [`BIT_WIDTH-1:0] r_z__55; +reg [`BIT_WIDTH-1:0] r_z__56; +reg [`BIT_WIDTH-1:0] r_z__57; +reg [`BIT_WIDTH-1:0] r_z__58; +reg [`BIT_WIDTH-1:0] r_z__59; + +//reg [`BIT_WIDTH-1:0] r_ux [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_ux__0; +reg [`BIT_WIDTH-1:0] r_ux__1; +reg [`BIT_WIDTH-1:0] r_ux__2; +reg [`BIT_WIDTH-1:0] r_ux__3; +reg [`BIT_WIDTH-1:0] r_ux__4; +reg [`BIT_WIDTH-1:0] r_ux__5; +reg [`BIT_WIDTH-1:0] r_ux__6; +reg [`BIT_WIDTH-1:0] r_ux__7; +reg [`BIT_WIDTH-1:0] r_ux__8; +reg [`BIT_WIDTH-1:0] r_ux__9; +reg [`BIT_WIDTH-1:0] r_ux__10; +reg [`BIT_WIDTH-1:0] r_ux__11; +reg [`BIT_WIDTH-1:0] r_ux__12; +reg [`BIT_WIDTH-1:0] r_ux__13; +reg [`BIT_WIDTH-1:0] r_ux__14; +reg [`BIT_WIDTH-1:0] r_ux__15; +reg [`BIT_WIDTH-1:0] r_ux__16; +reg [`BIT_WIDTH-1:0] r_ux__17; +reg [`BIT_WIDTH-1:0] r_ux__18; +reg [`BIT_WIDTH-1:0] r_ux__19; +reg [`BIT_WIDTH-1:0] r_ux__20; +reg [`BIT_WIDTH-1:0] r_ux__21; +reg [`BIT_WIDTH-1:0] r_ux__22; +reg [`BIT_WIDTH-1:0] r_ux__23; +reg [`BIT_WIDTH-1:0] r_ux__24; +reg [`BIT_WIDTH-1:0] r_ux__25; +reg [`BIT_WIDTH-1:0] r_ux__26; +reg [`BIT_WIDTH-1:0] r_ux__27; +reg [`BIT_WIDTH-1:0] r_ux__28; +reg [`BIT_WIDTH-1:0] r_ux__29; +reg [`BIT_WIDTH-1:0] r_ux__30; +reg [`BIT_WIDTH-1:0] r_ux__31; +reg [`BIT_WIDTH-1:0] r_ux__32; +reg [`BIT_WIDTH-1:0] r_ux__33; +reg [`BIT_WIDTH-1:0] r_ux__34; +reg [`BIT_WIDTH-1:0] r_ux__35; +reg [`BIT_WIDTH-1:0] r_ux__36; +reg [`BIT_WIDTH-1:0] r_ux__37; +reg [`BIT_WIDTH-1:0] r_ux__38; +reg [`BIT_WIDTH-1:0] r_ux__39; +reg [`BIT_WIDTH-1:0] r_ux__40; +reg [`BIT_WIDTH-1:0] r_ux__41; +reg [`BIT_WIDTH-1:0] r_ux__42; +reg [`BIT_WIDTH-1:0] r_ux__43; +reg [`BIT_WIDTH-1:0] r_ux__44; +reg [`BIT_WIDTH-1:0] r_ux__45; +reg [`BIT_WIDTH-1:0] r_ux__46; +reg [`BIT_WIDTH-1:0] r_ux__47; +reg [`BIT_WIDTH-1:0] r_ux__48; +reg [`BIT_WIDTH-1:0] r_ux__49; +reg [`BIT_WIDTH-1:0] r_ux__50; +reg [`BIT_WIDTH-1:0] r_ux__51; +reg [`BIT_WIDTH-1:0] r_ux__52; +reg [`BIT_WIDTH-1:0] r_ux__53; +reg [`BIT_WIDTH-1:0] r_ux__54; +reg [`BIT_WIDTH-1:0] r_ux__55; +reg [`BIT_WIDTH-1:0] r_ux__56; +reg [`BIT_WIDTH-1:0] r_ux__57; +reg [`BIT_WIDTH-1:0] r_ux__58; +reg [`BIT_WIDTH-1:0] r_ux__59; + +//reg [`BIT_WIDTH-1:0] r_uy [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_uy__0; +reg [`BIT_WIDTH-1:0] r_uy__1; +reg [`BIT_WIDTH-1:0] r_uy__2; +reg [`BIT_WIDTH-1:0] r_uy__3; +reg [`BIT_WIDTH-1:0] r_uy__4; +reg [`BIT_WIDTH-1:0] r_uy__5; +reg [`BIT_WIDTH-1:0] r_uy__6; +reg [`BIT_WIDTH-1:0] r_uy__7; +reg [`BIT_WIDTH-1:0] r_uy__8; +reg [`BIT_WIDTH-1:0] r_uy__9; +reg [`BIT_WIDTH-1:0] r_uy__10; +reg [`BIT_WIDTH-1:0] r_uy__11; +reg [`BIT_WIDTH-1:0] r_uy__12; +reg [`BIT_WIDTH-1:0] r_uy__13; +reg [`BIT_WIDTH-1:0] r_uy__14; +reg [`BIT_WIDTH-1:0] r_uy__15; +reg [`BIT_WIDTH-1:0] r_uy__16; +reg [`BIT_WIDTH-1:0] r_uy__17; +reg [`BIT_WIDTH-1:0] r_uy__18; +reg [`BIT_WIDTH-1:0] r_uy__19; +reg [`BIT_WIDTH-1:0] r_uy__20; +reg [`BIT_WIDTH-1:0] r_uy__21; +reg [`BIT_WIDTH-1:0] r_uy__22; +reg [`BIT_WIDTH-1:0] r_uy__23; +reg [`BIT_WIDTH-1:0] r_uy__24; +reg [`BIT_WIDTH-1:0] r_uy__25; +reg [`BIT_WIDTH-1:0] r_uy__26; +reg [`BIT_WIDTH-1:0] r_uy__27; +reg [`BIT_WIDTH-1:0] r_uy__28; +reg [`BIT_WIDTH-1:0] r_uy__29; +reg [`BIT_WIDTH-1:0] r_uy__30; +reg [`BIT_WIDTH-1:0] r_uy__31; +reg [`BIT_WIDTH-1:0] r_uy__32; +reg [`BIT_WIDTH-1:0] r_uy__33; +reg [`BIT_WIDTH-1:0] r_uy__34; +reg [`BIT_WIDTH-1:0] r_uy__35; +reg [`BIT_WIDTH-1:0] r_uy__36; +reg [`BIT_WIDTH-1:0] r_uy__37; +reg [`BIT_WIDTH-1:0] r_uy__38; +reg [`BIT_WIDTH-1:0] r_uy__39; +reg [`BIT_WIDTH-1:0] r_uy__40; +reg [`BIT_WIDTH-1:0] r_uy__41; +reg [`BIT_WIDTH-1:0] r_uy__42; +reg [`BIT_WIDTH-1:0] r_uy__43; +reg [`BIT_WIDTH-1:0] r_uy__44; +reg [`BIT_WIDTH-1:0] r_uy__45; +reg [`BIT_WIDTH-1:0] r_uy__46; +reg [`BIT_WIDTH-1:0] r_uy__47; +reg [`BIT_WIDTH-1:0] r_uy__48; +reg [`BIT_WIDTH-1:0] r_uy__49; +reg [`BIT_WIDTH-1:0] r_uy__50; +reg [`BIT_WIDTH-1:0] r_uy__51; +reg [`BIT_WIDTH-1:0] r_uy__52; +reg [`BIT_WIDTH-1:0] r_uy__53; +reg [`BIT_WIDTH-1:0] r_uy__54; +reg [`BIT_WIDTH-1:0] r_uy__55; +reg [`BIT_WIDTH-1:0] r_uy__56; +reg [`BIT_WIDTH-1:0] r_uy__57; +reg [`BIT_WIDTH-1:0] r_uy__58; +reg [`BIT_WIDTH-1:0] r_uy__59; + +//reg [`BIT_WIDTH-1:0] r_uz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_uz__0; +reg [`BIT_WIDTH-1:0] r_uz__1; +reg [`BIT_WIDTH-1:0] r_uz__2; +reg [`BIT_WIDTH-1:0] r_uz__3; +reg [`BIT_WIDTH-1:0] r_uz__4; +reg [`BIT_WIDTH-1:0] r_uz__5; +reg [`BIT_WIDTH-1:0] r_uz__6; +reg [`BIT_WIDTH-1:0] r_uz__7; +reg [`BIT_WIDTH-1:0] r_uz__8; +reg [`BIT_WIDTH-1:0] r_uz__9; +reg [`BIT_WIDTH-1:0] r_uz__10; +reg [`BIT_WIDTH-1:0] r_uz__11; +reg [`BIT_WIDTH-1:0] r_uz__12; +reg [`BIT_WIDTH-1:0] r_uz__13; +reg [`BIT_WIDTH-1:0] r_uz__14; +reg [`BIT_WIDTH-1:0] r_uz__15; +reg [`BIT_WIDTH-1:0] r_uz__16; +reg [`BIT_WIDTH-1:0] r_uz__17; +reg [`BIT_WIDTH-1:0] r_uz__18; +reg [`BIT_WIDTH-1:0] r_uz__19; +reg [`BIT_WIDTH-1:0] r_uz__20; +reg [`BIT_WIDTH-1:0] r_uz__21; +reg [`BIT_WIDTH-1:0] r_uz__22; +reg [`BIT_WIDTH-1:0] r_uz__23; +reg [`BIT_WIDTH-1:0] r_uz__24; +reg [`BIT_WIDTH-1:0] r_uz__25; +reg [`BIT_WIDTH-1:0] r_uz__26; +reg [`BIT_WIDTH-1:0] r_uz__27; +reg [`BIT_WIDTH-1:0] r_uz__28; +reg [`BIT_WIDTH-1:0] r_uz__29; +reg [`BIT_WIDTH-1:0] r_uz__30; +reg [`BIT_WIDTH-1:0] r_uz__31; +reg [`BIT_WIDTH-1:0] r_uz__32; +reg [`BIT_WIDTH-1:0] r_uz__33; +reg [`BIT_WIDTH-1:0] r_uz__34; +reg [`BIT_WIDTH-1:0] r_uz__35; +reg [`BIT_WIDTH-1:0] r_uz__36; +reg [`BIT_WIDTH-1:0] r_uz__37; +reg [`BIT_WIDTH-1:0] r_uz__38; +reg [`BIT_WIDTH-1:0] r_uz__39; +reg [`BIT_WIDTH-1:0] r_uz__40; +reg [`BIT_WIDTH-1:0] r_uz__41; +reg [`BIT_WIDTH-1:0] r_uz__42; +reg [`BIT_WIDTH-1:0] r_uz__43; +reg [`BIT_WIDTH-1:0] r_uz__44; +reg [`BIT_WIDTH-1:0] r_uz__45; +reg [`BIT_WIDTH-1:0] r_uz__46; +reg [`BIT_WIDTH-1:0] r_uz__47; +reg [`BIT_WIDTH-1:0] r_uz__48; +reg [`BIT_WIDTH-1:0] r_uz__49; +reg [`BIT_WIDTH-1:0] r_uz__50; +reg [`BIT_WIDTH-1:0] r_uz__51; +reg [`BIT_WIDTH-1:0] r_uz__52; +reg [`BIT_WIDTH-1:0] r_uz__53; +reg [`BIT_WIDTH-1:0] r_uz__54; +reg [`BIT_WIDTH-1:0] r_uz__55; +reg [`BIT_WIDTH-1:0] r_uz__56; +reg [`BIT_WIDTH-1:0] r_uz__57; +reg [`BIT_WIDTH-1:0] r_uz__58; +reg [`BIT_WIDTH-1:0] r_uz__59; + + +//reg [`BIT_WIDTH-1:0] r_sz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sz__0; +reg [`BIT_WIDTH-1:0] r_sz__1; +reg [`BIT_WIDTH-1:0] r_sz__2; +reg [`BIT_WIDTH-1:0] r_sz__3; +reg [`BIT_WIDTH-1:0] r_sz__4; +reg [`BIT_WIDTH-1:0] r_sz__5; +reg [`BIT_WIDTH-1:0] r_sz__6; +reg [`BIT_WIDTH-1:0] r_sz__7; +reg [`BIT_WIDTH-1:0] r_sz__8; +reg [`BIT_WIDTH-1:0] r_sz__9; +reg [`BIT_WIDTH-1:0] r_sz__10; +reg [`BIT_WIDTH-1:0] r_sz__11; +reg [`BIT_WIDTH-1:0] r_sz__12; +reg [`BIT_WIDTH-1:0] r_sz__13; +reg [`BIT_WIDTH-1:0] r_sz__14; +reg [`BIT_WIDTH-1:0] r_sz__15; +reg [`BIT_WIDTH-1:0] r_sz__16; +reg [`BIT_WIDTH-1:0] r_sz__17; +reg [`BIT_WIDTH-1:0] r_sz__18; +reg [`BIT_WIDTH-1:0] r_sz__19; +reg [`BIT_WIDTH-1:0] r_sz__20; +reg [`BIT_WIDTH-1:0] r_sz__21; +reg [`BIT_WIDTH-1:0] r_sz__22; +reg [`BIT_WIDTH-1:0] r_sz__23; +reg [`BIT_WIDTH-1:0] r_sz__24; +reg [`BIT_WIDTH-1:0] r_sz__25; +reg [`BIT_WIDTH-1:0] r_sz__26; +reg [`BIT_WIDTH-1:0] r_sz__27; +reg [`BIT_WIDTH-1:0] r_sz__28; +reg [`BIT_WIDTH-1:0] r_sz__29; +reg [`BIT_WIDTH-1:0] r_sz__30; +reg [`BIT_WIDTH-1:0] r_sz__31; +reg [`BIT_WIDTH-1:0] r_sz__32; +reg [`BIT_WIDTH-1:0] r_sz__33; +reg [`BIT_WIDTH-1:0] r_sz__34; +reg [`BIT_WIDTH-1:0] r_sz__35; +reg [`BIT_WIDTH-1:0] r_sz__36; +reg [`BIT_WIDTH-1:0] r_sz__37; +reg [`BIT_WIDTH-1:0] r_sz__38; +reg [`BIT_WIDTH-1:0] r_sz__39; +reg [`BIT_WIDTH-1:0] r_sz__40; +reg [`BIT_WIDTH-1:0] r_sz__41; +reg [`BIT_WIDTH-1:0] r_sz__42; +reg [`BIT_WIDTH-1:0] r_sz__43; +reg [`BIT_WIDTH-1:0] r_sz__44; +reg [`BIT_WIDTH-1:0] r_sz__45; +reg [`BIT_WIDTH-1:0] r_sz__46; +reg [`BIT_WIDTH-1:0] r_sz__47; +reg [`BIT_WIDTH-1:0] r_sz__48; +reg [`BIT_WIDTH-1:0] r_sz__49; +reg [`BIT_WIDTH-1:0] r_sz__50; +reg [`BIT_WIDTH-1:0] r_sz__51; +reg [`BIT_WIDTH-1:0] r_sz__52; +reg [`BIT_WIDTH-1:0] r_sz__53; +reg [`BIT_WIDTH-1:0] r_sz__54; +reg [`BIT_WIDTH-1:0] r_sz__55; +reg [`BIT_WIDTH-1:0] r_sz__56; +reg [`BIT_WIDTH-1:0] r_sz__57; +reg [`BIT_WIDTH-1:0] r_sz__58; +reg [`BIT_WIDTH-1:0] r_sz__59; + +//reg [`BIT_WIDTH-1:0] r_sr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sr__0; +reg [`BIT_WIDTH-1:0] r_sr__1; +reg [`BIT_WIDTH-1:0] r_sr__2; +reg [`BIT_WIDTH-1:0] r_sr__3; +reg [`BIT_WIDTH-1:0] r_sr__4; +reg [`BIT_WIDTH-1:0] r_sr__5; +reg [`BIT_WIDTH-1:0] r_sr__6; +reg [`BIT_WIDTH-1:0] r_sr__7; +reg [`BIT_WIDTH-1:0] r_sr__8; +reg [`BIT_WIDTH-1:0] r_sr__9; +reg [`BIT_WIDTH-1:0] r_sr__10; +reg [`BIT_WIDTH-1:0] r_sr__11; +reg [`BIT_WIDTH-1:0] r_sr__12; +reg [`BIT_WIDTH-1:0] r_sr__13; +reg [`BIT_WIDTH-1:0] r_sr__14; +reg [`BIT_WIDTH-1:0] r_sr__15; +reg [`BIT_WIDTH-1:0] r_sr__16; +reg [`BIT_WIDTH-1:0] r_sr__17; +reg [`BIT_WIDTH-1:0] r_sr__18; +reg [`BIT_WIDTH-1:0] r_sr__19; +reg [`BIT_WIDTH-1:0] r_sr__20; +reg [`BIT_WIDTH-1:0] r_sr__21; +reg [`BIT_WIDTH-1:0] r_sr__22; +reg [`BIT_WIDTH-1:0] r_sr__23; +reg [`BIT_WIDTH-1:0] r_sr__24; +reg [`BIT_WIDTH-1:0] r_sr__25; +reg [`BIT_WIDTH-1:0] r_sr__26; +reg [`BIT_WIDTH-1:0] r_sr__27; +reg [`BIT_WIDTH-1:0] r_sr__28; +reg [`BIT_WIDTH-1:0] r_sr__29; +reg [`BIT_WIDTH-1:0] r_sr__30; +reg [`BIT_WIDTH-1:0] r_sr__31; +reg [`BIT_WIDTH-1:0] r_sr__32; +reg [`BIT_WIDTH-1:0] r_sr__33; +reg [`BIT_WIDTH-1:0] r_sr__34; +reg [`BIT_WIDTH-1:0] r_sr__35; +reg [`BIT_WIDTH-1:0] r_sr__36; +reg [`BIT_WIDTH-1:0] r_sr__37; +reg [`BIT_WIDTH-1:0] r_sr__38; +reg [`BIT_WIDTH-1:0] r_sr__39; +reg [`BIT_WIDTH-1:0] r_sr__40; +reg [`BIT_WIDTH-1:0] r_sr__41; +reg [`BIT_WIDTH-1:0] r_sr__42; +reg [`BIT_WIDTH-1:0] r_sr__43; +reg [`BIT_WIDTH-1:0] r_sr__44; +reg [`BIT_WIDTH-1:0] r_sr__45; +reg [`BIT_WIDTH-1:0] r_sr__46; +reg [`BIT_WIDTH-1:0] r_sr__47; +reg [`BIT_WIDTH-1:0] r_sr__48; +reg [`BIT_WIDTH-1:0] r_sr__49; +reg [`BIT_WIDTH-1:0] r_sr__50; +reg [`BIT_WIDTH-1:0] r_sr__51; +reg [`BIT_WIDTH-1:0] r_sr__52; +reg [`BIT_WIDTH-1:0] r_sr__53; +reg [`BIT_WIDTH-1:0] r_sr__54; +reg [`BIT_WIDTH-1:0] r_sr__55; +reg [`BIT_WIDTH-1:0] r_sr__56; +reg [`BIT_WIDTH-1:0] r_sr__57; +reg [`BIT_WIDTH-1:0] r_sr__58; +reg [`BIT_WIDTH-1:0] r_sr__59; + +//reg [`BIT_WIDTH-1:0] r_sleftz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sleftz__0; +reg [`BIT_WIDTH-1:0] r_sleftz__1; +reg [`BIT_WIDTH-1:0] r_sleftz__2; +reg [`BIT_WIDTH-1:0] r_sleftz__3; +reg [`BIT_WIDTH-1:0] r_sleftz__4; +reg [`BIT_WIDTH-1:0] r_sleftz__5; +reg [`BIT_WIDTH-1:0] r_sleftz__6; +reg [`BIT_WIDTH-1:0] r_sleftz__7; +reg [`BIT_WIDTH-1:0] r_sleftz__8; +reg [`BIT_WIDTH-1:0] r_sleftz__9; +reg [`BIT_WIDTH-1:0] r_sleftz__10; +reg [`BIT_WIDTH-1:0] r_sleftz__11; +reg [`BIT_WIDTH-1:0] r_sleftz__12; +reg [`BIT_WIDTH-1:0] r_sleftz__13; +reg [`BIT_WIDTH-1:0] r_sleftz__14; +reg [`BIT_WIDTH-1:0] r_sleftz__15; +reg [`BIT_WIDTH-1:0] r_sleftz__16; +reg [`BIT_WIDTH-1:0] r_sleftz__17; +reg [`BIT_WIDTH-1:0] r_sleftz__18; +reg [`BIT_WIDTH-1:0] r_sleftz__19; +reg [`BIT_WIDTH-1:0] r_sleftz__20; +reg [`BIT_WIDTH-1:0] r_sleftz__21; +reg [`BIT_WIDTH-1:0] r_sleftz__22; +reg [`BIT_WIDTH-1:0] r_sleftz__23; +reg [`BIT_WIDTH-1:0] r_sleftz__24; +reg [`BIT_WIDTH-1:0] r_sleftz__25; +reg [`BIT_WIDTH-1:0] r_sleftz__26; +reg [`BIT_WIDTH-1:0] r_sleftz__27; +reg [`BIT_WIDTH-1:0] r_sleftz__28; +reg [`BIT_WIDTH-1:0] r_sleftz__29; +reg [`BIT_WIDTH-1:0] r_sleftz__30; +reg [`BIT_WIDTH-1:0] r_sleftz__31; +reg [`BIT_WIDTH-1:0] r_sleftz__32; +reg [`BIT_WIDTH-1:0] r_sleftz__33; +reg [`BIT_WIDTH-1:0] r_sleftz__34; +reg [`BIT_WIDTH-1:0] r_sleftz__35; +reg [`BIT_WIDTH-1:0] r_sleftz__36; +reg [`BIT_WIDTH-1:0] r_sleftz__37; +reg [`BIT_WIDTH-1:0] r_sleftz__38; +reg [`BIT_WIDTH-1:0] r_sleftz__39; +reg [`BIT_WIDTH-1:0] r_sleftz__40; +reg [`BIT_WIDTH-1:0] r_sleftz__41; +reg [`BIT_WIDTH-1:0] r_sleftz__42; +reg [`BIT_WIDTH-1:0] r_sleftz__43; +reg [`BIT_WIDTH-1:0] r_sleftz__44; +reg [`BIT_WIDTH-1:0] r_sleftz__45; +reg [`BIT_WIDTH-1:0] r_sleftz__46; +reg [`BIT_WIDTH-1:0] r_sleftz__47; +reg [`BIT_WIDTH-1:0] r_sleftz__48; +reg [`BIT_WIDTH-1:0] r_sleftz__49; +reg [`BIT_WIDTH-1:0] r_sleftz__50; +reg [`BIT_WIDTH-1:0] r_sleftz__51; +reg [`BIT_WIDTH-1:0] r_sleftz__52; +reg [`BIT_WIDTH-1:0] r_sleftz__53; +reg [`BIT_WIDTH-1:0] r_sleftz__54; +reg [`BIT_WIDTH-1:0] r_sleftz__55; +reg [`BIT_WIDTH-1:0] r_sleftz__56; +reg [`BIT_WIDTH-1:0] r_sleftz__57; +reg [`BIT_WIDTH-1:0] r_sleftz__58; +reg [`BIT_WIDTH-1:0] r_sleftz__59; + + + +//reg [`BIT_WIDTH-1:0] r_sleftr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sleftr__0; +reg [`BIT_WIDTH-1:0] r_sleftr__1; +reg [`BIT_WIDTH-1:0] r_sleftr__2; +reg [`BIT_WIDTH-1:0] r_sleftr__3; +reg [`BIT_WIDTH-1:0] r_sleftr__4; +reg [`BIT_WIDTH-1:0] r_sleftr__5; +reg [`BIT_WIDTH-1:0] r_sleftr__6; +reg [`BIT_WIDTH-1:0] r_sleftr__7; +reg [`BIT_WIDTH-1:0] r_sleftr__8; +reg [`BIT_WIDTH-1:0] r_sleftr__9; +reg [`BIT_WIDTH-1:0] r_sleftr__10; +reg [`BIT_WIDTH-1:0] r_sleftr__11; +reg [`BIT_WIDTH-1:0] r_sleftr__12; +reg [`BIT_WIDTH-1:0] r_sleftr__13; + +reg [`BIT_WIDTH-1:0] r_sleftr__14; +reg [`BIT_WIDTH-1:0] r_sleftr__15; +reg [`BIT_WIDTH-1:0] r_sleftr__16; +reg [`BIT_WIDTH-1:0] r_sleftr__17; +reg [`BIT_WIDTH-1:0] r_sleftr__18; +reg [`BIT_WIDTH-1:0] r_sleftr__19; +reg [`BIT_WIDTH-1:0] r_sleftr__20; +reg [`BIT_WIDTH-1:0] r_sleftr__21; +reg [`BIT_WIDTH-1:0] r_sleftr__22; +reg [`BIT_WIDTH-1:0] r_sleftr__23; +reg [`BIT_WIDTH-1:0] r_sleftr__24; +reg [`BIT_WIDTH-1:0] r_sleftr__25; +reg [`BIT_WIDTH-1:0] r_sleftr__26; +reg [`BIT_WIDTH-1:0] r_sleftr__27; +reg [`BIT_WIDTH-1:0] r_sleftr__28; +reg [`BIT_WIDTH-1:0] r_sleftr__29; +reg [`BIT_WIDTH-1:0] r_sleftr__30; +reg [`BIT_WIDTH-1:0] r_sleftr__31; +reg [`BIT_WIDTH-1:0] r_sleftr__32; +reg [`BIT_WIDTH-1:0] r_sleftr__33; +reg [`BIT_WIDTH-1:0] r_sleftr__34; +reg [`BIT_WIDTH-1:0] r_sleftr__35; +reg [`BIT_WIDTH-1:0] r_sleftr__36; +reg [`BIT_WIDTH-1:0] r_sleftr__37; +reg [`BIT_WIDTH-1:0] r_sleftr__38; +reg [`BIT_WIDTH-1:0] r_sleftr__39; +reg [`BIT_WIDTH-1:0] r_sleftr__40; +reg [`BIT_WIDTH-1:0] r_sleftr__41; +reg [`BIT_WIDTH-1:0] r_sleftr__42; +reg [`BIT_WIDTH-1:0] r_sleftr__43; +reg [`BIT_WIDTH-1:0] r_sleftr__44; +reg [`BIT_WIDTH-1:0] r_sleftr__45; +reg [`BIT_WIDTH-1:0] r_sleftr__46; +reg [`BIT_WIDTH-1:0] r_sleftr__47; +reg [`BIT_WIDTH-1:0] r_sleftr__48; +reg [`BIT_WIDTH-1:0] r_sleftr__49; +reg [`BIT_WIDTH-1:0] r_sleftr__50; +reg [`BIT_WIDTH-1:0] r_sleftr__51; +reg [`BIT_WIDTH-1:0] r_sleftr__52; +reg [`BIT_WIDTH-1:0] r_sleftr__53; +reg [`BIT_WIDTH-1:0] r_sleftr__54; +reg [`BIT_WIDTH-1:0] r_sleftr__55; +reg [`BIT_WIDTH-1:0] r_sleftr__56; +reg [`BIT_WIDTH-1:0] r_sleftr__57; +reg [`BIT_WIDTH-1:0] r_sleftr__58; +reg [`BIT_WIDTH-1:0] r_sleftr__59; + + +//reg [`BIT_WIDTH-1:0] r_weight [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_weight__0; +reg [`BIT_WIDTH-1:0] r_weight__1; +reg [`BIT_WIDTH-1:0] r_weight__2; +reg [`BIT_WIDTH-1:0] r_weight__3; +reg [`BIT_WIDTH-1:0] r_weight__4; +reg [`BIT_WIDTH-1:0] r_weight__5; +reg [`BIT_WIDTH-1:0] r_weight__6; +reg [`BIT_WIDTH-1:0] r_weight__7; +reg [`BIT_WIDTH-1:0] r_weight__8; +reg [`BIT_WIDTH-1:0] r_weight__9; +reg [`BIT_WIDTH-1:0] r_weight__10; +reg [`BIT_WIDTH-1:0] r_weight__11; +reg [`BIT_WIDTH-1:0] r_weight__12; +reg [`BIT_WIDTH-1:0] r_weight__13; +reg [`BIT_WIDTH-1:0] r_weight__14; +reg [`BIT_WIDTH-1:0] r_weight__15; +reg [`BIT_WIDTH-1:0] r_weight__16; +reg [`BIT_WIDTH-1:0] r_weight__17; +reg [`BIT_WIDTH-1:0] r_weight__18; +reg [`BIT_WIDTH-1:0] r_weight__19; +reg [`BIT_WIDTH-1:0] r_weight__20; +reg [`BIT_WIDTH-1:0] r_weight__21; +reg [`BIT_WIDTH-1:0] r_weight__22; +reg [`BIT_WIDTH-1:0] r_weight__23; +reg [`BIT_WIDTH-1:0] r_weight__24; +reg [`BIT_WIDTH-1:0] r_weight__25; +reg [`BIT_WIDTH-1:0] r_weight__26; +reg [`BIT_WIDTH-1:0] r_weight__27; +reg [`BIT_WIDTH-1:0] r_weight__28; +reg [`BIT_WIDTH-1:0] r_weight__29; +reg [`BIT_WIDTH-1:0] r_weight__30; +reg [`BIT_WIDTH-1:0] r_weight__31; +reg [`BIT_WIDTH-1:0] r_weight__32; +reg [`BIT_WIDTH-1:0] r_weight__33; +reg [`BIT_WIDTH-1:0] r_weight__34; +reg [`BIT_WIDTH-1:0] r_weight__35; +reg [`BIT_WIDTH-1:0] r_weight__36; +reg [`BIT_WIDTH-1:0] r_weight__37; +reg [`BIT_WIDTH-1:0] r_weight__38; +reg [`BIT_WIDTH-1:0] r_weight__39; +reg [`BIT_WIDTH-1:0] r_weight__40; +reg [`BIT_WIDTH-1:0] r_weight__41; +reg [`BIT_WIDTH-1:0] r_weight__42; +reg [`BIT_WIDTH-1:0] r_weight__43; +reg [`BIT_WIDTH-1:0] r_weight__44; +reg [`BIT_WIDTH-1:0] r_weight__45; +reg [`BIT_WIDTH-1:0] r_weight__46; +reg [`BIT_WIDTH-1:0] r_weight__47; +reg [`BIT_WIDTH-1:0] r_weight__48; +reg [`BIT_WIDTH-1:0] r_weight__49; +reg [`BIT_WIDTH-1:0] r_weight__50; +reg [`BIT_WIDTH-1:0] r_weight__51; +reg [`BIT_WIDTH-1:0] r_weight__52; +reg [`BIT_WIDTH-1:0] r_weight__53; +reg [`BIT_WIDTH-1:0] r_weight__54; +reg [`BIT_WIDTH-1:0] r_weight__55; +reg [`BIT_WIDTH-1:0] r_weight__56; +reg [`BIT_WIDTH-1:0] r_weight__57; +reg [`BIT_WIDTH-1:0] r_weight__58; +reg [`BIT_WIDTH-1:0] r_weight__59; + +//reg [`LAYER_WIDTH-1:0] r_layer [TOTAL_LATENCY - 1:0]; + +reg [`LAYER_WIDTH-1:0] r_layer__0; +reg [`LAYER_WIDTH-1:0] r_layer__1; +reg [`LAYER_WIDTH-1:0] r_layer__2; +reg [`LAYER_WIDTH-1:0] r_layer__3; +reg [`LAYER_WIDTH-1:0] r_layer__4; +reg [`LAYER_WIDTH-1:0] r_layer__5; +reg [`LAYER_WIDTH-1:0] r_layer__6; +reg [`LAYER_WIDTH-1:0] r_layer__7; +reg [`LAYER_WIDTH-1:0] r_layer__8; +reg [`LAYER_WIDTH-1:0] r_layer__9; +reg [`LAYER_WIDTH-1:0] r_layer__10; +reg [`LAYER_WIDTH-1:0] r_layer__11; +reg [`LAYER_WIDTH-1:0] r_layer__12; +reg [`LAYER_WIDTH-1:0] r_layer__13; +reg [`LAYER_WIDTH-1:0] r_layer__14; +reg [`LAYER_WIDTH-1:0] r_layer__15; +reg [`LAYER_WIDTH-1:0] r_layer__16; +reg [`LAYER_WIDTH-1:0] r_layer__17; +reg [`LAYER_WIDTH-1:0] r_layer__18; +reg [`LAYER_WIDTH-1:0] r_layer__19; +reg [`LAYER_WIDTH-1:0] r_layer__20; +reg [`LAYER_WIDTH-1:0] r_layer__21; +reg [`LAYER_WIDTH-1:0] r_layer__22; +reg [`LAYER_WIDTH-1:0] r_layer__23; +reg [`LAYER_WIDTH-1:0] r_layer__24; +reg [`LAYER_WIDTH-1:0] r_layer__25; +reg [`LAYER_WIDTH-1:0] r_layer__26; +reg [`LAYER_WIDTH-1:0] r_layer__27; +reg [`LAYER_WIDTH-1:0] r_layer__28; +reg [`LAYER_WIDTH-1:0] r_layer__29; +reg [`LAYER_WIDTH-1:0] r_layer__30; +reg [`LAYER_WIDTH-1:0] r_layer__31; +reg [`LAYER_WIDTH-1:0] r_layer__32; +reg [`LAYER_WIDTH-1:0] r_layer__33; +reg [`LAYER_WIDTH-1:0] r_layer__34; +reg [`LAYER_WIDTH-1:0] r_layer__35; +reg [`LAYER_WIDTH-1:0] r_layer__36; +reg [`LAYER_WIDTH-1:0] r_layer__37; +reg [`LAYER_WIDTH-1:0] r_layer__38; +reg [`LAYER_WIDTH-1:0] r_layer__39; +reg [`LAYER_WIDTH-1:0] r_layer__40; +reg [`LAYER_WIDTH-1:0] r_layer__41; +reg [`LAYER_WIDTH-1:0] r_layer__42; +reg [`LAYER_WIDTH-1:0] r_layer__43; +reg [`LAYER_WIDTH-1:0] r_layer__44; +reg [`LAYER_WIDTH-1:0] r_layer__45; +reg [`LAYER_WIDTH-1:0] r_layer__46; +reg [`LAYER_WIDTH-1:0] r_layer__47; +reg [`LAYER_WIDTH-1:0] r_layer__48; +reg [`LAYER_WIDTH-1:0] r_layer__49; +reg [`LAYER_WIDTH-1:0] r_layer__50; +reg [`LAYER_WIDTH-1:0] r_layer__51; +reg [`LAYER_WIDTH-1:0] r_layer__52; +reg [`LAYER_WIDTH-1:0] r_layer__53; +reg [`LAYER_WIDTH-1:0] r_layer__54; +reg [`LAYER_WIDTH-1:0] r_layer__55; +reg [`LAYER_WIDTH-1:0] r_layer__56; +reg [`LAYER_WIDTH-1:0] r_layer__57; +reg [`LAYER_WIDTH-1:0] r_layer__58; +reg [`LAYER_WIDTH-1:0] r_layer__59; + +//reg r_dead [TOTAL_LATENCY - 1:0]; + +reg r_dead__0; +reg r_dead__1; +reg r_dead__2; +reg r_dead__3; +reg r_dead__4; +reg r_dead__5; +reg r_dead__6; +reg r_dead__7; +reg r_dead__8; +reg r_dead__9; +reg r_dead__10; +reg r_dead__11; +reg r_dead__12; +reg r_dead__13; +reg r_dead__14; +reg r_dead__15; +reg r_dead__16; +reg r_dead__17; +reg r_dead__18; +reg r_dead__19; +reg r_dead__20; +reg r_dead__21; +reg r_dead__22; +reg r_dead__23; +reg r_dead__24; +reg r_dead__25; +reg r_dead__26; +reg r_dead__27; +reg r_dead__28; +reg r_dead__29; +reg r_dead__30; +reg r_dead__31; +reg r_dead__32; +reg r_dead__33; +reg r_dead__34; +reg r_dead__35; +reg r_dead__36; +reg r_dead__37; +reg r_dead__38; +reg r_dead__39; +reg r_dead__40; +reg r_dead__41; +reg r_dead__42; +reg r_dead__43; +reg r_dead__44; +reg r_dead__45; +reg r_dead__46; +reg r_dead__47; +reg r_dead__48; +reg r_dead__49; +reg r_dead__50; +reg r_dead__51; +reg r_dead__52; +reg r_dead__53; +reg r_dead__54; +reg r_dead__55; +reg r_dead__56; +reg r_dead__57; +reg r_dead__58; +reg r_dead__59; + +//reg r_hit [TOTAL_LATENCY - 1:0]; + +reg r_hit__0; +reg r_hit__1; +reg r_hit__2; +reg r_hit__3; +reg r_hit__4; +reg r_hit__5; +reg r_hit__6; +reg r_hit__7; +reg r_hit__8; +reg r_hit__9; +reg r_hit__10; +reg r_hit__11; +reg r_hit__12; +reg r_hit__13; +reg r_hit__14; +reg r_hit__15; +reg r_hit__16; +reg r_hit__17; +reg r_hit__18; +reg r_hit__19; +reg r_hit__20; +reg r_hit__21; +reg r_hit__22; +reg r_hit__23; +reg r_hit__24; +reg r_hit__25; +reg r_hit__26; +reg r_hit__27; +reg r_hit__28; +reg r_hit__29; +reg r_hit__30; +reg r_hit__31; +reg r_hit__32; +reg r_hit__33; +reg r_hit__34; +reg r_hit__35; +reg r_hit__36; +reg r_hit__37; +reg r_hit__38; +reg r_hit__39; +reg r_hit__40; +reg r_hit__41; +reg r_hit__42; +reg r_hit__43; +reg r_hit__44; +reg r_hit__45; +reg r_hit__46; +reg r_hit__47; +reg r_hit__48; +reg r_hit__49; +reg r_hit__50; +reg r_hit__51; +reg r_hit__52; +reg r_hit__53; +reg r_hit__54; +reg r_hit__55; +reg r_hit__56; +reg r_hit__57; +reg r_hit__58; +reg r_hit__59; + +//reg [`BIT_WIDTH-1:0] r_diff[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_diff__0; +reg [`BIT_WIDTH-1:0] r_diff__1; +reg [`BIT_WIDTH-1:0] r_diff__2; +reg [`BIT_WIDTH-1:0] r_diff__3; +reg [`BIT_WIDTH-1:0] r_diff__4; +reg [`BIT_WIDTH-1:0] r_diff__5; +reg [`BIT_WIDTH-1:0] r_diff__6; +reg [`BIT_WIDTH-1:0] r_diff__7; +reg [`BIT_WIDTH-1:0] r_diff__8; +reg [`BIT_WIDTH-1:0] r_diff__9; +reg [`BIT_WIDTH-1:0] r_diff__10; +reg [`BIT_WIDTH-1:0] r_diff__11; +reg [`BIT_WIDTH-1:0] r_diff__12; +reg [`BIT_WIDTH-1:0] r_diff__13; +reg [`BIT_WIDTH-1:0] r_diff__14; +reg [`BIT_WIDTH-1:0] r_diff__15; +reg [`BIT_WIDTH-1:0] r_diff__16; +reg [`BIT_WIDTH-1:0] r_diff__17; +reg [`BIT_WIDTH-1:0] r_diff__18; +reg [`BIT_WIDTH-1:0] r_diff__19; +reg [`BIT_WIDTH-1:0] r_diff__20; +reg [`BIT_WIDTH-1:0] r_diff__21; +reg [`BIT_WIDTH-1:0] r_diff__22; +reg [`BIT_WIDTH-1:0] r_diff__23; +reg [`BIT_WIDTH-1:0] r_diff__24; +reg [`BIT_WIDTH-1:0] r_diff__25; +reg [`BIT_WIDTH-1:0] r_diff__26; +reg [`BIT_WIDTH-1:0] r_diff__27; +reg [`BIT_WIDTH-1:0] r_diff__28; +reg [`BIT_WIDTH-1:0] r_diff__29; +reg [`BIT_WIDTH-1:0] r_diff__30; +reg [`BIT_WIDTH-1:0] r_diff__31; +reg [`BIT_WIDTH-1:0] r_diff__32; +reg [`BIT_WIDTH-1:0] r_diff__33; +reg [`BIT_WIDTH-1:0] r_diff__34; +reg [`BIT_WIDTH-1:0] r_diff__35; +reg [`BIT_WIDTH-1:0] r_diff__36; +reg [`BIT_WIDTH-1:0] r_diff__37; +reg [`BIT_WIDTH-1:0] r_diff__38; +reg [`BIT_WIDTH-1:0] r_diff__39; +reg [`BIT_WIDTH-1:0] r_diff__40; +reg [`BIT_WIDTH-1:0] r_diff__41; +reg [`BIT_WIDTH-1:0] r_diff__42; +reg [`BIT_WIDTH-1:0] r_diff__43; +reg [`BIT_WIDTH-1:0] r_diff__44; +reg [`BIT_WIDTH-1:0] r_diff__45; +reg [`BIT_WIDTH-1:0] r_diff__46; +reg [`BIT_WIDTH-1:0] r_diff__47; +reg [`BIT_WIDTH-1:0] r_diff__48; +reg [`BIT_WIDTH-1:0] r_diff__49; +reg [`BIT_WIDTH-1:0] r_diff__50; +reg [`BIT_WIDTH-1:0] r_diff__51; +reg [`BIT_WIDTH-1:0] r_diff__52; +reg [`BIT_WIDTH-1:0] r_diff__53; +reg [`BIT_WIDTH-1:0] r_diff__54; +reg [`BIT_WIDTH-1:0] r_diff__55; +reg [`BIT_WIDTH-1:0] r_diff__56; +reg [`BIT_WIDTH-1:0] r_diff__57; +reg [`BIT_WIDTH-1:0] r_diff__58; +reg [`BIT_WIDTH-1:0] r_diff__59; + +//reg [`BIT_WIDTH-1:0] r_dl_b[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_dl_b__0; +reg [`BIT_WIDTH-1:0] r_dl_b__1; +reg [`BIT_WIDTH-1:0] r_dl_b__2; +reg [`BIT_WIDTH-1:0] r_dl_b__3; +reg [`BIT_WIDTH-1:0] r_dl_b__4; +reg [`BIT_WIDTH-1:0] r_dl_b__5; +reg [`BIT_WIDTH-1:0] r_dl_b__6; +reg [`BIT_WIDTH-1:0] r_dl_b__7; +reg [`BIT_WIDTH-1:0] r_dl_b__8; +reg [`BIT_WIDTH-1:0] r_dl_b__9; +reg [`BIT_WIDTH-1:0] r_dl_b__10; +reg [`BIT_WIDTH-1:0] r_dl_b__11; +reg [`BIT_WIDTH-1:0] r_dl_b__12; +reg [`BIT_WIDTH-1:0] r_dl_b__13; +reg [`BIT_WIDTH-1:0] r_dl_b__14; +reg [`BIT_WIDTH-1:0] r_dl_b__15; +reg [`BIT_WIDTH-1:0] r_dl_b__16; +reg [`BIT_WIDTH-1:0] r_dl_b__17; +reg [`BIT_WIDTH-1:0] r_dl_b__18; +reg [`BIT_WIDTH-1:0] r_dl_b__19; +reg [`BIT_WIDTH-1:0] r_dl_b__20; +reg [`BIT_WIDTH-1:0] r_dl_b__21; +reg [`BIT_WIDTH-1:0] r_dl_b__22; +reg [`BIT_WIDTH-1:0] r_dl_b__23; +reg [`BIT_WIDTH-1:0] r_dl_b__24; +reg [`BIT_WIDTH-1:0] r_dl_b__25; +reg [`BIT_WIDTH-1:0] r_dl_b__26; +reg [`BIT_WIDTH-1:0] r_dl_b__27; +reg [`BIT_WIDTH-1:0] r_dl_b__28; +reg [`BIT_WIDTH-1:0] r_dl_b__29; +reg [`BIT_WIDTH-1:0] r_dl_b__30; +reg [`BIT_WIDTH-1:0] r_dl_b__31; +reg [`BIT_WIDTH-1:0] r_dl_b__32; +reg [`BIT_WIDTH-1:0] r_dl_b__33; +reg [`BIT_WIDTH-1:0] r_dl_b__34; +reg [`BIT_WIDTH-1:0] r_dl_b__35; +reg [`BIT_WIDTH-1:0] r_dl_b__36; +reg [`BIT_WIDTH-1:0] r_dl_b__37; +reg [`BIT_WIDTH-1:0] r_dl_b__38; +reg [`BIT_WIDTH-1:0] r_dl_b__39; +reg [`BIT_WIDTH-1:0] r_dl_b__40; +reg [`BIT_WIDTH-1:0] r_dl_b__41; +reg [`BIT_WIDTH-1:0] r_dl_b__42; +reg [`BIT_WIDTH-1:0] r_dl_b__43; +reg [`BIT_WIDTH-1:0] r_dl_b__44; +reg [`BIT_WIDTH-1:0] r_dl_b__45; +reg [`BIT_WIDTH-1:0] r_dl_b__46; +reg [`BIT_WIDTH-1:0] r_dl_b__47; +reg [`BIT_WIDTH-1:0] r_dl_b__48; +reg [`BIT_WIDTH-1:0] r_dl_b__49; +reg [`BIT_WIDTH-1:0] r_dl_b__50; +reg [`BIT_WIDTH-1:0] r_dl_b__51; +reg [`BIT_WIDTH-1:0] r_dl_b__52; +reg [`BIT_WIDTH-1:0] r_dl_b__53; +reg [`BIT_WIDTH-1:0] r_dl_b__54; +reg [`BIT_WIDTH-1:0] r_dl_b__55; +reg [`BIT_WIDTH-1:0] r_dl_b__56; +reg [`BIT_WIDTH-1:0] r_dl_b__57; +reg [`BIT_WIDTH-1:0] r_dl_b__58; +reg [`BIT_WIDTH-1:0] r_dl_b__59; + +//reg [2*`BIT_WIDTH-1:0] r_numer[TOTAL_LATENCY - 1:0]; + +reg [2*`BIT_WIDTH-1:0] r_numer__0; +reg [2*`BIT_WIDTH-1:0] r_numer__1; +reg [2*`BIT_WIDTH-1:0] r_numer__2; +reg [2*`BIT_WIDTH-1:0] r_numer__3; +reg [2*`BIT_WIDTH-1:0] r_numer__4; +reg [2*`BIT_WIDTH-1:0] r_numer__5; +reg [2*`BIT_WIDTH-1:0] r_numer__6; +reg [2*`BIT_WIDTH-1:0] r_numer__7; +reg [2*`BIT_WIDTH-1:0] r_numer__8; +reg [2*`BIT_WIDTH-1:0] r_numer__9; +reg [2*`BIT_WIDTH-1:0] r_numer__10; +reg [2*`BIT_WIDTH-1:0] r_numer__11; +reg [2*`BIT_WIDTH-1:0] r_numer__12; +reg [2*`BIT_WIDTH-1:0] r_numer__13; +reg [2*`BIT_WIDTH-1:0] r_numer__14; +reg [2*`BIT_WIDTH-1:0] r_numer__15; +reg [2*`BIT_WIDTH-1:0] r_numer__16; +reg [2*`BIT_WIDTH-1:0] r_numer__17; +reg [2*`BIT_WIDTH-1:0] r_numer__18; +reg [2*`BIT_WIDTH-1:0] r_numer__19; +reg [2*`BIT_WIDTH-1:0] r_numer__20; +reg [2*`BIT_WIDTH-1:0] r_numer__21; +reg [2*`BIT_WIDTH-1:0] r_numer__22; +reg [2*`BIT_WIDTH-1:0] r_numer__23; +reg [2*`BIT_WIDTH-1:0] r_numer__24; +reg [2*`BIT_WIDTH-1:0] r_numer__25; +reg [2*`BIT_WIDTH-1:0] r_numer__26; +reg [2*`BIT_WIDTH-1:0] r_numer__27; +reg [2*`BIT_WIDTH-1:0] r_numer__28; +reg [2*`BIT_WIDTH-1:0] r_numer__29; +reg [2*`BIT_WIDTH-1:0] r_numer__30; +reg [2*`BIT_WIDTH-1:0] r_numer__31; +reg [2*`BIT_WIDTH-1:0] r_numer__32; +reg [2*`BIT_WIDTH-1:0] r_numer__33; +reg [2*`BIT_WIDTH-1:0] r_numer__34; +reg [2*`BIT_WIDTH-1:0] r_numer__35; +reg [2*`BIT_WIDTH-1:0] r_numer__36; +reg [2*`BIT_WIDTH-1:0] r_numer__37; +reg [2*`BIT_WIDTH-1:0] r_numer__38; +reg [2*`BIT_WIDTH-1:0] r_numer__39; +reg [2*`BIT_WIDTH-1:0] r_numer__40; +reg [2*`BIT_WIDTH-1:0] r_numer__41; +reg [2*`BIT_WIDTH-1:0] r_numer__42; +reg [2*`BIT_WIDTH-1:0] r_numer__43; +reg [2*`BIT_WIDTH-1:0] r_numer__44; +reg [2*`BIT_WIDTH-1:0] r_numer__45; +reg [2*`BIT_WIDTH-1:0] r_numer__46; +reg [2*`BIT_WIDTH-1:0] r_numer__47; +reg [2*`BIT_WIDTH-1:0] r_numer__48; +reg [2*`BIT_WIDTH-1:0] r_numer__49; +reg [2*`BIT_WIDTH-1:0] r_numer__50; +reg [2*`BIT_WIDTH-1:0] r_numer__51; +reg [2*`BIT_WIDTH-1:0] r_numer__52; +reg [2*`BIT_WIDTH-1:0] r_numer__53; +reg [2*`BIT_WIDTH-1:0] r_numer__54; +reg [2*`BIT_WIDTH-1:0] r_numer__55; +reg [2*`BIT_WIDTH-1:0] r_numer__56; +reg [2*`BIT_WIDTH-1:0] r_numer__57; +reg [2*`BIT_WIDTH-1:0] r_numer__58; +reg [2*`BIT_WIDTH-1:0] r_numer__59; + +//reg [`BIT_WIDTH-1:0] r_z1[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z1__0; +reg [`BIT_WIDTH-1:0] r_z1__1; +reg [`BIT_WIDTH-1:0] r_z1__2; +reg [`BIT_WIDTH-1:0] r_z1__3; +reg [`BIT_WIDTH-1:0] r_z1__4; +reg [`BIT_WIDTH-1:0] r_z1__5; +reg [`BIT_WIDTH-1:0] r_z1__6; +reg [`BIT_WIDTH-1:0] r_z1__7; +reg [`BIT_WIDTH-1:0] r_z1__8; +reg [`BIT_WIDTH-1:0] r_z1__9; +reg [`BIT_WIDTH-1:0] r_z1__10; +reg [`BIT_WIDTH-1:0] r_z1__11; +reg [`BIT_WIDTH-1:0] r_z1__12; +reg [`BIT_WIDTH-1:0] r_z1__13; +reg [`BIT_WIDTH-1:0] r_z1__14; +reg [`BIT_WIDTH-1:0] r_z1__15; +reg [`BIT_WIDTH-1:0] r_z1__16; +reg [`BIT_WIDTH-1:0] r_z1__17; +reg [`BIT_WIDTH-1:0] r_z1__18; +reg [`BIT_WIDTH-1:0] r_z1__19; +reg [`BIT_WIDTH-1:0] r_z1__20; +reg [`BIT_WIDTH-1:0] r_z1__21; +reg [`BIT_WIDTH-1:0] r_z1__22; +reg [`BIT_WIDTH-1:0] r_z1__23; +reg [`BIT_WIDTH-1:0] r_z1__24; +reg [`BIT_WIDTH-1:0] r_z1__25; +reg [`BIT_WIDTH-1:0] r_z1__26; +reg [`BIT_WIDTH-1:0] r_z1__27; +reg [`BIT_WIDTH-1:0] r_z1__28; +reg [`BIT_WIDTH-1:0] r_z1__29; +reg [`BIT_WIDTH-1:0] r_z1__30; +reg [`BIT_WIDTH-1:0] r_z1__31; +reg [`BIT_WIDTH-1:0] r_z1__32; +reg [`BIT_WIDTH-1:0] r_z1__33; +reg [`BIT_WIDTH-1:0] r_z1__34; +reg [`BIT_WIDTH-1:0] r_z1__35; +reg [`BIT_WIDTH-1:0] r_z1__36; +reg [`BIT_WIDTH-1:0] r_z1__37; +reg [`BIT_WIDTH-1:0] r_z1__38; +reg [`BIT_WIDTH-1:0] r_z1__39; +reg [`BIT_WIDTH-1:0] r_z1__40; +reg [`BIT_WIDTH-1:0] r_z1__41; +reg [`BIT_WIDTH-1:0] r_z1__42; +reg [`BIT_WIDTH-1:0] r_z1__43; +reg [`BIT_WIDTH-1:0] r_z1__44; +reg [`BIT_WIDTH-1:0] r_z1__45; +reg [`BIT_WIDTH-1:0] r_z1__46; +reg [`BIT_WIDTH-1:0] r_z1__47; +reg [`BIT_WIDTH-1:0] r_z1__48; +reg [`BIT_WIDTH-1:0] r_z1__49; +reg [`BIT_WIDTH-1:0] r_z1__50; +reg [`BIT_WIDTH-1:0] r_z1__51; +reg [`BIT_WIDTH-1:0] r_z1__52; +reg [`BIT_WIDTH-1:0] r_z1__53; +reg [`BIT_WIDTH-1:0] r_z1__54; +reg [`BIT_WIDTH-1:0] r_z1__55; +reg [`BIT_WIDTH-1:0] r_z1__56; +reg [`BIT_WIDTH-1:0] r_z1__57; +reg [`BIT_WIDTH-1:0] r_z1__58; +reg [`BIT_WIDTH-1:0] r_z1__59; + +//reg [`BIT_WIDTH-1:0] r_z0[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z0__0; +reg [`BIT_WIDTH-1:0] r_z0__1; +reg [`BIT_WIDTH-1:0] r_z0__2; +reg [`BIT_WIDTH-1:0] r_z0__3; +reg [`BIT_WIDTH-1:0] r_z0__4; +reg [`BIT_WIDTH-1:0] r_z0__5; +reg [`BIT_WIDTH-1:0] r_z0__6; +reg [`BIT_WIDTH-1:0] r_z0__7; +reg [`BIT_WIDTH-1:0] r_z0__8; +reg [`BIT_WIDTH-1:0] r_z0__9; +reg [`BIT_WIDTH-1:0] r_z0__10; +reg [`BIT_WIDTH-1:0] r_z0__11; +reg [`BIT_WIDTH-1:0] r_z0__12; +reg [`BIT_WIDTH-1:0] r_z0__13; +reg [`BIT_WIDTH-1:0] r_z0__14; +reg [`BIT_WIDTH-1:0] r_z0__15; +reg [`BIT_WIDTH-1:0] r_z0__16; +reg [`BIT_WIDTH-1:0] r_z0__17; +reg [`BIT_WIDTH-1:0] r_z0__18; +reg [`BIT_WIDTH-1:0] r_z0__19; +reg [`BIT_WIDTH-1:0] r_z0__20; +reg [`BIT_WIDTH-1:0] r_z0__21; +reg [`BIT_WIDTH-1:0] r_z0__22; +reg [`BIT_WIDTH-1:0] r_z0__23; +reg [`BIT_WIDTH-1:0] r_z0__24; +reg [`BIT_WIDTH-1:0] r_z0__25; +reg [`BIT_WIDTH-1:0] r_z0__26; +reg [`BIT_WIDTH-1:0] r_z0__27; +reg [`BIT_WIDTH-1:0] r_z0__28; +reg [`BIT_WIDTH-1:0] r_z0__29; +reg [`BIT_WIDTH-1:0] r_z0__30; +reg [`BIT_WIDTH-1:0] r_z0__31; +reg [`BIT_WIDTH-1:0] r_z0__32; +reg [`BIT_WIDTH-1:0] r_z0__33; +reg [`BIT_WIDTH-1:0] r_z0__34; +reg [`BIT_WIDTH-1:0] r_z0__35; +reg [`BIT_WIDTH-1:0] r_z0__36; +reg [`BIT_WIDTH-1:0] r_z0__37; +reg [`BIT_WIDTH-1:0] r_z0__38; +reg [`BIT_WIDTH-1:0] r_z0__39; +reg [`BIT_WIDTH-1:0] r_z0__40; +reg [`BIT_WIDTH-1:0] r_z0__41; +reg [`BIT_WIDTH-1:0] r_z0__42; +reg [`BIT_WIDTH-1:0] r_z0__43; +reg [`BIT_WIDTH-1:0] r_z0__44; +reg [`BIT_WIDTH-1:0] r_z0__45; +reg [`BIT_WIDTH-1:0] r_z0__46; +reg [`BIT_WIDTH-1:0] r_z0__47; +reg [`BIT_WIDTH-1:0] r_z0__48; +reg [`BIT_WIDTH-1:0] r_z0__49; +reg [`BIT_WIDTH-1:0] r_z0__50; +reg [`BIT_WIDTH-1:0] r_z0__51; +reg [`BIT_WIDTH-1:0] r_z0__52; +reg [`BIT_WIDTH-1:0] r_z0__53; +reg [`BIT_WIDTH-1:0] r_z0__54; +reg [`BIT_WIDTH-1:0] r_z0__55; +reg [`BIT_WIDTH-1:0] r_z0__56; +reg [`BIT_WIDTH-1:0] r_z0__57; +reg [`BIT_WIDTH-1:0] r_z0__58; +reg [`BIT_WIDTH-1:0] r_z0__59; +//reg [`BIT_WIDTH-1:0] r_mut[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_mut__0; +reg [`BIT_WIDTH-1:0] r_mut__1; +reg [`BIT_WIDTH-1:0] r_mut__2; +reg [`BIT_WIDTH-1:0] r_mut__3; +reg [`BIT_WIDTH-1:0] r_mut__4; +reg [`BIT_WIDTH-1:0] r_mut__5; +reg [`BIT_WIDTH-1:0] r_mut__6; +reg [`BIT_WIDTH-1:0] r_mut__7; +reg [`BIT_WIDTH-1:0] r_mut__8; +reg [`BIT_WIDTH-1:0] r_mut__9; +reg [`BIT_WIDTH-1:0] r_mut__10; +reg [`BIT_WIDTH-1:0] r_mut__11; +reg [`BIT_WIDTH-1:0] r_mut__12; +reg [`BIT_WIDTH-1:0] r_mut__13; +reg [`BIT_WIDTH-1:0] r_mut__14; +reg [`BIT_WIDTH-1:0] r_mut__15; +reg [`BIT_WIDTH-1:0] r_mut__16; +reg [`BIT_WIDTH-1:0] r_mut__17; +reg [`BIT_WIDTH-1:0] r_mut__18; +reg [`BIT_WIDTH-1:0] r_mut__19; +reg [`BIT_WIDTH-1:0] r_mut__20; +reg [`BIT_WIDTH-1:0] r_mut__21; +reg [`BIT_WIDTH-1:0] r_mut__22; +reg [`BIT_WIDTH-1:0] r_mut__23; +reg [`BIT_WIDTH-1:0] r_mut__24; +reg [`BIT_WIDTH-1:0] r_mut__25; +reg [`BIT_WIDTH-1:0] r_mut__26; +reg [`BIT_WIDTH-1:0] r_mut__27; +reg [`BIT_WIDTH-1:0] r_mut__28; +reg [`BIT_WIDTH-1:0] r_mut__29; +reg [`BIT_WIDTH-1:0] r_mut__30; +reg [`BIT_WIDTH-1:0] r_mut__31; +reg [`BIT_WIDTH-1:0] r_mut__32; +reg [`BIT_WIDTH-1:0] r_mut__33; +reg [`BIT_WIDTH-1:0] r_mut__34; +reg [`BIT_WIDTH-1:0] r_mut__35; +reg [`BIT_WIDTH-1:0] r_mut__36; +reg [`BIT_WIDTH-1:0] r_mut__37; +reg [`BIT_WIDTH-1:0] r_mut__38; +reg [`BIT_WIDTH-1:0] r_mut__39; +reg [`BIT_WIDTH-1:0] r_mut__40; +reg [`BIT_WIDTH-1:0] r_mut__41; +reg [`BIT_WIDTH-1:0] r_mut__42; +reg [`BIT_WIDTH-1:0] r_mut__43; +reg [`BIT_WIDTH-1:0] r_mut__44; +reg [`BIT_WIDTH-1:0] r_mut__45; +reg [`BIT_WIDTH-1:0] r_mut__46; +reg [`BIT_WIDTH-1:0] r_mut__47; +reg [`BIT_WIDTH-1:0] r_mut__48; +reg [`BIT_WIDTH-1:0] r_mut__49; +reg [`BIT_WIDTH-1:0] r_mut__50; +reg [`BIT_WIDTH-1:0] r_mut__51; +reg [`BIT_WIDTH-1:0] r_mut__52; +reg [`BIT_WIDTH-1:0] r_mut__53; +reg [`BIT_WIDTH-1:0] r_mut__54; +reg [`BIT_WIDTH-1:0] r_mut__55; +reg [`BIT_WIDTH-1:0] r_mut__56; +reg [`BIT_WIDTH-1:0] r_mut__57; +reg [`BIT_WIDTH-1:0] r_mut__58; +reg [`BIT_WIDTH-1:0] r_mut__59; + +wire [2*`BIT_WIDTH-1:0] sleftz_big; +wire [2*`BIT_WIDTH-1:0] sleftr_big; +wire [2*`BIT_WIDTH-1:0] sr_big; +wire [`BIT_WIDTH-1:0] remainder_div1; +wire [2*`BIT_WIDTH-1:0] quotient_div1; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +assign x_boundaryChecker = r_x__59; +assign y_boundaryChecker = r_y__59; +assign z_boundaryChecker = r_z__59; +assign ux_boundaryChecker = r_ux__59; +assign uy_boundaryChecker = r_uy__59; +assign uz_boundaryChecker = r_uz__59; +assign sz_boundaryChecker = r_sz__59; +assign sr_boundaryChecker = r_sr__59; +assign sleftz_boundaryChecker = r_sleftz__59; +assign sleftr_boundaryChecker = r_sleftr__59; +assign weight_boundaryChecker = r_weight__59; +assign layer_boundaryChecker = r_layer__59; +assign dead_boundaryChecker = r_dead__59; +assign hit_boundaryChecker = r_hit__59; + +// divider +signed_div_30 divide_u1 ( + .clock(clock), + .denom(c_uz__0), + .numer(c_numer__0), + .quotient(quotient_div1), + .remain(remainder_div1)); + +// multipliers +mult_signed_32_bc mult_u1( + .clock(clock), + .dataa(c_diff__30), + .datab(c_mut__30), + .result(sleftz_big)); + +mult_signed_32_bc mult_u2( + .clock(clock), + .dataa(maxDepth_over_maxRadius), + .datab(c_sleftz__31), + .result(sleftr_big)); + +mult_signed_32_bc mult_u3( + .clock(clock), + .dataa(maxDepth_over_maxRadius), + .datab(c_dl_b__30), + .result(sr_big)); + +// multiplexor to find z1 and z0 +always @(c_layer__0 or z1_0 or z0_0 or mut_0 or + z1_1 or z0_1 or mut_1 or + z1_2 or z0_2 or mut_2 or + z1_3 or z0_3 or mut_3 or + z1_4 or z0_4 or mut_4 or + z1_5 or z0_5 or mut_5) +begin + case(c_layer__0) + 3'b000: + begin + c_z1__0 = z1_0; + c_z0__0 = z0_0; + c_mut__0 = mut_0; + end + 3'b001: + begin + c_z1__0 = z1_1; + c_z0__0 = z0_1; + c_mut__0 = mut_1; + end + 3'b010: + begin + c_z1__0 = z1_2; + c_z0__0 = z0_2; + c_mut__0 = mut_2; + end + 3'b011: + begin + c_z1__0 = z1_3; + c_z0__0 = z0_3; + c_mut__0 = mut_3; + end + 3'b100: + begin + c_z1__0 = z1_4; + c_z0__0 = z0_4; + c_mut__0 = mut_4; + end + 3'b101: + begin + c_z1__0 = z1_5; + c_z0__0 = z0_5; + c_mut__0 = mut_5; + end + default: + begin + c_z1__0 = 0; + c_z0__0 = 0; + c_mut__0 = 0; + end + endcase +end + +// May have to change block staments on this one for odin +// set numerator +always @(c_uz__0 or c_z1__0 or c_z__0 or c_z0__0) +begin + //c_numer__0 = 63'b0; + if(c_uz__0[31] == 1'b0) + begin + c_numer__0[63:32] = c_z1__0 - c_z__0; + c_numer__0[31:0] = 32'b0; + end + else if(c_uz__0[31] == 1'b1) + begin + c_numer__0[63:32] = c_z0__0 - c_z__0; + c_numer__0[31:0] = 32'b0; + end + else + begin + c_numer__0 = 63'b0; + end +end + +// initialize uninitialized data in pipeline +always @(x_mover or y_mover or z_mover or + ux_mover or uy_mover or uz_mover or + sz_mover or sr_mover or sleftz_mover or sleftr_mover or + weight_mover or layer_mover or dead_mover) +begin + c_x__0 = x_mover; + c_y__0 = y_mover; + c_z__0 = z_mover; + c_ux__0 = ux_mover; + c_uy__0 = uy_mover; + c_uz__0 = uz_mover; + c_sz__0 = sz_mover; + c_sr__0 = sr_mover; + c_sleftz__0 = sleftz_mover; + c_sleftr__0 = sleftr_mover; + c_weight__0 = weight_mover; + c_layer__0 = layer_mover; + c_dead__0 = dead_mover; + c_hit__0 = 1'b0; + c_diff__0 = 32'b0; + c_dl_b__0 = 32'b0; +end + +// Determine new (x,y,z) coordinates +always @(r_x__0 or r_y__0 or r_z__0 or r_ux__0 or r_uy__0 or r_uz__0 or r_sz__0 or r_sr__0 or r_sleftz__0 or r_sleftr__0 or + r_weight__0 or r_layer__0 or r_dead__0 or r_hit__0 or r_diff__0 or r_dl_b__0 or r_numer__0 or r_z1__0 or r_z0__0 or r_mut__0 or + + r_x__1 or r_y__1 or r_z__1 or r_ux__1 or r_uy__1 or r_uz__1 or r_sz__1 or r_sr__1 or r_sleftz__1 or r_sleftr__1 or + r_weight__1 or r_layer__1 or r_dead__1 or r_hit__1 or r_diff__1 or r_dl_b__1 or r_numer__1 or r_z1__1 or r_z0__1 or r_mut__1 or + + r_x__2 or r_y__2 or r_z__2 or r_ux__2 or r_uy__2 or r_uz__2 or r_sz__2 or r_sr__2 or r_sleftz__2 or r_sleftr__2 or + r_weight__2 or r_layer__2 or r_dead__2 or r_hit__2 or r_diff__2 or r_dl_b__2 or r_numer__2 or r_z1__2 or r_z0__2 or r_mut__2 or + + r_x__3 or r_y__3 or r_z__3 or r_ux__3 or r_uy__3 or r_uz__3 or r_sz__3 or r_sr__3 or r_sleftz__3 or r_sleftr__3 or + r_weight__3 or r_layer__3 or r_dead__3 or r_hit__3 or r_diff__3 or r_dl_b__3 or r_numer__3 or r_z1__3 or r_z0__3 or r_mut__3 or + + r_x__4 or r_y__4 or r_z__4 or r_ux__4 or r_uy__4 or r_uz__4 or r_sz__4 or r_sr__4 or r_sleftz__4 or r_sleftr__4 or + r_weight__4 or r_layer__4 or r_dead__4 or r_hit__4 or r_diff__4 or r_dl_b__4 or r_numer__4 or r_z1__4 or r_z0__4 or r_mut__4 or + + r_x__5 or r_y__5 or r_z__5 or r_ux__5 or r_uy__5 or r_uz__5 or r_sz__5 or r_sr__5 or r_sleftz__5 or r_sleftr__5 or + r_weight__5 or r_layer__5 or r_dead__5 or r_hit__5 or r_diff__5 or r_dl_b__5 or r_numer__5 or r_z1__5 or r_z0__5 or r_mut__5 or + + r_x__6 or r_y__6 or r_z__6 or r_ux__6 or r_uy__6 or r_uz__6 or r_sz__6 or r_sr__6 or r_sleftz__6 or r_sleftr__6 or + r_weight__6 or r_layer__6 or r_dead__6 or r_hit__6 or r_diff__6 or r_dl_b__6 or r_numer__6 or r_z1__6 or r_z0__6 or r_mut__6 or + + r_x__7 or r_y__7 or r_z__7 or r_ux__7 or r_uy__7 or r_uz__7 or r_sz__7 or r_sr__7 or r_sleftz__7 or r_sleftr__7 or + r_weight__7 or r_layer__7 or r_dead__7 or r_hit__7 or r_diff__7 or r_dl_b__7 or r_numer__7 or r_z1__7 or r_z0__7 or r_mut__7 or + + r_x__8 or r_y__8 or r_z__8 or r_ux__8 or r_uy__8 or r_uz__8 or r_sz__8 or r_sr__8 or r_sleftz__8 or r_sleftr__8 or + r_weight__8 or r_layer__8 or r_dead__8 or r_hit__8 or r_diff__8 or r_dl_b__8 or r_numer__8 or r_z1__8 or r_z0__8 or r_mut__8 or + + r_x__9 or r_y__9 or r_z__9 or r_ux__9 or r_uy__9 or r_uz__9 or r_sz__9 or r_sr__9 or r_sleftz__9 or r_sleftr__9 or + r_weight__9 or r_layer__9 or r_dead__9 or r_hit__9 or r_diff__9 or r_dl_b__9 or r_numer__9 or r_z1__9 or r_z0__9 or r_mut__9 or + + r_x__10 or r_y__10 or r_z__10 or r_ux__10 or r_uy__10 or r_uz__10 or r_sz__10 or r_sr__10 or r_sleftz__10 or r_sleftr__10 or + r_weight__10 or r_layer__10 or r_dead__10 or r_hit__10 or r_diff__10 or r_dl_b__10 or r_numer__10 or r_z1__10 or r_z0__10 or r_mut__10 or + + r_x__11 or r_y__11 or r_z__11 or r_ux__11 or r_uy__11 or r_uz__11 or r_sz__11 or r_sr__11 or r_sleftz__11 or r_sleftr__11 or + r_weight__11 or r_layer__11 or r_dead__11 or r_hit__11 or r_diff__11 or r_dl_b__11 or r_numer__11 or r_z1__11 or r_z0__11 or r_mut__11 or + + r_x__12 or r_y__12 or r_z__12 or r_ux__12 or r_uy__12 or r_uz__12 or r_sz__12 or r_sr__12 or r_sleftz__12 or r_sleftr__12 or + r_weight__12 or r_layer__12 or r_dead__12 or r_hit__12 or r_diff__12 or r_dl_b__12 or r_numer__12 or r_z1__12 or r_z0__12 or r_mut__12 or + + r_x__13 or r_y__13 or r_z__13 or r_ux__13 or r_uy__13 or r_uz__13 or r_sz__13 or r_sr__13 or r_sleftz__13 or r_sleftr__13 or + r_weight__13 or r_layer__13 or r_dead__13 or r_hit__13 or r_diff__13 or r_dl_b__13 or r_numer__13 or r_z1__13 or r_z0__13 or r_mut__13 or + + r_x__14 or r_y__14 or r_z__14 or r_ux__14 or r_uy__14 or r_uz__14 or r_sz__14 or r_sr__14 or r_sleftz__14 or r_sleftr__14 or + r_weight__14 or r_layer__14 or r_dead__14 or r_hit__14 or r_diff__14 or r_dl_b__14 or r_numer__14 or r_z1__14 or r_z0__14 or r_mut__14 or + + r_x__15 or r_y__15 or r_z__15 or r_ux__15 or r_uy__15 or r_uz__15 or r_sz__15 or r_sr__15 or r_sleftz__15 or r_sleftr__15 or + r_weight__15 or r_layer__15 or r_dead__15 or r_hit__15 or r_diff__15 or r_dl_b__15 or r_numer__15 or r_z1__15 or r_z0__15 or r_mut__15 or + + r_x__16 or r_y__16 or r_z__16 or r_ux__16 or r_uy__16 or r_uz__16 or r_sz__16 or r_sr__16 or r_sleftz__16 or r_sleftr__16 or + r_weight__16 or r_layer__16 or r_dead__16 or r_hit__16 or r_diff__16 or r_dl_b__16 or r_numer__16 or r_z1__16 or r_z0__16 or r_mut__16 or + + r_x__17 or r_y__17 or r_z__17 or r_ux__17 or r_uy__17 or r_uz__17 or r_sz__17 or r_sr__17 or r_sleftz__17 or r_sleftr__17 or + r_weight__17 or r_layer__17 or r_dead__17 or r_hit__17 or r_diff__17 or r_dl_b__17 or r_numer__17 or r_z1__17 or r_z0__17 or r_mut__17 or + + r_x__18 or r_y__18 or r_z__18 or r_ux__18 or r_uy__18 or r_uz__18 or r_sz__18 or r_sr__18 or r_sleftz__18 or r_sleftr__18 or + r_weight__18 or r_layer__18 or r_dead__18 or r_hit__18 or r_diff__18 or r_dl_b__18 or r_numer__18 or r_z1__18 or r_z0__18 or r_mut__18 or + + r_x__19 or r_y__19 or r_z__19 or r_ux__19 or r_uy__19 or r_uz__19 or r_sz__19 or r_sr__19 or r_sleftz__19 or r_sleftr__19 or + r_weight__19 or r_layer__19 or r_dead__19 or r_hit__19 or r_diff__19 or r_dl_b__19 or r_numer__19 or r_z1__19 or r_z0__19 or r_mut__19 or + + r_x__20 or r_y__20 or r_z__20 or r_ux__20 or r_uy__20 or r_uz__20 or r_sz__20 or r_sr__20 or r_sleftz__20 or r_sleftr__20 or + r_weight__20 or r_layer__20 or r_dead__20 or r_hit__20 or r_diff__20 or r_dl_b__20 or r_numer__20 or r_z1__20 or r_z0__20 or r_mut__20 or + + r_x__21 or r_y__21 or r_z__21 or r_ux__21 or r_uy__21 or r_uz__21 or r_sz__21 or r_sr__21 or r_sleftz__21 or r_sleftr__21 or + r_weight__21 or r_layer__21 or r_dead__21 or r_hit__21 or r_diff__21 or r_dl_b__21 or r_numer__21 or r_z1__21 or r_z0__21 or r_mut__21 or + + r_x__22 or r_y__22 or r_z__22 or r_ux__22 or r_uy__22 or r_uz__22 or r_sz__22 or r_sr__22 or r_sleftz__22 or r_sleftr__22 or + r_weight__22 or r_layer__22 or r_dead__22 or r_hit__22 or r_diff__22 or r_dl_b__22 or r_numer__22 or r_z1__22 or r_z0__22 or r_mut__22 or + + r_x__23 or r_y__23 or r_z__23 or r_ux__23 or r_uy__23 or r_uz__23 or r_sz__23 or r_sr__23 or r_sleftz__23 or r_sleftr__23 or + r_weight__23 or r_layer__23 or r_dead__23 or r_hit__23 or r_diff__23 or r_dl_b__23 or r_numer__23 or r_z1__23 or r_z0__23 or r_mut__23 or + + r_x__24 or r_y__24 or r_z__24 or r_ux__24 or r_uy__24 or r_uz__24 or r_sz__24 or r_sr__24 or r_sleftz__24 or r_sleftr__24 or + r_weight__24 or r_layer__24 or r_dead__24 or r_hit__24 or r_diff__24 or r_dl_b__24 or r_numer__24 or r_z1__24 or r_z0__24 or r_mut__24 or + + r_x__25 or r_y__25 or r_z__25 or r_ux__25 or r_uy__25 or r_uz__25 or r_sz__25 or r_sr__25 or r_sleftz__25 or r_sleftr__25 or + r_weight__25 or r_layer__25 or r_dead__25 or r_hit__25 or r_diff__25 or r_dl_b__25 or r_numer__25 or r_z1__25 or r_z0__25 or r_mut__25 or + + r_x__26 or r_y__26 or r_z__26 or r_ux__26 or r_uy__26 or r_uz__26 or r_sz__26 or r_sr__26 or r_sleftz__26 or r_sleftr__26 or + r_weight__26 or r_layer__26 or r_dead__26 or r_hit__26 or r_diff__26 or r_dl_b__26 or r_numer__26 or r_z1__26 or r_z0__26 or r_mut__26 or + + r_x__27 or r_y__27 or r_z__27 or r_ux__27 or r_uy__27 or r_uz__27 or r_sz__27 or r_sr__27 or r_sleftz__27 or r_sleftr__27 or + r_weight__27 or r_layer__27 or r_dead__27 or r_hit__27 or r_diff__27 or r_dl_b__27 or r_numer__27 or r_z1__27 or r_z0__27 or r_mut__27 or + + r_x__28 or r_y__28 or r_z__28 or r_ux__28 or r_uy__28 or r_uz__28 or r_sz__28 or r_sr__28 or r_sleftz__28 or r_sleftr__28 or + r_weight__28 or r_layer__28 or r_dead__28 or r_hit__28 or r_diff__28 or r_dl_b__28 or r_numer__28 or r_z1__28 or r_z0__28 or r_mut__28 or + + r_x__29 or r_y__29 or r_z__29 or r_ux__29 or r_uy__29 or r_uz__29 or r_sz__29 or r_sr__29 or r_sleftz__29 or r_sleftr__29 or + r_weight__29 or r_layer__29 or r_dead__29 or r_hit__29 or r_diff__29 or r_dl_b__29 or r_numer__29 or r_z1__29 or r_z0__29 or r_mut__29 or + + r_x__30 or r_y__30 or r_z__30 or r_ux__30 or r_uy__30 or r_uz__30 or r_sz__30 or r_sr__30 or r_sleftz__30 or r_sleftr__30 or + r_weight__30 or r_layer__30 or r_dead__30 or r_hit__30 or r_diff__30 or r_dl_b__30 or r_numer__30 or r_z1__30 or r_z0__30 or r_mut__30 or + + r_x__31 or r_y__31 or r_z__31 or r_ux__31 or r_uy__31 or r_uz__31 or r_sz__31 or r_sr__31 or r_sleftz__31 or r_sleftr__31 or + r_weight__31 or r_layer__31 or r_dead__31 or r_hit__31 or r_diff__31 or r_dl_b__31 or r_numer__31 or r_z1__31 or r_z0__31 or r_mut__31 or + + r_x__32 or r_y__32 or r_z__32 or r_ux__32 or r_uy__32 or r_uz__32 or r_sz__32 or r_sr__32 or r_sleftz__32 or r_sleftr__32 or + r_weight__32 or r_layer__32 or r_dead__32 or r_hit__32 or r_diff__32 or r_dl_b__32 or r_numer__32 or r_z1__32 or r_z0__32 or r_mut__32 or + + r_x__33 or r_y__33 or r_z__33 or r_ux__33 or r_uy__33 or r_uz__33 or r_sz__33 or r_sr__33 or r_sleftz__33 or r_sleftr__33 or + r_weight__33 or r_layer__33 or r_dead__33 or r_hit__33 or r_diff__33 or r_dl_b__33 or r_numer__33 or r_z1__33 or r_z0__33 or r_mut__33 or + + r_x__34 or r_y__34 or r_z__34 or r_ux__34 or r_uy__34 or r_uz__34 or r_sz__34 or r_sr__34 or r_sleftz__34 or r_sleftr__34 or + r_weight__34 or r_layer__34 or r_dead__34 or r_hit__34 or r_diff__34 or r_dl_b__34 or r_numer__34 or r_z1__34 or r_z0__34 or r_mut__34 or + + r_x__35 or r_y__35 or r_z__35 or r_ux__35 or r_uy__35 or r_uz__35 or r_sz__35 or r_sr__35 or r_sleftz__35 or r_sleftr__35 or + r_weight__35 or r_layer__35 or r_dead__35 or r_hit__35 or r_diff__35 or r_dl_b__35 or r_numer__35 or r_z1__35 or r_z0__35 or r_mut__35 or + + r_x__36 or r_y__36 or r_z__36 or r_ux__36 or r_uy__36 or r_uz__36 or r_sz__36 or r_sr__36 or r_sleftz__36 or r_sleftr__36 or + r_weight__36 or r_layer__36 or r_dead__36 or r_hit__36 or r_diff__36 or r_dl_b__36 or r_numer__36 or r_z1__36 or r_z0__36 or r_mut__36 or + + r_x__37 or r_y__37 or r_z__37 or r_ux__37 or r_uy__37 or r_uz__37 or r_sz__37 or r_sr__37 or r_sleftz__37 or r_sleftr__37 or + r_weight__37 or r_layer__37 or r_dead__37 or r_hit__37 or r_diff__37 or r_dl_b__37 or r_numer__37 or r_z1__37 or r_z0__37 or r_mut__37 or + + r_x__38 or r_y__38 or r_z__38 or r_ux__38 or r_uy__38 or r_uz__38 or r_sz__38 or r_sr__38 or r_sleftz__38 or r_sleftr__38 or + r_weight__38 or r_layer__38 or r_dead__38 or r_hit__38 or r_diff__38 or r_dl_b__38 or r_numer__38 or r_z1__38 or r_z0__38 or r_mut__38 or + + r_x__39 or r_y__39 or r_z__39 or r_ux__39 or r_uy__39 or r_uz__39 or r_sz__39 or r_sr__39 or r_sleftz__39 or r_sleftr__39 or + r_weight__39 or r_layer__39 or r_dead__39 or r_hit__39 or r_diff__39 or r_dl_b__39 or r_numer__39 or r_z1__39 or r_z0__39 or r_mut__39 or + + r_x__40 or r_y__40 or r_z__40 or r_ux__40 or r_uy__40 or r_uz__40 or r_sz__40 or r_sr__40 or r_sleftz__40 or r_sleftr__40 or + r_weight__40 or r_layer__40 or r_dead__40 or r_hit__40 or r_diff__40 or r_dl_b__40 or r_numer__40 or r_z1__40 or r_z0__40 or r_mut__40 or + + r_x__41 or r_y__41 or r_z__41 or r_ux__41 or r_uy__41 or r_uz__41 or r_sz__41 or r_sr__41 or r_sleftz__41 or r_sleftr__41 or + r_weight__41 or r_layer__41 or r_dead__41 or r_hit__41 or r_diff__41 or r_dl_b__41 or r_numer__41 or r_z1__41 or r_z0__41 or r_mut__41 or + + r_x__42 or r_y__42 or r_z__42 or r_ux__42 or r_uy__42 or r_uz__42 or r_sz__42 or r_sr__42 or r_sleftz__42 or r_sleftr__42 or + r_weight__42 or r_layer__42 or r_dead__42 or r_hit__42 or r_diff__42 or r_dl_b__42 or r_numer__42 or r_z1__42 or r_z0__42 or r_mut__42 or + + r_x__43 or r_y__43 or r_z__43 or r_ux__43 or r_uy__43 or r_uz__43 or r_sz__43 or r_sr__43 or r_sleftz__43 or r_sleftr__43 or + r_weight__43 or r_layer__43 or r_dead__43 or r_hit__43 or r_diff__43 or r_dl_b__43 or r_numer__43 or r_z1__43 or r_z0__43 or r_mut__43 or + + r_x__44 or r_y__44 or r_z__44 or r_ux__44 or r_uy__44 or r_uz__44 or r_sz__44 or r_sr__44 or r_sleftz__44 or r_sleftr__44 or + r_weight__44 or r_layer__44 or r_dead__44 or r_hit__44 or r_diff__44 or r_dl_b__44 or r_numer__44 or r_z1__44 or r_z0__44 or r_mut__44 or + + r_x__45 or r_y__45 or r_z__45 or r_ux__45 or r_uy__45 or r_uz__45 or r_sz__45 or r_sr__45 or r_sleftz__45 or r_sleftr__45 or + r_weight__45 or r_layer__45 or r_dead__45 or r_hit__45 or r_diff__45 or r_dl_b__45 or r_numer__45 or r_z1__45 or r_z0__45 or r_mut__45 or + + r_x__46 or r_y__46 or r_z__46 or r_ux__46 or r_uy__46 or r_uz__46 or r_sz__46 or r_sr__46 or r_sleftz__46 or r_sleftr__46 or + r_weight__46 or r_layer__46 or r_dead__46 or r_hit__46 or r_diff__46 or r_dl_b__46 or r_numer__46 or r_z1__46 or r_z0__46 or r_mut__46 or + + r_x__47 or r_y__47 or r_z__47 or r_ux__47 or r_uy__47 or r_uz__47 or r_sz__47 or r_sr__47 or r_sleftz__47 or r_sleftr__47 or + r_weight__47 or r_layer__47 or r_dead__47 or r_hit__47 or r_diff__47 or r_dl_b__47 or r_numer__47 or r_z1__47 or r_z0__47 or r_mut__47 or + + r_x__48 or r_y__48 or r_z__48 or r_ux__48 or r_uy__48 or r_uz__48 or r_sz__48 or r_sr__48 or r_sleftz__48 or r_sleftr__48 or + r_weight__48 or r_layer__48 or r_dead__48 or r_hit__48 or r_diff__48 or r_dl_b__48 or r_numer__48 or r_z1__48 or r_z0__48 or r_mut__48 or + + r_x__49 or r_y__49 or r_z__49 or r_ux__49 or r_uy__49 or r_uz__49 or r_sz__49 or r_sr__49 or r_sleftz__49 or r_sleftr__49 or + r_weight__49 or r_layer__49 or r_dead__49 or r_hit__49 or r_diff__49 or r_dl_b__49 or r_numer__49 or r_z1__49 or r_z0__49 or r_mut__49 or + + r_x__50 or r_y__50 or r_z__50 or r_ux__50 or r_uy__50 or r_uz__50 or r_sz__50 or r_sr__50 or r_sleftz__50 or r_sleftr__50 or + r_weight__50 or r_layer__50 or r_dead__50 or r_hit__50 or r_diff__50 or r_dl_b__50 or r_numer__50 or r_z1__50 or r_z0__50 or r_mut__50 or + + r_x__51 or r_y__51 or r_z__51 or r_ux__51 or r_uy__51 or r_uz__51 or r_sz__51 or r_sr__51 or r_sleftz__51 or r_sleftr__51 or + r_weight__51 or r_layer__51 or r_dead__51 or r_hit__51 or r_diff__51 or r_dl_b__51 or r_numer__51 or r_z1__51 or r_z0__51 or r_mut__51 or + + r_x__52 or r_y__52 or r_z__52 or r_ux__52 or r_uy__52 or r_uz__52 or r_sz__52 or r_sr__52 or r_sleftz__52 or r_sleftr__52 or + r_weight__52 or r_layer__52 or r_dead__52 or r_hit__52 or r_diff__52 or r_dl_b__52 or r_numer__52 or r_z1__52 or r_z0__52 or r_mut__52 or + + r_x__53 or r_y__53 or r_z__53 or r_ux__53 or r_uy__53 or r_uz__53 or r_sz__53 or r_sr__53 or r_sleftz__53 or r_sleftr__53 or + r_weight__53 or r_layer__53 or r_dead__53 or r_hit__53 or r_diff__53 or r_dl_b__53 or r_numer__53 or r_z1__53 or r_z0__53 or r_mut__53 or + + r_x__54 or r_y__54 or r_z__54 or r_ux__54 or r_uy__54 or r_uz__54 or r_sz__54 or r_sr__54 or r_sleftz__54 or r_sleftr__54 or + r_weight__54 or r_layer__54 or r_dead__54 or r_hit__54 or r_diff__54 or r_dl_b__54 or r_numer__54 or r_z1__54 or r_z0__54 or r_mut__54 or + + r_x__55 or r_y__55 or r_z__55 or r_ux__55 or r_uy__55 or r_uz__55 or r_sz__55 or r_sr__55 or r_sleftz__55 or r_sleftr__55 or + r_weight__55 or r_layer__55 or r_dead__55 or r_hit__55 or r_diff__55 or r_dl_b__55 or r_numer__55 or r_z1__55 or r_z0__55 or r_mut__55 or + + r_x__56 or r_y__56 or r_z__56 or r_ux__56 or r_uy__56 or r_uz__56 or r_sz__56 or r_sr__56 or r_sleftz__56 or r_sleftr__56 or + r_weight__56 or r_layer__56 or r_dead__56 or r_hit__56 or r_diff__56 or r_dl_b__56 or r_numer__56 or r_z1__56 or r_z0__56 or r_mut__56 or + + r_x__57 or r_y__57 or r_z__57 or r_ux__57 or r_uy__57 or r_uz__57 or r_sz__57 or r_sr__57 or r_sleftz__57 or r_sleftr__57 or + r_weight__57 or r_layer__57 or r_dead__57 or r_hit__57 or r_diff__57 or r_dl_b__57 or r_numer__57 or r_z1__57 or r_z0__57 or r_mut__57 or + + r_x__58 or r_y__58 or r_z__58 or r_ux__58 or r_uy__58 or r_uz__58 or r_sz__58 or r_sr__58 or r_sleftz__58 or r_sleftr__58 or + r_weight__58 or r_layer__58 or r_dead__58 or r_hit__58 or r_diff__58 or r_dl_b__58 or r_numer__58 or r_z1__58 or r_z0__58 or r_mut__58 or + + r_x__59 or r_y__59 or r_z__59 or r_ux__59 or r_uy__59 or r_uz__59 or r_sz__59 or r_sr__59 or r_sleftz__59 or r_sleftr__59 or + r_weight__59 or r_layer__59 or r_dead__59 or r_hit__59 or r_diff__59 or r_dl_b__59 or r_numer__59 or r_z1__59 or r_z0__59 or r_mut__59 or + + sr_big or sleftz_big or sleftr_big or quotient_div1) + + // default + // setup standard pipeline +// for(i = 1; i < `TOTAL_LATENCY; i = i + 1) +// begin +// c_x[i] = r_x[i-1]; +// c_y[i] = r_y[i-1]; +// c_z[i] = r_z[i-1]; +// c_ux[i] = r_ux[i-1]; +// c_uy[i] = r_uy[i-1]; +// c_uz[i] = r_uz[i-1]; +// c_sz[i] = r_sz[i-1]; +// c_sr[i] = r_sr[i-1]; +// c_sleftz[i] = r_sleftz[i-1]; +// c_sleftr[i] = r_sleftr[i-1]; +// c_weight[i] = r_weight[i-1]; +// c_layer[i] = r_layer[i-1]; +// c_dead[i] = r_dead[i-1]; +// c_hit[i] = r_hit[i-1]; +// c_diff[i] = r_diff[i-1]; +// c_dl_b[i] = r_dl_b[i-1]; +// c_numer[i] = r_numer[i-1]; +// c_z1[i] = r_z1[i-1]; +// c_z0[i] = r_z0[i-1]; +// c_mut[i] = r_mut[i-1]; +// end + +begin + //Instatiate all 60 instances of the above for-loop + //for 1 + c_x__1 = r_x__0; + c_y__1 = r_y__0; + c_z__1 = r_z__0; + c_ux__1 = r_ux__0; + c_uy__1 = r_uy__0; + c_uz__1 = r_uz__0; + c_sz__1 = r_sz__0; + c_sr__1 = r_sr__0; + c_sleftz__1 = r_sleftz__0; + c_sleftr__1 = r_sleftr__0; + c_weight__1 = r_weight__0; + c_layer__1 = r_layer__0; + c_dead__1 = r_dead__0; + c_hit__1 = r_hit__0; + c_diff__1 = r_diff__0; + c_dl_b__1 = r_dl_b__0; + c_numer__1 = r_numer__0; + c_z1__1 = r_z1__0; + c_z0__1 = r_z0__0; + c_mut__1 = r_mut__0; + + //for 2 + c_x__2 = r_x__1; + c_y__2 = r_y__1; + c_z__2 = r_z__1; + c_ux__2 = r_ux__1; + c_uy__2 = r_uy__1; + c_uz__2 = r_uz__1; + c_sz__2 = r_sz__1; + c_sr__2 = r_sr__1; + c_sleftz__2 = r_sleftz__1; + c_sleftr__2 = r_sleftr__1; + c_weight__2 = r_weight__1; + c_layer__2 = r_layer__1; + c_dead__2 = r_dead__1; + c_hit__2 = r_hit__1; + c_diff__2 = r_diff__1; + c_dl_b__2 = r_dl_b__1; + c_numer__2 = r_numer__1; + c_z1__2 = r_z1__1; + c_z0__2 = r_z0__1; + c_mut__2 = r_mut__1; + + //for 3 + c_x__3 = r_x__2; + c_y__3 = r_y__2; + c_z__3 = r_z__2; + c_ux__3 = r_ux__2; + c_uy__3 = r_uy__2; + c_uz__3 = r_uz__2; + c_sz__3 = r_sz__2; + c_sr__3 = r_sr__2; + c_sleftz__3 = r_sleftz__2; + c_sleftr__3 = r_sleftr__2; + c_weight__3 = r_weight__2; + c_layer__3 = r_layer__2; + c_dead__3 = r_dead__2; + c_hit__3 = r_hit__2; + c_diff__3 = r_diff__2; + c_dl_b__3 = r_dl_b__2; + c_numer__3 = r_numer__2; + c_z1__3 = r_z1__2; + c_z0__3 = r_z0__2; + c_mut__3 = r_mut__2; + + //for 4 + c_x__4 = r_x__3; + c_y__4 = r_y__3; + c_z__4 = r_z__3; + c_ux__4 = r_ux__3; + c_uy__4 = r_uy__3; + c_uz__4 = r_uz__3; + c_sz__4 = r_sz__3; + c_sr__4 = r_sr__3; + c_sleftz__4 = r_sleftz__3; + c_sleftr__4 = r_sleftr__3; + c_weight__4 = r_weight__3; + c_layer__4 = r_layer__3; + c_dead__4 = r_dead__3; + c_hit__4 = r_hit__3; + c_diff__4 = r_diff__3; + c_dl_b__4 = r_dl_b__3; + c_numer__4 = r_numer__3; + c_z1__4 = r_z1__3; + c_z0__4 = r_z0__3; + c_mut__4 = r_mut__3; + + //for 5 + c_x__5 = r_x__4; + c_y__5 = r_y__4; + c_z__5 = r_z__4; + c_ux__5 = r_ux__4; + c_uy__5 = r_uy__4; + c_uz__5 = r_uz__4; + c_sz__5 = r_sz__4; + c_sr__5 = r_sr__4; + c_sleftz__5 = r_sleftz__4; + c_sleftr__5 = r_sleftr__4; + c_weight__5 = r_weight__4; + c_layer__5 = r_layer__4; + c_dead__5 = r_dead__4; + c_hit__5 = r_hit__4; + c_diff__5 = r_diff__4; + c_dl_b__5 = r_dl_b__4; + c_numer__5 = r_numer__4; + c_z1__5 = r_z1__4; + c_z0__5 = r_z0__4; + c_mut__5 = r_mut__4; + + //for 6 + c_x__6 = r_x__5; + c_y__6 = r_y__5; + c_z__6 = r_z__5; + c_ux__6 = r_ux__5; + c_uy__6 = r_uy__5; + c_uz__6 = r_uz__5; + c_sz__6 = r_sz__5; + c_sr__6 = r_sr__5; + c_sleftz__6 = r_sleftz__5; + c_sleftr__6 = r_sleftr__5; + c_weight__6 = r_weight__5; + c_layer__6 = r_layer__5; + c_dead__6 = r_dead__5; + c_hit__6 = r_hit__5; + c_diff__6 = r_diff__5; + c_dl_b__6 = r_dl_b__5; + c_numer__6 = r_numer__5; + c_z1__6 = r_z1__5; + c_z0__6 = r_z0__5; + c_mut__6 = r_mut__5; + + //for 7 + c_x__7 = r_x__6; + c_y__7 = r_y__6; + c_z__7 = r_z__6; + c_ux__7 = r_ux__6; + c_uy__7 = r_uy__6; + c_uz__7 = r_uz__6; + c_sz__7 = r_sz__6; + c_sr__7 = r_sr__6; + c_sleftz__7 = r_sleftz__6; + c_sleftr__7 = r_sleftr__6; + c_weight__7 = r_weight__6; + c_layer__7 = r_layer__6; + c_dead__7 = r_dead__6; + c_hit__7 = r_hit__6; + c_diff__7 = r_diff__6; + c_dl_b__7 = r_dl_b__6; + c_numer__7 = r_numer__6; + c_z1__7 = r_z1__6; + c_z0__7 = r_z0__6; + c_mut__7 = r_mut__6; + + //for 8 + c_x__8 = r_x__7; + c_y__8 = r_y__7; + c_z__8 = r_z__7; + c_ux__8 = r_ux__7; + c_uy__8 = r_uy__7; + c_uz__8 = r_uz__7; + c_sz__8 = r_sz__7; + c_sr__8 = r_sr__7; + c_sleftz__8 = r_sleftz__7; + c_sleftr__8 = r_sleftr__7; + c_weight__8 = r_weight__7; + c_layer__8 = r_layer__7; + c_dead__8 = r_dead__7; + c_hit__8 = r_hit__7; + c_diff__8 = r_diff__7; + c_dl_b__8 = r_dl_b__7; + c_numer__8 = r_numer__7; + c_z1__8 = r_z1__7; + c_z0__8 = r_z0__7; + c_mut__8 = r_mut__7; + + //for 9 + c_x__9 = r_x__8; + c_y__9 = r_y__8; + c_z__9 = r_z__8; + c_ux__9 = r_ux__8; + c_uy__9 = r_uy__8; + c_uz__9 = r_uz__8; + c_sz__9 = r_sz__8; + c_sr__9 = r_sr__8; + c_sleftz__9 = r_sleftz__8; + c_sleftr__9 = r_sleftr__8; + c_weight__9 = r_weight__8; + c_layer__9 = r_layer__8; + c_dead__9 = r_dead__8; + c_hit__9 = r_hit__8; + c_diff__9 = r_diff__8; + c_dl_b__9 = r_dl_b__8; + c_numer__9 = r_numer__8; + c_z1__9 = r_z1__8; + c_z0__9 = r_z0__8; + c_mut__9 = r_mut__8; + + //for 10 + c_x__10 = r_x__9; + c_y__10 = r_y__9; + c_z__10 = r_z__9; + c_ux__10 = r_ux__9; + c_uy__10 = r_uy__9; + c_uz__10 = r_uz__9; + c_sz__10 = r_sz__9; + c_sr__10 = r_sr__9; + c_sleftz__10 = r_sleftz__9; + c_sleftr__10 = r_sleftr__9; + c_weight__10 = r_weight__9; + c_layer__10 = r_layer__9; + c_dead__10 = r_dead__9; + c_hit__10 = r_hit__9; + c_diff__10 = r_diff__9; + c_dl_b__10 = r_dl_b__9; + c_numer__10 = r_numer__9; + c_z1__10 = r_z1__9; + c_z0__10 = r_z0__9; + c_mut__10 = r_mut__9; + + //for 11 + c_x__11 = r_x__10; + c_y__11 = r_y__10; + c_z__11 = r_z__10; + c_ux__11 = r_ux__10; + c_uy__11 = r_uy__10; + c_uz__11 = r_uz__10; + c_sz__11 = r_sz__10; + c_sr__11 = r_sr__10; + c_sleftz__11 = r_sleftz__10; + c_sleftr__11 = r_sleftr__10; + c_weight__11 = r_weight__10; + c_layer__11 = r_layer__10; + c_dead__11 = r_dead__10; + c_hit__11 = r_hit__10; + c_diff__11 = r_diff__10; + c_dl_b__11 = r_dl_b__10; + c_numer__11 = r_numer__10; + c_z1__11 = r_z1__10; + c_z0__11 = r_z0__10; + c_mut__11 = r_mut__10; + + //for 12 + c_x__12 = r_x__11; + c_y__12 = r_y__11; + c_z__12 = r_z__11; + c_ux__12 = r_ux__11; + c_uy__12 = r_uy__11; + c_uz__12 = r_uz__11; + c_sz__12 = r_sz__11; + c_sr__12 = r_sr__11; + c_sleftz__12 = r_sleftz__11; + c_sleftr__12 = r_sleftr__11; + c_weight__12 = r_weight__11; + c_layer__12 = r_layer__11; + c_dead__12 = r_dead__11; + c_hit__12 = r_hit__11; + c_diff__12 = r_diff__11; + c_dl_b__12 = r_dl_b__11; + c_numer__12 = r_numer__11; + c_z1__12 = r_z1__11; + c_z0__12 = r_z0__11; + c_mut__12 = r_mut__11; + + //for 13 + c_x__13 = r_x__12; + c_y__13 = r_y__12; + c_z__13 = r_z__12; + c_ux__13 = r_ux__12; + c_uy__13 = r_uy__12; + c_uz__13 = r_uz__12; + c_sz__13 = r_sz__12; + c_sr__13 = r_sr__12; + c_sleftz__13 = r_sleftz__12; + c_sleftr__13 = r_sleftr__12; + c_weight__13 = r_weight__12; + c_layer__13 = r_layer__12; + c_dead__13 = r_dead__12; + c_hit__13 = r_hit__12; + c_diff__13 = r_diff__12; + c_dl_b__13 = r_dl_b__12; + c_numer__13 = r_numer__12; + c_z1__13 = r_z1__12; + c_z0__13 = r_z0__12; + c_mut__13 = r_mut__12; + + //for 14 + c_x__14 = r_x__13; + c_y__14 = r_y__13; + c_z__14 = r_z__13; + c_ux__14 = r_ux__13; + c_uy__14 = r_uy__13; + c_uz__14 = r_uz__13; + c_sz__14 = r_sz__13; + c_sr__14 = r_sr__13; + c_sleftz__14 = r_sleftz__13; + c_sleftr__14 = r_sleftr__13; + c_weight__14 = r_weight__13; + c_layer__14 = r_layer__13; + c_dead__14 = r_dead__13; + c_hit__14 = r_hit__13; + c_diff__14 = r_diff__13; + c_dl_b__14 = r_dl_b__13; + c_numer__14 = r_numer__13; + c_z1__14 = r_z1__13; + c_z0__14 = r_z0__13; + c_mut__14 = r_mut__13; + + //for 15 + c_x__15 = r_x__14; + c_y__15 = r_y__14; + c_z__15 = r_z__14; + c_ux__15 = r_ux__14; + c_uy__15 = r_uy__14; + c_uz__15 = r_uz__14; + c_sz__15 = r_sz__14; + c_sr__15 = r_sr__14; + c_sleftz__15 = r_sleftz__14; + c_sleftr__15 = r_sleftr__14; + c_weight__15 = r_weight__14; + c_layer__15 = r_layer__14; + c_dead__15 = r_dead__14; + c_hit__15 = r_hit__14; + c_diff__15 = r_diff__14; + c_dl_b__15 = r_dl_b__14; + c_numer__15 = r_numer__14; + c_z1__15 = r_z1__14; + c_z0__15 = r_z0__14; + c_mut__15 = r_mut__14; + + //for 16 + c_x__16 = r_x__15; + c_y__16 = r_y__15; + c_z__16 = r_z__15; + c_ux__16 = r_ux__15; + c_uy__16 = r_uy__15; + c_uz__16 = r_uz__15; + c_sz__16 = r_sz__15; + c_sr__16 = r_sr__15; + c_sleftz__16 = r_sleftz__15; + c_sleftr__16 = r_sleftr__15; + c_weight__16 = r_weight__15; + c_layer__16 = r_layer__15; + c_dead__16 = r_dead__15; + c_hit__16 = r_hit__15; + c_diff__16 = r_diff__15; + c_dl_b__16 = r_dl_b__15; + c_numer__16 = r_numer__15; + c_z1__16 = r_z1__15; + c_z0__16 = r_z0__15; + c_mut__16 = r_mut__15; + + //for 17 + c_x__17 = r_x__16; + c_y__17 = r_y__16; + c_z__17 = r_z__16; + c_ux__17 = r_ux__16; + c_uy__17 = r_uy__16; + c_uz__17 = r_uz__16; + c_sz__17 = r_sz__16; + c_sr__17 = r_sr__16; + c_sleftz__17 = r_sleftz__16; + c_sleftr__17 = r_sleftr__16; + c_weight__17 = r_weight__16; + c_layer__17 = r_layer__16; + c_dead__17 = r_dead__16; + c_hit__17 = r_hit__16; + c_diff__17 = r_diff__16; + c_dl_b__17 = r_dl_b__16; + c_numer__17 = r_numer__16; + c_z1__17 = r_z1__16; + c_z0__17 = r_z0__16; + c_mut__17 = r_mut__16; + + //for 18 + c_x__18 = r_x__17; + c_y__18 = r_y__17; + c_z__18 = r_z__17; + c_ux__18 = r_ux__17; + c_uy__18 = r_uy__17; + c_uz__18 = r_uz__17; + c_sz__18 = r_sz__17; + c_sr__18 = r_sr__17; + c_sleftz__18 = r_sleftz__17; + c_sleftr__18 = r_sleftr__17; + c_weight__18 = r_weight__17; + c_layer__18 = r_layer__17; + c_dead__18 = r_dead__17; + c_hit__18 = r_hit__17; + c_diff__18 = r_diff__17; + c_dl_b__18 = r_dl_b__17; + c_numer__18 = r_numer__17; + c_z1__18 = r_z1__17; + c_z0__18 = r_z0__17; + c_mut__18 = r_mut__17; + + //for 19 + c_x__19 = r_x__18; + c_y__19 = r_y__18; + c_z__19 = r_z__18; + c_ux__19 = r_ux__18; + c_uy__19 = r_uy__18; + c_uz__19 = r_uz__18; + c_sz__19 = r_sz__18; + c_sr__19 = r_sr__18; + c_sleftz__19 = r_sleftz__18; + c_sleftr__19 = r_sleftr__18; + c_weight__19 = r_weight__18; + c_layer__19 = r_layer__18; + c_dead__19 = r_dead__18; + c_hit__19 = r_hit__18; + c_diff__19 = r_diff__18; + c_dl_b__19 = r_dl_b__18; + c_numer__19 = r_numer__18; + c_z1__19 = r_z1__18; + c_z0__19 = r_z0__18; + c_mut__19 = r_mut__18; + + //for 20 + c_x__20 = r_x__19; + c_y__20 = r_y__19; + c_z__20 = r_z__19; + c_ux__20 = r_ux__19; + c_uy__20 = r_uy__19; + c_uz__20 = r_uz__19; + c_sz__20 = r_sz__19; + c_sr__20 = r_sr__19; + c_sleftz__20 = r_sleftz__19; + c_sleftr__20 = r_sleftr__19; + c_weight__20 = r_weight__19; + c_layer__20 = r_layer__19; + c_dead__20 = r_dead__19; + c_hit__20 = r_hit__19; + c_diff__20 = r_diff__19; + c_dl_b__20 = r_dl_b__19; + c_numer__20 = r_numer__19; + c_z1__20 = r_z1__19; + c_z0__20 = r_z0__19; + c_mut__20 = r_mut__19; + + + //for 21 + c_x__21 = r_x__20; + c_y__21 = r_y__20; + c_z__21 = r_z__20; + c_ux__21 = r_ux__20; + c_uy__21 = r_uy__20; + c_uz__21 = r_uz__20; + c_sz__21 = r_sz__20; + c_sr__21 = r_sr__20; + c_sleftz__21 = r_sleftz__20; + c_sleftr__21 = r_sleftr__20; + c_weight__21 = r_weight__20; + c_layer__21 = r_layer__20; + c_dead__21 = r_dead__20; + c_hit__21 = r_hit__20; + c_diff__21 = r_diff__20; + c_dl_b__21 = r_dl_b__20; + c_numer__21 = r_numer__20; + c_z1__21 = r_z1__20; + c_z0__21 = r_z0__20; + c_mut__21 = r_mut__20; + + //for 22 + c_x__22 = r_x__21; + c_y__22 = r_y__21; + c_z__22 = r_z__21; + c_ux__22 = r_ux__21; + c_uy__22 = r_uy__21; + c_uz__22 = r_uz__21; + c_sz__22 = r_sz__21; + c_sr__22 = r_sr__21; + c_sleftz__22 = r_sleftz__21; + c_sleftr__22 = r_sleftr__21; + c_weight__22 = r_weight__21; + c_layer__22 = r_layer__21; + c_dead__22 = r_dead__21; + c_hit__22 = r_hit__21; + c_diff__22 = r_diff__21; + c_dl_b__22 = r_dl_b__21; + c_numer__22 = r_numer__21; + c_z1__22 = r_z1__21; + c_z0__22 = r_z0__21; + c_mut__22 = r_mut__21; + + //for 23 + c_x__23 = r_x__22; + c_y__23 = r_y__22; + c_z__23 = r_z__22; + c_ux__23 = r_ux__22; + c_uy__23 = r_uy__22; + c_uz__23 = r_uz__22; + c_sz__23 = r_sz__22; + c_sr__23 = r_sr__22; + c_sleftz__23 = r_sleftz__22; + c_sleftr__23 = r_sleftr__22; + c_weight__23 = r_weight__22; + c_layer__23 = r_layer__22; + c_dead__23 = r_dead__22; + c_hit__23 = r_hit__22; + c_diff__23 = r_diff__22; + c_dl_b__23 = r_dl_b__22; + c_numer__23 = r_numer__22; + c_z1__23 = r_z1__22; + c_z0__23 = r_z0__22; + c_mut__23 = r_mut__22; + + //for 24 + c_x__24 = r_x__23; + c_y__24 = r_y__23; + c_z__24 = r_z__23; + c_ux__24 = r_ux__23; + c_uy__24 = r_uy__23; + c_uz__24 = r_uz__23; + c_sz__24 = r_sz__23; + c_sr__24 = r_sr__23; + c_sleftz__24 = r_sleftz__23; + c_sleftr__24 = r_sleftr__23; + c_weight__24 = r_weight__23; + c_layer__24 = r_layer__23; + c_dead__24 = r_dead__23; + c_hit__24 = r_hit__23; + c_diff__24 = r_diff__23; + c_dl_b__24 = r_dl_b__23; + c_numer__24 = r_numer__23; + c_z1__24 = r_z1__23; + c_z0__24 = r_z0__23; + c_mut__24 = r_mut__23; + + //for 25 + c_x__25 = r_x__24; + c_y__25 = r_y__24; + c_z__25 = r_z__24; + c_ux__25 = r_ux__24; + c_uy__25 = r_uy__24; + c_uz__25 = r_uz__24; + c_sz__25 = r_sz__24; + c_sr__25 = r_sr__24; + c_sleftz__25 = r_sleftz__24; + c_sleftr__25 = r_sleftr__24; + c_weight__25 = r_weight__24; + c_layer__25 = r_layer__24; + c_dead__25 = r_dead__24; + c_hit__25 = r_hit__24; + c_diff__25 = r_diff__24; + c_dl_b__25 = r_dl_b__24; + c_numer__25 = r_numer__24; + c_z1__25 = r_z1__24; + c_z0__25 = r_z0__24; + c_mut__25 = r_mut__24; + + //for 26 + c_x__26 = r_x__25; + c_y__26 = r_y__25; + c_z__26 = r_z__25; + c_ux__26 = r_ux__25; + c_uy__26 = r_uy__25; + c_uz__26 = r_uz__25; + c_sz__26 = r_sz__25; + c_sr__26 = r_sr__25; + c_sleftz__26 = r_sleftz__25; + c_sleftr__26 = r_sleftr__25; + c_weight__26 = r_weight__25; + c_layer__26 = r_layer__25; + c_dead__26 = r_dead__25; + c_hit__26 = r_hit__25; + c_diff__26 = r_diff__25; + c_dl_b__26 = r_dl_b__25; + c_numer__26 = r_numer__25; + c_z1__26 = r_z1__25; + c_z0__26 = r_z0__25; + c_mut__26 = r_mut__25; + + //for 27 + c_x__27 = r_x__26; + c_y__27 = r_y__26; + c_z__27 = r_z__26; + c_ux__27 = r_ux__26; + c_uy__27 = r_uy__26; + c_uz__27 = r_uz__26; + c_sz__27 = r_sz__26; + c_sr__27 = r_sr__26; + c_sleftz__27 = r_sleftz__26; + c_sleftr__27 = r_sleftr__26; + c_weight__27 = r_weight__26; + c_layer__27 = r_layer__26; + c_dead__27 = r_dead__26; + c_hit__27 = r_hit__26; + c_diff__27 = r_diff__26; + c_dl_b__27 = r_dl_b__26; + c_numer__27 = r_numer__26; + c_z1__27 = r_z1__26; + c_z0__27 = r_z0__26; + c_mut__27 = r_mut__26; + + //for 28 + c_x__28 = r_x__27; + c_y__28 = r_y__27; + c_z__28 = r_z__27; + c_ux__28 = r_ux__27; + c_uy__28 = r_uy__27; + c_uz__28 = r_uz__27; + c_sz__28 = r_sz__27; + c_sr__28 = r_sr__27; + c_sleftz__28 = r_sleftz__27; + c_sleftr__28 = r_sleftr__27; + c_weight__28 = r_weight__27; + c_layer__28 = r_layer__27; + c_dead__28 = r_dead__27; + c_hit__28 = r_hit__27; + c_diff__28 = r_diff__27; + c_dl_b__28 = r_dl_b__27; + c_numer__28 = r_numer__27; + c_z1__28 = r_z1__27; + c_z0__28 = r_z0__27; + c_mut__28 = r_mut__27; + + //for 29 + c_x__29 = r_x__28; + c_y__29 = r_y__28; + c_z__29 = r_z__28; + c_ux__29 = r_ux__28; + c_uy__29 = r_uy__28; + c_uz__29 = r_uz__28; + c_sz__29 = r_sz__28; + c_sr__29 = r_sr__28; + c_sleftz__29 = r_sleftz__28; + c_sleftr__29 = r_sleftr__28; + c_weight__29 = r_weight__28; + c_layer__29 = r_layer__28; + c_dead__29 = r_dead__28; + c_hit__29 = r_hit__28; + c_diff__29 = r_diff__28; + c_dl_b__29 = r_dl_b__28; + c_numer__29 = r_numer__28; + c_z1__29 = r_z1__28; + c_z0__29 = r_z0__28; + c_mut__29 = r_mut__28; + + //for 30 + c_x__30 = r_x__29; + c_y__30 = r_y__29; + c_z__30 = r_z__29; + c_ux__30 = r_ux__29; + c_uy__30 = r_uy__29; + c_uz__30 = r_uz__29; + c_sz__30 = r_sz__29; + c_sr__30 = r_sr__29; + c_sleftz__30 = r_sleftz__29; + c_sleftr__30 = r_sleftr__29; + c_weight__30 = r_weight__29; + c_layer__30 = r_layer__29; + c_dead__30 = r_dead__29; + // c_hit__30 = r_hit__29;// + // c_diff__30 = r_diff__29;// + // this value is set later, removing default - peter m + // c_dl_b__30 = r_dl_b__29;// + // this one too + c_numer__30 = r_numer__29; + c_z1__30 = r_z1__29; + c_z0__30 = r_z0__29; + c_mut__30 = r_mut__29; + + //for 31 + c_x__31 = r_x__30; + c_y__31 = r_y__30; + // c_z__31 = r_z__30;// + c_ux__31 = r_ux__30; + c_uy__31 = r_uy__30; + c_uz__31 = r_uz__30; + // c_sz__31 = r_sz__30;// + // c_sr__31 = r_sr__30;// + // c_sleftz__31 = r_sleftz__30;// + c_sleftr__31 = r_sleftr__30; + c_weight__31 = r_weight__30; + c_layer__31 = r_layer__30; + c_dead__31 = r_dead__30; + c_hit__31 = r_hit__30; + c_diff__31 = r_diff__30; + c_dl_b__31 = r_dl_b__30; + c_numer__31 = r_numer__30; + c_z1__31 = r_z1__30; + c_z0__31 = r_z0__30; + c_mut__31 = r_mut__30; + + //for 32 + c_x__32 = r_x__31; + c_y__32 = r_y__31; + c_z__32 = r_z__31; + c_ux__32 = r_ux__31; + c_uy__32 = r_uy__31; + c_uz__32 = r_uz__31; + c_sz__32 = r_sz__31; + c_sr__32 = r_sr__31; + c_sleftz__32 = r_sleftz__31; + // c_sleftr__32 = r_sleftr__31;// + c_weight__32 = r_weight__31; + c_layer__32 = r_layer__31; + c_dead__32 = r_dead__31; + c_hit__32 = r_hit__31; + c_diff__32 = r_diff__31; + c_dl_b__32 = r_dl_b__31; + c_numer__32 = r_numer__31; + c_z1__32 = r_z1__31; + c_z0__32 = r_z0__31; + c_mut__32 = r_mut__31; + + //for 33 + c_x__33 = r_x__32; + c_y__33 = r_y__32; + c_z__33 = r_z__32; + c_ux__33 = r_ux__32; + c_uy__33 = r_uy__32; + c_uz__33 = r_uz__32; + c_sz__33 = r_sz__32; + c_sr__33 = r_sr__32; + c_sleftz__33 = r_sleftz__32; + c_sleftr__33 = r_sleftr__32; + c_weight__33 = r_weight__32; + c_layer__33 = r_layer__32; + c_dead__33 = r_dead__32; + c_hit__33 = r_hit__32; + c_diff__33 = r_diff__32; + c_dl_b__33 = r_dl_b__32; + c_numer__33 = r_numer__32; + c_z1__33 = r_z1__32; + c_z0__33 = r_z0__32; + c_mut__33 = r_mut__32; + + //for 34 + c_x__34 = r_x__33; + c_y__34 = r_y__33; + c_z__34 = r_z__33; + c_ux__34 = r_ux__33; + c_uy__34 = r_uy__33; + c_uz__34 = r_uz__33; + c_sz__34 = r_sz__33; + c_sr__34 = r_sr__33; + c_sleftz__34 = r_sleftz__33; + c_sleftr__34 = r_sleftr__33; + c_weight__34 = r_weight__33; + c_layer__34 = r_layer__33; + c_dead__34 = r_dead__33; + c_hit__34 = r_hit__33; + c_diff__34 = r_diff__33; + c_dl_b__34 = r_dl_b__33; + c_numer__34 = r_numer__33; + c_z1__34 = r_z1__33; + c_z0__34 = r_z0__33; + c_mut__34 = r_mut__33; + + //for 35 + c_x__35 = r_x__34; + c_y__35 = r_y__34; + c_z__35 = r_z__34; + c_ux__35 = r_ux__34; + c_uy__35 = r_uy__34; + c_uz__35 = r_uz__34; + c_sz__35 = r_sz__34; + c_sr__35 = r_sr__34; + c_sleftz__35 = r_sleftz__34; + c_sleftr__35 = r_sleftr__34; + c_weight__35 = r_weight__34; + c_layer__35 = r_layer__34; + c_dead__35 = r_dead__34; + c_hit__35 = r_hit__34; + c_diff__35 = r_diff__34; + c_dl_b__35 = r_dl_b__34; + c_numer__35 = r_numer__34; + c_z1__35 = r_z1__34; + c_z0__35 = r_z0__34; + c_mut__35 = r_mut__34; + + //for 36 + c_x__36 = r_x__35; + c_y__36 = r_y__35; + c_z__36 = r_z__35; + c_ux__36 = r_ux__35; + c_uy__36 = r_uy__35; + c_uz__36 = r_uz__35; + c_sz__36 = r_sz__35; + c_sr__36 = r_sr__35; + c_sleftz__36 = r_sleftz__35; + c_sleftr__36 = r_sleftr__35; + c_weight__36 = r_weight__35; + c_layer__36 = r_layer__35; + c_dead__36 = r_dead__35; + c_hit__36 = r_hit__35; + c_diff__36 = r_diff__35; + c_dl_b__36 = r_dl_b__35; + c_numer__36 = r_numer__35; + c_z1__36 = r_z1__35; + c_z0__36 = r_z0__35; + c_mut__36 = r_mut__35; + + //for 37 + c_x__37 = r_x__36; + c_y__37 = r_y__36; + c_z__37 = r_z__36; + c_ux__37 = r_ux__36; + c_uy__37 = r_uy__36; + c_uz__37 = r_uz__36; + c_sz__37 = r_sz__36; + c_sr__37 = r_sr__36; + c_sleftz__37 = r_sleftz__36; + c_sleftr__37 = r_sleftr__36; + c_weight__37 = r_weight__36; + c_layer__37 = r_layer__36; + c_dead__37 = r_dead__36; + c_hit__37 = r_hit__36; + c_diff__37 = r_diff__36; + c_dl_b__37 = r_dl_b__36; + c_numer__37 = r_numer__36; + c_z1__37 = r_z1__36; + c_z0__37 = r_z0__36; + c_mut__37 = r_mut__36; + + //for 38 + c_x__38 = r_x__37; + c_y__38 = r_y__37; + c_z__38 = r_z__37; + c_ux__38 = r_ux__37; + c_uy__38 = r_uy__37; + c_uz__38 = r_uz__37; + c_sz__38 = r_sz__37; + c_sr__38 = r_sr__37; + c_sleftz__38 = r_sleftz__37; + c_sleftr__38 = r_sleftr__37; + c_weight__38 = r_weight__37; + c_layer__38 = r_layer__37; + c_dead__38 = r_dead__37; + c_hit__38 = r_hit__37; + c_diff__38 = r_diff__37; + c_dl_b__38 = r_dl_b__37; + c_numer__38 = r_numer__37; + c_z1__38 = r_z1__37; + c_z0__38 = r_z0__37; + c_mut__38 = r_mut__37; + + //for 39 + c_x__39 = r_x__38; + c_y__39 = r_y__38; + c_z__39 = r_z__38; + c_ux__39 = r_ux__38; + c_uy__39 = r_uy__38; + c_uz__39 = r_uz__38; + c_sz__39 = r_sz__38; + c_sr__39 = r_sr__38; + c_sleftz__39 = r_sleftz__38; + c_sleftr__39 = r_sleftr__38; + c_weight__39 = r_weight__38; + c_layer__39 = r_layer__38; + c_dead__39 = r_dead__38; + c_hit__39 = r_hit__38; + c_diff__39 = r_diff__38; + c_dl_b__39 = r_dl_b__38; + c_numer__39 = r_numer__38; + c_z1__39 = r_z1__38; + c_z0__39 = r_z0__38; + c_mut__39 = r_mut__38; + + //for 40 + c_x__40 = r_x__39; + c_y__40 = r_y__39; + c_z__40 = r_z__39; + c_ux__40 = r_ux__39; + c_uy__40 = r_uy__39; + c_uz__40 = r_uz__39; + c_sz__40 = r_sz__39; + c_sr__40 = r_sr__39; + c_sleftz__40 = r_sleftz__39; + c_sleftr__40 = r_sleftr__39; + c_weight__40 = r_weight__39; + c_layer__40 = r_layer__39; + c_dead__40 = r_dead__39; + c_hit__40 = r_hit__39; + c_diff__40 = r_diff__39; + c_dl_b__40 = r_dl_b__39; + c_numer__40 = r_numer__39; + c_z1__40 = r_z1__39; + c_z0__40 = r_z0__39; + c_mut__40 = r_mut__39; + + //for 41 + c_x__41 = r_x__40; + c_y__41 = r_y__40; + c_z__41 = r_z__40; + c_ux__41 = r_ux__40; + c_uy__41 = r_uy__40; + c_uz__41 = r_uz__40; + c_sz__41 = r_sz__40; + c_sr__41 = r_sr__40; + c_sleftz__41 = r_sleftz__40; + c_sleftr__41 = r_sleftr__40; + c_weight__41 = r_weight__40; + c_layer__41 = r_layer__40; + c_dead__41 = r_dead__40; + c_hit__41 = r_hit__40; + c_diff__41 = r_diff__40; + c_dl_b__41 = r_dl_b__40; + c_numer__41 = r_numer__40; + c_z1__41 = r_z1__40; + c_z0__41 = r_z0__40; + c_mut__41 = r_mut__40; + + //for 42 + c_x__42 = r_x__41; + c_y__42 = r_y__41; + c_z__42 = r_z__41; + c_ux__42 = r_ux__41; + c_uy__42 = r_uy__41; + c_uz__42 = r_uz__41; + c_sz__42 = r_sz__41; + c_sr__42 = r_sr__41; + c_sleftz__42 = r_sleftz__41; + c_sleftr__42 = r_sleftr__41; + c_weight__42 = r_weight__41; + c_layer__42 = r_layer__41; + c_dead__42 = r_dead__41; + c_hit__42 = r_hit__41; + c_diff__42 = r_diff__41; + c_dl_b__42 = r_dl_b__41; + c_numer__42 = r_numer__41; + c_z1__42 = r_z1__41; + c_z0__42 = r_z0__41; + c_mut__42 = r_mut__41; + + //for 43 + c_x__43 = r_x__42; + c_y__43 = r_y__42; + c_z__43 = r_z__42; + c_ux__43 = r_ux__42; + c_uy__43 = r_uy__42; + c_uz__43 = r_uz__42; + c_sz__43 = r_sz__42; + c_sr__43 = r_sr__42; + c_sleftz__43 = r_sleftz__42; + c_sleftr__43 = r_sleftr__42; + c_weight__43 = r_weight__42; + c_layer__43 = r_layer__42; + c_dead__43 = r_dead__42; + c_hit__43 = r_hit__42; + c_diff__43 = r_diff__42; + c_dl_b__43 = r_dl_b__42; + c_numer__43 = r_numer__42; + c_z1__43 = r_z1__42; + c_z0__43 = r_z0__42; + c_mut__43 = r_mut__42; + + //for 44 + c_x__44 = r_x__43; + c_y__44 = r_y__43; + c_z__44 = r_z__43; + c_ux__44 = r_ux__43; + c_uy__44 = r_uy__43; + c_uz__44 = r_uz__43; + c_sz__44 = r_sz__43; + c_sr__44 = r_sr__43; + c_sleftz__44 = r_sleftz__43; + c_sleftr__44 = r_sleftr__43; + c_weight__44 = r_weight__43; + c_layer__44 = r_layer__43; + c_dead__44 = r_dead__43; + c_hit__44 = r_hit__43; + c_diff__44 = r_diff__43; + c_dl_b__44 = r_dl_b__43; + c_numer__44 = r_numer__43; + c_z1__44 = r_z1__43; + c_z0__44 = r_z0__43; + c_mut__44 = r_mut__43; + + //for 45 + c_x__45 = r_x__44; + c_y__45 = r_y__44; + c_z__45 = r_z__44; + c_ux__45 = r_ux__44; + c_uy__45 = r_uy__44; + c_uz__45 = r_uz__44; + c_sz__45 = r_sz__44; + c_sr__45 = r_sr__44; + c_sleftz__45 = r_sleftz__44; + c_sleftr__45 = r_sleftr__44; + c_weight__45 = r_weight__44; + c_layer__45 = r_layer__44; + c_dead__45 = r_dead__44; + c_hit__45 = r_hit__44; + c_diff__45 = r_diff__44; + c_dl_b__45 = r_dl_b__44; + c_numer__45 = r_numer__44; + c_z1__45 = r_z1__44; + c_z0__45 = r_z0__44; + c_mut__45 = r_mut__44; + + //for 46 + c_x__46 = r_x__45; + c_y__46 = r_y__45; + c_z__46 = r_z__45; + c_ux__46 = r_ux__45; + c_uy__46 = r_uy__45; + c_uz__46 = r_uz__45; + c_sz__46 = r_sz__45; + c_sr__46 = r_sr__45; + c_sleftz__46 = r_sleftz__45; + c_sleftr__46 = r_sleftr__45; + c_weight__46 = r_weight__45; + c_layer__46 = r_layer__45; + c_dead__46 = r_dead__45; + c_hit__46 = r_hit__45; + c_diff__46 = r_diff__45; + c_dl_b__46 = r_dl_b__45; + c_numer__46 = r_numer__45; + c_z1__46 = r_z1__45; + c_z0__46 = r_z0__45; + c_mut__46 = r_mut__45; + + //for 47 + c_x__47 = r_x__46; + c_y__47 = r_y__46; + c_z__47 = r_z__46; + c_ux__47 = r_ux__46; + c_uy__47 = r_uy__46; + c_uz__47 = r_uz__46; + c_sz__47 = r_sz__46; + c_sr__47 = r_sr__46; + c_sleftz__47 = r_sleftz__46; + c_sleftr__47 = r_sleftr__46; + c_weight__47 = r_weight__46; + c_layer__47 = r_layer__46; + c_dead__47 = r_dead__46; + c_hit__47 = r_hit__46; + c_diff__47 = r_diff__46; + c_dl_b__47 = r_dl_b__46; + c_numer__47 = r_numer__46; + c_z1__47 = r_z1__46; + c_z0__47 = r_z0__46; + c_mut__47 = r_mut__46; + + //for 48 + c_x__48 = r_x__47; + c_y__48 = r_y__47; + c_z__48 = r_z__47; + c_ux__48 = r_ux__47; + c_uy__48 = r_uy__47; + c_uz__48 = r_uz__47; + c_sz__48 = r_sz__47; + c_sr__48 = r_sr__47; + c_sleftz__48 = r_sleftz__47; + c_sleftr__48 = r_sleftr__47; + c_weight__48 = r_weight__47; + c_layer__48 = r_layer__47; + c_dead__48 = r_dead__47; + c_hit__48 = r_hit__47; + c_diff__48 = r_diff__47; + c_dl_b__48 = r_dl_b__47; + c_numer__48 = r_numer__47; + c_z1__48 = r_z1__47; + c_z0__48 = r_z0__47; + c_mut__48 = r_mut__47; + + //for 49 + c_x__49 = r_x__48; + c_y__49 = r_y__48; + c_z__49 = r_z__48; + c_ux__49 = r_ux__48; + c_uy__49 = r_uy__48; + c_uz__49 = r_uz__48; + c_sz__49 = r_sz__48; + c_sr__49 = r_sr__48; + c_sleftz__49 = r_sleftz__48; + c_sleftr__49 = r_sleftr__48; + c_weight__49 = r_weight__48; + c_layer__49 = r_layer__48; + c_dead__49 = r_dead__48; + c_hit__49 = r_hit__48; + c_diff__49 = r_diff__48; + c_dl_b__49 = r_dl_b__48; + c_numer__49 = r_numer__48; + c_z1__49 = r_z1__48; + c_z0__49 = r_z0__48; + c_mut__49 = r_mut__48; + + //for 50 + c_x__50 = r_x__49; + c_y__50 = r_y__49; + c_z__50 = r_z__49; + c_ux__50 = r_ux__49; + c_uy__50 = r_uy__49; + c_uz__50 = r_uz__49; + c_sz__50 = r_sz__49; + c_sr__50 = r_sr__49; + c_sleftz__50 = r_sleftz__49; + c_sleftr__50 = r_sleftr__49; + c_weight__50 = r_weight__49; + c_layer__50 = r_layer__49; + c_dead__50 = r_dead__49; + c_hit__50 = r_hit__49; + c_diff__50 = r_diff__49; + c_dl_b__50 = r_dl_b__49; + c_numer__50 = r_numer__49; + c_z1__50 = r_z1__49; + c_z0__50 = r_z0__49; + c_mut__50 = r_mut__49; + + //for 51 + c_x__51 = r_x__50; + c_y__51 = r_y__50; + c_z__51 = r_z__50; + c_ux__51 = r_ux__50; + c_uy__51 = r_uy__50; + c_uz__51 = r_uz__50; + c_sz__51 = r_sz__50; + c_sr__51 = r_sr__50; + c_sleftz__51 = r_sleftz__50; + c_sleftr__51 = r_sleftr__50; + c_weight__51 = r_weight__50; + c_layer__51 = r_layer__50; + c_dead__51 = r_dead__50; + c_hit__51 = r_hit__50; + c_diff__51 = r_diff__50; + c_dl_b__51 = r_dl_b__50; + c_numer__51 = r_numer__50; + c_z1__51 = r_z1__50; + c_z0__51 = r_z0__50; + c_mut__51 = r_mut__50; + + //for 52 + c_x__52 = r_x__51; + c_y__52 = r_y__51; + c_z__52 = r_z__51; + c_ux__52 = r_ux__51; + c_uy__52 = r_uy__51; + c_uz__52 = r_uz__51; + c_sz__52 = r_sz__51; + c_sr__52 = r_sr__51; + c_sleftz__52 = r_sleftz__51; + c_sleftr__52 = r_sleftr__51; + c_weight__52 = r_weight__51; + c_layer__52 = r_layer__51; + c_dead__52 = r_dead__51; + c_hit__52 = r_hit__51; + c_diff__52 = r_diff__51; + c_dl_b__52 = r_dl_b__51; + c_numer__52 = r_numer__51; + c_z1__52 = r_z1__51; + c_z0__52 = r_z0__51; + c_mut__52 = r_mut__51; + + //for 53 + c_x__53 = r_x__52; + c_y__53 = r_y__52; + c_z__53 = r_z__52; + c_ux__53 = r_ux__52; + c_uy__53 = r_uy__52; + c_uz__53 = r_uz__52; + c_sz__53 = r_sz__52; + c_sr__53 = r_sr__52; + c_sleftz__53 = r_sleftz__52; + c_sleftr__53 = r_sleftr__52; + c_weight__53 = r_weight__52; + c_layer__53 = r_layer__52; + c_dead__53 = r_dead__52; + c_hit__53 = r_hit__52; + c_diff__53 = r_diff__52; + c_dl_b__53 = r_dl_b__52; + c_numer__53 = r_numer__52; + c_z1__53 = r_z1__52; + c_z0__53 = r_z0__52; + c_mut__53 = r_mut__52; + + //for 54 + c_x__54 = r_x__53; + c_y__54 = r_y__53; + c_z__54 = r_z__53; + c_ux__54 = r_ux__53; + c_uy__54 = r_uy__53; + c_uz__54 = r_uz__53; + c_sz__54 = r_sz__53; + c_sr__54 = r_sr__53; + c_sleftz__54 = r_sleftz__53; + c_sleftr__54 = r_sleftr__53; + c_weight__54 = r_weight__53; + c_layer__54 = r_layer__53; + c_dead__54 = r_dead__53; + c_hit__54 = r_hit__53; + c_diff__54 = r_diff__53; + c_dl_b__54 = r_dl_b__53; + c_numer__54 = r_numer__53; + c_z1__54 = r_z1__53; + c_z0__54 = r_z0__53; + c_mut__54 = r_mut__53; + + //for 55 + c_x__55 = r_x__54; + c_y__55 = r_y__54; + c_z__55 = r_z__54; + c_ux__55 = r_ux__54; + c_uy__55 = r_uy__54; + c_uz__55 = r_uz__54; + c_sz__55 = r_sz__54; + c_sr__55 = r_sr__54; + c_sleftz__55 = r_sleftz__54; + c_sleftr__55 = r_sleftr__54; + c_weight__55 = r_weight__54; + c_layer__55 = r_layer__54; + c_dead__55 = r_dead__54; + c_hit__55 = r_hit__54; + c_diff__55 = r_diff__54; + c_dl_b__55 = r_dl_b__54; + c_numer__55 = r_numer__54; + c_z1__55 = r_z1__54; + c_z0__55 = r_z0__54; + c_mut__55 = r_mut__54; + + //for 56 + c_x__56 = r_x__55; + c_y__56 = r_y__55; + c_z__56 = r_z__55; + c_ux__56 = r_ux__55; + c_uy__56 = r_uy__55; + c_uz__56 = r_uz__55; + c_sz__56 = r_sz__55; + c_sr__56 = r_sr__55; + c_sleftz__56 = r_sleftz__55; + c_sleftr__56 = r_sleftr__55; + c_weight__56 = r_weight__55; + c_layer__56 = r_layer__55; + c_dead__56 = r_dead__55; + c_hit__56 = r_hit__55; + c_diff__56 = r_diff__55; + c_dl_b__56 = r_dl_b__55; + c_numer__56 = r_numer__55; + c_z1__56 = r_z1__55; + c_z0__56 = r_z0__55; + c_mut__56 = r_mut__55; + + //for 57 + c_x__57 = r_x__56; + c_y__57 = r_y__56; + c_z__57 = r_z__56; + c_ux__57 = r_ux__56; + c_uy__57 = r_uy__56; + c_uz__57 = r_uz__56; + c_sz__57 = r_sz__56; + c_sr__57 = r_sr__56; + c_sleftz__57 = r_sleftz__56; + c_sleftr__57 = r_sleftr__56; + c_weight__57 = r_weight__56; + c_layer__57 = r_layer__56; + c_dead__57 = r_dead__56; + c_hit__57 = r_hit__56; + c_diff__57 = r_diff__56; + c_dl_b__57 = r_dl_b__56; + c_numer__57 = r_numer__56; + c_z1__57 = r_z1__56; + c_z0__57 = r_z0__56; + c_mut__57 = r_mut__56; + + //for 58 + c_x__58 = r_x__57; + c_y__58 = r_y__57; + c_z__58 = r_z__57; + c_ux__58 = r_ux__57; + c_uy__58 = r_uy__57; + c_uz__58 = r_uz__57; + c_sz__58 = r_sz__57; + c_sr__58 = r_sr__57; + c_sleftz__58 = r_sleftz__57; + c_sleftr__58 = r_sleftr__57; + c_weight__58 = r_weight__57; + c_layer__58 = r_layer__57; + c_dead__58 = r_dead__57; + c_hit__58 = r_hit__57; + c_diff__58 = r_diff__57; + c_dl_b__58 = r_dl_b__57; + c_numer__58 = r_numer__57; + c_z1__58 = r_z1__57; + c_z0__58 = r_z0__57; + c_mut__58 = r_mut__57; + + //for 59 + c_x__59 = r_x__58; + c_y__59 = r_y__58; + c_z__59 = r_z__58; + c_ux__59 = r_ux__58; + c_uy__59 = r_uy__58; + c_uz__59 = r_uz__58; + c_sz__59 = r_sz__58; + c_sr__59 = r_sr__58; + c_sleftz__59 = r_sleftz__58; + c_sleftr__59 = r_sleftr__58; + c_weight__59 = r_weight__58; + c_layer__59 = r_layer__58; + c_dead__59 = r_dead__58; + c_hit__59 = r_hit__58; + c_diff__59 = r_diff__58; + c_dl_b__59 = r_dl_b__58; + c_numer__59 = r_numer__58; + c_z1__59 = r_z1__58; + c_z0__59 = r_z0__58; + c_mut__59 = r_mut__58; + + + // Pull out and replace signals in pipe + /* STAGE 1: Division completed */ + c_dl_b__30 = quotient_div1[32:1]; + c_diff__30 = c_sz__30 - c_dl_b__30; + + if(c_uz__30 != 32'b0 && c_sz__30 > c_dl_b__30 && quotient_div1[63:32] == 32'b0) + begin + /* not horizontal & crossing. */ + c_hit__30 = 1'b1; + end + //Remove blocking on c_hit__30 + else + begin + c_hit__30 = r_hit__29; + end + + /* STAGE 2: First multiply completed */ + if(c_hit__31 == 1'b1) + begin + /*step left = (original step - distance travelled) * scaling factor*/ + + c_sleftz__31 = sleftz_big[2*`BIT_WIDTH-2:`BIT_WIDTH - 1]; + if(c_uz__31[`BIT_WIDTH-1] == 1'b0) + begin + c_z__31 = c_z1__31; + end + else + begin + c_z__31 = c_z0__31; + end + + c_sz__31 = c_dl_b__31; + c_sr__31 = sr_big[2*`BIT_WIDTH-2 - `ASPECT_RATIO:`BIT_WIDTH - 1 - `ASPECT_RATIO]; + end + //Remove blocking on c_sleftz_31, c_sr__31, c_sz__31, c_z__31 + else + begin + c_sleftz__31 = r_sleftz__30; + c_sr__31 = r_sr__30; + c_sz__31 = r_sz__30; + c_z__31 = r_z__30; + end + + /* STAGE 3: Second multiply completed */ + if(c_hit__32 == 1'b1) + begin + /*additional scaling factor on dl_b to switch to r-dimension scale*/ + c_sleftr__32 = sleftr_big[2*`BIT_WIDTH-2 - `ASPECT_RATIO:`BIT_WIDTH - 1 - `ASPECT_RATIO]; + end + //Remove blocking on c_sleftr__32 + else + begin + c_sleftr__32 = r_sleftr__31; + + end +end + +// latch values +always @ (posedge clock) +begin +// for(j = 0; j < `TOTAL_LATENCY; j = j + 1) +// begin +// if (reset) +// begin +// r_x[j] <= 32'b0; +// r_y[j] <= 32'b0; +// r_z[j] <= 32'b0; +// r_ux[j] <= 32'b0; +// r_uy[j] <= 32'b0; +// r_uz[j] <= 32'b0; +// r_sz[j] <= 32'b0; +// r_sr[j] <= 32'b0; +// r_sleftz[j] <= 32'b0; +// r_sleftr[j] <= 32'b0; +// r_weight[j] <= 32'b0; +// r_layer[j] <= 3'b0; +// r_dead[j] <= 1'b1; +// r_hit[j] <= 1'b0; +// r_diff[j] <= 32'b0; +// r_dl_b[j] <= 32'b0; +// r_numer[j] <= 64'b0; +// r_z1[j] <= 32'b0; +// r_z0[j] <= 32'b0; +// r_mut[j] <= 32'b0; +// end +// else +// begin +// if(enable) +// begin +// r_x[j] <= c_x[j]; +// r_y[j] <= c_y[j]; +// r_z[j] <= c_z[j]; +// r_ux[j] <= c_ux[j]; +// r_uy[j] <= c_uy[j]; +// r_uz[j] <= c_uz[j]; +// r_sz[j] <= c_sz[j]; +// r_sr[j] <= c_sr[j]; +// r_sleftz[j] <= c_sleftz[j]; +// r_sleftr[j] <= c_sleftr[j]; +// r_weight[j] <= c_weight[j]; +// r_layer[j] <= c_layer[j]; +// r_dead[j] <= c_dead[j]; +// r_hit[j] <= c_hit[j]; +// r_diff[j] <= c_diff[j]; +// r_dl_b[j] <= c_dl_b[j]; +// r_numer[j] <= c_numer[j]; +// r_z1[j] <= c_z1[j]; +// r_z0[j] <= c_z0[j]; +// r_mut[j] <= c_mut[j]; +// end +// end +// end + if(reset) + begin + //Instantiate all 60 aspects of loop + r_x__59 <= 32'b00000000000000000000000000000000; + r_y__59 <= 32'b00000000000000000000000000000000; + r_z__59 <= 32'b00000000000000000000000000000000; + r_ux__59 <= 32'b00000000000000000000000000000000; + r_uy__59 <= 32'b00000000000000000000000000000000; + r_uz__59 <= 32'b00000000000000000000000000000000; + r_sz__59 <= 32'b00000000000000000000000000000000; + r_sr__59 <= 32'b00000000000000000000000000000000; + r_sleftz__59 <= 32'b00000000000000000000000000000000; + r_sleftr__59 <= 32'b00000000000000000000000000000000; + r_weight__59 <= 32'b00000000000000000000000000000000; + r_layer__59 <= 3'b000; + r_dead__59 <= 1'b1; + r_hit__59 <= 1'b0; + r_diff__59 <= 32'b00000000000000000000000000000000; + r_dl_b__59 <= 32'b00000000000000000000000000000000; + r_numer__59 <= 0; + r_z1__59 <= 32'b00000000000000000000000000000000; + r_z0__59 <= 32'b00000000000000000000000000000000; + r_mut__59 <= 32'b00000000000000000000000000000000; + + r_x__58 <= 32'b00000000000000000000000000000000; + r_y__58 <= 32'b00000000000000000000000000000000; + r_z__58 <= 32'b00000000000000000000000000000000; + r_ux__58 <= 32'b00000000000000000000000000000000; + r_uy__58 <= 32'b00000000000000000000000000000000; + r_uz__58 <= 32'b00000000000000000000000000000000; + r_sz__58 <= 32'b00000000000000000000000000000000; + r_sr__58 <= 32'b00000000000000000000000000000000; + r_sleftz__58 <= 32'b00000000000000000000000000000000; + r_sleftr__58 <= 32'b00000000000000000000000000000000; + r_weight__58 <= 32'b00000000000000000000000000000000; + r_layer__58 <= 3'b000; + r_dead__58 <= 1'b1; + r_hit__58 <= 1'b0; + r_diff__58 <= 32'b00000000000000000000000000000000; + r_dl_b__58 <= 32'b00000000000000000000000000000000; + r_numer__58 <= 0; + r_z1__58 <= 32'b00000000000000000000000000000000; + r_z0__58 <= 32'b00000000000000000000000000000000; + r_mut__58 <= 32'b00000000000000000000000000000000; + + r_x__57 <= 32'b00000000000000000000000000000000; + r_y__57 <= 32'b00000000000000000000000000000000; + r_z__57 <= 32'b00000000000000000000000000000000; + r_ux__57 <= 32'b00000000000000000000000000000000; + r_uy__57 <= 32'b00000000000000000000000000000000; + r_uz__57 <= 32'b00000000000000000000000000000000; + r_sz__57 <= 32'b00000000000000000000000000000000; + r_sr__57 <= 32'b00000000000000000000000000000000; + r_sleftz__57 <= 32'b00000000000000000000000000000000; + r_sleftr__57 <= 32'b00000000000000000000000000000000; + r_weight__57 <= 32'b00000000000000000000000000000000; + r_layer__57 <= 3'b000; + r_dead__57 <= 1'b1; + r_hit__57 <= 1'b0; + r_diff__57 <= 32'b00000000000000000000000000000000; + r_dl_b__57 <= 32'b00000000000000000000000000000000; + r_numer__57 <= 0; + r_z1__57 <= 32'b00000000000000000000000000000000; + r_z0__57 <= 32'b00000000000000000000000000000000; + r_mut__57 <= 32'b00000000000000000000000000000000; + + r_x__56 <= 32'b00000000000000000000000000000000; + r_y__56 <= 32'b00000000000000000000000000000000; + r_z__56 <= 32'b00000000000000000000000000000000; + r_ux__56 <= 32'b00000000000000000000000000000000; + r_uy__56 <= 32'b00000000000000000000000000000000; + r_uz__56 <= 32'b00000000000000000000000000000000; + r_sz__56 <= 32'b00000000000000000000000000000000; + r_sr__56 <= 32'b00000000000000000000000000000000; + r_sleftz__56 <= 32'b00000000000000000000000000000000; + r_sleftr__56 <= 32'b00000000000000000000000000000000; + r_weight__56 <= 32'b00000000000000000000000000000000; + r_layer__56 <= 3'b000; + r_dead__56 <= 1'b1; + r_hit__56 <= 1'b0; + r_diff__56 <= 32'b00000000000000000000000000000000; + r_dl_b__56 <= 32'b00000000000000000000000000000000; + r_numer__56 <= 0; + r_z1__56 <= 32'b00000000000000000000000000000000; + r_z0__56 <= 32'b00000000000000000000000000000000; + r_mut__56 <= 32'b00000000000000000000000000000000; + + r_x__55 <= 32'b00000000000000000000000000000000; + r_y__55 <= 32'b00000000000000000000000000000000; + r_z__55 <= 32'b00000000000000000000000000000000; + r_ux__55 <= 32'b00000000000000000000000000000000; + r_uy__55 <= 32'b00000000000000000000000000000000; + r_uz__55 <= 32'b00000000000000000000000000000000; + r_sz__55 <= 32'b00000000000000000000000000000000; + r_sr__55 <= 32'b00000000000000000000000000000000; + r_sleftz__55 <= 32'b00000000000000000000000000000000; + r_sleftr__55 <= 32'b00000000000000000000000000000000; + r_weight__55 <= 32'b00000000000000000000000000000000; + r_layer__55 <= 3'b000; + r_dead__55 <= 1'b1; + r_hit__55 <= 1'b0; + r_diff__55 <= 32'b00000000000000000000000000000000; + r_dl_b__55 <= 32'b00000000000000000000000000000000; + r_numer__55 <= 0; + r_z1__55 <= 32'b00000000000000000000000000000000; + r_z0__55 <= 32'b00000000000000000000000000000000; + r_mut__55 <= 32'b00000000000000000000000000000000; + + r_x__54 <= 32'b00000000000000000000000000000000; + r_y__54 <= 32'b00000000000000000000000000000000; + r_z__54 <= 32'b00000000000000000000000000000000; + r_ux__54 <= 32'b00000000000000000000000000000000; + r_uy__54 <= 32'b00000000000000000000000000000000; + r_uz__54 <= 32'b00000000000000000000000000000000; + r_sz__54 <= 32'b00000000000000000000000000000000; + r_sr__54 <= 32'b00000000000000000000000000000000; + r_sleftz__54 <= 32'b00000000000000000000000000000000; + r_sleftr__54 <= 32'b00000000000000000000000000000000; + r_weight__54 <= 32'b00000000000000000000000000000000; + r_layer__54 <= 3'b000; + r_dead__54 <= 1'b1; + r_hit__54 <= 1'b0; + r_diff__54 <= 32'b00000000000000000000000000000000; + r_dl_b__54 <= 32'b00000000000000000000000000000000; + r_numer__54 <= 0; + r_z1__54 <= 32'b00000000000000000000000000000000; + r_z0__54 <= 32'b00000000000000000000000000000000; + r_mut__54 <= 32'b00000000000000000000000000000000; + + r_x__53 <= 32'b00000000000000000000000000000000; + r_y__53 <= 32'b00000000000000000000000000000000; + r_z__53 <= 32'b00000000000000000000000000000000; + r_ux__53 <= 32'b00000000000000000000000000000000; + r_uy__53 <= 32'b00000000000000000000000000000000; + r_uz__53 <= 32'b00000000000000000000000000000000; + r_sz__53 <= 32'b00000000000000000000000000000000; + r_sr__53 <= 32'b00000000000000000000000000000000; + r_sleftz__53 <= 32'b00000000000000000000000000000000; + r_sleftr__53 <= 32'b00000000000000000000000000000000; + r_weight__53 <= 32'b00000000000000000000000000000000; + r_layer__53 <= 3'b000; + r_dead__53 <= 1'b1; + r_hit__53 <= 1'b0; + r_diff__53 <= 32'b00000000000000000000000000000000; + r_dl_b__53 <= 32'b00000000000000000000000000000000; + r_numer__53 <= 0; + r_z1__53 <= 32'b00000000000000000000000000000000; + r_z0__53 <= 32'b00000000000000000000000000000000; + r_mut__53 <= 32'b00000000000000000000000000000000; + + r_x__52 <= 32'b00000000000000000000000000000000; + r_y__52 <= 32'b00000000000000000000000000000000; + r_z__52 <= 32'b00000000000000000000000000000000; + r_ux__52 <= 32'b00000000000000000000000000000000; + r_uy__52 <= 32'b00000000000000000000000000000000; + r_uz__52 <= 32'b00000000000000000000000000000000; + r_sz__52 <= 32'b00000000000000000000000000000000; + r_sr__52 <= 32'b00000000000000000000000000000000; + r_sleftz__52 <= 32'b00000000000000000000000000000000; + r_sleftr__52 <= 32'b00000000000000000000000000000000; + r_weight__52 <= 32'b00000000000000000000000000000000; + r_layer__52 <= 3'b000; + r_dead__52 <= 1'b1; + r_hit__52 <= 1'b0; + r_diff__52 <= 32'b00000000000000000000000000000000; + r_dl_b__52 <= 32'b00000000000000000000000000000000; + r_numer__52 <= 0; + r_z1__52 <= 32'b00000000000000000000000000000000; + r_z0__52 <= 32'b00000000000000000000000000000000; + r_mut__52 <= 32'b00000000000000000000000000000000; + + r_x__51 <= 32'b00000000000000000000000000000000; + r_y__51 <= 32'b00000000000000000000000000000000; + r_z__51 <= 32'b00000000000000000000000000000000; + r_ux__51 <= 32'b00000000000000000000000000000000; + r_uy__51 <= 32'b00000000000000000000000000000000; + r_uz__51 <= 32'b00000000000000000000000000000000; + r_sz__51 <= 32'b00000000000000000000000000000000; + r_sr__51 <= 32'b00000000000000000000000000000000; + r_sleftz__51 <= 32'b00000000000000000000000000000000; + r_sleftr__51 <= 32'b00000000000000000000000000000000; + r_weight__51 <= 32'b00000000000000000000000000000000; + r_layer__51 <= 3'b000; + r_dead__51 <= 1'b1; + r_hit__51 <= 1'b0; + r_diff__51 <= 32'b00000000000000000000000000000000; + r_dl_b__51 <= 32'b00000000000000000000000000000000; + r_numer__51 <= 0; + r_z1__51 <= 32'b00000000000000000000000000000000; + r_z0__51 <= 32'b00000000000000000000000000000000; + r_mut__51 <= 32'b00000000000000000000000000000000; + + r_x__50 <= 32'b00000000000000000000000000000000; + r_y__50 <= 32'b00000000000000000000000000000000; + r_z__50 <= 32'b00000000000000000000000000000000; + r_ux__50 <= 32'b00000000000000000000000000000000; + r_uy__50 <= 32'b00000000000000000000000000000000; + r_uz__50 <= 32'b00000000000000000000000000000000; + r_sz__50 <= 32'b00000000000000000000000000000000; + r_sr__50 <= 32'b00000000000000000000000000000000; + r_sleftz__50 <= 32'b00000000000000000000000000000000; + r_sleftr__50 <= 32'b00000000000000000000000000000000; + r_weight__50 <= 32'b00000000000000000000000000000000; + r_layer__50 <= 3'b000; + r_dead__50 <= 1'b1; + r_hit__50 <= 1'b0; + r_diff__50 <= 32'b00000000000000000000000000000000; + r_dl_b__50 <= 32'b00000000000000000000000000000000; + r_numer__50 <= 0; + r_z1__50 <= 32'b00000000000000000000000000000000; + r_z0__50 <= 32'b00000000000000000000000000000000; + r_mut__50 <= 32'b00000000000000000000000000000000; + + r_x__49 <= 32'b00000000000000000000000000000000; + r_y__49 <= 32'b00000000000000000000000000000000; + r_z__49 <= 32'b00000000000000000000000000000000; + r_ux__49 <= 32'b00000000000000000000000000000000; + r_uy__49 <= 32'b00000000000000000000000000000000; + r_uz__49 <= 32'b00000000000000000000000000000000; + r_sz__49 <= 32'b00000000000000000000000000000000; + r_sr__49 <= 32'b00000000000000000000000000000000; + r_sleftz__49 <= 32'b00000000000000000000000000000000; + r_sleftr__49 <= 32'b00000000000000000000000000000000; + r_weight__49 <= 32'b00000000000000000000000000000000; + r_layer__49 <= 3'b000; + r_dead__49 <= 1'b1; + r_hit__49 <= 1'b0; + r_diff__49 <= 32'b00000000000000000000000000000000; + r_dl_b__49 <= 32'b00000000000000000000000000000000; + r_numer__49 <= 0; + r_z1__49 <= 32'b00000000000000000000000000000000; + r_z0__49 <= 32'b00000000000000000000000000000000; + r_mut__49 <= 32'b00000000000000000000000000000000; + + r_x__48 <= 32'b00000000000000000000000000000000; + r_y__48 <= 32'b00000000000000000000000000000000; + r_z__48 <= 32'b00000000000000000000000000000000; + r_ux__48 <= 32'b00000000000000000000000000000000; + r_uy__48 <= 32'b00000000000000000000000000000000; + r_uz__48 <= 32'b00000000000000000000000000000000; + r_sz__48 <= 32'b00000000000000000000000000000000; + r_sr__48 <= 32'b00000000000000000000000000000000; + r_sleftz__48 <= 32'b00000000000000000000000000000000; + r_sleftr__48 <= 32'b00000000000000000000000000000000; + r_weight__48 <= 32'b00000000000000000000000000000000; + r_layer__48 <= 3'b000; + r_dead__48 <= 1'b1; + r_hit__48 <= 1'b0; + r_diff__48 <= 32'b00000000000000000000000000000000; + r_dl_b__48 <= 32'b00000000000000000000000000000000; + r_numer__48 <= 0; + r_z1__48 <= 32'b00000000000000000000000000000000; + r_z0__48 <= 32'b00000000000000000000000000000000; + r_mut__48 <= 32'b00000000000000000000000000000000; + + r_x__47 <= 32'b00000000000000000000000000000000; + r_y__47 <= 32'b00000000000000000000000000000000; + r_z__47 <= 32'b00000000000000000000000000000000; + r_ux__47 <= 32'b00000000000000000000000000000000; + r_uy__47 <= 32'b00000000000000000000000000000000; + r_uz__47 <= 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32'b00000000000000000000000000000000; + r_mut__19 <= 32'b00000000000000000000000000000000; + + r_x__18 <= 32'b00000000000000000000000000000000; + r_y__18 <= 32'b00000000000000000000000000000000; + r_z__18 <= 32'b00000000000000000000000000000000; + r_ux__18 <= 32'b00000000000000000000000000000000; + r_uy__18 <= 32'b00000000000000000000000000000000; + r_uz__18 <= 32'b00000000000000000000000000000000; + r_sz__18 <= 32'b00000000000000000000000000000000; + r_sr__18 <= 32'b00000000000000000000000000000000; + r_sleftz__18 <= 32'b00000000000000000000000000000000; + r_sleftr__18 <= 32'b00000000000000000000000000000000; + r_weight__18 <= 32'b00000000000000000000000000000000; + r_layer__18 <= 3'b000; + r_dead__18 <= 1'b1; + r_hit__18 <= 1'b0; + r_diff__18 <= 32'b00000000000000000000000000000000; + r_dl_b__18 <= 32'b00000000000000000000000000000000; + r_numer__18 <= 0; + r_z1__18 <= 32'b00000000000000000000000000000000; + r_z0__18 <= 32'b00000000000000000000000000000000; + r_mut__18 <= 32'b00000000000000000000000000000000; + + r_x__17 <= 32'b00000000000000000000000000000000; + r_y__17 <= 32'b00000000000000000000000000000000; + r_z__17 <= 32'b00000000000000000000000000000000; + r_ux__17 <= 32'b00000000000000000000000000000000; + r_uy__17 <= 32'b00000000000000000000000000000000; + r_uz__17 <= 32'b00000000000000000000000000000000; + r_sz__17 <= 32'b00000000000000000000000000000000; + r_sr__17 <= 32'b00000000000000000000000000000000; + r_sleftz__17 <= 32'b00000000000000000000000000000000; + r_sleftr__17 <= 32'b00000000000000000000000000000000; + r_weight__17 <= 32'b00000000000000000000000000000000; + r_layer__17 <= 3'b000; + r_dead__17 <= 1'b1; + r_hit__17 <= 1'b0; + r_diff__17 <= 32'b00000000000000000000000000000000; + r_dl_b__17 <= 32'b00000000000000000000000000000000; + r_numer__17 <= 0; + r_z1__17 <= 32'b00000000000000000000000000000000; + r_z0__17 <= 32'b00000000000000000000000000000000; + r_mut__17 <= 32'b00000000000000000000000000000000; + + r_x__16 <= 32'b00000000000000000000000000000000; + r_y__16 <= 32'b00000000000000000000000000000000; + r_z__16 <= 32'b00000000000000000000000000000000; + r_ux__16 <= 32'b00000000000000000000000000000000; + r_uy__16 <= 32'b00000000000000000000000000000000; + r_uz__16 <= 32'b00000000000000000000000000000000; + r_sz__16 <= 32'b00000000000000000000000000000000; + r_sr__16 <= 32'b00000000000000000000000000000000; + r_sleftz__16 <= 32'b00000000000000000000000000000000; + r_sleftr__16 <= 32'b00000000000000000000000000000000; + r_weight__16 <= 32'b00000000000000000000000000000000; + r_layer__16 <= 3'b000; + r_dead__16 <= 1'b1; + r_hit__16 <= 1'b0; + r_diff__16 <= 32'b00000000000000000000000000000000; + r_dl_b__16 <= 32'b00000000000000000000000000000000; + r_numer__16 <= 0; + r_z1__16 <= 32'b00000000000000000000000000000000; + r_z0__16 <= 32'b00000000000000000000000000000000; + r_mut__16 <= 32'b00000000000000000000000000000000; + + r_x__15 <= 32'b00000000000000000000000000000000; + r_y__15 <= 32'b00000000000000000000000000000000; + r_z__15 <= 32'b00000000000000000000000000000000; + r_ux__15 <= 32'b00000000000000000000000000000000; + r_uy__15 <= 32'b00000000000000000000000000000000; + r_uz__15 <= 32'b00000000000000000000000000000000; + r_sz__15 <= 32'b00000000000000000000000000000000; + r_sr__15 <= 32'b00000000000000000000000000000000; + r_sleftz__15 <= 32'b00000000000000000000000000000000; + r_sleftr__15 <= 32'b00000000000000000000000000000000; + r_weight__15 <= 32'b00000000000000000000000000000000; + r_layer__15 <= 3'b000; + r_dead__15 <= 1'b1; + r_hit__15 <= 1'b0; + r_diff__15 <= 32'b00000000000000000000000000000000; + r_dl_b__15 <= 32'b00000000000000000000000000000000; + r_numer__15 <= 0; + r_z1__15 <= 32'b00000000000000000000000000000000; + r_z0__15 <= 32'b00000000000000000000000000000000; + r_mut__15 <= 32'b00000000000000000000000000000000; + + r_x__14 <= 32'b00000000000000000000000000000000; + r_y__14 <= 32'b00000000000000000000000000000000; + r_z__14 <= 32'b00000000000000000000000000000000; + r_ux__14 <= 32'b00000000000000000000000000000000; + r_uy__14 <= 32'b00000000000000000000000000000000; + r_uz__14 <= 32'b00000000000000000000000000000000; + r_sz__14 <= 32'b00000000000000000000000000000000; + r_sr__14 <= 32'b00000000000000000000000000000000; + r_sleftz__14 <= 32'b00000000000000000000000000000000; + r_sleftr__14 <= 32'b00000000000000000000000000000000; + r_weight__14 <= 32'b00000000000000000000000000000000; + r_layer__14 <= 3'b000; + r_dead__14 <= 1'b1; + r_hit__14 <= 1'b0; + r_diff__14 <= 32'b00000000000000000000000000000000; + r_dl_b__14 <= 32'b00000000000000000000000000000000; + r_numer__14 <= 0; + r_z1__14 <= 32'b00000000000000000000000000000000; + r_z0__14 <= 32'b00000000000000000000000000000000; + r_mut__14 <= 32'b00000000000000000000000000000000; + + r_x__13 <= 32'b00000000000000000000000000000000; + r_y__13 <= 32'b00000000000000000000000000000000; + r_z__13 <= 32'b00000000000000000000000000000000; + r_ux__13 <= 32'b00000000000000000000000000000000; + r_uy__13 <= 32'b00000000000000000000000000000000; + r_uz__13 <= 32'b00000000000000000000000000000000; + r_sz__13 <= 32'b00000000000000000000000000000000; + r_sr__13 <= 32'b00000000000000000000000000000000; + r_sleftz__13 <= 32'b00000000000000000000000000000000; + r_sleftr__13 <= 32'b00000000000000000000000000000000; + r_weight__13 <= 32'b00000000000000000000000000000000; + r_layer__13 <= 3'b000; + r_dead__13 <= 1'b1; + r_hit__13 <= 1'b0; + r_diff__13 <= 32'b00000000000000000000000000000000; + r_dl_b__13 <= 32'b00000000000000000000000000000000; + r_numer__13 <= 0; + r_z1__13 <= 32'b00000000000000000000000000000000; + r_z0__13 <= 32'b00000000000000000000000000000000; + r_mut__13 <= 32'b00000000000000000000000000000000; + + r_x__12 <= 32'b00000000000000000000000000000000; + r_y__12 <= 32'b00000000000000000000000000000000; + r_z__12 <= 32'b00000000000000000000000000000000; + r_ux__12 <= 32'b00000000000000000000000000000000; + r_uy__12 <= 32'b00000000000000000000000000000000; + r_uz__12 <= 32'b00000000000000000000000000000000; + r_sz__12 <= 32'b00000000000000000000000000000000; + r_sr__12 <= 32'b00000000000000000000000000000000; + r_sleftz__12 <= 32'b00000000000000000000000000000000; + r_sleftr__12 <= 32'b00000000000000000000000000000000; + r_weight__12 <= 32'b00000000000000000000000000000000; + r_layer__12 <= 3'b000; + r_dead__12 <= 1'b1; + r_hit__12 <= 1'b0; + r_diff__12 <= 32'b00000000000000000000000000000000; + r_dl_b__12 <= 32'b00000000000000000000000000000000; + r_numer__12 <= 0; + r_z1__12 <= 32'b00000000000000000000000000000000; + r_z0__12 <= 32'b00000000000000000000000000000000; + r_mut__12 <= 32'b00000000000000000000000000000000; + + r_x__11 <= 32'b00000000000000000000000000000000; + r_y__11 <= 32'b00000000000000000000000000000000; + r_z__11 <= 32'b00000000000000000000000000000000; + r_ux__11 <= 32'b00000000000000000000000000000000; + r_uy__11 <= 32'b00000000000000000000000000000000; + r_uz__11 <= 32'b00000000000000000000000000000000; + r_sz__11 <= 32'b00000000000000000000000000000000; + r_sr__11 <= 32'b00000000000000000000000000000000; + r_sleftz__11 <= 32'b00000000000000000000000000000000; + r_sleftr__11 <= 32'b00000000000000000000000000000000; + r_weight__11 <= 32'b00000000000000000000000000000000; + r_layer__11 <= 3'b000; + r_dead__11 <= 1'b1; + r_hit__11 <= 1'b0; + r_diff__11 <= 32'b00000000000000000000000000000000; + r_dl_b__11 <= 32'b00000000000000000000000000000000; + r_numer__11 <= 0; + r_z1__11 <= 32'b00000000000000000000000000000000; + r_z0__11 <= 32'b00000000000000000000000000000000; + r_mut__11 <= 32'b00000000000000000000000000000000; + + r_x__10 <= 32'b00000000000000000000000000000000; + r_y__10 <= 32'b00000000000000000000000000000000; + r_z__10 <= 32'b00000000000000000000000000000000; + r_ux__10 <= 32'b00000000000000000000000000000000; + r_uy__10 <= 32'b00000000000000000000000000000000; + r_uz__10 <= 32'b00000000000000000000000000000000; + r_sz__10 <= 32'b00000000000000000000000000000000; + r_sr__10 <= 32'b00000000000000000000000000000000; + r_sleftz__10 <= 32'b00000000000000000000000000000000; + r_sleftr__10 <= 32'b00000000000000000000000000000000; + r_weight__10 <= 32'b00000000000000000000000000000000; + r_layer__10 <= 3'b000; + r_dead__10 <= 1'b1; + r_hit__10 <= 1'b0; + r_diff__10 <= 32'b00000000000000000000000000000000; + r_dl_b__10 <= 32'b00000000000000000000000000000000; + r_numer__10 <= 0; + r_z1__10 <= 32'b00000000000000000000000000000000; + r_z0__10 <= 32'b00000000000000000000000000000000; + r_mut__10 <= 32'b00000000000000000000000000000000; + + r_x__9 <= 32'b00000000000000000000000000000000; + r_y__9 <= 32'b00000000000000000000000000000000; + r_z__9 <= 32'b00000000000000000000000000000000; + r_ux__9 <= 32'b00000000000000000000000000000000; + r_uy__9 <= 32'b00000000000000000000000000000000; + r_uz__9 <= 32'b00000000000000000000000000000000; + r_sz__9 <= 32'b00000000000000000000000000000000; + r_sr__9 <= 32'b00000000000000000000000000000000; + r_sleftz__9 <= 32'b00000000000000000000000000000000; + r_sleftr__9 <= 32'b00000000000000000000000000000000; + r_weight__9 <= 32'b00000000000000000000000000000000; + r_layer__9 <= 3'b000; + r_dead__9 <= 1'b1; + r_hit__9 <= 1'b0; + r_diff__9 <= 32'b00000000000000000000000000000000; + r_dl_b__9 <= 32'b00000000000000000000000000000000; + r_numer__9 <= 0; + r_z1__9 <= 32'b00000000000000000000000000000000; + r_z0__9 <= 32'b00000000000000000000000000000000; + r_mut__9 <= 32'b00000000000000000000000000000000; + + r_x__8 <= 32'b00000000000000000000000000000000; + r_y__8 <= 32'b00000000000000000000000000000000; + r_z__8 <= 32'b00000000000000000000000000000000; + r_ux__8 <= 32'b00000000000000000000000000000000; + r_uy__8 <= 32'b00000000000000000000000000000000; + r_uz__8 <= 32'b00000000000000000000000000000000; + r_sz__8 <= 32'b00000000000000000000000000000000; + r_sr__8 <= 32'b00000000000000000000000000000000; + r_sleftz__8 <= 32'b00000000000000000000000000000000; + r_sleftr__8 <= 32'b00000000000000000000000000000000; + r_weight__8 <= 32'b00000000000000000000000000000000; + r_layer__8 <= 3'b000; + r_dead__8 <= 1'b1; + r_hit__8 <= 1'b0; + r_diff__8 <= 32'b00000000000000000000000000000000; + r_dl_b__8 <= 32'b00000000000000000000000000000000; + r_numer__8 <= 0; + r_z1__8 <= 32'b00000000000000000000000000000000; + r_z0__8 <= 32'b00000000000000000000000000000000; + r_mut__8 <= 32'b00000000000000000000000000000000; + + r_x__7 <= 32'b00000000000000000000000000000000; + r_y__7 <= 32'b00000000000000000000000000000000; + r_z__7 <= 32'b00000000000000000000000000000000; + r_ux__7 <= 32'b00000000000000000000000000000000; + r_uy__7 <= 32'b00000000000000000000000000000000; + r_uz__7 <= 32'b00000000000000000000000000000000; + r_sz__7 <= 32'b00000000000000000000000000000000; + r_sr__7 <= 32'b00000000000000000000000000000000; + r_sleftz__7 <= 32'b00000000000000000000000000000000; + r_sleftr__7 <= 32'b00000000000000000000000000000000; + r_weight__7 <= 32'b00000000000000000000000000000000; + r_layer__7 <= 3'b000; + r_dead__7 <= 1'b1; + r_hit__7 <= 1'b0; + r_diff__7 <= 32'b00000000000000000000000000000000; + r_dl_b__7 <= 32'b00000000000000000000000000000000; + r_numer__7 <= 0; + r_z1__7 <= 32'b00000000000000000000000000000000; + r_z0__7 <= 32'b00000000000000000000000000000000; + r_mut__7 <= 32'b00000000000000000000000000000000; + + r_x__6 <= 32'b00000000000000000000000000000000; + r_y__6 <= 32'b00000000000000000000000000000000; + r_z__6 <= 32'b00000000000000000000000000000000; + r_ux__6 <= 32'b00000000000000000000000000000000; + r_uy__6 <= 32'b00000000000000000000000000000000; + r_uz__6 <= 32'b00000000000000000000000000000000; + r_sz__6 <= 32'b00000000000000000000000000000000; + r_sr__6 <= 32'b00000000000000000000000000000000; + r_sleftz__6 <= 32'b00000000000000000000000000000000; + r_sleftr__6 <= 32'b00000000000000000000000000000000; + r_weight__6 <= 32'b00000000000000000000000000000000; + r_layer__6 <= 3'b000; + r_dead__6 <= 1'b1; + r_hit__6 <= 1'b0; + r_diff__6 <= 32'b00000000000000000000000000000000; + r_dl_b__6 <= 32'b00000000000000000000000000000000; + r_numer__6 <= 0; + r_z1__6 <= 32'b00000000000000000000000000000000; + r_z0__6 <= 32'b00000000000000000000000000000000; + r_mut__6 <= 32'b00000000000000000000000000000000; + + r_x__5 <= 32'b00000000000000000000000000000000; + r_y__5 <= 32'b00000000000000000000000000000000; + r_z__5 <= 32'b00000000000000000000000000000000; + r_ux__5 <= 32'b00000000000000000000000000000000; + r_uy__5 <= 32'b00000000000000000000000000000000; + r_uz__5 <= 32'b00000000000000000000000000000000; + r_sz__5 <= 32'b00000000000000000000000000000000; + r_sr__5 <= 32'b00000000000000000000000000000000; + r_sleftz__5 <= 32'b00000000000000000000000000000000; + r_sleftr__5 <= 32'b00000000000000000000000000000000; + r_weight__5 <= 32'b00000000000000000000000000000000; + r_layer__5 <= 3'b000; + r_dead__5 <= 1'b1; + r_hit__5 <= 1'b0; + r_diff__5 <= 32'b00000000000000000000000000000000; + r_dl_b__5 <= 32'b00000000000000000000000000000000; + r_numer__5 <= 0; + r_z1__5 <= 32'b00000000000000000000000000000000; + r_z0__5 <= 32'b00000000000000000000000000000000; + r_mut__5 <= 32'b00000000000000000000000000000000; + + r_x__4 <= 32'b00000000000000000000000000000000; + r_y__4 <= 32'b00000000000000000000000000000000; + r_z__4 <= 32'b00000000000000000000000000000000; + r_ux__4 <= 32'b00000000000000000000000000000000; + r_uy__4 <= 32'b00000000000000000000000000000000; + r_uz__4 <= 32'b00000000000000000000000000000000; + r_sz__4 <= 32'b00000000000000000000000000000000; + r_sr__4 <= 32'b00000000000000000000000000000000; + r_sleftz__4 <= 32'b00000000000000000000000000000000; + r_sleftr__4 <= 32'b00000000000000000000000000000000; + r_weight__4 <= 32'b00000000000000000000000000000000; + r_layer__4 <= 3'b000; + r_dead__4 <= 1'b1; + r_hit__4 <= 1'b0; + r_diff__4 <= 32'b00000000000000000000000000000000; + r_dl_b__4 <= 32'b00000000000000000000000000000000; + r_numer__4 <= 0; + r_z1__4 <= 32'b00000000000000000000000000000000; + r_z0__4 <= 32'b00000000000000000000000000000000; + r_mut__4 <= 32'b00000000000000000000000000000000; + + r_x__3 <= 32'b00000000000000000000000000000000; + r_y__3 <= 32'b00000000000000000000000000000000; + r_z__3 <= 32'b00000000000000000000000000000000; + r_ux__3 <= 32'b00000000000000000000000000000000; + r_uy__3 <= 32'b00000000000000000000000000000000; + r_uz__3 <= 32'b00000000000000000000000000000000; + r_sz__3 <= 32'b00000000000000000000000000000000; + r_sr__3 <= 32'b00000000000000000000000000000000; + r_sleftz__3 <= 32'b00000000000000000000000000000000; + r_sleftr__3 <= 32'b00000000000000000000000000000000; + r_weight__3 <= 32'b00000000000000000000000000000000; + r_layer__3 <= 3'b000; + r_dead__3 <= 1'b1; + r_hit__3 <= 1'b0; + r_diff__3 <= 32'b00000000000000000000000000000000; + r_dl_b__3 <= 32'b00000000000000000000000000000000; + r_numer__3 <= 0; + r_z1__3 <= 32'b00000000000000000000000000000000; + r_z0__3 <= 32'b00000000000000000000000000000000; + r_mut__3 <= 32'b00000000000000000000000000000000; + + r_x__2 <= 32'b00000000000000000000000000000000; + r_y__2 <= 32'b00000000000000000000000000000000; + r_z__2 <= 32'b00000000000000000000000000000000; + r_ux__2 <= 32'b00000000000000000000000000000000; + r_uy__2 <= 32'b00000000000000000000000000000000; + r_uz__2 <= 32'b00000000000000000000000000000000; + r_sz__2 <= 32'b00000000000000000000000000000000; + r_sr__2 <= 32'b00000000000000000000000000000000; + r_sleftz__2 <= 32'b00000000000000000000000000000000; + r_sleftr__2 <= 32'b00000000000000000000000000000000; + r_weight__2 <= 32'b00000000000000000000000000000000; + r_layer__2 <= 3'b000; + r_dead__2 <= 1'b1; + r_hit__2 <= 1'b0; + r_diff__2 <= 32'b00000000000000000000000000000000; + r_dl_b__2 <= 32'b00000000000000000000000000000000; + r_numer__2 <= 0; + r_z1__2 <= 32'b00000000000000000000000000000000; + r_z0__2 <= 32'b00000000000000000000000000000000; + r_mut__2 <= 32'b00000000000000000000000000000000; + + r_x__1 <= 32'b00000000000000000000000000000000; + r_y__1 <= 32'b00000000000000000000000000000000; + r_z__1 <= 32'b00000000000000000000000000000000; + r_ux__1 <= 32'b00000000000000000000000000000000; + r_uy__1 <= 32'b00000000000000000000000000000000; + r_uz__1 <= 32'b00000000000000000000000000000000; + r_sz__1 <= 32'b00000000000000000000000000000000; + r_sr__1 <= 32'b00000000000000000000000000000000; + r_sleftz__1 <= 32'b00000000000000000000000000000000; + r_sleftr__1 <= 32'b00000000000000000000000000000000; + r_weight__1 <= 32'b00000000000000000000000000000000; + r_layer__1 <= 3'b000; + r_dead__1 <= 1'b1; + r_hit__1 <= 1'b0; + r_diff__1 <= 32'b00000000000000000000000000000000; + r_dl_b__1 <= 32'b00000000000000000000000000000000; + r_numer__1 <= 0; + r_z1__1 <= 32'b00000000000000000000000000000000; + r_z0__1 <= 32'b00000000000000000000000000000000; + r_mut__1 <= 32'b00000000000000000000000000000000; + + r_x__0 <= 32'b00000000000000000000000000000000; + r_y__0 <= 32'b00000000000000000000000000000000; + r_z__0 <= 32'b00000000000000000000000000000000; + r_ux__0 <= 32'b00000000000000000000000000000000; + r_uy__0 <= 32'b00000000000000000000000000000000; + r_uz__0 <= 32'b00000000000000000000000000000000; + r_sz__0 <= 32'b00000000000000000000000000000000; + r_sr__0 <= 32'b00000000000000000000000000000000; + r_sleftz__0 <= 32'b00000000000000000000000000000000; + r_sleftr__0 <= 32'b00000000000000000000000000000000; + r_weight__0 <= 32'b00000000000000000000000000000000; + r_layer__0 <= 3'b000; + r_dead__0 <= 1'b0; + r_hit__0 <= 1'b0; + r_diff__0 <= 32'b00000000000000000000000000000000; + r_dl_b__0 <= 32'b00000000000000000000000000000000; + r_numer__0 <= 0; + r_z1__0 <= 32'b00000000000000000000000000000000; + r_z0__0 <= 32'b00000000000000000000000000000000; + r_mut__0 <= 32'b00000000000000000000000000000000; + end + + else + begin + if(enable) + begin + + //for 0 + r_x__0 <=c_x__0; + r_y__0 <=c_y__0; + r_z__0 <=c_z__0; + r_ux__0 <=c_ux__0; + r_uy__0 <=c_uy__0; + r_uz__0 <=c_uz__0; + r_sz__0 <=c_sz__0; + r_sr__0 <=c_sr__0; + r_sleftz__0 <=c_sleftz__0; + r_sleftr__0 <=c_sleftr__0; + r_weight__0 <=c_weight__0; + r_layer__0 <=c_layer__0; + r_dead__0 <=c_dead__0; + r_hit__0 <=c_hit__0; + r_diff__0 <=c_diff__0; + r_dl_b__0 <=c_dl_b__0; + r_numer__0 <=c_numer__0; + r_z1__0 <=c_z1__0; + r_z0__0 <=c_z0__0; + r_mut__0 <=c_mut__0; + + //for 1 + + r_x__1 <=c_x__1; + r_y__1 <=c_y__1; + r_z__1 <=c_z__1; + r_ux__1 <=c_ux__1; + r_uy__1 <=c_uy__1; + r_uz__1 <=c_uz__1; + r_sz__1 <=c_sz__1; + r_sr__1 <=c_sr__1; + r_sleftz__1 <=c_sleftz__1; + r_sleftr__1 <=c_sleftr__1; + r_weight__1 <=c_weight__1; + r_layer__1 <=c_layer__1; + r_dead__1 <=c_dead__1; + r_hit__1 <=c_hit__1; + r_diff__1 <=c_diff__1; + r_dl_b__1 <=c_dl_b__1; + r_numer__1 <=c_numer__1; + r_z1__1 <=c_z1__1; + r_z0__1 <=c_z0__1; + r_mut__1 <=c_mut__1; + + //for 2 + r_x__2 <=c_x__2; + r_y__2 <=c_y__2; + r_z__2 <=c_z__2; + r_ux__2 <=c_ux__2; + r_uy__2 <=c_uy__2; + r_uz__2 <=c_uz__2; + r_sz__2 <=c_sz__2; + r_sr__2 <=c_sr__2; + r_sleftz__2 <=c_sleftz__2; + r_sleftr__2 <=c_sleftr__2; + r_weight__2 <=c_weight__2; + r_layer__2 <=c_layer__2; + r_dead__2 <=c_dead__2; + r_hit__2 <=c_hit__2; + r_diff__2 <=c_diff__2; + r_dl_b__2 <=c_dl_b__2; + r_numer__2 <=c_numer__2; + r_z1__2 <=c_z1__2; + r_z0__2 <=c_z0__2; + r_mut__2 <=c_mut__2; + + //for 3 + r_x__3 <=c_x__3; + r_y__3 <=c_y__3; + r_z__3 <=c_z__3; + r_ux__3 <=c_ux__3; + r_uy__3 <=c_uy__3; + r_uz__3 <=c_uz__3; + r_sz__3 <=c_sz__3; + r_sr__3 <=c_sr__3; + r_sleftz__3 <=c_sleftz__3; + r_sleftr__3 <=c_sleftr__3; + r_weight__3 <=c_weight__3; + r_layer__3 <=c_layer__3; + r_dead__3 <=c_dead__3; + r_hit__3 <=c_hit__3; + r_diff__3 <=c_diff__3; + r_dl_b__3 <=c_dl_b__3; + r_numer__3 <=c_numer__3; + r_z1__3 <=c_z1__3; + r_z0__3 <=c_z0__3; + r_mut__3 <=c_mut__3; + + //for 4 + r_x__4 <=c_x__4; + r_y__4 <=c_y__4; + r_z__4 <=c_z__4; + r_ux__4 <=c_ux__4; + r_uy__4 <=c_uy__4; + r_uz__4 <=c_uz__4; + r_sz__4 <=c_sz__4; + r_sr__4 <=c_sr__4; + r_sleftz__4 <=c_sleftz__4; + r_sleftr__4 <=c_sleftr__4; + r_weight__4 <=c_weight__4; + r_layer__4 <=c_layer__4; + r_dead__4 <=c_dead__4; + r_hit__4 <=c_hit__4; + r_diff__4 <=c_diff__4; + r_dl_b__4 <=c_dl_b__4; + r_numer__4 <=c_numer__4; + r_z1__4 <=c_z1__4; + r_z0__4 <=c_z0__4; + r_mut__4 <=c_mut__4; + + //for 5 + r_x__5 <=c_x__5; + r_y__5 <=c_y__5; + r_z__5 <=c_z__5; + r_ux__5 <=c_ux__5; + r_uy__5 <=c_uy__5; + r_uz__5 <=c_uz__5; + r_sz__5 <=c_sz__5; + r_sr__5 <=c_sr__5; + r_sleftz__5 <=c_sleftz__5; + r_sleftr__5 <=c_sleftr__5; + r_weight__5 <=c_weight__5; + r_layer__5 <=c_layer__5; + r_dead__5 <=c_dead__5; + r_hit__5 <=c_hit__5; + r_diff__5 <=c_diff__5; + r_dl_b__5 <=c_dl_b__5; + r_numer__5 <=c_numer__5; + r_z1__5 <=c_z1__5; + r_z0__5 <=c_z0__5; + r_mut__5 <=c_mut__5; + + //for 6 + r_x__6 <=c_x__6; + r_y__6 <=c_y__6; + r_z__6 <=c_z__6; + r_ux__6 <=c_ux__6; + r_uy__6 <=c_uy__6; + r_uz__6 <=c_uz__6; + r_sz__6 <=c_sz__6; + r_sr__6 <=c_sr__6; + r_sleftz__6 <=c_sleftz__6; + r_sleftr__6 <=c_sleftr__6; + r_weight__6 <=c_weight__6; + r_layer__6 <=c_layer__6; + r_dead__6 <=c_dead__6; + r_hit__6 <=c_hit__6; + r_diff__6 <=c_diff__6; + r_dl_b__6 <=c_dl_b__6; + r_numer__6 <=c_numer__6; + r_z1__6 <=c_z1__6; + r_z0__6 <=c_z0__6; + r_mut__6 <=c_mut__6; + + //for 7 + r_x__7 <=c_x__7; + r_y__7 <=c_y__7; + r_z__7 <=c_z__7; + r_ux__7 <=c_ux__7; + r_uy__7 <=c_uy__7; + r_uz__7 <=c_uz__7; + r_sz__7 <=c_sz__7; + r_sr__7 <=c_sr__7; + r_sleftz__7 <=c_sleftz__7; + r_sleftr__7 <=c_sleftr__7; + r_weight__7 <=c_weight__7; + r_layer__7 <=c_layer__7; + r_dead__7 <=c_dead__7; + r_hit__7 <=c_hit__7; + r_diff__7 <=c_diff__7; + r_dl_b__7 <=c_dl_b__7; + r_numer__7 <=c_numer__7; + r_z1__7 <=c_z1__7; + r_z0__7 <=c_z0__7; + r_mut__7 <=c_mut__7; + + //for 8 + r_x__8 <=c_x__8; + r_y__8 <=c_y__8; + r_z__8 <=c_z__8; + r_ux__8 <=c_ux__8; + r_uy__8 <=c_uy__8; + r_uz__8 <=c_uz__8; + r_sz__8 <=c_sz__8; + r_sr__8 <=c_sr__8; + r_sleftz__8 <=c_sleftz__8; + r_sleftr__8 <=c_sleftr__8; + r_weight__8 <=c_weight__8; + r_layer__8 <=c_layer__8; + r_dead__8 <=c_dead__8; + r_hit__8 <=c_hit__8; + r_diff__8 <=c_diff__8; + r_dl_b__8 <=c_dl_b__8; + r_numer__8 <=c_numer__8; + r_z1__8 <=c_z1__8; + r_z0__8 <=c_z0__8; + r_mut__8 <=c_mut__8; + + //for 9 + r_x__9 <=c_x__9; + r_y__9 <=c_y__9; + r_z__9 <=c_z__9; + r_ux__9 <=c_ux__9; + r_uy__9 <=c_uy__9; + r_uz__9 <=c_uz__9; + r_sz__9 <=c_sz__9; + r_sr__9 <=c_sr__9; + r_sleftz__9 <=c_sleftz__9; + r_sleftr__9 <=c_sleftr__9; + r_weight__9 <=c_weight__9; + r_layer__9 <=c_layer__9; + r_dead__9 <=c_dead__9; + r_hit__9 <=c_hit__9; + r_diff__9 <=c_diff__9; + r_dl_b__9 <=c_dl_b__9; + r_numer__9 <=c_numer__9; + r_z1__9 <=c_z1__9; + r_z0__9 <=c_z0__9; + r_mut__9 <=c_mut__9; + + //for 10 + r_x__10 <=c_x__10; + r_y__10 <=c_y__10; + r_z__10 <=c_z__10; + r_ux__10 <=c_ux__10; + r_uy__10 <=c_uy__10; + r_uz__10 <=c_uz__10; + r_sz__10 <=c_sz__10; + r_sr__10 <=c_sr__10; + r_sleftz__10 <=c_sleftz__10; + r_sleftr__10 <=c_sleftr__10; + r_weight__10 <=c_weight__10; + r_layer__10 <=c_layer__10; + r_dead__10 <=c_dead__10; + r_hit__10 <=c_hit__10; + r_diff__10 <=c_diff__10; + r_dl_b__10 <=c_dl_b__10; + r_numer__10 <=c_numer__10; + r_z1__10 <=c_z1__10; + r_z0__10 <=c_z0__10; + r_mut__10 <=c_mut__10; + + //for 11 + r_x__11 <=c_x__11; + r_y__11 <=c_y__11; + r_z__11 <=c_z__11; + r_ux__11 <=c_ux__11; + r_uy__11 <=c_uy__11; + r_uz__11 <=c_uz__11; + r_sz__11 <=c_sz__11; + r_sr__11 <=c_sr__11; + r_sleftz__11 <=c_sleftz__11; + r_sleftr__11 <=c_sleftr__11; + r_weight__11 <=c_weight__11; + r_layer__11 <=c_layer__11; + r_dead__11 <=c_dead__11; + r_hit__11 <=c_hit__11; + r_diff__11 <=c_diff__11; + r_dl_b__11 <=c_dl_b__11; + r_numer__11 <=c_numer__11; + r_z1__11 <=c_z1__11; + r_z0__11 <=c_z0__11; + r_mut__11 <=c_mut__11; + + //for 12 + r_x__12 <=c_x__12; + r_y__12 <=c_y__12; + r_z__12 <=c_z__12; + r_ux__12 <=c_ux__12; + r_uy__12 <=c_uy__12; + r_uz__12 <=c_uz__12; + r_sz__12 <=c_sz__12; + r_sr__12 <=c_sr__12; + r_sleftz__12 <=c_sleftz__12; + r_sleftr__12 <=c_sleftr__12; + r_weight__12 <=c_weight__12; + r_layer__12 <=c_layer__12; + r_dead__12 <=c_dead__12; + r_hit__12 <=c_hit__12; + r_diff__12 <=c_diff__12; + r_dl_b__12 <=c_dl_b__12; + r_numer__12 <=c_numer__12; + r_z1__12 <=c_z1__12; + r_z0__12 <=c_z0__12; + r_mut__12 <=c_mut__12; + + //for 13 + r_x__13 <=c_x__13; + r_y__13 <=c_y__13; + r_z__13 <=c_z__13; + r_ux__13 <=c_ux__13; + r_uy__13 <=c_uy__13; + r_uz__13 <=c_uz__13; + r_sz__13 <=c_sz__13; + r_sr__13 <=c_sr__13; + r_sleftz__13 <=c_sleftz__13; + r_sleftr__13 <=c_sleftr__13; + r_weight__13 <=c_weight__13; + r_layer__13 <=c_layer__13; + r_dead__13 <=c_dead__13; + r_hit__13 <=c_hit__13; + r_diff__13 <=c_diff__13; + r_dl_b__13 <=c_dl_b__13; + r_numer__13 <=c_numer__13; + r_z1__13 <=c_z1__13; + r_z0__13 <=c_z0__13; + r_mut__13 <=c_mut__13; + + //for 14 + r_x__14 <=c_x__14; + r_y__14 <=c_y__14; + r_z__14 <=c_z__14; + r_ux__14 <=c_ux__14; + r_uy__14 <=c_uy__14; + r_uz__14 <=c_uz__14; + r_sz__14 <=c_sz__14; + r_sr__14 <=c_sr__14; + r_sleftz__14 <=c_sleftz__14; + r_sleftr__14 <=c_sleftr__14; + r_weight__14 <=c_weight__14; + r_layer__14 <=c_layer__14; + r_dead__14 <=c_dead__14; + r_hit__14 <=c_hit__14; + r_diff__14 <=c_diff__14; + r_dl_b__14 <=c_dl_b__14; + r_numer__14 <=c_numer__14; + r_z1__14 <=c_z1__14; + r_z0__14 <=c_z0__14; + r_mut__14 <=c_mut__14; + + //for 15 + r_x__15 <=c_x__15; + r_y__15 <=c_y__15; + r_z__15 <=c_z__15; + r_ux__15 <=c_ux__15; + r_uy__15 <=c_uy__15; + r_uz__15 <=c_uz__15; + r_sz__15 <=c_sz__15; + r_sr__15 <=c_sr__15; + r_sleftz__15 <=c_sleftz__15; + r_sleftr__15 <=c_sleftr__15; + r_weight__15 <=c_weight__15; + r_layer__15 <=c_layer__15; + r_dead__15 <=c_dead__15; + r_hit__15 <=c_hit__15; + r_diff__15 <=c_diff__15; + r_dl_b__15 <=c_dl_b__15; + r_numer__15 <=c_numer__15; + r_z1__15 <=c_z1__15; + r_z0__15 <=c_z0__15; + r_mut__15 <=c_mut__15; + + //for 16 + r_x__16 <=c_x__16; + r_y__16 <=c_y__16; + r_z__16 <=c_z__16; + r_ux__16 <=c_ux__16; + r_uy__16 <=c_uy__16; + r_uz__16 <=c_uz__16; + r_sz__16 <=c_sz__16; + r_sr__16 <=c_sr__16; + r_sleftz__16 <=c_sleftz__16; + r_sleftr__16 <=c_sleftr__16; + r_weight__16 <=c_weight__16; + r_layer__16 <=c_layer__16; + r_dead__16 <=c_dead__16; + r_hit__16 <=c_hit__16; + r_diff__16 <=c_diff__16; + r_dl_b__16 <=c_dl_b__16; + r_numer__16 <=c_numer__16; + r_z1__16 <=c_z1__16; + r_z0__16 <=c_z0__16; + r_mut__16 <=c_mut__16; + + //for 17 + r_x__17 <=c_x__17; + r_y__17 <=c_y__17; + r_z__17 <=c_z__17; + r_ux__17 <=c_ux__17; + r_uy__17 <=c_uy__17; + r_uz__17 <=c_uz__17; + r_sz__17 <=c_sz__17; + r_sr__17 <=c_sr__17; + r_sleftz__17 <=c_sleftz__17; + r_sleftr__17 <=c_sleftr__17; + r_weight__17 <=c_weight__17; + r_layer__17 <=c_layer__17; + r_dead__17 <=c_dead__17; + r_hit__17 <=c_hit__17; + r_diff__17 <=c_diff__17; + r_dl_b__17 <=c_dl_b__17; + r_numer__17 <=c_numer__17; + r_z1__17 <=c_z1__17; + r_z0__17 <=c_z0__17; + r_mut__17 <=c_mut__17; + + //for 18 + r_x__18 <=c_x__18; + r_y__18 <=c_y__18; + r_z__18 <=c_z__18; + r_ux__18 <=c_ux__18; + r_uy__18 <=c_uy__18; + r_uz__18 <=c_uz__18; + r_sz__18 <=c_sz__18; + r_sr__18 <=c_sr__18; + r_sleftz__18 <=c_sleftz__18; + r_sleftr__18 <=c_sleftr__18; + r_weight__18 <=c_weight__18; + r_layer__18 <=c_layer__18; + r_dead__18 <=c_dead__18; + r_hit__18 <=c_hit__18; + r_diff__18 <=c_diff__18; + r_dl_b__18 <=c_dl_b__18; + r_numer__18 <=c_numer__18; + r_z1__18 <=c_z1__18; + r_z0__18 <=c_z0__18; + r_mut__18 <=c_mut__18; + + //for 19 + r_x__19 <=c_x__19; + r_y__19 <=c_y__19; + r_z__19 <=c_z__19; + r_ux__19 <=c_ux__19; + r_uy__19 <=c_uy__19; + r_uz__19 <=c_uz__19; + r_sz__19 <=c_sz__19; + r_sr__19 <=c_sr__19; + r_sleftz__19 <=c_sleftz__19; + r_sleftr__19 <=c_sleftr__19; + r_weight__19 <=c_weight__19; + r_layer__19 <=c_layer__19; + r_dead__19 <=c_dead__19; + r_hit__19 <=c_hit__19; + r_diff__19 <=c_diff__19; + r_dl_b__19 <=c_dl_b__19; + r_numer__19 <=c_numer__19; + r_z1__19 <=c_z1__19; + r_z0__19 <=c_z0__19; + r_mut__19 <=c_mut__19; + + //for 20 + r_x__20 <=c_x__20; + r_y__20 <=c_y__20; + r_z__20 <=c_z__20; + r_ux__20 <=c_ux__20; + r_uy__20 <=c_uy__20; + r_uz__20 <=c_uz__20; + r_sz__20 <=c_sz__20; + r_sr__20 <=c_sr__20; + r_sleftz__20 <=c_sleftz__20; + r_sleftr__20 <=c_sleftr__20; + r_weight__20 <=c_weight__20; + r_layer__20 <=c_layer__20; + r_dead__20 <=c_dead__20; + r_hit__20 <=c_hit__20; + r_diff__20 <=c_diff__20; + r_dl_b__20 <=c_dl_b__20; + r_numer__20 <=c_numer__20; + r_z1__20 <=c_z1__20; + r_z0__20 <=c_z0__20; + r_mut__20 <=c_mut__20; + + + //for 21 + r_x__21 <=c_x__21; + r_y__21 <=c_y__21; + r_z__21 <=c_z__21; + r_ux__21 <=c_ux__21; + r_uy__21 <=c_uy__21; + r_uz__21 <=c_uz__21; + r_sz__21 <=c_sz__21; + r_sr__21 <=c_sr__21; + r_sleftz__21 <=c_sleftz__21; + r_sleftr__21 <=c_sleftr__21; + r_weight__21 <=c_weight__21; + r_layer__21 <=c_layer__21; + r_dead__21 <=c_dead__21; + r_hit__21 <=c_hit__21; + r_diff__21 <=c_diff__21; + r_dl_b__21 <=c_dl_b__21; + r_numer__21 <=c_numer__21; + r_z1__21 <=c_z1__21; + r_z0__21 <=c_z0__21; + r_mut__21 <=c_mut__21; + + //for 22 + r_x__22 <=c_x__22; + r_y__22 <=c_y__22; + r_z__22 <=c_z__22; + r_ux__22 <=c_ux__22; + r_uy__22 <=c_uy__22; + r_uz__22 <=c_uz__22; + r_sz__22 <=c_sz__22; + r_sr__22 <=c_sr__22; + r_sleftz__22 <=c_sleftz__22; + r_sleftr__22 <=c_sleftr__22; + r_weight__22 <=c_weight__22; + r_layer__22 <=c_layer__22; + r_dead__22 <=c_dead__22; + r_hit__22 <=c_hit__22; + r_diff__22 <=c_diff__22; + r_dl_b__22 <=c_dl_b__22; + r_numer__22 <=c_numer__22; + r_z1__22 <=c_z1__22; + r_z0__22 <=c_z0__22; + r_mut__22 <=c_mut__22; + + //for 23 + r_x__23 <=c_x__23; + r_y__23 <=c_y__23; + r_z__23 <=c_z__23; + r_ux__23 <=c_ux__23; + r_uy__23 <=c_uy__23; + r_uz__23 <=c_uz__23; + r_sz__23 <=c_sz__23; + r_sr__23 <=c_sr__23; + r_sleftz__23 <=c_sleftz__23; + r_sleftr__23 <=c_sleftr__23; + r_weight__23 <=c_weight__23; + r_layer__23 <=c_layer__23; + r_dead__23 <=c_dead__23; + r_hit__23 <=c_hit__23; + r_diff__23 <=c_diff__23; + r_dl_b__23 <=c_dl_b__23; + r_numer__23 <=c_numer__23; + r_z1__23 <=c_z1__23; + r_z0__23 <=c_z0__23; + r_mut__23 <=c_mut__23; + + //for 24 + r_x__24 <=c_x__24; + r_y__24 <=c_y__24; + r_z__24 <=c_z__24; + r_ux__24 <=c_ux__24; + r_uy__24 <=c_uy__24; + r_uz__24 <=c_uz__24; + r_sz__24 <=c_sz__24; + r_sr__24 <=c_sr__24; + r_sleftz__24 <=c_sleftz__24; + r_sleftr__24 <=c_sleftr__24; + r_weight__24 <=c_weight__24; + r_layer__24 <=c_layer__24; + r_dead__24 <=c_dead__24; + r_hit__24 <=c_hit__24; + r_diff__24 <=c_diff__24; + r_dl_b__24 <=c_dl_b__24; + r_numer__24 <=c_numer__24; + r_z1__24 <=c_z1__24; + r_z0__24 <=c_z0__24; + r_mut__24 <=c_mut__24; + + //for 25 + r_x__25 <=c_x__25; + r_y__25 <=c_y__25; + r_z__25 <=c_z__25; + r_ux__25 <=c_ux__25; + r_uy__25 <=c_uy__25; + r_uz__25 <=c_uz__25; + r_sz__25 <=c_sz__25; + r_sr__25 <=c_sr__25; + r_sleftz__25 <=c_sleftz__25; + r_sleftr__25 <=c_sleftr__25; + r_weight__25 <=c_weight__25; + r_layer__25 <=c_layer__25; + r_dead__25 <=c_dead__25; + r_hit__25 <=c_hit__25; + r_diff__25 <=c_diff__25; + r_dl_b__25 <=c_dl_b__25; + r_numer__25 <=c_numer__25; + r_z1__25 <=c_z1__25; + r_z0__25 <=c_z0__25; + r_mut__25 <=c_mut__25; + + //for 26 + r_x__26 <=c_x__26; + r_y__26 <=c_y__26; + r_z__26 <=c_z__26; + r_ux__26 <=c_ux__26; + r_uy__26 <=c_uy__26; + r_uz__26 <=c_uz__26; + r_sz__26 <=c_sz__26; + r_sr__26 <=c_sr__26; + r_sleftz__26 <=c_sleftz__26; + r_sleftr__26 <=c_sleftr__26; + r_weight__26 <=c_weight__26; + r_layer__26 <=c_layer__26; + r_dead__26 <=c_dead__26; + r_hit__26 <=c_hit__26; + r_diff__26 <=c_diff__26; + r_dl_b__26 <=c_dl_b__26; + r_numer__26 <=c_numer__26; + r_z1__26 <=c_z1__26; + r_z0__26 <=c_z0__26; + r_mut__26 <=c_mut__26; + + //for 27 + r_x__27 <=c_x__27; + r_y__27 <=c_y__27; + r_z__27 <=c_z__27; + r_ux__27 <=c_ux__27; + r_uy__27 <=c_uy__27; + r_uz__27 <=c_uz__27; + r_sz__27 <=c_sz__27; + r_sr__27 <=c_sr__27; + r_sleftz__27 <=c_sleftz__27; + r_sleftr__27 <=c_sleftr__27; + r_weight__27 <=c_weight__27; + r_layer__27 <=c_layer__27; + r_dead__27 <=c_dead__27; + r_hit__27 <=c_hit__27; + r_diff__27 <=c_diff__27; + r_dl_b__27 <=c_dl_b__27; + r_numer__27 <=c_numer__27; + r_z1__27 <=c_z1__27; + r_z0__27 <=c_z0__27; + r_mut__27 <=c_mut__27; + + //for 28 + r_x__28 <=c_x__28; + r_y__28 <=c_y__28; + r_z__28 <=c_z__28; + r_ux__28 <=c_ux__28; + r_uy__28 <=c_uy__28; + r_uz__28 <=c_uz__28; + r_sz__28 <=c_sz__28; + r_sr__28 <=c_sr__28; + r_sleftz__28 <=c_sleftz__28; + r_sleftr__28 <=c_sleftr__28; + r_weight__28 <=c_weight__28; + r_layer__28 <=c_layer__28; + r_dead__28 <=c_dead__28; + r_hit__28 <=c_hit__28; + r_diff__28 <=c_diff__28; + r_dl_b__28 <=c_dl_b__28; + r_numer__28 <=c_numer__28; + r_z1__28 <=c_z1__28; + r_z0__28 <=c_z0__28; + r_mut__28 <=c_mut__28; + + //for 29 + r_x__29 <=c_x__29; + r_y__29 <=c_y__29; + r_z__29 <=c_z__29; + r_ux__29 <=c_ux__29; + r_uy__29 <=c_uy__29; + r_uz__29 <=c_uz__29; + r_sz__29 <=c_sz__29; + r_sr__29 <=c_sr__29; + r_sleftz__29 <=c_sleftz__29; + r_sleftr__29 <=c_sleftr__29; + r_weight__29 <=c_weight__29; + r_layer__29 <=c_layer__29; + r_dead__29 <=c_dead__29; + r_hit__29 <=c_hit__29; + r_diff__29 <=c_diff__29; + r_dl_b__29 <=c_dl_b__29; + r_numer__29 <=c_numer__29; + r_z1__29 <=c_z1__29; + r_z0__29 <=c_z0__29; + r_mut__29 <=c_mut__29; + + //for 30 + r_x__30 <=c_x__30; + r_y__30 <=c_y__30; + r_z__30 <=c_z__30; + r_ux__30 <=c_ux__30; + r_uy__30 <=c_uy__30; + r_uz__30 <=c_uz__30; + r_sz__30 <=c_sz__30; + r_sr__30 <=c_sr__30; + r_sleftz__30 <=c_sleftz__30; + r_sleftr__30 <=c_sleftr__30; + r_weight__30 <=c_weight__30; + r_layer__30 <=c_layer__30; + r_dead__30 <=c_dead__30; + r_hit__30 <=c_hit__30; + r_diff__30 <=c_diff__30; + r_dl_b__30 <=c_dl_b__30; + r_numer__30 <=c_numer__30; + r_z1__30 <=c_z1__30; + r_z0__30 <=c_z0__30; + r_mut__30 <=c_mut__30; + + //for 31 + r_x__31 <=c_x__31; + r_y__31 <=c_y__31; + r_z__31 <=c_z__31; + r_ux__31 <=c_ux__31; + r_uy__31 <=c_uy__31; + r_uz__31 <=c_uz__31; + r_sz__31 <=c_sz__31; + r_sr__31 <=c_sr__31; + r_sleftz__31 <=c_sleftz__31; + r_sleftr__31 <=c_sleftr__31; + r_weight__31 <=c_weight__31; + r_layer__31 <=c_layer__31; + r_dead__31 <=c_dead__31; + r_hit__31 <=c_hit__31; + r_diff__31 <=c_diff__31; + r_dl_b__31 <=c_dl_b__31; + r_numer__31 <=c_numer__31; + r_z1__31 <=c_z1__31; + r_z0__31 <=c_z0__31; + r_mut__31 <=c_mut__31; + + //for 32 + r_x__32 <=c_x__32; + r_y__32 <=c_y__32; + r_z__32 <=c_z__32; + r_ux__32 <=c_ux__32; + r_uy__32 <=c_uy__32; + r_uz__32 <=c_uz__32; + r_sz__32 <=c_sz__32; + r_sr__32 <=c_sr__32; + r_sleftz__32 <=c_sleftz__32; + r_sleftr__32 <=c_sleftr__32; + r_weight__32 <=c_weight__32; + r_layer__32 <=c_layer__32; + r_dead__32 <=c_dead__32; + r_hit__32 <=c_hit__32; + r_diff__32 <=c_diff__32; + r_dl_b__32 <=c_dl_b__32; + r_numer__32 <=c_numer__32; + r_z1__32 <=c_z1__32; + r_z0__32 <=c_z0__32; + r_mut__32 <=c_mut__32; + + //for 33 + r_x__33 <=c_x__33; + r_y__33 <=c_y__33; + r_z__33 <=c_z__33; + r_ux__33 <=c_ux__33; + r_uy__33 <=c_uy__33; + r_uz__33 <=c_uz__33; + r_sz__33 <=c_sz__33; + r_sr__33 <=c_sr__33; + r_sleftz__33 <=c_sleftz__33; + r_sleftr__33 <=c_sleftr__33; + r_weight__33 <=c_weight__33; + r_layer__33 <=c_layer__33; + r_dead__33 <=c_dead__33; + r_hit__33 <=c_hit__33; + r_diff__33 <=c_diff__33; + r_dl_b__33 <=c_dl_b__33; + r_numer__33 <=c_numer__33; + r_z1__33 <=c_z1__33; + r_z0__33 <=c_z0__33; + r_mut__33 <=c_mut__33; + + //for 34 + r_x__34 <=c_x__34; + r_y__34 <=c_y__34; + r_z__34 <=c_z__34; + r_ux__34 <=c_ux__34; + r_uy__34 <=c_uy__34; + r_uz__34 <=c_uz__34; + r_sz__34 <=c_sz__34; + r_sr__34 <=c_sr__34; + r_sleftz__34 <=c_sleftz__34; + r_sleftr__34 <=c_sleftr__34; + r_weight__34 <=c_weight__34; + r_layer__34 <=c_layer__34; + r_dead__34 <=c_dead__34; + r_hit__34 <=c_hit__34; + r_diff__34 <=c_diff__34; + r_dl_b__34 <=c_dl_b__34; + r_numer__34 <=c_numer__34; + r_z1__34 <=c_z1__34; + r_z0__34 <=c_z0__34; + r_mut__34 <=c_mut__34; + + //for 35 + r_x__35 <=c_x__35; + r_y__35 <=c_y__35; + r_z__35 <=c_z__35; + r_ux__35 <=c_ux__35; + r_uy__35 <=c_uy__35; + r_uz__35 <=c_uz__35; + r_sz__35 <=c_sz__35; + r_sr__35 <=c_sr__35; + r_sleftz__35 <=c_sleftz__35; + r_sleftr__35 <=c_sleftr__35; + r_weight__35 <=c_weight__35; + r_layer__35 <=c_layer__35; + r_dead__35 <=c_dead__35; + r_hit__35 <=c_hit__35; + r_diff__35 <=c_diff__35; + r_dl_b__35 <=c_dl_b__35; + r_numer__35 <=c_numer__35; + r_z1__35 <=c_z1__35; + r_z0__35 <=c_z0__35; + r_mut__35 <=c_mut__35; + + //for 36 + r_x__36 <=c_x__36; + r_y__36 <=c_y__36; + r_z__36 <=c_z__36; + r_ux__36 <=c_ux__36; + r_uy__36 <=c_uy__36; + r_uz__36 <=c_uz__36; + r_sz__36 <=c_sz__36; + r_sr__36 <=c_sr__36; + r_sleftz__36 <=c_sleftz__36; + r_sleftr__36 <=c_sleftr__36; + r_weight__36 <=c_weight__36; + r_layer__36 <=c_layer__36; + r_dead__36 <=c_dead__36; + r_hit__36 <=c_hit__36; + r_diff__36 <=c_diff__36; + r_dl_b__36 <=c_dl_b__36; + r_numer__36 <=c_numer__36; + r_z1__36 <=c_z1__36; + r_z0__36 <=c_z0__36; + r_mut__36 <=c_mut__36; + + //for 37 + r_x__37 <=c_x__37; + r_y__37 <=c_y__37; + r_z__37 <=c_z__37; + r_ux__37 <=c_ux__37; + r_uy__37 <=c_uy__37; + r_uz__37 <=c_uz__37; + r_sz__37 <=c_sz__37; + r_sr__37 <=c_sr__37; + r_sleftz__37 <=c_sleftz__37; + r_sleftr__37 <=c_sleftr__37; + r_weight__37 <=c_weight__37; + r_layer__37 <=c_layer__37; + r_dead__37 <=c_dead__37; + r_hit__37 <=c_hit__37; + r_diff__37 <=c_diff__37; + r_dl_b__37 <=c_dl_b__37; + r_numer__37 <=c_numer__37; + r_z1__37 <=c_z1__37; + r_z0__37 <=c_z0__37; + r_mut__37 <=c_mut__37; + + //for 38 + r_x__38 <=c_x__38; + r_y__38 <=c_y__38; + r_z__38 <=c_z__38; + r_ux__38 <=c_ux__38; + r_uy__38 <=c_uy__38; + r_uz__38 <=c_uz__38; + r_sz__38 <=c_sz__38; + r_sr__38 <=c_sr__38; + r_sleftz__38 <=c_sleftz__38; + r_sleftr__38 <=c_sleftr__38; + r_weight__38 <=c_weight__38; + r_layer__38 <=c_layer__38; + r_dead__38 <=c_dead__38; + r_hit__38 <=c_hit__38; + r_diff__38 <=c_diff__38; + r_dl_b__38 <=c_dl_b__38; + r_numer__38 <=c_numer__38; + r_z1__38 <=c_z1__38; + r_z0__38 <=c_z0__38; + r_mut__38 <=c_mut__38; + + //for 39 + r_x__39 <=c_x__39; + r_y__39 <=c_y__39; + r_z__39 <=c_z__39; + r_ux__39 <=c_ux__39; + r_uy__39 <=c_uy__39; + r_uz__39 <=c_uz__39; + r_sz__39 <=c_sz__39; + r_sr__39 <=c_sr__39; + r_sleftz__39 <=c_sleftz__39; + r_sleftr__39 <=c_sleftr__39; + r_weight__39 <=c_weight__39; + r_layer__39 <=c_layer__39; + r_dead__39 <=c_dead__39; + r_hit__39 <=c_hit__39; + r_diff__39 <=c_diff__39; + r_dl_b__39 <=c_dl_b__39; + r_numer__39 <=c_numer__39; + r_z1__39 <=c_z1__39; + r_z0__39 <=c_z0__39; + r_mut__39 <=c_mut__39; + + //for 40 + r_x__40 <=c_x__40; + r_y__40 <=c_y__40; + r_z__40 <=c_z__40; + r_ux__40 <=c_ux__40; + r_uy__40 <=c_uy__40; + r_uz__40 <=c_uz__40; + r_sz__40 <=c_sz__40; + r_sr__40 <=c_sr__40; + r_sleftz__40 <=c_sleftz__40; + r_sleftr__40 <=c_sleftr__40; + r_weight__40 <=c_weight__40; + r_layer__40 <=c_layer__40; + r_dead__40 <=c_dead__40; + r_hit__40 <=c_hit__40; + r_diff__40 <=c_diff__40; + r_dl_b__40 <=c_dl_b__40; + r_numer__40 <=c_numer__40; + r_z1__40 <=c_z1__40; + r_z0__40 <=c_z0__40; + r_mut__40 <=c_mut__40; + + //for 41 + r_x__41 <=c_x__41; + r_y__41 <=c_y__41; + r_z__41 <=c_z__41; + r_ux__41 <=c_ux__41; + r_uy__41 <=c_uy__41; + r_uz__41 <=c_uz__41; + r_sz__41 <=c_sz__41; + r_sr__41 <=c_sr__41; + r_sleftz__41 <=c_sleftz__41; + r_sleftr__41 <=c_sleftr__41; + r_weight__41 <=c_weight__41; + r_layer__41 <=c_layer__41; + r_dead__41 <=c_dead__41; + r_hit__41 <=c_hit__41; + r_diff__41 <=c_diff__41; + r_dl_b__41 <=c_dl_b__41; + r_numer__41 <=c_numer__41; + r_z1__41 <=c_z1__41; + r_z0__41 <=c_z0__41; + r_mut__41 <=c_mut__41; + + //for 42 + r_x__42 <=c_x__42; + r_y__42 <=c_y__42; + r_z__42 <=c_z__42; + r_ux__42 <=c_ux__42; + r_uy__42 <=c_uy__42; + r_uz__42 <=c_uz__42; + r_sz__42 <=c_sz__42; + r_sr__42 <=c_sr__42; + r_sleftz__42 <=c_sleftz__42; + r_sleftr__42 <=c_sleftr__42; + r_weight__42 <=c_weight__42; + r_layer__42 <=c_layer__42; + r_dead__42 <=c_dead__42; + r_hit__42 <=c_hit__42; + r_diff__42 <=c_diff__42; + r_dl_b__42 <=c_dl_b__42; + r_numer__42 <=c_numer__42; + r_z1__42 <=c_z1__42; + r_z0__42 <=c_z0__42; + r_mut__42 <=c_mut__42; + + //for 43 + r_x__43 <=c_x__43; + r_y__43 <=c_y__43; + r_z__43 <=c_z__43; + r_ux__43 <=c_ux__43; + r_uy__43 <=c_uy__43; + r_uz__43 <=c_uz__43; + r_sz__43 <=c_sz__43; + r_sr__43 <=c_sr__43; + r_sleftz__43 <=c_sleftz__43; + r_sleftr__43 <=c_sleftr__43; + r_weight__43 <=c_weight__43; + r_layer__43 <=c_layer__43; + r_dead__43 <=c_dead__43; + r_hit__43 <=c_hit__43; + r_diff__43 <=c_diff__43; + r_dl_b__43 <=c_dl_b__43; + r_numer__43 <=c_numer__43; + r_z1__43 <=c_z1__43; + r_z0__43 <=c_z0__43; + r_mut__43 <=c_mut__43; + + //for 44 + r_x__44 <=c_x__44; + r_y__44 <=c_y__44; + r_z__44 <=c_z__44; + r_ux__44 <=c_ux__44; + r_uy__44 <=c_uy__44; + r_uz__44 <=c_uz__44; + r_sz__44 <=c_sz__44; + r_sr__44 <=c_sr__44; + r_sleftz__44 <=c_sleftz__44; + r_sleftr__44 <=c_sleftr__44; + r_weight__44 <=c_weight__44; + r_layer__44 <=c_layer__44; + r_dead__44 <=c_dead__44; + r_hit__44 <=c_hit__44; + r_diff__44 <=c_diff__44; + r_dl_b__44 <=c_dl_b__44; + r_numer__44 <=c_numer__44; + r_z1__44 <=c_z1__44; + r_z0__44 <=c_z0__44; + r_mut__44 <=c_mut__44; + + //for 45 + r_x__45 <=c_x__45; + r_y__45 <=c_y__45; + r_z__45 <=c_z__45; + r_ux__45 <=c_ux__45; + r_uy__45 <=c_uy__45; + r_uz__45 <=c_uz__45; + r_sz__45 <=c_sz__45; + r_sr__45 <=c_sr__45; + r_sleftz__45 <=c_sleftz__45; + r_sleftr__45 <=c_sleftr__45; + r_weight__45 <=c_weight__45; + r_layer__45 <=c_layer__45; + r_dead__45 <=c_dead__45; + r_hit__45 <=c_hit__45; + r_diff__45 <=c_diff__45; + r_dl_b__45 <=c_dl_b__45; + r_numer__45 <=c_numer__45; + r_z1__45 <=c_z1__45; + r_z0__45 <=c_z0__45; + r_mut__45 <=c_mut__45; + + //for 46 + r_x__46 <=c_x__46; + r_y__46 <=c_y__46; + r_z__46 <=c_z__46; + r_ux__46 <=c_ux__46; + r_uy__46 <=c_uy__46; + r_uz__46 <=c_uz__46; + r_sz__46 <=c_sz__46; + r_sr__46 <=c_sr__46; + r_sleftz__46 <=c_sleftz__46; + r_sleftr__46 <=c_sleftr__46; + r_weight__46 <=c_weight__46; + r_layer__46 <=c_layer__46; + r_dead__46 <=c_dead__46; + r_hit__46 <=c_hit__46; + r_diff__46 <=c_diff__46; + r_dl_b__46 <=c_dl_b__46; + r_numer__46 <=c_numer__46; + r_z1__46 <=c_z1__46; + r_z0__46 <=c_z0__46; + r_mut__46 <=c_mut__46; + + //for 47 + r_x__47 <=c_x__47; + r_y__47 <=c_y__47; + r_z__47 <=c_z__47; + r_ux__47 <=c_ux__47; + r_uy__47 <=c_uy__47; + r_uz__47 <=c_uz__47; + r_sz__47 <=c_sz__47; + r_sr__47 <=c_sr__47; + r_sleftz__47 <=c_sleftz__47; + r_sleftr__47 <=c_sleftr__47; + r_weight__47 <=c_weight__47; + r_layer__47 <=c_layer__47; + r_dead__47 <=c_dead__47; + r_hit__47 <=c_hit__47; + r_diff__47 <=c_diff__47; + r_dl_b__47 <=c_dl_b__47; + r_numer__47 <=c_numer__47; + r_z1__47 <=c_z1__47; + r_z0__47 <=c_z0__47; + r_mut__47 <=c_mut__47; + + //for 48 + r_x__48 <=c_x__48; + r_y__48 <=c_y__48; + r_z__48 <=c_z__48; + r_ux__48 <=c_ux__48; + r_uy__48 <=c_uy__48; + r_uz__48 <=c_uz__48; + r_sz__48 <=c_sz__48; + r_sr__48 <=c_sr__48; + r_sleftz__48 <=c_sleftz__48; + r_sleftr__48 <=c_sleftr__48; + r_weight__48 <=c_weight__48; + r_layer__48 <=c_layer__48; + r_dead__48 <=c_dead__48; + r_hit__48 <=c_hit__48; + r_diff__48 <=c_diff__48; + r_dl_b__48 <=c_dl_b__48; + r_numer__48 <=c_numer__48; + r_z1__48 <=c_z1__48; + r_z0__48 <=c_z0__48; + r_mut__48 <=c_mut__48; + + //for 49 + r_x__49 <=c_x__49; + r_y__49 <=c_y__49; + r_z__49 <=c_z__49; + r_ux__49 <=c_ux__49; + r_uy__49 <=c_uy__49; + r_uz__49 <=c_uz__49; + r_sz__49 <=c_sz__49; + r_sr__49 <=c_sr__49; + r_sleftz__49 <=c_sleftz__49; + r_sleftr__49 <=c_sleftr__49; + r_weight__49 <=c_weight__49; + r_layer__49 <=c_layer__49; + r_dead__49 <=c_dead__49; + r_hit__49 <=c_hit__49; + r_diff__49 <=c_diff__49; + r_dl_b__49 <=c_dl_b__49; + r_numer__49 <=c_numer__49; + r_z1__49 <=c_z1__49; + r_z0__49 <=c_z0__49; + r_mut__49 <=c_mut__49; + + //for 50 + r_x__50 <=c_x__50; + r_y__50 <=c_y__50; + r_z__50 <=c_z__50; + r_ux__50 <=c_ux__50; + r_uy__50 <=c_uy__50; + r_uz__50 <=c_uz__50; + r_sz__50 <=c_sz__50; + r_sr__50 <=c_sr__50; + r_sleftz__50 <=c_sleftz__50; + r_sleftr__50 <=c_sleftr__50; + r_weight__50 <=c_weight__50; + r_layer__50 <=c_layer__50; + r_dead__50 <=c_dead__50; + r_hit__50 <=c_hit__50; + r_diff__50 <=c_diff__50; + r_dl_b__50 <=c_dl_b__50; + r_numer__50 <=c_numer__50; + r_z1__50 <=c_z1__50; + r_z0__50 <=c_z0__50; + r_mut__50 <=c_mut__50; + + //for 51 + r_x__51 <=c_x__51; + r_y__51 <=c_y__51; + r_z__51 <=c_z__51; + r_ux__51 <=c_ux__51; + r_uy__51 <=c_uy__51; + r_uz__51 <=c_uz__51; + r_sz__51 <=c_sz__51; + r_sr__51 <=c_sr__51; + r_sleftz__51 <=c_sleftz__51; + r_sleftr__51 <=c_sleftr__51; + r_weight__51 <=c_weight__51; + r_layer__51 <=c_layer__51; + r_dead__51 <=c_dead__51; + r_hit__51 <=c_hit__51; + r_diff__51 <=c_diff__51; + r_dl_b__51 <=c_dl_b__51; + r_numer__51 <=c_numer__51; + r_z1__51 <=c_z1__51; + r_z0__51 <=c_z0__51; + r_mut__51 <=c_mut__51; + + //for 52 + r_x__52 <=c_x__52; + r_y__52 <=c_y__52; + r_z__52 <=c_z__52; + r_ux__52 <=c_ux__52; + r_uy__52 <=c_uy__52; + r_uz__52 <=c_uz__52; + r_sz__52 <=c_sz__52; + r_sr__52 <=c_sr__52; + r_sleftz__52 <=c_sleftz__52; + r_sleftr__52 <=c_sleftr__52; + r_weight__52 <=c_weight__52; + r_layer__52 <=c_layer__52; + r_dead__52 <=c_dead__52; + r_hit__52 <=c_hit__52; + r_diff__52 <=c_diff__52; + r_dl_b__52 <=c_dl_b__52; + r_numer__52 <=c_numer__52; + r_z1__52 <=c_z1__52; + r_z0__52 <=c_z0__52; + r_mut__52 <=c_mut__52; + + //for 53 + r_x__53 <=c_x__53; + r_y__53 <=c_y__53; + r_z__53 <=c_z__53; + r_ux__53 <=c_ux__53; + r_uy__53 <=c_uy__53; + r_uz__53 <=c_uz__53; + r_sz__53 <=c_sz__53; + r_sr__53 <=c_sr__53; + r_sleftz__53 <=c_sleftz__53; + r_sleftr__53 <=c_sleftr__53; + r_weight__53 <=c_weight__53; + r_layer__53 <=c_layer__53; + r_dead__53 <=c_dead__53; + r_hit__53 <=c_hit__53; + r_diff__53 <=c_diff__53; + r_dl_b__53 <=c_dl_b__53; + r_numer__53 <=c_numer__53; + r_z1__53 <=c_z1__53; + r_z0__53 <=c_z0__53; + r_mut__53 <=c_mut__53; + + //for 54 + r_x__54 <=c_x__54; + r_y__54 <=c_y__54; + r_z__54 <=c_z__54; + r_ux__54 <=c_ux__54; + r_uy__54 <=c_uy__54; + r_uz__54 <=c_uz__54; + r_sz__54 <=c_sz__54; + r_sr__54 <=c_sr__54; + r_sleftz__54 <=c_sleftz__54; + r_sleftr__54 <=c_sleftr__54; + r_weight__54 <=c_weight__54; + r_layer__54 <=c_layer__54; + r_dead__54 <=c_dead__54; + r_hit__54 <=c_hit__54; + r_diff__54 <=c_diff__54; + r_dl_b__54 <=c_dl_b__54; + r_numer__54 <=c_numer__54; + r_z1__54 <=c_z1__54; + r_z0__54 <=c_z0__54; + r_mut__54 <=c_mut__54; + + //for 55 + r_x__55 <=c_x__55; + r_y__55 <=c_y__55; + r_z__55 <=c_z__55; + r_ux__55 <=c_ux__55; + r_uy__55 <=c_uy__55; + r_uz__55 <=c_uz__55; + r_sz__55 <=c_sz__55; + r_sr__55 <=c_sr__55; + r_sleftz__55 <=c_sleftz__55; + r_sleftr__55 <=c_sleftr__55; + r_weight__55 <=c_weight__55; + r_layer__55 <=c_layer__55; + r_dead__55 <=c_dead__55; + r_hit__55 <=c_hit__55; + r_diff__55 <=c_diff__55; + r_dl_b__55 <=c_dl_b__55; + r_numer__55 <=c_numer__55; + r_z1__55 <=c_z1__55; + r_z0__55 <=c_z0__55; + r_mut__55 <=c_mut__55; + + //for 56 + r_x__56 <=c_x__56; + r_y__56 <=c_y__56; + r_z__56 <=c_z__56; + r_ux__56 <=c_ux__56; + r_uy__56 <=c_uy__56; + r_uz__56 <=c_uz__56; + r_sz__56 <=c_sz__56; + r_sr__56 <=c_sr__56; + r_sleftz__56 <=c_sleftz__56; + r_sleftr__56 <=c_sleftr__56; + r_weight__56 <=c_weight__56; + r_layer__56 <=c_layer__56; + r_dead__56 <=c_dead__56; + r_hit__56 <=c_hit__56; + r_diff__56 <=c_diff__56; + r_dl_b__56 <=c_dl_b__56; + r_numer__56 <=c_numer__56; + r_z1__56 <=c_z1__56; + r_z0__56 <=c_z0__56; + r_mut__56 <=c_mut__56; + + //for 57 + r_x__57 <=c_x__57; + r_y__57 <=c_y__57; + r_z__57 <=c_z__57; + r_ux__57 <=c_ux__57; + r_uy__57 <=c_uy__57; + r_uz__57 <=c_uz__57; + r_sz__57 <=c_sz__57; + r_sr__57 <=c_sr__57; + r_sleftz__57 <=c_sleftz__57; + r_sleftr__57 <=c_sleftr__57; + r_weight__57 <=c_weight__57; + r_layer__57 <=c_layer__57; + r_dead__57 <=c_dead__57; + r_hit__57 <=c_hit__57; + r_diff__57 <=c_diff__57; + r_dl_b__57 <=c_dl_b__57; + r_numer__57 <=c_numer__57; + r_z1__57 <=c_z1__57; + r_z0__57 <=c_z0__57; + r_mut__57 <=c_mut__57; + + //for 58 + r_x__58 <=c_x__58; + r_y__58 <=c_y__58; + r_z__58 <=c_z__58; + r_ux__58 <=c_ux__58; + r_uy__58 <=c_uy__58; + r_uz__58 <=c_uz__58; + r_sz__58 <=c_sz__58; + r_sr__58 <=c_sr__58; + r_sleftz__58 <=c_sleftz__58; + r_sleftr__58 <=c_sleftr__58; + r_weight__58 <=c_weight__58; + r_layer__58 <=c_layer__58; + r_dead__58 <=c_dead__58; + r_hit__58 <=c_hit__58; + r_diff__58 <=c_diff__58; + r_dl_b__58 <=c_dl_b__58; + r_numer__58 <=c_numer__58; + r_z1__58 <=c_z1__58; + r_z0__58 <=c_z0__58; + r_mut__58 <=c_mut__58; + + //for 59 + r_x__59 <=c_x__59; + r_y__59 <=c_y__59; + r_z__59 <=c_z__59; + r_ux__59 <=c_ux__59; + r_uy__59 <=c_uy__59; + r_uz__59 <=c_uz__59; + r_sz__59 <=c_sz__59; + r_sr__59 <=c_sr__59; + r_sleftz__59 <=c_sleftz__59; + r_sleftr__59 <=c_sleftr__59; + r_weight__59 <=c_weight__59; + r_layer__59 <=c_layer__59; + r_dead__59 <=c_dead__59; + r_hit__59 <=c_hit__59; + r_diff__59 <=c_diff__59; + r_dl_b__59 <=c_dl_b__59; + r_numer__59 <=c_numer__59; + r_z1__59 <=c_z1__59; + r_z0__59 <=c_z0__59; + r_mut__59 <=c_mut__59; + + end + end +end + +endmodule + + +///////////////////////////////////////////////////////////// +//mult_signed_32_bc +///////////////////////////////////////////////////////////// +module mult_signed_32_bc ( clock, dataa, datab, result); + + + input clock; + input [31:0] dataa; + input [31:0] datab; + output [63:0] result; + reg [63:0] result; + + wire [63:0] prelim_result; + + + wire [31:0] opa; + wire [31:0] opb; + wire [31:0] opa_comp; + wire [31:0] opb_comp; + + assign opa_comp = ((~dataa) + 32'b00000000000000000000000000000001); + + assign opb_comp = ((~datab) + 32'b00000000000000000000000000000001); + + + wire opa_is_neg; + wire opb_is_neg; + assign opa_is_neg = dataa[31]; + assign opb_is_neg = datab [31]; + assign opa = (opa_is_neg== 1'b1) ? opa_comp:dataa; + assign opb = (opb_is_neg == 1'b1) ? opb_comp:datab; + + + assign prelim_result = opa * opb ; + wire sign; + assign sign = dataa[31] ^ datab[31]; + + wire [63:0] prelim_result_comp; + wire [63:0] prelim_result_changed; + wire [63:0] result_changed; + assign result_changed = (sign==1'b1)? prelim_result_comp :prelim_result; + assign prelim_result_comp = ((~prelim_result) + 1); + + always @ (posedge clock) + begin + result <= result_changed; + end + + endmodule + + +///////////////////////////////////////////////////////////// +//signed_div_30 +///////////////////////////////////////////////////////////// +module signed_div_30 (clock , denom , numer, quotient, remain); + +input clock; + +input [31:0] denom; + +input [63:0] numer; + +output [63:0] quotient; + +output [31:0] remain; + +Div_64b div_replace (.clock(clock), .denom(denom), .numer(numer), .quotient(quotient), .remain(remain)); + +endmodule +module Hop( //INPUTS + clock, reset, enable, + x_boundaryChecker, y_boundaryChecker, z_boundaryChecker, + ux_boundaryChecker, uy_boundaryChecker, uz_boundaryChecker, + sz_boundaryChecker, sr_boundaryChecker, + sleftz_boundaryChecker, sleftr_boundaryChecker, + layer_boundaryChecker, weight_boundaryChecker, dead_boundaryChecker, + hit_boundaryChecker, + + //OUTPUTS + x_hop, y_hop, z_hop, + ux_hop, uy_hop, uz_hop, + sz_hop, sr_hop, + sleftz_hop, sleftr_hop, + layer_hop, weight_hop, dead_hop, hit_hop + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter INTMAX=2147483647; +//parameter INTMIN=-2147483648; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_boundaryChecker; +input [`BIT_WIDTH-1:0] y_boundaryChecker; +input [`BIT_WIDTH-1:0] z_boundaryChecker; +input [`BIT_WIDTH-1:0] ux_boundaryChecker; +input [`BIT_WIDTH-1:0] uy_boundaryChecker; +input [`BIT_WIDTH-1:0] uz_boundaryChecker; +input [`BIT_WIDTH-1:0] sz_boundaryChecker; +input [`BIT_WIDTH-1:0] sr_boundaryChecker; +input [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +input [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +input [`LAYER_WIDTH-1:0] layer_boundaryChecker; +input [`BIT_WIDTH-1:0] weight_boundaryChecker; +input dead_boundaryChecker; +input hit_boundaryChecker; + +output [`BIT_WIDTH-1:0] x_hop; +output [`BIT_WIDTH-1:0] y_hop; +output [`BIT_WIDTH-1:0] z_hop; +output [`BIT_WIDTH-1:0] ux_hop; +output [`BIT_WIDTH-1:0] uy_hop; +output [`BIT_WIDTH-1:0] uz_hop; +output [`BIT_WIDTH-1:0] sz_hop; +output [`BIT_WIDTH-1:0] sr_hop; +output [`BIT_WIDTH-1:0] sleftz_hop; +output [`BIT_WIDTH-1:0] sleftr_hop; +output [`LAYER_WIDTH-1:0]layer_hop; +output [`BIT_WIDTH-1:0] weight_hop; +output dead_hop; +output hit_hop; + +//------------Local Variables------------------------ +reg [`BIT_WIDTH-1:0] c_x; +reg [`BIT_WIDTH-1:0] c_y; +reg [`BIT_WIDTH-1:0] c_z; +reg c_dead; + +reg [`BIT_WIDTH:0] c_x_big; +reg [`BIT_WIDTH:0] c_y_big; +reg [`BIT_WIDTH:0] c_z_big; + +wire [2*`BIT_WIDTH-1:0] c_xmult_big; +wire [2*`BIT_WIDTH-1:0] c_ymult_big; +wire [2*`BIT_WIDTH-1:0] c_zmult_big; + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_hop; +reg [`BIT_WIDTH-1:0] y_hop; +reg [`BIT_WIDTH-1:0] z_hop; +reg [`BIT_WIDTH-1:0] ux_hop; +reg [`BIT_WIDTH-1:0] uy_hop; +reg [`BIT_WIDTH-1:0] uz_hop; +reg [`BIT_WIDTH-1:0] sz_hop; +reg [`BIT_WIDTH-1:0] sr_hop; +reg [`BIT_WIDTH-1:0] sleftz_hop; +reg [`BIT_WIDTH-1:0] sleftr_hop; +reg [`LAYER_WIDTH-1:0]layer_hop; +reg [`BIT_WIDTH-1:0] weight_hop; +reg dead_hop; +reg hit_hop; + +mult_signed_32 u1(sr_boundaryChecker, ux_boundaryChecker, c_xmult_big); +mult_signed_32 u2(sr_boundaryChecker, uy_boundaryChecker, c_ymult_big); +mult_signed_32 u3(sz_boundaryChecker, uz_boundaryChecker, c_zmult_big); + +// Determine new (x,y,z) coordinates +always @(c_dead or + c_x_big or c_y_big or c_z_big or + c_x or c_y or c_z or + x_boundaryChecker or y_boundaryChecker or z_boundaryChecker or + c_xmult_big or c_ymult_big or c_zmult_big + or hit_boundaryChecker or dead_boundaryChecker) +begin + + c_x_big = x_boundaryChecker + c_xmult_big[2*`BIT_WIDTH-2:31]; + c_y_big = y_boundaryChecker + c_ymult_big[2*`BIT_WIDTH-2:31]; + c_z_big = z_boundaryChecker + c_zmult_big[2*`BIT_WIDTH-2:31]; + + + // Calculate x position, photon dies if outside grid + if(c_x_big[`BIT_WIDTH] != c_x_big[`BIT_WIDTH-1] && x_boundaryChecker[`BIT_WIDTH-1] == c_xmult_big[2*`BIT_WIDTH-2]) + begin + if(c_x_big[`BIT_WIDTH] == 1'b0) + begin + // c_dead = 1'b1; + c_x = `INTMAX; + end + else + begin + // c_dead = 1'b1; + c_x = `INTMIN; + end + end + else + begin + c_x = c_x_big[`BIT_WIDTH-1:0]; + end + + + // Calculate y position, photon dies if outside grid + if(c_y_big[`BIT_WIDTH] != c_y_big[`BIT_WIDTH-1] && y_boundaryChecker[`BIT_WIDTH-1] == c_ymult_big[2*`BIT_WIDTH-2]) + begin + if(c_y_big[`BIT_WIDTH] == 1'b0) + begin + // c_dead = 1'b1; + c_y = `INTMAX; + end + else + begin + // c_dead = 1'b1; + c_y = `INTMIN; + end + end + else + begin + c_y = c_y_big[`BIT_WIDTH-1:0]; + end + + // Calculate z position, photon dies if outside grid + if(hit_boundaryChecker) + begin + c_z = z_boundaryChecker; + end + else if(c_z_big[`BIT_WIDTH] != c_z_big[`BIT_WIDTH-1] && z_boundaryChecker[`BIT_WIDTH-1] == c_zmult_big[2*`BIT_WIDTH-2]) + begin + // c_dead = 1'b1; + c_z = `INTMAX; + end + else if (c_z_big[`BIT_WIDTH-1] == 1'b1) + begin + // c_dead = 1'b1; + c_z = 0; + end + else + begin + c_z = c_z_big[`BIT_WIDTH-1:0]; + end + + // Calculate c_dead (necessary because odin does not support block statements). + if( (c_x_big[`BIT_WIDTH] != c_x_big[`BIT_WIDTH-1] && x_boundaryChecker[`BIT_WIDTH-1] == c_xmult_big[2*`BIT_WIDTH-2]) + |(c_y_big[`BIT_WIDTH] != c_y_big[`BIT_WIDTH-1] && y_boundaryChecker[`BIT_WIDTH-1] == c_ymult_big[2*`BIT_WIDTH-2]) + |(c_z_big[`BIT_WIDTH] != c_z_big[`BIT_WIDTH-1] && z_boundaryChecker[`BIT_WIDTH-1] == c_zmult_big[2*`BIT_WIDTH-2]) ) + begin + c_dead = 1'b1; + end + else + begin + c_dead = dead_boundaryChecker; + end + +end + +// latch values +always @ (posedge clock) +begin + if (reset) + begin + // Photon variables + x_hop <= 0; + y_hop <= 0; + z_hop <= 0; + ux_hop <= 0; + uy_hop <= 0; + uz_hop <= 0; + sz_hop <= 0; + sr_hop <= 0; + sleftz_hop <= 0; + sleftr_hop <= 0; + layer_hop <= 0; + weight_hop <= 0; + dead_hop <= 1'b1; + hit_hop <= 1'b0; + end + else + begin + if(enable) + begin + // Photon variables + ux_hop <= ux_boundaryChecker; + uy_hop <= uy_boundaryChecker; + uz_hop <= uz_boundaryChecker; + sz_hop <= sz_boundaryChecker; + sr_hop <= sr_boundaryChecker; + sleftz_hop <= sleftz_boundaryChecker; + sleftr_hop <= sleftr_boundaryChecker; + layer_hop <= layer_boundaryChecker; + weight_hop <= weight_boundaryChecker; + hit_hop <= hit_boundaryChecker; + + x_hop <= c_x; + y_hop <= c_y; + z_hop <= c_z; + dead_hop <= c_dead; + end + end +end + +endmodule + + +///////////////////////////////////////////////////////////// +//mult_signed_32 +///////////////////////////////////////////////////////////// +module mult_signed_32(a, b, c); + input [31:0]a; + input [31:0]b; + output [63:0]c; + reg [63:0]c; + + reg is_neg_a; + reg is_neg_b; + reg [31:0]a_tmp; + reg [31:0]b_tmp; + reg [63:0]c_tmp; + + +always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +begin + + if(a[31] == 1) begin + a_tmp = -a; + is_neg_a = 1; + end else + begin + a_tmp = a; + is_neg_a = 0; + end + + if(b[31] == 1) begin + b_tmp = -b; + is_neg_b = 1; + end else + begin + b_tmp = b; + is_neg_b = 0; + end + + if( is_neg_a != is_neg_b) begin + c_tmp = -(a_tmp * b_tmp); + end else + begin + c_tmp = (a_tmp * b_tmp); + end +end + +always@(c_tmp) +begin + c = c_tmp; +end + +endmodule + + +module Roulette ( //INPUTS + clock, reset, enable, + x_RouletteMux, y_RouletteMux, z_RouletteMux, + ux_RouletteMux, uy_RouletteMux, uz_RouletteMux, + sz_RouletteMux, sr_RouletteMux, + sleftz_RouletteMux, sleftr_RouletteMux, + layer_RouletteMux, weight_absorber, dead_RouletteMux, + + //From Random Number Generator in Skeleton.v + randnumber, + + //OUTPUTS + x_Roulette, y_Roulette, z_Roulette, + ux_Roulette, uy_Roulette, uz_Roulette, + sz_Roulette, sr_Roulette, + sleftz_Roulette, sleftr_Roulette, + layer_Roulette, weight_Roulette, dead_Roulette + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; + +//parameter LEFTSHIFT=3; // 2^3=8=1/0.125 where 0.125 = CHANCE of roulette +//parameter INTCHANCE=536870912; //Based on 32 bit rand num generator +//parameter MIN_WEIGHT=200; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_RouletteMux; +input [`BIT_WIDTH-1:0] y_RouletteMux; +input [`BIT_WIDTH-1:0] z_RouletteMux; +input [`BIT_WIDTH-1:0] ux_RouletteMux; +input [`BIT_WIDTH-1:0] uy_RouletteMux; +input [`BIT_WIDTH-1:0] uz_RouletteMux; +input [`BIT_WIDTH-1:0] sz_RouletteMux; +input [`BIT_WIDTH-1:0] sr_RouletteMux; +input [`BIT_WIDTH-1:0] sleftz_RouletteMux; +input [`BIT_WIDTH-1:0] sleftr_RouletteMux; +input [`LAYER_WIDTH-1:0] layer_RouletteMux; +input [`BIT_WIDTH-1:0] weight_absorber; +input [`BIT_WIDTH-1:0] randnumber; +input dead_RouletteMux; + +output [`BIT_WIDTH-1:0] x_Roulette; +output [`BIT_WIDTH-1:0] y_Roulette; +output [`BIT_WIDTH-1:0] z_Roulette; +output [`BIT_WIDTH-1:0] ux_Roulette; +output [`BIT_WIDTH-1:0] uy_Roulette; +output [`BIT_WIDTH-1:0] uz_Roulette; +output [`BIT_WIDTH-1:0] sz_Roulette; +output [`BIT_WIDTH-1:0] sr_Roulette; +output [`BIT_WIDTH-1:0] sleftz_Roulette; +output [`BIT_WIDTH-1:0] sleftr_Roulette; +output [`LAYER_WIDTH-1:0]layer_Roulette; +output [`BIT_WIDTH-1:0] weight_Roulette; +output dead_Roulette; + +//------------Local Variables------------------------ +reg dead_roulette; +reg [`BIT_WIDTH-1:0] weight_roulette; +reg [31:0] randBits; //Hard-coded bitwidth because rng is 32-bit + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_Roulette; +reg [`BIT_WIDTH-1:0] y_Roulette; +reg [`BIT_WIDTH-1:0] z_Roulette; +reg [`BIT_WIDTH-1:0] ux_Roulette; +reg [`BIT_WIDTH-1:0] uy_Roulette; +reg [`BIT_WIDTH-1:0] uz_Roulette; +reg [`BIT_WIDTH-1:0] sz_Roulette; +reg [`BIT_WIDTH-1:0] sr_Roulette; +reg [`BIT_WIDTH-1:0] sleftz_Roulette; +reg [`BIT_WIDTH-1:0] sleftr_Roulette; +reg [`LAYER_WIDTH-1:0]layer_Roulette; +reg [`BIT_WIDTH-1:0] weight_Roulette; +reg dead_Roulette; + +always @ (reset or enable or weight_absorber or randBits or randnumber or dead_RouletteMux) begin + //Default case moved inside else statements for odin + //randBits = randnumber; //Reading from external random num generator + //weight_roulette=weight_absorber; //Avoid inferring a latch + //dead_roulette=dead_RouletteMux; + + if (reset) begin + //Local variables + weight_roulette=0; + dead_roulette=0; + randBits=0; + end + + else if (enable) begin + //Set default case + randBits = randnumber; + //DO ROULETTE!!! + if (weight_absorber < `MIN_WEIGHT && !dead_RouletteMux) begin + //Replicate Operator (same as 32'b000000..., except more flexible) + if (weight_absorber== {`BIT_WIDTH{1'b0}}) begin + dead_roulette = 1; + weight_roulette = weight_absorber; + end + + else if (randBits < `INTCHANCE) begin // survived the roulette + dead_roulette=0; + weight_roulette=weight_absorber << `LEFTSHIFT; //To avoid mult + end + + else begin + dead_roulette=1; + weight_roulette = weight_absorber; + end + end + + //No Roulette + else begin + weight_roulette = weight_absorber; + dead_roulette = 0; + end + end + + else //for insurance that this is default case + begin + randBits = randnumber; + weight_roulette = weight_absorber; + dead_roulette = dead_RouletteMux; + end +end + +always @ (posedge clock) begin + if (reset) begin + x_Roulette <= 0; + y_Roulette <= 0; + z_Roulette <= 0; + ux_Roulette <= 0; + uy_Roulette <= 0; + uz_Roulette <= 0; + sz_Roulette <= 0; + sr_Roulette <= 0; + sleftz_Roulette <= 0; + sleftr_Roulette <= 0; + layer_Roulette <= 0; + weight_Roulette <= 0; + dead_Roulette <= 1'b1; + end + + else if (enable) begin + //Write through values from Roulette block + dead_Roulette <= (dead_RouletteMux | dead_roulette); //OR operator ??? + weight_Roulette <= weight_roulette; //weight_absorber.read(); + + //Write through unchanged values + x_Roulette <= x_RouletteMux; + y_Roulette <= y_RouletteMux; + z_Roulette <= z_RouletteMux; + + ux_Roulette <= ux_RouletteMux; + uy_Roulette <= uy_RouletteMux; + uz_Roulette <= uz_RouletteMux; + sz_Roulette <= sz_RouletteMux; + sr_Roulette <= sr_RouletteMux; + sleftz_Roulette <= sleftz_RouletteMux; + sleftr_Roulette <= sleftr_RouletteMux; + layer_Roulette <= layer_RouletteMux; + end +end + +endmodule + + +module rng(clk, en, resetn,loadseed_i,seed_i,number_o); +input clk; +input resetn; +input en; +input loadseed_i; +input [31:0] seed_i; +output [31:0] number_o; + +wire [31:0] number_o; + +reg [31:0] c_b1, c_b2, c_b3; +reg [31:0] c_s1, c_s2, c_s3; + +reg [31:0] r_s1, r_s2, r_s3; + +assign number_o = r_s1 ^ r_s2 ^ r_s3; + +always @(loadseed_i or seed_i or r_s1 or r_s2 or r_s3) +begin + if(loadseed_i) + begin + c_b1 = 32'b0; + c_s1 = seed_i; + c_b2 = 32'b0; + c_s2 = {seed_i[5:0], seed_i[17], seed_i[18], seed_i[19], seed_i[20], seed_i[25:21], seed_i[31:26], seed_i[16:6]} ^ 32'd1493609598; + c_b3 = 32'b0; + c_s3 = {seed_i[23:16], seed_i[5], seed_i[6], seed_i[7], seed_i[15:8], seed_i[4:0], seed_i[31:24]} ^ 32'd3447127471; + end + else + begin + c_b1 = (((r_s1 << 13) ^ r_s1) >> 19); + c_s1 = (((r_s1 & 32'd4294967294) << 12) ^ c_b1); + c_b2 = (((r_s2 << 2) ^ r_s2) >> 25); + c_s2 = (((r_s2 & 32'd4294967288) << 4) ^ c_b2); + c_b3 = (((r_s3 << 3) ^ r_s3) >> 11); + c_s3 = (((r_s3 & 32'd4294967280) << 17) ^ c_b3); + end +end + + +//combinate: +always @(posedge clk or negedge resetn) + begin + if (!resetn ) + begin + r_s1 <= 32'b0; + r_s2 <= 32'b0; + r_s3 <= 32'b0; + end + else if (en) //Originally else only + begin + r_s1 <= c_s1; + r_s2 <= c_s2; + r_s3 <= c_s3; + end + end + +endmodule + + + +module LogCalc(clock, reset, enable, in_x, log_x); + +//parameter BIT_WIDTH=32; +//parameter MANTISSA_PRECISION=10; +//parameter LOG2_BIT_WIDTH = 6; +//parameter LOG2=93032639; + +input clock; +input reset; +input enable; +input [`BIT_WIDTH - 1:0] in_x; +output [`BIT_WIDTH - 1:0] log_x; + + +wire [`BIT_WIDTH - 1:0] mantissa; + +reg [`BIT_WIDTH - 1:0] c_mantissa_val; + +// deleted unsigned in these +reg [`BIT_WIDTH - 1:0] c_log_x; +reg [`LOG2_BIT_WIDTH - 1:0] c_indexFirstOne; +reg [`BIT_WIDTH - 1:0] c_temp_shift_x; +reg [`MANTISSA_PRECISION - 1:0] c_shifted_x; + +reg [`LOG2_BIT_WIDTH - 1:0] r_indexFirstOne; +reg [`BIT_WIDTH - 1:0] log_x; + +//Log_mantissa u1(c_shifted_x, clock, mantissa); +wire [31:0]blank; +assign blank = 32'b000000000000000000000000000000; +single_port_ram sram_replace0 (.clk (clock), .addr (c_shifted_x), .data (blank), .we (1'b0), .out (mantissa)); + +// priority encoder +//integer i; +//always @* +//begin +// c_indexFirstOne = 6'b0; +// for(i = 0; i < `BIT_WIDTH; i = i + 1) +// begin +// if(in_x[i]) +// c_indexFirstOne = i; +// end +//end + +// Priority encoder, loop expanded +always @(in_x) +begin + if (in_x[31]) begin + c_indexFirstOne = 6'b011111; + end + else if (in_x[30]) begin + c_indexFirstOne = 6'b011110; + end + else if (in_x[29]) begin + c_indexFirstOne = 6'b011101; + end + else if (in_x[28]) begin + c_indexFirstOne = 6'b011100; + end + else if (in_x[27]) begin + c_indexFirstOne = 6'b011011; + end + else if (in_x[26]) begin + c_indexFirstOne = 6'b011010; + end + else if (in_x[25]) begin + c_indexFirstOne = 6'b011001; + end + else if (in_x[24]) begin + c_indexFirstOne = 6'b011000; + end + else if (in_x[23]) begin + c_indexFirstOne = 6'b010111; + end + else if (in_x[22]) begin + c_indexFirstOne = 6'b010110; + end + else if (in_x[21]) begin + c_indexFirstOne = 6'b010101; + end + else if (in_x[20]) begin + c_indexFirstOne = 6'b010100; + end + else if (in_x[19]) begin + c_indexFirstOne = 6'b010011; + end + else if (in_x[18]) begin + c_indexFirstOne = 6'b010010; + end + else if (in_x[17]) begin + c_indexFirstOne = 6'b010001; + end + else if (in_x[16]) begin + c_indexFirstOne = 6'b010000; + end + else if (in_x[15]) begin + c_indexFirstOne = 6'b001111; + end + else if (in_x[14]) begin + c_indexFirstOne = 6'b001110; + end + else if (in_x[13]) begin + c_indexFirstOne = 6'b001101; + end + else if (in_x[12]) begin + c_indexFirstOne = 6'b001100; + end + else if (in_x[11]) begin + c_indexFirstOne = 6'b001011; + end + else if (in_x[10]) begin + c_indexFirstOne = 6'b001010; + end + else if (in_x[9]) begin + c_indexFirstOne = 6'b001001; + end + else if (in_x[8]) begin + c_indexFirstOne = 6'b001000; + end + else if (in_x[7]) begin + c_indexFirstOne = 6'b000111; + end + else if (in_x[6]) begin + c_indexFirstOne = 6'b000110; + end + else if (in_x[5]) begin + c_indexFirstOne = 6'b000101; + end + else if (in_x[4]) begin + c_indexFirstOne = 6'b000100; + end + else if (in_x[3]) begin + c_indexFirstOne = 6'b000011; + end + else if (in_x[2]) begin + c_indexFirstOne = 6'b000010; + end + else if (in_x[1]) begin + c_indexFirstOne = 6'b000001; + end + else if (in_x[0]) begin + c_indexFirstOne = 6'b000000; + end + else begin + c_indexFirstOne = 6'b000000; + end +end + +// shift operation based on priority encoder results + +//Need constant shift +wire [5:0]shifted; +assign shifted = c_indexFirstOne - `MANTISSA_PRECISION + 1; + +always@(c_indexFirstOne or in_x or shifted) +begin +// c_temp_shift_x = in_x >> (c_indexFirstOne - `MANTISSA_PRECISION + 1); + if(c_indexFirstOne >= `MANTISSA_PRECISION) + begin + if(shifted == 22) begin + c_temp_shift_x = in_x >> 22; + end + else if(shifted == 21) begin + c_temp_shift_x = in_x >> 21; + end + else if(shifted == 20) begin + c_temp_shift_x = in_x >> 20; + end + else if(shifted == 19) begin + c_temp_shift_x = in_x >> 19; + end + else if(shifted == 18) begin + c_temp_shift_x = in_x >> 18; + end + else if(shifted == 17) begin + c_temp_shift_x = in_x >> 17; + end + else if(shifted == 16) begin + c_temp_shift_x = in_x >> 16; + end + else if(shifted == 15) begin + c_temp_shift_x = in_x >> 15; + end + else if(shifted == 14) begin + c_temp_shift_x = in_x >> 14; + end + else if(shifted == 13) begin + c_temp_shift_x = in_x >> 13; + end + else if(shifted == 12) begin + c_temp_shift_x = in_x >> 12; + end + else if(shifted == 11) begin + c_temp_shift_x = in_x >> 11; + end + else if(shifted == 10) begin + c_temp_shift_x = in_x >> 10; + end + else if(shifted == 9) begin + c_temp_shift_x = in_x >> 9; + end + else if(shifted == 8) begin + c_temp_shift_x = in_x >> 8; + end + else if(shifted == 7) begin + c_temp_shift_x = in_x >> 7; + end + else if(shifted == 6) begin + c_temp_shift_x = in_x >> 6; + end + else if(shifted == 5) begin + c_temp_shift_x = in_x >> 5; + end + else if(shifted == 4) begin + c_temp_shift_x = in_x >> 4; + end + else if(shifted == 3) begin + c_temp_shift_x = in_x >> 3; + end + else if(shifted == 2) begin + c_temp_shift_x = in_x >> 2; + end + else if(shifted == 1) begin + c_temp_shift_x = in_x >> 1; + end + else begin + c_temp_shift_x = in_x >> 0; + end + //Store needed bits of shifted value + c_shifted_x = c_temp_shift_x[`MANTISSA_PRECISION - 1:0]; + end + else begin + c_shifted_x = in_x[`MANTISSA_PRECISION - 1:0]; + c_temp_shift_x = 32'b0; + end +end + +// calculate log +always@(r_indexFirstOne or mantissa) +begin + if(r_indexFirstOne >= `MANTISSA_PRECISION) + begin + c_log_x = mantissa - ((`MANTISSA_PRECISION - 1) * `LOG2) + (r_indexFirstOne * `LOG2); + end + else + begin + c_log_x = mantissa; + end +end + +// latch values +always @(posedge clock) +begin + if(reset) + begin + log_x <= 0; + r_indexFirstOne <= 0; + end + else + begin + if(enable) + begin + r_indexFirstOne <= c_indexFirstOne; + log_x <= c_log_x; + end + end +end + +endmodule + + + +module DropSpinWrapper ( + clock, reset, enable, + + //From Hopper Module + i_x, + i_y, + i_z, + i_ux, + i_uy, + i_uz, + i_sz, + i_sr, + i_sleftz, + i_sleftr, + i_weight, + i_layer, + i_dead, + i_hit, + + + //From System Register File (5 layers)- Absorber + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + + //From System Register File - ScattererReflector + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + + + ////////////////////////////////////////////////////////////////////////////// + //I/O to on-chip mem + ///////////////////////////////////////////////////////////////////////////// + + data, + rdaddress, wraddress, + wren, q, + + //From Memories + up_rFresnel, + down_rFresnel, + sint, + cost, + rand2, + rand3, + rand5, + //To Memories + tindex, + fresIndex, + + + //To DeadOrAlive Module + o_x, + o_y, + o_z, + o_ux, + o_uy, + o_uz, + o_sz, + o_sr, + o_sleftz, + o_sleftr, + o_weight, + o_layer, + o_dead, + o_hit + + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter PIPE_DEPTH = 37; +//parameter ADDR_WIDTH=16; //TODO: TBD +//parameter WORD_WIDTH=64; + +////////////////////////////////////////////////////////////////////////////// +//INPUTS +////////////////////////////////////////////////////////////////////////////// +input clock, reset, enable; + +//From Hopper Module +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; +input [`BIT_WIDTH-1:0] i_ux; +input [`BIT_WIDTH-1:0] i_uy; +input [`BIT_WIDTH-1:0] i_uz; +input [`BIT_WIDTH-1:0] i_sz; +input [`BIT_WIDTH-1:0] i_sr; +input [`BIT_WIDTH-1:0] i_sleftz; +input [`BIT_WIDTH-1:0] i_sleftr; +input [`BIT_WIDTH-1:0] i_weight; +input [`LAYER_WIDTH-1:0] i_layer; +input i_dead; +input i_hit; + + +//From System Register File (5 layers)- Absorber +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + +//From System Register File - ScattererReflector +input [`BIT_WIDTH-1:0] down_niOverNt_1; +input [`BIT_WIDTH-1:0] down_niOverNt_2; +input [`BIT_WIDTH-1:0] down_niOverNt_3; +input [`BIT_WIDTH-1:0] down_niOverNt_4; +input [`BIT_WIDTH-1:0] down_niOverNt_5; +input [`BIT_WIDTH-1:0] up_niOverNt_1; +input [`BIT_WIDTH-1:0] up_niOverNt_2; +input [`BIT_WIDTH-1:0] up_niOverNt_3; +input [`BIT_WIDTH-1:0] up_niOverNt_4; +input [`BIT_WIDTH-1:0] up_niOverNt_5; +input [`WORD_WIDTH-1:0] down_niOverNt_2_1; +input [`WORD_WIDTH-1:0] down_niOverNt_2_2; +input [`WORD_WIDTH-1:0] down_niOverNt_2_3; +input [`WORD_WIDTH-1:0] down_niOverNt_2_4; +input [`WORD_WIDTH-1:0] down_niOverNt_2_5; +input [`WORD_WIDTH-1:0] up_niOverNt_2_1; +input [`WORD_WIDTH-1:0] up_niOverNt_2_2; +input [`WORD_WIDTH-1:0] up_niOverNt_2_3; +input [`WORD_WIDTH-1:0] up_niOverNt_2_4; +input [`WORD_WIDTH-1:0] up_niOverNt_2_5; +input [`BIT_WIDTH-1:0] downCritAngle_0; +input [`BIT_WIDTH-1:0] downCritAngle_1; +input [`BIT_WIDTH-1:0] downCritAngle_2; +input [`BIT_WIDTH-1:0] downCritAngle_3; +input [`BIT_WIDTH-1:0] downCritAngle_4; +input [`BIT_WIDTH-1:0] upCritAngle_0; +input [`BIT_WIDTH-1:0] upCritAngle_1; +input [`BIT_WIDTH-1:0] upCritAngle_2; +input [`BIT_WIDTH-1:0] upCritAngle_3; +input [`BIT_WIDTH-1:0] upCritAngle_4; + +//Generated by random number generators controlled by skeleton +output [12:0] tindex; +output [9:0] fresIndex; + + +input [31:0] rand2; +input [31:0] rand3; +input [31:0] rand5; +input [31:0] sint; +input [31:0] cost; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + + + +////////////////////////////////////////////////////////////////////////////// +//OUTPUTS +///////////////////////////////////////////////////////////////////////////// +//To DeadOrAlive Module +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; +output [`BIT_WIDTH-1:0] o_ux; +output [`BIT_WIDTH-1:0] o_uy; +output [`BIT_WIDTH-1:0] o_uz; +output [`BIT_WIDTH-1:0] o_sz; +output [`BIT_WIDTH-1:0] o_sr; +output [`BIT_WIDTH-1:0] o_sleftz; +output [`BIT_WIDTH-1:0] o_sleftr; +output [`BIT_WIDTH-1:0] o_weight; +output [`LAYER_WIDTH-1:0] o_layer; +output o_dead; +output o_hit; + +wire [`BIT_WIDTH-1:0] o_x; +wire [`BIT_WIDTH-1:0] o_y; +wire [`BIT_WIDTH-1:0] o_z; +reg [`BIT_WIDTH-1:0] o_ux; +reg [`BIT_WIDTH-1:0] o_uy; +reg [`BIT_WIDTH-1:0] o_uz; +wire [`BIT_WIDTH-1:0] o_sz; +wire [`BIT_WIDTH-1:0] o_sr; +wire [`BIT_WIDTH-1:0] o_sleftz; +wire [`BIT_WIDTH-1:0] o_sleftr; +wire [`BIT_WIDTH-1:0] o_weight; +reg [`LAYER_WIDTH-1:0] o_layer; +reg o_dead; +wire o_hit; + + +////////////////////////////////////////////////////////////////////////////// +//I/O to on-chip mem +///////////////////////////////////////////////////////////////////////////// + +output [`WORD_WIDTH-1:0] data; +output [`ADDR_WIDTH-1:0] rdaddress, wraddress; +output wren; +input [`WORD_WIDTH-1:0] q; + + +////////////////////////////////////////////////////////////////////////////// +//Generate SHARED REGISTER PIPELINE +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS +//wire [`BIT_WIDTH-1:0] x [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] y [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] z [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] ux [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] uy [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] uz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sr [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sleftz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sleftr [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] weight [PIPE_DEPTH:0]; +//wire [LAYER_WIDTH-1:0] layer [PIPE_DEPTH:0]; +//wire dead [PIPE_DEPTH:0]; +//wire hit [PIPE_DEPTH:0]; + +//WIRES FOR CONNECTING REGISTERS +//wire [32-1:0] x [37:0]; +wire [32-1:0] x__0; +wire [32-1:0] x__1; +wire [32-1:0] x__2; +wire [32-1:0] x__3; +wire [32-1:0] x__4; +wire [32-1:0] x__5; +wire [32-1:0] x__6; +wire [32-1:0] x__7; +wire [32-1:0] x__8; +wire [32-1:0] x__9; +wire [32-1:0] x__10; +wire [32-1:0] x__11; +wire [32-1:0] x__12; +wire [32-1:0] x__13; +wire [32-1:0] x__14; +wire [32-1:0] x__15; +wire [32-1:0] x__16; +wire [32-1:0] x__17; +wire [32-1:0] x__18; +wire [32-1:0] x__19; +wire [32-1:0] x__20; +wire [32-1:0] x__21; +wire [32-1:0] x__22; +wire [32-1:0] x__23; +wire [32-1:0] x__24; +wire [32-1:0] x__25; +wire [32-1:0] x__26; +wire [32-1:0] x__27; +wire [32-1:0] x__28; +wire [32-1:0] x__29; +wire [32-1:0] x__30; +wire [32-1:0] x__31; +wire [32-1:0] x__32; +wire [32-1:0] x__33; +wire [32-1:0] x__34; +wire [32-1:0] x__35; +wire [32-1:0] x__36; +wire [32-1:0] x__37; + + + + +//wire [32-1:0] y [37:0]; +wire [32-1:0] y__0; +wire [32-1:0] y__1; +wire [32-1:0] y__2; +wire [32-1:0] y__3; +wire [32-1:0] y__4; +wire [32-1:0] y__5; +wire [32-1:0] y__6; +wire [32-1:0] y__7; +wire [32-1:0] y__8; +wire [32-1:0] y__9; +wire [32-1:0] y__10; +wire [32-1:0] y__11; +wire [32-1:0] y__12; +wire [32-1:0] y__13; +wire [32-1:0] y__14; +wire [32-1:0] y__15; +wire [32-1:0] y__16; +wire [32-1:0] y__17; +wire [32-1:0] y__18; +wire [32-1:0] y__19; +wire [32-1:0] y__20; +wire [32-1:0] y__21; +wire [32-1:0] y__22; +wire [32-1:0] y__23; +wire [32-1:0] y__24; +wire [32-1:0] y__25; +wire [32-1:0] y__26; +wire [32-1:0] y__27; +wire [32-1:0] y__28; +wire [32-1:0] y__29; +wire [32-1:0] y__30; +wire [32-1:0] y__31; +wire [32-1:0] y__32; +wire [32-1:0] y__33; +wire [32-1:0] y__34; +wire [32-1:0] y__35; +wire [32-1:0] y__36; +wire [32-1:0] y__37; + + + +//wire [32-1:0] z [37:0]; +wire [32-1:0] z__0; +wire [32-1:0] z__1; +wire [32-1:0] z__2; +wire [32-1:0] z__3; +wire [32-1:0] z__4; +wire [32-1:0] z__5; +wire [32-1:0] z__6; +wire [32-1:0] z__7; +wire [32-1:0] z__8; +wire [32-1:0] z__9; +wire [32-1:0] z__10; +wire [32-1:0] z__11; +wire [32-1:0] z__12; +wire [32-1:0] z__13; +wire [32-1:0] z__14; +wire [32-1:0] z__15; +wire [32-1:0] z__16; +wire [32-1:0] z__17; +wire [32-1:0] z__18; +wire [32-1:0] z__19; +wire [32-1:0] z__20; +wire [32-1:0] z__21; +wire [32-1:0] z__22; +wire [32-1:0] z__23; +wire [32-1:0] z__24; +wire [32-1:0] z__25; +wire [32-1:0] z__26; +wire [32-1:0] z__27; +wire [32-1:0] z__28; +wire [32-1:0] z__29; +wire [32-1:0] z__30; +wire [32-1:0] z__31; +wire [32-1:0] z__32; +wire [32-1:0] z__33; +wire [32-1:0] z__34; +wire [32-1:0] z__35; +wire [32-1:0] z__36; +wire [32-1:0] z__37; + + +//wire [32-1:0] ux [37:0]; +wire [32-1:0] ux__0; +wire [32-1:0] ux__1; +wire [32-1:0] ux__2; +wire [32-1:0] ux__3; +wire [32-1:0] ux__4; +wire [32-1:0] ux__5; +wire [32-1:0] ux__6; +wire [32-1:0] ux__7; +wire [32-1:0] ux__8; +wire [32-1:0] ux__9; +wire [32-1:0] ux__10; +wire [32-1:0] ux__11; +wire [32-1:0] ux__12; +wire [32-1:0] ux__13; +wire [32-1:0] ux__14; +wire [32-1:0] ux__15; +wire [32-1:0] ux__16; +wire [32-1:0] ux__17; +wire [32-1:0] ux__18; +wire [32-1:0] ux__19; +wire [32-1:0] ux__20; +wire [32-1:0] ux__21; +wire [32-1:0] ux__22; +wire [32-1:0] ux__23; +wire [32-1:0] ux__24; +wire [32-1:0] ux__25; +wire [32-1:0] ux__26; +wire [32-1:0] ux__27; +wire [32-1:0] ux__28; +wire [32-1:0] ux__29; +wire [32-1:0] ux__30; +wire [32-1:0] ux__31; +wire [32-1:0] ux__32; +wire [32-1:0] ux__33; +wire [32-1:0] ux__34; +wire [32-1:0] ux__35; +wire [32-1:0] ux__36; +wire [32-1:0] ux__37; + + + +//wire [32-1:0] uy [37:0]; +wire [32-1:0] uy__0; +wire [32-1:0] uy__1; +wire [32-1:0] uy__2; +wire [32-1:0] uy__3; +wire [32-1:0] uy__4; +wire [32-1:0] uy__5; +wire [32-1:0] uy__6; +wire [32-1:0] uy__7; +wire [32-1:0] uy__8; +wire [32-1:0] uy__9; +wire [32-1:0] uy__10; +wire [32-1:0] uy__11; +wire [32-1:0] uy__12; +wire [32-1:0] uy__13; +wire [32-1:0] uy__14; +wire [32-1:0] uy__15; +wire [32-1:0] uy__16; +wire [32-1:0] uy__17; +wire [32-1:0] uy__18; +wire [32-1:0] uy__19; +wire [32-1:0] uy__20; +wire [32-1:0] uy__21; +wire [32-1:0] uy__22; +wire [32-1:0] uy__23; +wire [32-1:0] uy__24; +wire [32-1:0] uy__25; +wire [32-1:0] uy__26; +wire [32-1:0] uy__27; +wire [32-1:0] uy__28; +wire [32-1:0] uy__29; +wire [32-1:0] uy__30; +wire [32-1:0] uy__31; +wire [32-1:0] uy__32; +wire [32-1:0] uy__33; +wire [32-1:0] uy__34; +wire [32-1:0] uy__35; +wire [32-1:0] uy__36; +wire [32-1:0] uy__37; + + +//wire [32-1:0] uz [37:0]; +wire [32-1:0] uz__0; +wire [32-1:0] uz__1; +wire [32-1:0] uz__2; +wire [32-1:0] uz__3; +wire [32-1:0] uz__4; +wire [32-1:0] uz__5; +wire [32-1:0] uz__6; +wire [32-1:0] uz__7; +wire [32-1:0] uz__8; +wire [32-1:0] uz__9; +wire [32-1:0] uz__10; +wire [32-1:0] uz__11; +wire [32-1:0] uz__12; +wire [32-1:0] uz__13; +wire [32-1:0] uz__14; +wire [32-1:0] uz__15; +wire [32-1:0] uz__16; +wire [32-1:0] uz__17; +wire [32-1:0] uz__18; +wire [32-1:0] uz__19; +wire [32-1:0] uz__20; +wire [32-1:0] uz__21; +wire [32-1:0] uz__22; +wire [32-1:0] uz__23; +wire [32-1:0] uz__24; +wire [32-1:0] uz__25; +wire [32-1:0] uz__26; +wire [32-1:0] uz__27; +wire [32-1:0] uz__28; +wire [32-1:0] uz__29; +wire [32-1:0] uz__30; +wire [32-1:0] uz__31; +wire [32-1:0] uz__32; +wire [32-1:0] uz__33; +wire [32-1:0] uz__34; +wire [32-1:0] uz__35; +wire [32-1:0] uz__36; +wire [32-1:0] uz__37; + + +//wire [32-1:0] sz [37:0]; +wire [32-1:0] sz__0; +wire [32-1:0] sz__1; +wire [32-1:0] sz__2; +wire [32-1:0] sz__3; +wire [32-1:0] sz__4; +wire [32-1:0] sz__5; +wire [32-1:0] sz__6; +wire [32-1:0] sz__7; +wire [32-1:0] sz__8; +wire [32-1:0] sz__9; +wire [32-1:0] sz__10; +wire [32-1:0] sz__11; +wire [32-1:0] sz__12; +wire [32-1:0] sz__13; +wire [32-1:0] sz__14; +wire [32-1:0] sz__15; +wire [32-1:0] sz__16; +wire [32-1:0] sz__17; +wire [32-1:0] sz__18; +wire [32-1:0] sz__19; +wire [32-1:0] sz__20; +wire [32-1:0] sz__21; +wire [32-1:0] sz__22; +wire [32-1:0] sz__23; +wire [32-1:0] sz__24; +wire [32-1:0] sz__25; +wire [32-1:0] sz__26; +wire [32-1:0] sz__27; +wire [32-1:0] sz__28; +wire [32-1:0] sz__29; +wire [32-1:0] sz__30; +wire [32-1:0] sz__31; +wire [32-1:0] sz__32; +wire [32-1:0] sz__33; +wire [32-1:0] sz__34; +wire [32-1:0] sz__35; +wire [32-1:0] sz__36; +wire [32-1:0] sz__37; + + +//wire [32-1:0] sr [37:0]; +wire [32-1:0] sr__0; +wire [32-1:0] sr__1; +wire [32-1:0] sr__2; +wire [32-1:0] sr__3; +wire [32-1:0] sr__4; +wire [32-1:0] sr__5; +wire [32-1:0] sr__6; +wire [32-1:0] sr__7; +wire [32-1:0] sr__8; +wire [32-1:0] sr__9; +wire [32-1:0] sr__10; +wire [32-1:0] sr__11; +wire [32-1:0] sr__12; +wire [32-1:0] sr__13; +wire [32-1:0] sr__14; +wire [32-1:0] sr__15; +wire [32-1:0] sr__16; +wire [32-1:0] sr__17; +wire [32-1:0] sr__18; +wire [32-1:0] sr__19; +wire [32-1:0] sr__20; +wire [32-1:0] sr__21; +wire [32-1:0] sr__22; +wire [32-1:0] sr__23; +wire [32-1:0] sr__24; +wire [32-1:0] sr__25; +wire [32-1:0] sr__26; +wire [32-1:0] sr__27; +wire [32-1:0] sr__28; +wire [32-1:0] sr__29; +wire [32-1:0] sr__30; +wire [32-1:0] sr__31; +wire [32-1:0] sr__32; +wire [32-1:0] sr__33; +wire [32-1:0] sr__34; +wire [32-1:0] sr__35; +wire [32-1:0] sr__36; +wire [32-1:0] sr__37; + + + +//wire [32-1:0] sleftz [37:0]; +wire [32-1:0] sleftz__0; +wire [32-1:0] sleftz__1; +wire [32-1:0] sleftz__2; +wire [32-1:0] sleftz__3; +wire [32-1:0] sleftz__4; +wire [32-1:0] sleftz__5; +wire [32-1:0] sleftz__6; +wire [32-1:0] sleftz__7; +wire [32-1:0] sleftz__8; +wire [32-1:0] sleftz__9; +wire [32-1:0] sleftz__10; +wire [32-1:0] sleftz__11; +wire [32-1:0] sleftz__12; +wire [32-1:0] sleftz__13; +wire [32-1:0] sleftz__14; +wire [32-1:0] sleftz__15; +wire [32-1:0] sleftz__16; +wire [32-1:0] sleftz__17; +wire [32-1:0] sleftz__18; +wire [32-1:0] sleftz__19; +wire [32-1:0] sleftz__20; +wire [32-1:0] sleftz__21; +wire [32-1:0] sleftz__22; +wire [32-1:0] sleftz__23; +wire [32-1:0] sleftz__24; +wire [32-1:0] sleftz__25; +wire [32-1:0] sleftz__26; +wire [32-1:0] sleftz__27; +wire [32-1:0] sleftz__28; +wire [32-1:0] sleftz__29; +wire [32-1:0] sleftz__30; +wire [32-1:0] sleftz__31; +wire [32-1:0] sleftz__32; +wire [32-1:0] sleftz__33; +wire [32-1:0] sleftz__34; +wire [32-1:0] sleftz__35; +wire [32-1:0] sleftz__36; +wire [32-1:0] sleftz__37; + + +//wire [32-1:0] sleftr [37:0]; +wire [32-1:0] sleftr__0; +wire [32-1:0] sleftr__1; +wire [32-1:0] sleftr__2; +wire [32-1:0] sleftr__3; +wire [32-1:0] sleftr__4; +wire [32-1:0] sleftr__5; +wire [32-1:0] sleftr__6; +wire [32-1:0] sleftr__7; +wire [32-1:0] sleftr__8; +wire [32-1:0] sleftr__9; +wire [32-1:0] sleftr__10; +wire [32-1:0] sleftr__11; +wire [32-1:0] sleftr__12; +wire [32-1:0] sleftr__13; +wire [32-1:0] sleftr__14; +wire [32-1:0] sleftr__15; +wire [32-1:0] sleftr__16; +wire [32-1:0] sleftr__17; +wire [32-1:0] sleftr__18; +wire [32-1:0] sleftr__19; +wire [32-1:0] sleftr__20; +wire [32-1:0] sleftr__21; +wire [32-1:0] sleftr__22; +wire [32-1:0] sleftr__23; +wire [32-1:0] sleftr__24; +wire [32-1:0] sleftr__25; +wire [32-1:0] sleftr__26; +wire [32-1:0] sleftr__27; +wire [32-1:0] sleftr__28; +wire [32-1:0] sleftr__29; +wire [32-1:0] sleftr__30; +wire [32-1:0] sleftr__31; +wire [32-1:0] sleftr__32; +wire [32-1:0] sleftr__33; +wire [32-1:0] sleftr__34; +wire [32-1:0] sleftr__35; +wire [32-1:0] sleftr__36; +wire [32-1:0] sleftr__37; + + +//wire [32-1:0] weight [37:0]; +wire [32-1:0] weight__0; +wire [32-1:0] weight__1; +wire [32-1:0] weight__2; +wire [32-1:0] weight__3; +wire [32-1:0] weight__4; +wire [32-1:0] weight__5; +wire [32-1:0] weight__6; +wire [32-1:0] weight__7; +wire [32-1:0] weight__8; +wire [32-1:0] weight__9; +wire [32-1:0] weight__10; +wire [32-1:0] weight__11; +wire [32-1:0] weight__12; +wire [32-1:0] weight__13; +wire [32-1:0] weight__14; +wire [32-1:0] weight__15; +wire [32-1:0] weight__16; +wire [32-1:0] weight__17; +wire [32-1:0] weight__18; +wire [32-1:0] weight__19; +wire [32-1:0] weight__20; +wire [32-1:0] weight__21; +wire [32-1:0] weight__22; +wire [32-1:0] weight__23; +wire [32-1:0] weight__24; +wire [32-1:0] weight__25; +wire [32-1:0] weight__26; +wire [32-1:0] weight__27; +wire [32-1:0] weight__28; +wire [32-1:0] weight__29; +wire [32-1:0] weight__30; +wire [32-1:0] weight__31; +wire [32-1:0] weight__32; +wire [32-1:0] weight__33; +wire [32-1:0] weight__34; +wire [32-1:0] weight__35; +wire [32-1:0] weight__36; +wire [32-1:0] weight__37; + + +//wire [3-1:0] layer [37:0]; +wire [3-1:0] layer__0; +wire [3-1:0] layer__1; +wire [3-1:0] layer__2; +wire [3-1:0] layer__3; +wire [3-1:0] layer__4; +wire [3-1:0] layer__5; +wire [3-1:0] layer__6; +wire [3-1:0] layer__7; +wire [3-1:0] layer__8; +wire [3-1:0] layer__9; +wire [3-1:0] layer__10; +wire [3-1:0] layer__11; +wire [3-1:0] layer__12; +wire [3-1:0] layer__13; +wire [3-1:0] layer__14; +wire [3-1:0] layer__15; +wire [3-1:0] layer__16; +wire [3-1:0] layer__17; +wire [3-1:0] layer__18; +wire [3-1:0] layer__19; +wire [3-1:0] layer__20; +wire [3-1:0] layer__21; +wire [3-1:0] layer__22; +wire [3-1:0] layer__23; +wire [3-1:0] layer__24; +wire [3-1:0] layer__25; +wire [3-1:0] layer__26; +wire [3-1:0] layer__27; +wire [3-1:0] layer__28; +wire [3-1:0] layer__29; +wire [3-1:0] layer__30; +wire [3-1:0] layer__31; +wire [3-1:0] layer__32; +wire [3-1:0] layer__33; +wire [3-1:0] layer__34; +wire [3-1:0] layer__35; +wire [3-1:0] layer__36; +wire [3-1:0] layer__37; + +//wire [37:0] dead; +wire dead__0; +wire dead__1; +wire dead__2; +wire dead__3; +wire dead__4; +wire dead__5; +wire dead__6; +wire dead__7; +wire dead__8; +wire dead__9; +wire dead__10; +wire dead__11; +wire dead__12; +wire dead__13; +wire dead__14; +wire dead__15; +wire dead__16; +wire dead__17; +wire dead__18; +wire dead__19; +wire dead__20; +wire dead__21; +wire dead__22; +wire dead__23; +wire dead__24; +wire dead__25; +wire dead__26; +wire dead__27; +wire dead__28; +wire dead__29; +wire dead__30; +wire dead__31; +wire dead__32; +wire dead__33; +wire dead__34; +wire dead__35; +wire dead__36; +wire dead__37; + + +//wire [37:0] hit ; + +wire hit__0; +wire hit__1; +wire hit__2; +wire hit__3; +wire hit__4; +wire hit__5; +wire hit__6; +wire hit__7; +wire hit__8; +wire hit__9; +wire hit__10; +wire hit__11; +wire hit__12; +wire hit__13; +wire hit__14; +wire hit__15; +wire hit__16; +wire hit__17; +wire hit__18; +wire hit__19; +wire hit__20; +wire hit__21; +wire hit__22; +wire hit__23; +wire hit__24; +wire hit__25; +wire hit__26; +wire hit__27; +wire hit__28; +wire hit__29; +wire hit__30; +wire hit__31; +wire hit__32; +wire hit__33; +wire hit__34; +wire hit__35; +wire hit__36; +wire hit__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign x__0 = i_x; +assign y__0 = i_y; +assign z__0 = i_z; +assign ux__0 = i_ux; +assign uy__0 = i_uy; +assign uz__0 = i_uz; +assign sz__0 = i_sz; +assign sr__0 = i_sr; +assign sleftz__0 = i_sleftz; +assign sleftr__0 = i_sleftr; +assign weight__0 = i_weight; +assign layer__0 = i_layer; +assign dead__0 = i_dead; +assign hit__0 = i_hit; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +//TODO: Assign outputs from the correct module +assign o_x =x__37; +assign o_y =y__37; +assign o_z =z__37; +//assign o_ux =ux[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_uy =uy[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_uz =uz[PIPE_DEPTH]; Assigned by deadOrAliveMux +assign o_sz =sz__37; +assign o_sr =sr__37; +assign o_sleftz =sleftz__37; +assign o_sleftr =sleftr__37; +//assign o_weight =weight[PIPE_DEPTH]; Assigned by absorber module (below) +//assign o_layer =layer[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_dead =dead[PIPE_DEPTH]; Assigned by deadOrAliveMux +assign o_hit =hit__37; + + +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=PIPE_DEPTH; i>0; i=i-1) begin: regPipe +// case(i) +// +// default: +// PhotonBlock5 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(x[i-1]), +// .i_y(y[i-1]), +// .i_z(z[i-1]), +// .i_ux(ux[i-1]), +// .i_uy(uy[i-1]), +// .i_uz(uz[i-1]), +// .i_sz(sz[i-1]), +// .i_sr(sr[i-1]), +// .i_sleftz(sleftz[i-1]), +// .i_sleftr(sleftr[i-1]), +// .i_weight(weight[i-1]), +// .i_layer(layer[i-1]), +// .i_dead(dead[i-1]), +// .i_hit(hit[i-1]), +// +// //Outputs +// .o_x(x[i]), +// .o_y(y[i]), +// .o_z(z[i]), +// .o_ux(ux[i]), +// .o_uy(uy[i]), +// .o_uz(uz[i]), +// .o_sz(sz[i]), +// .o_sr(sr[i]), +// .o_sleftz(sleftz[i]), +// .o_sleftr(sleftr[i]), +// .o_weight(weight[i]), +// .o_layer(layer[i]), +// .o_dead(dead[i]), +// .o_hit(hit[i]) +// ); +// endcase +// end +//endgenerate + +PhotonBlock5 photon37( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__36), +.i_y(y__36), +.i_z(z__36), +.i_ux(ux__36), +.i_uy(uy__36), +.i_uz(uz__36), +.i_sz(sz__36), +.i_sr(sr__36), +.i_sleftz(sleftz__36), +.i_sleftr(sleftr__36), +.i_weight(weight__36), +.i_layer(layer__36), +.i_dead(dead__36), +.i_hit(hit__36), +//Outputs +.o_x(x__37), +.o_y(y__37), +.o_z(z__37), +.o_ux(ux__37), +.o_uy(uy__37), +.o_uz(uz__37), +.o_sz(sz__37), +.o_sr(sr__37), +.o_sleftz(sleftz__37), +.o_sleftr(sleftr__37), +.o_weight(weight__37), +.o_layer(layer__37), +.o_dead(dead__37), +.o_hit(hit__37) +); +PhotonBlock5 photon36( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__35), +.i_y(y__35), +.i_z(z__35), +.i_ux(ux__35), +.i_uy(uy__35), +.i_uz(uz__35), +.i_sz(sz__35), +.i_sr(sr__35), +.i_sleftz(sleftz__35), +.i_sleftr(sleftr__35), +.i_weight(weight__35), +.i_layer(layer__35), +.i_dead(dead__35), +.i_hit(hit__35), +//Outputs +.o_x(x__36), +.o_y(y__36), +.o_z(z__36), +.o_ux(ux__36), +.o_uy(uy__36), +.o_uz(uz__36), +.o_sz(sz__36), +.o_sr(sr__36), +.o_sleftz(sleftz__36), +.o_sleftr(sleftr__36), +.o_weight(weight__36), +.o_layer(layer__36), +.o_dead(dead__36), +.o_hit(hit__36) +); +PhotonBlock5 photon35( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__34), +.i_y(y__34), +.i_z(z__34), +.i_ux(ux__34), +.i_uy(uy__34), +.i_uz(uz__34), +.i_sz(sz__34), +.i_sr(sr__34), +.i_sleftz(sleftz__34), +.i_sleftr(sleftr__34), +.i_weight(weight__34), +.i_layer(layer__34), +.i_dead(dead__34), +.i_hit(hit__34), +//Outputs +.o_x(x__35), +.o_y(y__35), +.o_z(z__35), +.o_ux(ux__35), +.o_uy(uy__35), +.o_uz(uz__35), +.o_sz(sz__35), +.o_sr(sr__35), +.o_sleftz(sleftz__35), +.o_sleftr(sleftr__35), +.o_weight(weight__35), +.o_layer(layer__35), +.o_dead(dead__35), +.o_hit(hit__35) +); +PhotonBlock5 photon34( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__33), +.i_y(y__33), +.i_z(z__33), +.i_ux(ux__33), +.i_uy(uy__33), +.i_uz(uz__33), +.i_sz(sz__33), +.i_sr(sr__33), +.i_sleftz(sleftz__33), +.i_sleftr(sleftr__33), +.i_weight(weight__33), +.i_layer(layer__33), +.i_dead(dead__33), +.i_hit(hit__33), +//Outputs +.o_x(x__34), +.o_y(y__34), +.o_z(z__34), +.o_ux(ux__34), +.o_uy(uy__34), +.o_uz(uz__34), +.o_sz(sz__34), +.o_sr(sr__34), +.o_sleftz(sleftz__34), +.o_sleftr(sleftr__34), +.o_weight(weight__34), +.o_layer(layer__34), +.o_dead(dead__34), +.o_hit(hit__34) +); +PhotonBlock5 photon33( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__32), +.i_y(y__32), +.i_z(z__32), +.i_ux(ux__32), +.i_uy(uy__32), +.i_uz(uz__32), +.i_sz(sz__32), +.i_sr(sr__32), +.i_sleftz(sleftz__32), +.i_sleftr(sleftr__32), +.i_weight(weight__32), +.i_layer(layer__32), +.i_dead(dead__32), +.i_hit(hit__32), +//Outputs +.o_x(x__33), +.o_y(y__33), +.o_z(z__33), +.o_ux(ux__33), +.o_uy(uy__33), +.o_uz(uz__33), +.o_sz(sz__33), +.o_sr(sr__33), +.o_sleftz(sleftz__33), +.o_sleftr(sleftr__33), +.o_weight(weight__33), +.o_layer(layer__33), +.o_dead(dead__33), +.o_hit(hit__33) +); +PhotonBlock5 photon32( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__31), +.i_y(y__31), +.i_z(z__31), +.i_ux(ux__31), +.i_uy(uy__31), +.i_uz(uz__31), +.i_sz(sz__31), +.i_sr(sr__31), +.i_sleftz(sleftz__31), +.i_sleftr(sleftr__31), +.i_weight(weight__31), +.i_layer(layer__31), +.i_dead(dead__31), +.i_hit(hit__31), +//Outputs +.o_x(x__32), +.o_y(y__32), +.o_z(z__32), +.o_ux(ux__32), +.o_uy(uy__32), +.o_uz(uz__32), +.o_sz(sz__32), +.o_sr(sr__32), +.o_sleftz(sleftz__32), +.o_sleftr(sleftr__32), +.o_weight(weight__32), +.o_layer(layer__32), +.o_dead(dead__32), +.o_hit(hit__32) +); +PhotonBlock5 photon31( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__30), +.i_y(y__30), +.i_z(z__30), +.i_ux(ux__30), +.i_uy(uy__30), +.i_uz(uz__30), +.i_sz(sz__30), +.i_sr(sr__30), +.i_sleftz(sleftz__30), +.i_sleftr(sleftr__30), +.i_weight(weight__30), +.i_layer(layer__30), +.i_dead(dead__30), +.i_hit(hit__30), +//Outputs +.o_x(x__31), +.o_y(y__31), +.o_z(z__31), +.o_ux(ux__31), +.o_uy(uy__31), +.o_uz(uz__31), +.o_sz(sz__31), +.o_sr(sr__31), +.o_sleftz(sleftz__31), +.o_sleftr(sleftr__31), +.o_weight(weight__31), +.o_layer(layer__31), +.o_dead(dead__31), +.o_hit(hit__31) +); +PhotonBlock5 photon30( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__29), +.i_y(y__29), +.i_z(z__29), +.i_ux(ux__29), +.i_uy(uy__29), +.i_uz(uz__29), +.i_sz(sz__29), +.i_sr(sr__29), +.i_sleftz(sleftz__29), +.i_sleftr(sleftr__29), +.i_weight(weight__29), +.i_layer(layer__29), +.i_dead(dead__29), +.i_hit(hit__29), +//Outputs +.o_x(x__30), +.o_y(y__30), +.o_z(z__30), +.o_ux(ux__30), +.o_uy(uy__30), +.o_uz(uz__30), +.o_sz(sz__30), +.o_sr(sr__30), +.o_sleftz(sleftz__30), +.o_sleftr(sleftr__30), +.o_weight(weight__30), +.o_layer(layer__30), +.o_dead(dead__30), +.o_hit(hit__30) +); +PhotonBlock5 photon29( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__28), +.i_y(y__28), +.i_z(z__28), +.i_ux(ux__28), +.i_uy(uy__28), +.i_uz(uz__28), +.i_sz(sz__28), +.i_sr(sr__28), +.i_sleftz(sleftz__28), +.i_sleftr(sleftr__28), +.i_weight(weight__28), +.i_layer(layer__28), +.i_dead(dead__28), +.i_hit(hit__28), +//Outputs +.o_x(x__29), +.o_y(y__29), +.o_z(z__29), +.o_ux(ux__29), +.o_uy(uy__29), +.o_uz(uz__29), +.o_sz(sz__29), +.o_sr(sr__29), +.o_sleftz(sleftz__29), +.o_sleftr(sleftr__29), +.o_weight(weight__29), +.o_layer(layer__29), +.o_dead(dead__29), +.o_hit(hit__29) +); +PhotonBlock5 photon28( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__27), +.i_y(y__27), +.i_z(z__27), +.i_ux(ux__27), +.i_uy(uy__27), +.i_uz(uz__27), +.i_sz(sz__27), +.i_sr(sr__27), +.i_sleftz(sleftz__27), +.i_sleftr(sleftr__27), +.i_weight(weight__27), +.i_layer(layer__27), +.i_dead(dead__27), +.i_hit(hit__27), +//Outputs +.o_x(x__28), +.o_y(y__28), +.o_z(z__28), +.o_ux(ux__28), +.o_uy(uy__28), +.o_uz(uz__28), +.o_sz(sz__28), +.o_sr(sr__28), +.o_sleftz(sleftz__28), +.o_sleftr(sleftr__28), +.o_weight(weight__28), +.o_layer(layer__28), +.o_dead(dead__28), +.o_hit(hit__28) +); +PhotonBlock5 photon27( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__26), +.i_y(y__26), +.i_z(z__26), +.i_ux(ux__26), +.i_uy(uy__26), +.i_uz(uz__26), +.i_sz(sz__26), +.i_sr(sr__26), +.i_sleftz(sleftz__26), +.i_sleftr(sleftr__26), +.i_weight(weight__26), +.i_layer(layer__26), +.i_dead(dead__26), +.i_hit(hit__26), +//Outputs +.o_x(x__27), +.o_y(y__27), +.o_z(z__27), +.o_ux(ux__27), +.o_uy(uy__27), +.o_uz(uz__27), +.o_sz(sz__27), +.o_sr(sr__27), +.o_sleftz(sleftz__27), +.o_sleftr(sleftr__27), +.o_weight(weight__27), +.o_layer(layer__27), +.o_dead(dead__27), +.o_hit(hit__27) +); +PhotonBlock5 photon26( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__25), +.i_y(y__25), +.i_z(z__25), +.i_ux(ux__25), +.i_uy(uy__25), +.i_uz(uz__25), +.i_sz(sz__25), +.i_sr(sr__25), +.i_sleftz(sleftz__25), +.i_sleftr(sleftr__25), +.i_weight(weight__25), +.i_layer(layer__25), +.i_dead(dead__25), +.i_hit(hit__25), +//Outputs +.o_x(x__26), +.o_y(y__26), +.o_z(z__26), +.o_ux(ux__26), +.o_uy(uy__26), +.o_uz(uz__26), +.o_sz(sz__26), +.o_sr(sr__26), +.o_sleftz(sleftz__26), +.o_sleftr(sleftr__26), +.o_weight(weight__26), +.o_layer(layer__26), +.o_dead(dead__26), +.o_hit(hit__26) +); +PhotonBlock5 photon25( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__24), +.i_y(y__24), +.i_z(z__24), +.i_ux(ux__24), +.i_uy(uy__24), +.i_uz(uz__24), +.i_sz(sz__24), +.i_sr(sr__24), +.i_sleftz(sleftz__24), +.i_sleftr(sleftr__24), +.i_weight(weight__24), +.i_layer(layer__24), +.i_dead(dead__24), +.i_hit(hit__24), +//Outputs +.o_x(x__25), +.o_y(y__25), +.o_z(z__25), +.o_ux(ux__25), +.o_uy(uy__25), +.o_uz(uz__25), +.o_sz(sz__25), +.o_sr(sr__25), +.o_sleftz(sleftz__25), +.o_sleftr(sleftr__25), +.o_weight(weight__25), +.o_layer(layer__25), +.o_dead(dead__25), +.o_hit(hit__25) +); +PhotonBlock5 photon24( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__23), +.i_y(y__23), +.i_z(z__23), +.i_ux(ux__23), +.i_uy(uy__23), +.i_uz(uz__23), +.i_sz(sz__23), +.i_sr(sr__23), +.i_sleftz(sleftz__23), +.i_sleftr(sleftr__23), +.i_weight(weight__23), +.i_layer(layer__23), +.i_dead(dead__23), +.i_hit(hit__23), +//Outputs +.o_x(x__24), +.o_y(y__24), +.o_z(z__24), +.o_ux(ux__24), +.o_uy(uy__24), +.o_uz(uz__24), +.o_sz(sz__24), +.o_sr(sr__24), +.o_sleftz(sleftz__24), +.o_sleftr(sleftr__24), +.o_weight(weight__24), +.o_layer(layer__24), +.o_dead(dead__24), +.o_hit(hit__24) +); +PhotonBlock5 photon23( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__22), +.i_y(y__22), +.i_z(z__22), +.i_ux(ux__22), +.i_uy(uy__22), +.i_uz(uz__22), +.i_sz(sz__22), +.i_sr(sr__22), +.i_sleftz(sleftz__22), +.i_sleftr(sleftr__22), +.i_weight(weight__22), +.i_layer(layer__22), +.i_dead(dead__22), +.i_hit(hit__22), +//Outputs +.o_x(x__23), +.o_y(y__23), +.o_z(z__23), +.o_ux(ux__23), +.o_uy(uy__23), +.o_uz(uz__23), +.o_sz(sz__23), +.o_sr(sr__23), +.o_sleftz(sleftz__23), +.o_sleftr(sleftr__23), +.o_weight(weight__23), +.o_layer(layer__23), +.o_dead(dead__23), +.o_hit(hit__23) +); +PhotonBlock5 photon22( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__21), +.i_y(y__21), +.i_z(z__21), +.i_ux(ux__21), +.i_uy(uy__21), +.i_uz(uz__21), +.i_sz(sz__21), +.i_sr(sr__21), +.i_sleftz(sleftz__21), +.i_sleftr(sleftr__21), +.i_weight(weight__21), +.i_layer(layer__21), +.i_dead(dead__21), +.i_hit(hit__21), +//Outputs +.o_x(x__22), +.o_y(y__22), +.o_z(z__22), +.o_ux(ux__22), +.o_uy(uy__22), +.o_uz(uz__22), +.o_sz(sz__22), +.o_sr(sr__22), +.o_sleftz(sleftz__22), +.o_sleftr(sleftr__22), +.o_weight(weight__22), +.o_layer(layer__22), +.o_dead(dead__22), +.o_hit(hit__22) +); +PhotonBlock5 photon21( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__20), +.i_y(y__20), +.i_z(z__20), +.i_ux(ux__20), +.i_uy(uy__20), +.i_uz(uz__20), +.i_sz(sz__20), +.i_sr(sr__20), +.i_sleftz(sleftz__20), +.i_sleftr(sleftr__20), +.i_weight(weight__20), +.i_layer(layer__20), +.i_dead(dead__20), +.i_hit(hit__20), +//Outputs +.o_x(x__21), +.o_y(y__21), +.o_z(z__21), +.o_ux(ux__21), +.o_uy(uy__21), +.o_uz(uz__21), +.o_sz(sz__21), +.o_sr(sr__21), +.o_sleftz(sleftz__21), +.o_sleftr(sleftr__21), +.o_weight(weight__21), +.o_layer(layer__21), +.o_dead(dead__21), +.o_hit(hit__21) +); +PhotonBlock5 photon20( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__19), +.i_y(y__19), +.i_z(z__19), +.i_ux(ux__19), +.i_uy(uy__19), +.i_uz(uz__19), +.i_sz(sz__19), +.i_sr(sr__19), +.i_sleftz(sleftz__19), +.i_sleftr(sleftr__19), +.i_weight(weight__19), +.i_layer(layer__19), +.i_dead(dead__19), +.i_hit(hit__19), +//Outputs +.o_x(x__20), +.o_y(y__20), +.o_z(z__20), +.o_ux(ux__20), +.o_uy(uy__20), +.o_uz(uz__20), +.o_sz(sz__20), +.o_sr(sr__20), +.o_sleftz(sleftz__20), +.o_sleftr(sleftr__20), +.o_weight(weight__20), +.o_layer(layer__20), +.o_dead(dead__20), +.o_hit(hit__20) +); +PhotonBlock5 photon19( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__18), +.i_y(y__18), +.i_z(z__18), +.i_ux(ux__18), +.i_uy(uy__18), +.i_uz(uz__18), +.i_sz(sz__18), +.i_sr(sr__18), +.i_sleftz(sleftz__18), +.i_sleftr(sleftr__18), +.i_weight(weight__18), +.i_layer(layer__18), +.i_dead(dead__18), +.i_hit(hit__18), +//Outputs +.o_x(x__19), +.o_y(y__19), +.o_z(z__19), +.o_ux(ux__19), +.o_uy(uy__19), +.o_uz(uz__19), +.o_sz(sz__19), +.o_sr(sr__19), +.o_sleftz(sleftz__19), +.o_sleftr(sleftr__19), +.o_weight(weight__19), +.o_layer(layer__19), +.o_dead(dead__19), +.o_hit(hit__19) +); +PhotonBlock5 photon18( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__17), +.i_y(y__17), +.i_z(z__17), +.i_ux(ux__17), +.i_uy(uy__17), +.i_uz(uz__17), +.i_sz(sz__17), +.i_sr(sr__17), +.i_sleftz(sleftz__17), +.i_sleftr(sleftr__17), +.i_weight(weight__17), +.i_layer(layer__17), +.i_dead(dead__17), +.i_hit(hit__17), +//Outputs +.o_x(x__18), +.o_y(y__18), +.o_z(z__18), +.o_ux(ux__18), +.o_uy(uy__18), +.o_uz(uz__18), +.o_sz(sz__18), +.o_sr(sr__18), +.o_sleftz(sleftz__18), +.o_sleftr(sleftr__18), +.o_weight(weight__18), +.o_layer(layer__18), +.o_dead(dead__18), +.o_hit(hit__18) +); +PhotonBlock5 photon17( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__16), +.i_y(y__16), +.i_z(z__16), +.i_ux(ux__16), +.i_uy(uy__16), +.i_uz(uz__16), +.i_sz(sz__16), +.i_sr(sr__16), +.i_sleftz(sleftz__16), +.i_sleftr(sleftr__16), +.i_weight(weight__16), +.i_layer(layer__16), +.i_dead(dead__16), +.i_hit(hit__16), +//Outputs +.o_x(x__17), +.o_y(y__17), +.o_z(z__17), +.o_ux(ux__17), +.o_uy(uy__17), +.o_uz(uz__17), +.o_sz(sz__17), +.o_sr(sr__17), +.o_sleftz(sleftz__17), +.o_sleftr(sleftr__17), +.o_weight(weight__17), +.o_layer(layer__17), +.o_dead(dead__17), +.o_hit(hit__17) +); +PhotonBlock5 photon16( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__15), +.i_y(y__15), +.i_z(z__15), +.i_ux(ux__15), +.i_uy(uy__15), +.i_uz(uz__15), +.i_sz(sz__15), +.i_sr(sr__15), +.i_sleftz(sleftz__15), +.i_sleftr(sleftr__15), +.i_weight(weight__15), +.i_layer(layer__15), +.i_dead(dead__15), +.i_hit(hit__15), +//Outputs +.o_x(x__16), +.o_y(y__16), +.o_z(z__16), +.o_ux(ux__16), +.o_uy(uy__16), +.o_uz(uz__16), +.o_sz(sz__16), +.o_sr(sr__16), +.o_sleftz(sleftz__16), +.o_sleftr(sleftr__16), +.o_weight(weight__16), +.o_layer(layer__16), +.o_dead(dead__16), +.o_hit(hit__16) +); +PhotonBlock5 photon15( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__14), +.i_y(y__14), +.i_z(z__14), +.i_ux(ux__14), +.i_uy(uy__14), +.i_uz(uz__14), +.i_sz(sz__14), +.i_sr(sr__14), +.i_sleftz(sleftz__14), +.i_sleftr(sleftr__14), +.i_weight(weight__14), +.i_layer(layer__14), +.i_dead(dead__14), +.i_hit(hit__14), +//Outputs +.o_x(x__15), +.o_y(y__15), +.o_z(z__15), +.o_ux(ux__15), +.o_uy(uy__15), +.o_uz(uz__15), +.o_sz(sz__15), +.o_sr(sr__15), +.o_sleftz(sleftz__15), +.o_sleftr(sleftr__15), +.o_weight(weight__15), +.o_layer(layer__15), +.o_dead(dead__15), +.o_hit(hit__15) +); +PhotonBlock5 photon14( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__13), +.i_y(y__13), +.i_z(z__13), +.i_ux(ux__13), +.i_uy(uy__13), +.i_uz(uz__13), +.i_sz(sz__13), +.i_sr(sr__13), +.i_sleftz(sleftz__13), +.i_sleftr(sleftr__13), +.i_weight(weight__13), +.i_layer(layer__13), +.i_dead(dead__13), +.i_hit(hit__13), +//Outputs +.o_x(x__14), +.o_y(y__14), +.o_z(z__14), +.o_ux(ux__14), +.o_uy(uy__14), +.o_uz(uz__14), +.o_sz(sz__14), +.o_sr(sr__14), +.o_sleftz(sleftz__14), +.o_sleftr(sleftr__14), +.o_weight(weight__14), +.o_layer(layer__14), +.o_dead(dead__14), +.o_hit(hit__14) +); +PhotonBlock5 photon13( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__12), +.i_y(y__12), +.i_z(z__12), +.i_ux(ux__12), +.i_uy(uy__12), +.i_uz(uz__12), +.i_sz(sz__12), +.i_sr(sr__12), +.i_sleftz(sleftz__12), +.i_sleftr(sleftr__12), +.i_weight(weight__12), +.i_layer(layer__12), +.i_dead(dead__12), +.i_hit(hit__12), +//Outputs +.o_x(x__13), +.o_y(y__13), +.o_z(z__13), +.o_ux(ux__13), +.o_uy(uy__13), +.o_uz(uz__13), +.o_sz(sz__13), +.o_sr(sr__13), +.o_sleftz(sleftz__13), +.o_sleftr(sleftr__13), +.o_weight(weight__13), +.o_layer(layer__13), +.o_dead(dead__13), +.o_hit(hit__13) +); +PhotonBlock5 photon12( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__11), +.i_y(y__11), +.i_z(z__11), +.i_ux(ux__11), +.i_uy(uy__11), +.i_uz(uz__11), +.i_sz(sz__11), +.i_sr(sr__11), +.i_sleftz(sleftz__11), +.i_sleftr(sleftr__11), +.i_weight(weight__11), +.i_layer(layer__11), +.i_dead(dead__11), +.i_hit(hit__11), +//Outputs +.o_x(x__12), +.o_y(y__12), +.o_z(z__12), +.o_ux(ux__12), +.o_uy(uy__12), +.o_uz(uz__12), +.o_sz(sz__12), +.o_sr(sr__12), +.o_sleftz(sleftz__12), +.o_sleftr(sleftr__12), +.o_weight(weight__12), +.o_layer(layer__12), +.o_dead(dead__12), +.o_hit(hit__12) +); +PhotonBlock5 photon11( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__10), +.i_y(y__10), +.i_z(z__10), +.i_ux(ux__10), +.i_uy(uy__10), +.i_uz(uz__10), +.i_sz(sz__10), +.i_sr(sr__10), +.i_sleftz(sleftz__10), +.i_sleftr(sleftr__10), +.i_weight(weight__10), +.i_layer(layer__10), +.i_dead(dead__10), +.i_hit(hit__10), +//Outputs +.o_x(x__11), +.o_y(y__11), +.o_z(z__11), +.o_ux(ux__11), +.o_uy(uy__11), +.o_uz(uz__11), +.o_sz(sz__11), +.o_sr(sr__11), +.o_sleftz(sleftz__11), +.o_sleftr(sleftr__11), +.o_weight(weight__11), +.o_layer(layer__11), +.o_dead(dead__11), +.o_hit(hit__11) +); +PhotonBlock5 photon10( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__9), +.i_y(y__9), +.i_z(z__9), +.i_ux(ux__9), +.i_uy(uy__9), +.i_uz(uz__9), +.i_sz(sz__9), +.i_sr(sr__9), +.i_sleftz(sleftz__9), +.i_sleftr(sleftr__9), +.i_weight(weight__9), +.i_layer(layer__9), +.i_dead(dead__9), +.i_hit(hit__9), +//Outputs +.o_x(x__10), +.o_y(y__10), +.o_z(z__10), +.o_ux(ux__10), +.o_uy(uy__10), +.o_uz(uz__10), +.o_sz(sz__10), +.o_sr(sr__10), +.o_sleftz(sleftz__10), +.o_sleftr(sleftr__10), +.o_weight(weight__10), +.o_layer(layer__10), +.o_dead(dead__10), +.o_hit(hit__10) +); +PhotonBlock5 photon9( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__8), +.i_y(y__8), +.i_z(z__8), +.i_ux(ux__8), +.i_uy(uy__8), +.i_uz(uz__8), +.i_sz(sz__8), +.i_sr(sr__8), +.i_sleftz(sleftz__8), +.i_sleftr(sleftr__8), +.i_weight(weight__8), +.i_layer(layer__8), +.i_dead(dead__8), +.i_hit(hit__8), +//Outputs +.o_x(x__9), +.o_y(y__9), +.o_z(z__9), +.o_ux(ux__9), +.o_uy(uy__9), +.o_uz(uz__9), +.o_sz(sz__9), +.o_sr(sr__9), +.o_sleftz(sleftz__9), +.o_sleftr(sleftr__9), +.o_weight(weight__9), +.o_layer(layer__9), +.o_dead(dead__9), +.o_hit(hit__9) +); +PhotonBlock5 photon8( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__7), +.i_y(y__7), +.i_z(z__7), +.i_ux(ux__7), +.i_uy(uy__7), +.i_uz(uz__7), +.i_sz(sz__7), +.i_sr(sr__7), +.i_sleftz(sleftz__7), +.i_sleftr(sleftr__7), +.i_weight(weight__7), +.i_layer(layer__7), +.i_dead(dead__7), +.i_hit(hit__7), +//Outputs +.o_x(x__8), +.o_y(y__8), +.o_z(z__8), +.o_ux(ux__8), +.o_uy(uy__8), +.o_uz(uz__8), +.o_sz(sz__8), +.o_sr(sr__8), +.o_sleftz(sleftz__8), +.o_sleftr(sleftr__8), +.o_weight(weight__8), +.o_layer(layer__8), +.o_dead(dead__8), +.o_hit(hit__8) +); +PhotonBlock5 photon7( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__6), +.i_y(y__6), +.i_z(z__6), +.i_ux(ux__6), +.i_uy(uy__6), +.i_uz(uz__6), +.i_sz(sz__6), +.i_sr(sr__6), +.i_sleftz(sleftz__6), +.i_sleftr(sleftr__6), +.i_weight(weight__6), +.i_layer(layer__6), +.i_dead(dead__6), +.i_hit(hit__6), +//Outputs +.o_x(x__7), +.o_y(y__7), +.o_z(z__7), +.o_ux(ux__7), +.o_uy(uy__7), +.o_uz(uz__7), +.o_sz(sz__7), +.o_sr(sr__7), +.o_sleftz(sleftz__7), +.o_sleftr(sleftr__7), +.o_weight(weight__7), +.o_layer(layer__7), +.o_dead(dead__7), +.o_hit(hit__7) +); +PhotonBlock5 photon6( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__5), +.i_y(y__5), +.i_z(z__5), +.i_ux(ux__5), +.i_uy(uy__5), +.i_uz(uz__5), +.i_sz(sz__5), +.i_sr(sr__5), +.i_sleftz(sleftz__5), +.i_sleftr(sleftr__5), +.i_weight(weight__5), +.i_layer(layer__5), +.i_dead(dead__5), +.i_hit(hit__5), +//Outputs +.o_x(x__6), +.o_y(y__6), +.o_z(z__6), +.o_ux(ux__6), +.o_uy(uy__6), +.o_uz(uz__6), +.o_sz(sz__6), +.o_sr(sr__6), +.o_sleftz(sleftz__6), +.o_sleftr(sleftr__6), +.o_weight(weight__6), +.o_layer(layer__6), +.o_dead(dead__6), +.o_hit(hit__6) +); +PhotonBlock5 photon5( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__4), +.i_y(y__4), +.i_z(z__4), +.i_ux(ux__4), +.i_uy(uy__4), +.i_uz(uz__4), +.i_sz(sz__4), +.i_sr(sr__4), +.i_sleftz(sleftz__4), +.i_sleftr(sleftr__4), +.i_weight(weight__4), +.i_layer(layer__4), +.i_dead(dead__4), +.i_hit(hit__4), +//Outputs +.o_x(x__5), +.o_y(y__5), +.o_z(z__5), +.o_ux(ux__5), +.o_uy(uy__5), +.o_uz(uz__5), +.o_sz(sz__5), +.o_sr(sr__5), +.o_sleftz(sleftz__5), +.o_sleftr(sleftr__5), +.o_weight(weight__5), +.o_layer(layer__5), +.o_dead(dead__5), +.o_hit(hit__5) +); +PhotonBlock5 photon4( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__3), +.i_y(y__3), +.i_z(z__3), +.i_ux(ux__3), +.i_uy(uy__3), +.i_uz(uz__3), +.i_sz(sz__3), +.i_sr(sr__3), +.i_sleftz(sleftz__3), +.i_sleftr(sleftr__3), +.i_weight(weight__3), +.i_layer(layer__3), +.i_dead(dead__3), +.i_hit(hit__3), +//Outputs +.o_x(x__4), +.o_y(y__4), +.o_z(z__4), +.o_ux(ux__4), +.o_uy(uy__4), +.o_uz(uz__4), +.o_sz(sz__4), +.o_sr(sr__4), +.o_sleftz(sleftz__4), +.o_sleftr(sleftr__4), +.o_weight(weight__4), +.o_layer(layer__4), +.o_dead(dead__4), +.o_hit(hit__4) +); +PhotonBlock5 photon3( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__2), +.i_y(y__2), +.i_z(z__2), +.i_ux(ux__2), +.i_uy(uy__2), +.i_uz(uz__2), +.i_sz(sz__2), +.i_sr(sr__2), +.i_sleftz(sleftz__2), +.i_sleftr(sleftr__2), +.i_weight(weight__2), +.i_layer(layer__2), +.i_dead(dead__2), +.i_hit(hit__2), +//Outputs +.o_x(x__3), +.o_y(y__3), +.o_z(z__3), +.o_ux(ux__3), +.o_uy(uy__3), +.o_uz(uz__3), +.o_sz(sz__3), +.o_sr(sr__3), +.o_sleftz(sleftz__3), +.o_sleftr(sleftr__3), +.o_weight(weight__3), +.o_layer(layer__3), +.o_dead(dead__3), +.o_hit(hit__3) +); +PhotonBlock5 photon2( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__1), +.i_y(y__1), +.i_z(z__1), +.i_ux(ux__1), +.i_uy(uy__1), +.i_uz(uz__1), +.i_sz(sz__1), +.i_sr(sr__1), +.i_sleftz(sleftz__1), +.i_sleftr(sleftr__1), +.i_weight(weight__1), +.i_layer(layer__1), +.i_dead(dead__1), +.i_hit(hit__1), +//Outputs +.o_x(x__2), +.o_y(y__2), +.o_z(z__2), +.o_ux(ux__2), +.o_uy(uy__2), +.o_uz(uz__2), +.o_sz(sz__2), +.o_sr(sr__2), +.o_sleftz(sleftz__2), +.o_sleftr(sleftr__2), +.o_weight(weight__2), +.o_layer(layer__2), +.o_dead(dead__2), +.o_hit(hit__2) +); +PhotonBlock5 photon1( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__0), +.i_y(y__0), +.i_z(z__0), +.i_ux(ux__0), +.i_uy(uy__0), +.i_uz(uz__0), +.i_sz(sz__0), +.i_sr(sr__0), +.i_sleftz(sleftz__0), +.i_sleftr(sleftr__0), +.i_weight(weight__0), +.i_layer(layer__0), +.i_dead(dead__0), +.i_hit(hit__0), +//Outputs +.o_x(x__1), +.o_y(y__1), +.o_z(z__1), +.o_ux(ux__1), +.o_uy(uy__1), +.o_uz(uz__1), +.o_sz(sz__1), +.o_sr(sr__1), +.o_sleftz(sleftz__1), +.o_sleftr(sleftr__1), +.o_weight(weight__1), +.o_layer(layer__1), +.o_dead(dead__1), +.o_hit(hit__1) +); + + + +////////////////////////////////////////////////////////////////////////////// +//Tapping into the Registered Pipeline +//***NOTE: Index must be incremented by 1 compared to SystemC version +////////////////////////////////////////////////////////////////////////////// + +//>>>>>>>>>>>>> Absorber <<<<<<<<<<<<<<<<<< +wire [`BIT_WIDTH-1:0] x_pipe, y_pipe, z_pipe; +wire [`LAYER_WIDTH-1:0] layer_pipe; +assign x_pipe=x__2; +assign y_pipe=y__2; +assign z_pipe=z__14; //TODO: Check square-root latency and modify z[14] if needed!!!! +assign layer_pipe=layer__4; + +//>>>>>>>>>>>>> ScattererReflectorWrapper <<<<<<<<<<<<<<<<<< +wire [`BIT_WIDTH-1:0] ux_scatterer; +wire [`BIT_WIDTH-1:0] uy_scatterer; +wire [`BIT_WIDTH-1:0] uz_scatterer; +wire [`BIT_WIDTH-1:0] ux_reflector; +wire [`BIT_WIDTH-1:0] uy_reflector; +wire [`BIT_WIDTH-1:0] uz_reflector; +wire [`LAYER_WIDTH-1:0] layer_reflector; +wire dead_reflector; + + + + +////////////////////////////////////////////////////////////////////////////// +//Connect up different modules +////////////////////////////////////////////////////////////////////////////// + +//>>>>>>>>>>>>> Absorber <<<<<<<<<<<<<<<<<< + +Absorber absorb ( //INPUTS + .clock(clock) , .reset(reset), .enable(enable), + + //From hopper + .weight_hop(i_weight), .hit_hop(i_hit), .dead_hop(i_dead), + + //From Shared Registers + .x_pipe (x_pipe), .y_pipe (y_pipe), .z_pipe(z_pipe), .layer_pipe(layer_pipe), + + //From System Register File (5 layers) + .muaFraction1(muaFraction1), .muaFraction2(muaFraction2), .muaFraction3(muaFraction3), .muaFraction4(muaFraction4), .muaFraction5(muaFraction5), + + //Dual-port Mem + .data(data), .rdaddress(rdaddress), .wraddress(wraddress), + .wren(wren), .q(q), + + //OUTPUT + .weight_absorber(o_weight) + + ); + +//>>>>>>>>>>>>> ScattererReflectorWrapper <<<<<<<<<<<<<<<<<< + +ScattererReflectorWrapper scattererReflector( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + //Inputs + + //Photon values + .i_uz1_pipeWrapper(uz__1), + .i_hit2_pipeWrapper(hit__1), + .i_ux3_pipeWrapper(ux__3), + .i_uz3_pipeWrapper(uz__3), + .i_layer3_pipeWrapper(layer__3), + .i_hit4_pipeWrapper(hit__3), + .i_hit6_pipeWrapper(hit__5), + .i_hit16_pipeWrapper(hit__15), + .i_layer31_pipeWrapper(layer__31), + .i_uy32_pipeWrapper(uy__32), + .i_uz32_pipeWrapper(uz__32), + .i_hit33_pipeWrapper(hit__32), + .i_ux33_pipeWrapper(ux__33), + .i_uy33_pipeWrapper(uy__33), + .i_hit34_pipeWrapper(hit__33), + .i_ux35_pipeWrapper(ux__35), + .i_uy35_pipeWrapper(uy__35), + .i_uz35_pipeWrapper(uz__35), + .i_layer35_pipeWrapper(layer__35), + .i_hit36_pipeWrapper(hit__35), + .i_ux36_pipeWrapper(ux__36), + .i_uy36_pipeWrapper(uy__36), + .i_uz36_pipeWrapper(uz__36), + .i_layer36_pipeWrapper(layer__36), + .i_dead36_pipeWrapper(dead__36), + + //Memory Interface + //Inputs + .rand2(rand2), + .rand3(rand3), + .rand5(rand5), + .sint(sint), + .cost(cost), + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + //Outputs + .tindex(tindex), + .fresIndex(fresIndex), + + //Constants + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + //Outputs + .ux_scatterer(ux_scatterer), + .uy_scatterer(uy_scatterer), + .uz_scatterer(uz_scatterer), + + .ux_reflector(ux_reflector), + .uy_reflector(uy_reflector), + .uz_reflector(uz_reflector), + .layer_reflector(layer_reflector), + .dead_reflector(dead_reflector) + ); + + +////////////////////////////////////////////////////////////////////// +//// dead or alive MUX //// +//// //// +//// Description: //// +//// Used to determine whether the output from the scatterer //// +//// or the reflector should be used in any clock cycle //// +////////////////////////////////////////////////////////////////////// + +always @ (hit__37 or ux_scatterer or uy_scatterer or uz_scatterer or layer__37 or dead__37 or + ux_reflector or uy_reflector or uz_reflector or layer_reflector or dead_reflector) begin + case (hit__37) + 0: begin + o_ux = ux_scatterer; + o_uy = uy_scatterer; + o_uz = uz_scatterer; + o_layer = layer__37; + o_dead = dead__37; + end + 1: begin + o_ux = ux_reflector; + o_uy = uy_reflector; + o_uz = uz_reflector; + o_layer = layer_reflector; + o_dead = dead_reflector; + end + endcase + +end + +endmodule + +//Photons that make up the register pipeline +module PhotonBlock5( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + i_ux, + i_uy, + i_uz, + i_sz, + i_sr, + i_sleftz, + i_sleftr, + i_weight, + i_layer, + i_dead, + i_hit, + //Outputs + o_x, + o_y, + o_z, + o_ux, + o_uy, + o_uz, + o_sz, + o_sr, + o_sleftz, + o_sleftr, + o_weight, + o_layer, + o_dead, + o_hit + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; +input [`BIT_WIDTH-1:0] i_ux; +input [`BIT_WIDTH-1:0] i_uy; +input [`BIT_WIDTH-1:0] i_uz; +input [`BIT_WIDTH-1:0] i_sz; +input [`BIT_WIDTH-1:0] i_sr; +input [`BIT_WIDTH-1:0] i_sleftz; +input [`BIT_WIDTH-1:0] i_sleftr; +input [`BIT_WIDTH-1:0] i_weight; +input [`LAYER_WIDTH-1:0] i_layer; +input i_dead; +input i_hit; + + +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; +output [`BIT_WIDTH-1:0] o_ux; +output [`BIT_WIDTH-1:0] o_uy; +output [`BIT_WIDTH-1:0] o_uz; +output [`BIT_WIDTH-1:0] o_sz; +output [`BIT_WIDTH-1:0] o_sr; +output [`BIT_WIDTH-1:0] o_sleftz; +output [`BIT_WIDTH-1:0] o_sleftr; +output [`BIT_WIDTH-1:0] o_weight; +output [`LAYER_WIDTH-1:0] o_layer; +output o_dead; +output o_hit; + + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire [`BIT_WIDTH-1:0] i_y; +wire [`BIT_WIDTH-1:0] i_z; +wire [`BIT_WIDTH-1:0] i_ux; +wire [`BIT_WIDTH-1:0] i_uy; +wire [`BIT_WIDTH-1:0] i_uz; +wire [`BIT_WIDTH-1:0] i_sz; +wire [`BIT_WIDTH-1:0] i_sr; +wire [`BIT_WIDTH-1:0] i_sleftz; +wire [`BIT_WIDTH-1:0] i_sleftr; +wire [`BIT_WIDTH-1:0] i_weight; +wire [`LAYER_WIDTH-1:0] i_layer; +wire i_dead; +wire i_hit; + + +reg [`BIT_WIDTH-1:0] o_x; +reg [`BIT_WIDTH-1:0] o_y; +reg [`BIT_WIDTH-1:0] o_z; +reg [`BIT_WIDTH-1:0] o_ux; +reg [`BIT_WIDTH-1:0] o_uy; +reg [`BIT_WIDTH-1:0] o_uz; +reg [`BIT_WIDTH-1:0] o_sz; +reg [`BIT_WIDTH-1:0] o_sr; +reg [`BIT_WIDTH-1:0] o_sleftz; +reg [`BIT_WIDTH-1:0] o_sleftr; +reg [`BIT_WIDTH-1:0] o_weight; +reg [`LAYER_WIDTH-1:0] o_layer; +reg o_dead; +reg o_hit; + + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}}; + o_y <= {`BIT_WIDTH{1'b0}}; + o_z <= {`BIT_WIDTH{1'b0}}; + o_ux <= {`BIT_WIDTH{1'b0}}; + o_uy <= {`BIT_WIDTH{1'b0}}; + o_uz <= {`BIT_WIDTH{1'b0}}; + o_sz <= {`BIT_WIDTH{1'b0}}; + o_sr <= {`BIT_WIDTH{1'b0}}; + o_sleftz <= {`BIT_WIDTH{1'b0}}; + o_sleftr <= {`BIT_WIDTH{1'b0}}; + o_weight <= {`BIT_WIDTH{1'b0}}; + o_layer <= {`LAYER_WIDTH{1'b0}}; + o_dead <= 1'b1; + o_hit <= 1'b0; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + o_ux <= i_ux; + o_uy <= i_uy; + o_uz <= i_uz; + o_sz <= i_sz; + o_sr <= i_sr; + o_sleftz <= i_sleftz; + o_sleftr <= i_sleftr; + o_weight <= i_weight; + o_layer <= i_layer; + o_dead <= i_dead; + o_hit <= i_hit; + end +endmodule + + +//module FluenceUpdate ( //INPUTS +module Absorber ( //INPUTS + clock, reset, enable, + + //From hopper + weight_hop, hit_hop, dead_hop, + + //From Shared Registers + x_pipe, y_pipe, z_pipe, layer_pipe, + + //From System Register File (5 layers) + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + + //I/O to on-chip mem -- check interface + data, rdaddress, wraddress, wren, q, + + //OUTPUT + weight_absorber + + ); + + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter `NR=256; +//parameter `NZ=256; +// +//parameter `NR_EXP=8; //meaning `NR=2^`NR_exp or 2^8=256 +//parameter `RGRID_SCLAE_EXP=21; //2^21 = RGRID_SCALE +//parameter `ZGRID_SCLAE_EXP=21; //2^21 = ZGRID_SCALE +// +// +//parameter `BIT_WIDTH=32; +//parameter `BIT_WIDTH_2=64; +//parameter `WORD_WIDTH=64; +//parameter `ADDR_WIDTH=16; //256x256=2^8*2^8=2^16 +// +// +//parameter `LAYER_WIDTH=3; +//parameter `PIPE_DEPTH = 37; + + +////////////////////////////////////////////////////////////////////////////// +//INPUTS +////////////////////////////////////////////////////////////////////////////// +input clock; +input reset; +input enable; + +//From hopper +input [`BIT_WIDTH-1:0] weight_hop; +input hit_hop; +input dead_hop; + +//From Shared Reg +//input signed [`BIT_WIDTH-1:0] x_pipe; +//input signed [`BIT_WIDTH-1:0] y_pipe; +input [`BIT_WIDTH-1:0] x_pipe; +input [`BIT_WIDTH-1:0] y_pipe; +input [`BIT_WIDTH-1:0] z_pipe; +input [`LAYER_WIDTH-1:0] layer_pipe; + +//From System Reg File +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + +////////////////////////////////////////////////////////////////////////////// +//OUTPUTS +////////////////////////////////////////////////////////////////////////////// +output [`BIT_WIDTH-1:0] weight_absorber; + +////////////////////////////////////////////////////////////////////////////// +//I/O to on-chip mem -- check interface +////////////////////////////////////////////////////////////////////////////// +output [`WORD_WIDTH-1:0] data; +output [`ADDR_WIDTH-1:0] rdaddress, wraddress; +output wren; +reg wren; +input [`WORD_WIDTH-1:0] q; + +////////////////////////////////////////////////////////////////////////////// +//Local AND Registered Value Variables +////////////////////////////////////////////////////////////////////////////// +//STAGE 1 - Do nothing + +//STAGE 2 +reg [`BIT_WIDTH_2-1:0] x2_temp, y2_temp; //From mult +reg [`BIT_WIDTH_2-1:0] x2_P, y2_P; //Registered Value + +//STAGE 3 +reg [`BIT_WIDTH_2-1:0] r2_temp, r2_P; +wire [`BIT_WIDTH_2-1:0] r2_P_wire; + +//STAGE 4 +reg [`BIT_WIDTH-1:0] fractionScaled; +reg [`BIT_WIDTH-1:0] weight_P4; +reg [`BIT_WIDTH-1:0] r_P; +wire [`BIT_WIDTH-1:0] r_P_wire; + +reg [`BIT_WIDTH_2-1:0] product64bit; +reg [`BIT_WIDTH-1:0] dwa_temp; + +//STAGE 14 +reg [`BIT_WIDTH-1:0] ir_temp; +reg [`BIT_WIDTH-1:0] iz_temp; + +//STAGE 15 +reg [`BIT_WIDTH-1:0] ir_P; +reg [`BIT_WIDTH-1:0] iz_P; +reg [`BIT_WIDTH-1:0] ir_scaled; +reg [`ADDR_WIDTH-1:0] rADDR_temp; +reg [`ADDR_WIDTH-1:0] rADDR_16; + +//STAGE 16 +reg [`WORD_WIDTH-1:0] oldAbs_MEM; +reg [`WORD_WIDTH-1:0] oldAbs_P; +reg [`ADDR_WIDTH-1:0] rADDR_17; + +//STAGE 17 +reg [`BIT_WIDTH-1:0] weight_P; +reg [`BIT_WIDTH-1:0] dwa_P; +reg [`BIT_WIDTH-1:0] newWeight; + +reg [`WORD_WIDTH-1:0] newAbs_P; +reg [`WORD_WIDTH-1:0] newAbs_temp; + +//reg [`ADDR_WIDTH-1:0] wADDR; + + +////////////////////////////////////////////////////////////////////////////// +//PIPELINE weight, hit, dead +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS + +//peter m made this manual +//wire [32-1:0] weight [37:0]; + +wire [32-1:0] weight__0; +wire [32-1:0] weight__1; +wire [32-1:0] weight__2; +wire [32-1:0] weight__3; +wire [32-1:0] weight__4; +wire [32-1:0] weight__5; +wire [32-1:0] weight__6; +wire [32-1:0] weight__7; +wire [32-1:0] weight__8; +wire [32-1:0] weight__9; +wire [32-1:0] weight__10; +wire [32-1:0] weight__11; +wire [32-1:0] weight__12; +wire [32-1:0] weight__13; +wire [32-1:0] weight__14; +wire [32-1:0] weight__15; +wire [32-1:0] weight__16; +wire [32-1:0] weight__17; +wire [32-1:0] weight__18; +wire [32-1:0] weight__19; +wire [32-1:0] weight__20; +wire [32-1:0] weight__21; +wire [32-1:0] weight__22; +wire [32-1:0] weight__23; +wire [32-1:0] weight__24; +wire [32-1:0] weight__25; +wire [32-1:0] weight__26; +wire [32-1:0] weight__27; +wire [32-1:0] weight__28; +wire [32-1:0] weight__29; +wire [32-1:0] weight__30; +wire [32-1:0] weight__31; +wire [32-1:0] weight__32; +wire [32-1:0] weight__33; +wire [32-1:0] weight__34; +wire [32-1:0] weight__35; +wire [32-1:0] weight__36; +wire [32-1:0] weight__37; + + +//wire [37:0] hit ; +wire hit__0; +wire hit__1; +wire hit__2; +wire hit__3; +wire hit__4; +wire hit__5; +wire hit__6; +wire hit__7; +wire hit__8; +wire hit__9; +wire hit__10; +wire hit__11; +wire hit__12; +wire hit__13; +wire hit__14; +wire hit__15; +wire hit__16; +wire hit__17; +wire hit__18; +wire hit__19; +wire hit__20; +wire hit__21; +wire hit__22; +wire hit__23; +wire hit__24; +wire hit__25; +wire hit__26; +wire hit__27; +wire hit__28; +wire hit__29; +wire hit__30; +wire hit__31; +wire hit__32; +wire hit__33; +wire hit__34; +wire hit__35; +wire hit__36; +wire hit__37; + + + +//wire [37:0] dead ; +wire dead__0; +wire dead__1; +wire dead__2; +wire dead__3; +wire dead__4; +wire dead__5; +wire dead__6; +wire dead__7; +wire dead__8; +wire dead__9; +wire dead__10; +wire dead__11; +wire dead__12; +wire dead__13; +wire dead__14; +wire dead__15; +wire dead__16; +wire dead__17; +wire dead__18; +wire dead__19; +wire dead__20; +wire dead__21; +wire dead__22; +wire dead__23; +wire dead__24; +wire dead__25; +wire dead__26; +wire dead__27; +wire dead__28; +wire dead__29; +wire dead__30; +wire dead__31; +wire dead__32; +wire dead__33; +wire dead__34; +wire dead__35; +wire dead__36; +wire dead__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign weight__0 = weight_hop; +assign hit__0 = hit_hop; +assign dead__0 = dead_hop; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +assign weight_absorber = weight__37; + +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=`PIPE_DEPTH; i>0; i=i-1) begin: weightHitDeadPipe +// case(i) +// +// //REGISTER 17 on diagram!! +// 18: +// begin +// +// PhotonBlock2 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(newWeight), +// .i_y(hit[17]), +// .i_z(dead[17]), +// +// //Outputs +// .o_x(weight[18]), +// .o_y(hit[18]), +// .o_z(dead[18]) +// ); +// +// end +// default: +// begin +// PhotonBlock2 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(weight[i-1]), +// .i_y(hit[i-1]), +// .i_z(dead[i-1]), +// +// //Outputs +// .o_x(weight[i]), +// .o_y(hit[i]), +// .o_z(dead[i]) +// ); +// end +// endcase +// end +//endgenerate + +//Expand pipeline generation +//special case i = 18 first +PhotonBlock2 photon18( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(newWeight), + .i_y(hit__17), + .i_z(dead__17), + + //Outputs + .o_x(weight__18), + .o_y(hit__18), + .o_z(dead__18) + ); + +PhotonBlock2 photon37( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__36), +.i_y(hit__36), +.i_z(dead__36), +//Outputs + .o_x(weight__37), +.o_y(hit__37), +.o_z(dead__37) +); + +PhotonBlock2 photon36( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__35), +.i_y(hit__35), +.i_z(dead__35), +//Outputs + .o_x(weight__36), +.o_y(hit__36), +.o_z(dead__36) +); + +PhotonBlock2 photon35( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__34), +.i_y(hit__34), +.i_z(dead__34), +//Outputs + .o_x(weight__35), +.o_y(hit__35), +.o_z(dead__35) +); + +PhotonBlock2 photon34( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__33), +.i_y(hit__33), +.i_z(dead__33), +//Outputs + .o_x(weight__34), +.o_y(hit__34), +.o_z(dead__34) +); + +PhotonBlock2 photon33( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__32), +.i_y(hit__32), +.i_z(dead__32), +//Outputs + .o_x(weight__33), +.o_y(hit__33), +.o_z(dead__33) +); + +PhotonBlock2 photon32( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__31), +.i_y(hit__31), +.i_z(dead__31), +//Outputs + .o_x(weight__32), +.o_y(hit__32), +.o_z(dead__32) +); + +PhotonBlock2 photon31( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__30), +.i_y(hit__30), +.i_z(dead__30), +//Outputs + .o_x(weight__31), +.o_y(hit__31), +.o_z(dead__31) +); + +PhotonBlock2 photon30( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__29), +.i_y(hit__29), +.i_z(dead__29), +//Outputs + .o_x(weight__30), +.o_y(hit__30), +.o_z(dead__30) +); + +PhotonBlock2 photon29( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__28), +.i_y(hit__28), +.i_z(dead__28), +//Outputs + .o_x(weight__29), +.o_y(hit__29), +.o_z(dead__29) +); + +PhotonBlock2 photon28( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__27), +.i_y(hit__27), +.i_z(dead__27), +//Outputs + .o_x(weight__28), +.o_y(hit__28), +.o_z(dead__28) +); + +PhotonBlock2 photon27( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__26), +.i_y(hit__26), +.i_z(dead__26), +//Outputs + .o_x(weight__27), +.o_y(hit__27), +.o_z(dead__27) +); + +PhotonBlock2 photon26( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__25), +.i_y(hit__25), +.i_z(dead__25), +//Outputs + .o_x(weight__26), +.o_y(hit__26), +.o_z(dead__26) +); + +PhotonBlock2 photon25( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__24), +.i_y(hit__24), +.i_z(dead__24), +//Outputs + .o_x(weight__25), +.o_y(hit__25), +.o_z(dead__25) +); + +PhotonBlock2 photon24( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__23), +.i_y(hit__23), +.i_z(dead__23), +//Outputs + .o_x(weight__24), +.o_y(hit__24), +.o_z(dead__24) +); + +PhotonBlock2 photon23( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__22), +.i_y(hit__22), +.i_z(dead__22), +//Outputs + .o_x(weight__23), +.o_y(hit__23), +.o_z(dead__23) +); + +PhotonBlock2 photon22( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__21), +.i_y(hit__21), +.i_z(dead__21), +//Outputs + .o_x(weight__22), +.o_y(hit__22), +.o_z(dead__22) +); + +PhotonBlock2 photon21( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__20), +.i_y(hit__20), +.i_z(dead__20), +//Outputs + .o_x(weight__21), +.o_y(hit__21), +.o_z(dead__21) +); + +PhotonBlock2 photon20( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__19), +.i_y(hit__19), +.i_z(dead__19), +//Outputs + .o_x(weight__20), +.o_y(hit__20), +.o_z(dead__20) +); + +PhotonBlock2 photon19( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__18), +.i_y(hit__18), +.i_z(dead__18), +//Outputs + .o_x(weight__19), +.o_y(hit__19), +.o_z(dead__19) +); + + +PhotonBlock2 photon17( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__16), +.i_y(hit__16), +.i_z(dead__16), +//Outputs + .o_x(weight__17), +.o_y(hit__17), +.o_z(dead__17) +); + +PhotonBlock2 photon16( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__15), +.i_y(hit__15), +.i_z(dead__15), +//Outputs + .o_x(weight__16), +.o_y(hit__16), +.o_z(dead__16) +); + +PhotonBlock2 photon15( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__14), +.i_y(hit__14), +.i_z(dead__14), +//Outputs + .o_x(weight__15), +.o_y(hit__15), +.o_z(dead__15) +); + +PhotonBlock2 photon14( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__13), +.i_y(hit__13), +.i_z(dead__13), +//Outputs + .o_x(weight__14), +.o_y(hit__14), +.o_z(dead__14) +); + +PhotonBlock2 photon13( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__12), +.i_y(hit__12), +.i_z(dead__12), +//Outputs + .o_x(weight__13), +.o_y(hit__13), +.o_z(dead__13) +); + +PhotonBlock2 photon12( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__11), +.i_y(hit__11), +.i_z(dead__11), +//Outputs + .o_x(weight__12), +.o_y(hit__12), +.o_z(dead__12) +); + +PhotonBlock2 photon11( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__10), +.i_y(hit__10), +.i_z(dead__10), +//Outputs + .o_x(weight__11), +.o_y(hit__11), +.o_z(dead__11) +); + +PhotonBlock2 photon10( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__9), +.i_y(hit__9), +.i_z(dead__9), +//Outputs + .o_x(weight__10), +.o_y(hit__10), +.o_z(dead__10) +); + +PhotonBlock2 photon9( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__8), +.i_y(hit__8), +.i_z(dead__8), +//Outputs + .o_x(weight__9), +.o_y(hit__9), +.o_z(dead__9) +); + +PhotonBlock2 photon8( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__7), +.i_y(hit__7), +.i_z(dead__7), +//Outputs + .o_x(weight__8), +.o_y(hit__8), +.o_z(dead__8) +); + +PhotonBlock2 photon7( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__6), +.i_y(hit__6), +.i_z(dead__6), +//Outputs + .o_x(weight__7), +.o_y(hit__7), +.o_z(dead__7) +); + +PhotonBlock2 photon6( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__5), +.i_y(hit__5), +.i_z(dead__5), +//Outputs + .o_x(weight__6), +.o_y(hit__6), +.o_z(dead__6) +); + +PhotonBlock2 photon5( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__4), +.i_y(hit__4), +.i_z(dead__4), +//Outputs + .o_x(weight__5), +.o_y(hit__5), +.o_z(dead__5) +); + +PhotonBlock2 photon4( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__3), +.i_y(hit__3), +.i_z(dead__3), +//Outputs + .o_x(weight__4), +.o_y(hit__4), +.o_z(dead__4) +); + +PhotonBlock2 photon3( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__2), +.i_y(hit__2), +.i_z(dead__2), +//Outputs + .o_x(weight__3), +.o_y(hit__3), +.o_z(dead__3) +); + +PhotonBlock2 photon2( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__1), +.i_y(hit__1), +.i_z(dead__1), +//Outputs + .o_x(weight__2), +.o_y(hit__2), +.o_z(dead__2) +); + +PhotonBlock2 photon1( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__0), +.i_y(hit__0), +.i_z(dead__0), +//Outputs + .o_x(weight__1), +.o_y(hit__1), +.o_z(dead__1) +); + + +////////////////////////////////////////////////////////////////////////////// +//PIPELINE ir,iz,dwa +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS +//wire [32-1:0] ir [37:0]; + +wire [32-1:0] ir__0; +wire [32-1:0] ir__1; +wire [32-1:0] ir__2; +wire [32-1:0] ir__3; +wire [32-1:0] ir__4; +wire [32-1:0] ir__5; +wire [32-1:0] ir__6; +wire [32-1:0] ir__7; +wire [32-1:0] ir__8; +wire [32-1:0] ir__9; +wire [32-1:0] ir__10; +wire [32-1:0] ir__11; +wire [32-1:0] ir__12; +wire [32-1:0] ir__13; +wire [32-1:0] ir__14; +wire [32-1:0] ir__15; +wire [32-1:0] ir__16; +wire [32-1:0] ir__17; +wire [32-1:0] ir__18; +wire [32-1:0] ir__19; +wire [32-1:0] ir__20; +wire [32-1:0] ir__21; +wire [32-1:0] ir__22; +wire [32-1:0] ir__23; +wire [32-1:0] ir__24; +wire [32-1:0] ir__25; +wire [32-1:0] ir__26; +wire [32-1:0] ir__27; +wire [32-1:0] ir__28; +wire [32-1:0] ir__29; +wire [32-1:0] ir__30; +wire [32-1:0] ir__31; +wire [32-1:0] ir__32; +wire [32-1:0] ir__33; +wire [32-1:0] ir__34; +wire [32-1:0] ir__35; +wire [32-1:0] ir__36; +wire [32-1:0] ir__37; + + +//wire [32-1:0] iz [37:0]; + + +wire [32-1:0] iz__0; +wire [32-1:0] iz__1; +wire [32-1:0] iz__2; +wire [32-1:0] iz__3; +wire [32-1:0] iz__4; +wire [32-1:0] iz__5; +wire [32-1:0] iz__6; +wire [32-1:0] iz__7; +wire [32-1:0] iz__8; +wire [32-1:0] iz__9; +wire [32-1:0] iz__10; +wire [32-1:0] iz__11; +wire [32-1:0] iz__12; +wire [32-1:0] iz__13; +wire [32-1:0] iz__14; +wire [32-1:0] iz__15; +wire [32-1:0] iz__16; +wire [32-1:0] iz__17; +wire [32-1:0] iz__18; +wire [32-1:0] iz__19; +wire [32-1:0] iz__20; +wire [32-1:0] iz__21; +wire [32-1:0] iz__22; +wire [32-1:0] iz__23; +wire [32-1:0] iz__24; +wire [32-1:0] iz__25; +wire [32-1:0] iz__26; +wire [32-1:0] iz__27; +wire [32-1:0] iz__28; +wire [32-1:0] iz__29; +wire [32-1:0] iz__30; +wire [32-1:0] iz__31; +wire [32-1:0] iz__32; +wire [32-1:0] iz__33; +wire [32-1:0] iz__34; +wire [32-1:0] iz__35; +wire [32-1:0] iz__36; +wire [32-1:0] iz__37; + + +//wire [32-1:0] dwa [37:0]; + + +wire [32-1:0] dwa__0; +wire [32-1:0] dwa__1; +wire [32-1:0] dwa__2; +wire [32-1:0] dwa__3; +wire [32-1:0] dwa__4; +wire [32-1:0] dwa__5; +wire [32-1:0] dwa__6; +wire [32-1:0] dwa__7; +wire [32-1:0] dwa__8; +wire [32-1:0] dwa__9; +wire [32-1:0] dwa__10; +wire [32-1:0] dwa__11; +wire [32-1:0] dwa__12; +wire [32-1:0] dwa__13; +wire [32-1:0] dwa__14; +wire [32-1:0] dwa__15; +wire [32-1:0] dwa__16; +wire [32-1:0] dwa__17; +wire [32-1:0] dwa__18; +wire [32-1:0] dwa__19; +wire [32-1:0] dwa__20; +wire [32-1:0] dwa__21; +wire [32-1:0] dwa__22; +wire [32-1:0] dwa__23; +wire [32-1:0] dwa__24; +wire [32-1:0] dwa__25; +wire [32-1:0] dwa__26; +wire [32-1:0] dwa__27; +wire [32-1:0] dwa__28; +wire [32-1:0] dwa__29; +wire [32-1:0] dwa__30; +wire [32-1:0] dwa__31; +wire [32-1:0] dwa__32; +wire [32-1:0] dwa__33; +wire [32-1:0] dwa__34; +wire [32-1:0] dwa__35; +wire [32-1:0] dwa__36; +wire [32-1:0] dwa__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign ir__0 = 32'b0; +assign iz__0 = 32'b0; +assign dwa__0 = 32'b0; + +//GENERATE PIPELINE +//generate +// for(i=`PIPE_DEPTH; i>0; i=i-1) begin: IrIzDwaPipe +// case(i) +// +// //NOTE: STAGE 14 --> REGISTER 14 on diagram !! ir, iz +// 15: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir_temp), +// .i_y(iz_temp), +// .i_z(dwa[14]), +// +// //Outputs +// .o_x(ir[15]), +// .o_y(iz[15]), +// .o_z(dwa[15]) +// ); +// +// end +// +// //NOTE: STAGE 4 --> REGISTER 4 on diagram !! dwa +// 5: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir[4]), +// .i_y(iz[4]), +// .i_z(dwa_temp), +// +// //Outputs +// .o_x(ir[5]), +// .o_y(iz[5]), +// .o_z(dwa[5]) +// ); +// +// end +// +// default: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir[i-1]), +// .i_y(iz[i-1]), +// .i_z(dwa[i-1]), +// +// //Outputs +// .o_x(ir[i]), +// .o_y(iz[i]), +// .o_z(dwa[i]) +// ); +// end +// endcase +// end +//endgenerate + +//Expanded generation + + +//special cases first peter m + + + + PhotonBlock1 photon15q( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(ir_temp), + .i_y(iz_temp), + .i_z(dwa__14), + + //Outputs + .o_x(ir__15), + .o_y(iz__15), + .o_z(dwa__15) + ); + + + + //NOTE: STAGE 4 --> REGISTER 4 on diagram !! dwa + + + PhotonBlock1 photon5q( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(ir__4), + .i_y(iz__4), + .i_z(dwa_temp), + + //Outputs + .o_x(ir__5), + .o_y(iz__5), + .o_z(dwa__5) + ); + + PhotonBlock1 photon37q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__36), +.i_y(iz__36), +.i_z(dwa__36), +//Outputs + .o_x(ir__37), +.o_y(iz__37), +.o_z(dwa__37) +); +PhotonBlock1 photon36q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__35), +.i_y(iz__35), +.i_z(dwa__35), +//Outputs + .o_x(ir__36), +.o_y(iz__36), +.o_z(dwa__36) +); +PhotonBlock1 photon35q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__34), +.i_y(iz__34), +.i_z(dwa__34), +//Outputs + .o_x(ir__35), +.o_y(iz__35), +.o_z(dwa__35) +); +PhotonBlock1 photon34q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__33), +.i_y(iz__33), +.i_z(dwa__33), +//Outputs + .o_x(ir__34), +.o_y(iz__34), +.o_z(dwa__34) +); +PhotonBlock1 photon33q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__32), +.i_y(iz__32), +.i_z(dwa__32), +//Outputs + .o_x(ir__33), +.o_y(iz__33), +.o_z(dwa__33) +); +PhotonBlock1 photon32q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__31), +.i_y(iz__31), +.i_z(dwa__31), +//Outputs + .o_x(ir__32), +.o_y(iz__32), +.o_z(dwa__32) +); +PhotonBlock1 photon31q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__30), +.i_y(iz__30), +.i_z(dwa__30), +//Outputs + .o_x(ir__31), +.o_y(iz__31), +.o_z(dwa__31) +); +PhotonBlock1 photon30q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__29), +.i_y(iz__29), +.i_z(dwa__29), +//Outputs + .o_x(ir__30), +.o_y(iz__30), +.o_z(dwa__30) +); +PhotonBlock1 photon29q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__28), +.i_y(iz__28), +.i_z(dwa__28), +//Outputs + .o_x(ir__29), +.o_y(iz__29), +.o_z(dwa__29) +); +PhotonBlock1 photon28q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__27), +.i_y(iz__27), +.i_z(dwa__27), +//Outputs + .o_x(ir__28), +.o_y(iz__28), +.o_z(dwa__28) +); +PhotonBlock1 photon27q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__26), +.i_y(iz__26), +.i_z(dwa__26), +//Outputs + .o_x(ir__27), +.o_y(iz__27), +.o_z(dwa__27) +); +PhotonBlock1 photon26q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__25), +.i_y(iz__25), +.i_z(dwa__25), +//Outputs + .o_x(ir__26), +.o_y(iz__26), +.o_z(dwa__26) +); +PhotonBlock1 photon25q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__24), +.i_y(iz__24), +.i_z(dwa__24), +//Outputs + .o_x(ir__25), +.o_y(iz__25), +.o_z(dwa__25) +); +PhotonBlock1 photon24q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__23), +.i_y(iz__23), +.i_z(dwa__23), +//Outputs + .o_x(ir__24), +.o_y(iz__24), +.o_z(dwa__24) +); +PhotonBlock1 photon23q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__22), +.i_y(iz__22), +.i_z(dwa__22), +//Outputs + .o_x(ir__23), +.o_y(iz__23), +.o_z(dwa__23) +); +PhotonBlock1 photon22q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__21), +.i_y(iz__21), +.i_z(dwa__21), +//Outputs + .o_x(ir__22), +.o_y(iz__22), +.o_z(dwa__22) +); +PhotonBlock1 photon21q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__20), +.i_y(iz__20), +.i_z(dwa__20), +//Outputs + .o_x(ir__21), +.o_y(iz__21), +.o_z(dwa__21) +); +PhotonBlock1 photon20q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__19), +.i_y(iz__19), +.i_z(dwa__19), +//Outputs + .o_x(ir__20), +.o_y(iz__20), +.o_z(dwa__20) +); +PhotonBlock1 photon19q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__18), +.i_y(iz__18), +.i_z(dwa__18), +//Outputs + .o_x(ir__19), +.o_y(iz__19), +.o_z(dwa__19) +); +PhotonBlock1 photon18q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__17), +.i_y(iz__17), +.i_z(dwa__17), +//Outputs + .o_x(ir__18), +.o_y(iz__18), +.o_z(dwa__18) +); +PhotonBlock1 photon17q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__16), +.i_y(iz__16), +.i_z(dwa__16), +//Outputs + .o_x(ir__17), +.o_y(iz__17), +.o_z(dwa__17) +); +PhotonBlock1 photon16q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__15), +.i_y(iz__15), +.i_z(dwa__15), +//Outputs + .o_x(ir__16), +.o_y(iz__16), +.o_z(dwa__16) +); + + + + +PhotonBlock1 photon14q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__13), +.i_y(iz__13), +.i_z(dwa__13), +//Outputs + .o_x(ir__14), +.o_y(iz__14), +.o_z(dwa__14) +); +PhotonBlock1 photon13q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__12), +.i_y(iz__12), +.i_z(dwa__12), +//Outputs + .o_x(ir__13), +.o_y(iz__13), +.o_z(dwa__13) +); +PhotonBlock1 photon12q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__11), +.i_y(iz__11), +.i_z(dwa__11), +//Outputs + .o_x(ir__12), +.o_y(iz__12), +.o_z(dwa__12) +); +PhotonBlock1 photon11q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__10), +.i_y(iz__10), +.i_z(dwa__10), +//Outputs + .o_x(ir__11), +.o_y(iz__11), +.o_z(dwa__11) +); +PhotonBlock1 photon10q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__9), +.i_y(iz__9), +.i_z(dwa__9), +//Outputs + .o_x(ir__10), +.o_y(iz__10), +.o_z(dwa__10) +); +PhotonBlock1 photon9q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__8), +.i_y(iz__8), +.i_z(dwa__8), +//Outputs + .o_x(ir__9), +.o_y(iz__9), +.o_z(dwa__9) +); +PhotonBlock1 photon8q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__7), +.i_y(iz__7), +.i_z(dwa__7), +//Outputs + .o_x(ir__8), +.o_y(iz__8), +.o_z(dwa__8) +); +PhotonBlock1 photon7q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__6), +.i_y(iz__6), +.i_z(dwa__6), +//Outputs + .o_x(ir__7), +.o_y(iz__7), +.o_z(dwa__7) +); +PhotonBlock1 photon6q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__5), +.i_y(iz__5), +.i_z(dwa__5), +//Outputs + .o_x(ir__6), +.o_y(iz__6), +.o_z(dwa__6) +); + + + +PhotonBlock1 photon4q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__3), +.i_y(iz__3), +.i_z(dwa__3), +//Outputs + .o_x(ir__4), +.o_y(iz__4), +.o_z(dwa__4) +); +PhotonBlock1 photon3q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__2), +.i_y(iz__2), +.i_z(dwa__2), +//Outputs + .o_x(ir__3), +.o_y(iz__3), +.o_z(dwa__3) +); +PhotonBlock1 photon2q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__1), +.i_y(iz__1), +.i_z(dwa__1), +//Outputs + .o_x(ir__2), +.o_y(iz__2), +.o_z(dwa__2) +); +PhotonBlock1 photon1q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__0), +.i_y(iz__0), +.i_z(dwa__0), +//Outputs + .o_x(ir__1), +.o_y(iz__1), +.o_z(dwa__1) +); + + + +////////////////////////////////////////////////////////////////////////////// +//STAGE BY STAGE PIPELINE DESIGN +////////////////////////////////////////////////////////////////////////////// + +///////////////STAGE 2 - square of x and y///////////////////////// +always @(reset or x_pipe or y_pipe) begin + if (reset) begin + x2_temp=0; + y2_temp=0; + end + else begin + x2_temp=x_pipe*x_pipe; + y2_temp=y_pipe*y_pipe; + end +end + +///////////////STAGE 3 - square of r///////////////////////// +always @(reset or x2_P or y2_P) begin + if (reset) + r2_temp=0; + else + r2_temp=x2_P+y2_P; +end + +///////////////STAGE 4 - Find r and dwa///////////////////////// +//Create MUX +always@(layer_pipe or muaFraction1 or muaFraction2 or muaFraction3 or muaFraction4 or muaFraction5) + case(layer_pipe) + 1: fractionScaled=muaFraction1; + 2: fractionScaled=muaFraction2; + 3: fractionScaled=muaFraction3; + 4: fractionScaled=muaFraction4; + 5: fractionScaled=muaFraction5; + default: fractionScaled=0; //Sys Reset case + endcase + + +always @(reset or weight__4 or r_P_wire or weight_P4 or fractionScaled or product64bit or dead__4 or hit__4) begin + if (reset) begin + weight_P4=0; + r_P=0; + product64bit=0; + dwa_temp=0; + end + else begin + weight_P4=weight__4; + r_P=r_P_wire; //Connect to sqrt block + product64bit=weight_P4*fractionScaled; + + //Checking corner cases + if (dead__4==1) //Dead photon + dwa_temp=weight_P4;//drop all its weight + else if (hit__4==1) //Hit Boundary + dwa_temp=0; //Don't add to absorption array + else + dwa_temp=product64bit[63:32]; + end +end + +assign r2_P_wire=r2_P; + +Sqrt_64b squareRoot ( + .clk(clock), + .num_(r2_P_wire), + .res(r_P_wire) + ); + +///////////////STAGE 14 - Find ir and iz///////////////////////// +always @(reset or r_P or z_pipe or dead__14 or hit__14 or iz_temp or ir_temp) begin + if (reset) begin + ir_temp=0; + iz_temp=0; + end + + //Checking corner cases!!! + else begin + //ir_temp=r_P>>`RGRID_SCLAE_EXP; + //iz_temp=z_pipe>>`ZGRID_SCLAE_EXP; + if (dead__14==1) begin + ir_temp=`NR-1; + iz_temp=`NZ-1; + end + else if (hit__14==1) begin + ir_temp=0; + iz_temp=0; + end + else begin + if ((z_pipe>>`ZGRID_SCLAE_EXP) >=`NZ ) begin + iz_temp=`NZ-1; + end + else begin + iz_temp=z_pipe>>`ZGRID_SCLAE_EXP; + end + + if ((r_P>>`RGRID_SCLAE_EXP) >= `NR ) begin + ir_temp=`NR-1; + end + else begin + ir_temp=r_P>>`RGRID_SCLAE_EXP; + end + end + +// if (iz_temp>=`NZ) begin +// iz_temp=`NZ-1; +// end +// +// +// if (ir_temp>=`NR) begin +// ir_temp=`NR-1; +// end + + + end +end + +///////////////STAGE 15 - Compute MEM address///////////////////////// +always @(reset or ir__15 or iz__15 or ir_P or iz_P or ir_scaled) begin + if (reset) begin + ir_P=0; + iz_P=0; + ir_scaled=0; + rADDR_temp=0; + end + else begin + ir_P=ir__15; + iz_P=iz__15; + ir_scaled=ir_P<<`NR_EXP; + rADDR_temp=ir_scaled[15:0] + iz_P[15:0]; + end +end + +///////////////STAGE 16 - MEM read///////////////////////// +always @(reset or ir__16 or ir__17 or iz__16 or iz__17 or ir__18 or iz__18 or newAbs_P or q or newAbs_temp) begin + if (reset) begin + oldAbs_MEM=0; + end else begin + //Check Corner cases (RAW hazards) + if ((ir__16==ir__17) && (iz__16==iz__17)) begin + oldAbs_MEM=newAbs_temp; + end else if ((ir__16==ir__18) && (iz__16==iz__18)) begin + oldAbs_MEM=newAbs_P; //RAW hazard + end else begin + oldAbs_MEM=q; //Connect to REAL dual-port MEM + end + end + +end + +///////////////STAGE 17 - Update Weight///////////////////////// +//TO BE TESTED!!! +always @(reset or dwa__17 or weight__17 or weight_P or dwa_P or oldAbs_P) begin + if(reset) begin + dwa_P=0; //How to specify Base 10??? + weight_P=0; + newWeight = 0; + newAbs_temp =0; + end + else begin + dwa_P=dwa__17; + weight_P=weight__17; + newWeight=weight_P-dwa_P; + newAbs_temp=oldAbs_P+dwa_P; //Check bit width casting (64-bit<--64-bit+32-bit) + end +end + +////////////////////////////////////////////////////////////////////////////// +//STAGE BY STAGE - EXTRA REGISTERS +////////////////////////////////////////////////////////////////////////////// +always @ (posedge clock) +begin + if (reset) begin + //Stage 2 + x2_P<=0; + y2_P<=0; + + //Stage 3 + r2_P<=0; + + //Stage 15 + rADDR_16<=0; + + //Stage 16 + oldAbs_P<=0; + rADDR_17<=0; + + //Stage 17 + newAbs_P<=0; + // wADDR <=0; + end + + else if (enable) begin + //Stage 2 + x2_P<=x2_temp; //From comb logic above + y2_P<=y2_temp; + + //Stage 3 + r2_P<=r2_temp; + + //Stage 15 + rADDR_16<=rADDR_temp; + + //Stage 16 + oldAbs_P<=oldAbs_MEM; + rADDR_17<=rADDR_16; + + //Stage 17 + newAbs_P<=newAbs_temp; + // wADDR <=rADDR_17; + end +end + +////////////////////////////////////////////////////////////////////////////// +//INTERFACE to on-chip MEM +////////////////////////////////////////////////////////////////////////////// +always @ (posedge clock) +begin + if (reset) + wren <=0; + else + wren<=1; //Memory enabled every cycle after global enable +end + +assign rdaddress=rADDR_temp; +assign wraddress=rADDR_17; + +assign data=newAbs_temp; + +endmodule + + +//Photons that make up the register pipeline +module PhotonBlock1( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + + //Outputs + o_x, + o_y, + o_z + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; + + +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire [`BIT_WIDTH-1:0] i_y; +wire [`BIT_WIDTH-1:0] i_z; + +reg [`BIT_WIDTH-1:0] o_x; +reg [`BIT_WIDTH-1:0] o_y; +reg [`BIT_WIDTH-1:0] o_z; + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}} ; + o_y <= {`BIT_WIDTH{1'b0}}; + o_z <= {`BIT_WIDTH{1'b0}}; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + end +endmodule + + +//Photons that make up the register pipeline +module PhotonBlock2( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + + //Outputs + o_x, + o_y, + o_z + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input i_y; +input i_z; + + +output [`BIT_WIDTH-1:0] o_x; +output o_y; +output o_z; + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire i_y; +wire i_z; + +reg [`BIT_WIDTH-1:0] o_x; +reg o_y; +reg o_z; + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}} ; + o_y <= 1'b0; + o_z <= 1'b0; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + end +endmodule + + + + + + + + +module ScattererReflectorWrapper ( + //Inputs + clock, + reset, + enable, + //MEMORY WRAPPER + + //Inputs + + //Photon values + i_uz1_pipeWrapper, + i_hit2_pipeWrapper, + i_ux3_pipeWrapper, + i_uz3_pipeWrapper, + i_layer3_pipeWrapper, + i_hit4_pipeWrapper, + i_hit6_pipeWrapper, + i_hit16_pipeWrapper, + i_layer31_pipeWrapper, + i_uy32_pipeWrapper, + i_uz32_pipeWrapper, + i_hit33_pipeWrapper, + i_ux33_pipeWrapper, + i_uy33_pipeWrapper, + i_hit34_pipeWrapper, + i_ux35_pipeWrapper, + i_uy35_pipeWrapper, + i_uz35_pipeWrapper, + i_layer35_pipeWrapper, + i_hit36_pipeWrapper, + i_ux36_pipeWrapper, + i_uy36_pipeWrapper, + i_uz36_pipeWrapper, + i_layer36_pipeWrapper, + i_dead36_pipeWrapper, + + + //Memory Interface + //Inputs + rand2, + rand3, + rand5, + sint, + cost, + up_rFresnel, + down_rFresnel, + //Outputs + tindex, + fresIndex, + + //Constants + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + //Outputs + ux_scatterer, + uy_scatterer, + uz_scatterer, + + ux_reflector, + uy_reflector, + uz_reflector, + layer_reflector, + dead_reflector + ); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used later in the program. + +//parameter INTMAX_2 = 64'h3FFFFFFF00000001; +//The above parameter is never used in the ScattererReflectorWrapper module itself + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). + + +input clock; +input reset; +input enable; +input [2:0] i_layer31_pipeWrapper; + + + +input [31:0] i_uz1_pipeWrapper; +input i_hit2_pipeWrapper; +input [31:0] i_ux3_pipeWrapper; +input [31:0] i_uz3_pipeWrapper; +input [2:0] i_layer3_pipeWrapper; +input i_hit4_pipeWrapper; +input i_hit6_pipeWrapper; +input i_hit16_pipeWrapper; +input [31:0] i_uy32_pipeWrapper; +input [31:0] i_uz32_pipeWrapper; +input i_hit33_pipeWrapper; +input [31:0] i_ux33_pipeWrapper; +input [31:0] i_uy33_pipeWrapper; +input i_hit34_pipeWrapper; +input [31:0] i_ux35_pipeWrapper; +input [31:0] i_uy35_pipeWrapper; +input [31:0] i_uz35_pipeWrapper; +input [2:0] i_layer35_pipeWrapper; +input i_hit36_pipeWrapper; +input [31:0] i_ux36_pipeWrapper; +input [31:0] i_uy36_pipeWrapper; +input [31:0] i_uz36_pipeWrapper; +input [2:0] i_layer36_pipeWrapper; +input i_dead36_pipeWrapper; + + +//Memory Interface +input [31:0] rand2; +input [31:0] rand3; +input [31:0] rand5; +input [31:0] sint; +input [31:0] cost; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + +output [12:0] tindex; +output [9:0] fresIndex; + + +//Constants +input [31:0] down_niOverNt_1; +input [31:0] down_niOverNt_2; +input [31:0] down_niOverNt_3; +input [31:0] down_niOverNt_4; +input [31:0] down_niOverNt_5; +input [31:0] up_niOverNt_1; +input [31:0] up_niOverNt_2; +input [31:0] up_niOverNt_3; +input [31:0] up_niOverNt_4; +input [31:0] up_niOverNt_5; +input [63:0] down_niOverNt_2_1; +input [63:0] down_niOverNt_2_2; +input [63:0] down_niOverNt_2_3; +input [63:0] down_niOverNt_2_4; +input [63:0] down_niOverNt_2_5; +input [63:0] up_niOverNt_2_1; +input [63:0] up_niOverNt_2_2; +input [63:0] up_niOverNt_2_3; +input [63:0] up_niOverNt_2_4; +input [63:0] up_niOverNt_2_5; +input [31:0] downCritAngle_0; +input [31:0] downCritAngle_1; +input [31:0] downCritAngle_2; +input [31:0] downCritAngle_3; +input [31:0] downCritAngle_4; +input [31:0] upCritAngle_0; +input [31:0] upCritAngle_1; +input [31:0] upCritAngle_2; +input [31:0] upCritAngle_3; +input [31:0] upCritAngle_4; + + +output [31:0] ux_scatterer; +output [31:0] uy_scatterer; +output [31:0] uz_scatterer; +output [31:0] ux_reflector; +output [31:0] uy_reflector; +output [31:0] uz_reflector; +output [2:0] layer_reflector; +output dead_reflector; + + + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. +wire clock; +wire reset; +wire enable; + +wire [2:0] i_layer31_pipeWrapper; + +wire [31:0] i_uz1_pipeWrapper; +wire i_hit2_pipeWrapper; +wire [31:0] i_ux3_pipeWrapper; +wire [31:0] i_uz3_pipeWrapper; +wire [2:0] i_layer3_pipeWrapper; +wire i_hit4_pipeWrapper; +wire i_hit6_pipeWrapper; +wire i_hit16_pipeWrapper; +wire [31:0] i_uy32_pipeWrapper; +wire [31:0] i_uz32_pipeWrapper; +wire i_hit33_pipeWrapper; +wire [31:0] i_ux33_pipeWrapper; +wire [31:0] i_uy33_pipeWrapper; +wire i_hit34_pipeWrapper; +wire [31:0] i_ux35_pipeWrapper; +wire [31:0] i_uy35_pipeWrapper; +wire [31:0] i_uz35_pipeWrapper; +wire [2:0] i_layer35_pipeWrapper; +wire i_hit36_pipeWrapper; +wire [31:0] i_ux36_pipeWrapper; +wire [31:0] i_uy36_pipeWrapper; +wire [31:0] i_uz36_pipeWrapper; +wire [2:0] i_layer36_pipeWrapper; +wire i_dead36_pipeWrapper; + +wire [9:0] pindex; +wire [12:0] tindex; +wire [31:0] rand2; +wire [31:0] rand3; +wire [31:0] rand5; + + +//Constants +wire [31:0] down_niOverNt_1; +wire [31:0] down_niOverNt_2; +wire [31:0] down_niOverNt_3; +wire [31:0] down_niOverNt_4; +wire [31:0] down_niOverNt_5; +wire [31:0] up_niOverNt_1; +wire [31:0] up_niOverNt_2; +wire [31:0] up_niOverNt_3; +wire [31:0] up_niOverNt_4; +wire [31:0] up_niOverNt_5; +wire [63:0] down_niOverNt_2_1; +wire [63:0] down_niOverNt_2_2; +wire [63:0] down_niOverNt_2_3; +wire [63:0] down_niOverNt_2_4; +wire [63:0] down_niOverNt_2_5; +wire [63:0] up_niOverNt_2_1; +wire [63:0] up_niOverNt_2_2; +wire [63:0] up_niOverNt_2_3; +wire [63:0] up_niOverNt_2_4; +wire [63:0] up_niOverNt_2_5; +wire [31:0] downCritAngle_0; +wire [31:0] downCritAngle_1; +wire [31:0] downCritAngle_2; +wire [31:0] downCritAngle_3; +wire [31:0] downCritAngle_4; +wire [31:0] upCritAngle_0; +wire [31:0] upCritAngle_1; +wire [31:0] upCritAngle_2; +wire [31:0] upCritAngle_3; +wire [31:0] upCritAngle_4; + +//Scatterer, final calculated values +wire [31:0] ux_scatterer; +wire [31:0] uy_scatterer; +wire [31:0] uz_scatterer; +wire [31:0] ux_reflector; +wire [31:0] uy_reflector; +wire [31:0] uz_reflector; +wire [2:0] layer_reflector; +wire dead_reflector; + + +//Mathematics results signals +wire [63:0] prod1_2; +wire [63:0] prod1_4; +wire [31:0] sqrtResult1_6; +//wire [32:0] sqrtRemainder; //not necessary, not used except as dummy var in sqrt. +wire [63:0] prod1_33; +wire [63:0] prod2_33; +wire [63:0] prod3_33; +wire [63:0] prod1_34; +wire [63:0] prod2_34; +wire [63:0] prod3_34; +wire [63:0] prod4_34; +wire [63:0] quot1_16; +wire [31:0] divRemainder; +wire [63:0] prod1_36; +wire [63:0] prod2_36; +wire [63:0] prod3_36; +wire [63:0] prod4_36; +wire [63:0] prod5_36; +wire [63:0] prod6_36; + +//Scatterer Operands +wire [31:0] op1_2_1_scatterer; +wire [31:0] op1_2_2_scatterer; +wire [31:0] op1_4_1_scatterer; +wire [31:0] op1_4_2_scatterer; +wire [63:0] sqrtOperand1_6_scatterer; +wire [63:0] divNumerator1_16_scatterer; +wire [31:0] divDenominator1_16_scatterer; +wire [31:0] op1_33_1_scatterer; +wire [31:0] op1_33_2_scatterer; +wire [31:0] op2_33_1_scatterer; +wire [31:0] op2_33_2_scatterer; +wire [31:0] op3_33_1_scatterer; +wire [31:0] op3_33_2_scatterer; +wire [31:0] op1_34_1_scatterer; +wire [31:0] op1_34_2_scatterer; +wire [31:0] op2_34_1_scatterer; +wire [31:0] op2_34_2_scatterer; +wire [31:0] op3_34_1_scatterer; +wire [31:0] op3_34_2_scatterer; +wire [31:0] op4_34_1_scatterer; +wire [31:0] op4_34_2_scatterer; +wire [31:0] op1_36_1_scatterer; +wire [31:0] op1_36_2_scatterer; +wire [31:0] op2_36_1_scatterer; +wire [31:0] op2_36_2_scatterer; +wire [31:0] op3_36_1_scatterer; +wire [31:0] op3_36_2_scatterer; +wire [31:0] op4_36_1_scatterer; +wire [31:0] op4_36_2_scatterer; +wire [31:0] op5_36_1_scatterer; +wire [31:0] op5_36_2_scatterer; +wire [31:0] op6_36_1_scatterer; +wire [31:0] op6_36_2_scatterer; + + +//Reflector Operands +wire [31:0] op1_2_1_reflector; +wire [31:0] op1_2_2_reflector; +wire [31:0] op1_4_1_reflector; +wire [31:0] op1_4_2_reflector; +wire [63:0] sqrtOperand1_6_reflector; +wire [31:0] op1_36_1_reflector; +wire [31:0] op1_36_2_reflector; +wire [31:0] op2_36_1_reflector; +wire [31:0] op2_36_2_reflector; + + + + +//Operands entering the multipliers, divider, and sqrt +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +wire [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [63:0] divNumerator1_16; +wire [31:0] divDenominator1_16; +wire [31:0] op1_33_1; +wire [31:0] op1_33_2; +wire [31:0] op2_33_1; +wire [31:0] op2_33_2; +wire [31:0] op3_33_1; +wire [31:0] op3_33_2; +wire [31:0] op1_34_1; +wire [31:0] op1_34_2; +wire [31:0] op2_34_1; +wire [31:0] op2_34_2; +wire [31:0] op3_34_1; +wire [31:0] op3_34_2; +wire [31:0] op4_34_1; +wire [31:0] op4_34_2; +wire [31:0] op1_36_1; +wire [31:0] op1_36_2; +wire [31:0] op2_36_1; +wire [31:0] op2_36_2; +wire [31:0] op3_36_1; +wire [31:0] op3_36_2; +wire [31:0] op4_36_1; +wire [31:0] op4_36_2; +wire [31:0] op5_36_1; +wire [31:0] op5_36_2; +wire [31:0] op6_36_1; +wire [31:0] op6_36_2; + + +reg [2:0] layerMinusOne; + +wire [31:0] sint; +wire [31:0] cost; +wire [31:0] sinp; +wire [31:0] cosp; + +wire [31:0] up_rFresnel; +wire [31:0] down_rFresnel; +wire [9:0] fresIndex; + + + +//Need this to deal with 'unused' inputs for ODIN II +wire bigOr; +assign bigOr = i_hit16_pipeWrapper|i_hit33_pipeWrapper|i_hit34_pipeWrapper| + rand2[31]|rand2[30]|rand2[29]|rand2[28]|rand2[27]|rand2[26]| + rand2[25]|rand2[24]|rand2[23]|rand2[22]|rand2[21]|rand2[20]| + rand2[19]|rand2[18]|rand2[17]|rand2[16]|rand2[15]|rand2[14]| + rand2[13]|rand2[12]|rand2[11]|rand2[10]| + rand3[31]|rand3[30]|rand3[29]|rand3[28]|rand3[27]|rand3[26]| + rand3[25]|rand3[24]|rand3[23]|rand3[22]|rand3[21]|rand3[20]| + rand3[19]|rand3[18]|rand3[17]|rand3[16]|rand3[15]|rand3[14]| + rand3[13]|rand3[12]|rand3[11]|rand3[10]| + rand5[31]|(1'b1); +wire reset_new; +assign reset_new = reset & bigOr; + + +//MUX for sending in indices for memory. +always @ (i_layer31_pipeWrapper) begin + case (i_layer31_pipeWrapper) + 3'b001: layerMinusOne = 0; + 3'b010: layerMinusOne = 1; + 3'b011: layerMinusOne = 2; + 3'b100: layerMinusOne = 3; + 3'b101: layerMinusOne = 4; + default: layerMinusOne = 0; + endcase +end + +assign tindex = {layerMinusOne, rand2[9:0]}; +assign pindex = rand3[9:0]; + + +//Arbitrarily decide on values of sine and cosine for now, should be memory lookups +Memory_Wrapper memories( + //INPUTS + .clock(clock), + //.reset(reset), //Unused. ODIN II complained. + .pindex(pindex), + //OUTPUTS + .sinp(sinp), + .cosp(cosp) + ); + + +Scatterer scatterer_0 ( + .clock(clock), + .reset(reset_new), //so pins are used + .enable(enable), + //Photon values + .i_uz1(i_uz1_pipeWrapper), + .i_ux3(i_ux3_pipeWrapper), + .i_uz3(i_uz3_pipeWrapper), + .i_uy32(i_uy32_pipeWrapper), + .i_uz32(i_uz32_pipeWrapper), + .i_ux33(i_ux33_pipeWrapper), + .i_uy33(i_uy33_pipeWrapper), + .i_ux35(i_ux35_pipeWrapper), + .i_uy35(i_uy35_pipeWrapper), + .i_uz35(i_uz35_pipeWrapper), + .i_uz36(i_uz36_pipeWrapper), + //Mathematics Results + .prod1_2(prod1_2), + .prod1_4({prod1_4[63:63], prod1_4[61:31]}), + .sqrtResult1_6(sqrtResult1_6), + .prod1_33({prod1_33[63:63], prod1_33[61:31]}), + .prod2_33({prod2_33[63:63], prod2_33[61:31]}), + .prod3_33({prod3_33[63:63], prod3_33[61:31]}), + .prod1_34({prod1_34[63:63], prod1_34[61:31]}), + .prod2_34({prod2_34[63:63], prod2_34[61:31]}), + .prod3_34({prod3_34[63:63], prod3_34[61:31]}), + .prod4_34({prod4_34[63:63], prod4_34[61:31]}), + .quot1_16(quot1_16[63:0]), + .prod1_36(prod1_36[63:0]), + .prod2_36(prod2_36[63:0]), + .prod3_36({prod3_36[63:63], prod3_36[61:31]}), + .prod4_36({prod4_36[63:63], prod4_36[61:31]}), + .prod5_36({prod5_36[63:63], prod5_36[61:31]}), + .prod6_36({prod6_36[63:63], prod6_36[61:31]}), + //Trig from Memory + .sint_Mem(sint), + .cost_Mem(cost), + .sinp_Mem(sinp), + .cosp_Mem(cosp), + //Operands for mathematics + .op1_2_1(op1_2_1_scatterer), + .op1_2_2(op1_2_2_scatterer), + .op1_4_1(op1_4_1_scatterer), + .op1_4_2(op1_4_2_scatterer), + .sqrtOperand1_6(sqrtOperand1_6_scatterer), + .divNumerator1_16(divNumerator1_16_scatterer), + .divDenominator1_16(divDenominator1_16_scatterer), + .op1_33_1(op1_33_1_scatterer), + .op1_33_2(op1_33_2_scatterer), + .op2_33_1(op2_33_1_scatterer), + .op2_33_2(op2_33_2_scatterer), + .op3_33_1(op3_33_1_scatterer), + .op3_33_2(op3_33_2_scatterer), + .op1_34_1(op1_34_1_scatterer), + .op1_34_2(op1_34_2_scatterer), + .op2_34_1(op2_34_1_scatterer), + .op2_34_2(op2_34_2_scatterer), + .op3_34_1(op3_34_1_scatterer), + .op3_34_2(op3_34_2_scatterer), + .op4_34_1(op4_34_1_scatterer), + .op4_34_2(op4_34_2_scatterer), + .op1_36_1(op1_36_1_scatterer), + .op1_36_2(op1_36_2_scatterer), + .op2_36_1(op2_36_1_scatterer), + .op2_36_2(op2_36_2_scatterer), + .op3_36_1(op3_36_1_scatterer), + .op3_36_2(op3_36_2_scatterer), + .op4_36_1(op4_36_1_scatterer), + .op4_36_2(op4_36_2_scatterer), + .op5_36_1(op5_36_1_scatterer), + .op5_36_2(op5_36_2_scatterer), + .op6_36_1(op6_36_1_scatterer), + .op6_36_2(op6_36_2_scatterer), + + //Final calculated values + .ux_scatterer(ux_scatterer), + .uy_scatterer(uy_scatterer), + .uz_scatterer(uz_scatterer) + + ); + +Reflector reflector_0 ( + + //INPUTS + .clock(clock), + .reset(reset), + .enable(enable), + //Photon values + .i_uz1(i_uz1_pipeWrapper), + .i_uz3(i_uz3_pipeWrapper), + .i_layer3(i_layer3_pipeWrapper), + .i_ux35(i_ux35_pipeWrapper), + .i_uy35(i_uy35_pipeWrapper), + .i_uz35(i_uz35_pipeWrapper), + .i_layer35(i_layer35_pipeWrapper), + .i_ux36(i_ux36_pipeWrapper), + .i_uy36(i_uy36_pipeWrapper), + .i_uz36(i_uz36_pipeWrapper), + .i_layer36(i_layer36_pipeWrapper), + .i_dead36(i_dead36_pipeWrapper), + + //Constants + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + //Fresnels inputs + .rnd({1'b0, rand5[30:0]}), + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + + //Mathematics Results + .prod1_2(prod1_2), + .prod1_4(prod1_4), + .sqrtResult1_6(sqrtResult1_6), + .prod1_36(prod1_36), + .prod2_36(prod2_36), + + //OUTPUTS + + //Fresnels outputs + .fresIndex(fresIndex), + + //Mathematics Operands + .op1_2_1(op1_2_1_reflector), + .op1_2_2(op1_2_2_reflector), + .op1_4_1(op1_4_1_reflector), + .op1_4_2(op1_4_2_reflector), + .sqrtOperand1_6(sqrtOperand1_6_reflector), + .op1_36_1(op1_36_1_reflector), + .op1_36_2(op1_36_2_reflector), + .op2_36_1(op2_36_1_reflector), + .op2_36_2(op2_36_2_reflector), + + + //Final Calculated Results + .ux_reflector(ux_reflector), + .uy_reflector(uy_reflector), + .uz_reflector(uz_reflector), + .layer_reflector(layer_reflector), + .dead_reflector(dead_reflector) + +); + + + + + +//Multipliers, Dividers, and Sqrts for Scatterer & Reflector + +assign op1_2_1 = (i_hit2_pipeWrapper == 1'b1) ? op1_2_1_reflector : op1_2_1_scatterer; +assign op1_2_2 = (i_hit2_pipeWrapper == 1'b1) ? op1_2_2_reflector : op1_2_2_scatterer; + +Mult_32b multiplier1_2 ( + .dataa(op1_2_1), + .datab(op1_2_2), + .result(prod1_2) + ); + +assign op1_4_1 = (i_hit4_pipeWrapper == 1'b1) ? op1_4_1_reflector : op1_4_1_scatterer; +assign op1_4_2 = (i_hit4_pipeWrapper == 1'b1) ? op1_4_2_reflector : op1_4_2_scatterer; + +Mult_32b multiplier1_4 ( + .dataa(op1_4_1), + .datab(op1_4_2), + .result(prod1_4) + ); + + + +Mult_32b multiplier1_33 ( + .dataa(op1_33_1_scatterer), + .datab(op1_33_2_scatterer), + .result(prod1_33) + ); + +Mult_32b multiplier2_33 ( + .dataa(op2_33_1_scatterer), + .datab(op2_33_2_scatterer), + .result(prod2_33) + ); + +Mult_32b multiplier3_33 ( + .dataa(op3_33_1_scatterer), + .datab(op3_33_2_scatterer), + .result(prod3_33) + ); + + +Mult_32b multiplier1_34 ( + .dataa(op1_34_1_scatterer), + .datab(op1_34_2_scatterer), + .result(prod1_34) + ); + + +Mult_32b multiplier2_34 ( + .dataa(op2_34_1_scatterer), + .datab(op2_34_2_scatterer), + .result(prod2_34) + ); + + +Mult_32b multiplier3_34 ( + .dataa(op3_34_1_scatterer), + .datab(op3_34_2_scatterer), + .result(prod3_34) + ); + +Mult_32b multiplier4_34 ( + .dataa(op4_34_1_scatterer), + .datab(op4_34_2_scatterer), + .result(prod4_34) + ); + +assign op1_36_1 = (i_hit36_pipeWrapper == 1'b1) ? op1_36_1_reflector : op1_36_1_scatterer; +assign op1_36_2 = (i_hit36_pipeWrapper == 1'b1) ? op1_36_2_reflector : op1_36_2_scatterer; + +Mult_32b multiplier1_36 ( + .dataa(op1_36_1), + .datab(op1_36_2), + .result(prod1_36) + ); + +assign op2_36_1 = (i_hit36_pipeWrapper == 1'b1) ? op2_36_1_reflector : op2_36_1_scatterer; +assign op2_36_2 = (i_hit36_pipeWrapper == 1'b1) ? op2_36_2_reflector : op2_36_2_scatterer; + +Mult_32b multiplier2_36 ( + .dataa(op2_36_1), + .datab(op2_36_2), + .result(prod2_36) + ); + +Mult_32b multiplier3_36 ( + .dataa(op3_36_1_scatterer), + .datab(op3_36_2_scatterer), + .result(prod3_36) + ); + + +Mult_32b multiplier4_36 ( + .dataa(op4_36_1_scatterer), + .datab(op4_36_2_scatterer), + .result(prod4_36) + ); + + +Mult_32b multiplier5_36 ( + .dataa(op5_36_1_scatterer), + .datab(op5_36_2_scatterer), + .result(prod5_36) + ); + + +Mult_32b multiplier6_36 ( + .dataa(op6_36_1_scatterer), + .datab(op6_36_2_scatterer), + .result(prod6_36) + ); + +assign sqrtOperand1_6 = (i_hit6_pipeWrapper == 1'b1) ? sqrtOperand1_6_reflector : sqrtOperand1_6_scatterer; + +Sqrt_64b squareRoot1_6 ( + .clk(clock), + .num_(sqrtOperand1_6), + .res(sqrtResult1_6) + ); + + + +Div_64b divide1_16 ( + .clock(clock), + .denom(divDenominator1_16_scatterer), + .numer(divNumerator1_16_scatterer), + .quotient(quot1_16), + .remain(divRemainder) + ); + + +endmodule + + + + +module InternalsBlock_Reflector( + //Inputs + clock, + reset, + enable, + + i_uz_2, //uz^2 + i_uz2, //new uz, should the photon transmit to new layer + i_oneMinusUz_2, //(1-uz)^2 + i_sa2_2, //(sine of angle 2)^2 (uz2 = cosine of angle 2). + i_uz2_2, //(uz2)^2, new uz squared. + i_ux_transmitted, //new value for ux, if the photon transmits to the next layer + i_uy_transmitted, //new value for uy, if the photon transmits to the next layer + + //Outputs + o_uz_2, + o_uz2, + o_oneMinusUz_2, + o_sa2_2, + o_uz2_2, + o_ux_transmitted, + o_uy_transmitted + ); + +input clock; +input reset; +input enable; + +input [63:0] i_uz_2; +input [31:0] i_uz2; +input [63:0] i_oneMinusUz_2; +input [63:0] i_sa2_2; +input [63:0] i_uz2_2; +input [31:0] i_ux_transmitted; +input [31:0] i_uy_transmitted; + +output [63:0] o_uz_2; +output [31:0] o_uz2; +output [63:0] o_oneMinusUz_2; +output [63:0] o_sa2_2; +output [63:0] o_uz2_2; +output [31:0] o_ux_transmitted; +output [31:0] o_uy_transmitted; + + +wire clock; +wire reset; +wire enable; + +wire [63:0] i_uz_2; +wire [31:0] i_uz2; +wire [63:0] i_oneMinusUz_2; +wire [63:0] i_sa2_2; +wire [63:0] i_uz2_2; +wire [31:0] i_ux_transmitted; +wire [31:0] i_uy_transmitted; + + +reg [63:0] o_uz_2; +reg [31:0] o_uz2; +reg [63:0] o_oneMinusUz_2; +reg [63:0] o_sa2_2; +reg [63:0] o_uz2_2; +reg [31:0] o_ux_transmitted; +reg [31:0] o_uy_transmitted; + + + +always @ (posedge clock) + if(reset) begin + o_uz_2 <= 64'h3FFFFFFFFFFFFFFF; + o_uz2 <= 32'h7FFFFFFF; + o_oneMinusUz_2 <= 64'h0000000000000000; + o_sa2_2 <= 64'h0000000000000000; + o_uz2_2 <= 64'h3FFFFFFFFFFFFFFF; + o_ux_transmitted <= 32'h00000000; + o_uy_transmitted <= 32'h00000000; + end else if(enable) begin + o_uz_2 <= i_uz_2; + o_uz2 <= i_uz2; + o_oneMinusUz_2 <= i_oneMinusUz_2; + o_sa2_2 <= i_sa2_2; + o_uz2_2 <= i_uz2_2; + o_ux_transmitted <= i_ux_transmitted; + o_uy_transmitted <= i_uy_transmitted; + end +endmodule + + +module Reflector ( + + //INPUTS + clock, + reset, + enable, + //Values from Photon Pipeline + i_uz1, + i_uz3, + i_layer3, + i_ux35, + i_uy35, + i_uz35, + i_layer35, + i_ux36, + i_uy36, + i_uz36, + i_layer36, + i_dead36, + + //Constants + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + //Fresnels inputs + rnd, + up_rFresnel, + down_rFresnel, + + //Mathematics Results + prod1_2, + prod1_4, + sqrtResult1_6, + prod1_36, + prod2_36, + + + //OUTPUTS + + //Fresnels outputs + fresIndex, + + //Mathematics Operands + op1_2_1, + op1_2_2, + op1_4_1, + op1_4_2, + sqrtOperand1_6, + op1_36_1, + op1_36_2, + op2_36_1, + op2_36_2, + + + //Final Calcu`LATed Results + ux_reflector, + uy_reflector, + uz_reflector, + layer_reflector, + dead_reflector +); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used `LATer in the program. + +//parameter `DIV = 20; +//parameter `SQRT = 10; +//parameter `LAT = `DIV + `SQRT + 7; +//parameter `INTMAX_2 = 64'h3FFFFFFFFFFFFFFF; +//parameter `INTMAX = 2147483647; +//parameter `INTMIN = -2147483647; + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). +input clock; +input reset; +input enable; + +//Values from Photon Pipeline +input [31:0] i_uz1; +input [31:0] i_uz3; +input [2:0] i_layer3; +input [31:0] i_ux35; +input [31:0] i_uy35; +input [31:0] i_uz35; +input [2:0] i_layer35; +input [31:0] i_ux36; +input [31:0] i_uy36; +input [31:0] i_uz36; +input [2:0] i_layer36; +input i_dead36; + +//Constants +input [31:0] down_niOverNt_1; +input [31:0] down_niOverNt_2; +input [31:0] down_niOverNt_3; +input [31:0] down_niOverNt_4; +input [31:0] down_niOverNt_5; +input [31:0] up_niOverNt_1; +input [31:0] up_niOverNt_2; +input [31:0] up_niOverNt_3; +input [31:0] up_niOverNt_4; +input [31:0] up_niOverNt_5; +input [63:0] down_niOverNt_2_1; +input [63:0] down_niOverNt_2_2; +input [63:0] down_niOverNt_2_3; +input [63:0] down_niOverNt_2_4; +input [63:0] down_niOverNt_2_5; +input [63:0] up_niOverNt_2_1; +input [63:0] up_niOverNt_2_2; +input [63:0] up_niOverNt_2_3; +input [63:0] up_niOverNt_2_4; +input [63:0] up_niOverNt_2_5; +input [31:0] downCritAngle_0; +input [31:0] downCritAngle_1; +input [31:0] downCritAngle_2; +input [31:0] downCritAngle_3; +input [31:0] downCritAngle_4; +input [31:0] upCritAngle_0; +input [31:0] upCritAngle_1; +input [31:0] upCritAngle_2; +input [31:0] upCritAngle_3; +input [31:0] upCritAngle_4; + +//Fresnels inputs +input [31:0] rnd; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + +//Mathematics Results +input [63:0] prod1_2; +input [63:0] prod1_4; +input [31:0] sqrtResult1_6; +input [63:0] prod1_36; +input [63:0] prod2_36; + +//OUTPUTS + +//Fresnels outputs +output [9:0] fresIndex; + +//Mathematics operands +output [31:0] op1_2_1; +output [31:0] op1_2_2; +output [31:0] op1_4_1; +output [31:0] op1_4_2; +output [63:0] sqrtOperand1_6; +output [31:0] op1_36_1; +output [31:0] op1_36_2; +output [31:0] op2_36_1; +output [31:0] op2_36_2; + + +//Final Calcu`LATed Results +output [31:0] ux_reflector; +output [31:0] uy_reflector; +output [31:0] uz_reflector; +output [2:0] layer_reflector; +output dead_reflector; + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. + +wire clock; +wire reset; +wire enable; +//Values from Photon Pipeline +wire [31:0] i_uz1; +wire [31:0] i_uz3; +wire [2:0] i_layer3; +wire [31:0] i_ux35; +wire [31:0] i_uy35; +wire [31:0] i_uz35; +wire [2:0] i_layer35; +wire [31:0] i_ux36; +wire [31:0] i_uy36; +wire [31:0] i_uz36; +wire [2:0] i_layer36; +wire i_dead36; + +//Constants +wire [31:0] down_niOverNt_1; +wire [31:0] down_niOverNt_2; +wire [31:0] down_niOverNt_3; +wire [31:0] down_niOverNt_4; +wire [31:0] down_niOverNt_5; +wire [31:0] up_niOverNt_1; +wire [31:0] up_niOverNt_2; +wire [31:0] up_niOverNt_3; +wire [31:0] up_niOverNt_4; +wire [31:0] up_niOverNt_5; +wire [63:0] down_niOverNt_2_1; +wire [63:0] down_niOverNt_2_2; +wire [63:0] down_niOverNt_2_3; +wire [63:0] down_niOverNt_2_4; +wire [63:0] down_niOverNt_2_5; +wire [63:0] up_niOverNt_2_1; +wire [63:0] up_niOverNt_2_2; +wire [63:0] up_niOverNt_2_3; +wire [63:0] up_niOverNt_2_4; +wire [63:0] up_niOverNt_2_5; +wire [31:0] downCritAngle_0; +wire [31:0] downCritAngle_1; +wire [31:0] downCritAngle_2; +wire [31:0] downCritAngle_3; +wire [31:0] downCritAngle_4; +wire [31:0] upCritAngle_0; +wire [31:0] upCritAngle_1; +wire [31:0] upCritAngle_2; +wire [31:0] upCritAngle_3; +wire [31:0] upCritAngle_4; + +//Fresnels inputs +wire [31:0] rnd; +wire [31:0] up_rFresnel; +wire [31:0] down_rFresnel; + +//Mathematics Results +wire [63:0] prod1_2; +wire [63:0] prod1_4; +wire [31:0] sqrtResult1_6; +wire [63:0] prod1_36; +wire [63:0] prod2_36; + +//OUTPUTS + + +//Fresnels outputs +reg [9:0] fresIndex; + +//Operands for shared resources +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +reg [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [31:0] op1_36_1; +reg [31:0] op1_36_2; +wire [31:0] op2_36_1; +reg [31:0] op2_36_2; + +//Final Calcu`LATed Results +reg [31:0] ux_reflector; +reg [31:0] uy_reflector; +reg [31:0] uz_reflector; +reg [2:0] layer_reflector; +reg dead_reflector; + + +//Need this to deal with 'unused' inputs for ODIN II +wire [63:0]bigOr; +assign bigOr = i_uz3|down_niOverNt_2_1|down_niOverNt_2_2|down_niOverNt_2_3|down_niOverNt_2_3|down_niOverNt_2_4|down_niOverNt_2_5|up_niOverNt_2_1|up_niOverNt_2_2|up_niOverNt_2_3|up_niOverNt_2_3|up_niOverNt_2_4|up_niOverNt_2_5|prod1_36|prod2_36|({32'hFFFFFFFF,32'hFFFFFFFF}); +wire reset_new; +assign reset_new = reset & bigOr[63] & bigOr[62] & bigOr[61] & bigOr[60] & bigOr[59] & bigOr[58] & bigOr[57] & bigOr[56] & bigOr[55] & bigOr[54] & bigOr[53] & bigOr[52] & bigOr[51] & bigOr[50] & bigOr[49] & bigOr[48] & bigOr[47] & bigOr[46] & bigOr[45] & bigOr[44] & bigOr[43] & bigOr[42] & bigOr[41] & bigOr[40] & bigOr[39] & bigOr[38] & bigOr[37] & bigOr[36] & bigOr[35] & bigOr[34] & bigOr[33] & bigOr[32] & bigOr[31] & bigOr[30] & bigOr[29] & bigOr[28] & bigOr[27] & bigOr[26] & bigOr[25] & bigOr[24] & bigOr[23] & bigOr[22] & bigOr[21] & bigOr[20] & bigOr[19] & bigOr[18] & bigOr[17] & bigOr[16] & bigOr[15] & bigOr[14] & bigOr[13] & bigOr[12] & bigOr[11] & bigOr[10] & bigOr[9] & bigOr[8] & bigOr[7] & bigOr[6] & bigOr[5] & bigOr[4] & bigOr[3] & bigOr[2] & bigOr[1] & bigOr[0]; + + + +//-----------------------------END Pin Types------------------------- + +//Overflow Wiring +wire overflow1_4; +wire toAnd1_36_1; +wire toAnd1_36_2; +wire overflow1_36; +wire negOverflow1_36; +wire toAnd2_36_1; +wire toAnd2_36_2; +wire overflow2_36; +wire negOverflow2_36; + +//Wiring for calcu`LATing final Results +reg [31:0] new_ux; +reg [31:0] new_uy; +reg [31:0] new_uz; +reg [2:0] new_layer; +reg new_dead; +reg [31:0] downCritAngle; +reg [31:0] upCritAngle; +reg [31:0] negUz; + + + +//Wires to Connect to Internal Registers +//wire [63:0] uz_2[`LAT:0]; +//wire [31:0] uz2[`LAT:0]; +//wire [63:0] oneMinusUz_2[`LAT:0]; +//wire [63:0] sa2_2[`LAT:0]; +//wire [63:0] uz2_2[`LAT:0]; +//wire [31:0] ux_transmitted[`LAT:0]; +//wire [31:0] uy_transmitted[`LAT:0]; + +wire [63:0] uz_2__0; +wire [63:0] uz_2__1; +wire [63:0] uz_2__2; +wire [63:0] uz_2__3; +wire [63:0] uz_2__4; +wire [63:0] uz_2__5; +wire [63:0] uz_2__6; +wire [63:0] uz_2__7; +wire [63:0] uz_2__8; +wire [63:0] uz_2__9; +wire [63:0] uz_2__10; +wire [63:0] uz_2__11; +wire [63:0] uz_2__12; +wire [63:0] uz_2__13; +wire [63:0] uz_2__14; +wire [63:0] uz_2__15; +wire [63:0] uz_2__16; +wire [63:0] uz_2__17; +wire [63:0] uz_2__18; +wire [63:0] uz_2__19; +wire [63:0] uz_2__20; +wire [63:0] uz_2__21; +wire [63:0] uz_2__22; +wire [63:0] uz_2__23; +wire [63:0] uz_2__24; +wire [63:0] uz_2__25; +wire [63:0] uz_2__26; +wire [63:0] uz_2__27; +wire [63:0] uz_2__28; +wire [63:0] uz_2__29; +wire [63:0] uz_2__30; +wire [63:0] uz_2__31; +wire [63:0] uz_2__32; +wire [63:0] uz_2__33; +wire [63:0] uz_2__34; +wire [63:0] uz_2__35; +wire [63:0] uz_2__36; +wire [63:0] uz_2__37; + + + +//wire [31:0] uz2[37:0]; +wire [32-1:0] uz2__0; +wire [32-1:0] uz2__1; +wire [32-1:0] uz2__2; +wire [32-1:0] uz2__3; +wire [32-1:0] uz2__4; +wire [32-1:0] uz2__5; +wire [32-1:0] uz2__6; +wire [32-1:0] uz2__7; +wire [32-1:0] uz2__8; +wire [32-1:0] uz2__9; +wire [32-1:0] uz2__10; +wire [32-1:0] uz2__11; +wire [32-1:0] uz2__12; +wire [32-1:0] uz2__13; +wire [32-1:0] uz2__14; +wire [32-1:0] uz2__15; +wire [32-1:0] uz2__16; +wire [32-1:0] uz2__17; +wire [32-1:0] uz2__18; +wire [32-1:0] uz2__19; +wire [32-1:0] uz2__20; +wire [32-1:0] uz2__21; +wire [32-1:0] uz2__22; +wire [32-1:0] uz2__23; +wire [32-1:0] uz2__24; +wire [32-1:0] uz2__25; +wire [32-1:0] uz2__26; +wire [32-1:0] uz2__27; +wire [32-1:0] uz2__28; +wire [32-1:0] uz2__29; +wire [32-1:0] uz2__30; +wire [32-1:0] uz2__31; +wire [32-1:0] uz2__32; +wire [32-1:0] uz2__33; +wire [32-1:0] uz2__34; +wire [32-1:0] uz2__35; +wire [32-1:0] uz2__36; +wire [32-1:0] uz2__37; + + +//wire [63:0] oneMinusUz_2[37:0]; + +wire [63:0] oneMinusUz_2__0; +wire [63:0] oneMinusUz_2__1; +wire [63:0] oneMinusUz_2__2; +wire [63:0] oneMinusUz_2__3; +wire [63:0] oneMinusUz_2__4; +wire [63:0] oneMinusUz_2__5; +wire [63:0] oneMinusUz_2__6; +wire [63:0] oneMinusUz_2__7; +wire [63:0] oneMinusUz_2__8; +wire [63:0] oneMinusUz_2__9; +wire [63:0] oneMinusUz_2__10; +wire [63:0] oneMinusUz_2__11; +wire [63:0] oneMinusUz_2__12; +wire [63:0] oneMinusUz_2__13; +wire [63:0] oneMinusUz_2__14; +wire [63:0] oneMinusUz_2__15; +wire [63:0] oneMinusUz_2__16; +wire [63:0] oneMinusUz_2__17; +wire [63:0] oneMinusUz_2__18; +wire [63:0] oneMinusUz_2__19; +wire [63:0] oneMinusUz_2__20; +wire [63:0] oneMinusUz_2__21; +wire [63:0] oneMinusUz_2__22; +wire [63:0] oneMinusUz_2__23; +wire [63:0] oneMinusUz_2__24; +wire [63:0] oneMinusUz_2__25; +wire [63:0] oneMinusUz_2__26; +wire [63:0] oneMinusUz_2__27; +wire [63:0] oneMinusUz_2__28; +wire [63:0] oneMinusUz_2__29; +wire [63:0] oneMinusUz_2__30; +wire [63:0] oneMinusUz_2__31; +wire [63:0] oneMinusUz_2__32; +wire [63:0] oneMinusUz_2__33; +wire [63:0] oneMinusUz_2__34; +wire [63:0] oneMinusUz_2__35; +wire [63:0] oneMinusUz_2__36; +wire [63:0] oneMinusUz_2__37; + + +//wire [63:0] sa2_2[37:0]; +wire [63:0] sa2_2__0; +wire [63:0] sa2_2__1; +wire [63:0] sa2_2__2; +wire [63:0] sa2_2__3; +wire [63:0] sa2_2__4; +wire [63:0] sa2_2__5; +wire [63:0] sa2_2__6; +wire [63:0] sa2_2__7; +wire [63:0] sa2_2__8; +wire [63:0] sa2_2__9; +wire [63:0] sa2_2__10; +wire [63:0] sa2_2__11; +wire [63:0] sa2_2__12; +wire [63:0] sa2_2__13; +wire [63:0] sa2_2__14; +wire [63:0] sa2_2__15; +wire [63:0] sa2_2__16; +wire [63:0] sa2_2__17; +wire [63:0] sa2_2__18; +wire [63:0] sa2_2__19; +wire [63:0] sa2_2__20; +wire [63:0] sa2_2__21; +wire [63:0] sa2_2__22; +wire [63:0] sa2_2__23; +wire [63:0] sa2_2__24; +wire [63:0] sa2_2__25; +wire [63:0] sa2_2__26; +wire [63:0] sa2_2__27; +wire [63:0] sa2_2__28; +wire [63:0] sa2_2__29; +wire [63:0] sa2_2__30; +wire [63:0] sa2_2__31; +wire [63:0] sa2_2__32; +wire [63:0] sa2_2__33; +wire [63:0] sa2_2__34; +wire [63:0] sa2_2__35; +wire [63:0] sa2_2__36; +wire [63:0] sa2_2__37; + + +//wire [63:0] uz2_2[37:0]; + +wire [63:0] uz2_2__0; +wire [63:0] uz2_2__1; +wire [63:0] uz2_2__2; +wire [63:0] uz2_2__3; +wire [63:0] uz2_2__4; +wire [63:0] uz2_2__5; +wire [63:0] uz2_2__6; +wire [63:0] uz2_2__7; +wire [63:0] uz2_2__8; +wire [63:0] uz2_2__9; +wire [63:0] uz2_2__10; +wire [63:0] uz2_2__11; +wire [63:0] uz2_2__12; +wire [63:0] uz2_2__13; +wire [63:0] uz2_2__14; +wire [63:0] uz2_2__15; +wire [63:0] uz2_2__16; +wire [63:0] uz2_2__17; +wire [63:0] uz2_2__18; +wire [63:0] uz2_2__19; +wire [63:0] uz2_2__20; +wire [63:0] uz2_2__21; +wire [63:0] uz2_2__22; +wire [63:0] uz2_2__23; +wire [63:0] uz2_2__24; +wire [63:0] uz2_2__25; +wire [63:0] uz2_2__26; +wire [63:0] uz2_2__27; +wire [63:0] uz2_2__28; +wire [63:0] uz2_2__29; +wire [63:0] uz2_2__30; +wire [63:0] uz2_2__31; +wire [63:0] uz2_2__32; +wire [63:0] uz2_2__33; +wire [63:0] uz2_2__34; +wire [63:0] uz2_2__35; +wire [63:0] uz2_2__36; +wire [63:0] uz2_2__37; + +//wire [31:0] ux_transmitted[37:0]; + +wire [32-1:0] ux_transmitted__0; +wire [32-1:0] ux_transmitted__1; +wire [32-1:0] ux_transmitted__2; +wire [32-1:0] ux_transmitted__3; +wire [32-1:0] ux_transmitted__4; +wire [32-1:0] ux_transmitted__5; +wire [32-1:0] ux_transmitted__6; +wire [32-1:0] ux_transmitted__7; +wire [32-1:0] ux_transmitted__8; +wire [32-1:0] ux_transmitted__9; +wire [32-1:0] ux_transmitted__10; +wire [32-1:0] ux_transmitted__11; +wire [32-1:0] ux_transmitted__12; +wire [32-1:0] ux_transmitted__13; +wire [32-1:0] ux_transmitted__14; +wire [32-1:0] ux_transmitted__15; +wire [32-1:0] ux_transmitted__16; +wire [32-1:0] ux_transmitted__17; +wire [32-1:0] ux_transmitted__18; +wire [32-1:0] ux_transmitted__19; +wire [32-1:0] ux_transmitted__20; +wire [32-1:0] ux_transmitted__21; +wire [32-1:0] ux_transmitted__22; +wire [32-1:0] ux_transmitted__23; +wire [32-1:0] ux_transmitted__24; +wire [32-1:0] ux_transmitted__25; +wire [32-1:0] ux_transmitted__26; +wire [32-1:0] ux_transmitted__27; +wire [32-1:0] ux_transmitted__28; +wire [32-1:0] ux_transmitted__29; +wire [32-1:0] ux_transmitted__30; +wire [32-1:0] ux_transmitted__31; +wire [32-1:0] ux_transmitted__32; +wire [32-1:0] ux_transmitted__33; +wire [32-1:0] ux_transmitted__34; +wire [32-1:0] ux_transmitted__35; +wire [32-1:0] ux_transmitted__36; +wire [32-1:0] ux_transmitted__37; + +//wire [31:0] uy_transmitted[37:0]; + +wire [32-1:0] uy_transmitted__0; +wire [32-1:0] uy_transmitted__1; +wire [32-1:0] uy_transmitted__2; +wire [32-1:0] uy_transmitted__3; +wire [32-1:0] uy_transmitted__4; +wire [32-1:0] uy_transmitted__5; +wire [32-1:0] uy_transmitted__6; +wire [32-1:0] uy_transmitted__7; +wire [32-1:0] uy_transmitted__8; +wire [32-1:0] uy_transmitted__9; +wire [32-1:0] uy_transmitted__10; +wire [32-1:0] uy_transmitted__11; +wire [32-1:0] uy_transmitted__12; +wire [32-1:0] uy_transmitted__13; +wire [32-1:0] uy_transmitted__14; +wire [32-1:0] uy_transmitted__15; +wire [32-1:0] uy_transmitted__16; +wire [32-1:0] uy_transmitted__17; +wire [32-1:0] uy_transmitted__18; +wire [32-1:0] uy_transmitted__19; +wire [32-1:0] uy_transmitted__20; +wire [32-1:0] uy_transmitted__21; +wire [32-1:0] uy_transmitted__22; +wire [32-1:0] uy_transmitted__23; +wire [32-1:0] uy_transmitted__24; +wire [32-1:0] uy_transmitted__25; +wire [32-1:0] uy_transmitted__26; +wire [32-1:0] uy_transmitted__27; +wire [32-1:0] uy_transmitted__28; +wire [32-1:0] uy_transmitted__29; +wire [32-1:0] uy_transmitted__30; +wire [32-1:0] uy_transmitted__31; +wire [32-1:0] uy_transmitted__32; +wire [32-1:0] uy_transmitted__33; +wire [32-1:0] uy_transmitted__34; +wire [32-1:0] uy_transmitted__35; +wire [32-1:0] uy_transmitted__36; +wire [32-1:0] uy_transmitted__37; + +wire [63:0] new_uz_2; +wire [31:0] new_uz2; +wire [63:0] new_oneMinusUz_2; +wire [63:0] new_sa2_2; +wire [63:0] new_uz2_2; +reg [31:0] new_ux_transmitted; +reg [31:0] new_uy_transmitted; + + + +//------------------Register Pipeline----------------- +//Generation Methodology: Standard block, called InternalsBlock_Reflector, +//is repeated multiple times, based on the `LATency of the reflector and +//scatterer. This block contains the list of all internal variables +//that need to be registered and passed along in the pipeline. +// +//Previous values in the pipeline are passed to the next register on each +//clock tick. The exception comes when an internal variable gets +//calcu`LATed. Each time a new internal variable is calcu`LATed, a new +//case is added to the case statement, and instead of hooking previous +//values of that variable to next, the new, calcu`LATed values are hooked up. +// +//This method will generate many more registers than what are required, but +//it is expected that the synthesis tool will synthesize these away. +// +// +//Commenting Convention: Whenever a new value is injected into the pipe, the +//comment //Changed Value is added directly above the variable in question. +//When multiple values are calcu`LATed in a single clock cycle, multiple such +//comments are placed. Wires connected to "Changed Values" always start with +//the prefix new_. +// +//GENERATE PIPELINE + +//genvar i; +//generate +// for(i=`LAT; i>0; i=i-1) begin: internalPipe_Reflector +// case(i) +// +// 2: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// Changed Value +// .i_uz_2(new_uz_2), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// 3: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// // Changed Value +// .i_oneMinusUz_2(new_oneMinusUz_2), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// 4: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// Changed Value +// .i_sa2_2(new_sa2_2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// 5: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// Changed Value +// .i_uz2_2(new_uz2_2), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// (`SQRT+6): +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// Changed Value +// .i_uz2(new_uz2), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// (`SQRT+`DIV+6): +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// Changed Value +// .i_ux_transmitted(new_ux_transmitted), //New value for ux, if photon moves to next layer +// Changed Value +// .i_uy_transmitted(new_uy_transmitted), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// default: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// endcase +// end +//endgenerate + + + +// special cases first + + // forloop2 + InternalsBlock_Reflector pipeReg2( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + //Changed Value + .i_uz_2(new_uz_2), //uz^2 + .i_uz2(uz2__1), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__1), //(1-uz)^2 + .i_sa2_2(sa2_2__1), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__1), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__1), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__1), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__2), + .o_uz2(uz2__2), + .o_oneMinusUz_2(oneMinusUz_2__2), + .o_sa2_2(sa2_2__2), + .o_uz2_2(uz2_2__2), + .o_ux_transmitted(ux_transmitted__2), + .o_uy_transmitted(uy_transmitted__2) + ); + + // for loop3: + InternalsBlock_Reflector pipeReg3( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__2), //uz^2 + .i_uz2(uz2__2), //new uz, should the photon transmit to new layer + //Changed Value + .i_oneMinusUz_2(new_oneMinusUz_2), //(1-uz)^2 + .i_sa2_2(sa2_2__2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__2), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__2), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__2), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__3), + .o_uz2(uz2__3), + .o_oneMinusUz_2(oneMinusUz_2__3), + .o_sa2_2(sa2_2__3), + .o_uz2_2(uz2_2__3), + .o_ux_transmitted(ux_transmitted__3), + .o_uy_transmitted(uy_transmitted__3) + ); + + // for loop4 + InternalsBlock_Reflector pipeReg4( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__3), //uz^2 + .i_uz2(uz2__3), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__3), //(1-uz)^2 + //Changed Value + .i_sa2_2(new_sa2_2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__3), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__3), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__3), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__4), + .o_uz2(uz2__4), + .o_oneMinusUz_2(oneMinusUz_2__4), + .o_sa2_2(sa2_2__4), + .o_uz2_2(uz2_2__4), + .o_ux_transmitted(ux_transmitted__4), + .o_uy_transmitted(uy_transmitted__4) + ); + + //for loop5 + InternalsBlock_Reflector pipeReg5( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__4), //uz^2 + .i_uz2(uz2__4), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__4), //(1-uz)^2 + .i_sa2_2(sa2_2__4), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + //Changed Value + .i_uz2_2(new_uz2_2), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__4), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__4), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__5), + .o_uz2(uz2__5), + .o_oneMinusUz_2(oneMinusUz_2__5), + .o_sa2_2(sa2_2__5), + .o_uz2_2(uz2_2__5), + .o_ux_transmitted(ux_transmitted__5), + .o_uy_transmitted(uy_transmitted__5) + ); + + //for loop(10+6): + InternalsBlock_Reflector pipeReg16( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__15), //uz^2 + //Changed Value + .i_uz2(new_uz2), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__15), //(1-uz)^2 + .i_sa2_2(sa2_2__15), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__15), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__15), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__15), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__16), + .o_uz2(uz2__16), + .o_oneMinusUz_2(oneMinusUz_2__16), + .o_sa2_2(sa2_2__16), + .o_uz2_2(uz2_2__16), + .o_ux_transmitted(ux_transmitted__16), + .o_uy_transmitted(uy_transmitted__16) + ); + + //for loop (10+20+6): + InternalsBlock_Reflector pipeReg36( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__35), //uz^2 + .i_uz2(uz2__35), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__35), //(1-uz)^2 + .i_sa2_2(sa2_2__35), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__35), //(uz2)^2, new uz squared. + //Changed Value + .i_ux_transmitted(new_ux_transmitted), //New value for ux, if photon moves to next layer + //Changed Value + .i_uy_transmitted(new_uy_transmitted), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__36), + .o_uz2(uz2__36), + .o_oneMinusUz_2(oneMinusUz_2__36), + .o_sa2_2(sa2_2__36), + .o_uz2_2(uz2_2__36), + .o_ux_transmitted(ux_transmitted__36), + .o_uy_transmitted(uy_transmitted__36) + ); + + + //rest of loop + +InternalsBlock_Reflector pipeReg37( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__36), +.i_uz2(uz2__36), +.i_oneMinusUz_2(oneMinusUz_2__36), +.i_sa2_2(sa2_2__36), +.i_uz2_2(uz2_2__36), +.i_ux_transmitted(ux_transmitted__36), +.i_uy_transmitted(uy_transmitted__36), + + //outputs + +.o_uz_2(uz_2__37), +.o_uz2(uz2__37), +.o_oneMinusUz_2(oneMinusUz_2__37), +.o_sa2_2(sa2_2__37), +.o_uz2_2(uz2_2__37), +.o_ux_transmitted(ux_transmitted__37), +.o_uy_transmitted(uy_transmitted__37) +); + +//removed 36 +InternalsBlock_Reflector pipeReg35( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__34), +.i_uz2(uz2__34), +.i_oneMinusUz_2(oneMinusUz_2__34), +.i_sa2_2(sa2_2__34), +.i_uz2_2(uz2_2__34), +.i_ux_transmitted(ux_transmitted__34), +.i_uy_transmitted(uy_transmitted__34), + + //outputs + +.o_uz_2(uz_2__35), +.o_uz2(uz2__35), +.o_oneMinusUz_2(oneMinusUz_2__35), +.o_sa2_2(sa2_2__35), +.o_uz2_2(uz2_2__35), +.o_ux_transmitted(ux_transmitted__35), +.o_uy_transmitted(uy_transmitted__35) +); + +InternalsBlock_Reflector pipeReg34( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__33), +.i_uz2(uz2__33), +.i_oneMinusUz_2(oneMinusUz_2__33), +.i_sa2_2(sa2_2__33), +.i_uz2_2(uz2_2__33), +.i_ux_transmitted(ux_transmitted__33), +.i_uy_transmitted(uy_transmitted__33), + + //outputs + +.o_uz_2(uz_2__34), +.o_uz2(uz2__34), +.o_oneMinusUz_2(oneMinusUz_2__34), +.o_sa2_2(sa2_2__34), +.o_uz2_2(uz2_2__34), +.o_ux_transmitted(ux_transmitted__34), +.o_uy_transmitted(uy_transmitted__34) +); + +InternalsBlock_Reflector pipeReg33( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__32), +.i_uz2(uz2__32), +.i_oneMinusUz_2(oneMinusUz_2__32), +.i_sa2_2(sa2_2__32), +.i_uz2_2(uz2_2__32), +.i_ux_transmitted(ux_transmitted__32), +.i_uy_transmitted(uy_transmitted__32), + + //outputs + +.o_uz_2(uz_2__33), +.o_uz2(uz2__33), +.o_oneMinusUz_2(oneMinusUz_2__33), +.o_sa2_2(sa2_2__33), +.o_uz2_2(uz2_2__33), +.o_ux_transmitted(ux_transmitted__33), +.o_uy_transmitted(uy_transmitted__33) +); + +InternalsBlock_Reflector pipeReg32( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__31), +.i_uz2(uz2__31), +.i_oneMinusUz_2(oneMinusUz_2__31), +.i_sa2_2(sa2_2__31), +.i_uz2_2(uz2_2__31), +.i_ux_transmitted(ux_transmitted__31), +.i_uy_transmitted(uy_transmitted__31), + + //outputs + +.o_uz_2(uz_2__32), +.o_uz2(uz2__32), +.o_oneMinusUz_2(oneMinusUz_2__32), +.o_sa2_2(sa2_2__32), +.o_uz2_2(uz2_2__32), +.o_ux_transmitted(ux_transmitted__32), +.o_uy_transmitted(uy_transmitted__32) +); + +InternalsBlock_Reflector pipeReg31( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__30), +.i_uz2(uz2__30), +.i_oneMinusUz_2(oneMinusUz_2__30), +.i_sa2_2(sa2_2__30), +.i_uz2_2(uz2_2__30), +.i_ux_transmitted(ux_transmitted__30), +.i_uy_transmitted(uy_transmitted__30), + + //outputs + +.o_uz_2(uz_2__31), +.o_uz2(uz2__31), +.o_oneMinusUz_2(oneMinusUz_2__31), +.o_sa2_2(sa2_2__31), +.o_uz2_2(uz2_2__31), +.o_ux_transmitted(ux_transmitted__31), +.o_uy_transmitted(uy_transmitted__31) +); + +InternalsBlock_Reflector pipeReg30( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__29), +.i_uz2(uz2__29), +.i_oneMinusUz_2(oneMinusUz_2__29), +.i_sa2_2(sa2_2__29), +.i_uz2_2(uz2_2__29), +.i_ux_transmitted(ux_transmitted__29), +.i_uy_transmitted(uy_transmitted__29), + + //outputs + +.o_uz_2(uz_2__30), +.o_uz2(uz2__30), +.o_oneMinusUz_2(oneMinusUz_2__30), +.o_sa2_2(sa2_2__30), +.o_uz2_2(uz2_2__30), +.o_ux_transmitted(ux_transmitted__30), +.o_uy_transmitted(uy_transmitted__30) +); + +InternalsBlock_Reflector pipeReg29( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__28), +.i_uz2(uz2__28), +.i_oneMinusUz_2(oneMinusUz_2__28), +.i_sa2_2(sa2_2__28), +.i_uz2_2(uz2_2__28), +.i_ux_transmitted(ux_transmitted__28), +.i_uy_transmitted(uy_transmitted__28), + + //outputs + +.o_uz_2(uz_2__29), +.o_uz2(uz2__29), +.o_oneMinusUz_2(oneMinusUz_2__29), +.o_sa2_2(sa2_2__29), +.o_uz2_2(uz2_2__29), +.o_ux_transmitted(ux_transmitted__29), +.o_uy_transmitted(uy_transmitted__29) +); + +InternalsBlock_Reflector pipeReg28( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__27), +.i_uz2(uz2__27), +.i_oneMinusUz_2(oneMinusUz_2__27), +.i_sa2_2(sa2_2__27), +.i_uz2_2(uz2_2__27), +.i_ux_transmitted(ux_transmitted__27), +.i_uy_transmitted(uy_transmitted__27), + + //outputs + +.o_uz_2(uz_2__28), +.o_uz2(uz2__28), +.o_oneMinusUz_2(oneMinusUz_2__28), +.o_sa2_2(sa2_2__28), +.o_uz2_2(uz2_2__28), +.o_ux_transmitted(ux_transmitted__28), +.o_uy_transmitted(uy_transmitted__28) +); + +InternalsBlock_Reflector pipeReg27( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__26), +.i_uz2(uz2__26), +.i_oneMinusUz_2(oneMinusUz_2__26), +.i_sa2_2(sa2_2__26), +.i_uz2_2(uz2_2__26), +.i_ux_transmitted(ux_transmitted__26), +.i_uy_transmitted(uy_transmitted__26), + + //outputs + +.o_uz_2(uz_2__27), +.o_uz2(uz2__27), +.o_oneMinusUz_2(oneMinusUz_2__27), +.o_sa2_2(sa2_2__27), +.o_uz2_2(uz2_2__27), +.o_ux_transmitted(ux_transmitted__27), +.o_uy_transmitted(uy_transmitted__27) +); + +InternalsBlock_Reflector pipeReg26( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__25), +.i_uz2(uz2__25), +.i_oneMinusUz_2(oneMinusUz_2__25), +.i_sa2_2(sa2_2__25), +.i_uz2_2(uz2_2__25), +.i_ux_transmitted(ux_transmitted__25), +.i_uy_transmitted(uy_transmitted__25), + + //outputs + +.o_uz_2(uz_2__26), +.o_uz2(uz2__26), +.o_oneMinusUz_2(oneMinusUz_2__26), +.o_sa2_2(sa2_2__26), +.o_uz2_2(uz2_2__26), +.o_ux_transmitted(ux_transmitted__26), +.o_uy_transmitted(uy_transmitted__26) +); + +InternalsBlock_Reflector pipeReg25( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__24), +.i_uz2(uz2__24), +.i_oneMinusUz_2(oneMinusUz_2__24), +.i_sa2_2(sa2_2__24), +.i_uz2_2(uz2_2__24), +.i_ux_transmitted(ux_transmitted__24), +.i_uy_transmitted(uy_transmitted__24), + + //outputs + +.o_uz_2(uz_2__25), +.o_uz2(uz2__25), +.o_oneMinusUz_2(oneMinusUz_2__25), +.o_sa2_2(sa2_2__25), +.o_uz2_2(uz2_2__25), +.o_ux_transmitted(ux_transmitted__25), +.o_uy_transmitted(uy_transmitted__25) +); + +InternalsBlock_Reflector pipeReg24( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__23), +.i_uz2(uz2__23), +.i_oneMinusUz_2(oneMinusUz_2__23), +.i_sa2_2(sa2_2__23), +.i_uz2_2(uz2_2__23), +.i_ux_transmitted(ux_transmitted__23), +.i_uy_transmitted(uy_transmitted__23), + + //outputs + +.o_uz_2(uz_2__24), +.o_uz2(uz2__24), +.o_oneMinusUz_2(oneMinusUz_2__24), +.o_sa2_2(sa2_2__24), +.o_uz2_2(uz2_2__24), +.o_ux_transmitted(ux_transmitted__24), +.o_uy_transmitted(uy_transmitted__24) +); + +InternalsBlock_Reflector pipeReg23( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__22), +.i_uz2(uz2__22), +.i_oneMinusUz_2(oneMinusUz_2__22), +.i_sa2_2(sa2_2__22), +.i_uz2_2(uz2_2__22), +.i_ux_transmitted(ux_transmitted__22), +.i_uy_transmitted(uy_transmitted__22), + + //outputs + +.o_uz_2(uz_2__23), +.o_uz2(uz2__23), +.o_oneMinusUz_2(oneMinusUz_2__23), +.o_sa2_2(sa2_2__23), +.o_uz2_2(uz2_2__23), +.o_ux_transmitted(ux_transmitted__23), +.o_uy_transmitted(uy_transmitted__23) +); + +InternalsBlock_Reflector pipeReg22( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__21), +.i_uz2(uz2__21), +.i_oneMinusUz_2(oneMinusUz_2__21), +.i_sa2_2(sa2_2__21), +.i_uz2_2(uz2_2__21), +.i_ux_transmitted(ux_transmitted__21), +.i_uy_transmitted(uy_transmitted__21), + + //outputs + +.o_uz_2(uz_2__22), +.o_uz2(uz2__22), +.o_oneMinusUz_2(oneMinusUz_2__22), +.o_sa2_2(sa2_2__22), +.o_uz2_2(uz2_2__22), +.o_ux_transmitted(ux_transmitted__22), +.o_uy_transmitted(uy_transmitted__22) +); + +InternalsBlock_Reflector pipeReg21( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__20), +.i_uz2(uz2__20), +.i_oneMinusUz_2(oneMinusUz_2__20), +.i_sa2_2(sa2_2__20), +.i_uz2_2(uz2_2__20), +.i_ux_transmitted(ux_transmitted__20), +.i_uy_transmitted(uy_transmitted__20), + + //outputs + +.o_uz_2(uz_2__21), +.o_uz2(uz2__21), +.o_oneMinusUz_2(oneMinusUz_2__21), +.o_sa2_2(sa2_2__21), +.o_uz2_2(uz2_2__21), +.o_ux_transmitted(ux_transmitted__21), +.o_uy_transmitted(uy_transmitted__21) +); + +InternalsBlock_Reflector pipeReg20( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__19), +.i_uz2(uz2__19), +.i_oneMinusUz_2(oneMinusUz_2__19), +.i_sa2_2(sa2_2__19), +.i_uz2_2(uz2_2__19), +.i_ux_transmitted(ux_transmitted__19), +.i_uy_transmitted(uy_transmitted__19), + + //outputs + +.o_uz_2(uz_2__20), +.o_uz2(uz2__20), +.o_oneMinusUz_2(oneMinusUz_2__20), +.o_sa2_2(sa2_2__20), +.o_uz2_2(uz2_2__20), +.o_ux_transmitted(ux_transmitted__20), +.o_uy_transmitted(uy_transmitted__20) +); + +InternalsBlock_Reflector pipeReg19( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__18), +.i_uz2(uz2__18), +.i_oneMinusUz_2(oneMinusUz_2__18), +.i_sa2_2(sa2_2__18), +.i_uz2_2(uz2_2__18), +.i_ux_transmitted(ux_transmitted__18), +.i_uy_transmitted(uy_transmitted__18), + + //outputs + +.o_uz_2(uz_2__19), +.o_uz2(uz2__19), +.o_oneMinusUz_2(oneMinusUz_2__19), +.o_sa2_2(sa2_2__19), +.o_uz2_2(uz2_2__19), +.o_ux_transmitted(ux_transmitted__19), +.o_uy_transmitted(uy_transmitted__19) +); + +InternalsBlock_Reflector pipeReg18( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__17), +.i_uz2(uz2__17), +.i_oneMinusUz_2(oneMinusUz_2__17), +.i_sa2_2(sa2_2__17), +.i_uz2_2(uz2_2__17), +.i_ux_transmitted(ux_transmitted__17), +.i_uy_transmitted(uy_transmitted__17), + + //outputs + +.o_uz_2(uz_2__18), +.o_uz2(uz2__18), +.o_oneMinusUz_2(oneMinusUz_2__18), +.o_sa2_2(sa2_2__18), +.o_uz2_2(uz2_2__18), +.o_ux_transmitted(ux_transmitted__18), +.o_uy_transmitted(uy_transmitted__18) +); + +InternalsBlock_Reflector pipeReg17( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__16), +.i_uz2(uz2__16), +.i_oneMinusUz_2(oneMinusUz_2__16), +.i_sa2_2(sa2_2__16), +.i_uz2_2(uz2_2__16), +.i_ux_transmitted(ux_transmitted__16), +.i_uy_transmitted(uy_transmitted__16), + + //outputs + +.o_uz_2(uz_2__17), +.o_uz2(uz2__17), +.o_oneMinusUz_2(oneMinusUz_2__17), +.o_sa2_2(sa2_2__17), +.o_uz2_2(uz2_2__17), +.o_ux_transmitted(ux_transmitted__17), +.o_uy_transmitted(uy_transmitted__17) +); +//removed 16 + +InternalsBlock_Reflector pipeReg15( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__14), +.i_uz2(uz2__14), +.i_oneMinusUz_2(oneMinusUz_2__14), +.i_sa2_2(sa2_2__14), +.i_uz2_2(uz2_2__14), +.i_ux_transmitted(ux_transmitted__14), +.i_uy_transmitted(uy_transmitted__14), + + //outputs + +.o_uz_2(uz_2__15), +.o_uz2(uz2__15), +.o_oneMinusUz_2(oneMinusUz_2__15), +.o_sa2_2(sa2_2__15), +.o_uz2_2(uz2_2__15), +.o_ux_transmitted(ux_transmitted__15), +.o_uy_transmitted(uy_transmitted__15) +); + +InternalsBlock_Reflector pipeReg14( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__13), +.i_uz2(uz2__13), +.i_oneMinusUz_2(oneMinusUz_2__13), +.i_sa2_2(sa2_2__13), +.i_uz2_2(uz2_2__13), +.i_ux_transmitted(ux_transmitted__13), +.i_uy_transmitted(uy_transmitted__13), + + //outputs + +.o_uz_2(uz_2__14), +.o_uz2(uz2__14), +.o_oneMinusUz_2(oneMinusUz_2__14), +.o_sa2_2(sa2_2__14), +.o_uz2_2(uz2_2__14), +.o_ux_transmitted(ux_transmitted__14), +.o_uy_transmitted(uy_transmitted__14) +); + +InternalsBlock_Reflector pipeReg13( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__12), +.i_uz2(uz2__12), +.i_oneMinusUz_2(oneMinusUz_2__12), +.i_sa2_2(sa2_2__12), +.i_uz2_2(uz2_2__12), +.i_ux_transmitted(ux_transmitted__12), +.i_uy_transmitted(uy_transmitted__12), + + //outputs + +.o_uz_2(uz_2__13), +.o_uz2(uz2__13), +.o_oneMinusUz_2(oneMinusUz_2__13), +.o_sa2_2(sa2_2__13), +.o_uz2_2(uz2_2__13), +.o_ux_transmitted(ux_transmitted__13), +.o_uy_transmitted(uy_transmitted__13) +); + +InternalsBlock_Reflector pipeReg12( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__11), +.i_uz2(uz2__11), +.i_oneMinusUz_2(oneMinusUz_2__11), +.i_sa2_2(sa2_2__11), +.i_uz2_2(uz2_2__11), +.i_ux_transmitted(ux_transmitted__11), +.i_uy_transmitted(uy_transmitted__11), + + //outputs + +.o_uz_2(uz_2__12), +.o_uz2(uz2__12), +.o_oneMinusUz_2(oneMinusUz_2__12), +.o_sa2_2(sa2_2__12), +.o_uz2_2(uz2_2__12), +.o_ux_transmitted(ux_transmitted__12), +.o_uy_transmitted(uy_transmitted__12) +); + +InternalsBlock_Reflector pipeReg11( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__10), +.i_uz2(uz2__10), +.i_oneMinusUz_2(oneMinusUz_2__10), +.i_sa2_2(sa2_2__10), +.i_uz2_2(uz2_2__10), +.i_ux_transmitted(ux_transmitted__10), +.i_uy_transmitted(uy_transmitted__10), + + //outputs + +.o_uz_2(uz_2__11), +.o_uz2(uz2__11), +.o_oneMinusUz_2(oneMinusUz_2__11), +.o_sa2_2(sa2_2__11), +.o_uz2_2(uz2_2__11), +.o_ux_transmitted(ux_transmitted__11), +.o_uy_transmitted(uy_transmitted__11) +); + +InternalsBlock_Reflector pipeReg10( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__9), +.i_uz2(uz2__9), +.i_oneMinusUz_2(oneMinusUz_2__9), +.i_sa2_2(sa2_2__9), +.i_uz2_2(uz2_2__9), +.i_ux_transmitted(ux_transmitted__9), +.i_uy_transmitted(uy_transmitted__9), + + //outputs + +.o_uz_2(uz_2__10), +.o_uz2(uz2__10), +.o_oneMinusUz_2(oneMinusUz_2__10), +.o_sa2_2(sa2_2__10), +.o_uz2_2(uz2_2__10), +.o_ux_transmitted(ux_transmitted__10), +.o_uy_transmitted(uy_transmitted__10) +); + +InternalsBlock_Reflector pipeReg9( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__8), +.i_uz2(uz2__8), +.i_oneMinusUz_2(oneMinusUz_2__8), +.i_sa2_2(sa2_2__8), +.i_uz2_2(uz2_2__8), +.i_ux_transmitted(ux_transmitted__8), +.i_uy_transmitted(uy_transmitted__8), + + //outputs + +.o_uz_2(uz_2__9), +.o_uz2(uz2__9), +.o_oneMinusUz_2(oneMinusUz_2__9), +.o_sa2_2(sa2_2__9), +.o_uz2_2(uz2_2__9), +.o_ux_transmitted(ux_transmitted__9), +.o_uy_transmitted(uy_transmitted__9) +); + +InternalsBlock_Reflector pipeReg8( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__7), +.i_uz2(uz2__7), +.i_oneMinusUz_2(oneMinusUz_2__7), +.i_sa2_2(sa2_2__7), +.i_uz2_2(uz2_2__7), +.i_ux_transmitted(ux_transmitted__7), +.i_uy_transmitted(uy_transmitted__7), + + //outputs + +.o_uz_2(uz_2__8), +.o_uz2(uz2__8), +.o_oneMinusUz_2(oneMinusUz_2__8), +.o_sa2_2(sa2_2__8), +.o_uz2_2(uz2_2__8), +.o_ux_transmitted(ux_transmitted__8), +.o_uy_transmitted(uy_transmitted__8) +); + +InternalsBlock_Reflector pipeReg7( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__6), +.i_uz2(uz2__6), +.i_oneMinusUz_2(oneMinusUz_2__6), +.i_sa2_2(sa2_2__6), +.i_uz2_2(uz2_2__6), +.i_ux_transmitted(ux_transmitted__6), +.i_uy_transmitted(uy_transmitted__6), + + //outputs + +.o_uz_2(uz_2__7), +.o_uz2(uz2__7), +.o_oneMinusUz_2(oneMinusUz_2__7), +.o_sa2_2(sa2_2__7), +.o_uz2_2(uz2_2__7), +.o_ux_transmitted(ux_transmitted__7), +.o_uy_transmitted(uy_transmitted__7) +); + +InternalsBlock_Reflector pipeReg6( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__5), +.i_uz2(uz2__5), +.i_oneMinusUz_2(oneMinusUz_2__5), +.i_sa2_2(sa2_2__5), +.i_uz2_2(uz2_2__5), +.i_ux_transmitted(ux_transmitted__5), +.i_uy_transmitted(uy_transmitted__5), + + //outputs + +.o_uz_2(uz_2__6), +.o_uz2(uz2__6), +.o_oneMinusUz_2(oneMinusUz_2__6), +.o_sa2_2(sa2_2__6), +.o_uz2_2(uz2_2__6), +.o_ux_transmitted(ux_transmitted__6), +.o_uy_transmitted(uy_transmitted__6) +); + + +//removed 2,3,4,5 + + +//peter m +// no driver +assign uz_2__0 = 64'b0; +assign uz2__0 = 32'b0; +assign oneMinusUz_2__0 = 0; +assign sa2_2__0 = 0; +assign uz2_2__0 = 64'b0; +assign ux_transmitted__0 = 32'b00000000000000000000000000000000; +assign uy_transmitted__0 = 32'b00000000000000000000000000000000; + + +InternalsBlock_Reflector pipeReg1( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__0), +.i_uz2(uz2__0), +.i_oneMinusUz_2(oneMinusUz_2__0), +.i_sa2_2(sa2_2__0), +.i_uz2_2(uz2_2__0), +.i_ux_transmitted(ux_transmitted__0), +.i_uy_transmitted(uy_transmitted__0), + + //outputs + +.o_uz_2(uz_2__1), +.o_uz2(uz2__1), +.o_oneMinusUz_2(oneMinusUz_2__1), +.o_sa2_2(sa2_2__1), +.o_uz2_2(uz2_2__1), +.o_ux_transmitted(ux_transmitted__1), +.o_uy_transmitted(uy_transmitted__1) +); + + + + +//-------------SYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is the end of the generate statement, and the beginning of the +//synchronous logic. On the clock event, the outputs calcu`LATed from +//this block are put on the output pins for reading (registered +//outputs, as per the convention). + +//Assign outputs from block on positive clock edge. +always @ (posedge clock) begin + if(reset_new) begin + //Reset internal non-pipelined registers here. + ux_reflector <= 32'h00000000; + uy_reflector <= 32'h00000000; + uz_reflector <= 32'h7FFFFFFF; + layer_reflector <= 3'b001; + dead_reflector <= 1'b1; + end else if (enable) begin + ux_reflector <= new_ux; + uy_reflector <= new_uy; + uz_reflector <= new_uz; + layer_reflector <= new_layer; + dead_reflector <= new_dead; + end +end + + +//-------------ASYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is where the asynchronous logic takes place. Things that +//occur here include setting up wiring to send to the multipliers, +//and square root unit. Also, products brought in from the wrapper +//are placed on the appropriate wires for placement in the pipeline. + +//-------------MUXES for SYNCHRONOUS LOGIC-------- +always @ (i_layer36 or downCritAngle_0 or upCritAngle_0 or + downCritAngle_1 or upCritAngle_1 or + downCritAngle_2 or upCritAngle_2 or + downCritAngle_3 or upCritAngle_3 or + downCritAngle_4 or upCritAngle_4) begin + case (i_layer36) + 1:begin + downCritAngle = downCritAngle_0; + upCritAngle = upCritAngle_0; + end + 2:begin + downCritAngle = downCritAngle_1; + upCritAngle = upCritAngle_1; + end + 3:begin + downCritAngle = downCritAngle_2; + upCritAngle = upCritAngle_2; + end + 4:begin + downCritAngle = downCritAngle_3; + upCritAngle = upCritAngle_3; + end + 5:begin + downCritAngle = downCritAngle_4; + upCritAngle = upCritAngle_4; + end + //Should never occur + default:begin + downCritAngle = downCritAngle_0; + upCritAngle = upCritAngle_0; + end + endcase +end + +always @ (i_uz35 or i_layer35) begin + negUz = -i_uz35; + case (i_uz35[31]) + 0: begin + case (i_layer35) + 1: fresIndex = {3'b000, i_uz35[30:24]}; + 2: fresIndex = {3'b001, i_uz35[30:24]}; + 3: fresIndex = {3'b010, i_uz35[30:24]}; + 4: fresIndex = {3'b011, i_uz35[30:24]}; + 5: fresIndex = {3'b100, i_uz35[30:24]}; + //Should never occur + default: fresIndex = {3'b000, i_uz35[30:24]}; + endcase + end + 1: begin + case (i_layer35) + 1: fresIndex = {3'b000, negUz[30:24]}; + 2: fresIndex = {3'b001, negUz[30:24]}; + 3: fresIndex = {3'b010, negUz[30:24]}; + 4: fresIndex = {3'b011, negUz[30:24]}; + 5: fresIndex = {3'b100, negUz[30:24]}; + //Should never occur + default: fresIndex = {3'b000, negUz[30:24]}; + endcase + end + endcase + +end + + +//-------------OPERAND SETUP---------------------- + + +//NAMING CONVENTION: +//opX_Y_Z, op stands for operand, X stands for the multiplication number for +//that clock cycle, Y stands for the clock cycle, Z is either 1 or 2 for the +//first or second operand for this multiply +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calcu`LATed will be ready for the Xth register +//location, where 0 is the register prior to any calcu`LATions being done, 1 is +//after the 1st clock cycle of calcu`LATion, etc. + +//CC 2 +assign op1_2_1 = i_uz1; +assign op1_2_2 = i_uz1; + +//CC 3 +//SUBTRACTION, see math results + +//CC 4 +always @ (i_uz3 or i_layer3 or down_niOverNt_2_1 or up_niOverNt_2_1 or + down_niOverNt_2_2 or up_niOverNt_2_2 or + down_niOverNt_2_3 or up_niOverNt_2_3 or + down_niOverNt_2_4 or up_niOverNt_2_4 or + down_niOverNt_2_5 or up_niOverNt_2_5) begin + case (i_uz3[31]) + //uz >= 0 + 0:begin + case (i_layer3) + 1: op1_4_1 = {down_niOverNt_2_1[63], down_niOverNt_2_1[61:31]}; + 2: op1_4_1 = {down_niOverNt_2_2[63], down_niOverNt_2_2[61:31]}; + 3: op1_4_1 = {down_niOverNt_2_3[63], down_niOverNt_2_3[61:31]}; + 4: op1_4_1 = {down_niOverNt_2_4[63], down_niOverNt_2_4[61:31]}; + 5: op1_4_1 = {down_niOverNt_2_5[63], down_niOverNt_2_5[61:31]}; + default: op1_4_1 = {down_niOverNt_2_1[63], down_niOverNt_2_1[61:31]}; + endcase + end + //uz < 0 + 1:begin + case (i_layer3) + 1: op1_4_1 = {up_niOverNt_2_1[63], up_niOverNt_2_1[61:31]}; + 2: op1_4_1 = {up_niOverNt_2_2[63], up_niOverNt_2_2[61:31]}; + 3: op1_4_1 = {up_niOverNt_2_3[63], up_niOverNt_2_3[61:31]}; + 4: op1_4_1 = {up_niOverNt_2_4[63], up_niOverNt_2_4[61:31]}; + 5: op1_4_1 = {up_niOverNt_2_5[63], up_niOverNt_2_5[61:31]}; + default: op1_4_1 = {up_niOverNt_2_1[63], up_niOverNt_2_1[61:31]}; + endcase + end + endcase +end + +assign op1_4_2 = {oneMinusUz_2__3[63], oneMinusUz_2__3[61:31]}; + +//CC 5 +//SUBTRACTION, see math results + +//CC `SQRT+5 -- Started in CC 6 +assign sqrtOperand1_6 = uz2_2__5; + +//CC `SQRT+`DIV+6 -- Line up with Scatterer. +assign op1_36_1 = i_ux35; + +always @ (i_uz35 or i_layer35 or down_niOverNt_1 or up_niOverNt_1 or + down_niOverNt_2 or up_niOverNt_2 or + down_niOverNt_3 or up_niOverNt_3 or + down_niOverNt_4 or up_niOverNt_4 or + down_niOverNt_5 or up_niOverNt_5) begin + case (i_uz35[31]) + 0: begin//uz >= 0 + case (i_layer35) + 1:begin + op1_36_2 = down_niOverNt_1; + op2_36_2 = down_niOverNt_1; + end + 2:begin + op1_36_2 = down_niOverNt_2; + op2_36_2 = down_niOverNt_2; + end + 3:begin + op1_36_2 = down_niOverNt_3; + op2_36_2 = down_niOverNt_3; + end + 4:begin + op1_36_2 = down_niOverNt_4; + op2_36_2 = down_niOverNt_4; + end + 5:begin + op1_36_2 = down_niOverNt_5; + op2_36_2 = down_niOverNt_5; + end + default:begin + op1_36_2 = down_niOverNt_1; + op2_36_2 = down_niOverNt_1; + end + endcase + end + 1: begin//uz < 0 + case (i_layer35) + 1:begin + op1_36_2 = up_niOverNt_1; + op2_36_2 = up_niOverNt_1; + end + 2:begin + op1_36_2 = up_niOverNt_2; + op2_36_2 = up_niOverNt_2; + end + 3:begin + op1_36_2 = up_niOverNt_3; + op2_36_2 = up_niOverNt_3; + end + 4:begin + op1_36_2 = up_niOverNt_4; + op2_36_2 = up_niOverNt_4; + end + 5:begin + op1_36_2 = up_niOverNt_5; + op2_36_2 = up_niOverNt_5; + end + default:begin + op1_36_2 = up_niOverNt_1; + op2_36_2 = up_niOverNt_1; + end + endcase + end + endcase +end + +assign op2_36_1 = i_uy35; + + + + + +//-------------MATH RESULTS---------------------- + + +//NAMING CONVENTION: +//new_VAR means that the variable named VAR will be stored into the register +//pipeline at the clock cycle indicated by the comments above it. +// +//prod stands for product, quot stands for quotient, `SQRT stands for square root +//prodX_Y means the Xth product which started calcu`LATion at the Yth clock cycle +//Similarly for quot and `SQRTResult. +// +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calcu`LATed will be ready for the Xth register +//location, where 0 is the register prior to any calcu`LATions being done, 1 is +//after the 1st clock cycle of calcu`LATion, etc. + + +//CC 2 +assign new_uz_2 = prod1_2; + +//CC 3 +sub_64b oneMinusUz2_sub( + .dataa(`INTMAX_2_ref), + .datab(uz_2__2), + .result(new_oneMinusUz_2) + ); + +//CC 4 +//Used to determine whether or not the multiply operation overflowed. +//or U1(overflow1_4, prod1_4[62], prod1_4[61], prod1_4[60], prod1_4[59], prod1_4[58]); +assign overflow1_4 = prod1_4[62]|prod1_4[61]|prod1_4[60]|prod1_4[59]|prod1_4[58]; + +//Cannot take `SQRT of negative number, that is why prod1_4[58] must be 0. + + //sign //data //padding +assign new_sa2_2 = (overflow1_4 == 1)? `INTMAX_2_ref : {prod1_4[63], prod1_4[58:0], 4'h0}; + +//5th CC +sub_64b uz2_2_sub( + .dataa(`INTMAX_2_ref), + .datab(sa2_2__4), + .result(new_uz2_2) + ); + +//CC `SQRT+5 +assign new_uz2 = sqrtResult1_6; + +//CC `SQRT+`DIV+6 -- Line up with Scatterer. + + +//Used to determine whether or not the multiply operation overflowed. +//or U2(toAnd1_36_1, prod1_36[62], prod1_36[61], prod1_36[60]); +assign toAnd1_36_1 = prod1_36[62]|prod1_36[61]|prod1_36[60]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U3(toAnd1_36_2, ~prod1_36[62], ~prod1_36[61], ~prod1_36[60]); +assign toAnd1_36_2 = ~prod1_36[62]|~prod1_36[61]|~prod1_36[60]; + +//and U4(overflow1_36, ~prod1_36[63], toAnd1_36_1); +assign overflow1_36 = ~prod1_36[63] & toAnd1_36_1; +//and U5(negOverflow1_36, prod1_36[63], toAnd1_36_2); +assign negOverflow1_36 = prod1_36[63] & toAnd1_36_2; + + +//Used to determine whether or not the multiply operation overflowed. +//or U6(toAnd2_36_1, prod2_36[62], prod2_36[61], prod2_36[60]); +assign toAnd2_36_1 = prod2_36[62]|prod2_36[61]|prod2_36[60]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U7(toAnd2_36_2, ~prod2_36[62], ~prod2_36[61], ~prod2_36[60]); +assign toAnd2_36_2 = ~prod2_36[62]|~prod2_36[61]|~prod2_36[60]; + + +//and U8(overflow2_36, ~prod2_36[63], toAnd2_36_1); +assign overflow2_36 = ~prod2_36[63] & toAnd2_36_1; +//and U9(negOverflow2_36, prod2_36[63], toAnd2_36_2); +assign negOverflow2_36 = prod2_36[63] & toAnd2_36_2; + +always @ (overflow1_36 or negOverflow1_36 or prod1_36 or + overflow2_36 or negOverflow2_36 or prod2_36) begin + case ({overflow1_36, negOverflow1_36}) + 0: new_ux_transmitted = {prod1_36[63:63], prod1_36[59:29]}; + 1: new_ux_transmitted = `INTMIN; + 2: new_ux_transmitted = `INTMAX; + //Should never occur + 3: new_ux_transmitted = {prod1_36[63:63], prod1_36[59:29]}; + endcase + + case ({overflow2_36, negOverflow2_36}) + + 0: new_uy_transmitted = {prod2_36[63:63], prod2_36[59:29]}; + 1: new_uy_transmitted = `INTMIN; + 2: new_uy_transmitted = `INTMAX; + //Should never occur + 3: new_uy_transmitted = {prod2_36[63:63], prod2_36[59:29]}; + endcase +end + + +//-------------FINAL CALCU`LATED VALUES---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +// +// +always @ (i_uz36 or downCritAngle or upCritAngle or down_rFresnel or i_ux36 or + i_uy36 or i_layer36 or i_dead36 or rnd or up_rFresnel or ux_transmitted__37 or + uy_transmitted__37 or uz2__37) begin + //REFLECTED -- Due to total internal reflection while moving down + if (~i_uz36[31] && i_uz36 <= downCritAngle) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to total internal reflection while moving up + end else if (i_uz36[31] && -i_uz36 <= upCritAngle) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to random number being too small while moving down + end else if (~i_uz36[31] && rnd <= down_rFresnel) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to random number being too small while moving up + end else if (i_uz36[31] && rnd <= up_rFresnel) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //TRANSMITTED + end else begin + new_ux = ux_transmitted__37; + new_uy = uy_transmitted__37; + case (i_uz36[31]) + 0:begin//uz >= 0 + if (i_layer36 == 5) begin + new_layer = 3'h5; + new_dead = 1'b1; + end else begin + new_layer = i_layer36+3'h1; + new_dead = i_dead36; + end + new_uz = uz2__37; + end + 1:begin//uz < 0 + if (i_layer36 == 1) begin + new_layer = 3'h1; + new_dead = 1'b1; + end else begin + new_layer = i_layer36-3'h1; + new_dead = i_dead36; + end + new_uz = -uz2__37; + end + endcase + + end +end + +endmodule + + +module Memory_Wrapper ( + //Inputs + clock, +// reset, //This is unused in the module. ODIN II complains. + pindex, + //Outputs + sinp, + cosp + ); + + +input clock; +//input reset; +input [9:0] pindex; + + +output [31:0] sinp; +output [31:0] cosp; + +//sinp_ROM sinp_MEM (.address(pindex), .clock(clock), .q(sinp)); +//cosp_ROM cosp_MEM (.address(pindex), .clock(clock), .q(cosp)); + +//Instantiate a single port ram for odin +wire [31:0]blank; +assign blank = 32'b000000000000000000000000000000; +single_port_ram_1024x32 sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (sinp)); +single_port_ram_1024x32 cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp)); + + +endmodule + + +module InternalsBlock( + //Inputs + clock, + reset, + enable, + + i_sint, + i_cost, + i_sinp, + i_cosp, + i_sintCosp, + i_sintSinp, + i_uz2, + i_uxUz, + i_uyUz, + i_uySintSinp, + i_oneMinusUz2, + i_uyUzSintCosp, + i_uxUzSintCosp, + i_uxSintSinp, + i_sqrtOneMinusUz2, + i_sintCospSqrtOneMinusUz2, + i_uxCost, + i_uzCost, + i_sqrtOneMinusUz2_inv, + i_uxNumerator, + i_uyNumerator, + i_uyCost, + i_uxQuotient, + i_uyQuotient, + //Outputs + o_sint, + o_cost, + o_sinp, + o_cosp, + o_sintCosp, + o_sintSinp, + o_uz2, + o_uxUz, + o_uyUz, + o_uySintSinp, + o_oneMinusUz2, + o_uyUzSintCosp, + o_uxUzSintCosp, + o_uxSintSinp, + o_sqrtOneMinusUz2, + o_sintCospSqrtOneMinusUz2, + o_uxCost, + o_uzCost, + o_sqrtOneMinusUz2_inv, + o_uxNumerator, + o_uyNumerator, + o_uyCost, + o_uxQuotient, + o_uyQuotient + ); + +input clock; +input reset; +input enable; + +input [31:0] i_sint; +input [31:0] i_cost; +input [31:0] i_sinp; +input [31:0] i_cosp; +input [31:0] i_sintCosp; +input [31:0] i_sintSinp; +input [63:0] i_uz2; +input [31:0] i_uxUz; +input [31:0] i_uyUz; +input [31:0] i_uySintSinp; +input [63:0] i_oneMinusUz2; +input [31:0] i_uyUzSintCosp; +input [31:0] i_uxUzSintCosp; +input [31:0] i_uxSintSinp; +input [31:0] i_sqrtOneMinusUz2; +input [31:0] i_sintCospSqrtOneMinusUz2; +input [31:0] i_uxCost; +input [31:0] i_uzCost; +input [31:0] i_sqrtOneMinusUz2_inv; +input [31:0] i_uxNumerator; +input [31:0] i_uyNumerator; +input [31:0] i_uyCost; +input [31:0] i_uxQuotient; +input [31:0] i_uyQuotient; + + +output [31:0] o_sint; +output [31:0] o_cost; +output [31:0] o_sinp; +output [31:0] o_cosp; +output [31:0] o_sintCosp; +output [31:0] o_sintSinp; +output [63:0] o_uz2; +output [31:0] o_uxUz; +output [31:0] o_uyUz; +output [31:0] o_uySintSinp; +output [63:0] o_oneMinusUz2; +output [31:0] o_uyUzSintCosp; +output [31:0] o_uxUzSintCosp; +output [31:0] o_uxSintSinp; +output [31:0] o_sqrtOneMinusUz2; +output [31:0] o_sintCospSqrtOneMinusUz2; +output [31:0] o_uxCost; +output [31:0] o_uzCost; +output [31:0] o_sqrtOneMinusUz2_inv; +output [31:0] o_uxNumerator; +output [31:0] o_uyNumerator; +output [31:0] o_uyCost; +output [31:0] o_uxQuotient; +output [31:0] o_uyQuotient; + + +wire clock; +wire reset; +wire enable; + +wire [31:0] i_sint; +wire [31:0] i_cost; +wire [31:0] i_sinp; +wire [31:0] i_cosp; +wire [31:0] i_sintCosp; +wire [31:0] i_sintSinp; +wire [63:0] i_uz2; +wire [31:0] i_uxUz; +wire [31:0] i_uyUz; +wire [31:0] i_uySintSinp; +wire [63:0] i_oneMinusUz2; +wire [31:0] i_uyUzSintCosp; +wire [31:0] i_uxUzSintCosp; +wire [31:0] i_uxSintSinp; +wire [31:0] i_sqrtOneMinusUz2; +wire [31:0] i_sintCospSqrtOneMinusUz2; +wire [31:0] i_uxCost; +wire [31:0] i_uzCost; +wire [31:0] i_sqrtOneMinusUz2_inv; +wire [31:0] i_uxNumerator; +wire [31:0] i_uyNumerator; +wire [31:0] i_uyCost; +wire [31:0] i_uxQuotient; +wire [31:0] i_uyQuotient; + + +reg [31:0] o_sint; +reg [31:0] o_cost; +reg [31:0] o_sinp; +reg [31:0] o_cosp; +reg [31:0] o_sintCosp; +reg [31:0] o_sintSinp; +reg [63:0] o_uz2; +reg [31:0] o_uxUz; +reg [31:0] o_uyUz; +reg [31:0] o_uySintSinp; +reg [63:0] o_oneMinusUz2; +reg [31:0] o_uyUzSintCosp; +reg [31:0] o_uxUzSintCosp; +reg [31:0] o_uxSintSinp; +reg [31:0] o_sqrtOneMinusUz2; +reg [31:0] o_sintCospSqrtOneMinusUz2; +reg [31:0] o_uxCost; +reg [31:0] o_uzCost; +reg [31:0] o_sqrtOneMinusUz2_inv; +reg [31:0] o_uxNumerator; +reg [31:0] o_uyNumerator; +reg [31:0] o_uyCost; +reg [31:0] o_uxQuotient; +reg [31:0] o_uyQuotient; + + + + +always @ (posedge clock) + if(reset) begin + o_sint <= 32'h00000000; + o_cost <= 32'h00000000; + o_sinp <= 32'h00000000; + o_cosp <= 32'h00000000; + o_sintCosp <= 32'h00000000; + o_sintSinp <= 32'h00000000; + o_uz2 <= 64'h0000000000000000; + o_uxUz <= 32'h00000000; + o_uyUz <= 32'h00000000; + o_uySintSinp <= 32'h00000000; + o_oneMinusUz2 <= 64'h0000000000000000; + o_uyUzSintCosp <= 32'h00000000; + o_uxUzSintCosp <= 32'h00000000; + o_uxSintSinp <= 32'h00000000; + o_sqrtOneMinusUz2 <= 32'h00000000; + o_sintCospSqrtOneMinusUz2 <= 32'h00000000; + o_uxCost <= 32'h00000000; + o_uzCost <= 32'h00000000; + o_sqrtOneMinusUz2_inv <= 32'h00000000; + o_uxNumerator <= 32'h00000000; + o_uyNumerator <= 32'h00000000; + o_uyCost <= 32'h00000000; + o_uxQuotient <= 32'h00000000; + o_uyQuotient <= 32'h00000000; + end else if(enable) begin + o_sint <= i_sint; + o_cost <= i_cost; + o_sinp <= i_sinp; + o_cosp <= i_cosp; + o_sintCosp <= i_sintCosp; + o_sintSinp <= i_sintSinp; + o_uz2 <= i_uz2; + o_uxUz <= i_uxUz; + o_uyUz <= i_uyUz; + o_uySintSinp <= i_uySintSinp; + o_oneMinusUz2 <= i_oneMinusUz2; + o_uyUzSintCosp <= i_uyUzSintCosp; + o_uxUzSintCosp <= i_uxUzSintCosp; + o_uxSintSinp <= i_uxSintSinp; + o_sqrtOneMinusUz2 <= i_sqrtOneMinusUz2; + o_sintCospSqrtOneMinusUz2 <= i_sintCospSqrtOneMinusUz2; + o_uxCost <= i_uxCost; + o_uzCost <= i_uzCost; + o_sqrtOneMinusUz2_inv <= i_sqrtOneMinusUz2_inv; + o_uxNumerator <= i_uxNumerator; + o_uyNumerator <= i_uyNumerator; + o_uyCost <= i_uyCost; + o_uxQuotient <= i_uxQuotient; + o_uyQuotient <= i_uyQuotient; + end +endmodule + + +module Scatterer ( + //INPUTS + clock, + reset, + enable, + //Values from Photon Pipeline + i_uz1, + i_ux3, + i_uz3, + i_uy32, + i_uz32, + i_ux33, + i_uy33, + i_ux35, + i_uy35, + i_uz35, + i_uz36, + + //Mathematics Results + prod1_2, + prod1_4, + sqrtResult1_6, + prod1_33, + prod2_33, + prod3_33, + prod1_34, + prod2_34, + prod3_34, + prod4_34, + quot1_16, + prod1_36, + prod2_36, + prod3_36, + prod4_36, + prod5_36, + prod6_36, + + //Trig from Memory + sint_Mem, + cost_Mem, + sinp_Mem, + cosp_Mem, + + //OUTPUTS + op1_2_1, + op1_2_2, + op1_4_1, + op1_4_2, + sqrtOperand1_6, + divNumerator1_16, + divDenominator1_16, + op1_33_1, + op1_33_2, + op2_33_1, + op2_33_2, + op3_33_1, + op3_33_2, + op1_34_1, + op1_34_2, + op2_34_1, + op2_34_2, + op3_34_1, + op3_34_2, + op4_34_1, + op4_34_2, + op1_36_1, + op1_36_2, + op2_36_1, + op2_36_2, + op3_36_1, + op3_36_2, + op4_36_1, + op4_36_2, + op5_36_1, + op5_36_2, + op6_36_1, + op6_36_2, + + //Final calculated values + ux_scatterer, + uy_scatterer, + uz_scatterer + + + ); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used later in the program. + +//parameter DIV = 20; +//parameter SQRT = 10; +//parameter LAT = DIV + SQRT + 7; +//parameter `INTMAX_2 = 64'h3FFFFFFF00000001; +//parameter `INTMAX = 2147483647; +//parameter `INTMIN = -2147483647; +//parameter `INTMAXMinus3 = 2147483644; +//parameter neg`INTMAXPlus3 = -2147483644; + + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). + +input clock; +input reset; +input enable; +//Values from Photon Pipeline +input [31:0] i_uz1; +input [31:0] i_ux3; +input [31:0] i_uz3; +input [31:0] i_uy32; +input [31:0] i_uz32; +input [31:0] i_ux33; +input [31:0] i_uy33; +input [31:0] i_ux35; +input [31:0] i_uy35; +input [31:0] i_uz35; +input [31:0] i_uz36; + +//Multiplication Results +input [63:0] prod1_2; +input [31:0] prod1_4; +input [31:0] sqrtResult1_6; +input [31:0] prod1_33; +input [31:0] prod2_33; +input [31:0] prod3_33; +input [31:0] prod1_34; +input [31:0] prod2_34; +input [31:0] prod3_34; +input [31:0] prod4_34; +input [63:0] quot1_16; +//Need all 64-bits for these two to detect overflows +input [63:0] prod1_36; +input [63:0] prod2_36; +input [31:0] prod3_36; +input [31:0] prod4_36; +input [31:0] prod5_36; +input [31:0] prod6_36; + + +//Trig Values from Memory +input [31:0] sint_Mem; +input [31:0] cost_Mem; +input [31:0] sinp_Mem; +input [31:0] cosp_Mem; + +output [31:0] op1_2_1; +output [31:0] op1_2_2; +output [31:0] op1_4_1; +output [31:0] op1_4_2; +output [63:0] sqrtOperand1_6; +output [63:0] divNumerator1_16; +output [31:0] divDenominator1_16; +output [31:0] op1_33_1; +output [31:0] op1_33_2; +output [31:0] op2_33_1; +output [31:0] op2_33_2; +output [31:0] op3_33_1; +output [31:0] op3_33_2; +output [31:0] op1_34_1; +output [31:0] op1_34_2; +output [31:0] op2_34_1; +output [31:0] op2_34_2; +output [31:0] op3_34_1; +output [31:0] op3_34_2; +output [31:0] op4_34_1; +output [31:0] op4_34_2; +output [31:0] op1_36_1; +output [31:0] op1_36_2; +output [31:0] op2_36_1; +output [31:0] op2_36_2; +output [31:0] op3_36_1; +output [31:0] op3_36_2; +output [31:0] op4_36_1; +output [31:0] op4_36_2; +output [31:0] op5_36_1; +output [31:0] op5_36_2; +output [31:0] op6_36_1; +output [31:0] op6_36_2; + +//Final Calculated Results +output [31:0] ux_scatterer; +output [31:0] uy_scatterer; +output [31:0] uz_scatterer; + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. + + +wire clock; +wire reset; +wire enable; +//Values from Photon Pipeline +wire [31:0] i_uz1; +wire [31:0] i_ux3; +wire [31:0] i_uz3; +wire [31:0] i_uy32; +wire [31:0] i_uz32; +wire [31:0] i_ux33; +wire [31:0] i_uy33; +wire [31:0] i_ux35; +wire [31:0] i_uy35; +wire [31:0] i_uz35; +wire [31:0] i_uz36; + +//Multiplication Results +wire [63:0] prod1_2; +wire [31:0] prod1_4; +wire [31:0] sqrtResult1_6; +wire [31:0] prod1_33; +wire [31:0] prod2_33; +wire [31:0] prod3_33; +wire [31:0] prod1_34; +wire [31:0] prod2_34; +wire [31:0] prod3_34; +wire [31:0] prod4_34; +wire [63:0] quot1_16; +wire [63:0] prod1_36; +wire [63:0] prod2_36; +wire [31:0] prod3_36; +wire [31:0] prod4_36; +wire [31:0] prod5_36; +wire [31:0] prod6_36; + + +//Trig Values from Memory +wire [31:0] sint_Mem; +wire [31:0] cost_Mem; +wire [31:0] sinp_Mem; +wire [31:0] cosp_Mem; + +//Operands for shared resources +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +wire [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [63:0] divNumerator1_16; +wire [31:0] divDenominator1_16; +wire [31:0] op1_33_1; +wire [31:0] op1_33_2; +wire [31:0] op2_33_1; +wire [31:0] op2_33_2; +wire [31:0] op3_33_1; +wire [31:0] op3_33_2; +wire [31:0] op1_34_1; +wire [31:0] op1_34_2; +wire [31:0] op2_34_1; +wire [31:0] op2_34_2; +wire [31:0] op3_34_1; +wire [31:0] op3_34_2; +wire [31:0] op4_34_1; +wire [31:0] op4_34_2; +wire [31:0] op1_36_1; +wire [31:0] op1_36_2; +wire [31:0] op2_36_1; +wire [31:0] op2_36_2; +wire [31:0] op3_36_1; +wire [31:0] op3_36_2; +wire [31:0] op4_36_1; +wire [31:0] op4_36_2; +wire [31:0] op5_36_1; +wire [31:0] op5_36_2; +wire [31:0] op6_36_1; +wire [31:0] op6_36_2; + +//Final outputs +reg [31:0] ux_scatterer; +reg [31:0] uy_scatterer; +reg [31:0] uz_scatterer; + + +//Need this to deal with 'unused' inputs for ODIN II +wire [63:0]bigOr; +assign bigOr = quot1_16|prod1_36|prod2_36|({32'hFFFFFFFF,32'hFFFFFFFF}); +wire reset_new; +assign reset_new = reset & bigOr[63] & bigOr[62] & bigOr[61] & bigOr[60] & bigOr[59] & bigOr[58] & bigOr[57] & bigOr[56] & bigOr[55] & bigOr[54] & bigOr[53] & bigOr[52] & bigOr[51] & bigOr[50] & bigOr[49] & bigOr[48] & bigOr[47] & bigOr[46] & bigOr[45] & bigOr[44] & bigOr[43] & bigOr[42] & bigOr[41] & bigOr[40] & bigOr[39] & bigOr[38] & bigOr[37] & bigOr[36] & bigOr[35] & bigOr[34] & bigOr[33] & bigOr[32] & bigOr[31] & bigOr[30] & bigOr[29] & bigOr[28] & bigOr[27] & bigOr[26] & bigOr[25] & bigOr[24] & bigOr[23] & bigOr[22] & bigOr[21] & bigOr[20] & bigOr[19] & bigOr[18] & bigOr[17] & bigOr[16] & bigOr[15] & bigOr[14] & bigOr[13] & bigOr[12] & bigOr[11] & bigOr[10] & bigOr[9] & bigOr[8] & bigOr[7] & bigOr[6] & bigOr[5] & bigOr[4] & bigOr[3] & bigOr[2] & bigOr[1] & bigOr[0]; + + +//-----------------------------END Pin Types------------------------- + + + +//Wires to Connect to Internal Registers +//wire [31:0] sint[`LAT:0]; +//wire [31:0] cost[`LAT:0]; +//wire [31:0] sinp[`LAT:0]; +//wire [31:0] cosp[`LAT:0]; +//wire [31:0] sintCosp[`LAT:0]; +//wire [31:0] sintSinp[`LAT:0]; +//wire [63:0] uz2[`LAT:0]; +//wire [31:0] uxUz[`LAT:0]; +//wire [31:0] uyUz[`LAT:0]; +//wire [31:0] uySintSinp[`LAT:0]; +//wire [63:0] oneMinusUz2[`LAT:0]; +//wire [31:0] uyUzSintCosp[`LAT:0]; +//wire [31:0] uxUzSintCosp[`LAT:0]; +//wire [31:0] uxSintSinp[`LAT:0]; +//wire [31:0] sqrtOneMinusUz2[`LAT:0]; +//wire [31:0] sintCospSqrtOneMinusUz2[`LAT:0]; +//wire [31:0] uxCost[`LAT:0]; +//wire [31:0] uzCost[`LAT:0]; +//wire [31:0] sqrtOneMinusUz2_inv[`LAT:0]; +//wire [31:0] uxNumerator[`LAT:0]; +//wire [31:0] uyNumerator[`LAT:0]; +//wire [31:0] uyCost[`LAT:0]; +//wire [31:0] uxQuotient[`LAT:0]; +//wire [31:0] uyQuotient[`LAT:0]; +//wire [31:0] sint[37:0]; +wire [32-1:0] sint__0; +wire [32-1:0] sint__1; +wire [32-1:0] sint__2; +wire [32-1:0] sint__3; +wire [32-1:0] sint__4; +wire [32-1:0] sint__5; +wire [32-1:0] sint__6; +wire [32-1:0] sint__7; +wire [32-1:0] sint__8; +wire [32-1:0] sint__9; +wire [32-1:0] sint__10; +wire [32-1:0] sint__11; +wire [32-1:0] sint__12; +wire [32-1:0] sint__13; +wire [32-1:0] sint__14; +wire [32-1:0] sint__15; +wire [32-1:0] sint__16; +wire [32-1:0] sint__17; +wire [32-1:0] sint__18; +wire [32-1:0] sint__19; +wire [32-1:0] sint__20; +wire [32-1:0] sint__21; +wire [32-1:0] sint__22; +wire [32-1:0] sint__23; +wire [32-1:0] sint__24; +wire [32-1:0] sint__25; +wire [32-1:0] sint__26; +wire [32-1:0] sint__27; +wire [32-1:0] sint__28; +wire [32-1:0] sint__29; +wire [32-1:0] sint__30; +wire [32-1:0] sint__31; +wire [32-1:0] sint__32; +wire [32-1:0] sint__33; +wire [32-1:0] sint__34; +wire [32-1:0] sint__35; +wire [32-1:0] sint__36; +wire [32-1:0] sint__37; + + + + + +//wire [31:0] cost[37:0]; + + +wire [32-1:0] cost__0; +wire [32-1:0] cost__1; +wire [32-1:0] cost__2; +wire [32-1:0] cost__3; +wire [32-1:0] cost__4; +wire [32-1:0] cost__5; +wire [32-1:0] cost__6; +wire [32-1:0] cost__7; +wire [32-1:0] cost__8; +wire [32-1:0] cost__9; +wire [32-1:0] cost__10; +wire [32-1:0] cost__11; +wire [32-1:0] cost__12; +wire [32-1:0] cost__13; +wire [32-1:0] cost__14; +wire [32-1:0] cost__15; +wire [32-1:0] cost__16; +wire [32-1:0] cost__17; +wire [32-1:0] cost__18; +wire [32-1:0] cost__19; +wire [32-1:0] cost__20; +wire [32-1:0] cost__21; +wire [32-1:0] cost__22; +wire [32-1:0] cost__23; +wire [32-1:0] cost__24; +wire [32-1:0] cost__25; +wire [32-1:0] cost__26; +wire [32-1:0] cost__27; +wire [32-1:0] cost__28; +wire [32-1:0] cost__29; +wire [32-1:0] cost__30; +wire [32-1:0] cost__31; +wire [32-1:0] cost__32; +wire [32-1:0] cost__33; +wire [32-1:0] cost__34; +wire [32-1:0] cost__35; +wire [32-1:0] cost__36; +wire [32-1:0] cost__37; + + +//wire [31:0] sinp[37:0]; + + +wire [32-1:0] sinp__0; +wire [32-1:0] sinp__1; +wire [32-1:0] sinp__2; +wire [32-1:0] sinp__3; +wire [32-1:0] sinp__4; +wire [32-1:0] sinp__5; +wire [32-1:0] sinp__6; +wire [32-1:0] sinp__7; +wire [32-1:0] sinp__8; +wire [32-1:0] sinp__9; +wire [32-1:0] sinp__10; +wire [32-1:0] sinp__11; +wire [32-1:0] sinp__12; +wire [32-1:0] sinp__13; +wire [32-1:0] sinp__14; +wire [32-1:0] sinp__15; +wire [32-1:0] sinp__16; +wire [32-1:0] sinp__17; +wire [32-1:0] sinp__18; +wire [32-1:0] sinp__19; +wire [32-1:0] sinp__20; +wire [32-1:0] sinp__21; +wire [32-1:0] sinp__22; +wire [32-1:0] sinp__23; +wire [32-1:0] sinp__24; +wire [32-1:0] sinp__25; +wire [32-1:0] sinp__26; +wire [32-1:0] sinp__27; +wire [32-1:0] sinp__28; +wire [32-1:0] sinp__29; +wire [32-1:0] sinp__30; +wire [32-1:0] sinp__31; +wire [32-1:0] sinp__32; +wire [32-1:0] sinp__33; +wire [32-1:0] sinp__34; +wire [32-1:0] sinp__35; +wire [32-1:0] sinp__36; +wire [32-1:0] sinp__37; + + +//wire [31:0] cosp[37:0]; + + +wire [32-1:0] cosp__0; +wire [32-1:0] cosp__1; +wire [32-1:0] cosp__2; +wire [32-1:0] cosp__3; +wire [32-1:0] cosp__4; +wire [32-1:0] cosp__5; +wire [32-1:0] cosp__6; +wire [32-1:0] cosp__7; +wire [32-1:0] cosp__8; +wire [32-1:0] cosp__9; +wire [32-1:0] cosp__10; +wire [32-1:0] cosp__11; +wire [32-1:0] cosp__12; +wire [32-1:0] cosp__13; +wire [32-1:0] cosp__14; +wire [32-1:0] cosp__15; +wire [32-1:0] cosp__16; +wire [32-1:0] cosp__17; +wire [32-1:0] cosp__18; +wire [32-1:0] cosp__19; +wire [32-1:0] cosp__20; +wire [32-1:0] cosp__21; +wire [32-1:0] cosp__22; +wire [32-1:0] cosp__23; +wire [32-1:0] cosp__24; +wire [32-1:0] cosp__25; +wire [32-1:0] cosp__26; +wire [32-1:0] cosp__27; +wire [32-1:0] cosp__28; +wire [32-1:0] cosp__29; +wire [32-1:0] cosp__30; +wire [32-1:0] cosp__31; +wire [32-1:0] cosp__32; +wire [32-1:0] cosp__33; +wire [32-1:0] cosp__34; +wire [32-1:0] cosp__35; +wire [32-1:0] cosp__36; +wire [32-1:0] cosp__37; + + +//wire [31:0] sintCosp[37:0]; + +wire [32-1:0] sintCosp__0; +wire [32-1:0] sintCosp__1; +wire [32-1:0] sintCosp__2; +wire [32-1:0] sintCosp__3; +wire [32-1:0] sintCosp__4; +wire [32-1:0] sintCosp__5; +wire [32-1:0] sintCosp__6; +wire [32-1:0] sintCosp__7; +wire [32-1:0] sintCosp__8; +wire [32-1:0] sintCosp__9; +wire [32-1:0] sintCosp__10; +wire [32-1:0] sintCosp__11; +wire [32-1:0] sintCosp__12; +wire [32-1:0] sintCosp__13; +wire [32-1:0] sintCosp__14; +wire [32-1:0] sintCosp__15; +wire [32-1:0] sintCosp__16; +wire [32-1:0] sintCosp__17; +wire [32-1:0] sintCosp__18; +wire [32-1:0] sintCosp__19; +wire [32-1:0] sintCosp__20; +wire [32-1:0] sintCosp__21; +wire [32-1:0] sintCosp__22; +wire [32-1:0] sintCosp__23; +wire [32-1:0] sintCosp__24; +wire [32-1:0] sintCosp__25; +wire [32-1:0] sintCosp__26; +wire [32-1:0] sintCosp__27; +wire [32-1:0] sintCosp__28; +wire [32-1:0] sintCosp__29; +wire [32-1:0] sintCosp__30; +wire [32-1:0] sintCosp__31; +wire [32-1:0] sintCosp__32; +wire [32-1:0] sintCosp__33; +wire [32-1:0] sintCosp__34; +wire [32-1:0] sintCosp__35; +wire [32-1:0] sintCosp__36; +wire [32-1:0] sintCosp__37; + + +//wire [31:0] sintSinp[37:0]; + + +wire [32-1:0] sintSinp__0; +wire [32-1:0] sintSinp__1; +wire [32-1:0] sintSinp__2; +wire [32-1:0] sintSinp__3; +wire [32-1:0] sintSinp__4; +wire [32-1:0] sintSinp__5; +wire [32-1:0] sintSinp__6; +wire [32-1:0] sintSinp__7; +wire [32-1:0] sintSinp__8; +wire [32-1:0] sintSinp__9; +wire [32-1:0] sintSinp__10; +wire [32-1:0] sintSinp__11; +wire [32-1:0] sintSinp__12; +wire [32-1:0] sintSinp__13; +wire [32-1:0] sintSinp__14; +wire [32-1:0] sintSinp__15; +wire [32-1:0] sintSinp__16; +wire [32-1:0] sintSinp__17; +wire [32-1:0] sintSinp__18; +wire [32-1:0] sintSinp__19; +wire [32-1:0] sintSinp__20; +wire [32-1:0] sintSinp__21; +wire [32-1:0] sintSinp__22; +wire [32-1:0] sintSinp__23; +wire [32-1:0] sintSinp__24; +wire [32-1:0] sintSinp__25; +wire [32-1:0] sintSinp__26; +wire [32-1:0] sintSinp__27; +wire [32-1:0] sintSinp__28; +wire [32-1:0] sintSinp__29; +wire [32-1:0] sintSinp__30; +wire [32-1:0] sintSinp__31; +wire [32-1:0] sintSinp__32; +wire [32-1:0] sintSinp__33; +wire [32-1:0] sintSinp__34; +wire [32-1:0] sintSinp__35; +wire [32-1:0] sintSinp__36; +wire [32-1:0] sintSinp__37; + + +//wire [63:0] uz2[37:0]; + + +wire [63:0] uz2__0; +wire [63:0] uz2__1; +wire [63:0] uz2__2; +wire [63:0] uz2__3; +wire [63:0] uz2__4; +wire [63:0] uz2__5; +wire [63:0] uz2__6; +wire [63:0] uz2__7; +wire [63:0] uz2__8; +wire [63:0] uz2__9; +wire [63:0] uz2__10; +wire [63:0] uz2__11; +wire [63:0] uz2__12; +wire [63:0] uz2__13; +wire [63:0] uz2__14; +wire [63:0] uz2__15; +wire [63:0] uz2__16; +wire [63:0] uz2__17; +wire [63:0] uz2__18; +wire [63:0] uz2__19; +wire [63:0] uz2__20; +wire [63:0] uz2__21; +wire [63:0] uz2__22; +wire [63:0] uz2__23; +wire [63:0] uz2__24; +wire [63:0] uz2__25; +wire [63:0] uz2__26; +wire [63:0] uz2__27; +wire [63:0] uz2__28; +wire [63:0] uz2__29; +wire [63:0] uz2__30; +wire [63:0] uz2__31; +wire [63:0] uz2__32; +wire [63:0] uz2__33; +wire [63:0] uz2__34; +wire [63:0] uz2__35; +wire [63:0] uz2__36; +wire [63:0] uz2__37; + + +//wire [31:0] uxUz[37:0]; + +wire [32-1:0] uxUz__0; +wire [32-1:0] uxUz__1; +wire [32-1:0] uxUz__2; +wire [32-1:0] uxUz__3; +wire [32-1:0] uxUz__4; +wire [32-1:0] uxUz__5; +wire [32-1:0] uxUz__6; +wire [32-1:0] uxUz__7; +wire [32-1:0] uxUz__8; +wire [32-1:0] uxUz__9; +wire [32-1:0] uxUz__10; +wire [32-1:0] uxUz__11; +wire [32-1:0] uxUz__12; +wire [32-1:0] uxUz__13; +wire [32-1:0] uxUz__14; +wire [32-1:0] uxUz__15; +wire [32-1:0] uxUz__16; +wire [32-1:0] uxUz__17; +wire [32-1:0] uxUz__18; +wire [32-1:0] uxUz__19; +wire [32-1:0] uxUz__20; +wire [32-1:0] uxUz__21; +wire [32-1:0] uxUz__22; +wire [32-1:0] uxUz__23; +wire [32-1:0] uxUz__24; +wire [32-1:0] uxUz__25; +wire [32-1:0] uxUz__26; +wire [32-1:0] uxUz__27; +wire [32-1:0] uxUz__28; +wire [32-1:0] uxUz__29; +wire [32-1:0] uxUz__30; +wire [32-1:0] uxUz__31; +wire [32-1:0] uxUz__32; +wire [32-1:0] uxUz__33; +wire [32-1:0] uxUz__34; +wire [32-1:0] uxUz__35; +wire [32-1:0] uxUz__36; +wire [32-1:0] uxUz__37; + + +//wire [31:0] uyUz[37:0]; + + +wire [32-1:0] uyUz__0; +wire [32-1:0] uyUz__1; +wire [32-1:0] uyUz__2; +wire [32-1:0] uyUz__3; +wire [32-1:0] uyUz__4; +wire [32-1:0] uyUz__5; +wire [32-1:0] uyUz__6; +wire [32-1:0] uyUz__7; +wire [32-1:0] uyUz__8; +wire [32-1:0] uyUz__9; +wire [32-1:0] uyUz__10; +wire [32-1:0] uyUz__11; +wire [32-1:0] uyUz__12; +wire [32-1:0] uyUz__13; +wire [32-1:0] uyUz__14; +wire [32-1:0] uyUz__15; +wire [32-1:0] uyUz__16; +wire [32-1:0] uyUz__17; +wire [32-1:0] uyUz__18; +wire [32-1:0] uyUz__19; +wire [32-1:0] uyUz__20; +wire [32-1:0] uyUz__21; +wire [32-1:0] uyUz__22; +wire [32-1:0] uyUz__23; +wire [32-1:0] uyUz__24; +wire [32-1:0] uyUz__25; +wire [32-1:0] uyUz__26; +wire [32-1:0] uyUz__27; +wire [32-1:0] uyUz__28; +wire [32-1:0] uyUz__29; +wire [32-1:0] uyUz__30; +wire [32-1:0] uyUz__31; +wire [32-1:0] uyUz__32; +wire [32-1:0] uyUz__33; +wire [32-1:0] uyUz__34; +wire [32-1:0] uyUz__35; +wire [32-1:0] uyUz__36; +wire [32-1:0] uyUz__37; + +//wire [31:0] uySintSinp[37:0]; + + +wire [32-1:0] uySintSinp__0; +wire [32-1:0] uySintSinp__1; +wire [32-1:0] uySintSinp__2; +wire [32-1:0] uySintSinp__3; +wire [32-1:0] uySintSinp__4; +wire [32-1:0] uySintSinp__5; +wire [32-1:0] uySintSinp__6; +wire [32-1:0] uySintSinp__7; +wire [32-1:0] uySintSinp__8; +wire [32-1:0] uySintSinp__9; +wire [32-1:0] uySintSinp__10; +wire [32-1:0] uySintSinp__11; +wire [32-1:0] uySintSinp__12; +wire [32-1:0] uySintSinp__13; +wire [32-1:0] uySintSinp__14; +wire [32-1:0] uySintSinp__15; +wire [32-1:0] uySintSinp__16; +wire [32-1:0] uySintSinp__17; +wire [32-1:0] uySintSinp__18; +wire [32-1:0] uySintSinp__19; +wire [32-1:0] uySintSinp__20; +wire [32-1:0] uySintSinp__21; +wire [32-1:0] uySintSinp__22; +wire [32-1:0] uySintSinp__23; +wire [32-1:0] uySintSinp__24; +wire [32-1:0] uySintSinp__25; +wire [32-1:0] uySintSinp__26; +wire [32-1:0] uySintSinp__27; +wire [32-1:0] uySintSinp__28; +wire [32-1:0] uySintSinp__29; +wire [32-1:0] uySintSinp__30; +wire [32-1:0] uySintSinp__31; +wire [32-1:0] uySintSinp__32; +wire [32-1:0] uySintSinp__33; +wire [32-1:0] uySintSinp__34; +wire [32-1:0] uySintSinp__35; +wire [32-1:0] uySintSinp__36; +wire [32-1:0] uySintSinp__37; + + +//wire [63:0] oneMinusUz2[37:0]; + + +wire [63:0] oneMinusUz2__0; +wire [63:0] oneMinusUz2__1; +wire [63:0] oneMinusUz2__2; +wire [63:0] oneMinusUz2__3; +wire [63:0] oneMinusUz2__4; +wire [63:0] oneMinusUz2__5; +wire [63:0] oneMinusUz2__6; +wire [63:0] oneMinusUz2__7; +wire [63:0] oneMinusUz2__8; +wire [63:0] oneMinusUz2__9; +wire [63:0] oneMinusUz2__10; +wire [63:0] oneMinusUz2__11; +wire [63:0] oneMinusUz2__12; +wire [63:0] oneMinusUz2__13; +wire [63:0] oneMinusUz2__14; +wire [63:0] oneMinusUz2__15; +wire [63:0] oneMinusUz2__16; +wire [63:0] oneMinusUz2__17; +wire [63:0] oneMinusUz2__18; +wire [63:0] oneMinusUz2__19; +wire [63:0] oneMinusUz2__20; +wire [63:0] oneMinusUz2__21; +wire [63:0] oneMinusUz2__22; +wire [63:0] oneMinusUz2__23; +wire [63:0] oneMinusUz2__24; +wire [63:0] oneMinusUz2__25; +wire [63:0] oneMinusUz2__26; +wire [63:0] oneMinusUz2__27; +wire [63:0] oneMinusUz2__28; +wire [63:0] oneMinusUz2__29; +wire [63:0] oneMinusUz2__30; +wire [63:0] oneMinusUz2__31; +wire [63:0] oneMinusUz2__32; +wire [63:0] oneMinusUz2__33; +wire [63:0] oneMinusUz2__34; +wire [63:0] oneMinusUz2__35; +wire [63:0] oneMinusUz2__36; +wire [63:0] oneMinusUz2__37; + + +//wire [31:0] uyUzSintCosp[37:0]; + + +wire [32-1:0] uyUzSintCosp__0; +wire [32-1:0] uyUzSintCosp__1; +wire [32-1:0] uyUzSintCosp__2; +wire [32-1:0] uyUzSintCosp__3; +wire [32-1:0] uyUzSintCosp__4; +wire [32-1:0] uyUzSintCosp__5; +wire [32-1:0] uyUzSintCosp__6; +wire [32-1:0] uyUzSintCosp__7; +wire [32-1:0] uyUzSintCosp__8; +wire [32-1:0] uyUzSintCosp__9; +wire [32-1:0] uyUzSintCosp__10; +wire [32-1:0] uyUzSintCosp__11; +wire [32-1:0] uyUzSintCosp__12; +wire [32-1:0] uyUzSintCosp__13; +wire [32-1:0] uyUzSintCosp__14; +wire [32-1:0] uyUzSintCosp__15; +wire [32-1:0] uyUzSintCosp__16; +wire [32-1:0] uyUzSintCosp__17; +wire [32-1:0] uyUzSintCosp__18; +wire [32-1:0] uyUzSintCosp__19; +wire [32-1:0] uyUzSintCosp__20; +wire [32-1:0] uyUzSintCosp__21; +wire [32-1:0] uyUzSintCosp__22; +wire [32-1:0] uyUzSintCosp__23; +wire [32-1:0] uyUzSintCosp__24; +wire [32-1:0] uyUzSintCosp__25; +wire [32-1:0] uyUzSintCosp__26; +wire [32-1:0] uyUzSintCosp__27; +wire [32-1:0] uyUzSintCosp__28; +wire [32-1:0] uyUzSintCosp__29; +wire [32-1:0] uyUzSintCosp__30; +wire [32-1:0] uyUzSintCosp__31; +wire [32-1:0] uyUzSintCosp__32; +wire [32-1:0] uyUzSintCosp__33; +wire [32-1:0] uyUzSintCosp__34; +wire [32-1:0] uyUzSintCosp__35; +wire [32-1:0] uyUzSintCosp__36; +wire [32-1:0] uyUzSintCosp__37; + + +//wire [31:0] uxUzSintCosp[37:0]; + + +wire [32-1:0] uxUzSintCosp__0; +wire [32-1:0] uxUzSintCosp__1; +wire [32-1:0] uxUzSintCosp__2; +wire [32-1:0] uxUzSintCosp__3; +wire [32-1:0] uxUzSintCosp__4; +wire [32-1:0] uxUzSintCosp__5; +wire [32-1:0] uxUzSintCosp__6; +wire [32-1:0] uxUzSintCosp__7; +wire [32-1:0] uxUzSintCosp__8; +wire [32-1:0] uxUzSintCosp__9; +wire [32-1:0] uxUzSintCosp__10; +wire [32-1:0] uxUzSintCosp__11; +wire [32-1:0] uxUzSintCosp__12; +wire [32-1:0] uxUzSintCosp__13; +wire [32-1:0] uxUzSintCosp__14; +wire [32-1:0] uxUzSintCosp__15; +wire [32-1:0] uxUzSintCosp__16; +wire [32-1:0] uxUzSintCosp__17; +wire [32-1:0] uxUzSintCosp__18; +wire [32-1:0] uxUzSintCosp__19; +wire [32-1:0] uxUzSintCosp__20; +wire [32-1:0] uxUzSintCosp__21; +wire [32-1:0] uxUzSintCosp__22; +wire [32-1:0] uxUzSintCosp__23; +wire [32-1:0] uxUzSintCosp__24; +wire [32-1:0] uxUzSintCosp__25; +wire [32-1:0] uxUzSintCosp__26; +wire [32-1:0] uxUzSintCosp__27; +wire [32-1:0] uxUzSintCosp__28; +wire [32-1:0] uxUzSintCosp__29; +wire [32-1:0] uxUzSintCosp__30; +wire [32-1:0] uxUzSintCosp__31; +wire [32-1:0] uxUzSintCosp__32; +wire [32-1:0] uxUzSintCosp__33; +wire [32-1:0] uxUzSintCosp__34; +wire [32-1:0] uxUzSintCosp__35; +wire [32-1:0] uxUzSintCosp__36; +wire [32-1:0] uxUzSintCosp__37; + + +//wire [31:0] uxSintSinp[37:0]; + +wire [32-1:0] uxSintSinp__0; +wire [32-1:0] uxSintSinp__1; +wire [32-1:0] uxSintSinp__2; +wire [32-1:0] uxSintSinp__3; +wire [32-1:0] uxSintSinp__4; +wire [32-1:0] uxSintSinp__5; +wire [32-1:0] uxSintSinp__6; +wire [32-1:0] uxSintSinp__7; +wire [32-1:0] uxSintSinp__8; +wire [32-1:0] uxSintSinp__9; +wire [32-1:0] uxSintSinp__10; +wire [32-1:0] uxSintSinp__11; +wire [32-1:0] uxSintSinp__12; +wire [32-1:0] uxSintSinp__13; +wire [32-1:0] uxSintSinp__14; +wire [32-1:0] uxSintSinp__15; +wire [32-1:0] uxSintSinp__16; +wire [32-1:0] uxSintSinp__17; +wire [32-1:0] uxSintSinp__18; +wire [32-1:0] uxSintSinp__19; +wire [32-1:0] uxSintSinp__20; +wire [32-1:0] uxSintSinp__21; +wire [32-1:0] uxSintSinp__22; +wire [32-1:0] uxSintSinp__23; +wire [32-1:0] uxSintSinp__24; +wire [32-1:0] uxSintSinp__25; +wire [32-1:0] uxSintSinp__26; +wire [32-1:0] uxSintSinp__27; +wire [32-1:0] uxSintSinp__28; +wire [32-1:0] uxSintSinp__29; +wire [32-1:0] uxSintSinp__30; +wire [32-1:0] uxSintSinp__31; +wire [32-1:0] uxSintSinp__32; +wire [32-1:0] uxSintSinp__33; +wire [32-1:0] uxSintSinp__34; +wire [32-1:0] uxSintSinp__35; +wire [32-1:0] uxSintSinp__36; +wire [32-1:0] uxSintSinp__37; + + +//wire [31:0] sqrtOneMinusUz2[37:0]; + +wire [32-1:0] sqrtOneMinusUz2__0; +wire [32-1:0] sqrtOneMinusUz2__1; +wire [32-1:0] sqrtOneMinusUz2__2; +wire [32-1:0] sqrtOneMinusUz2__3; +wire [32-1:0] sqrtOneMinusUz2__4; +wire [32-1:0] sqrtOneMinusUz2__5; +wire [32-1:0] sqrtOneMinusUz2__6; +wire [32-1:0] sqrtOneMinusUz2__7; +wire [32-1:0] sqrtOneMinusUz2__8; +wire [32-1:0] sqrtOneMinusUz2__9; +wire [32-1:0] sqrtOneMinusUz2__10; +wire [32-1:0] sqrtOneMinusUz2__11; +wire [32-1:0] sqrtOneMinusUz2__12; +wire [32-1:0] sqrtOneMinusUz2__13; +wire [32-1:0] sqrtOneMinusUz2__14; +wire [32-1:0] sqrtOneMinusUz2__15; +wire [32-1:0] sqrtOneMinusUz2__16; +wire [32-1:0] sqrtOneMinusUz2__17; +wire [32-1:0] sqrtOneMinusUz2__18; +wire [32-1:0] sqrtOneMinusUz2__19; +wire [32-1:0] sqrtOneMinusUz2__20; +wire [32-1:0] sqrtOneMinusUz2__21; +wire [32-1:0] sqrtOneMinusUz2__22; +wire [32-1:0] sqrtOneMinusUz2__23; +wire [32-1:0] sqrtOneMinusUz2__24; +wire [32-1:0] sqrtOneMinusUz2__25; +wire [32-1:0] sqrtOneMinusUz2__26; +wire [32-1:0] sqrtOneMinusUz2__27; +wire [32-1:0] sqrtOneMinusUz2__28; +wire [32-1:0] sqrtOneMinusUz2__29; +wire [32-1:0] sqrtOneMinusUz2__30; +wire [32-1:0] sqrtOneMinusUz2__31; +wire [32-1:0] sqrtOneMinusUz2__32; +wire [32-1:0] sqrtOneMinusUz2__33; +wire [32-1:0] sqrtOneMinusUz2__34; +wire [32-1:0] sqrtOneMinusUz2__35; +wire [32-1:0] sqrtOneMinusUz2__36; +wire [32-1:0] sqrtOneMinusUz2__37; + +//wire [31:0] sintCospSqrtOneMinusUz2[37:0]; + + +wire [32-1:0] sintCospSqrtOneMinusUz2__0; +wire [32-1:0] sintCospSqrtOneMinusUz2__1; +wire [32-1:0] sintCospSqrtOneMinusUz2__2; +wire [32-1:0] sintCospSqrtOneMinusUz2__3; +wire [32-1:0] sintCospSqrtOneMinusUz2__4; +wire [32-1:0] sintCospSqrtOneMinusUz2__5; +wire [32-1:0] sintCospSqrtOneMinusUz2__6; +wire [32-1:0] sintCospSqrtOneMinusUz2__7; +wire [32-1:0] sintCospSqrtOneMinusUz2__8; +wire [32-1:0] sintCospSqrtOneMinusUz2__9; +wire [32-1:0] sintCospSqrtOneMinusUz2__10; +wire [32-1:0] sintCospSqrtOneMinusUz2__11; +wire [32-1:0] sintCospSqrtOneMinusUz2__12; +wire [32-1:0] sintCospSqrtOneMinusUz2__13; +wire [32-1:0] sintCospSqrtOneMinusUz2__14; +wire [32-1:0] sintCospSqrtOneMinusUz2__15; +wire [32-1:0] sintCospSqrtOneMinusUz2__16; +wire [32-1:0] sintCospSqrtOneMinusUz2__17; +wire [32-1:0] sintCospSqrtOneMinusUz2__18; +wire [32-1:0] sintCospSqrtOneMinusUz2__19; +wire [32-1:0] sintCospSqrtOneMinusUz2__20; +wire [32-1:0] sintCospSqrtOneMinusUz2__21; +wire [32-1:0] sintCospSqrtOneMinusUz2__22; +wire [32-1:0] sintCospSqrtOneMinusUz2__23; +wire [32-1:0] sintCospSqrtOneMinusUz2__24; +wire [32-1:0] sintCospSqrtOneMinusUz2__25; +wire [32-1:0] sintCospSqrtOneMinusUz2__26; +wire [32-1:0] sintCospSqrtOneMinusUz2__27; +wire [32-1:0] sintCospSqrtOneMinusUz2__28; +wire [32-1:0] sintCospSqrtOneMinusUz2__29; +wire [32-1:0] sintCospSqrtOneMinusUz2__30; +wire [32-1:0] sintCospSqrtOneMinusUz2__31; +wire [32-1:0] sintCospSqrtOneMinusUz2__32; +wire [32-1:0] sintCospSqrtOneMinusUz2__33; +wire [32-1:0] sintCospSqrtOneMinusUz2__34; +wire [32-1:0] sintCospSqrtOneMinusUz2__35; +wire [32-1:0] sintCospSqrtOneMinusUz2__36; +wire [32-1:0] sintCospSqrtOneMinusUz2__37; + +//wire [31:0] uxCost[37:0]; + + +wire [32-1:0] uxCost__0; +wire [32-1:0] uxCost__1; +wire [32-1:0] uxCost__2; +wire [32-1:0] uxCost__3; +wire [32-1:0] uxCost__4; +wire [32-1:0] uxCost__5; +wire [32-1:0] uxCost__6; +wire [32-1:0] uxCost__7; +wire [32-1:0] uxCost__8; +wire [32-1:0] uxCost__9; +wire [32-1:0] uxCost__10; +wire [32-1:0] uxCost__11; +wire [32-1:0] uxCost__12; +wire [32-1:0] uxCost__13; +wire [32-1:0] uxCost__14; +wire [32-1:0] uxCost__15; +wire [32-1:0] uxCost__16; +wire [32-1:0] uxCost__17; +wire [32-1:0] uxCost__18; +wire [32-1:0] uxCost__19; +wire [32-1:0] uxCost__20; +wire [32-1:0] uxCost__21; +wire [32-1:0] uxCost__22; +wire [32-1:0] uxCost__23; +wire [32-1:0] uxCost__24; +wire [32-1:0] uxCost__25; +wire [32-1:0] uxCost__26; +wire [32-1:0] uxCost__27; +wire [32-1:0] uxCost__28; +wire [32-1:0] uxCost__29; +wire [32-1:0] uxCost__30; +wire [32-1:0] uxCost__31; +wire [32-1:0] uxCost__32; +wire [32-1:0] uxCost__33; +wire [32-1:0] uxCost__34; +wire [32-1:0] uxCost__35; +wire [32-1:0] uxCost__36; +wire [32-1:0] uxCost__37; + +//wire [31:0] uzCost[37:0]; + + +wire [32-1:0] uzCost__0; +wire [32-1:0] uzCost__1; +wire [32-1:0] uzCost__2; +wire [32-1:0] uzCost__3; +wire [32-1:0] uzCost__4; +wire [32-1:0] uzCost__5; +wire [32-1:0] uzCost__6; +wire [32-1:0] uzCost__7; +wire [32-1:0] uzCost__8; +wire [32-1:0] uzCost__9; +wire [32-1:0] uzCost__10; +wire [32-1:0] uzCost__11; +wire [32-1:0] uzCost__12; +wire [32-1:0] uzCost__13; +wire [32-1:0] uzCost__14; +wire [32-1:0] uzCost__15; +wire [32-1:0] uzCost__16; +wire [32-1:0] uzCost__17; +wire [32-1:0] uzCost__18; +wire [32-1:0] uzCost__19; +wire [32-1:0] uzCost__20; +wire [32-1:0] uzCost__21; +wire [32-1:0] uzCost__22; +wire [32-1:0] uzCost__23; +wire [32-1:0] uzCost__24; +wire [32-1:0] uzCost__25; +wire [32-1:0] uzCost__26; +wire [32-1:0] uzCost__27; +wire [32-1:0] uzCost__28; +wire [32-1:0] uzCost__29; +wire [32-1:0] uzCost__30; +wire [32-1:0] uzCost__31; +wire [32-1:0] uzCost__32; +wire [32-1:0] uzCost__33; +wire [32-1:0] uzCost__34; +wire [32-1:0] uzCost__35; +wire [32-1:0] uzCost__36; +wire [32-1:0] uzCost__37; + + +//wire [31:0] sqrtOneMinusUz2_inv[37:0]; + + +wire [32-1:0] sqrtOneMinusUz2_inv__0; +wire [32-1:0] sqrtOneMinusUz2_inv__1; +wire [32-1:0] sqrtOneMinusUz2_inv__2; +wire [32-1:0] sqrtOneMinusUz2_inv__3; +wire [32-1:0] sqrtOneMinusUz2_inv__4; +wire [32-1:0] sqrtOneMinusUz2_inv__5; +wire [32-1:0] sqrtOneMinusUz2_inv__6; +wire [32-1:0] sqrtOneMinusUz2_inv__7; +wire [32-1:0] sqrtOneMinusUz2_inv__8; +wire [32-1:0] sqrtOneMinusUz2_inv__9; +wire [32-1:0] sqrtOneMinusUz2_inv__10; +wire [32-1:0] sqrtOneMinusUz2_inv__11; +wire [32-1:0] sqrtOneMinusUz2_inv__12; +wire [32-1:0] sqrtOneMinusUz2_inv__13; +wire [32-1:0] sqrtOneMinusUz2_inv__14; +wire [32-1:0] sqrtOneMinusUz2_inv__15; +wire [32-1:0] sqrtOneMinusUz2_inv__16; +wire [32-1:0] sqrtOneMinusUz2_inv__17; +wire [32-1:0] sqrtOneMinusUz2_inv__18; +wire [32-1:0] sqrtOneMinusUz2_inv__19; +wire [32-1:0] sqrtOneMinusUz2_inv__20; +wire [32-1:0] sqrtOneMinusUz2_inv__21; +wire [32-1:0] sqrtOneMinusUz2_inv__22; +wire [32-1:0] sqrtOneMinusUz2_inv__23; +wire [32-1:0] sqrtOneMinusUz2_inv__24; +wire [32-1:0] sqrtOneMinusUz2_inv__25; +wire [32-1:0] sqrtOneMinusUz2_inv__26; +wire [32-1:0] sqrtOneMinusUz2_inv__27; +wire [32-1:0] sqrtOneMinusUz2_inv__28; +wire [32-1:0] sqrtOneMinusUz2_inv__29; +wire [32-1:0] sqrtOneMinusUz2_inv__30; +wire [32-1:0] sqrtOneMinusUz2_inv__31; +wire [32-1:0] sqrtOneMinusUz2_inv__32; +wire [32-1:0] sqrtOneMinusUz2_inv__33; +wire [32-1:0] sqrtOneMinusUz2_inv__34; +wire [32-1:0] sqrtOneMinusUz2_inv__35; +wire [32-1:0] sqrtOneMinusUz2_inv__36; +wire [32-1:0] sqrtOneMinusUz2_inv__37; + +//wire [31:0] uxNumerator[37:0]; + + +wire [32-1:0] uxNumerator__0; +wire [32-1:0] uxNumerator__1; +wire [32-1:0] uxNumerator__2; +wire [32-1:0] uxNumerator__3; +wire [32-1:0] uxNumerator__4; +wire [32-1:0] uxNumerator__5; +wire [32-1:0] uxNumerator__6; +wire [32-1:0] uxNumerator__7; +wire [32-1:0] uxNumerator__8; +wire [32-1:0] uxNumerator__9; +wire [32-1:0] uxNumerator__10; +wire [32-1:0] uxNumerator__11; +wire [32-1:0] uxNumerator__12; +wire [32-1:0] uxNumerator__13; +wire [32-1:0] uxNumerator__14; +wire [32-1:0] uxNumerator__15; +wire [32-1:0] uxNumerator__16; +wire [32-1:0] uxNumerator__17; +wire [32-1:0] uxNumerator__18; +wire [32-1:0] uxNumerator__19; +wire [32-1:0] uxNumerator__20; +wire [32-1:0] uxNumerator__21; +wire [32-1:0] uxNumerator__22; +wire [32-1:0] uxNumerator__23; +wire [32-1:0] uxNumerator__24; +wire [32-1:0] uxNumerator__25; +wire [32-1:0] uxNumerator__26; +wire [32-1:0] uxNumerator__27; +wire [32-1:0] uxNumerator__28; +wire [32-1:0] uxNumerator__29; +wire [32-1:0] uxNumerator__30; +wire [32-1:0] uxNumerator__31; +wire [32-1:0] uxNumerator__32; +wire [32-1:0] uxNumerator__33; +wire [32-1:0] uxNumerator__34; +wire [32-1:0] uxNumerator__35; +wire [32-1:0] uxNumerator__36; +wire [32-1:0] uxNumerator__37; + +//wire [31:0] uyNumerator[37:0]; + + +wire [32-1:0] uyNumerator__0; +wire [32-1:0] uyNumerator__1; +wire [32-1:0] uyNumerator__2; +wire [32-1:0] uyNumerator__3; +wire [32-1:0] uyNumerator__4; +wire [32-1:0] uyNumerator__5; +wire [32-1:0] uyNumerator__6; +wire [32-1:0] uyNumerator__7; +wire [32-1:0] uyNumerator__8; +wire [32-1:0] uyNumerator__9; +wire [32-1:0] uyNumerator__10; +wire [32-1:0] uyNumerator__11; +wire [32-1:0] uyNumerator__12; +wire [32-1:0] uyNumerator__13; +wire [32-1:0] uyNumerator__14; +wire [32-1:0] uyNumerator__15; +wire [32-1:0] uyNumerator__16; +wire [32-1:0] uyNumerator__17; +wire [32-1:0] uyNumerator__18; +wire [32-1:0] uyNumerator__19; +wire [32-1:0] uyNumerator__20; +wire [32-1:0] uyNumerator__21; +wire [32-1:0] uyNumerator__22; +wire [32-1:0] uyNumerator__23; +wire [32-1:0] uyNumerator__24; +wire [32-1:0] uyNumerator__25; +wire [32-1:0] uyNumerator__26; +wire [32-1:0] uyNumerator__27; +wire [32-1:0] uyNumerator__28; +wire [32-1:0] uyNumerator__29; +wire [32-1:0] uyNumerator__30; +wire [32-1:0] uyNumerator__31; +wire [32-1:0] uyNumerator__32; +wire [32-1:0] uyNumerator__33; +wire [32-1:0] uyNumerator__34; +wire [32-1:0] uyNumerator__35; +wire [32-1:0] uyNumerator__36; +wire [32-1:0] uyNumerator__37; + +//wire [31:0] uyCost[37:0]; + + +wire [32-1:0] uyCost__0; +wire [32-1:0] uyCost__1; +wire [32-1:0] uyCost__2; +wire [32-1:0] uyCost__3; +wire [32-1:0] uyCost__4; +wire [32-1:0] uyCost__5; +wire [32-1:0] uyCost__6; +wire [32-1:0] uyCost__7; +wire [32-1:0] uyCost__8; +wire [32-1:0] uyCost__9; +wire [32-1:0] uyCost__10; +wire [32-1:0] uyCost__11; +wire [32-1:0] uyCost__12; +wire [32-1:0] uyCost__13; +wire [32-1:0] uyCost__14; +wire [32-1:0] uyCost__15; +wire [32-1:0] uyCost__16; +wire [32-1:0] uyCost__17; +wire [32-1:0] uyCost__18; +wire [32-1:0] uyCost__19; +wire [32-1:0] uyCost__20; +wire [32-1:0] uyCost__21; +wire [32-1:0] uyCost__22; +wire [32-1:0] uyCost__23; +wire [32-1:0] uyCost__24; +wire [32-1:0] uyCost__25; +wire [32-1:0] uyCost__26; +wire [32-1:0] uyCost__27; +wire [32-1:0] uyCost__28; +wire [32-1:0] uyCost__29; +wire [32-1:0] uyCost__30; +wire [32-1:0] uyCost__31; +wire [32-1:0] uyCost__32; +wire [32-1:0] uyCost__33; +wire [32-1:0] uyCost__34; +wire [32-1:0] uyCost__35; +wire [32-1:0] uyCost__36; +wire [32-1:0] uyCost__37; + +//wire [31:0] uxQuotient[37:0]; + + +wire [32-1:0] uxQuotient__0; +wire [32-1:0] uxQuotient__1; +wire [32-1:0] uxQuotient__2; +wire [32-1:0] uxQuotient__3; +wire [32-1:0] uxQuotient__4; +wire [32-1:0] uxQuotient__5; +wire [32-1:0] uxQuotient__6; +wire [32-1:0] uxQuotient__7; +wire [32-1:0] uxQuotient__8; +wire [32-1:0] uxQuotient__9; +wire [32-1:0] uxQuotient__10; +wire [32-1:0] uxQuotient__11; +wire [32-1:0] uxQuotient__12; +wire [32-1:0] uxQuotient__13; +wire [32-1:0] uxQuotient__14; +wire [32-1:0] uxQuotient__15; +wire [32-1:0] uxQuotient__16; +wire [32-1:0] uxQuotient__17; +wire [32-1:0] uxQuotient__18; +wire [32-1:0] uxQuotient__19; +wire [32-1:0] uxQuotient__20; +wire [32-1:0] uxQuotient__21; +wire [32-1:0] uxQuotient__22; +wire [32-1:0] uxQuotient__23; +wire [32-1:0] uxQuotient__24; +wire [32-1:0] uxQuotient__25; +wire [32-1:0] uxQuotient__26; +wire [32-1:0] uxQuotient__27; +wire [32-1:0] uxQuotient__28; +wire [32-1:0] uxQuotient__29; +wire [32-1:0] uxQuotient__30; +wire [32-1:0] uxQuotient__31; +wire [32-1:0] uxQuotient__32; +wire [32-1:0] uxQuotient__33; +wire [32-1:0] uxQuotient__34; +wire [32-1:0] uxQuotient__35; +wire [32-1:0] uxQuotient__36; +wire [32-1:0] uxQuotient__37; + +//wire [31:0] uyQuotient[37:0]; + + +wire [32-1:0] uyQuotient__0; +wire [32-1:0] uyQuotient__1; +wire [32-1:0] uyQuotient__2; +wire [32-1:0] uyQuotient__3; +wire [32-1:0] uyQuotient__4; +wire [32-1:0] uyQuotient__5; +wire [32-1:0] uyQuotient__6; +wire [32-1:0] uyQuotient__7; +wire [32-1:0] uyQuotient__8; +wire [32-1:0] uyQuotient__9; +wire [32-1:0] uyQuotient__10; +wire [32-1:0] uyQuotient__11; +wire [32-1:0] uyQuotient__12; +wire [32-1:0] uyQuotient__13; +wire [32-1:0] uyQuotient__14; +wire [32-1:0] uyQuotient__15; +wire [32-1:0] uyQuotient__16; +wire [32-1:0] uyQuotient__17; +wire [32-1:0] uyQuotient__18; +wire [32-1:0] uyQuotient__19; +wire [32-1:0] uyQuotient__20; +wire [32-1:0] uyQuotient__21; +wire [32-1:0] uyQuotient__22; +wire [32-1:0] uyQuotient__23; +wire [32-1:0] uyQuotient__24; +wire [32-1:0] uyQuotient__25; +wire [32-1:0] uyQuotient__26; +wire [32-1:0] uyQuotient__27; +wire [32-1:0] uyQuotient__28; +wire [32-1:0] uyQuotient__29; +wire [32-1:0] uyQuotient__30; +wire [32-1:0] uyQuotient__31; +wire [32-1:0] uyQuotient__32; +wire [32-1:0] uyQuotient__33; +wire [32-1:0] uyQuotient__34; +wire [32-1:0] uyQuotient__35; +wire [32-1:0] uyQuotient__36; +wire [32-1:0] uyQuotient__37; + +wire [31:0] new_sint; +wire [31:0] new_cost; +wire [31:0] new_sinp; +wire [31:0] new_cosp; +wire [31:0] new_sintCosp; +wire [31:0] new_sintSinp; +wire [63:0] new_uz2; +wire [31:0] new_uxUz; +wire [31:0] new_uyUz; +wire [31:0] new_uySintSinp; +wire [63:0] new_oneMinusUz2; +wire [31:0] new_uyUzSintCosp; +wire [31:0] new_uxUzSintCosp; +wire [31:0] new_uxSintSinp; +wire [31:0] new_sqrtOneMinusUz2; +wire [31:0] new_sintCospSqrtOneMinusUz2; +wire [31:0] new_uxCost; +wire [31:0] new_uzCost; +wire [31:0] new_sqrtOneMinusUz2_inv; +wire [31:0] new_uxNumerator; +wire [31:0] new_uyNumerator; +wire [31:0] new_uyCost; +reg [31:0] new_uxQuotient; +reg [31:0] new_uyQuotient; + + +//Wiring for calculating final values +wire uxNumerOverflow; +wire uyNumerOverflow; +reg normalIncident; +wire [31:0] ux_add_1; +wire [31:0] ux_add_2; +wire uxOverflow; +wire [31:0] uy_add_1; +wire [31:0] uy_add_2; +wire uyOverflow; +wire [31:0] normalUz; +wire [31:0] uz_sub_1; +wire [31:0] uz_sub_2; +wire uzOverflow; + +wire [31:0] new_ux; +wire [31:0] new_uy; +wire [31:0] new_uz; + +wire div_overflow; +wire toAnd1_36_1; +wire toAnd1_36_2; +wire overflow1_36; +wire negOverflow1_36; +wire toAnd2_36_1; +wire toAnd2_36_2; +wire overflow2_36; +wire negOverflow2_36; + + + +//------------------Register Pipeline----------------- +//Generation Methodology: Standard block, called InternalsBlock, is +//repeated multiple times, based on the latency of the reflector and +//scatterer. This block contains the list of all internal variables +//that need to be registered and passed along in the pipeline. +// +//Previous values in the pipeline are passed to the next register on each +//clock tick. The exception comes when an internal variable gets +//calculated. Each time a new internal variable is calculated, a new +//case is added to the case statement, and instead of hooking previous +//values of that variable to next, the new, calculated values are hooked up. +// +//This method will generate many more registers than what are required, but +//it is expected that the synthesis tool will synthesize these away. +// +// +//Commenting Convention: Whenever a new value is injected into the pipe, the +//comment //Changed Value is added directly above the variable in question. +//When multiple values are calculated in a single clock cycle, multiple such +//comments are placed. Wires connected to "Changed Values" always start with +//the prefix new_. +// +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=`LAT; i>0; i=i-1) begin: internalPipe +// case(i) +// +// 2: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// //Changed Value +// .i_uz2(new_uz2), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// 3: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// //Changed Value +// .i_oneMinusUz2(new_oneMinusUz2), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// 4: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// //Changed Value +// .i_uxUz(new_uxUz), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// (`SQRT+6): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// //Changed Value +// .i_sqrtOneMinusUz2(new_sqrtOneMinusUz2), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+3): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// //Changed Value +// .i_sint(new_sint), +// //Changed Value +// .i_cost(new_cost), +// //Changed Value +// .i_sinp(new_sinp), +// //Changed Value +// .i_cosp(new_cosp), +// //Changed Value +// .i_sintCosp(new_sintCosp), +// //Changed Value +// .i_sintSinp(new_sintSinp), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// //Changed Value +// .i_uyUz(new_uyUz), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+4): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// //Changed Value +// .i_uySintSinp(new_uySintSinp), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// //Changed Value +// .i_uyUzSintCosp(new_uyUzSintCosp), +// //Changed Value +// .i_uxUzSintCosp(new_uxUzSintCosp), +// //Changed Value +// .i_uxSintSinp(new_uxSintSinp), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+5): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// //Changed Value +// .i_sqrtOneMinusUz2_inv(new_sqrtOneMinusUz2_inv), +// //Changed Value +// .i_uxNumerator(new_uxNumerator), +// //Changed Value +// .i_uyNumerator(new_uyNumerator), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+6): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// //Changed Value +// .i_sintCospSqrtOneMinusUz2(new_sintCospSqrtOneMinusUz2), +// //Changed Value +// .i_uxCost(new_uxCost), +// //Changed Value +// .i_uzCost(new_uzCost), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// //Changed Value +// .i_uyCost(new_uyCost), +// //Changed Value +// .i_uxQuotient(new_uxQuotient), +// //Changed Value +// .i_uyQuotient(new_uyQuotient), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// default: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// endcase +// end +//endgenerate + +//Expanded generate loop: +//special cases first + //forloop2 + InternalsBlock pipeReg2( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_sint(sint__1), + .i_cost(cost__1), + .i_sinp(sinp__1), + .i_cosp(cosp__1), + .i_sintCosp(sintCosp__1), + .i_sintSinp(sintSinp__1), + //Changed Value + .i_uz2(new_uz2), + .i_uxUz(uxUz__1), + .i_uyUz(uyUz__1), + .i_uySintSinp(uySintSinp__1), + .i_oneMinusUz2(oneMinusUz2__1), + .i_uyUzSintCosp(uyUzSintCosp__1), + .i_uxUzSintCosp(uxUzSintCosp__1), + .i_uxSintSinp(uxSintSinp__1), + .i_sqrtOneMinusUz2(sqrtOneMinusUz2__1), + .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__1), + .i_uxCost(uxCost__1), + .i_uzCost(uzCost__1), + .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__1), + .i_uxNumerator(uxNumerator__1), + .i_uyNumerator(uyNumerator__1), + .i_uyCost(uyCost__1), + .i_uxQuotient(uxQuotient__1), + .i_uyQuotient(uyQuotient__1), + + //Outputs + .o_sint(sint__2), + .o_cost(cost__2), + .o_sinp(sinp__2), + .o_cosp(cosp__2), + .o_sintCosp(sintCosp__2), + .o_sintSinp(sintSinp__2), + .o_uz2(uz2__2), + .o_uxUz(uxUz__2), + .o_uyUz(uyUz__2), + .o_uySintSinp(uySintSinp__2), + .o_oneMinusUz2(oneMinusUz2__2), + .o_uyUzSintCosp(uyUzSintCosp__2), + .o_uxUzSintCosp(uxUzSintCosp__2), + .o_uxSintSinp(uxSintSinp__2), + .o_sqrtOneMinusUz2(sqrtOneMinusUz2__2), + .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__2), + .o_uxCost(uxCost__2), + .o_uzCost(uzCost__2), + .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__2), + .o_uxNumerator(uxNumerator__2), + .o_uyNumerator(uyNumerator__2), + .o_uyCost(uyCost__2), + .o_uxQuotient(uxQuotient__2), + .o_uyQuotient(uyQuotient__2) + ); + + + // forloop3 + InternalsBlock pipeReg3( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__2), +.i_cost(cost__2), +.i_sinp(sinp__2), +.i_cosp(cosp__2), +.i_sintCosp(sintCosp__2), +.i_sintSinp(sintSinp__2), +.i_uz2(uz2__2), +.i_uxUz(uxUz__2), +.i_uyUz(uyUz__2), +.i_uySintSinp(uySintSinp__2), +//changed +.i_oneMinusUz2(new_oneMinusUz2), +.i_uyUzSintCosp(uyUzSintCosp__2), +.i_uxUzSintCosp(uxUzSintCosp__2), +.i_uxSintSinp(uxSintSinp__2), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__2), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__2), +.i_uxCost(uxCost__2), +.i_uzCost(uzCost__2), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__2), +.i_uxNumerator(uxNumerator__2), +.i_uyNumerator(uyNumerator__2), +.i_uyCost(uyCost__2), +.i_uxQuotient(uxQuotient__2), +.i_uyQuotient(uyQuotient__2), +//Outputs +.o_sint(sint__3), +.o_cost(cost__3), +.o_sinp(sinp__3), +.o_cosp(cosp__3), +.o_sintCosp(sintCosp__3), +.o_sintSinp(sintSinp__3), +.o_uz2(uz2__3), +.o_uxUz(uxUz__3), +.o_uyUz(uyUz__3), +.o_uySintSinp(uySintSinp__3), +.o_oneMinusUz2(oneMinusUz2__3), +.o_uyUzSintCosp(uyUzSintCosp__3), +.o_uxUzSintCosp(uxUzSintCosp__3), +.o_uxSintSinp(uxSintSinp__3), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__3), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__3), +.o_uxCost(uxCost__3), +.o_uzCost(uzCost__3), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__3), +.o_uxNumerator(uxNumerator__3), +.o_uyNumerator(uyNumerator__3), +.o_uyCost(uyCost__3), +.o_uxQuotient(uxQuotient__3), +.o_uyQuotient(uyQuotient__3) +); + + //forloop4: + InternalsBlock pipeReg4( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__3), +.i_cost(cost__3), +.i_sinp(sinp__3), +.i_cosp(cosp__3), +.i_sintCosp(sintCosp__3), +.i_sintSinp(sintSinp__3), +.i_uz2(uz2__3), +//changed +.i_uxUz(new_uxUz), +.i_uyUz(uyUz__3), +.i_uySintSinp(uySintSinp__3), +.i_oneMinusUz2(oneMinusUz2__3), +.i_uyUzSintCosp(uyUzSintCosp__3), +.i_uxUzSintCosp(uxUzSintCosp__3), +.i_uxSintSinp(uxSintSinp__3), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__3), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__3), +.i_uxCost(uxCost__3), +.i_uzCost(uzCost__3), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__3), +.i_uxNumerator(uxNumerator__3), +.i_uyNumerator(uyNumerator__3), +.i_uyCost(uyCost__3), +.i_uxQuotient(uxQuotient__3), +.i_uyQuotient(uyQuotient__3), +//Outputs +.o_sint(sint__4), +.o_cost(cost__4), +.o_sinp(sinp__4), +.o_cosp(cosp__4), +.o_sintCosp(sintCosp__4), +.o_sintSinp(sintSinp__4), +.o_uz2(uz2__4), +.o_uxUz(uxUz__4), +.o_uyUz(uyUz__4), +.o_uySintSinp(uySintSinp__4), +.o_oneMinusUz2(oneMinusUz2__4), +.o_uyUzSintCosp(uyUzSintCosp__4), +.o_uxUzSintCosp(uxUzSintCosp__4), +.o_uxSintSinp(uxSintSinp__4), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__4), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__4), +.o_uxCost(uxCost__4), +.o_uzCost(uzCost__4), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__4), +.o_uxNumerator(uxNumerator__4), +.o_uyNumerator(uyNumerator__4), +.o_uyCost(uyCost__4), +.o_uxQuotient(uxQuotient__4), +.o_uyQuotient(uyQuotient__4) +); + +InternalsBlock pipeReg16( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__15), +.i_cost(cost__15), +.i_sinp(sinp__15), +.i_cosp(cosp__15), +.i_sintCosp(sintCosp__15), +.i_sintSinp(sintSinp__15), +.i_uz2(uz2__15), +.i_uxUz(uxUz__15), +.i_uyUz(uyUz__15), +.i_uySintSinp(uySintSinp__15), +.i_oneMinusUz2(oneMinusUz2__15), +.i_uyUzSintCosp(uyUzSintCosp__15), +.i_uxUzSintCosp(uxUzSintCosp__15), +.i_uxSintSinp(uxSintSinp__15), +//changed +.i_sqrtOneMinusUz2(new_sqrtOneMinusUz2), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__15), +.i_uxCost(uxCost__15), +.i_uzCost(uzCost__15), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__15), +.i_uxNumerator(uxNumerator__15), +.i_uyNumerator(uyNumerator__15), +.i_uyCost(uyCost__15), +.i_uxQuotient(uxQuotient__15), +.i_uyQuotient(uyQuotient__15), +//Outputs +.o_sint(sint__16), +.o_cost(cost__16), +.o_sinp(sinp__16), +.o_cosp(cosp__16), +.o_sintCosp(sintCosp__16), +.o_sintSinp(sintSinp__16), +.o_uz2(uz2__16), +.o_uxUz(uxUz__16), +.o_uyUz(uyUz__16), +.o_uySintSinp(uySintSinp__16), +.o_oneMinusUz2(oneMinusUz2__16), +.o_uyUzSintCosp(uyUzSintCosp__16), +.o_uxUzSintCosp(uxUzSintCosp__16), +.o_uxSintSinp(uxSintSinp__16), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__16), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__16), +.o_uxCost(uxCost__16), +.o_uzCost(uzCost__16), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__16), +.o_uxNumerator(uxNumerator__16), +.o_uyNumerator(uyNumerator__16), +.o_uyCost(uyCost__16), +.o_uxQuotient(uxQuotient__16), +.o_uyQuotient(uyQuotient__16) +); + + //forloop 33 (10+20+3): + +InternalsBlock pipeReg33( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +//changed +.i_sint(new_sint), +//changed +.i_cost(new_cost), +//changed +.i_sinp(new_sinp), +//changed +.i_cosp(new_cosp), +//changed +.i_sintCosp(new_sintCosp), +//changed +.i_sintSinp(new_sintSinp), +.i_uz2(uz2__32), +.i_uxUz(uxUz__32), +//changed +.i_uyUz(new_uyUz), +.i_uySintSinp(uySintSinp__32), +.i_oneMinusUz2(oneMinusUz2__32), +.i_uyUzSintCosp(uyUzSintCosp__32), +.i_uxUzSintCosp(uxUzSintCosp__32), +.i_uxSintSinp(uxSintSinp__32), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__32), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__32), +.i_uxCost(uxCost__32), +.i_uzCost(uzCost__32), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__32), +.i_uxNumerator(uxNumerator__32), +.i_uyNumerator(uyNumerator__32), +.i_uyCost(uyCost__32), +.i_uxQuotient(uxQuotient__32), +.i_uyQuotient(uyQuotient__32), +//Outputs +.o_sint(sint__33), +.o_cost(cost__33), +.o_sinp(sinp__33), +.o_cosp(cosp__33), +.o_sintCosp(sintCosp__33), +.o_sintSinp(sintSinp__33), +.o_uz2(uz2__33), +.o_uxUz(uxUz__33), +.o_uyUz(uyUz__33), +.o_uySintSinp(uySintSinp__33), +.o_oneMinusUz2(oneMinusUz2__33), +.o_uyUzSintCosp(uyUzSintCosp__33), +.o_uxUzSintCosp(uxUzSintCosp__33), +.o_uxSintSinp(uxSintSinp__33), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__33), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__33), +.o_uxCost(uxCost__33), +.o_uzCost(uzCost__33), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__33), +.o_uxNumerator(uxNumerator__33), +.o_uyNumerator(uyNumerator__33), +.o_uyCost(uyCost__33), +.o_uxQuotient(uxQuotient__33), +.o_uyQuotient(uyQuotient__33) +); + + //forloop34 (10+20+4): + +InternalsBlock pipeReg34( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__33), +.i_cost(cost__33), +.i_sinp(sinp__33), +.i_cosp(cosp__33), +.i_sintCosp(sintCosp__33), +.i_sintSinp(sintSinp__33), +.i_uz2(uz2__33), +.i_uxUz(uxUz__33), +.i_uyUz(uyUz__33), +//changed +.i_uySintSinp(new_uySintSinp), +.i_oneMinusUz2(oneMinusUz2__33), +//changed +.i_uyUzSintCosp(new_uyUzSintCosp), +//changed +.i_uxUzSintCosp(new_uxUzSintCosp), +//changed +.i_uxSintSinp(new_uxSintSinp), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__33), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__33), +.i_uxCost(uxCost__33), +.i_uzCost(uzCost__33), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__33), +.i_uxNumerator(uxNumerator__33), +.i_uyNumerator(uyNumerator__33), +.i_uyCost(uyCost__33), +.i_uxQuotient(uxQuotient__33), +.i_uyQuotient(uyQuotient__33), +//Outputs +.o_sint(sint__34), +.o_cost(cost__34), +.o_sinp(sinp__34), +.o_cosp(cosp__34), +.o_sintCosp(sintCosp__34), +.o_sintSinp(sintSinp__34), +.o_uz2(uz2__34), +.o_uxUz(uxUz__34), +.o_uyUz(uyUz__34), +.o_uySintSinp(uySintSinp__34), +.o_oneMinusUz2(oneMinusUz2__34), +.o_uyUzSintCosp(uyUzSintCosp__34), +.o_uxUzSintCosp(uxUzSintCosp__34), +.o_uxSintSinp(uxSintSinp__34), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__34), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__34), +.o_uxCost(uxCost__34), +.o_uzCost(uzCost__34), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__34), +.o_uxNumerator(uxNumerator__34), +.o_uyNumerator(uyNumerator__34), +.o_uyCost(uyCost__34), +.o_uxQuotient(uxQuotient__34), +.o_uyQuotient(uyQuotient__34) +); + + //forloop35(10+20+5): + InternalsBlock pipeReg35( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__34), +.i_cost(cost__34), +.i_sinp(sinp__34), +.i_cosp(cosp__34), +.i_sintCosp(sintCosp__34), +.i_sintSinp(sintSinp__34), +.i_uz2(uz2__34), +.i_uxUz(uxUz__34), +.i_uyUz(uyUz__34), +.i_uySintSinp(uySintSinp__34), +.i_oneMinusUz2(oneMinusUz2__34), +.i_uyUzSintCosp(uyUzSintCosp__34), +.i_uxUzSintCosp(uxUzSintCosp__34), +.i_uxSintSinp(uxSintSinp__34), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__34), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__34), +.i_uxCost(uxCost__34), +.i_uzCost(uzCost__34), +//changedval +.i_sqrtOneMinusUz2_inv(new_sqrtOneMinusUz2_inv), +//changed +.i_uxNumerator(new_uxNumerator), +//changed +.i_uyNumerator(new_uyNumerator), +.i_uyCost(uyCost__34), +.i_uxQuotient(uxQuotient__34), +.i_uyQuotient(uyQuotient__34), +//Outputs +.o_sint(sint__35), +.o_cost(cost__35), +.o_sinp(sinp__35), +.o_cosp(cosp__35), +.o_sintCosp(sintCosp__35), +.o_sintSinp(sintSinp__35), +.o_uz2(uz2__35), +.o_uxUz(uxUz__35), +.o_uyUz(uyUz__35), +.o_uySintSinp(uySintSinp__35), +.o_oneMinusUz2(oneMinusUz2__35), +.o_uyUzSintCosp(uyUzSintCosp__35), +.o_uxUzSintCosp(uxUzSintCosp__35), +.o_uxSintSinp(uxSintSinp__35), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__35), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__35), +.o_uxCost(uxCost__35), +.o_uzCost(uzCost__35), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__35), +.o_uxNumerator(uxNumerator__35), +.o_uyNumerator(uyNumerator__35), +.o_uyCost(uyCost__35), +.o_uxQuotient(uxQuotient__35), +.o_uyQuotient(uyQuotient__35) +); + + + //forloop36 (10+20+6): + +InternalsBlock pipeReg36( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__35), +.i_cost(cost__35), +.i_sinp(sinp__35), +.i_cosp(cosp__35), +.i_sintCosp(sintCosp__35), +.i_sintSinp(sintSinp__35), +.i_uz2(uz2__35), +.i_uxUz(uxUz__35), +.i_uyUz(uyUz__35), +.i_uySintSinp(uySintSinp__35), +.i_oneMinusUz2(oneMinusUz2__35), +.i_uyUzSintCosp(uyUzSintCosp__35), +.i_uxUzSintCosp(uxUzSintCosp__35), +.i_uxSintSinp(uxSintSinp__35), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__35), +//changed +.i_sintCospSqrtOneMinusUz2(new_sintCospSqrtOneMinusUz2), +//changed +.i_uxCost(new_uxCost), +//changed +.i_uzCost(new_uzCost), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__35), +.i_uxNumerator(uxNumerator__35), +.i_uyNumerator(uyNumerator__35), +//changed +.i_uyCost(new_uyCost), +//changed), +.i_uxQuotient(new_uxQuotient), +//cahgned +.i_uyQuotient(new_uyQuotient), +//Outputs +.o_sint(sint__36), +.o_cost(cost__36), +.o_sinp(sinp__36), +.o_cosp(cosp__36), +.o_sintCosp(sintCosp__36), +.o_sintSinp(sintSinp__36), +.o_uz2(uz2__36), +.o_uxUz(uxUz__36), +.o_uyUz(uyUz__36), +.o_uySintSinp(uySintSinp__36), +.o_oneMinusUz2(oneMinusUz2__36), +.o_uyUzSintCosp(uyUzSintCosp__36), +.o_uxUzSintCosp(uxUzSintCosp__36), +.o_uxSintSinp(uxSintSinp__36), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__36), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__36), +.o_uxCost(uxCost__36), +.o_uzCost(uzCost__36), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__36), +.o_uxNumerator(uxNumerator__36), +.o_uyNumerator(uyNumerator__36), +.o_uyCost(uyCost__36), +.o_uxQuotient(uxQuotient__36), +.o_uyQuotient(uyQuotient__36) +); + +InternalsBlock pipeReg37( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__36), +.i_cost(cost__36), +.i_sinp(sinp__36), +.i_cosp(cosp__36), +.i_sintCosp(sintCosp__36), +.i_sintSinp(sintSinp__36), +.i_uz2(uz2__36), +.i_uxUz(uxUz__36), +.i_uyUz(uyUz__36), +.i_uySintSinp(uySintSinp__36), +.i_oneMinusUz2(oneMinusUz2__36), +.i_uyUzSintCosp(uyUzSintCosp__36), +.i_uxUzSintCosp(uxUzSintCosp__36), +.i_uxSintSinp(uxSintSinp__36), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__36), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__36), +.i_uxCost(uxCost__36), +.i_uzCost(uzCost__36), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__36), +.i_uxNumerator(uxNumerator__36), +.i_uyNumerator(uyNumerator__36), +.i_uyCost(uyCost__36), +.i_uxQuotient(uxQuotient__36), +.i_uyQuotient(uyQuotient__36), +//Outputs +.o_sint(sint__37), +.o_cost(cost__37), +.o_sinp(sinp__37), +.o_cosp(cosp__37), +.o_sintCosp(sintCosp__37), +.o_sintSinp(sintSinp__37), +.o_uz2(uz2__37), +.o_uxUz(uxUz__37), +.o_uyUz(uyUz__37), +.o_uySintSinp(uySintSinp__37), +.o_oneMinusUz2(oneMinusUz2__37), +.o_uyUzSintCosp(uyUzSintCosp__37), +.o_uxUzSintCosp(uxUzSintCosp__37), +.o_uxSintSinp(uxSintSinp__37), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__37), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__37), +.o_uxCost(uxCost__37), +.o_uzCost(uzCost__37), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__37), +.o_uxNumerator(uxNumerator__37), +.o_uyNumerator(uyNumerator__37), +.o_uyCost(uyCost__37), +.o_uxQuotient(uxQuotient__37), +.o_uyQuotient(uyQuotient__37) +); + + + +InternalsBlock pipeReg32( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__31), +.i_cost(cost__31), +.i_sinp(sinp__31), +.i_cosp(cosp__31), +.i_sintCosp(sintCosp__31), +.i_sintSinp(sintSinp__31), +.i_uz2(uz2__31), +.i_uxUz(uxUz__31), +.i_uyUz(uyUz__31), +.i_uySintSinp(uySintSinp__31), +.i_oneMinusUz2(oneMinusUz2__31), +.i_uyUzSintCosp(uyUzSintCosp__31), +.i_uxUzSintCosp(uxUzSintCosp__31), +.i_uxSintSinp(uxSintSinp__31), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__31), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__31), +.i_uxCost(uxCost__31), +.i_uzCost(uzCost__31), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__31), +.i_uxNumerator(uxNumerator__31), +.i_uyNumerator(uyNumerator__31), +.i_uyCost(uyCost__31), +.i_uxQuotient(uxQuotient__31), +.i_uyQuotient(uyQuotient__31), +//Outputs +.o_sint(sint__32), +.o_cost(cost__32), +.o_sinp(sinp__32), +.o_cosp(cosp__32), +.o_sintCosp(sintCosp__32), +.o_sintSinp(sintSinp__32), +.o_uz2(uz2__32), +.o_uxUz(uxUz__32), +.o_uyUz(uyUz__32), +.o_uySintSinp(uySintSinp__32), +.o_oneMinusUz2(oneMinusUz2__32), +.o_uyUzSintCosp(uyUzSintCosp__32), +.o_uxUzSintCosp(uxUzSintCosp__32), +.o_uxSintSinp(uxSintSinp__32), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__32), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__32), +.o_uxCost(uxCost__32), +.o_uzCost(uzCost__32), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__32), +.o_uxNumerator(uxNumerator__32), +.o_uyNumerator(uyNumerator__32), +.o_uyCost(uyCost__32), +.o_uxQuotient(uxQuotient__32), +.o_uyQuotient(uyQuotient__32) +); + +InternalsBlock pipeReg31( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__30), +.i_cost(cost__30), +.i_sinp(sinp__30), +.i_cosp(cosp__30), +.i_sintCosp(sintCosp__30), +.i_sintSinp(sintSinp__30), +.i_uz2(uz2__30), +.i_uxUz(uxUz__30), +.i_uyUz(uyUz__30), +.i_uySintSinp(uySintSinp__30), +.i_oneMinusUz2(oneMinusUz2__30), +.i_uyUzSintCosp(uyUzSintCosp__30), +.i_uxUzSintCosp(uxUzSintCosp__30), +.i_uxSintSinp(uxSintSinp__30), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__30), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__30), +.i_uxCost(uxCost__30), +.i_uzCost(uzCost__30), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__30), +.i_uxNumerator(uxNumerator__30), +.i_uyNumerator(uyNumerator__30), +.i_uyCost(uyCost__30), +.i_uxQuotient(uxQuotient__30), +.i_uyQuotient(uyQuotient__30), +//Outputs +.o_sint(sint__31), +.o_cost(cost__31), +.o_sinp(sinp__31), +.o_cosp(cosp__31), +.o_sintCosp(sintCosp__31), +.o_sintSinp(sintSinp__31), +.o_uz2(uz2__31), +.o_uxUz(uxUz__31), +.o_uyUz(uyUz__31), +.o_uySintSinp(uySintSinp__31), +.o_oneMinusUz2(oneMinusUz2__31), +.o_uyUzSintCosp(uyUzSintCosp__31), +.o_uxUzSintCosp(uxUzSintCosp__31), +.o_uxSintSinp(uxSintSinp__31), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__31), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__31), +.o_uxCost(uxCost__31), +.o_uzCost(uzCost__31), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__31), +.o_uxNumerator(uxNumerator__31), +.o_uyNumerator(uyNumerator__31), +.o_uyCost(uyCost__31), +.o_uxQuotient(uxQuotient__31), +.o_uyQuotient(uyQuotient__31) +); + +InternalsBlock pipeReg30( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__29), +.i_cost(cost__29), +.i_sinp(sinp__29), +.i_cosp(cosp__29), +.i_sintCosp(sintCosp__29), +.i_sintSinp(sintSinp__29), +.i_uz2(uz2__29), +.i_uxUz(uxUz__29), +.i_uyUz(uyUz__29), +.i_uySintSinp(uySintSinp__29), +.i_oneMinusUz2(oneMinusUz2__29), +.i_uyUzSintCosp(uyUzSintCosp__29), +.i_uxUzSintCosp(uxUzSintCosp__29), +.i_uxSintSinp(uxSintSinp__29), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__29), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__29), +.i_uxCost(uxCost__29), +.i_uzCost(uzCost__29), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__29), +.i_uxNumerator(uxNumerator__29), +.i_uyNumerator(uyNumerator__29), +.i_uyCost(uyCost__29), +.i_uxQuotient(uxQuotient__29), +.i_uyQuotient(uyQuotient__29), +//Outputs +.o_sint(sint__30), +.o_cost(cost__30), +.o_sinp(sinp__30), +.o_cosp(cosp__30), +.o_sintCosp(sintCosp__30), +.o_sintSinp(sintSinp__30), +.o_uz2(uz2__30), +.o_uxUz(uxUz__30), +.o_uyUz(uyUz__30), +.o_uySintSinp(uySintSinp__30), +.o_oneMinusUz2(oneMinusUz2__30), +.o_uyUzSintCosp(uyUzSintCosp__30), +.o_uxUzSintCosp(uxUzSintCosp__30), +.o_uxSintSinp(uxSintSinp__30), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__30), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__30), +.o_uxCost(uxCost__30), +.o_uzCost(uzCost__30), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__30), +.o_uxNumerator(uxNumerator__30), +.o_uyNumerator(uyNumerator__30), +.o_uyCost(uyCost__30), +.o_uxQuotient(uxQuotient__30), +.o_uyQuotient(uyQuotient__30) +); + +InternalsBlock pipeReg29( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__28), +.i_cost(cost__28), +.i_sinp(sinp__28), +.i_cosp(cosp__28), +.i_sintCosp(sintCosp__28), +.i_sintSinp(sintSinp__28), +.i_uz2(uz2__28), +.i_uxUz(uxUz__28), +.i_uyUz(uyUz__28), +.i_uySintSinp(uySintSinp__28), +.i_oneMinusUz2(oneMinusUz2__28), +.i_uyUzSintCosp(uyUzSintCosp__28), +.i_uxUzSintCosp(uxUzSintCosp__28), +.i_uxSintSinp(uxSintSinp__28), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__28), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__28), +.i_uxCost(uxCost__28), +.i_uzCost(uzCost__28), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__28), +.i_uxNumerator(uxNumerator__28), +.i_uyNumerator(uyNumerator__28), +.i_uyCost(uyCost__28), +.i_uxQuotient(uxQuotient__28), +.i_uyQuotient(uyQuotient__28), +//Outputs +.o_sint(sint__29), +.o_cost(cost__29), +.o_sinp(sinp__29), +.o_cosp(cosp__29), +.o_sintCosp(sintCosp__29), +.o_sintSinp(sintSinp__29), +.o_uz2(uz2__29), +.o_uxUz(uxUz__29), +.o_uyUz(uyUz__29), +.o_uySintSinp(uySintSinp__29), +.o_oneMinusUz2(oneMinusUz2__29), +.o_uyUzSintCosp(uyUzSintCosp__29), +.o_uxUzSintCosp(uxUzSintCosp__29), +.o_uxSintSinp(uxSintSinp__29), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__29), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__29), +.o_uxCost(uxCost__29), +.o_uzCost(uzCost__29), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__29), +.o_uxNumerator(uxNumerator__29), +.o_uyNumerator(uyNumerator__29), +.o_uyCost(uyCost__29), +.o_uxQuotient(uxQuotient__29), +.o_uyQuotient(uyQuotient__29) +); + +InternalsBlock pipeReg28( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__27), +.i_cost(cost__27), +.i_sinp(sinp__27), +.i_cosp(cosp__27), +.i_sintCosp(sintCosp__27), +.i_sintSinp(sintSinp__27), +.i_uz2(uz2__27), +.i_uxUz(uxUz__27), +.i_uyUz(uyUz__27), +.i_uySintSinp(uySintSinp__27), +.i_oneMinusUz2(oneMinusUz2__27), +.i_uyUzSintCosp(uyUzSintCosp__27), +.i_uxUzSintCosp(uxUzSintCosp__27), +.i_uxSintSinp(uxSintSinp__27), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__27), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__27), +.i_uxCost(uxCost__27), +.i_uzCost(uzCost__27), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__27), +.i_uxNumerator(uxNumerator__27), +.i_uyNumerator(uyNumerator__27), +.i_uyCost(uyCost__27), +.i_uxQuotient(uxQuotient__27), +.i_uyQuotient(uyQuotient__27), +//Outputs +.o_sint(sint__28), +.o_cost(cost__28), +.o_sinp(sinp__28), +.o_cosp(cosp__28), +.o_sintCosp(sintCosp__28), +.o_sintSinp(sintSinp__28), +.o_uz2(uz2__28), +.o_uxUz(uxUz__28), +.o_uyUz(uyUz__28), +.o_uySintSinp(uySintSinp__28), +.o_oneMinusUz2(oneMinusUz2__28), +.o_uyUzSintCosp(uyUzSintCosp__28), +.o_uxUzSintCosp(uxUzSintCosp__28), +.o_uxSintSinp(uxSintSinp__28), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__28), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__28), +.o_uxCost(uxCost__28), +.o_uzCost(uzCost__28), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__28), +.o_uxNumerator(uxNumerator__28), +.o_uyNumerator(uyNumerator__28), +.o_uyCost(uyCost__28), +.o_uxQuotient(uxQuotient__28), +.o_uyQuotient(uyQuotient__28) +); + +InternalsBlock pipeReg27( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__26), +.i_cost(cost__26), +.i_sinp(sinp__26), +.i_cosp(cosp__26), +.i_sintCosp(sintCosp__26), +.i_sintSinp(sintSinp__26), +.i_uz2(uz2__26), +.i_uxUz(uxUz__26), +.i_uyUz(uyUz__26), +.i_uySintSinp(uySintSinp__26), +.i_oneMinusUz2(oneMinusUz2__26), +.i_uyUzSintCosp(uyUzSintCosp__26), +.i_uxUzSintCosp(uxUzSintCosp__26), +.i_uxSintSinp(uxSintSinp__26), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__26), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__26), +.i_uxCost(uxCost__26), +.i_uzCost(uzCost__26), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__26), +.i_uxNumerator(uxNumerator__26), +.i_uyNumerator(uyNumerator__26), +.i_uyCost(uyCost__26), +.i_uxQuotient(uxQuotient__26), +.i_uyQuotient(uyQuotient__26), +//Outputs +.o_sint(sint__27), +.o_cost(cost__27), +.o_sinp(sinp__27), +.o_cosp(cosp__27), +.o_sintCosp(sintCosp__27), +.o_sintSinp(sintSinp__27), +.o_uz2(uz2__27), +.o_uxUz(uxUz__27), +.o_uyUz(uyUz__27), +.o_uySintSinp(uySintSinp__27), +.o_oneMinusUz2(oneMinusUz2__27), +.o_uyUzSintCosp(uyUzSintCosp__27), +.o_uxUzSintCosp(uxUzSintCosp__27), +.o_uxSintSinp(uxSintSinp__27), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__27), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__27), +.o_uxCost(uxCost__27), +.o_uzCost(uzCost__27), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__27), +.o_uxNumerator(uxNumerator__27), +.o_uyNumerator(uyNumerator__27), +.o_uyCost(uyCost__27), +.o_uxQuotient(uxQuotient__27), +.o_uyQuotient(uyQuotient__27) +); + +InternalsBlock pipeReg26( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__25), +.i_cost(cost__25), +.i_sinp(sinp__25), +.i_cosp(cosp__25), +.i_sintCosp(sintCosp__25), +.i_sintSinp(sintSinp__25), +.i_uz2(uz2__25), +.i_uxUz(uxUz__25), +.i_uyUz(uyUz__25), +.i_uySintSinp(uySintSinp__25), +.i_oneMinusUz2(oneMinusUz2__25), +.i_uyUzSintCosp(uyUzSintCosp__25), +.i_uxUzSintCosp(uxUzSintCosp__25), +.i_uxSintSinp(uxSintSinp__25), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__25), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__25), +.i_uxCost(uxCost__25), +.i_uzCost(uzCost__25), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__25), +.i_uxNumerator(uxNumerator__25), +.i_uyNumerator(uyNumerator__25), +.i_uyCost(uyCost__25), +.i_uxQuotient(uxQuotient__25), +.i_uyQuotient(uyQuotient__25), +//Outputs +.o_sint(sint__26), +.o_cost(cost__26), +.o_sinp(sinp__26), +.o_cosp(cosp__26), +.o_sintCosp(sintCosp__26), +.o_sintSinp(sintSinp__26), +.o_uz2(uz2__26), +.o_uxUz(uxUz__26), +.o_uyUz(uyUz__26), +.o_uySintSinp(uySintSinp__26), +.o_oneMinusUz2(oneMinusUz2__26), +.o_uyUzSintCosp(uyUzSintCosp__26), +.o_uxUzSintCosp(uxUzSintCosp__26), +.o_uxSintSinp(uxSintSinp__26), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__26), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__26), +.o_uxCost(uxCost__26), +.o_uzCost(uzCost__26), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__26), +.o_uxNumerator(uxNumerator__26), +.o_uyNumerator(uyNumerator__26), +.o_uyCost(uyCost__26), +.o_uxQuotient(uxQuotient__26), +.o_uyQuotient(uyQuotient__26) +); + +InternalsBlock pipeReg25( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__24), +.i_cost(cost__24), +.i_sinp(sinp__24), +.i_cosp(cosp__24), +.i_sintCosp(sintCosp__24), +.i_sintSinp(sintSinp__24), +.i_uz2(uz2__24), +.i_uxUz(uxUz__24), +.i_uyUz(uyUz__24), +.i_uySintSinp(uySintSinp__24), +.i_oneMinusUz2(oneMinusUz2__24), +.i_uyUzSintCosp(uyUzSintCosp__24), +.i_uxUzSintCosp(uxUzSintCosp__24), +.i_uxSintSinp(uxSintSinp__24), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__24), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__24), +.i_uxCost(uxCost__24), +.i_uzCost(uzCost__24), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__24), +.i_uxNumerator(uxNumerator__24), +.i_uyNumerator(uyNumerator__24), +.i_uyCost(uyCost__24), +.i_uxQuotient(uxQuotient__24), +.i_uyQuotient(uyQuotient__24), +//Outputs +.o_sint(sint__25), +.o_cost(cost__25), +.o_sinp(sinp__25), +.o_cosp(cosp__25), +.o_sintCosp(sintCosp__25), +.o_sintSinp(sintSinp__25), +.o_uz2(uz2__25), +.o_uxUz(uxUz__25), +.o_uyUz(uyUz__25), +.o_uySintSinp(uySintSinp__25), +.o_oneMinusUz2(oneMinusUz2__25), +.o_uyUzSintCosp(uyUzSintCosp__25), +.o_uxUzSintCosp(uxUzSintCosp__25), +.o_uxSintSinp(uxSintSinp__25), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__25), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__25), +.o_uxCost(uxCost__25), +.o_uzCost(uzCost__25), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__25), +.o_uxNumerator(uxNumerator__25), +.o_uyNumerator(uyNumerator__25), +.o_uyCost(uyCost__25), +.o_uxQuotient(uxQuotient__25), +.o_uyQuotient(uyQuotient__25) +); + +InternalsBlock pipeReg24( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__23), +.i_cost(cost__23), +.i_sinp(sinp__23), +.i_cosp(cosp__23), +.i_sintCosp(sintCosp__23), +.i_sintSinp(sintSinp__23), +.i_uz2(uz2__23), +.i_uxUz(uxUz__23), +.i_uyUz(uyUz__23), +.i_uySintSinp(uySintSinp__23), +.i_oneMinusUz2(oneMinusUz2__23), +.i_uyUzSintCosp(uyUzSintCosp__23), +.i_uxUzSintCosp(uxUzSintCosp__23), +.i_uxSintSinp(uxSintSinp__23), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__23), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__23), +.i_uxCost(uxCost__23), +.i_uzCost(uzCost__23), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__23), +.i_uxNumerator(uxNumerator__23), +.i_uyNumerator(uyNumerator__23), +.i_uyCost(uyCost__23), +.i_uxQuotient(uxQuotient__23), +.i_uyQuotient(uyQuotient__23), +//Outputs +.o_sint(sint__24), +.o_cost(cost__24), +.o_sinp(sinp__24), +.o_cosp(cosp__24), +.o_sintCosp(sintCosp__24), +.o_sintSinp(sintSinp__24), +.o_uz2(uz2__24), +.o_uxUz(uxUz__24), +.o_uyUz(uyUz__24), +.o_uySintSinp(uySintSinp__24), +.o_oneMinusUz2(oneMinusUz2__24), +.o_uyUzSintCosp(uyUzSintCosp__24), +.o_uxUzSintCosp(uxUzSintCosp__24), +.o_uxSintSinp(uxSintSinp__24), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__24), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__24), +.o_uxCost(uxCost__24), +.o_uzCost(uzCost__24), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__24), +.o_uxNumerator(uxNumerator__24), +.o_uyNumerator(uyNumerator__24), +.o_uyCost(uyCost__24), +.o_uxQuotient(uxQuotient__24), +.o_uyQuotient(uyQuotient__24) +); + +InternalsBlock pipeReg23( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__22), +.i_cost(cost__22), +.i_sinp(sinp__22), +.i_cosp(cosp__22), +.i_sintCosp(sintCosp__22), +.i_sintSinp(sintSinp__22), +.i_uz2(uz2__22), +.i_uxUz(uxUz__22), +.i_uyUz(uyUz__22), +.i_uySintSinp(uySintSinp__22), +.i_oneMinusUz2(oneMinusUz2__22), +.i_uyUzSintCosp(uyUzSintCosp__22), +.i_uxUzSintCosp(uxUzSintCosp__22), +.i_uxSintSinp(uxSintSinp__22), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__22), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__22), +.i_uxCost(uxCost__22), +.i_uzCost(uzCost__22), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__22), +.i_uxNumerator(uxNumerator__22), +.i_uyNumerator(uyNumerator__22), +.i_uyCost(uyCost__22), +.i_uxQuotient(uxQuotient__22), +.i_uyQuotient(uyQuotient__22), +//Outputs +.o_sint(sint__23), +.o_cost(cost__23), +.o_sinp(sinp__23), +.o_cosp(cosp__23), +.o_sintCosp(sintCosp__23), +.o_sintSinp(sintSinp__23), +.o_uz2(uz2__23), +.o_uxUz(uxUz__23), +.o_uyUz(uyUz__23), +.o_uySintSinp(uySintSinp__23), +.o_oneMinusUz2(oneMinusUz2__23), +.o_uyUzSintCosp(uyUzSintCosp__23), +.o_uxUzSintCosp(uxUzSintCosp__23), +.o_uxSintSinp(uxSintSinp__23), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__23), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__23), +.o_uxCost(uxCost__23), +.o_uzCost(uzCost__23), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__23), +.o_uxNumerator(uxNumerator__23), +.o_uyNumerator(uyNumerator__23), +.o_uyCost(uyCost__23), +.o_uxQuotient(uxQuotient__23), +.o_uyQuotient(uyQuotient__23) +); + +InternalsBlock pipeReg22( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__21), +.i_cost(cost__21), +.i_sinp(sinp__21), +.i_cosp(cosp__21), +.i_sintCosp(sintCosp__21), +.i_sintSinp(sintSinp__21), +.i_uz2(uz2__21), +.i_uxUz(uxUz__21), +.i_uyUz(uyUz__21), +.i_uySintSinp(uySintSinp__21), +.i_oneMinusUz2(oneMinusUz2__21), +.i_uyUzSintCosp(uyUzSintCosp__21), +.i_uxUzSintCosp(uxUzSintCosp__21), +.i_uxSintSinp(uxSintSinp__21), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__21), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__21), +.i_uxCost(uxCost__21), +.i_uzCost(uzCost__21), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__21), +.i_uxNumerator(uxNumerator__21), +.i_uyNumerator(uyNumerator__21), +.i_uyCost(uyCost__21), +.i_uxQuotient(uxQuotient__21), +.i_uyQuotient(uyQuotient__21), +//Outputs +.o_sint(sint__22), +.o_cost(cost__22), +.o_sinp(sinp__22), +.o_cosp(cosp__22), +.o_sintCosp(sintCosp__22), +.o_sintSinp(sintSinp__22), +.o_uz2(uz2__22), +.o_uxUz(uxUz__22), +.o_uyUz(uyUz__22), +.o_uySintSinp(uySintSinp__22), +.o_oneMinusUz2(oneMinusUz2__22), +.o_uyUzSintCosp(uyUzSintCosp__22), +.o_uxUzSintCosp(uxUzSintCosp__22), +.o_uxSintSinp(uxSintSinp__22), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__22), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__22), +.o_uxCost(uxCost__22), +.o_uzCost(uzCost__22), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__22), +.o_uxNumerator(uxNumerator__22), +.o_uyNumerator(uyNumerator__22), +.o_uyCost(uyCost__22), +.o_uxQuotient(uxQuotient__22), +.o_uyQuotient(uyQuotient__22) +); + +InternalsBlock pipeReg21( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__20), +.i_cost(cost__20), +.i_sinp(sinp__20), +.i_cosp(cosp__20), +.i_sintCosp(sintCosp__20), +.i_sintSinp(sintSinp__20), +.i_uz2(uz2__20), +.i_uxUz(uxUz__20), +.i_uyUz(uyUz__20), +.i_uySintSinp(uySintSinp__20), +.i_oneMinusUz2(oneMinusUz2__20), +.i_uyUzSintCosp(uyUzSintCosp__20), +.i_uxUzSintCosp(uxUzSintCosp__20), +.i_uxSintSinp(uxSintSinp__20), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__20), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__20), +.i_uxCost(uxCost__20), +.i_uzCost(uzCost__20), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__20), +.i_uxNumerator(uxNumerator__20), +.i_uyNumerator(uyNumerator__20), +.i_uyCost(uyCost__20), +.i_uxQuotient(uxQuotient__20), +.i_uyQuotient(uyQuotient__20), +//Outputs +.o_sint(sint__21), +.o_cost(cost__21), +.o_sinp(sinp__21), +.o_cosp(cosp__21), +.o_sintCosp(sintCosp__21), +.o_sintSinp(sintSinp__21), +.o_uz2(uz2__21), +.o_uxUz(uxUz__21), +.o_uyUz(uyUz__21), +.o_uySintSinp(uySintSinp__21), +.o_oneMinusUz2(oneMinusUz2__21), +.o_uyUzSintCosp(uyUzSintCosp__21), +.o_uxUzSintCosp(uxUzSintCosp__21), +.o_uxSintSinp(uxSintSinp__21), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__21), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__21), +.o_uxCost(uxCost__21), +.o_uzCost(uzCost__21), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__21), +.o_uxNumerator(uxNumerator__21), +.o_uyNumerator(uyNumerator__21), +.o_uyCost(uyCost__21), +.o_uxQuotient(uxQuotient__21), +.o_uyQuotient(uyQuotient__21) +); + +InternalsBlock pipeReg20( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__19), +.i_cost(cost__19), +.i_sinp(sinp__19), +.i_cosp(cosp__19), +.i_sintCosp(sintCosp__19), +.i_sintSinp(sintSinp__19), +.i_uz2(uz2__19), +.i_uxUz(uxUz__19), +.i_uyUz(uyUz__19), +.i_uySintSinp(uySintSinp__19), +.i_oneMinusUz2(oneMinusUz2__19), +.i_uyUzSintCosp(uyUzSintCosp__19), +.i_uxUzSintCosp(uxUzSintCosp__19), +.i_uxSintSinp(uxSintSinp__19), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__19), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__19), +.i_uxCost(uxCost__19), +.i_uzCost(uzCost__19), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__19), +.i_uxNumerator(uxNumerator__19), +.i_uyNumerator(uyNumerator__19), +.i_uyCost(uyCost__19), +.i_uxQuotient(uxQuotient__19), +.i_uyQuotient(uyQuotient__19), +//Outputs +.o_sint(sint__20), +.o_cost(cost__20), +.o_sinp(sinp__20), +.o_cosp(cosp__20), +.o_sintCosp(sintCosp__20), +.o_sintSinp(sintSinp__20), +.o_uz2(uz2__20), +.o_uxUz(uxUz__20), +.o_uyUz(uyUz__20), +.o_uySintSinp(uySintSinp__20), +.o_oneMinusUz2(oneMinusUz2__20), +.o_uyUzSintCosp(uyUzSintCosp__20), +.o_uxUzSintCosp(uxUzSintCosp__20), +.o_uxSintSinp(uxSintSinp__20), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__20), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__20), +.o_uxCost(uxCost__20), +.o_uzCost(uzCost__20), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__20), +.o_uxNumerator(uxNumerator__20), +.o_uyNumerator(uyNumerator__20), +.o_uyCost(uyCost__20), +.o_uxQuotient(uxQuotient__20), +.o_uyQuotient(uyQuotient__20) +); + +InternalsBlock pipeReg19( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__18), +.i_cost(cost__18), +.i_sinp(sinp__18), +.i_cosp(cosp__18), +.i_sintCosp(sintCosp__18), +.i_sintSinp(sintSinp__18), +.i_uz2(uz2__18), +.i_uxUz(uxUz__18), +.i_uyUz(uyUz__18), +.i_uySintSinp(uySintSinp__18), +.i_oneMinusUz2(oneMinusUz2__18), +.i_uyUzSintCosp(uyUzSintCosp__18), +.i_uxUzSintCosp(uxUzSintCosp__18), +.i_uxSintSinp(uxSintSinp__18), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__18), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__18), +.i_uxCost(uxCost__18), +.i_uzCost(uzCost__18), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__18), +.i_uxNumerator(uxNumerator__18), +.i_uyNumerator(uyNumerator__18), +.i_uyCost(uyCost__18), +.i_uxQuotient(uxQuotient__18), +.i_uyQuotient(uyQuotient__18), +//Outputs +.o_sint(sint__19), +.o_cost(cost__19), +.o_sinp(sinp__19), +.o_cosp(cosp__19), +.o_sintCosp(sintCosp__19), +.o_sintSinp(sintSinp__19), +.o_uz2(uz2__19), +.o_uxUz(uxUz__19), +.o_uyUz(uyUz__19), +.o_uySintSinp(uySintSinp__19), +.o_oneMinusUz2(oneMinusUz2__19), +.o_uyUzSintCosp(uyUzSintCosp__19), +.o_uxUzSintCosp(uxUzSintCosp__19), +.o_uxSintSinp(uxSintSinp__19), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__19), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__19), +.o_uxCost(uxCost__19), +.o_uzCost(uzCost__19), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__19), +.o_uxNumerator(uxNumerator__19), +.o_uyNumerator(uyNumerator__19), +.o_uyCost(uyCost__19), +.o_uxQuotient(uxQuotient__19), +.o_uyQuotient(uyQuotient__19) +); + +InternalsBlock pipeReg18( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__17), +.i_cost(cost__17), +.i_sinp(sinp__17), +.i_cosp(cosp__17), +.i_sintCosp(sintCosp__17), +.i_sintSinp(sintSinp__17), +.i_uz2(uz2__17), +.i_uxUz(uxUz__17), +.i_uyUz(uyUz__17), +.i_uySintSinp(uySintSinp__17), +.i_oneMinusUz2(oneMinusUz2__17), +.i_uyUzSintCosp(uyUzSintCosp__17), +.i_uxUzSintCosp(uxUzSintCosp__17), +.i_uxSintSinp(uxSintSinp__17), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__17), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__17), +.i_uxCost(uxCost__17), +.i_uzCost(uzCost__17), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__17), +.i_uxNumerator(uxNumerator__17), +.i_uyNumerator(uyNumerator__17), +.i_uyCost(uyCost__17), +.i_uxQuotient(uxQuotient__17), +.i_uyQuotient(uyQuotient__17), +//Outputs +.o_sint(sint__18), +.o_cost(cost__18), +.o_sinp(sinp__18), +.o_cosp(cosp__18), +.o_sintCosp(sintCosp__18), +.o_sintSinp(sintSinp__18), +.o_uz2(uz2__18), +.o_uxUz(uxUz__18), +.o_uyUz(uyUz__18), +.o_uySintSinp(uySintSinp__18), +.o_oneMinusUz2(oneMinusUz2__18), +.o_uyUzSintCosp(uyUzSintCosp__18), +.o_uxUzSintCosp(uxUzSintCosp__18), +.o_uxSintSinp(uxSintSinp__18), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__18), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__18), +.o_uxCost(uxCost__18), +.o_uzCost(uzCost__18), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__18), +.o_uxNumerator(uxNumerator__18), +.o_uyNumerator(uyNumerator__18), +.o_uyCost(uyCost__18), +.o_uxQuotient(uxQuotient__18), +.o_uyQuotient(uyQuotient__18) +); + +InternalsBlock pipeReg17( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__16), +.i_cost(cost__16), +.i_sinp(sinp__16), +.i_cosp(cosp__16), +.i_sintCosp(sintCosp__16), +.i_sintSinp(sintSinp__16), +.i_uz2(uz2__16), +.i_uxUz(uxUz__16), +.i_uyUz(uyUz__16), +.i_uySintSinp(uySintSinp__16), +.i_oneMinusUz2(oneMinusUz2__16), +.i_uyUzSintCosp(uyUzSintCosp__16), +.i_uxUzSintCosp(uxUzSintCosp__16), +.i_uxSintSinp(uxSintSinp__16), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__16), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__16), +.i_uxCost(uxCost__16), +.i_uzCost(uzCost__16), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__16), +.i_uxNumerator(uxNumerator__16), +.i_uyNumerator(uyNumerator__16), +.i_uyCost(uyCost__16), +.i_uxQuotient(uxQuotient__16), +.i_uyQuotient(uyQuotient__16), +//Outputs +.o_sint(sint__17), +.o_cost(cost__17), +.o_sinp(sinp__17), +.o_cosp(cosp__17), +.o_sintCosp(sintCosp__17), +.o_sintSinp(sintSinp__17), +.o_uz2(uz2__17), +.o_uxUz(uxUz__17), +.o_uyUz(uyUz__17), +.o_uySintSinp(uySintSinp__17), +.o_oneMinusUz2(oneMinusUz2__17), +.o_uyUzSintCosp(uyUzSintCosp__17), +.o_uxUzSintCosp(uxUzSintCosp__17), +.o_uxSintSinp(uxSintSinp__17), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__17), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__17), +.o_uxCost(uxCost__17), +.o_uzCost(uzCost__17), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__17), +.o_uxNumerator(uxNumerator__17), +.o_uyNumerator(uyNumerator__17), +.o_uyCost(uyCost__17), +.o_uxQuotient(uxQuotient__17), +.o_uyQuotient(uyQuotient__17) +); + + +InternalsBlock pipeReg15( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__14), +.i_cost(cost__14), +.i_sinp(sinp__14), +.i_cosp(cosp__14), +.i_sintCosp(sintCosp__14), +.i_sintSinp(sintSinp__14), +.i_uz2(uz2__14), +.i_uxUz(uxUz__14), +.i_uyUz(uyUz__14), +.i_uySintSinp(uySintSinp__14), +.i_oneMinusUz2(oneMinusUz2__14), +.i_uyUzSintCosp(uyUzSintCosp__14), +.i_uxUzSintCosp(uxUzSintCosp__14), +.i_uxSintSinp(uxSintSinp__14), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__14), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__14), +.i_uxCost(uxCost__14), +.i_uzCost(uzCost__14), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__14), +.i_uxNumerator(uxNumerator__14), +.i_uyNumerator(uyNumerator__14), +.i_uyCost(uyCost__14), +.i_uxQuotient(uxQuotient__14), +.i_uyQuotient(uyQuotient__14), +//Outputs +.o_sint(sint__15), +.o_cost(cost__15), +.o_sinp(sinp__15), +.o_cosp(cosp__15), +.o_sintCosp(sintCosp__15), +.o_sintSinp(sintSinp__15), +.o_uz2(uz2__15), +.o_uxUz(uxUz__15), +.o_uyUz(uyUz__15), +.o_uySintSinp(uySintSinp__15), +.o_oneMinusUz2(oneMinusUz2__15), +.o_uyUzSintCosp(uyUzSintCosp__15), +.o_uxUzSintCosp(uxUzSintCosp__15), +.o_uxSintSinp(uxSintSinp__15), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__15), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__15), +.o_uxCost(uxCost__15), +.o_uzCost(uzCost__15), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__15), +.o_uxNumerator(uxNumerator__15), +.o_uyNumerator(uyNumerator__15), +.o_uyCost(uyCost__15), +.o_uxQuotient(uxQuotient__15), +.o_uyQuotient(uyQuotient__15) +); + +InternalsBlock pipeReg14( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__13), +.i_cost(cost__13), +.i_sinp(sinp__13), +.i_cosp(cosp__13), +.i_sintCosp(sintCosp__13), +.i_sintSinp(sintSinp__13), +.i_uz2(uz2__13), +.i_uxUz(uxUz__13), +.i_uyUz(uyUz__13), +.i_uySintSinp(uySintSinp__13), +.i_oneMinusUz2(oneMinusUz2__13), +.i_uyUzSintCosp(uyUzSintCosp__13), +.i_uxUzSintCosp(uxUzSintCosp__13), +.i_uxSintSinp(uxSintSinp__13), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__13), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__13), +.i_uxCost(uxCost__13), +.i_uzCost(uzCost__13), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__13), +.i_uxNumerator(uxNumerator__13), +.i_uyNumerator(uyNumerator__13), +.i_uyCost(uyCost__13), +.i_uxQuotient(uxQuotient__13), +.i_uyQuotient(uyQuotient__13), +//Outputs +.o_sint(sint__14), +.o_cost(cost__14), +.o_sinp(sinp__14), +.o_cosp(cosp__14), +.o_sintCosp(sintCosp__14), +.o_sintSinp(sintSinp__14), +.o_uz2(uz2__14), +.o_uxUz(uxUz__14), +.o_uyUz(uyUz__14), +.o_uySintSinp(uySintSinp__14), +.o_oneMinusUz2(oneMinusUz2__14), +.o_uyUzSintCosp(uyUzSintCosp__14), +.o_uxUzSintCosp(uxUzSintCosp__14), +.o_uxSintSinp(uxSintSinp__14), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__14), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__14), +.o_uxCost(uxCost__14), +.o_uzCost(uzCost__14), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__14), +.o_uxNumerator(uxNumerator__14), +.o_uyNumerator(uyNumerator__14), +.o_uyCost(uyCost__14), +.o_uxQuotient(uxQuotient__14), +.o_uyQuotient(uyQuotient__14) +); + +InternalsBlock pipeReg13( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__12), +.i_cost(cost__12), +.i_sinp(sinp__12), +.i_cosp(cosp__12), +.i_sintCosp(sintCosp__12), +.i_sintSinp(sintSinp__12), +.i_uz2(uz2__12), +.i_uxUz(uxUz__12), +.i_uyUz(uyUz__12), +.i_uySintSinp(uySintSinp__12), +.i_oneMinusUz2(oneMinusUz2__12), +.i_uyUzSintCosp(uyUzSintCosp__12), +.i_uxUzSintCosp(uxUzSintCosp__12), +.i_uxSintSinp(uxSintSinp__12), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__12), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__12), +.i_uxCost(uxCost__12), +.i_uzCost(uzCost__12), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__12), +.i_uxNumerator(uxNumerator__12), +.i_uyNumerator(uyNumerator__12), +.i_uyCost(uyCost__12), +.i_uxQuotient(uxQuotient__12), +.i_uyQuotient(uyQuotient__12), +//Outputs +.o_sint(sint__13), +.o_cost(cost__13), +.o_sinp(sinp__13), +.o_cosp(cosp__13), +.o_sintCosp(sintCosp__13), +.o_sintSinp(sintSinp__13), +.o_uz2(uz2__13), +.o_uxUz(uxUz__13), +.o_uyUz(uyUz__13), +.o_uySintSinp(uySintSinp__13), +.o_oneMinusUz2(oneMinusUz2__13), +.o_uyUzSintCosp(uyUzSintCosp__13), +.o_uxUzSintCosp(uxUzSintCosp__13), +.o_uxSintSinp(uxSintSinp__13), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__13), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__13), +.o_uxCost(uxCost__13), +.o_uzCost(uzCost__13), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__13), +.o_uxNumerator(uxNumerator__13), +.o_uyNumerator(uyNumerator__13), +.o_uyCost(uyCost__13), +.o_uxQuotient(uxQuotient__13), +.o_uyQuotient(uyQuotient__13) +); + +InternalsBlock pipeReg12( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__11), +.i_cost(cost__11), +.i_sinp(sinp__11), +.i_cosp(cosp__11), +.i_sintCosp(sintCosp__11), +.i_sintSinp(sintSinp__11), +.i_uz2(uz2__11), +.i_uxUz(uxUz__11), +.i_uyUz(uyUz__11), +.i_uySintSinp(uySintSinp__11), +.i_oneMinusUz2(oneMinusUz2__11), +.i_uyUzSintCosp(uyUzSintCosp__11), +.i_uxUzSintCosp(uxUzSintCosp__11), +.i_uxSintSinp(uxSintSinp__11), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__11), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__11), +.i_uxCost(uxCost__11), +.i_uzCost(uzCost__11), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__11), +.i_uxNumerator(uxNumerator__11), +.i_uyNumerator(uyNumerator__11), +.i_uyCost(uyCost__11), +.i_uxQuotient(uxQuotient__11), +.i_uyQuotient(uyQuotient__11), +//Outputs +.o_sint(sint__12), +.o_cost(cost__12), +.o_sinp(sinp__12), +.o_cosp(cosp__12), +.o_sintCosp(sintCosp__12), +.o_sintSinp(sintSinp__12), +.o_uz2(uz2__12), +.o_uxUz(uxUz__12), +.o_uyUz(uyUz__12), +.o_uySintSinp(uySintSinp__12), +.o_oneMinusUz2(oneMinusUz2__12), +.o_uyUzSintCosp(uyUzSintCosp__12), +.o_uxUzSintCosp(uxUzSintCosp__12), +.o_uxSintSinp(uxSintSinp__12), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__12), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__12), +.o_uxCost(uxCost__12), +.o_uzCost(uzCost__12), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__12), +.o_uxNumerator(uxNumerator__12), +.o_uyNumerator(uyNumerator__12), +.o_uyCost(uyCost__12), +.o_uxQuotient(uxQuotient__12), +.o_uyQuotient(uyQuotient__12) +); + +InternalsBlock pipeReg11( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__10), +.i_cost(cost__10), +.i_sinp(sinp__10), +.i_cosp(cosp__10), +.i_sintCosp(sintCosp__10), +.i_sintSinp(sintSinp__10), +.i_uz2(uz2__10), +.i_uxUz(uxUz__10), +.i_uyUz(uyUz__10), +.i_uySintSinp(uySintSinp__10), +.i_oneMinusUz2(oneMinusUz2__10), +.i_uyUzSintCosp(uyUzSintCosp__10), +.i_uxUzSintCosp(uxUzSintCosp__10), +.i_uxSintSinp(uxSintSinp__10), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__10), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__10), +.i_uxCost(uxCost__10), +.i_uzCost(uzCost__10), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__10), +.i_uxNumerator(uxNumerator__10), +.i_uyNumerator(uyNumerator__10), +.i_uyCost(uyCost__10), +.i_uxQuotient(uxQuotient__10), +.i_uyQuotient(uyQuotient__10), +//Outputs +.o_sint(sint__11), +.o_cost(cost__11), +.o_sinp(sinp__11), +.o_cosp(cosp__11), +.o_sintCosp(sintCosp__11), +.o_sintSinp(sintSinp__11), +.o_uz2(uz2__11), +.o_uxUz(uxUz__11), +.o_uyUz(uyUz__11), +.o_uySintSinp(uySintSinp__11), +.o_oneMinusUz2(oneMinusUz2__11), +.o_uyUzSintCosp(uyUzSintCosp__11), +.o_uxUzSintCosp(uxUzSintCosp__11), +.o_uxSintSinp(uxSintSinp__11), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__11), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__11), +.o_uxCost(uxCost__11), +.o_uzCost(uzCost__11), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__11), +.o_uxNumerator(uxNumerator__11), +.o_uyNumerator(uyNumerator__11), +.o_uyCost(uyCost__11), +.o_uxQuotient(uxQuotient__11), +.o_uyQuotient(uyQuotient__11) +); + +InternalsBlock pipeReg10( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__9), +.i_cost(cost__9), +.i_sinp(sinp__9), +.i_cosp(cosp__9), +.i_sintCosp(sintCosp__9), +.i_sintSinp(sintSinp__9), +.i_uz2(uz2__9), +.i_uxUz(uxUz__9), +.i_uyUz(uyUz__9), +.i_uySintSinp(uySintSinp__9), +.i_oneMinusUz2(oneMinusUz2__9), +.i_uyUzSintCosp(uyUzSintCosp__9), +.i_uxUzSintCosp(uxUzSintCosp__9), +.i_uxSintSinp(uxSintSinp__9), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__9), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__9), +.i_uxCost(uxCost__9), +.i_uzCost(uzCost__9), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__9), +.i_uxNumerator(uxNumerator__9), +.i_uyNumerator(uyNumerator__9), +.i_uyCost(uyCost__9), +.i_uxQuotient(uxQuotient__9), +.i_uyQuotient(uyQuotient__9), +//Outputs +.o_sint(sint__10), +.o_cost(cost__10), +.o_sinp(sinp__10), +.o_cosp(cosp__10), +.o_sintCosp(sintCosp__10), +.o_sintSinp(sintSinp__10), +.o_uz2(uz2__10), +.o_uxUz(uxUz__10), +.o_uyUz(uyUz__10), +.o_uySintSinp(uySintSinp__10), +.o_oneMinusUz2(oneMinusUz2__10), +.o_uyUzSintCosp(uyUzSintCosp__10), +.o_uxUzSintCosp(uxUzSintCosp__10), +.o_uxSintSinp(uxSintSinp__10), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__10), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__10), +.o_uxCost(uxCost__10), +.o_uzCost(uzCost__10), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__10), +.o_uxNumerator(uxNumerator__10), +.o_uyNumerator(uyNumerator__10), +.o_uyCost(uyCost__10), +.o_uxQuotient(uxQuotient__10), +.o_uyQuotient(uyQuotient__10) +); + +InternalsBlock pipeReg9( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__8), +.i_cost(cost__8), +.i_sinp(sinp__8), +.i_cosp(cosp__8), +.i_sintCosp(sintCosp__8), +.i_sintSinp(sintSinp__8), +.i_uz2(uz2__8), +.i_uxUz(uxUz__8), +.i_uyUz(uyUz__8), +.i_uySintSinp(uySintSinp__8), +.i_oneMinusUz2(oneMinusUz2__8), +.i_uyUzSintCosp(uyUzSintCosp__8), +.i_uxUzSintCosp(uxUzSintCosp__8), +.i_uxSintSinp(uxSintSinp__8), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__8), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__8), +.i_uxCost(uxCost__8), +.i_uzCost(uzCost__8), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__8), +.i_uxNumerator(uxNumerator__8), +.i_uyNumerator(uyNumerator__8), +.i_uyCost(uyCost__8), +.i_uxQuotient(uxQuotient__8), +.i_uyQuotient(uyQuotient__8), +//Outputs +.o_sint(sint__9), +.o_cost(cost__9), +.o_sinp(sinp__9), +.o_cosp(cosp__9), +.o_sintCosp(sintCosp__9), +.o_sintSinp(sintSinp__9), +.o_uz2(uz2__9), +.o_uxUz(uxUz__9), +.o_uyUz(uyUz__9), +.o_uySintSinp(uySintSinp__9), +.o_oneMinusUz2(oneMinusUz2__9), +.o_uyUzSintCosp(uyUzSintCosp__9), +.o_uxUzSintCosp(uxUzSintCosp__9), +.o_uxSintSinp(uxSintSinp__9), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__9), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__9), +.o_uxCost(uxCost__9), +.o_uzCost(uzCost__9), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__9), +.o_uxNumerator(uxNumerator__9), +.o_uyNumerator(uyNumerator__9), +.o_uyCost(uyCost__9), +.o_uxQuotient(uxQuotient__9), +.o_uyQuotient(uyQuotient__9) +); + +InternalsBlock pipeReg8( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__7), +.i_cost(cost__7), +.i_sinp(sinp__7), +.i_cosp(cosp__7), +.i_sintCosp(sintCosp__7), +.i_sintSinp(sintSinp__7), +.i_uz2(uz2__7), +.i_uxUz(uxUz__7), +.i_uyUz(uyUz__7), +.i_uySintSinp(uySintSinp__7), +.i_oneMinusUz2(oneMinusUz2__7), +.i_uyUzSintCosp(uyUzSintCosp__7), +.i_uxUzSintCosp(uxUzSintCosp__7), +.i_uxSintSinp(uxSintSinp__7), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__7), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__7), +.i_uxCost(uxCost__7), +.i_uzCost(uzCost__7), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__7), +.i_uxNumerator(uxNumerator__7), +.i_uyNumerator(uyNumerator__7), +.i_uyCost(uyCost__7), +.i_uxQuotient(uxQuotient__7), +.i_uyQuotient(uyQuotient__7), +//Outputs +.o_sint(sint__8), +.o_cost(cost__8), +.o_sinp(sinp__8), +.o_cosp(cosp__8), +.o_sintCosp(sintCosp__8), +.o_sintSinp(sintSinp__8), +.o_uz2(uz2__8), +.o_uxUz(uxUz__8), +.o_uyUz(uyUz__8), +.o_uySintSinp(uySintSinp__8), +.o_oneMinusUz2(oneMinusUz2__8), +.o_uyUzSintCosp(uyUzSintCosp__8), +.o_uxUzSintCosp(uxUzSintCosp__8), +.o_uxSintSinp(uxSintSinp__8), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__8), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__8), +.o_uxCost(uxCost__8), +.o_uzCost(uzCost__8), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__8), +.o_uxNumerator(uxNumerator__8), +.o_uyNumerator(uyNumerator__8), +.o_uyCost(uyCost__8), +.o_uxQuotient(uxQuotient__8), +.o_uyQuotient(uyQuotient__8) +); + +InternalsBlock pipeReg7( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__6), +.i_cost(cost__6), +.i_sinp(sinp__6), +.i_cosp(cosp__6), +.i_sintCosp(sintCosp__6), +.i_sintSinp(sintSinp__6), +.i_uz2(uz2__6), +.i_uxUz(uxUz__6), +.i_uyUz(uyUz__6), +.i_uySintSinp(uySintSinp__6), +.i_oneMinusUz2(oneMinusUz2__6), +.i_uyUzSintCosp(uyUzSintCosp__6), +.i_uxUzSintCosp(uxUzSintCosp__6), +.i_uxSintSinp(uxSintSinp__6), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__6), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__6), +.i_uxCost(uxCost__6), +.i_uzCost(uzCost__6), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__6), +.i_uxNumerator(uxNumerator__6), +.i_uyNumerator(uyNumerator__6), +.i_uyCost(uyCost__6), +.i_uxQuotient(uxQuotient__6), +.i_uyQuotient(uyQuotient__6), +//Outputs +.o_sint(sint__7), +.o_cost(cost__7), +.o_sinp(sinp__7), +.o_cosp(cosp__7), +.o_sintCosp(sintCosp__7), +.o_sintSinp(sintSinp__7), +.o_uz2(uz2__7), +.o_uxUz(uxUz__7), +.o_uyUz(uyUz__7), +.o_uySintSinp(uySintSinp__7), +.o_oneMinusUz2(oneMinusUz2__7), +.o_uyUzSintCosp(uyUzSintCosp__7), +.o_uxUzSintCosp(uxUzSintCosp__7), +.o_uxSintSinp(uxSintSinp__7), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__7), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__7), +.o_uxCost(uxCost__7), +.o_uzCost(uzCost__7), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__7), +.o_uxNumerator(uxNumerator__7), +.o_uyNumerator(uyNumerator__7), +.o_uyCost(uyCost__7), +.o_uxQuotient(uxQuotient__7), +.o_uyQuotient(uyQuotient__7) +); + +InternalsBlock pipeReg6( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__5), +.i_cost(cost__5), +.i_sinp(sinp__5), +.i_cosp(cosp__5), +.i_sintCosp(sintCosp__5), +.i_sintSinp(sintSinp__5), +.i_uz2(uz2__5), +.i_uxUz(uxUz__5), +.i_uyUz(uyUz__5), +.i_uySintSinp(uySintSinp__5), +.i_oneMinusUz2(oneMinusUz2__5), +.i_uyUzSintCosp(uyUzSintCosp__5), +.i_uxUzSintCosp(uxUzSintCosp__5), +.i_uxSintSinp(uxSintSinp__5), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__5), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__5), +.i_uxCost(uxCost__5), +.i_uzCost(uzCost__5), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__5), +.i_uxNumerator(uxNumerator__5), +.i_uyNumerator(uyNumerator__5), +.i_uyCost(uyCost__5), +.i_uxQuotient(uxQuotient__5), +.i_uyQuotient(uyQuotient__5), +//Outputs +.o_sint(sint__6), +.o_cost(cost__6), +.o_sinp(sinp__6), +.o_cosp(cosp__6), +.o_sintCosp(sintCosp__6), +.o_sintSinp(sintSinp__6), +.o_uz2(uz2__6), +.o_uxUz(uxUz__6), +.o_uyUz(uyUz__6), +.o_uySintSinp(uySintSinp__6), +.o_oneMinusUz2(oneMinusUz2__6), +.o_uyUzSintCosp(uyUzSintCosp__6), +.o_uxUzSintCosp(uxUzSintCosp__6), +.o_uxSintSinp(uxSintSinp__6), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__6), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__6), +.o_uxCost(uxCost__6), +.o_uzCost(uzCost__6), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__6), +.o_uxNumerator(uxNumerator__6), +.o_uyNumerator(uyNumerator__6), +.o_uyCost(uyCost__6), +.o_uxQuotient(uxQuotient__6), +.o_uyQuotient(uyQuotient__6) +); + +InternalsBlock pipeReg5( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__4), +.i_cost(cost__4), +.i_sinp(sinp__4), +.i_cosp(cosp__4), +.i_sintCosp(sintCosp__4), +.i_sintSinp(sintSinp__4), +.i_uz2(uz2__4), +.i_uxUz(uxUz__4), +.i_uyUz(uyUz__4), +.i_uySintSinp(uySintSinp__4), +.i_oneMinusUz2(oneMinusUz2__4), +.i_uyUzSintCosp(uyUzSintCosp__4), +.i_uxUzSintCosp(uxUzSintCosp__4), +.i_uxSintSinp(uxSintSinp__4), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__4), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__4), +.i_uxCost(uxCost__4), +.i_uzCost(uzCost__4), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__4), +.i_uxNumerator(uxNumerator__4), +.i_uyNumerator(uyNumerator__4), +.i_uyCost(uyCost__4), +.i_uxQuotient(uxQuotient__4), +.i_uyQuotient(uyQuotient__4), +//Outputs +.o_sint(sint__5), +.o_cost(cost__5), +.o_sinp(sinp__5), +.o_cosp(cosp__5), +.o_sintCosp(sintCosp__5), +.o_sintSinp(sintSinp__5), +.o_uz2(uz2__5), +.o_uxUz(uxUz__5), +.o_uyUz(uyUz__5), +.o_uySintSinp(uySintSinp__5), +.o_oneMinusUz2(oneMinusUz2__5), +.o_uyUzSintCosp(uyUzSintCosp__5), +.o_uxUzSintCosp(uxUzSintCosp__5), +.o_uxSintSinp(uxSintSinp__5), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__5), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__5), +.o_uxCost(uxCost__5), +.o_uzCost(uzCost__5), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__5), +.o_uxNumerator(uxNumerator__5), +.o_uyNumerator(uyNumerator__5), +.o_uyCost(uyCost__5), +.o_uxQuotient(uxQuotient__5), +.o_uyQuotient(uyQuotient__5) +); + + +//since these will be replaced later + + + assign sint__0 = 32'b00000000000000000000000000000000; + assign cost__0 = 32'b00000000000000000000000000000000; + assign sinp__0 = 32'b00000000000000000000000000000000; + assign cosp__0 = 32'b00000000000000000000000000000000; + assign sintCosp__0 = 32'b00000000000000000000000000000000; + assign sintSinp__0 = 32'b00000000000000000000000000000000; + assign uz2__0 = 0; + assign uxUz__0 = 32'b00000000000000000000000000000000; + assign uyUz__0 = 32'b00000000000000000000000000000000; + assign uySintSinp__0 = 32'b00000000000000000000000000000000; + assign oneMinusUz2__0 = 0; + assign uyUzSintCosp__0 = 32'b00000000000000000000000000000000; + assign uxUzSintCosp__0 = 32'b00000000000000000000000000000000; + assign uxSintSinp__0 = 32'b00000000000000000000000000000000; + assign sqrtOneMinusUz2__0 = 32'b00000000000000000000000000000000; + assign sintCospSqrtOneMinusUz2__0 = 32'b00000000000000000000000000000000; + assign uxCost__0 = 32'b00000000000000000000000000000000; + assign uzCost__0 = 32'b00000000000000000000000000000000; + assign sqrtOneMinusUz2_inv__0 = 32'b00000000000000000000000000000000; + assign uxNumerator__0 = 32'b00000000000000000000000000000000; + assign uyNumerator__0 = 32'b00000000000000000000000000000000; + assign uyCost__0 = 32'b00000000000000000000000000000000; + assign uxQuotient__0 = 32'b00000000000000000000000000000000; + assign uyQuotient__0 = 32'b00000000000000000000000000000000; + +InternalsBlock pipeReg1( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__0), +.i_cost(cost__0), +.i_sinp(sinp__0), +.i_cosp(cosp__0), +.i_sintCosp(sintCosp__0), +.i_sintSinp(sintSinp__0), +.i_uz2(uz2__0), +.i_uxUz(uxUz__0), +.i_uyUz(uyUz__0), +.i_uySintSinp(uySintSinp__0), +.i_oneMinusUz2(oneMinusUz2__0), +.i_uyUzSintCosp(uyUzSintCosp__0), +.i_uxUzSintCosp(uxUzSintCosp__0), +.i_uxSintSinp(uxSintSinp__0), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__0), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__0), +.i_uxCost(uxCost__0), +.i_uzCost(uzCost__0), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__0), +.i_uxNumerator(uxNumerator__0), +.i_uyNumerator(uyNumerator__0), +.i_uyCost(uyCost__0), +.i_uxQuotient(uxQuotient__0), +.i_uyQuotient(uyQuotient__0), +//Outputs +.o_sint(sint__1), +.o_cost(cost__1), +.o_sinp(sinp__1), +.o_cosp(cosp__1), +.o_sintCosp(sintCosp__1), +.o_sintSinp(sintSinp__1), +.o_uz2(uz2__1), +.o_uxUz(uxUz__1), +.o_uyUz(uyUz__1), +.o_uySintSinp(uySintSinp__1), +.o_oneMinusUz2(oneMinusUz2__1), +.o_uyUzSintCosp(uyUzSintCosp__1), +.o_uxUzSintCosp(uxUzSintCosp__1), +.o_uxSintSinp(uxSintSinp__1), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__1), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__1), +.o_uxCost(uxCost__1), +.o_uzCost(uzCost__1), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__1), +.o_uxNumerator(uxNumerator__1), +.o_uyNumerator(uyNumerator__1), +.o_uyCost(uyCost__1), +.o_uxQuotient(uxQuotient__1), +.o_uyQuotient(uyQuotient__1) +); + +//-------------SYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is the end of the generate statement, and the beginning of the +//synchronous logic. On the clock event, the outputs calculated from +//this block are put on the output pins for reading (registered +//outputs, as per the convention). + + + + +//Assign outputs from block on positive clock edge. +always @ (posedge clock) begin + if(reset_new) begin + //Reset internal non-pipelined registers here. + ux_scatterer <= 32'h00000000; + uy_scatterer <= 32'h00000000; + uz_scatterer <= 32'h7FFFFFFF; + end else if (enable) begin + ux_scatterer <= new_ux; + uy_scatterer <= new_uy; + uz_scatterer <= new_uz; + end +end + +//-------------ASYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is where the asynchronous logic takes place. Things that +//occur here include setting up wiring to send to the multipliers, +//divide unit, and square root unit. Also, products brought in +//from the wrapper are placed on the appropriate wires for placement +//in the pipeline. + + + + +//-------------OPERAND SETUP---------------------- + + +//NAMING CONVENTION: +//opX_Y_Z, op stands for operand, X stands for the multiplication number for +//that clock cycle, Y stands for the clock cycle, Z is either 1 or 2 for the +//first or second operand for this multiply +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calculated will be ready for the Xth register +//location, where 0 is the register prior to any calculations being done, 1 is +//after the 1st clock cycle of calculation, etc. + +//CC 2 +assign op1_2_1 = i_uz1; +assign op1_2_2 = i_uz1; + +//CC 3 +//SUBTRACTION, see math results + +//CC 4 +assign op1_4_1 = i_ux3; +assign op1_4_2 = i_uz3; + +//CC 5 -- NOOP, line up with reflector + +//CC `SQRT+5 -- Started in CC 6 +assign sqrtOperand1_6 = oneMinusUz2__5; + +//CC `SQRT+`DIV+6 -- Started in CC `SQRT+5 +assign divNumerator1_16 = `INTMAX_2; +//assign divDenominator1_16 = sqrtOneMinusUz2[`SQRT+5]; +assign divDenominator1_16 = new_sqrtOneMinusUz2; + +//CC `SQRT+`DIV+3 +assign op1_33_1 = sint_Mem; +assign op1_33_2 = cosp_Mem; + +assign op2_33_1 = sint_Mem; +assign op2_33_2 = sinp_Mem; + +assign op3_33_1 = i_uy32; +assign op3_33_2 = i_uz32; + +//CC `SQRT+`DIV+4 +assign op1_34_1 = i_ux33; +assign op1_34_2 = sintSinp__33; + +assign op2_34_1 = i_uy33; +assign op2_34_2 = sintSinp__33; + +assign op3_34_1 = uxUz__33; +assign op3_34_2 = sintCosp__33; + +assign op4_34_1 = uyUz__33; +assign op4_34_2 = sintCosp__33; + +//CC `SQRT+`DIV+5 +//2 SUBS (see math results) +//`DIVISION COMPLETE (see math results) + +//CC `SQRT+`DIV+6 -- Division is now complete and can be read. +assign op1_36_1 = uxNumerator__35; +assign op1_36_2 = new_sqrtOneMinusUz2_inv; + + +assign op2_36_1 = uyNumerator__35; +assign op2_36_2 = new_sqrtOneMinusUz2_inv; + +assign op3_36_1 = sintCosp__35; +assign op3_36_2 = sqrtOneMinusUz2__35; + +assign op4_36_1 = i_ux35; +assign op4_36_2 = cost__35; + +assign op5_36_1 = i_uy35; +assign op5_36_2 = cost__35; + +assign op6_36_1 = i_uz35; +assign op6_36_2 = cost__35; + + +//-------------MATH RESULTS---------------------- + + +//NAMING CONVENTION: +//new_VAR means that the variable named VAR will be stored into the register +//pipeline at the clock cycle indicated by the comments above it. +// +//prod stands for product, quot stands for quotient, sqrt stands for square root +//prodX_Y means the Xth product which started calculation at the Yth clock cycle +//Similarly for quot and sqrtResult. +// +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calculated will be ready for the Xth register +//location, where 0 is the register prior to any calculations being done, 1 is +//after the 1st clock cycle of calculation, etc. + + +//Used to determine whether or not the divide operation overflowed. +//or U1(div_overflow, quot1_16[62], quot1_16[61], quot1_16[60], quot1_16[59], quot1_16[58], quot1_16[57], quot1_16[56], quot1_16[55], quot1_16[54], quot1_16[53], quot1_16[52], quot1_16[51], quot1_16[50], quot1_16[49], quot1_16[48], quot1_16[47]); +assign div_overflow = quot1_16[62]| quot1_16[61]| quot1_16[60]| quot1_16[59]| quot1_16[58]| quot1_16[57]| quot1_16[56]| quot1_16[55]| quot1_16[54]| quot1_16[53]| quot1_16[52]| quot1_16[51]| quot1_16[50]| quot1_16[49]| quot1_16[48]| quot1_16[47]; + +//Used to determine whether or not the multiply operation overflowed. +//or U2(toAnd1_36_1, prod1_36[62], prod1_36[61], prod1_36[60], prod1_36[59], prod1_36[58], prod1_36[57], prod1_36[56], prod1_36[55], prod1_36[54], prod1_36[53], prod1_36[52], prod1_36[51], prod1_36[50], prod1_36[49], prod1_36[48], prod1_36[47], prod1_36[46]); +assign toAnd1_36_1 = prod1_36[62]| prod1_36[61]| prod1_36[60]| prod1_36[59]| prod1_36[58]| prod1_36[57]| prod1_36[56]| prod1_36[55]| prod1_36[54]| prod1_36[53]| prod1_36[52]| prod1_36[51]| prod1_36[50]| prod1_36[49]| prod1_36[48]| prod1_36[47]| prod1_36[46]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U3(toAnd1_36_2, ~prod1_36[62], ~prod1_36[61], ~prod1_36[60], ~prod1_36[59], ~prod1_36[58], ~prod1_36[57], ~prod1_36[56], ~prod1_36[55], ~prod1_36[54], ~prod1_36[53], ~prod1_36[52], ~prod1_36[51], ~prod1_36[50], ~prod1_36[49], ~prod1_36[48], ~prod1_36[47], ~prod1_36[46]); +assign toAnd1_36_2 = ~prod1_36[62]| ~prod1_36[61]| ~prod1_36[60]| ~prod1_36[59]| ~prod1_36[58]| ~prod1_36[57]| ~prod1_36[56]| ~prod1_36[55]| ~prod1_36[54]| ~prod1_36[53]| ~prod1_36[52]| ~prod1_36[51]| ~prod1_36[50]| ~prod1_36[49]| ~prod1_36[48]| ~prod1_36[47]| ~prod1_36[46]; + +//and U4(overflow1_36, ~prod1_36[63], toAnd1_36_1); +assign overflow1_36 = ~prod1_36[63]| toAnd1_36_1; +//and U5(negOverflow1_36, prod1_36[63], toAnd1_36_2); +assign negOverflow1_36 = prod1_36[63]| toAnd1_36_2; + + +//Used to determine whether or not the multiply operation overflowed. +//or U6(toAnd2_36_1, prod2_36[62], prod2_36[61], prod2_36[60], prod2_36[59], prod2_36[58], prod2_36[57], prod2_36[56], prod2_36[55], prod2_36[54], prod2_36[53], prod2_36[52], prod2_36[51], prod2_36[50], prod2_36[49], prod2_36[48], prod2_36[47], prod2_36[46]); +assign toAnd2_36_1 = prod2_36[62]| prod2_36[61]| prod2_36[60]| prod2_36[59]| prod2_36[58]| prod2_36[57]| prod2_36[56]| prod2_36[55]| prod2_36[54]| prod2_36[53]| prod2_36[52]| prod2_36[51]| prod2_36[50]| prod2_36[49]| prod2_36[48]| prod2_36[47]| prod2_36[46]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U7(toAnd2_36_2, ~prod2_36[62], ~prod2_36[61], ~prod2_36[60], ~prod2_36[59], ~prod2_36[58], ~prod2_36[57], ~prod2_36[56], ~prod2_36[55], ~prod2_36[54], ~prod2_36[53], ~prod2_36[52], ~prod2_36[51], ~prod2_36[50], ~prod2_36[49], ~prod2_36[48], ~prod2_36[47], ~prod2_36[46]); +assign toAnd2_36_2 = ~prod2_36[62]| ~prod2_36[61]| ~prod2_36[60]| ~prod2_36[59]| ~prod2_36[58]| ~prod2_36[57]| ~prod2_36[56]| ~prod2_36[55]| ~prod2_36[54]| ~prod2_36[53]| ~prod2_36[52]| ~prod2_36[51]| ~prod2_36[50]| ~prod2_36[49]| ~prod2_36[48]| ~prod2_36[47]| ~prod2_36[46]; + +//and U8(overflow2_36, ~prod2_36[63], toAnd2_36_1); +assign overflow2_36 = ~prod2_36[63]|toAnd2_36_1; +//and U9(negOverflow2_36, prod2_36[63], toAnd2_36_2); +assign negOverflow2_36 = prod2_36[63]|toAnd2_36_2; + + + +//CC 2 +assign new_uz2 = prod1_2; +//CC 3 +sub_64b oneMinusUz2_sub( + .dataa(`INTMAX_2), + .datab(uz2__2), + .result(new_oneMinusUz2) + ); + +//CC 4 +assign new_uxUz = prod1_4; +//CC `SQRT+5 +assign new_sqrtOneMinusUz2 = sqrtResult1_6; +//CC `SQRT+`DIV+3 +assign new_sintCosp = prod1_33; +assign new_sintSinp = prod2_33; +assign new_uyUz = prod3_33; +//CC `SQRT+`DIV+4 +assign new_sint = sint_Mem; +assign new_cost = cost_Mem; +assign new_sinp = sinp_Mem; +assign new_cosp = cosp_Mem; +assign new_uxSintSinp = prod1_34; +assign new_uySintSinp = prod2_34; +assign new_uxUzSintCosp = prod3_34; +assign new_uyUzSintCosp = prod4_34; +//CC `SQRT+`DIV+5 +sub_32b uxNumer_sub( + .dataa(uxUzSintCosp__34), + .datab(uySintSinp__34), + .overflow(uxNumerOverflow), + .result(new_uxNumerator) + ); + +add_32b uyNumer_add( + .dataa(uyUzSintCosp__34), + .datab(uxSintSinp__34), + .overflow(uyNumerOverflow), + .result(new_uyNumerator) + ); + + +//Possibility for division overflow (whereby the inverse is too large). Data storage for this +//value is 15 bits left of the decimal, and 16 bits to the right. +assign new_sqrtOneMinusUz2_inv = (div_overflow) ? `INTMAX : {quot1_16[63:63], quot1_16[46:16]}; + +//CC `SQRT+`DIV+6 +always @ (overflow1_36 or negOverflow1_36 or prod1_36 or overflow2_36 or negOverflow2_36 or prod2_36) begin + case ({overflow1_36, negOverflow1_36}) + 0: new_uxQuotient = {prod1_36[63:63], prod1_36[45:15]}; + 1: new_uxQuotient = `INTMIN; + 2: new_uxQuotient = `INTMAX; + //Should never occur + 3: new_uxQuotient = {prod1_36[63:63], prod1_36[45:15]}; + endcase + + case ({overflow2_36, negOverflow2_36}) + + 0: new_uyQuotient = {prod2_36[63:63], prod2_36[45:15]}; + 1: new_uyQuotient = `INTMIN; + 2: new_uyQuotient = `INTMAX; + //Should never occur + 3: new_uyQuotient = {prod2_36[63:63], prod2_36[45:15]}; + endcase +end + +//always @* begin +// new_uxQuotient = {prod1_36[63:63], prod1_36[47:16]}; +// new_uyQuotient = {prod2_36[63:63], prod2_36[47:16]}; +//end + +assign new_sintCospSqrtOneMinusUz2 = prod3_36; +assign new_uxCost = prod4_36; +assign new_uyCost = prod5_36; +assign new_uzCost = prod6_36; + + + +//-----------------------FINAL RESULT CALCULATIONS-------------- +// +// +// +// +// +// +// +//At this point, all calculations have been completed, save the +//final results. This part of the code decides whether or not the +//current calculation involved a normal (orthogonal) incident or not, +//and uses this information to determine how to calculate the +//final results. Final results are put on wires new_ux, new_uy, and +//new_uz, where they are output to registers ux_scatterer, +//uy_scatterer, and uz_scatterer on the clock event for synchronization +//(registered outputs, as per the convention). + + + +//Determine whether or not the photon calculation was done on a photon that +//was normal (orthogonal) to the plane of interest. This is to avoid divide +//by zero errors +always @ (i_uz36) begin + //If uz >= `INTMAX-3 || uz <= -`INTMAX+3, normal incident + if(i_uz36 == 32'h7FFFFFFF || i_uz36 == 32'h7FFFFFFE || i_uz36 == 32'h7FFFFFFD || i_uz36 == 32'h7FFFFFFC || i_uz36 == 32'h80000000 || i_uz36 == 32'h80000001 || i_uz36 == 32'h80000002 || i_uz36 == 32'h80000003 || i_uz36 == 32'h80000004) begin + normalIncident = 1'b1; + end else begin + normalIncident = 1'b0; + end +end + + + +//Assign calculation values for final ux result +assign ux_add_1 = (normalIncident) ? sintCosp__36 : uxQuotient__36; +assign ux_add_2 = (normalIncident) ? 32'b0 : uxCost__36; + +add_32b ux_add( + .dataa(ux_add_1), + .datab(ux_add_2), + .overflow(uxOverflow), + .result(new_ux) + ); + +//Assign calculation values for final uy result +assign uy_add_1 = (normalIncident) ? sintSinp__36 : uyQuotient__36; +assign uy_add_2 = (normalIncident) ? 32'b0 : uyCost__36; + +add_32b uy_add( + .dataa(uy_add_1), + .datab(uy_add_2), + .overflow(uyOverflow), + .result(new_uy) + ); + + + + +//Assign calculation values for final uz result. +//First MUX implements SIGN(uz) function. +assign normalUz = (i_uz36 >=0) ? cost__36 : -cost__36; +assign uz_sub_1 = (normalIncident) ? normalUz : uzCost__36; +assign uz_sub_2 = (normalIncident) ? 32'b0 : sintCospSqrtOneMinusUz2__36; + +sub_32b uz_sub( + .dataa(uz_sub_1), + .datab(uz_sub_2), + .overflow(uzOverflow), + .result(new_uz) + ); + + + +endmodule + + +//*********************************** +//Mathematical modules +//*********************************** + +module sub_64b (dataa, datab, result); + + input [63:0] dataa; + input [63:0] datab; + output [63:0] result; + + assign result = dataa - datab; + +endmodule + +module add_32b (dataa, datab, overflow, result); + + input [31:0] dataa; + input [31:0] datab; + output overflow; + output [31:0] result; + + wire [32:0]computation; //one extra bit to account for overflow + + assign computation = dataa + datab; + assign overflow = computation[32]; + assign result = computation[31:0]; + +endmodule + +module sub_32b (dataa, datab, overflow, result); + + input [31:0] dataa; + input [31:0] datab; + output overflow; + output [31:0] result; + + wire [32:0]computation; //one extra bit to account for overflow + + assign computation = dataa - datab; + assign overflow = computation[32]; + assign result = computation[31:0]; + +endmodule + +module Mult_32b (dataa, datab, result); //now signed version! + + input [31:0]dataa; + input [31:0]datab; + output [63:0]result; + + // assign result = dataa * datab; + + wire [31:0]a; + wire [31:0]b; + assign a = dataa; + assign b = datab; + + reg [63:0]c; + assign result = c; + + reg is_neg_a; + reg is_neg_b; + reg [31:0]a_tmp; + reg [31:0]b_tmp; + reg [63:0]mult_tmp; + reg [63:0]c_tmp; + +always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +begin + if(a[31] == 1) begin + a_tmp = -a; + is_neg_a = 1; + end else + begin + a_tmp = a; + is_neg_a = 0; + end + + if(b[31] == 1) begin + b_tmp = -b; + is_neg_b = 1; + end else + begin + b_tmp = b; + is_neg_b = 0; + end + + mult_tmp = a_tmp * b_tmp; + + if( is_neg_a != is_neg_b) begin + c_tmp = -mult_tmp; + end else + begin + c_tmp = mult_tmp; + end +end + +always@(c_tmp) +begin + c = c_tmp; +end + +endmodule + + + +module Div_64b (clock, denom, numer, quotient, remain); + input clock; + input [63:0]numer; + input [31:0]denom; + output [63:0]quotient; + reg [63:0]quotient; + output [31:0]remain; + reg [31:0]remain; + + wire [63:0]quotient_temp; + wire [31:0]remain_temp; + Div_64b_unsigned div_temp(.clock(clock), .denom_(denom), .numer_(numer), .quotient(quotient_temp), .remain(remain_temp)); + + always @ (numer or denom or quotient_temp or remain_temp) begin + if ( numer[63]^denom[31] ) begin // only one is negative + quotient = -quotient_temp; + remain = -remain_temp; + end else begin + quotient = quotient_temp; + remain = remain_temp; + end + end + +endmodule + + +/*module Div_64b (clock, denom, numer, quotient, remain); + input clock; + input [63:0]numer; + input [31:0]denom; + output [63:0]quotient; + reg [63:0]quotient; + output [31:0]remain; + reg [31:0]remain; */ + +module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); + input clock; + input [63:0]numer_; + input [31:0]denom_; + output [63:0]quotient; + output [31:0]remain; + + reg [63:0]numer; + reg [31:0]denom0; + + always @ (posedge clock) + begin + numer <= numer_; + denom0 <= denom_; + end + +///////////////////////////////////////////////////Unchanged starts here + reg [94:0]numer_temp_63; //need to add bits + reg [94:0]numer_temp_62; + reg [94:0]numer_temp_61; + reg [94:0]numer_temp_60_d, numer_temp_60_q; + reg [94:0]numer_temp_59; + reg [94:0]numer_temp_58; + reg [94:0]numer_temp_57_d, numer_temp_57_q; + reg [94:0]numer_temp_56; + reg [94:0]numer_temp_55; + reg [94:0]numer_temp_54_d, numer_temp_54_q; + reg [94:0]numer_temp_53; + reg [94:0]numer_temp_52; + reg [94:0]numer_temp_51_d, numer_temp_51_q; + reg [94:0]numer_temp_50; + reg [94:0]numer_temp_49; + reg [94:0]numer_temp_48_d, numer_temp_48_q; + reg [94:0]numer_temp_47; + reg [94:0]numer_temp_46; + reg [94:0]numer_temp_45_d, numer_temp_45_q; + reg [94:0]numer_temp_44; + reg [94:0]numer_temp_43; + reg [94:0]numer_temp_42_d, numer_temp_42_q; + reg [94:0]numer_temp_41; + reg [94:0]numer_temp_40; + reg [94:0]numer_temp_39_d, numer_temp_39_q; + reg [94:0]numer_temp_38; + reg [94:0]numer_temp_37; + reg [94:0]numer_temp_36_d, numer_temp_36_q; + reg [94:0]numer_temp_35; + reg [94:0]numer_temp_34; + reg [94:0]numer_temp_33_d, numer_temp_33_q; + reg [94:0]numer_temp_32; + reg [94:0]numer_temp_31; + reg [94:0]numer_temp_30_d, numer_temp_30_q; + reg [94:0]numer_temp_29; + reg [94:0]numer_temp_28; + reg [94:0]numer_temp_27_d, numer_temp_27_q; + reg [94:0]numer_temp_26; + reg [94:0]numer_temp_25; + reg [94:0]numer_temp_24; + reg [94:0]numer_temp_23_d, numer_temp_23_q; + reg [94:0]numer_temp_22; + reg [94:0]numer_temp_21; + reg [94:0]numer_temp_20; + reg [94:0]numer_temp_19_d, numer_temp_19_q; + reg [94:0]numer_temp_18; + reg [94:0]numer_temp_17; + reg [94:0]numer_temp_16; + reg [94:0]numer_temp_15_d, numer_temp_15_q; + reg [94:0]numer_temp_14; + reg [94:0]numer_temp_13; + reg [94:0]numer_temp_12; + reg [94:0]numer_temp_11_d, numer_temp_11_q; + reg [94:0]numer_temp_10; + reg [94:0]numer_temp_9; + reg [94:0]numer_temp_8; + reg [94:0]numer_temp_7_d, numer_temp_7_q; + reg [94:0]numer_temp_6; + reg [94:0]numer_temp_5; + reg [94:0]numer_temp_4; + reg [94:0]numer_temp_3_d, numer_temp_3_q; + reg [94:0]numer_temp_2; + reg [94:0]numer_temp_1_d, numer_temp_1_q; + reg [94:0]numer_temp_0; + reg [94:0]numer_temp; + + //The dummy pipeline (20 clock cycles) + reg [63:0]quo0_d; + reg [63:0]quo1_d; + reg [63:0]quo2_d; + reg [63:0]quo3_d; + reg [63:0]quo4_d; + reg [63:0]quo5_d; + reg [63:0]quo6_d; + reg [63:0]quo7_d; + reg [63:0]quo8_d; + reg [63:0]quo9_d; + reg [63:0]quo10_d; + reg [63:0]quo11_d; + reg [63:0]quo12_d; + reg [63:0]quo13_d; + reg [63:0]quo14_d; + reg [63:0]quo15_d; + reg [63:0]quo16_d; + reg [63:0]quo17_d; + reg [63:0]quo18_d; + reg [63:0]quo19_d; + + reg [63:0]quo0_q; + reg [63:0]quo1_q; + reg [63:0]quo2_q; + reg [63:0]quo3_q; + reg [63:0]quo4_q; + reg [63:0]quo5_q; + reg [63:0]quo6_q; + reg [63:0]quo7_q; + reg [63:0]quo8_q; + reg [63:0]quo9_q; + reg [63:0]quo10_q; + reg [63:0]quo11_q; + reg [63:0]quo12_q; + reg [63:0]quo13_q; + reg [63:0]quo14_q; + reg [63:0]quo15_q; + reg [63:0]quo16_q; + reg [63:0]quo17_q; + reg [63:0]quo18_q; + + reg [31:0]denom1; + reg [31:0]denom2; + reg [31:0]denom3; + reg [31:0]denom4; + reg [31:0]denom5; + reg [31:0]denom6; + reg [31:0]denom7; + reg [31:0]denom8; + reg [31:0]denom9; + reg [31:0]denom10; + reg [31:0]denom11; + reg [31:0]denom12; + reg [31:0]denom13; + reg [31:0]denom14; + reg [31:0]denom15; + reg [31:0]denom16; + reg [31:0]denom17; + reg [31:0]denom18; + reg [31:0]denom19; + + + always @(numer or denom0) begin + numer_temp_63 = {31'b0, numer}; + + //quo0[63] + if (numer_temp_63[94:63] >= denom0 ) begin + quo0_d[63] = 1'b1; + numer_temp_62 = {numer_temp_63[94:63] - denom0, numer_temp_63[62:0]}; + end else begin + quo0_d[63] = 1'b0; + numer_temp_62 = numer_temp_63; + end + + //quo0[62] + if (numer_temp_62[94:62] >= denom0 ) begin + quo0_d[62] = 1'b1; + numer_temp_61 = {numer_temp_62[94:62] - denom0, numer_temp_62[61:0]}; + end else begin + quo0_d[62] = 1'b0; + numer_temp_61 = numer_temp_62; + end + //quo0[61] + if (numer_temp_61[94:61] >= denom0 ) begin + quo0_d[61] = 1'b1; + numer_temp_60_d = {numer_temp_61[94:61] - denom0, numer_temp_61[60:0]}; + end else begin + quo0_d[61] = 1'b0; + numer_temp_60_d = numer_temp_61; + end + quo0_d[60:0] = 61'b0; + end + + always @ (posedge clock) begin + quo0_q <= quo0_d; + numer_temp_60_q <= numer_temp_60_d; + denom1 <= denom0; + end + + always @(numer_temp_60_q or denom1 or quo0_q) begin + quo1_d[63:61] = quo0_q[63:61]; + + //quo1_d[60] + if (numer_temp_60_q[94:60] >= denom1 ) begin + quo1_d[60] = 1'b1; + numer_temp_59 = {numer_temp_60_q[94:60] - denom1, numer_temp_60_q[59:0]}; + end else begin + quo1_d[60] = 1'b0; + numer_temp_59 = numer_temp_60_q; + end + //quo1_d[59] + if (numer_temp_59[94:59] >= denom1 ) begin + quo1_d[59] = 1'b1; + numer_temp_58 = {numer_temp_59[94:59] - denom1, numer_temp_59[58:0]}; + end else begin + quo1_d[59] = 1'b0; + numer_temp_58 = numer_temp_59; + end + //quo1_d[58] + if (numer_temp_58[94:58] >= denom1 ) begin + quo1_d[58] = 1'b1; + numer_temp_57_d = {numer_temp_58[94:58] - denom1, numer_temp_58[57:0]}; + end else begin + quo1_d[58] = 1'b0; + numer_temp_57_d = numer_temp_58; + end + quo1_d[57:0] = 58'b0; + end + + always @ (posedge clock) begin + quo1_q <= quo1_d; + numer_temp_57_q <= numer_temp_57_d; + denom2 <= denom1; + end + + always @ (numer_temp_57_q or denom2 or quo1_q) begin + quo2_d[63:58] = quo1_q[63:58]; + + //quo2_d[57] + if (numer_temp_57_q[94:57] >= denom2 ) begin + quo2_d[57] = 1'b1; + numer_temp_56 = {numer_temp_57_q[94:57] - denom2, numer_temp_57_q[56:0]}; + end else begin + quo2_d[57] = 1'b0; + numer_temp_56 = numer_temp_57_q; + end + //quo2_d[56] + if (numer_temp_56[94:56] >= denom2 ) begin + quo2_d[56] = 1'b1; + numer_temp_55 = {numer_temp_56[94:56] - denom2, numer_temp_56[55:0]}; + end else begin + quo2_d[56] = 1'b0; + numer_temp_55 = numer_temp_56; + end + //quo2_d[55] + if (numer_temp_55[94:55] >= denom2 ) begin + quo2_d[55] = 1'b1; + numer_temp_54_d = {numer_temp_55[94:55] - denom2, numer_temp_55[54:0]}; + end else begin + quo2_d[55] = 1'b0; + numer_temp_54_d = numer_temp_55; + end + quo2_d[54:0] = 55'b0; + end + + + always @ (posedge clock) begin + quo2_q <= quo2_d; + numer_temp_54_q <= numer_temp_54_d; + denom3 <= denom2; + end + + always @ (numer_temp_54_q or denom3 or quo2_q) begin + quo3_d[63:55] = quo2_q[63:55]; + + //quo3_d[54] + if (numer_temp_54_q[94:54] >= denom3 ) begin + quo3_d[54] = 1'b1; + numer_temp_53 = {numer_temp_54_q[94:54] - denom3, numer_temp_54_q[53:0]}; + end else begin + quo3_d[54] = 1'b0; + numer_temp_53 = numer_temp_54_q; + end + //quo3_d[53] + if (numer_temp_53[94:53] >= denom3 ) begin + quo3_d[53] = 1'b1; + numer_temp_52 = {numer_temp_53[94:53] - denom3, numer_temp_53[52:0]}; + end else begin + quo3_d[53] = 1'b0; + numer_temp_52 = numer_temp_53; + end + //quo3_d[52] + if (numer_temp_52[94:52] >= denom3 ) begin + quo3_d[52] = 1'b1; + numer_temp_51_d = {numer_temp_52[94:52] - denom3, numer_temp_52[51:0]}; + end else begin + quo3_d[52] = 1'b0; + numer_temp_51_d = numer_temp_52; + end + quo3_d[51:0] = 52'b0; + end + + always @ (posedge clock) begin + quo3_q <= quo3_d; + numer_temp_51_q <= numer_temp_51_d; + denom4 <= denom3; + end + + always @ (numer_temp_51_q or denom4 or quo3_q) begin + quo4_d[63:52] = quo3_q[63:52]; + + //quo4[51] + if (numer_temp_51_q[94:51] >= denom4 ) begin + quo4_d[51] = 1'b1; + numer_temp_50 = {numer_temp_51_q[94:51] - denom4, numer_temp_51_q[50:0]}; + end else begin + quo4_d[51] = 1'b0; + numer_temp_50 = numer_temp_51_q; + end + //quo4_d[50] + if (numer_temp_50[94:50] >= denom4 ) begin + quo4_d[50] = 1'b1; + numer_temp_49 = {numer_temp_50[94:50] - denom4, numer_temp_50[49:0]}; + end else begin + quo4_d[50] = 1'b0; + numer_temp_49 = numer_temp_50; + end + //quo4_d[49] + if (numer_temp_49[94:49] >= denom4 ) begin + quo4_d[49] = 1'b1; + numer_temp_48_d = {numer_temp_49[94:49] - denom4, numer_temp_49[48:0]}; + end else begin + quo4_d[49] = 1'b0; + numer_temp_48_d = numer_temp_49; + end + quo4_d[48:0] = 49'b0; + end + + always @ (posedge clock) begin + quo4_q <= quo4_d; + numer_temp_48_q <= numer_temp_48_d; + denom5 <= denom4; + end + + always @ (numer_temp_48_q or denom5 or quo4_q) begin + quo5_d[63:49] = quo4_q[63:49]; + + //quo5_d[48] + if (numer_temp_48_q[94:48] >= denom5 ) begin + quo5_d[48] = 1'b1; + numer_temp_47 = {numer_temp_48_q[94:48] - denom5, numer_temp_48_q[47:0]}; + end else begin + quo5_d[48] = 1'b0; + numer_temp_47 = numer_temp_48_q; + end + //quo5_d[47] + if (numer_temp_47[94:47] >= denom5 ) begin + quo5_d[47] = 1'b1; + numer_temp_46 = {numer_temp_47[94:47] - denom5, numer_temp_47[46:0]}; + end else begin + quo5_d[47] = 1'b0; + numer_temp_46 = numer_temp_47; + end + //quo5_d[46] + if (numer_temp_46[94:46] >= denom5 ) begin + quo5_d[46] = 1'b1; + numer_temp_45_d = {numer_temp_46[94:46] - denom5, numer_temp_46[45:0]}; + end else begin + quo5_d[46] = 1'b0; + numer_temp_45_d = numer_temp_46; + end + quo5_d[45:0] = 46'b0; + end + + always @ (posedge clock) begin + quo5_q <= quo5_d; + numer_temp_45_q <= numer_temp_45_d; + denom6 <= denom5; + end + + always @ (numer_temp_45_q or denom6 or quo5_q) begin + quo6_d[63:46] = quo5_q[63:46]; + + //quo6_d[45] + if (numer_temp_45_q[94:45] >= denom6 ) begin + quo6_d[45] = 1'b1; + numer_temp_44 = {numer_temp_45_q[94:45] - denom6, numer_temp_45_q[44:0]}; + end else begin + quo6_d[45] = 1'b0; + numer_temp_44 = numer_temp_45_q; + end + //quo6_d[44] + if (numer_temp_44[94:44] >= denom6 ) begin + quo6_d[44] = 1'b1; + numer_temp_43 = {numer_temp_44[94:44] - denom6, numer_temp_44[43:0]}; + end else begin + quo6_d[44] = 1'b0; + numer_temp_43 = numer_temp_44; + end + //quo6_d[43] + if (numer_temp_43[94:43] >= denom6 ) begin + quo6_d[43] = 1'b1; + numer_temp_42_d = {numer_temp_43[94:43] - denom6, numer_temp_43[42:0]}; + end else begin + quo6_d[43] = 1'b0; + numer_temp_42_d = numer_temp_43; + end + quo6_d[42:0] = 43'b0; + end + + always @ (posedge clock) begin + quo6_q<= quo6_d; + numer_temp_42_q <= numer_temp_42_d; + denom7 <= denom6; + end + + always @ (numer_temp_42_q or denom7 or quo6_q) begin + quo7_d[63:43] = quo6_q[63:43]; + + //quo7_d[42] + if (numer_temp_42_q[94:42] >= denom7 ) begin + quo7_d[42] = 1'b1; + numer_temp_41 = {numer_temp_42_q[94:42] - denom7, numer_temp_42_q[41:0]}; + end else begin + quo7_d[42] = 1'b0; + numer_temp_41 = numer_temp_42_q; + end + //quo7_d[41] + if (numer_temp_41[94:41] >= denom7 ) begin + quo7_d[41] = 1'b1; + numer_temp_40 = {numer_temp_41[94:41] - denom7, numer_temp_41[40:0]}; + end else begin + quo7_d[41] = 1'b0; + numer_temp_40 = numer_temp_41; + end + //quo7_d[40] + if (numer_temp_40[94:40] >= denom7 ) begin + quo7_d[40] = 1'b1; + numer_temp_39_d = {numer_temp_40[94:40] - denom7, numer_temp_40[39:0]}; + end else begin + quo7_d[40] = 1'b0; + numer_temp_39_d = numer_temp_40; + end + quo7_d[39:0] = 40'b0; + end + + always @ (posedge clock) begin + quo7_q <= quo7_d; + numer_temp_39_q <= numer_temp_39_d; + denom8 <= denom7; + end + + always @ (numer_temp_39_q or denom8 or quo7_q) begin + quo8_d[63:40] = quo7_q[63:40]; + + //quo8[39] + if (numer_temp_39_q[94:39] >= denom8 ) begin + quo8_d[39] = 1'b1; + numer_temp_38 = {numer_temp_39_q[94:39] - denom8, numer_temp_39_q[38:0]}; + end else begin + quo8_d[39] = 1'b0; + numer_temp_38 = numer_temp_39_q; + end + //quo8_d[38] + if (numer_temp_38[94:38] >= denom8 ) begin + quo8_d[38] = 1'b1; + numer_temp_37 = {numer_temp_38[94:38] - denom8, numer_temp_38[37:0]}; + end else begin + quo8_d[38] = 1'b0; + numer_temp_37 = numer_temp_38; + end + //quo8_d[37] + if (numer_temp_37[94:37] >= denom8 ) begin + quo8_d[37] = 1'b1; + numer_temp_36_d = {numer_temp_37[94:37] - denom8, numer_temp_37[36:0]}; + end else begin + quo8_d[37] = 1'b0; + numer_temp_36_d = numer_temp_37; + end + quo8_d[36:0] = 37'b0; + end + + always @ (posedge clock) begin + quo8_q <= quo8_d; + numer_temp_36_q <= numer_temp_36_d; + denom9 <= denom8; + end + + always @ (numer_temp_36_q or denom9 or quo8_q) begin + quo9_d[63:37] = quo8_q[63:37]; + + //quo9[36] + if (numer_temp_36_q[94:36] >= denom9 ) begin + quo9_d[36] = 1'b1; + numer_temp_35 = {numer_temp_36_q[94:36] - denom9, numer_temp_36_q[35:0]}; + end else begin + quo9_d[36] = 1'b0; + numer_temp_35 = numer_temp_36_q; + end + //quo9_d[35] + if (numer_temp_35[94:35] >= denom9 ) begin + quo9_d[35] = 1'b1; + numer_temp_34 = {numer_temp_35[94:35] - denom9, numer_temp_35[34:0]}; + end else begin + quo9_d[35] = 1'b0; + numer_temp_34 = numer_temp_35; + end + //quo9_d[34] + if (numer_temp_34[94:34] >= denom9 ) begin + quo9_d[34] = 1'b1; + numer_temp_33_d = {numer_temp_34[94:34] - denom9, numer_temp_34[33:0]}; + end else begin + quo9_d[34] = 1'b0; + numer_temp_33_d = numer_temp_34; + end + quo9_d[33:0] = 34'b0; + end + + always @ (posedge clock) begin + quo9_q <= quo9_d; + numer_temp_33_q <= numer_temp_33_d; + denom10 <= denom9; + end + + always @ (numer_temp_33_q or denom10 or quo9_q) begin + quo10_d[63:34] = quo9_q[63:34]; + + //quo10_d[33] + if (numer_temp_33_q[94:33] >= denom10 ) begin + quo10_d[33] = 1'b1; + numer_temp_32 = {numer_temp_33_q[94:33] - denom10, numer_temp_33_q[32:0]}; + end else begin + quo10_d[33] = 1'b0; + numer_temp_32 = numer_temp_33_q; + end + //quo10_d[32] + if (numer_temp_32[94:32] >= denom10 ) begin + quo10_d[32] = 1'b1; + numer_temp_31 = {numer_temp_32[94:32] - denom10, numer_temp_32[31:0]}; + end else begin + quo10_d[32] = 1'b0; + numer_temp_31 = numer_temp_32; + end + //quo10_d[31] + if (numer_temp_31[94:31] >= denom10 ) begin + quo10_d[31] = 1'b1; + numer_temp_30_d = {numer_temp_31[94:31] - denom10, numer_temp_31[30:0]}; + end else begin + quo10_d[31] = 1'b0; + numer_temp_30_d = numer_temp_31; + end + quo10_d[30:0] = 31'b0; + end + + always @ (posedge clock) begin + quo10_q <= quo10_d; + numer_temp_30_q <= numer_temp_30_d; + denom11 <= denom10; + end + + always @ (numer_temp_30_q or denom11 or quo10_q) begin + quo11_d[63:31] = quo10_q[63:31]; + + //quo11[30] + if (numer_temp_30_q[94:30] >= denom11 ) begin + quo11_d[30] = 1'b1; + numer_temp_29 = {numer_temp_30_q[94:30] - denom11, numer_temp_30_q[29:0]}; + end else begin + quo11_d[30] = 1'b0; + numer_temp_29 = numer_temp_30_q; + end + //quo11_d[29] + if (numer_temp_29[94:29] >= denom11 ) begin + quo11_d[29] = 1'b1; + numer_temp_28 = {numer_temp_29[94:29] - denom11, numer_temp_29[28:0]}; + end else begin + quo11_d[29] = 1'b0; + numer_temp_28 = numer_temp_29; + end + //quo11_d[28] + if (numer_temp_28[94:28] >= denom11 ) begin + quo11_d[28] = 1'b1; + numer_temp_27_d = {numer_temp_28[94:28] - denom11, numer_temp_28[27:0]}; + end else begin + quo11_d[28] = 1'b0; + numer_temp_27_d = numer_temp_28; + end + quo11_d[27:0] = 28'b0; + end + + always @ (posedge clock) begin + quo11_q <= quo11_d; + numer_temp_27_q <= numer_temp_27_d; + denom12 <= denom11; + end + + always @ (numer_temp_27_q or denom12 or quo11_q) begin + quo12_d[63:28] = quo11_q[63:28]; + + //quo12[27] + if (numer_temp_27_q[94:27] >= denom12 ) begin + quo12_d[27] = 1'b1; + numer_temp_26 = {numer_temp_27_q[94:27] - denom12, numer_temp_27_q[26:0]}; + end else begin + quo12_d[27] = 1'b0; + numer_temp_26 = numer_temp_27_q; + end + //quo12_d[26] + if (numer_temp_26[94:26] >= denom12 ) begin + quo12_d[26] = 1'b1; + numer_temp_25 = {numer_temp_26[94:26] - denom12, numer_temp_26[25:0]}; + end else begin + quo12_d[26] = 1'b0; + numer_temp_25 = numer_temp_26; + end + //quo12_d[25] + if (numer_temp_25[94:25] >= denom12 ) begin + quo12_d[25] = 1'b1; + numer_temp_24 = {numer_temp_25[94:25] - denom12, numer_temp_25[24:0]}; + end else begin + quo12_d[25] = 1'b0; + numer_temp_24 = numer_temp_25; + end + //quo12_d[24] + if (numer_temp_24[94:24] >= denom12 ) begin + quo12_d[24] = 1'b1; + numer_temp_23_d = {numer_temp_24[94:24] - denom12, numer_temp_24[23:0]}; + end else begin + quo12_d[24] = 1'b0; + numer_temp_23_d = numer_temp_24; + end + quo12_d[23:0] = 24'b0; + end + + always @ (posedge clock) begin + quo12_q <= quo12_d; + numer_temp_23_q <= numer_temp_23_d; + denom13 <= denom12; + end + + always @ (numer_temp_23_q or denom13 or quo12_q) begin + quo13_d[63:24] = quo12_q[63:24]; + + //quo13_d[23] + if (numer_temp_23_q[94:23] >= denom13 ) begin + quo13_d[23] = 1'b1; + numer_temp_22 = {numer_temp_23_q[94:23] - denom13, numer_temp_23_q[22:0]}; + end else begin + quo13_d[23] = 1'b0; + numer_temp_22 = numer_temp_23_q; + end + //quo13_d[22] + if (numer_temp_22[94:22] >= denom13 ) begin + quo13_d[22] = 1'b1; + numer_temp_21 = {numer_temp_22[94:22] - denom13, numer_temp_22[21:0]}; + end else begin + quo13_d[22] = 1'b0; + numer_temp_21 = numer_temp_22; + end + //quo13_d[21] + if (numer_temp_21[94:21] >= denom13 ) begin + quo13_d[21] = 1'b1; + numer_temp_20 = {numer_temp_21[94:21] - denom13, numer_temp_21[20:0]}; + end else begin + quo13_d[21] = 1'b0; + numer_temp_20 = numer_temp_21; + end + //quo13_d[20] + if (numer_temp_20[94:20] >= denom13 ) begin + quo13_d[20] = 1'b1; + numer_temp_19_d = {numer_temp_20[94:20] - denom13, numer_temp_20[19:0]}; + end else begin + quo13_d[20] = 1'b0; + numer_temp_19_d = numer_temp_20; + end + quo13_d[19:0] = 20'b0; + end + + always @ (posedge clock) begin + quo13_q <= quo13_d; + numer_temp_19_q <= numer_temp_19_d; + denom14 <= denom13; + end + + always @ (numer_temp_19_q or denom14 or quo13_q) begin + quo14_d[63:20] = quo13_q[63:20]; + + //quo14_d[19] + if (numer_temp_19_q[94:19] >= denom14 ) begin + quo14_d[19] = 1'b1; + numer_temp_18 = {numer_temp_19_q[94:19] - denom14, numer_temp_19_q[18:0]}; + end else begin + quo14_d[19] = 1'b0; + numer_temp_18 = numer_temp_19_q; + end + //quo14_d[18] + if (numer_temp_18[94:18] >= denom14 ) begin + quo14_d[18] = 1'b1; + numer_temp_17 = {numer_temp_18[94:18] - denom14, numer_temp_18[17:0]}; + end else begin + quo14_d[18] = 1'b0; + numer_temp_17 = numer_temp_18; + end + //quo14_d[17] + if (numer_temp_17[94:17] >= denom14 ) begin + quo14_d[17] = 1'b1; + numer_temp_16 = {numer_temp_17[94:17] - denom14, numer_temp_17[16:0]}; + end else begin + quo14_d[17] = 1'b0; + numer_temp_16 = numer_temp_17; + end + //quo14_d[16] + if (numer_temp_16[94:16] >= denom14 ) begin + quo14_d[16] = 1'b1; + numer_temp_15_d = {numer_temp_16[94:16] - denom14, numer_temp_16[15:0]}; + end else begin + quo14_d[16] = 1'b0; + numer_temp_15_d = numer_temp_16; + end + quo14_d[15:0] = 16'b0; + end + + always @ (posedge clock) begin + quo14_q <= quo14_d; + numer_temp_15_q <= numer_temp_15_d; + denom15 <= denom14; + end + + always @ (numer_temp_15_q or denom15 or quo14_q) begin + quo15_d[63:16] = quo14_q[63:16]; + + //quo15_d[15] + if (numer_temp_15_q[94:15] >= denom15 ) begin + quo15_d[15] = 1'b1; + numer_temp_14 = {numer_temp_15_q[94:15] - denom15, numer_temp_15_q[14:0]}; + end else begin + quo15_d[15] = 1'b0; + numer_temp_14 = numer_temp_15_q; + end + //quo15_d[14] + if (numer_temp_14[94:14] >= denom15 ) begin + quo15_d[14] = 1'b1; + numer_temp_13 = {numer_temp_14[94:14] - denom15, numer_temp_14[13:0]}; + end else begin + quo15_d[14] = 1'b0; + numer_temp_13 = numer_temp_14; + end + //quo15_d[13] + if (numer_temp_13[94:13] >= denom15 ) begin + quo15_d[13] = 1'b1; + numer_temp_12 = {numer_temp_13[94:13] - denom15, numer_temp_13[12:0]}; + end else begin + quo15_d[13] = 1'b0; + numer_temp_12 = numer_temp_13; + end + //quo15_d[12] + if (numer_temp_12[94:12] >= denom15 ) begin + quo15_d[12] = 1'b1; + numer_temp_11_d = {numer_temp_12[94:12] - denom15, numer_temp_12[11:0]}; + end else begin + quo15_d[12] = 1'b0; + numer_temp_11_d = numer_temp_12; + end + quo15_d[11:0] = 12'b0; + end + + always @ (posedge clock) begin + quo15_q <= quo15_d; + numer_temp_11_q <= numer_temp_11_d; + denom16 <= denom15; + end + + always @ (numer_temp_11_q or denom16 or quo15_q) begin + quo16_d[63:12] = quo15_q[63:12]; + + //quo16_d[11] + if (numer_temp_11_q[94:11] >= denom16 ) begin + quo16_d[11] = 1'b1; + numer_temp_10 = {numer_temp_11_q[94:11] - denom16, numer_temp_11_q[10:0]}; + end else begin + quo16_d[11] = 1'b0; + numer_temp_10 = numer_temp_11_q; + end + //quo16_d[10] + if (numer_temp_10[94:10] >= denom16 ) begin + quo16_d[10] = 1'b1; + numer_temp_9 = {numer_temp_10[94:10] - denom16, numer_temp_10[9:0]}; + end else begin + quo16_d[10] = 1'b0; + numer_temp_9 = numer_temp_10; + end + //quo16_d[9] + if (numer_temp_9[94:9] >= denom16 ) begin + quo16_d[9] = 1'b1; + numer_temp_8 = {numer_temp_9[94:9] - denom16, numer_temp_9[8:0]}; + end else begin + quo16_d[9] = 1'b0; + numer_temp_8 = numer_temp_9; + end + //quo16_d[8] + if (numer_temp_8[94:8] >= denom16 ) begin + quo16_d[8] = 1'b1; + numer_temp_7_d = {numer_temp_8[94:8] - denom16, numer_temp_8[7:0]}; + end else begin + quo16_d[8] = 1'b0; + numer_temp_7_d = numer_temp_8; + end + quo16_d[7:0] = 8'b0; + end + + always @ (posedge clock) begin + quo16_q <= quo16_d; + numer_temp_7_q <= numer_temp_7_d; + denom17 <= denom16; + end + + always @ (numer_temp_7_q or denom17 or quo16_q) begin + quo17_d[63:8] = quo16_q[63:8]; + + //quo17_d[7] + if (numer_temp_7_q[94:7] >= denom17 ) begin + quo17_d[7] = 1'b1; + numer_temp_6 = {numer_temp_7_q[94:7] - denom17, numer_temp_7_q[6:0]}; + end else begin + quo17_d[7] = 1'b0; + numer_temp_6 = numer_temp_7_q; + end + //quo17_d[6] + if (numer_temp_6[94:6] >= denom17 ) begin + quo17_d[6] = 1'b1; + numer_temp_5 = {numer_temp_6[94:6] - denom17, numer_temp_6[5:0]}; + end else begin + quo17_d[6] = 1'b0; + numer_temp_5 = numer_temp_6; + end + //quo17_d[5] + if (numer_temp_5[94:5] >= denom17 ) begin + quo17_d[5] = 1'b1; + numer_temp_4 = {numer_temp_5[94:5] - denom17, numer_temp_5[4:0]}; + end else begin + quo17_d[5] = 1'b0; + numer_temp_4 = numer_temp_5; + end + //quo17_d[4] + if (numer_temp_4[94:4] >= denom17 ) begin + quo17_d[4] = 1'b1; + numer_temp_3_d = {numer_temp_4[94:4] - denom17, numer_temp_4[3:0]}; + end else begin + quo17_d[4] = 1'b0; + numer_temp_3_d = numer_temp_4; + end + quo17_d[3:0] = 4'b0; + end + + always @ (posedge clock) begin + quo17_q <= quo17_d; + numer_temp_3_q <= numer_temp_3_d; + denom18 <= denom17; + end + + always @ (numer_temp_3_q or denom18 or quo17_q) begin + quo18_d[63:4] = quo17_q[63:4]; + + //quo18_d[3] + if (numer_temp_3_q[94:3] >= denom18 ) begin + quo18_d[3] = 1'b1; + numer_temp_2 = {numer_temp_3_q[94:3] - denom18, numer_temp_3_q[2:0]}; + end else begin + quo18_d[3] = 1'b0; + numer_temp_2 = numer_temp_3_q; + end + //quo18_d[2] + if (numer_temp_2[94:2] >= denom18 ) begin + quo18_d[2] = 1'b1; + numer_temp_1_d = {numer_temp_2[94:2] - denom18, numer_temp_2[1:0]}; + end else begin + quo18_d[2] = 1'b0; + numer_temp_1_d = numer_temp_2; + end + quo18_d[1:0] = 2'b0; + end + + always @ (posedge clock) begin + quo18_q <= quo18_d; + numer_temp_1_q <= numer_temp_1_d; + denom19 <= denom18; + end + + always @ (numer_temp_1_q or denom19 or quo18_q) begin + quo19_d[63:2] = quo18_q[63:2]; + //quo19_d[1] + if (numer_temp_1_q[94:1] >= denom19 ) begin + quo19_d[1] = 1'b1; + numer_temp_0 = {numer_temp_1_q[94:1] - denom19, numer_temp_1_q[0:0]}; + end else begin + quo19_d[1] = 1'b0; + numer_temp_0 = numer_temp_1_q; + + end + //quo19_d[0] + if (numer_temp_0[94:0] >= denom19 ) begin + quo19_d[0] = 1'b1; + numer_temp = numer_temp_0[94:0] - denom19; + end else begin + quo19_d[0] = 1'b0; + numer_temp = numer_temp_0; + end + end + + assign quotient = quo19_d; + assign remain = numer_temp[31:0]; + + + +endmodule + +/*module sqrt_64b (clk, num, res); + input clk; + input [63:0]num; + output [31:0]res; + reg [31:0]res;*/ + +//`timescale 1 ns / 1 ps + +module Sqrt_64b (clk, num_, res); + input clk; + input [63:0]num_; + output [31:0]res; + reg [31:0]res; + + reg [63:0]num; + + always @ (posedge clk) + begin + num <= num_; + end + +///////////////////////////////////////////////////Unchanged starts here + +// reg [63:0] one_[32:0]; +// reg [63:0] res_[32:0]; +// reg [63:0] op_[32:0]; + + wire [63:0]one__0; + reg [63:0]one__1; + reg [63:0]one__2; + reg [63:0]one__3_d, one__3_q; + reg [63:0]one__4; + reg [63:0]one__5; + reg [63:0]one__6; + reg [63:0]one__7_d, one__7_q; + reg [63:0]one__8; + reg [63:0]one__9; + reg [63:0]one__10; + reg [63:0]one__11_d, one__11_q; + reg [63:0]one__12; + reg [63:0]one__13; + reg [63:0]one__14; + reg [63:0]one__15_d, one__15_q; + reg [63:0]one__16; + reg [63:0]one__17; + reg [63:0]one__18_d, one__18_q; + reg [63:0]one__19; + reg [63:0]one__20; + reg [63:0]one__21_d, one__21_q; + reg [63:0]one__22; + reg [63:0]one__23; + reg [63:0]one__24_d, one__24_q; + reg [63:0]one__25; + reg [63:0]one__26; + reg [63:0]one__27_d, one__27_q; + reg [63:0]one__28; + reg [63:0]one__29; + reg [63:0]one__30_d, one__30_q; + reg [63:0]one__31; + reg [63:0]one__32; + + wire [63:0]res__0; + reg [63:0]res__1; + reg [63:0]res__2; + reg [63:0]res__3_d, res__3_q; + reg [63:0]res__4; + reg [63:0]res__5; + reg [63:0]res__6; + reg [63:0]res__7_d, res__7_q; + reg [63:0]res__8; + reg [63:0]res__9; + reg [63:0]res__10; + reg [63:0]res__11_d, res__11_q; + reg [63:0]res__12; + reg [63:0]res__13; + reg [63:0]res__14; + reg [63:0]res__15_d, res__15_q; + reg [63:0]res__16; + reg [63:0]res__17; + reg [63:0]res__18_d, res__18_q; + reg [63:0]res__19; + reg [63:0]res__20; + reg [63:0]res__21_d, res__21_q; + reg [63:0]res__22; + reg [63:0]res__23; + reg [63:0]res__24_d, res__24_q; + reg [63:0]res__25; + reg [63:0]res__26; + reg [63:0]res__27_d, res__27_q; + reg [63:0]res__28; + reg [63:0]res__29; + reg [63:0]res__30_d, res__30_q; + reg [63:0]res__31; + reg [63:0]res__32; + + wire [63:0]op__0; + reg [63:0]op__1; + reg [63:0]op__2; + reg [63:0]op__3_d, op__3_q; + reg [63:0]op__4; + reg [63:0]op__5; + reg [63:0]op__6; + reg [63:0]op__7_d, op__7_q; + reg [63:0]op__8; + reg [63:0]op__9; + reg [63:0]op__10; + reg [63:0]op__11_d, op__11_q; + reg [63:0]op__12; + reg [63:0]op__13; + reg [63:0]op__14; + reg [63:0]op__15_d, op__15_q; + reg [63:0]op__16; + reg [63:0]op__17; + reg [63:0]op__18_d, op__18_q; + reg [63:0]op__19; + reg [63:0]op__20; + reg [63:0]op__21_d, op__21_q; + reg [63:0]op__22; + reg [63:0]op__23; + reg [63:0]op__24_d, op__24_q; + reg [63:0]op__25; + reg [63:0]op__26; + reg [63:0]op__27_d, op__27_q; + reg [63:0]op__28; + reg [63:0]op__29; + reg [63:0]op__30_d, op__30_q; + reg [63:0]op__31; + reg [63:0]op__32; + + + reg [63:0]one; //This is the one that is selected in first expanded loop + reg [31:0]one_tmp; + + always @ (num) begin + + //The first for-loop: + //all of these will be zero no matter how 'one' is selected. + one[1] = 0; + one[3] = 0; + one[5] = 0; + one[7] = 0; + one[9] = 0; + one[11] = 0; + one[13] = 0; + one[15] = 0; + one[17] = 0; + one[19] = 0; + one[21] = 0; + one[23] = 0; + one[25] = 0; + one[27] = 0; + one[29] = 0; + one[31] = 0; + one[33] = 0; + one[35] = 0; + one[37] = 0; + one[39] = 0; + one[41] = 0; + one[43] = 0; + one[45] = 0; + one[47] = 0; + one[49] = 0; + one[51] = 0; + one[53] = 0; + one[55] = 0; + one[57] = 0; + one[59] = 0; + one[61] = 0; + one[63] = 0; + + one_tmp[0] = num[0]|num[1]; + one_tmp[1] = num[2]|num[3]; + one_tmp[2] = num[4]|num[5]; + one_tmp[3] = num[6]|num[7]; + one_tmp[4] = num[8]|num[9]; + one_tmp[5] = num[10]|num[11]; + one_tmp[6] = num[12]|num[13]; + one_tmp[7] = num[14]|num[15]; + one_tmp[8] = num[16]|num[17]; + one_tmp[9] = num[18]|num[19]; + one_tmp[10] = num[20]|num[21]; + one_tmp[11] = num[22]|num[23]; + one_tmp[12] = num[24]|num[25]; + one_tmp[13] = num[26]|num[27]; + one_tmp[14] = num[28]|num[29]; + one_tmp[15] = num[30]|num[31]; + one_tmp[16] = num[32]|num[33]; + one_tmp[17] = num[34]|num[35]; + one_tmp[18] = num[36]|num[37]; + one_tmp[19] = num[38]|num[39]; + one_tmp[20] = num[40]|num[41]; + one_tmp[21] = num[42]|num[43]; + one_tmp[22] = num[44]|num[45]; + one_tmp[23] = num[46]|num[47]; + one_tmp[24] = num[48]|num[49]; + one_tmp[25] = num[50]|num[51]; + one_tmp[26] = num[52]|num[53]; + one_tmp[27] = num[54]|num[55]; + one_tmp[28] = num[56]|num[57]; + one_tmp[29] = num[58]|num[59]; + one_tmp[30] = num[60]|num[61]; + one_tmp[31] = num[62]|num[63]; + + one[0] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&~one_tmp[2]&~one_tmp[1]&one_tmp[0]; + one[2] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&~one_tmp[2]&one_tmp[1]; + one[4] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&one_tmp[2]; + one[6] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&one_tmp[3]; + one[8] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&one_tmp[4]; + one[10] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&one_tmp[5]; + one[12] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&one_tmp[6]; + one[14] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&one_tmp[7]; + one[16] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&one_tmp[8]; + one[18] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&one_tmp[9]; + one[20] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&one_tmp[10]; + one[22] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&one_tmp[11]; + one[24] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&one_tmp[12]; + one[26] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&one_tmp[13]; + one[28] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&one_tmp[14]; + one[30] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&one_tmp[15]; + one[32] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&one_tmp[16]; + one[34] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&one_tmp[17]; + one[36] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&one_tmp[18]; + one[38] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&one_tmp[19]; + one[40] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&one_tmp[20]; + one[42] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&one_tmp[21]; + one[44] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&one_tmp[22]; + one[46] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&one_tmp[23]; + one[48] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&one_tmp[24]; + one[50] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&one_tmp[25]; + one[52] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&one_tmp[26]; + one[54] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&one_tmp[27]; + one[56] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&one_tmp[28]; + one[58] = ~one_tmp[31]&~one_tmp[30]&one_tmp[29]; + one[60] = ~one_tmp[31]&one_tmp[30]; + one[62] = one_tmp[31]; + end + +// //2nd for-loop: +// integer i; +// always @* begin +// op_[0] = num; +// one_[0] = one; +// res_[0] = 64'b0; +// res = 63'b0; +// res_assigned = 1'b0; +// +// for (i = 0; i <= 31; i=i+1) begin +// if ((one_[i] == 0) & ~res_assigned) begin +// res = res_[i]; +// res_assigned = 1'b1; +// end +// +// //Define the next stage: +// if (op_[i] >= res_[i] + one_[i]) begin +// op_[i+1] = op_[i] - res_[i] - one_[i]; +// res_[i+1] = (res_[i]>>1) + one_[i]; +// end else begin +// op_[i+1] = op_[i]; //this line had to be added for the verilog version. +// res_[i+1] = (res_[i]>>1); +// end +// one_[i+1] = (one_[i] >> 2); +// end +// +// //Add the part for really big numbers later: +// if (~res_assigned) begin +// res = res_[32]; +// end +// end + + //If-statement about defining the next stage: + assign op__0 = num; + assign res__0 = 64'b0; + assign one__0 = one; + + always @ (res__0 or op__0 or one__0) begin + + //i = 0 + if (op__0 >= res__0 + one__0) begin + op__1 = op__0 - res__0 - one__0; + res__1 = (res__0>>1) + one__0; + end else begin + op__1 = op__0; + res__1 = (res__0>>1); + end + one__1 = (one__0 >> 2); + + //i = 1 + if (op__1 >= res__1 + one__1) begin + op__2 = op__1 - res__1 - one__1; + res__2 = (res__1>>1) + one__1; + end else begin + op__2 = op__1; + res__2 = (res__1>>1); + end + one__2 = (one__1 >> 2); + + //i = 2 + if (op__2 >= res__2 + one__2) begin + op__3_d = op__2 - res__2 - one__2; + res__3_d = (res__2>>1) + one__2; + end else begin + op__3_d = op__2; + res__3_d = (res__2>>1); + end + one__3_d = (one__2 >> 2); + end + + always @ (posedge clk) begin + op__3_q <= op__3_d; + res__3_q <= res__3_d; + one__3_q <= one__3_d; + end + + always @ (op__3_q or res__3_q or one__3_q) begin + //i = 3 + if (op__3_q >= res__3_q + one__3_q) begin + op__4 = op__3_q - res__3_q - one__3_q; + res__4 = (res__3_q>>1) + one__3_q; + end else begin + op__4 = op__3_q; + res__4 = (res__3_q>>1); + end + one__4 = (one__3_q >> 2); + + //i = 4 + if (op__4 >= res__4 + one__4) begin + op__5 = op__4 - res__4 - one__4; + res__5 = (res__4>>1) + one__4; + end else begin + op__5 = op__4; + res__5 = (res__4>>1); + end + one__5 = (one__4 >> 2); + + //i = 5 + if (op__5 >= res__5 + one__5) begin + op__6 = op__5 - res__5 - one__5; + res__6 = (res__5>>1) + one__5; + end else begin + op__6 = op__5; + res__6 = (res__5>>1); + end + one__6 = (one__5 >> 2); + + //i = 6 + if (op__6 >= res__6 + one__6) begin + op__7_d = op__6 - res__6 - one__6; + res__7_d = (res__6>>1) + one__6; + end else begin + op__7_d = op__6; + res__7_d = (res__6>>1); + end + one__7_d = (one__6 >> 2); + end + + always @ (posedge clk) begin + op__7_q <= op__7_d; + one__7_q <= one__7_d; + res__7_q <= res__7_d; + end + + always @ (op__7_q or res__7_q or one__7_q) begin + //i = 7 + if (op__7_q >= res__7_q + one__7_q) begin + op__8 = op__7_q - res__7_q - one__7_q; + res__8 = (res__7_q>>1) + one__7_q; + end else begin + op__8 = op__7_q; + res__8 = (res__7_q>>1); + end + one__8 = (one__7_q >> 2); + + //i = 8 + if (op__8 >= res__8 + one__8) begin + op__9 = op__8 - res__8 - one__8; + res__9 = (res__8>>1) + one__8; + end else begin + op__9 = op__8; + res__9 = (res__8>>1); + end + one__9 = (one__8 >> 2); + + //i = 9 + if (op__9 >= res__9 + one__9) begin + op__10 = op__9 - res__9 - one__9; + res__10 = (res__9>>1) + one__9; + end else begin + op__10 = op__9; + res__10 = (res__9>>1); + end + one__10 = (one__9 >> 2); + + //i = 10 + if (op__10 >= res__10 + one__10) begin + op__11_d = op__10 - res__10 - one__10; + res__11_d = (res__10>>1) + one__10; + end else begin + op__11_d = op__10; + res__11_d = (res__10>>1); + end + one__11_d = (one__10 >> 2); + end + + always @ (posedge clk) begin + op__11_q <= op__11_d; + one__11_q <= one__11_d; + res__11_q <= res__11_d; + end + + always @ (op__11_q or res__11_q or one__11_q) begin + //i = 11 + if (op__11_q >= res__11_q + one__11_q) begin + op__12 = op__11_q - res__11_q - one__11_q; + res__12 = (res__11_q>>1) + one__11_q; + end else begin + op__12 = op__11_q; + res__12 = (res__11_q>>1); + end + one__12 = (one__11_q >> 2); + + //i = 12 + if (op__12 >= res__12 + one__12) begin + op__13 = op__12 - res__12 - one__12; + res__13 = (res__12>>1) + one__12; + end else begin + op__13 = op__12; + res__13 = (res__12>>1); + end + one__13 = (one__12 >> 2); + + //i = 13 + if (op__13 >= res__13 + one__13) begin + op__14 = op__13 - res__13 - one__13; + res__14 = (res__13>>1) + one__13; + end else begin + op__14 = op__13; + res__14 = (res__13>>1); + end + one__14 = (one__13 >> 2); + + //i = 14 + if (op__14 >= res__14 + one__14) begin + op__15_d = op__14 - res__14 - one__14; + res__15_d = (res__14>>1) + one__14; + end else begin + op__15_d = op__14; + res__15_d = (res__14>>1); + end + one__15_d = (one__14 >> 2); + end + + always @ (posedge clk) begin + op__15_q <= op__15_d; + one__15_q <= one__15_d; + res__15_q <= res__15_d; + end + + always @ (op__15_q or res__15_q or one__15_q) begin + //i = 15 + if (op__15_q >= res__15_q + one__15_q) begin + op__16 = op__15_q - res__15_q - one__15_q; + res__16 = (res__15_q>>1) + one__15_q; + end else begin + op__16 = op__15_q; + res__16 = (res__15_q>>1); + end + one__16 = (one__15_q >> 2); + + //i = 16 + if (op__16 >= res__16 + one__16) begin + op__17 = op__16 - res__16 - one__16; + res__17 = (res__16>>1) + one__16; + end else begin + op__17 = op__16; + res__17 = (res__16>>1); + end + one__17 = (one__16 >> 2); + + //i = 17 + if (op__17 >= res__17 + one__17) begin + op__18_d = op__17 - res__17 - one__17; + res__18_d = (res__17>>1) + one__17; + end else begin + op__18_d = op__17; + res__18_d = (res__17>>1); + end + one__18_d = (one__17 >> 2); + end + + always @ (posedge clk) begin + op__18_q <= op__18_d; + one__18_q <= one__18_d; + res__18_q <= res__18_d; + end + + always @ (op__18_q or res__18_q or one__18_q) begin + //i = 18 + if (op__18_q >= res__18_q + one__18_q) begin + op__19 = op__18_q - res__18_q - one__18_q; + res__19 = (res__18_q>>1) + one__18_q; + end else begin + op__19 = op__18_q; + res__19 = (res__18_q>>1); + end + one__19 = (one__18_q >> 2); + + //i = 19 + if (op__19 >= res__19 + one__19) begin + op__20 = op__19 - res__19 - one__19; + res__20 = (res__19>>1) + one__19; + end else begin + op__20 = op__19; + res__20 = (res__19>>1); + end + one__20 = (one__19 >> 2); + + //i = 20 + if (op__20 >= res__20 + one__20) begin + op__21_d = op__20 - res__20 - one__20; + res__21_d = (res__20>>1) + one__20; + end else begin + op__21_d = op__20; + res__21_d = (res__20>>1); + end + one__21_d = (one__20 >> 2); + end + + always @ (posedge clk) begin + op__21_q <= op__21_d; + one__21_q <= one__21_d; + res__21_q <= res__21_d; + end + + always @ (op__21_q or res__21_q or one__21_q) begin + //i = 21 + if (op__21_q >= res__21_q + one__21_q) begin + op__22 = op__21_q - res__21_q - one__21_q; + res__22 = (res__21_q>>1) + one__21_q; + end else begin + op__22 = op__21_q; + res__22 = (res__21_q>>1); + end + one__22 = (one__21_q >> 2); + + //i = 22 + if (op__22 >= res__22 + one__22) begin + op__23 = op__22 - res__22 - one__22; + res__23 = (res__22>>1) + one__22; + end else begin + op__23 = op__22; + res__23 = (res__22>>1); + end + one__23 = (one__22 >> 2); + + //i = 23 + if (op__23 >= res__23 + one__23) begin + op__24_d = op__23 - res__23 - one__23; + res__24_d = (res__23>>1) + one__23; + end else begin + op__24_d = op__23; + res__24_d = (res__23>>1); + end + one__24_d = (one__23 >> 2); + end + + always @ (posedge clk) begin + op__24_q <= op__24_d; + one__24_q <= one__24_d; + res__24_q <= res__24_d; + end + + always @ (op__24_q or res__24_q or one__24_q) begin + //i = 24 + if (op__24_q >= res__24_q + one__24_q) begin + op__25 = op__24_q - res__24_q - one__24_q; + res__25 = (res__24_q>>1) + one__24_q; + end else begin + op__25 = op__24_q; + res__25 = (res__24_q>>1); + end + one__25 = (one__24_q >> 2); + + //i = 25 + if (op__25 >= res__25 + one__25) begin + op__26 = op__25 - res__25 - one__25; + res__26 = (res__25>>1) + one__25; + end else begin + op__26 = op__25; + res__26 = (res__25>>1); + end + one__26 = (one__25 >> 2); + + //i = 26 + if (op__26 >= res__26 + one__26) begin + op__27_d = op__26 - res__26 - one__26; + res__27_d = (res__26>>1) + one__26; + end else begin + op__27_d = op__26; + res__27_d = (res__26>>1); + end + one__27_d = (one__26 >> 2); + end + + always @ (posedge clk) begin + op__27_q <= op__27_d; + one__27_q <= one__27_d; + res__27_q <= res__27_d; + end + + always @ (op__27_q or res__27_q or one__27_q) begin + //i = 27 + if (op__27_q >= res__27_q + one__27_q) begin + op__28 = op__27_q - res__27_q - one__27_q; + res__28 = (res__27_q>>1) + one__27_q; + end else begin + op__28 = op__27_q; + res__28 = (res__27_q>>1); + end + one__28 = (one__27_q >> 2); + + //i = 28 + if (op__28 >= res__28 + one__28) begin + op__29 = op__28 - res__28 - one__28; + res__29 = (res__28>>1) + one__28; + end else begin + op__29 = op__28; + res__29 = (res__28>>1); + end + one__29 = (one__28 >> 2); + + //i = 29 + if (op__29 >= res__29 + one__29) begin + op__30_d = op__29 - res__29 - one__29; + res__30_d = (res__29>>1) + one__29; + end else begin + op__30_d = op__29; + res__30_d = (res__29>>1); + end + one__30_d = (one__29 >> 2); + end + + always @ (posedge clk) begin + op__30_q <= op__30_d; + one__30_q <= one__30_d; + res__30_q <= res__30_d; + end + + always @* begin + //i = 30 + if (op__30_q >= res__30_q + one__30_q) begin + op__31 = op__30_q - res__30_q - one__30_q; + res__31 = (res__30_q>>1) + one__30_q; + end else begin + op__31 = op__30_q; + res__31 = (res__30_q>>1); + end + one__31 = (one__30_q >> 2); + + //i = 31 + if (op__31 >= res__31 + one__31) begin + op__32 = op__31 - res__31 - one__31; + res__32 = (res__31>>1) + one__31; + end else begin + op__32 = op__31; + res__32 = (res__31>>1); + end + one__32 = (one__31 >> 2); + end + + + //If-statement about assigning res: + always @* begin + if(one__0 == 0) begin + res = res__0[31:0]; + end else if (one__1 == 0) begin + res = res__1[31:0]; + end else if (one__2 == 0) begin + res = res__2[31:0]; + end else if (one__3_q == 0) begin + res = res__3_q[31:0]; + end else if (one__4 == 0) begin + res = res__4[31:0]; + end else if (one__5 == 0) begin + res = res__5[31:0]; + end else if (one__6 == 0) begin + res = res__6[31:0]; + end else if (one__7_q == 0) begin + res = res__7_q[31:0]; + end else if (one__8 == 0) begin + res = res__8[31:0]; + end else if (one__9 == 0) begin + res = res__9[31:0]; + end else if (one__10 == 0) begin + res = res__10[31:0]; + end else if (one__11_q == 0) begin + res = res__11_q[31:0]; + end else if (one__12 == 0) begin + res = res__12[31:0]; + end else if (one__13 == 0) begin + res = res__13[31:0]; + end else if (one__14 == 0) begin + res = res__14[31:0]; + end else if (one__15_q == 0) begin + res = res__15_q[31:0]; + end else if (one__16 == 0) begin + res = res__16[31:0]; + end else if (one__17 == 0) begin + res = res__17[31:0]; + end else if (one__18_q == 0) begin + res = res__18_q[31:0]; + end else if (one__19 == 0) begin + res = res__19[31:0]; + end else if (one__20 == 0) begin + res = res__20[31:0]; + end else if (one__21_q == 0) begin + res = res__21_q[31:0]; + end else if (one__22 == 0) begin + res = res__22[31:0]; + end else if (one__23 == 0) begin + res = res__23[31:0]; + end else if (one__24_q == 0) begin + res = res__24_q[31:0]; + end else if (one__25 == 0) begin + res = res__25[31:0]; + end else if (one__26 == 0) begin + res = res__26[31:0]; + end else if (one__27_q == 0) begin + res = res__27_q[31:0]; + end else if (one__28 == 0) begin + res = res__28[31:0]; + end else if (one__29 == 0) begin + res = res__29[31:0]; + end else if (one__30_q == 0) begin + res = res__30_q[31:0]; + end else if (one__31 == 0) begin + res = res__31[31:0]; + end else begin + res = res__32[31:0]; + end + + end + + +endmodule + +//--------------------------------------- +// A dual-port RAM 8192x32 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_8192x32 ( + input clk, + input we1, + input we2, + input [13 - 1 : 0] addr1, + input [32 - 1 : 0] data1, + output [32 - 1 : 0] out1, + input [13 - 1 : 0] addr2, + input [32 - 1 : 0] data2, + output [32 - 1 : 0] out2 +); + reg [32 - 1 : 0] ram[2**13 - 1 : 0]; + reg [32 - 1 : 0] data_out1; + reg [32 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 65536x36 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_65536x36 ( + input clk, + input we1, + input we2, + input [16 - 1 : 0] addr1, + input [36 - 1 : 0] data1, + output [36 - 1 : 0] out1, + input [16 - 1 : 0] addr2, + input [36 - 1 : 0] data2, + output [36 - 1 : 0] out2 +); + reg [36 - 1 : 0] ram[2**16 - 1 : 0]; + reg [36 - 1 : 0] data_out1; + reg [36 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 65536x18 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_65536x18 ( + input clk, + input we1, + input we2, + input [16 - 1 : 0] addr1, + input [18 - 1 : 0] data1, + output [18 - 1 : 0] out1, + input [16 - 1 : 0] addr2, + input [18 - 1 : 0] data2, + output [18 - 1 : 0] out2 +); + reg [18 - 1 : 0] ram[2**16 - 1 : 0]; + reg [18 - 1 : 0] data_out1; + reg [18 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 65536x8 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_65536x8 ( + input clk, + input we1, + input we2, + input [16 - 1 : 0] addr1, + input [8 - 1 : 0] data1, + output [8 - 1 : 0] out1, + input [16 - 1 : 0] addr2, + input [8 - 1 : 0] data2, + output [8 - 1 : 0] out2 +); + reg [8 - 1 : 0] ram[2**16 - 1 : 0]; + reg [8 - 1 : 0] data_out1; + reg [8 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A single-port RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [`MANTISSA_PRECISION - 1 : 0] addr, + input [31:0] data, + output [31:0] out ); + + reg [31:0] ram[2**`MANTISSA_PRECISION - 1 : 0]; + reg [31:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule + +//--------------------------------------- +// A single-port 1024x32bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram_1024x32 ( + input clk, + input we, + input [9:0] addr, + input [31:0] data, + output [31:0] out ); + + reg [31:0] ram[1023:0]; + reg [31:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v b/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v new file mode 100755 index 000000000..430f6a64b --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v @@ -0,0 +1,6858 @@ +`define n 32 +`define max_size 30 + + +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:43:40 EDT 2010 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 256 reg +// wsiM1_MByteEn O 32 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wmemiM_MCmd O 3 reg +// wmemiM_MReqLast O 1 reg +// wmemiM_MAddr O 36 reg +// wmemiM_MBurstLength O 12 reg +// wmemiM_MDataValid O 1 reg +// wmemiM_MDataLast O 1 reg +// wmemiM_MData O 128 reg +// wmemiM_MDataByteEn O 16 reg +// wmemiM_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 20 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 256 +// wsiS1_MByteEn I 32 +// wsiS1_MReqInfo I 8 +// wmemiM_SResp I 2 +// wmemiM_SData I 128 +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// wmemiM_SRespLast I 1 +// wmemiM_SCmdAccept I 1 +// wmemiM_SDataAccept I 1 +// +// No combinational paths from inputs to outputs +// +// + + + +module mkDelayWorker32B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n, + + wmemiM_MCmd, + + wmemiM_MReqLast, + + wmemiM_MAddr, + + wmemiM_MBurstLength, + + wmemiM_MDataValid, + + wmemiM_MDataLast, + + wmemiM_MData, + + wmemiM_MDataByteEn, + + wmemiM_SResp, + + wmemiM_SRespLast, + + wmemiM_SData, + + wmemiM_SCmdAccept, + + wmemiM_SDataAccept, + + wmemiM_MReset_n, + + prevent_hanging_nodes); + parameter [31 : 0] dlyCtrlInit = 32'b00000000000000000000000000000000; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [19 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [255 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [31 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [255 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [31 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // value method wmemiM_mCmd + output [2 : 0] wmemiM_MCmd; + + // value method wmemiM_mReqLast + output wmemiM_MReqLast; + + // value method wmemiM_mAddr + output [35 : 0] wmemiM_MAddr; + + // value method wmemiM_mBurstLength + output [11 : 0] wmemiM_MBurstLength; + + // value method wmemiM_mDataValid + output wmemiM_MDataValid; + + // value method wmemiM_mDataLast + output wmemiM_MDataLast; + + // value method wmemiM_mData + output [127 : 0] wmemiM_MData; + + // value method wmemiM_mDataByteEn + output [15 : 0] wmemiM_MDataByteEn; + + // action method wmemiM_sResp + input [1 : 0] wmemiM_SResp; + + // action method wmemiM_sRespLast + input wmemiM_SRespLast; + + // action method wmemiM_sData + input [127 : 0] wmemiM_SData; + + // action method wmemiM_sCmdAccept + input wmemiM_SCmdAccept; + + // action method wmemiM_sDataAccept + input wmemiM_SDataAccept; + + // value method wmemiM_mReset_n + output wmemiM_MReset_n; + + output prevent_hanging_nodes; + + // Hanging node logic + + + + wire dummy1; + wire dummy2; + wire dummy3; + wire dummy4; + wire dummy5; + wire dummy6; + wire dummy7; + wire dummy8; + wire dummy9; + assign dummy1 = &mesgRF_memory__DOB; + assign dummy2 = &mesgWF_memory__DOB; + assign dummy3 = &metaRF__D_OUT; + assign dummy4 = &metaWF__D_OUT ; + assign dummy5 = &wci_reqF__D_OUT; + assign dummy6 = &wide16Fa__D_OUT; + assign dummy7 = &wide16Fb__D_OUT; + assign dummy8 = &wmemi_respF__D_OUT; + assign dummy9 = &wsiS_reqFifo__D_OUT; + + wire prevent_hang_wire; + assign prevent_hang_wire = dummy1 & dummy2 & dummy3 & dummy4 &dummy5 & dummy6 & dummy7 & dummy8 & dummy9; + assign prevent_hanging_nodes = prevent_hang_wire; + + // signals for module outputs + wire [255 : 0] wsiM1_MData; + wire [127 : 0] wmemiM_MData; + wire [35 : 0] wmemiM_MAddr; + wire [31 : 0] wciS0_SData, wsiM1_MByteEn; + wire [15 : 0] wmemiM_MDataByteEn; + wire [11 : 0] wmemiM_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM1_MReqInfo; + wire [2 : 0] wmemiM_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wmemiM_MDataLast, + wmemiM_MDataValid, + wmemiM_MReqLast, + wmemiM_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [312 : 0] wsiM_reqFifo_x_wire__wget, wsiS_wsiReq__wget; + wire [255 : 0] mesgRF_wDataIn__wget, + mesgRF_wDataOut__wget, + mesgWF_wDataIn__wget, + mesgWF_wDataOut__wget, + wsi_Es_mData_w__wget; + wire [145 : 0] wmemi_dhF_x_wire__wget; + wire [130 : 0] wmemi_wmemiResponse__wget; + wire [127 : 0] wmemi_Em_sData_w__wget; + wire [95 : 0] wsiM_extStatusW__wget, wsiS_extStatusW__wget; + wire [59 : 0] wci_wciReq__wget; + wire [51 : 0] wmemi_reqF_x_wire__wget; + wire [33 : 0] wci_respF_x_wire__wget; + wire [31 : 0] wci_Es_mData_w__wget, wsi_Es_mByteEn_w__wget; + wire [19 : 0] dlyWordsStored_acc_v1__wget, + dlyWordsStored_acc_v2__wget, + wci_Es_mAddr_w__wget; + wire [11 : 0] wsi_Es_mBurstLength_w__wget; + wire [7 : 0] dlyReadCredit_acc_v1__wget, + dlyReadCredit_acc_v2__wget, + wsi_Es_mReqInfo_w__wget; + wire [3 : 0] wci_Es_mByteEn_w__wget; + wire [2 : 0] wci_Es_mCmd_w__wget, wci_wEdge__wget, wsi_Es_mCmd_w__wget; + wire [1 : 0] wmemi_Em_sResp_w__wget; + wire dlyReadCredit_acc_v1__whas, + dlyReadCredit_acc_v2__whas, + dlyWordsStored_acc_v1__whas, + dlyWordsStored_acc_v2__whas, + mesgRF_pwDequeue__whas, + mesgRF_pwEnqueue__whas, + mesgRF_wDataIn__whas, + mesgRF_wDataOut__whas, + mesgWF_pwDequeue__whas, + mesgWF_pwEnqueue__whas, + mesgWF_wDataIn__whas, + mesgWF_wDataOut__whas, + wci_Es_mAddrSpace_w__wget, + wci_Es_mAddrSpace_w__whas, + wci_Es_mAddr_w__whas, + wci_Es_mByteEn_w__whas, + wci_Es_mCmd_w__whas, + wci_Es_mData_w__whas, + wci_ctlAckReg_1__wget, + wci_ctlAckReg_1__whas, + wci_reqF_r_clr__whas, + wci_reqF_r_deq__whas, + wci_reqF_r_enq__whas, + wci_respF_dequeueing__whas, + wci_respF_enqueueing__whas, + wci_respF_x_wire__whas, + wci_sFlagReg_1__wget, + wci_sFlagReg_1__whas, + wci_sThreadBusy_pw__whas, + wci_wEdge__whas, + wci_wciReq__whas, + wci_wci_cfrd_pw__whas, + wci_wci_cfwr_pw__whas, + wci_wci_ctrl_pw__whas, + wmemi_Em_sData_w__whas, + wmemi_Em_sRespLast_w__whas, + wmemi_Em_sResp_w__whas, + wmemi_dhF_dequeueing__whas, + wmemi_dhF_enqueueing__whas, + wmemi_dhF_x_wire__whas, + wmemi_operateD_1__wget, + wmemi_operateD_1__whas, + wmemi_peerIsReady_1__wget, + wmemi_peerIsReady_1__whas, + wmemi_reqF_dequeueing__whas, + wmemi_reqF_enqueueing__whas, + wmemi_reqF_x_wire__whas, + wmemi_sCmdAccept_w__wget, + wmemi_sCmdAccept_w__whas, + wmemi_sDataAccept_w__wget, + wmemi_sDataAccept_w__whas, + wmemi_wmemiResponse__whas, + wsiM_operateD_1__wget, + wsiM_operateD_1__whas, + wsiM_peerIsReady_1__wget, + wsiM_peerIsReady_1__whas, + wsiM_reqFifo_dequeueing__whas, + wsiM_reqFifo_enqueueing__whas, + wsiM_reqFifo_x_wire__whas, + wsiM_sThreadBusy_pw__whas, + wsiS_operateD_1__wget, + wsiS_operateD_1__whas, + wsiS_peerIsReady_1__wget, + wsiS_peerIsReady_1__whas, + wsiS_reqFifo_r_clr__whas, + wsiS_reqFifo_r_deq__whas, + wsiS_reqFifo_r_enq__whas, + wsiS_wsiReq__whas, + wsi_Es_mBurstLength_w__whas, + wsi_Es_mBurstPrecise_w__whas, + wsi_Es_mByteEn_w__whas, + wsi_Es_mCmd_w__whas, + wsi_Es_mDataInfo_w__whas, + wsi_Es_mData_w__whas, + wsi_Es_mReqInfo_w__whas, + wsi_Es_mReqLast_w__whas; + + // register abortCount + reg [31 : 0] abortCount; + wire [31 : 0] abortCount__D_IN; + wire abortCount__EN; + + // register blockDelayWrite + reg blockDelayWrite; + wire blockDelayWrite__D_IN, blockDelayWrite__EN; + + // register bytesRead + reg [31 : 0] bytesRead; + wire [31 : 0] bytesRead__D_IN; + wire bytesRead__EN; + + // register bytesWritten + reg [31 : 0] bytesWritten; + wire [31 : 0] bytesWritten__D_IN; + wire bytesWritten__EN; + + // register cyclesPassed + reg [31 : 0] cyclesPassed; + wire [31 : 0] cyclesPassed__D_IN; + wire cyclesPassed__EN; + + // register dlyCtrl + reg [31 : 0] dlyCtrl; + wire [31 : 0] dlyCtrl__D_IN; + wire dlyCtrl__EN; + + // register dlyHoldoffBytes + reg [31 : 0] dlyHoldoffBytes; + wire [31 : 0] dlyHoldoffBytes__D_IN; + wire dlyHoldoffBytes__EN; + + // register dlyHoldoffCycles + reg [31 : 0] dlyHoldoffCycles; + wire [31 : 0] dlyHoldoffCycles__D_IN; + wire dlyHoldoffCycles__EN; + + // register dlyRAG + reg [19 : 0] dlyRAG; + wire [19 : 0] dlyRAG__D_IN; + wire dlyRAG__EN; + + // register dlyReadCredit_value + reg [7 : 0] dlyReadCredit_value; + wire [7 : 0] dlyReadCredit_value__D_IN; + wire dlyReadCredit_value__EN; + + // register dlyWAG + reg [19 : 0] dlyWAG; + wire [19 : 0] dlyWAG__D_IN; + wire dlyWAG__EN; + + // register dlyWordsStored_value + reg [19 : 0] dlyWordsStored_value; + wire [19 : 0] dlyWordsStored_value__D_IN; + wire dlyWordsStored_value__EN; + + // register doAbort + reg doAbort; + wire doAbort__D_IN, doAbort__EN; + + // register endOfMessage + reg endOfMessage; + wire endOfMessage__D_IN, endOfMessage__EN; + + // register errCount // jluu removed because never used +// reg [255 : 0] errCount; +// wire [255 : 0] errCount__D_IN; +// wire errCount__EN; + + // register impreciseBurst + reg impreciseBurst; + reg impreciseBurst__D_IN; + wire impreciseBurst__EN; + + // register mesgLength + reg [14 : 0] mesgLength; + reg [14 : 0] mesgLength__D_IN; + wire mesgLength__EN; + + // register mesgLengthSoFar + reg [13 : 0] mesgLengthSoFar; + wire [13 : 0] mesgLengthSoFar__D_IN; + wire mesgLengthSoFar__EN; + + // register mesgRF_rCache + reg [267 : 0] mesgRF_rCache; + wire [267 : 0] mesgRF_rCache__D_IN; + wire mesgRF_rCache__EN; + + // register mesgRF_rRdPtr + reg [10 : 0] mesgRF_rRdPtr; + wire [10 : 0] mesgRF_rRdPtr__D_IN; + wire mesgRF_rRdPtr__EN; + + // register mesgRF_rWrPtr + reg [10 : 0] mesgRF_rWrPtr; + wire [10 : 0] mesgRF_rWrPtr__D_IN; + wire mesgRF_rWrPtr__EN; + + // register mesgRdCount + reg [31 : 0] mesgRdCount; + wire [31 : 0] mesgRdCount__D_IN; + wire mesgRdCount__EN; + + // register mesgReqValid + reg mesgReqValid; + wire mesgReqValid__D_IN, mesgReqValid__EN; + + // register mesgWF_rCache + reg [267 : 0] mesgWF_rCache; + wire [267 : 0] mesgWF_rCache__D_IN; + wire mesgWF_rCache__EN; + + // register mesgWF_rRdPtr + reg [10 : 0] mesgWF_rRdPtr; + wire [10 : 0] mesgWF_rRdPtr__D_IN; + wire mesgWF_rRdPtr__EN; + + // register mesgWF_rWrPtr + reg [10 : 0] mesgWF_rWrPtr; + wire [10 : 0] mesgWF_rWrPtr__D_IN; + wire mesgWF_rWrPtr__EN; + + // register mesgWtCount + reg [31 : 0] mesgWtCount; + wire [31 : 0] mesgWtCount__D_IN; + wire mesgWtCount__EN; + + // register opcode + reg [8 : 0] opcode; + reg [8 : 0] opcode__D_IN; + wire opcode__EN; + + // register preciseBurst + reg preciseBurst; + reg preciseBurst__D_IN; + wire preciseBurst__EN; + + // register rdSerAddr + reg [31 : 0] rdSerAddr; + wire [31 : 0] rdSerAddr__D_IN; + wire rdSerAddr__EN; + + // register rdSerEmpty + reg rdSerEmpty; + wire rdSerEmpty__D_IN, rdSerEmpty__EN; + + // register rdSerMeta + reg [31 : 0] rdSerMeta; + wire [31 : 0] rdSerMeta__D_IN; + wire rdSerMeta__EN; + + // register rdSerPos + reg [1 : 0] rdSerPos; + wire [1 : 0] rdSerPos__D_IN; + wire rdSerPos__EN; + + // register rdSerStage + reg [31 : 0] rdSerStage; + wire [31 : 0] rdSerStage__D_IN; + wire rdSerStage__EN; + + // register rdSerStage_1 + reg [31 : 0] rdSerStage_1; + wire [31 : 0] rdSerStage_1__D_IN; + wire rdSerStage_1__EN; + + // register rdSerStage_2 + reg [31 : 0] rdSerStage_2; + wire [31 : 0] rdSerStage_2__D_IN; + wire rdSerStage_2__EN; + + // register rdSerStage_3 + reg [31 : 0] rdSerStage_3; + wire [31 : 0] rdSerStage_3__D_IN; + wire rdSerStage_3__EN; + + // register rdSerUnroll + reg [15 : 0] rdSerUnroll; + wire [15 : 0] rdSerUnroll__D_IN; + wire rdSerUnroll__EN; + + // register rdSyncWord + reg rdSyncWord; + reg rdSyncWord__D_IN; + wire rdSyncWord__EN; + + // register readMeta + reg [31 : 0] readMeta; + wire [31 : 0] readMeta__D_IN; + wire readMeta__EN; + + // register readyToPush + reg readyToPush; + reg readyToPush__D_IN; + wire readyToPush__EN; + + // register readyToRequest + reg readyToRequest; + wire readyToRequest__D_IN, readyToRequest__EN; + + // register unrollCnt + reg [15 : 0] unrollCnt; + wire [15 : 0] unrollCnt__D_IN; + wire unrollCnt__EN; + + // register valExpect +// reg [255 : 0] valExpect; +// wire [255 : 0] valExpect__D_IN; +// wire valExpect__EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge__D_IN; + wire wci_cEdge__EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState__D_IN; + wire wci_cState__EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg__D_IN, wci_ctlAckReg__EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive__D_IN, wci_ctlOpActive__EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge__D_IN, wci_illegalEdge__EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState__D_IN; + wire wci_nState__EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg__D_IN; + wire wci_reqF_countReg__EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r__D_IN; + wire wci_respF_c_r__EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0__D_IN; + wire wci_respF_q_0__EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1__D_IN; + wire wci_respF_q_1__EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg__D_IN, wci_sFlagReg__EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d__D_IN, wci_sThreadBusy_d__EN; + + // register wmemiRdReq + reg [31 : 0] wmemiRdReq; + wire [31 : 0] wmemiRdReq__D_IN; + wire wmemiRdReq__EN; + + // register wmemiRdResp + reg [31 : 0] wmemiRdResp; + wire [31 : 0] wmemiRdResp__D_IN; + wire wmemiRdResp__EN; + + // register wmemiWrReq + reg [31 : 0] wmemiWrReq; + wire [31 : 0] wmemiWrReq__D_IN; + wire wmemiWrReq__EN; + + // register wmemi_busyWithMessage + reg wmemi_busyWithMessage; + wire wmemi_busyWithMessage__D_IN, wmemi_busyWithMessage__EN; + + // register wmemi_dhF_c_r + reg [1 : 0] wmemi_dhF_c_r; + wire [1 : 0] wmemi_dhF_c_r__D_IN; + wire wmemi_dhF_c_r__EN; + + // register wmemi_dhF_q_0 + reg [145 : 0] wmemi_dhF_q_0; + reg [145 : 0] wmemi_dhF_q_0__D_IN; + wire wmemi_dhF_q_0__EN; + + // register wmemi_dhF_q_1 + reg [145 : 0] wmemi_dhF_q_1; + reg [145 : 0] wmemi_dhF_q_1__D_IN; + wire wmemi_dhF_q_1__EN; + + // register wmemi_errorSticky + reg wmemi_errorSticky; + wire wmemi_errorSticky__D_IN, wmemi_errorSticky__EN; + + // register wmemi_operateD + reg wmemi_operateD; + wire wmemi_operateD__D_IN, wmemi_operateD__EN; + + // register wmemi_peerIsReady + reg wmemi_peerIsReady; + wire wmemi_peerIsReady__D_IN, wmemi_peerIsReady__EN; + + // register wmemi_reqF_c_r + reg [1 : 0] wmemi_reqF_c_r; + wire [1 : 0] wmemi_reqF_c_r__D_IN; + wire wmemi_reqF_c_r__EN; + + // register wmemi_reqF_q_0 + reg [51 : 0] wmemi_reqF_q_0; + reg [51 : 0] wmemi_reqF_q_0__D_IN; + wire wmemi_reqF_q_0__EN; + + // register wmemi_reqF_q_1 + reg [51 : 0] wmemi_reqF_q_1; + reg [51 : 0] wmemi_reqF_q_1__D_IN; + wire wmemi_reqF_q_1__EN; + + // register wmemi_statusR + reg [7 : 0] wmemi_statusR; + wire [7 : 0] wmemi_statusR__D_IN; + wire wmemi_statusR__EN; + + // register wmemi_trafficSticky + reg wmemi_trafficSticky; + wire wmemi_trafficSticky__D_IN, wmemi_trafficSticky__EN; + + // register wrtDutyCount + reg [2 : 0] wrtDutyCount; + wire [2 : 0] wrtDutyCount__D_IN; + wire wrtDutyCount__EN; + + // register wrtSerAddr + reg [31 : 0] wrtSerAddr; + wire [31 : 0] wrtSerAddr__D_IN; + wire wrtSerAddr__EN; + + // register wrtSerMeta + reg [31 : 0] wrtSerMeta; + wire [31 : 0] wrtSerMeta__D_IN; + wire wrtSerMeta__EN; + + // register wrtSerPos + reg [1 : 0] wrtSerPos; + wire [1 : 0] wrtSerPos__D_IN; + wire wrtSerPos__EN; + + // register wrtSerStage + reg [31 : 0] wrtSerStage; + wire [31 : 0] wrtSerStage__D_IN; + wire wrtSerStage__EN; + + // register wrtSerStage_1 + reg [31 : 0] wrtSerStage_1; + wire [31 : 0] wrtSerStage_1__D_IN; + wire wrtSerStage_1__EN; + + // register wrtSerStage_2 + reg [31 : 0] wrtSerStage_2; + wire [31 : 0] wrtSerStage_2__D_IN; + wire wrtSerStage_2__EN; + + // register wrtSerStage_3 + reg [31 : 0] wrtSerStage_3; + wire [31 : 0] wrtSerStage_3__D_IN; + wire wrtSerStage_3__EN; + + // register wrtSerUnroll + reg [15 : 0] wrtSerUnroll; + wire [15 : 0] wrtSerUnroll__D_IN; + wire wrtSerUnroll__EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind__D_IN; + wire wsiM_burstKind__EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky__D_IN, wsiM_errorSticky__EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount__D_IN; + wire wsiM_iMesgCount__EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD__D_IN, wsiM_operateD__EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount__D_IN; + wire wsiM_pMesgCount__EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady__D_IN, wsiM_peerIsReady__EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r__D_IN; + wire wsiM_reqFifo_c_r__EN; + + // register wsiM_reqFifo_q_0 + reg [312 : 0] wsiM_reqFifo_q_0; + reg [312 : 0] wsiM_reqFifo_q_0__D_IN; + wire wsiM_reqFifo_q_0__EN; + + // register wsiM_reqFifo_q_1 + reg [312 : 0] wsiM_reqFifo_q_1; + reg [312 : 0] wsiM_reqFifo_q_1__D_IN; + wire wsiM_reqFifo_q_1__EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d__D_IN, wsiM_sThreadBusy_d__EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR__D_IN; + wire wsiM_statusR__EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount__D_IN; + wire wsiM_tBusyCount__EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky__D_IN, wsiM_trafficSticky__EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind__D_IN; + wire wsiS_burstKind__EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky__D_IN, wsiS_errorSticky__EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount__D_IN; + wire wsiS_iMesgCount__EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD__D_IN, wsiS_operateD__EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount__D_IN; + wire wsiS_pMesgCount__EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady__D_IN, wsiS_peerIsReady__EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg__D_IN; + wire wsiS_reqFifo_countReg__EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR__D_IN; + wire wsiS_statusR__EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount__D_IN; + wire wsiS_tBusyCount__EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky__D_IN, wsiS_trafficSticky__EN; + + // register wsiWordsRemain + reg [11 : 0] wsiWordsRemain; + wire [11 : 0] wsiWordsRemain__D_IN; + wire wsiWordsRemain__EN; + + // register zeroLengthMesg + reg zeroLengthMesg; + wire zeroLengthMesg__D_IN, zeroLengthMesg__EN; + + // ports of submodule mesgRF_memory + wire [255 : 0] mesgRF_memory__DIA, mesgRF_memory__DIB, mesgRF_memory__DOB; + wire [9 : 0] mesgRF_memory__ADDRA, mesgRF_memory__ADDRB; + wire mesgRF_memory__ENA, + mesgRF_memory__ENB, + mesgRF_memory__WEA, + mesgRF_memory__WEB; + + // ports of submodule mesgWF_memory + wire [255 : 0] mesgWF_memory__DIA, mesgWF_memory__DIB, mesgWF_memory__DOB; + wire [9 : 0] mesgWF_memory__ADDRA, mesgWF_memory__ADDRB; + wire mesgWF_memory__ENA, + mesgWF_memory__ENB, + mesgWF_memory__WEA, + mesgWF_memory__WEB; + + // ports of submodule metaRF + reg [31 : 0] metaRF__D_IN; + wire [31 : 0] metaRF__D_OUT; + wire metaRF__CLR, metaRF__DEQ, metaRF__EMPTY_N, metaRF__ENQ, metaRF__FULL_N; + + // ports of submodule metaWF + wire [31 : 0] metaWF__D_IN, metaWF__D_OUT; + wire metaWF__CLR, metaWF__DEQ, metaWF__EMPTY_N, metaWF__ENQ, metaWF__FULL_N; + + // ports of submodule wci_isReset + wire wci_isReset__VAL; + + // ports of submodule wci_reqF + wire [59 : 0] wci_reqF__D_IN, wci_reqF__D_OUT; + wire wci_reqF__CLR, wci_reqF__DEQ, wci_reqF__EMPTY_N, wci_reqF__ENQ; + + // ports of submodule wide16Fa + wire [127 : 0] wide16Fa__D_IN, wide16Fa__D_OUT; + wire wide16Fa__CLR, + wide16Fa__DEQ, + wide16Fa__EMPTY_N, + wide16Fa__ENQ, + wide16Fa__FULL_N; + + // ports of submodule wide16Fb + wire [127 : 0] wide16Fb__D_IN, wide16Fb__D_OUT; + wire wide16Fb__CLR, + wide16Fb__DEQ, + wide16Fb__EMPTY_N, + wide16Fb__ENQ, + wide16Fb__FULL_N; + + // ports of submodule wmemi_isReset + wire wmemi_isReset__VAL; + + // ports of submodule wmemi_respF + wire [130 : 0] wmemi_respF__D_IN, wmemi_respF__D_OUT; + wire wmemi_respF__CLR, + wmemi_respF__DEQ, + wmemi_respF__EMPTY_N, + wmemi_respF__ENQ, + wmemi_respF__FULL_N; + + // ports of submodule wsiM_isReset + wire wsiM_isReset__VAL; + + // ports of submodule wsiS_isReset + wire wsiS_isReset__VAL; + + // ports of submodule wsiS_reqFifo + wire [312 : 0] wsiS_reqFifo__D_IN, wsiS_reqFifo__D_OUT; + wire wsiS_reqFifo__CLR, + wsiS_reqFifo__DEQ, + wsiS_reqFifo__EMPTY_N, + wsiS_reqFifo__ENQ, + wsiS_reqFifo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_cycles_passed_count, + CAN_FIRE_RL_delay_read_req, + CAN_FIRE_RL_delay_read_resp, + CAN_FIRE_RL_delay_write_req, + CAN_FIRE_RL_delay_write_unblock, + CAN_FIRE_RL_dlyReadCredit_accumulate, + CAN_FIRE_RL_dlyWordsStored_accumulate, + CAN_FIRE_RL_mesgRF_portA, + CAN_FIRE_RL_mesgRF_portB, + CAN_FIRE_RL_mesgRF_portB_read_data, + CAN_FIRE_RL_mesgWF_portA, + CAN_FIRE_RL_mesgWF_portB, + CAN_FIRE_RL_mesgWF_portB_read_data, + CAN_FIRE_RL_operating_actions, + CAN_FIRE_RL_rdSer_begin, + CAN_FIRE_RL_rdSer_body, + CAN_FIRE_RL_rdSer_sync, + CAN_FIRE_RL_wci_Es_doAlways_Req, + CAN_FIRE_RL_wci_cfrd, + CAN_FIRE_RL_wci_cfwr, + CAN_FIRE_RL_wci_ctlAckReg__dreg_update, + CAN_FIRE_RL_wci_ctl_op_complete, + CAN_FIRE_RL_wci_ctl_op_start, + CAN_FIRE_RL_wci_ctrl_EiI, + CAN_FIRE_RL_wci_ctrl_IsO, + CAN_FIRE_RL_wci_ctrl_OrE, + CAN_FIRE_RL_wci_reqF__updateLevelCounter, + CAN_FIRE_RL_wci_reqF_enq, + CAN_FIRE_RL_wci_request_decode, + CAN_FIRE_RL_wci_respF_both, + CAN_FIRE_RL_wci_respF_decCtr, + CAN_FIRE_RL_wci_respF_deq, + CAN_FIRE_RL_wci_respF_incCtr, + CAN_FIRE_RL_wci_sFlagReg__dreg_update, + CAN_FIRE_RL_wci_sThreadBusy_reg, + CAN_FIRE_RL_wmemi_Em_doAlways, + CAN_FIRE_RL_wmemi_dhF_both, + CAN_FIRE_RL_wmemi_dhF_decCtr, + CAN_FIRE_RL_wmemi_dhF_deq, + CAN_FIRE_RL_wmemi_dhF_incCtr, + CAN_FIRE_RL_wmemi_operateD__dreg_update, + CAN_FIRE_RL_wmemi_peerIsReady__dreg_update, + CAN_FIRE_RL_wmemi_reqF_both, + CAN_FIRE_RL_wmemi_reqF_decCtr, + CAN_FIRE_RL_wmemi_reqF_deq, + CAN_FIRE_RL_wmemi_reqF_incCtr, + CAN_FIRE_RL_wmemi_respAdvance, + CAN_FIRE_RL_wmemi_update_statusR, + CAN_FIRE_RL_wmrd_mesgBegin, + CAN_FIRE_RL_wmrd_mesgBodyResponse, + CAN_FIRE_RL_wmwt_doAbort, + CAN_FIRE_RL_wmwt_mesgBegin, + CAN_FIRE_RL_wmwt_messageFinalize, + CAN_FIRE_RL_wmwt_messagePushImprecise, + CAN_FIRE_RL_wmwt_messagePushPrecise, + CAN_FIRE_RL_wmwt_requestPrecise, + CAN_FIRE_RL_wrtSer_begin, + CAN_FIRE_RL_wrtSer_body, + CAN_FIRE_RL_wsiM_ext_status_assign, + CAN_FIRE_RL_wsiM_inc_tBusyCount, + CAN_FIRE_RL_wsiM_operateD__dreg_update, + CAN_FIRE_RL_wsiM_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiM_reqFifo_both, + CAN_FIRE_RL_wsiM_reqFifo_decCtr, + CAN_FIRE_RL_wsiM_reqFifo_deq, + CAN_FIRE_RL_wsiM_reqFifo_incCtr, + CAN_FIRE_RL_wsiM_sThreadBusy_reg, + CAN_FIRE_RL_wsiM_update_statusR, + CAN_FIRE_RL_wsiS_ext_status_assign, + CAN_FIRE_RL_wsiS_inc_tBusyCount, + CAN_FIRE_RL_wsiS_operateD__dreg_update, + CAN_FIRE_RL_wsiS_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + CAN_FIRE_RL_wsiS_reqFifo_enq, + CAN_FIRE_RL_wsiS_update_statusR, + CAN_FIRE_RL_wsi_Es_doAlways, + CAN_FIRE_RL_wsipass_doMessagePush, + CAN_FIRE_wciS0_mAddr, + CAN_FIRE_wciS0_mAddrSpace, + CAN_FIRE_wciS0_mByteEn, + CAN_FIRE_wciS0_mCmd, + CAN_FIRE_wciS0_mData, + CAN_FIRE_wciS0_mFlag, + CAN_FIRE_wmemiM_sCmdAccept, + CAN_FIRE_wmemiM_sData, + CAN_FIRE_wmemiM_sDataAccept, + CAN_FIRE_wmemiM_sResp, + CAN_FIRE_wmemiM_sRespLast, + CAN_FIRE_wsiM1_sReset_n, + CAN_FIRE_wsiM1_sThreadBusy, + CAN_FIRE_wsiS1_mBurstLength, + CAN_FIRE_wsiS1_mBurstPrecise, + CAN_FIRE_wsiS1_mByteEn, + CAN_FIRE_wsiS1_mCmd, + CAN_FIRE_wsiS1_mData, + CAN_FIRE_wsiS1_mDataInfo, + CAN_FIRE_wsiS1_mReqInfo, + CAN_FIRE_wsiS1_mReqLast, + CAN_FIRE_wsiS1_mReset_n, + WILL_FIRE_RL_cycles_passed_count, + WILL_FIRE_RL_delay_read_req, + WILL_FIRE_RL_delay_read_resp, + WILL_FIRE_RL_delay_write_req, + WILL_FIRE_RL_delay_write_unblock, + WILL_FIRE_RL_dlyReadCredit_accumulate, + WILL_FIRE_RL_dlyWordsStored_accumulate, + WILL_FIRE_RL_mesgRF_portA, + WILL_FIRE_RL_mesgRF_portB, + WILL_FIRE_RL_mesgRF_portB_read_data, + WILL_FIRE_RL_mesgWF_portA, + WILL_FIRE_RL_mesgWF_portB, + WILL_FIRE_RL_mesgWF_portB_read_data, + WILL_FIRE_RL_operating_actions, + WILL_FIRE_RL_rdSer_begin, + WILL_FIRE_RL_rdSer_body, + WILL_FIRE_RL_rdSer_sync, + WILL_FIRE_RL_wci_Es_doAlways_Req, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctlAckReg__dreg_update, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_reqF__updateLevelCounter, + WILL_FIRE_RL_wci_reqF_enq, + WILL_FIRE_RL_wci_request_decode, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_deq, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wci_sFlagReg__dreg_update, + WILL_FIRE_RL_wci_sThreadBusy_reg, + WILL_FIRE_RL_wmemi_Em_doAlways, + WILL_FIRE_RL_wmemi_dhF_both, + WILL_FIRE_RL_wmemi_dhF_decCtr, + WILL_FIRE_RL_wmemi_dhF_deq, + WILL_FIRE_RL_wmemi_dhF_incCtr, + WILL_FIRE_RL_wmemi_operateD__dreg_update, + WILL_FIRE_RL_wmemi_peerIsReady__dreg_update, + WILL_FIRE_RL_wmemi_reqF_both, + WILL_FIRE_RL_wmemi_reqF_decCtr, + WILL_FIRE_RL_wmemi_reqF_deq, + WILL_FIRE_RL_wmemi_reqF_incCtr, + WILL_FIRE_RL_wmemi_respAdvance, + WILL_FIRE_RL_wmemi_update_statusR, + WILL_FIRE_RL_wmrd_mesgBegin, + WILL_FIRE_RL_wmrd_mesgBodyResponse, + WILL_FIRE_RL_wmwt_doAbort, + WILL_FIRE_RL_wmwt_mesgBegin, + WILL_FIRE_RL_wmwt_messageFinalize, + WILL_FIRE_RL_wmwt_messagePushImprecise, + WILL_FIRE_RL_wmwt_messagePushPrecise, + WILL_FIRE_RL_wmwt_requestPrecise, + WILL_FIRE_RL_wrtSer_begin, + WILL_FIRE_RL_wrtSer_body, + WILL_FIRE_RL_wsiM_ext_status_assign, + WILL_FIRE_RL_wsiM_inc_tBusyCount, + WILL_FIRE_RL_wsiM_operateD__dreg_update, + WILL_FIRE_RL_wsiM_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiM_sThreadBusy_reg, + WILL_FIRE_RL_wsiM_update_statusR, + WILL_FIRE_RL_wsiS_ext_status_assign, + WILL_FIRE_RL_wsiS_inc_tBusyCount, + WILL_FIRE_RL_wsiS_operateD__dreg_update, + WILL_FIRE_RL_wsiS_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_update_statusR, + WILL_FIRE_RL_wsi_Es_doAlways, + WILL_FIRE_RL_wsipass_doMessagePush, + WILL_FIRE_wciS0_mAddr, + WILL_FIRE_wciS0_mAddrSpace, + WILL_FIRE_wciS0_mByteEn, + WILL_FIRE_wciS0_mCmd, + WILL_FIRE_wciS0_mData, + WILL_FIRE_wciS0_mFlag, + WILL_FIRE_wmemiM_sCmdAccept, + WILL_FIRE_wmemiM_sData, + WILL_FIRE_wmemiM_sDataAccept, + WILL_FIRE_wmemiM_sResp, + WILL_FIRE_wmemiM_sRespLast, + WILL_FIRE_wsiM1_sReset_n, + WILL_FIRE_wsiM1_sThreadBusy, + WILL_FIRE_wsiS1_mBurstLength, + WILL_FIRE_wsiS1_mBurstPrecise, + WILL_FIRE_wsiS1_mByteEn, + WILL_FIRE_wsiS1_mCmd, + WILL_FIRE_wsiS1_mData, + WILL_FIRE_wsiS1_mDataInfo, + WILL_FIRE_wsiS1_mReqInfo, + WILL_FIRE_wsiS1_mReqLast, + WILL_FIRE_wsiS1_mReset_n; + + // inputs to muxes for submodule ports + reg [127 : 0] MUX_wide16Fa__enq_1__VAL_1, MUX_wide16Fa__enq_1__VAL_2; + reg [33 : 0] MUX_wci_respF_q_0__write_1__VAL_2; + wire [312 : 0] MUX_wsiM_reqFifo_q_0__write_1__VAL_1, + MUX_wsiM_reqFifo_q_0__write_1__VAL_2, + MUX_wsiM_reqFifo_q_1__write_1__VAL_1, + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1; + wire [145 : 0] MUX_wmemi_dhF_q_0__write_1__VAL_1, + MUX_wmemi_dhF_q_0__write_1__VAL_2, + MUX_wmemi_dhF_q_1__write_1__VAL_1; + wire [51 : 0] MUX_wmemi_reqF_q_0__write_1__VAL_1, + MUX_wmemi_reqF_q_0__write_1__VAL_2, + MUX_wmemi_reqF_q_1__write_1__VAL_1, + MUX_wmemi_reqF_x_wire__wset_1__VAL_1, + MUX_wmemi_reqF_x_wire__wset_1__VAL_2; + wire [33 : 0] MUX_wci_respF_q_0__write_1__VAL_1, + MUX_wci_respF_q_1__write_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_2; + wire [31 : 0] MUX_mesgRdCount__write_1__VAL_1, + MUX_mesgWtCount__write_1__VAL_1, + MUX_metaWF__enq_1__VAL_1; + wire [19 : 0] MUX_dlyRAG__write_1__VAL_1, + MUX_dlyWAG__write_1__VAL_1, + MUX_dlyWordsStored_value__write_1__VAL_2; + wire [15 : 0] MUX_rdSerUnroll__write_1__VAL_2, + MUX_unrollCnt__write_1__VAL_1, + MUX_unrollCnt__write_1__VAL_2, + MUX_wrtSerUnroll__write_1__VAL_1; + wire [14 : 0] MUX_mesgLength__write_1__VAL_2, MUX_mesgLength__write_1__VAL_3; + wire [13 : 0] MUX_mesgLengthSoFar__write_1__VAL_2; + wire [11 : 0] MUX_wsiWordsRemain__write_1__VAL_2; + wire [8 : 0] MUX_opcode__write_1__VAL_2; + wire [7 : 0] MUX_dlyReadCredit_value__write_1__VAL_2; + wire [1 : 0] MUX_rdSerPos__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_2, + MUX_wmemi_dhF_c_r__write_1__VAL_1, + MUX_wmemi_dhF_c_r__write_1__VAL_2, + MUX_wmemi_reqF_c_r__write_1__VAL_1, + MUX_wmemi_reqF_c_r__write_1__VAL_2, + MUX_wrtSerPos__write_1__VAL_1, + MUX_wrtSerPos__write_1__VAL_2, + MUX_wsiM_reqFifo_c_r__write_1__VAL_1, + MUX_wsiM_reqFifo_c_r__write_1__VAL_2; + wire MUX_endOfMessage__write_1__SEL_1, + MUX_impreciseBurst__write_1__SEL_2, + MUX_mesgLength__write_1__SEL_2, + MUX_mesgRdCount__write_1__SEL_1, + MUX_metaWF__enq_1__SEL_1, + MUX_rdSerEmpty__write_1__PSEL_1, + MUX_rdSerEmpty__write_1__SEL_1, + MUX_rdSyncWord__write_1__VAL_1, + MUX_rdSyncWord__write_1__VAL_2, + MUX_wci_illegalEdge__write_1__SEL_1, + MUX_wci_illegalEdge__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__VAL_2, + MUX_wci_respF_q_0__write_1__SEL_2, + MUX_wci_respF_q_1__write_1__SEL_2, + MUX_wide16Fa__enq_1__SEL_1, + MUX_wmemi_dhF_q_0__write_1__SEL_2, + MUX_wmemi_dhF_q_1__write_1__SEL_2, + MUX_wmemi_reqF_q_0__write_1__SEL_2, + MUX_wmemi_reqF_q_1__write_1__SEL_2, + MUX_wrtSerStage__write_1__SEL_1, + MUX_wrtSerStage_1__write_1__SEL_1, + MUX_wrtSerStage_2__write_1__SEL_1, + MUX_wrtSerStage_3__write_1__SEL_1, + MUX_wsiM_reqFifo_q_0__write_1__SEL_2, + MUX_wsiM_reqFifo_q_1__write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h17561, + v__h17806, + v__h19118, + v__h19195, + v__h21672, + v__h2670, + v__h2817, + v__h3716; + reg [31 : 0] x_data__h21804; + reg CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1, + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904; + wire [255 : 0] mesg__h22346, x__h15234, x__h16160, x__h19905; + wire [127 : 0] IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354, + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377, + x1__h19969, + x1__h19978, + x1__h20492, + x1__h20501; + wire [35 : 0] addr__h20994, addr__h21166; + wire [31 : 0] rdat__h21847, + rdat__h22030, + rdat__h22038, + rdat__h22046, + rdat__h22054, + v__h22720, + x_byteEn__h22438; + wire [23 : 0] x1_length__h17254, x__h21052, x__h21211, x__h21850; + wire [13 : 0] mlp1__h17953, x__h17298; + wire [11 : 0] x_burstLength__h22437; + wire [10 : 0] x__h15126, x__h16052; + wire [7 : 0] x1_opcode__h17253; + wire [1 : 0] wrtSerPos_11_PLUS_1___d1014; + wire NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272, + NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208, + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698, + _dor1bytesWritten__EN_write, + metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242, + metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365, + wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397; + + // action method wciS0_mCmd + assign CAN_FIRE_wciS0_mCmd = 1'b1 ; + assign WILL_FIRE_wciS0_mCmd = 1'b1 ; + + // action method wciS0_mAddrSpace + assign CAN_FIRE_wciS0_mAddrSpace = 1'b1 ; + assign WILL_FIRE_wciS0_mAddrSpace = 1'b1 ; + + // action method wciS0_mByteEn + assign CAN_FIRE_wciS0_mByteEn = 1'b1 ; + assign WILL_FIRE_wciS0_mByteEn = 1'b1 ; + + // action method wciS0_mAddr + assign CAN_FIRE_wciS0_mAddr = 1'b1 ; + assign WILL_FIRE_wciS0_mAddr = 1'b1 ; + + // action method wciS0_mData + assign CAN_FIRE_wciS0_mData = 1'b1 ; + assign WILL_FIRE_wciS0_mData = 1'b1 ; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = wci_reqF_countReg > 2'b01 || wci_isReset__VAL ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'b1, wci_sFlagReg } ; + + // action method wciS0_mFlag + assign CAN_FIRE_wciS0_mFlag = 1'b1 ; + assign WILL_FIRE_wciS0_mFlag = 1'b1 ; + + // action method wsiS1_mCmd + assign CAN_FIRE_wsiS1_mCmd = 1'b1 ; + assign WILL_FIRE_wsiS1_mCmd = 1'b1 ; + + // action method wsiS1_mReqLast + assign CAN_FIRE_wsiS1_mReqLast = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ; + + // action method wsiS1_mBurstPrecise + assign CAN_FIRE_wsiS1_mBurstPrecise = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ; + + // action method wsiS1_mBurstLength + assign CAN_FIRE_wsiS1_mBurstLength = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstLength = 1'b1 ; + + // action method wsiS1_mData + assign CAN_FIRE_wsiS1_mData = 1'b1 ; + assign WILL_FIRE_wsiS1_mData = 1'b1 ; + + // action method wsiS1_mByteEn + assign CAN_FIRE_wsiS1_mByteEn = 1'b1 ; + assign WILL_FIRE_wsiS1_mByteEn = 1'b1 ; + + // action method wsiS1_mReqInfo + assign CAN_FIRE_wsiS1_mReqInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqInfo = 1'b1 ; + + // action method wsiS1_mDataInfo + assign CAN_FIRE_wsiS1_mDataInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mDataInfo = 1'b1 ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsiS_isReset__VAL && wsiS_operateD ; + + // action method wsiS1_mReset_n + assign CAN_FIRE_wsiS1_mReset_n = 1'b1 ; + assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'b000 : wsiM_reqFifo_q_0[312:310] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsiM_sThreadBusy_d ? 12'b00 : wsiM_reqFifo_q_0[307:296] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsiM_reqFifo_q_0[295:40] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsiM_reqFifo_q_0[39:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'b00000000 : wsiM_reqFifo_q_0[7:0] ; + + // action method wsiM1_sThreadBusy + assign CAN_FIRE_wsiM1_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsiM_isReset__VAL && wsiM_operateD ; + + // action method wsiM1_sReset_n + assign CAN_FIRE_wsiM1_sReset_n = 1'b1 ; + assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ; + + // value method wmemiM_mCmd + assign wmemiM_MCmd = wmemi_reqF_q_0[51:49] ; + + // value method wmemiM_mReqLast + assign wmemiM_MReqLast = wmemi_reqF_q_0[48] ; + + // value method wmemiM_mAddr + assign wmemiM_MAddr = wmemi_reqF_q_0[47:12] ; + + // value method wmemiM_mBurstLength + assign wmemiM_MBurstLength = wmemi_reqF_q_0[11:0] ; + + // value method wmemiM_mDataValid + assign wmemiM_MDataValid = wmemi_dhF_q_0[145] ; + + // value method wmemiM_mDataLast + assign wmemiM_MDataLast = wmemi_dhF_q_0[144] ; + + // value method wmemiM_mData + assign wmemiM_MData = wmemi_dhF_q_0[143:16] ; + + // value method wmemiM_mDataByteEn + assign wmemiM_MDataByteEn = wmemi_dhF_q_0[15:0] ; + + // action method wmemiM_sResp + assign CAN_FIRE_wmemiM_sResp = 1'b1 ; + assign WILL_FIRE_wmemiM_sResp = 1'b1 ; + + // action method wmemiM_sRespLast + assign CAN_FIRE_wmemiM_sRespLast = 1'b1 ; + assign WILL_FIRE_wmemiM_sRespLast = wmemiM_SRespLast ; + + // action method wmemiM_sData + assign CAN_FIRE_wmemiM_sData = 1'b1 ; + assign WILL_FIRE_wmemiM_sData = 1'b1 ; + + // action method wmemiM_sCmdAccept + assign CAN_FIRE_wmemiM_sCmdAccept = 1'b1 ; + assign WILL_FIRE_wmemiM_sCmdAccept = wmemiM_SCmdAccept ; + + // action method wmemiM_sDataAccept + assign CAN_FIRE_wmemiM_sDataAccept = 1'b1 ; + assign WILL_FIRE_wmemiM_sDataAccept = wmemiM_SDataAccept ; + + // value method wmemiM_mReset_n + assign wmemiM_MReset_n = !wmemi_isReset__VAL && wmemi_operateD ; + + // submodule mesgRF_memory + +// #(.PIPELINED(1'b0), +// .ADDR_WIDTH(32'b010), +// .DATA_WIDTH(32'b1056), +// .MEMSIZE(11'b1024)) mesgRF_memory + +wire [255:0] dp_out_not_used1; +wire [255:0] dp_out_not_used2; + + dual_port_ram_1024x256 dpram1 ( + .clk(wciS0_Clk), + .addr1(mesgRF_memory__ADDRA), + .addr2(mesgRF_memory__ADDRB), + .data1(mesgRF_memory__DIA), + .data2(mesgRF_memory__DIB), + .we1(mesgRF_memory__WEA), + .we2(mesgRF_memory__WEB), + .out1(dp_out_not_used1), + .out2(mesgRF_memory__DOB) + ); + + // submodule mesgWF_memory +//#(.PIPELINED(1'b0), +// .ADDR_WIDTH(32'b010), +// .DATA_WIDTH(32'b1056), +// .MEMSIZE(11'b1024)) mesgWF_memory( + + dual_port_ram_1024x256 dpram2 ( + .clk(wciS0_Clk), + .addr1(mesgWF_memory__ADDRA), + .addr2(mesgWF_memory__ADDRB), + .data1(mesgWF_memory__DIA), + .data2(mesgWF_memory__DIB), + .we1(mesgWF_memory__WEA), + .we2(mesgWF_memory__WEB), + .out1(dp_out_not_used2), + .out2(mesgWF_memory__DOB) + ); + + // submodule metaRF + arSRLFIFO_a ars1 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(metaRF__D_IN), + .ENQ(metaRF__ENQ), + .DEQ(metaRF__DEQ), + .CLR(metaRF__CLR), + .D_OUT(metaRF__D_OUT), + .EMPTY_N(metaRF__EMPTY_N), + .FULL_N(metaRF__FULL_N) + ); + + // submodule metaWF + arSRLFIFO_b ars2 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(metaWF__D_IN), + .ENQ(metaWF__ENQ), + .DEQ(metaWF__DEQ), + .CLR(metaWF__CLR), + .D_OUT(metaWF__D_OUT), + .EMPTY_N(metaWF__EMPTY_N), + .FULL_N(metaWF__FULL_N) + ); + + // submodule wci_isReset + ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset__VAL)); + + wire full_a_not_used; + // submodule wci_reqF + SizedFIFO_a sizefifo1 ( + .CLK(wciS0_Clk), + .D_IN(wci_reqF__D_IN), + .ENQ(wci_reqF__ENQ), + .DEQ(wci_reqF__DEQ), + .CLR(wci_reqF__CLR), + .D_OUT(wci_reqF__D_OUT), + .FULL_N(full_a_not_used), + .EMPTY_N(wci_reqF__EMPTY_N) + ); + + // submodule wide16Fa + arSRLFIFO_c ars3 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(wide16Fa__D_IN), + .ENQ(wide16Fa__ENQ), + .DEQ(wide16Fa__DEQ), + .CLR(wide16Fa__CLR), + .D_OUT(wide16Fa__D_OUT), + .EMPTY_N(wide16Fa__EMPTY_N), + .FULL_N(wide16Fa__FULL_N) + ); + + // submodule wide16Fb + arSRLFIFO_d ars4 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(wide16Fb__D_IN), + .ENQ(wide16Fb__ENQ), + .DEQ(wide16Fb__DEQ), + .CLR(wide16Fb__CLR), + .D_OUT(wide16Fb__D_OUT), + .EMPTY_N(wide16Fb__EMPTY_N), + .FULL_N(wide16Fb__FULL_N) + ); + + // submodule wmemi_isReset + ResetToBool wmemi_isReset(.RST(wciS0_MReset_n), .VAL(wmemi_isReset__VAL)); + + // submodule wmemi_respF +// #(.width(32'b0131), +// .guarded(32'b01)) wmemi_respF(.RST_N(wciS0_MReset_n), + SizedFIFO_x fifo_2 ( + .CLK(wciS0_Clk), + .D_IN(wmemi_respF__D_IN), + .ENQ(wmemi_respF__ENQ), + .DEQ(wmemi_respF__DEQ), + .CLR(wmemi_respF__CLR), + .D_OUT(wmemi_respF__D_OUT), + .FULL_N(wmemi_respF__FULL_N), + .EMPTY_N(wmemi_respF__EMPTY_N) + ); + + // submodule wsiM_isReset + ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset__VAL)); + + // submodule wsiS_isReset + ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset__VAL)); + + //#(.p1width(32'b1113), + // .p2depth(32'b11), + // .p3cntr_width(32'b01), + // .guarded(32'b01)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + // submodule wsiS_reqFifo + SizedFIFO_b sizefifo2 ( + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo__D_IN), + .ENQ(wsiS_reqFifo__ENQ), + .DEQ(wsiS_reqFifo__DEQ), + .CLR(wsiS_reqFifo__CLR), + .D_OUT(wsiS_reqFifo__D_OUT), + .FULL_N(wsiS_reqFifo__FULL_N), + .EMPTY_N(wsiS_reqFifo__EMPTY_N) + ); + + // rule RL_wci_request_decode + assign CAN_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + assign WILL_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + + // rule RL_wci_ctl_op_start + assign CAN_FIRE_RL_wci_ctl_op_start = + wci_reqF__EMPTY_N && wci_wci_ctrl_pw__whas ; + assign WILL_FIRE_RL_wci_ctl_op_start = + CAN_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign CAN_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b000 && + wci_reqF__D_OUT[36:34] == 3'b000 ; + assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ; + + // rule RL_wci_ctrl_OrE + assign CAN_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b010 && + wci_reqF__D_OUT[36:34] == 3'b011 ; + assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ; + + // rule RL_wci_respF_deq + assign CAN_FIRE_RL_wci_respF_deq = 1'b1 ; + assign WILL_FIRE_RL_wci_respF_deq = 1'b1 ; + + // rule RL_wmemi_update_statusR + assign CAN_FIRE_RL_wmemi_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wmemi_update_statusR = 1'b1 ; + + // rule RL_wci_sThreadBusy_reg + assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + + // rule RL_wci_sFlagReg__dreg_update + assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + + // rule RL_wsi_Es_doAlways + assign CAN_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + + // rule RL_wsiS_update_statusR + assign CAN_FIRE_RL_wsiS_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiS_update_statusR = 1'b1 ; + + // rule RL_wsiS_ext_status_assign + assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + + // rule RL_wsiS_inc_tBusyCount + assign CAN_FIRE_RL_wsiS_inc_tBusyCount = + wsiS_operateD && wsiS_peerIsReady && + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 ; + assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // rule RL_wsiS_reqFifo_enq + assign CAN_FIRE_RL_wsiS_reqFifo_enq = + wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq__wget[312:310] == 3'b001 ; + assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // rule RL_wsiS_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wsiM_update_statusR + assign CAN_FIRE_RL_wsiM_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiM_update_statusR = 1'b1 ; + + // rule RL_wsiM_ext_status_assign + assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + + // rule RL_wci_cfrd + assign CAN_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfrd_pw__whas ; + assign WILL_FIRE_RL_wci_cfrd = + CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wsiM_inc_tBusyCount + assign CAN_FIRE_RL_wsiM_inc_tBusyCount = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // rule RL_wsiM_reqFifo_deq + assign CAN_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'b00 && !wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_sThreadBusy_reg + assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + + // rule RL_wsiM_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_operating_actions + assign CAN_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + assign WILL_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + + // rule RL_wsiS_operateD__dreg_update + assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + + // rule RL_wsiM_operateD__dreg_update + assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + + // rule RL_wmrd_mesgBegin + assign CAN_FIRE_RL_wmrd_mesgBegin = + metaRF__EMPTY_N && wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && + unrollCnt == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ; + + // rule RL_wmwt_messageFinalize + assign CAN_FIRE_RL_wmwt_messageFinalize = + (!impreciseBurst || metaWF__FULL_N) && + wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397 ; + assign WILL_FIRE_RL_wmwt_messageFinalize = + CAN_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wci_Es_doAlways_Req + assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + + // rule RL_wci_reqF_enq + assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq__wget[59:57] != 3'b000 ; + assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ; + + // rule RL_wsipass_doMessagePush + assign CAN_FIRE_RL_wsipass_doMessagePush = + wsiM_reqFifo_c_r != 2'b10 && wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h0 ; + assign WILL_FIRE_RL_wsipass_doMessagePush = + CAN_FIRE_RL_wsipass_doMessagePush ; + + // rule RL_delay_write_req + assign CAN_FIRE_RL_delay_write_req = + wide16Fa__EMPTY_N && wmemi_reqF_c_r != 2'b10 && + wmemi_dhF_c_r != 2'b10 && + wmemi_operateD && + wmemi_peerIsReady && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + !blockDelayWrite ; + assign WILL_FIRE_RL_delay_write_req = CAN_FIRE_RL_delay_write_req ; + + // rule RL_delay_read_req + assign CAN_FIRE_RL_delay_read_req = + wmemi_reqF_c_r != 2'b10 && wmemi_operateD && wmemi_peerIsReady && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272 && + (dlyReadCredit_value ^ 8'h80) > 8'b10000000 ; + assign WILL_FIRE_RL_delay_read_req = + CAN_FIRE_RL_delay_read_req && !WILL_FIRE_RL_delay_write_req ; + + // rule RL_wmwt_messagePushPrecise + assign CAN_FIRE_RL_wmwt_messagePushPrecise = + mesgWF_rRdPtr + 11'b01000000000 != mesgWF_rWrPtr && + wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wsiWordsRemain != 12'b00 && + mesgReqValid && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushPrecise = + CAN_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_requestPrecise + assign CAN_FIRE_RL_wmwt_requestPrecise = + metaWF__FULL_N && wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && + readyToRequest && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_requestPrecise = + CAN_FIRE_RL_wmwt_requestPrecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_messagePushImprecise + assign CAN_FIRE_RL_wmwt_messagePushImprecise = + mesgWF_rRdPtr + 11'b01000000000 != mesgWF_rWrPtr && + wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + readyToPush && + impreciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushImprecise = + CAN_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wsiS_reqFifo__updateLevelCounter + assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq__whas ; + assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // rule RL_wmwt_mesgBegin + assign CAN_FIRE_RL_wmwt_mesgBegin = + wsiS_reqFifo__EMPTY_N && wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + !opcode[8] ; + assign WILL_FIRE_RL_wmwt_mesgBegin = + CAN_FIRE_RL_wmwt_mesgBegin && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_doAbort + assign CAN_FIRE_RL_wmwt_doAbort = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && doAbort ; + assign WILL_FIRE_RL_wmwt_doAbort = CAN_FIRE_RL_wmwt_doAbort ; + + // rule RL_wmemi_Em_doAlways + assign CAN_FIRE_RL_wmemi_Em_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wmemi_Em_doAlways = 1'b1 ; + + // rule RL_rdSer_sync + assign CAN_FIRE_RL_rdSer_sync = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && rdSyncWord ; + assign WILL_FIRE_RL_rdSer_sync = CAN_FIRE_RL_rdSer_sync ; + + // rule RL_rdSer_body + assign CAN_FIRE_RL_rdSer_body = + NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + rdSerUnroll != 16'b0000000000000000 && + !rdSyncWord ; + assign WILL_FIRE_RL_rdSer_body = CAN_FIRE_RL_rdSer_body ; + + // rule RL_rdSer_begin + assign CAN_FIRE_RL_rdSer_begin = + metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + rdSerUnroll == 16'b0000000000000000 && + !rdSyncWord ; + assign WILL_FIRE_RL_rdSer_begin = CAN_FIRE_RL_rdSer_begin ; + + // rule RL_delay_read_resp + assign CAN_FIRE_RL_delay_read_resp = + wide16Fb__FULL_N && wmemi_respF__EMPTY_N && wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 ; + assign WILL_FIRE_RL_delay_read_resp = CAN_FIRE_RL_delay_read_resp ; + + // rule RL_delay_write_unblock + assign CAN_FIRE_RL_delay_write_unblock = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && blockDelayWrite ; + assign WILL_FIRE_RL_delay_write_unblock = CAN_FIRE_RL_delay_write_unblock ; + + // rule RL_wrtSer_begin + assign CAN_FIRE_RL_wrtSer_begin = + metaWF__EMPTY_N && + metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wrtSerUnroll == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wrtSer_begin = CAN_FIRE_RL_wrtSer_begin ; + + // rule RL_cycles_passed_count + assign CAN_FIRE_RL_cycles_passed_count = wsiS_statusR[0] ; + assign WILL_FIRE_RL_cycles_passed_count = CAN_FIRE_RL_cycles_passed_count ; + + // rule RL_dlyWordsStored_accumulate + assign CAN_FIRE_RL_dlyWordsStored_accumulate = 1'b1 ; + assign WILL_FIRE_RL_dlyWordsStored_accumulate = 1'b1 ; + + // rule RL_dlyReadCredit_accumulate + assign CAN_FIRE_RL_dlyReadCredit_accumulate = 1'b1 ; + assign WILL_FIRE_RL_dlyReadCredit_accumulate = 1'b1 ; + + // rule RL_wci_ctrl_IsO + assign CAN_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b001 && + wci_reqF__D_OUT[36:34] == 3'b001 ; + assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ; + + // rule RL_mesgRF_portB_read_data + assign CAN_FIRE_RL_mesgRF_portB_read_data = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portB_read_data = 1'b1 ; + + // rule RL_wmrd_mesgBodyResponse + assign CAN_FIRE_RL_wmrd_mesgBodyResponse = + wsiM_reqFifo_c_r != 2'b10 && mesgRF_rRdPtr != mesgRF_rWrPtr && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + unrollCnt != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // rule RL_wsiM_reqFifo_both + assign CAN_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'b01) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b10 || wsiM_reqFifo_x_wire__whas) && + CAN_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ; + + // rule RL_wsiM_reqFifo_decCtr + assign CAN_FIRE_RL_wsiM_reqFifo_decCtr = + CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ; + + // rule RL_wsiM_reqFifo_incCtr + assign CAN_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'b00) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b01 || wsiM_reqFifo_x_wire__whas) && + wsiM_reqFifo_enqueueing__whas && + !CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ; + + // rule RL_mesgRF_portB + assign CAN_FIRE_RL_mesgRF_portB = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portB = 1'b1 ; + + // rule RL_mesgRF_portA + assign CAN_FIRE_RL_mesgRF_portA = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portA = 1'b1 ; + + // rule RL_mesgWF_portB_read_data + assign CAN_FIRE_RL_mesgWF_portB_read_data = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portB_read_data = 1'b1 ; + + // rule RL_wrtSer_body + assign CAN_FIRE_RL_wrtSer_body = + mesgWF_rRdPtr != mesgWF_rWrPtr && + CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 && + (wrtSerPos != 2'b11 && wrtSerUnroll != 16'b0000000000000001 || + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904) && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wrtSerUnroll != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wrtSer_body = CAN_FIRE_RL_wrtSer_body ; + + // rule RL_wci_ctl_op_complete + assign CAN_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'b10 && wci_ctlOpActive && wci_ctlAckReg ; + assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_cfwr + assign CAN_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfwr_pw__whas ; + assign WILL_FIRE_RL_wci_cfwr = + CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctlAckReg__dreg_update + assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + + // rule RL_wci_respF_both + assign CAN_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'b01) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b10 || wci_respF_x_wire__whas) && + wci_respF_c_r != 2'b00 && + wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ; + + // rule RL_wci_respF_decCtr + assign CAN_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'b00 && !wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ; + + // rule RL_wci_respF_incCtr + assign CAN_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'b00) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b01 || wci_respF_x_wire__whas) && + wci_respF_enqueueing__whas && + !(wci_respF_c_r != 2'b00) ; + assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ; + + // rule RL_wci_reqF__updateLevelCounter + assign CAN_FIRE_RL_wci_reqF__updateLevelCounter = + (wci_wciReq__wget[59:57] != 3'b000) != wci_reqF_r_deq__whas ; + assign WILL_FIRE_RL_wci_reqF__updateLevelCounter = + CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // rule RL_mesgWF_portB + assign CAN_FIRE_RL_mesgWF_portB = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portB = 1'b1 ; + + // rule RL_mesgWF_portA + assign CAN_FIRE_RL_mesgWF_portA = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portA = 1'b1 ; + + // rule RL_wmemi_respAdvance + assign CAN_FIRE_RL_wmemi_respAdvance = + wmemi_respF__FULL_N && wmemi_operateD && wmemi_peerIsReady && + wmemi_wmemiResponse__wget[130:129] != 2'b00 ; + assign WILL_FIRE_RL_wmemi_respAdvance = CAN_FIRE_RL_wmemi_respAdvance ; + + // rule RL_wmemi_peerIsReady__dreg_update + assign CAN_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wmemi_operateD__dreg_update + assign CAN_FIRE_RL_wmemi_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmemi_operateD__dreg_update = 1'b1 ; + + // rule RL_wmemi_dhF_deq + assign CAN_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ; + assign WILL_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ; + + // rule RL_wmemi_reqF_deq + assign CAN_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ; + assign WILL_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ; + + // rule RL_wmemi_dhF_both + assign CAN_FIRE_RL_wmemi_dhF_both = + ((wmemi_dhF_c_r == 2'b01) ? + CAN_FIRE_RL_delay_write_req : + wmemi_dhF_c_r != 2'b10 || CAN_FIRE_RL_delay_write_req) && + wmemi_dhF_dequeueing__whas && + CAN_FIRE_RL_delay_write_req ; + assign WILL_FIRE_RL_wmemi_dhF_both = CAN_FIRE_RL_wmemi_dhF_both ; + + // rule RL_wmemi_dhF_decCtr + assign CAN_FIRE_RL_wmemi_dhF_decCtr = + wmemi_dhF_dequeueing__whas && !CAN_FIRE_RL_delay_write_req ; + assign WILL_FIRE_RL_wmemi_dhF_decCtr = CAN_FIRE_RL_wmemi_dhF_decCtr ; + + // rule RL_wmemi_dhF_incCtr + assign CAN_FIRE_RL_wmemi_dhF_incCtr = + ((wmemi_dhF_c_r == 2'b00) ? + CAN_FIRE_RL_delay_write_req : + wmemi_dhF_c_r != 2'b01 || CAN_FIRE_RL_delay_write_req) && + CAN_FIRE_RL_delay_write_req && + !wmemi_dhF_dequeueing__whas ; + assign WILL_FIRE_RL_wmemi_dhF_incCtr = CAN_FIRE_RL_wmemi_dhF_incCtr ; + + // rule RL_wmemi_reqF_both + assign CAN_FIRE_RL_wmemi_reqF_both = + ((wmemi_reqF_c_r == 2'b01) ? + wmemi_reqF_enqueueing__whas : + wmemi_reqF_c_r != 2'b10 || wmemi_reqF_enqueueing__whas) && + wmemi_reqF_dequeueing__whas && + wmemi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_both = CAN_FIRE_RL_wmemi_reqF_both ; + + // rule RL_wmemi_reqF_incCtr + assign CAN_FIRE_RL_wmemi_reqF_incCtr = + ((wmemi_reqF_c_r == 2'b00) ? + wmemi_reqF_enqueueing__whas : + wmemi_reqF_c_r != 2'b01 || wmemi_reqF_enqueueing__whas) && + wmemi_reqF_enqueueing__whas && + !wmemi_reqF_dequeueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_incCtr = CAN_FIRE_RL_wmemi_reqF_incCtr ; + + // rule RL_wmemi_reqF_decCtr + assign CAN_FIRE_RL_wmemi_reqF_decCtr = + wmemi_reqF_dequeueing__whas && !wmemi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_decCtr = CAN_FIRE_RL_wmemi_reqF_decCtr ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge__write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge__write_1__VAL_2 = + wci_reqF__D_OUT[36:34] != 3'b100 && wci_reqF__D_OUT[36:34] != 3'b101 && + wci_reqF__D_OUT[36:34] != 3'b110 ; + assign MUX_wci_respF_c_r__write_1__VAL_2 = wci_respF_c_r + 2'b01 ; + assign MUX_wci_respF_c_r__write_1__VAL_1 = wci_respF_c_r - 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_2 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_illegalEdge__write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState != 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && wci_cState != 3'b001 && + wci_cState != 3'b011 || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState != 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && wci_cState != 3'b011 && + wci_cState != 3'b010 && + wci_cState != 3'b001 || + wci_reqF__D_OUT[36:34] == 3'b100 || + wci_reqF__D_OUT[36:34] == 3'b101 || + wci_reqF__D_OUT[36:34] == 3'b110 || + wci_reqF__D_OUT[36:34] == 3'b111) ; + assign MUX_wci_respF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 ; + assign MUX_wci_respF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_1 = wsiM_reqFifo_c_r - 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_2 = wsiM_reqFifo_c_r + 2'b01 ; + assign MUX_wsiM_reqFifo_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 ; + assign MUX_wsiM_reqFifo_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 ; + assign MUX_mesgLength__write_1__VAL_2 = + (wsiS_reqFifo__D_OUT[39:8] == 32'b00000000000000000000000000000000) ? + 15'b100000000000000 : + { 1'b1, wsiS_reqFifo__D_OUT[304:296], 5'b00000 } ; + assign MUX_mesgLengthSoFar__write_1__VAL_2 = mesgLengthSoFar + 14'b00000000000001 ; + assign MUX_opcode__write_1__VAL_2 = { 1'b1, wsiS_reqFifo__D_OUT[7:0] } ; + assign MUX_unrollCnt__write_1__VAL_1 = + (metaRF__D_OUT[23:0] == 24'b000000000000000000000000) ? 16'b0000000000000001 : metaRF__D_OUT[20:5] ; + assign MUX_unrollCnt__write_1__VAL_2 = unrollCnt - 16'b0000000000000001 ; + assign MUX_wsiWordsRemain__write_1__VAL_2 = wsiWordsRemain - 12'b01 ; + assign MUX_mesgLength__write_1__VAL_3 = { 1'b1, mlp1__h17953[8:0], 5'b00000 } ; + assign MUX_mesgRdCount__write_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 ; + assign MUX_dlyRAG__write_1__VAL_1 = dlyRAG + 20'b00000000000000000001 ; + assign MUX_dlyWAG__write_1__VAL_1 = dlyWAG + 20'b00000000000000000001 ; + assign MUX_mesgRdCount__write_1__VAL_1 = mesgRdCount + 32'b00000000000000000000000000000001 ; + assign MUX_mesgWtCount__write_1__VAL_1 = mesgWtCount + 32'b00000000000000000000000000000001 ; + assign MUX_metaWF__enq_1__VAL_1 = { x1_opcode__h17253, x1_length__h17254 } ; + assign MUX_rdSerPos__write_1__VAL_1 = rdSerPos + 2'b01 ; + assign MUX_rdSerUnroll__write_1__VAL_2 = rdSerUnroll - 16'b0000000000000001 ; + assign MUX_rdSyncWord__write_1__VAL_1 = + rdSerPos != 2'b11 && rdSerUnroll == 16'b0000000000000001 ; + assign MUX_wmemi_dhF_c_r__write_1__VAL_1 = wmemi_dhF_c_r - 2'b01 ; + assign MUX_wmemi_dhF_c_r__write_1__VAL_2 = wmemi_dhF_c_r + 2'b01 ; + assign MUX_wmemi_dhF_q_0__write_1__VAL_2 = + { 2'b11, wide16Fa__D_OUT, 16'b1111111111111111 } ; + assign MUX_wmemi_dhF_q_0__write_1__VAL_1 = + (wmemi_dhF_c_r == 2'b01) ? + MUX_wmemi_dhF_q_0__write_1__VAL_2 : + wmemi_dhF_q_1 ; + assign MUX_wmemi_dhF_q_1__write_1__VAL_1 = + (wmemi_dhF_c_r == 2'b10) ? + MUX_wmemi_dhF_q_0__write_1__VAL_2 : + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign MUX_wmemi_reqF_c_r__write_1__VAL_1 = wmemi_reqF_c_r - 2'b01 ; + assign MUX_wmemi_reqF_c_r__write_1__VAL_2 = wmemi_reqF_c_r + 2'b01 ; + assign MUX_wrtSerUnroll__write_1__VAL_1 = wrtSerUnroll - 16'b0000000000000001 ; + assign MUX_wmemi_dhF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b00 ; + assign MUX_wmemi_dhF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b01 ; + assign MUX_wmemi_reqF_x_wire__wset_1__VAL_1 = { 4'b0101, addr__h20994, 12'b01 } ; + assign MUX_wmemi_reqF_x_wire__wset_1__VAL_2 = { 4'b0011, addr__h21166, 12'b01 } ; + assign MUX_wci_respF_x_wire__wset_1__VAL_1 = { 2'b01, x_data__h21804 } ; + always@(WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0__write_1__VAL_2 = + MUX_wci_respF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0__write_1__VAL_2 = + MUX_wci_respF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0__write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0__write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_0__write_1__VAL_1 = + (wci_respF_c_r == 2'b01) ? + MUX_wci_respF_q_0__write_1__VAL_2 : + wci_respF_q_1 ; + assign MUX_wci_respF_q_1__write_1__VAL_1 = + (wci_respF_c_r == 2'b10) ? + MUX_wci_respF_q_0__write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_rdSyncWord__write_1__VAL_2 = + rdSerPos != 2'b11 && v__h22720[23:0] == 24'b000000000000000000000000 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 = + { 3'b001, + unrollCnt == 16'b0000000000000001, + 1'b1, + x_burstLength__h22437, + mesg__h22346, + x_byteEn__h22438, + readMeta[31:24] } ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_2 = + WILL_FIRE_RL_wmrd_mesgBodyResponse ? + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 : + wsiS_reqFifo__D_OUT ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b01) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b10) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + assign MUX_rdSerEmpty__write_1__PSEL_1 = + WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ; + assign MUX_rdSerEmpty__write_1__SEL_1 = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + assign MUX_dlyReadCredit_value__write_1__VAL_2 = + dlyReadCredit_value + + (WILL_FIRE_RL_delay_read_req ? 8'b11111111 : 8'b00000000) + + (CAN_FIRE_RL_delay_read_resp ? 8'b00000001 : 8'b00000000) ; + assign MUX_dlyWordsStored_value__write_1__VAL_2 = + dlyWordsStored_value + + (CAN_FIRE_RL_delay_write_req ? 20'b00000000000000000001 : 20'b00000000000000000000) + + (WILL_FIRE_RL_delay_read_req ? 20'b00000000000000000001: 20'b00000000000000000000) ; + assign MUX_wmemi_reqF_q_0__write_1__VAL_2 = + WILL_FIRE_RL_delay_read_req ? + MUX_wmemi_reqF_x_wire__wset_1__VAL_1 : + MUX_wmemi_reqF_x_wire__wset_1__VAL_2 ; + assign MUX_wmemi_reqF_q_0__write_1__VAL_1 = + (wmemi_reqF_c_r == 2'b01) ? + MUX_wmemi_reqF_q_0__write_1__VAL_2 : + wmemi_reqF_q_1 ; + assign MUX_wmemi_reqF_q_1__write_1__VAL_1 = + (wmemi_reqF_c_r == 2'b10) ? + MUX_wmemi_reqF_q_0__write_1__VAL_2 : + 52'h0AAAAAAAAAAAA ; + assign MUX_wmemi_reqF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b00 ; + assign MUX_wmemi_reqF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b01 ; + always@(wrtSerPos or + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354 or + x1__h19969 or x1__h19978) + begin + case (wrtSerPos) + 2'b00: MUX_wide16Fa__enq_1__VAL_2 = x1__h19969; + 2'b01: MUX_wide16Fa__enq_1__VAL_2 = x1__h19978; + default: MUX_wide16Fa__enq_1__VAL_2 = + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354; + endcase + end + always@(wrtSerPos or + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377 or + x1__h20492 or x1__h20501) + begin + case (wrtSerPos) + 2'b00: MUX_wide16Fa__enq_1__VAL_1 = x1__h20492; + 2'b01: MUX_wide16Fa__enq_1__VAL_1 = x1__h20501; + default: MUX_wide16Fa__enq_1__VAL_1 = + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377; + endcase + end + assign MUX_wrtSerPos__write_1__VAL_1 = + (wrtSerUnroll == 16'b0000000000000001) ? 2'b00 : wrtSerPos_11_PLUS_1___d1014 ; + assign MUX_wrtSerPos__write_1__VAL_2 = + (metaWF__D_OUT[23:0] == 24'b000000000000000000000000) ? + 2'b00 : + wrtSerPos_11_PLUS_1___d1014 ; + assign MUX_endOfMessage__write_1__SEL_1 = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 ; + assign MUX_impreciseBurst__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] ; + assign MUX_mesgLength__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] ; + assign MUX_metaWF__enq_1__SEL_1 = + WILL_FIRE_RL_wmwt_messageFinalize && impreciseBurst ; + assign MUX_wrtSerStage__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b00 ; + assign MUX_wrtSerStage_1__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b01 ; + assign MUX_wrtSerStage_2__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b10 ; + assign MUX_wrtSerStage_3__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b11 ; + assign MUX_wide16Fa__enq_1__SEL_1 = + WILL_FIRE_RL_wrtSer_begin && + (wrtSerPos == 2'b11 || metaWF__D_OUT[23:0] == 24'b000000000000000000000000) ; + + // inlined wires + assign wci_wciReq__whas = 1'b1 ; + assign wci_wciReq__wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_reqF_r_enq__whas = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF_r_clr__whas = 1'b0 ; + assign wci_respF_dequeueing__whas = wci_respF_c_r != 2'b00 ; + assign wci_wEdge__wget = wci_reqF__D_OUT[36:34] ; + assign wci_sThreadBusy_pw__whas = 1'b0 ; + assign wci_sFlagReg_1__wget = 1'b0 ; + assign wci_wci_cfwr_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b001 ; + assign wci_sFlagReg_1__whas = 1'b0 ; + assign wci_wci_cfrd_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_wci_ctrl_pw__whas = + wci_reqF__EMPTY_N && !wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_reqF_r_deq__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_respF_enqueueing__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_respF_x_wire__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_cfwr ; + assign wci_wEdge__whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_ctlAckReg_1__wget = 1'b1 ; + assign wci_ctlAckReg_1__whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wmemi_operateD_1__wget = 1'b1 ; + assign wmemi_operateD_1__whas = wci_cState == 3'b010 ; + assign wmemi_peerIsReady_1__whas = 1'b0 ; + assign wmemi_peerIsReady_1__wget = 1'b0 ; + assign wsiM_reqFifo_dequeueing__whas = CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw__whas = wsiM1_SThreadBusy ; + assign wsiM_operateD_1__wget = 1'b1 ; + assign wsiM_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiM_peerIsReady_1__wget = 1'b1 ; + assign wsiM_peerIsReady_1__whas = wsiM1_SReset_n ; + assign wsiM_extStatusW__wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + assign wsiS_reqFifo_r_clr__whas = 1'b0 ; + assign wsiS_wsiReq__wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsiS_wsiReq__whas = 1'b1 ; + assign wsiS_reqFifo_r_enq__whas = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_operateD_1__wget = 1'b1 ; + assign wsiS_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiS_peerIsReady_1__wget = 1'b1 ; + assign wsiS_peerIsReady_1__whas = wsiS1_MReset_n ; + assign wsiS_extStatusW__wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsi_Es_mCmd_w__wget = wsiS1_MCmd ; + assign wsi_Es_mCmd_w__whas = 1'b1 ; + assign wsi_Es_mReqLast_w__whas = wsiS1_MReqLast ; + assign wsi_Es_mBurstPrecise_w__whas = wsiS1_MBurstPrecise ; + assign wsi_Es_mBurstLength_w__wget = wsiS1_MBurstLength ; + assign wsi_Es_mBurstLength_w__whas = 1'b1 ; + assign wsi_Es_mData_w__wget = wsiS1_MData ; + assign wsi_Es_mData_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__wget = wsiS1_MByteEn ; + assign wsi_Es_mReqInfo_w__wget = wsiS1_MReqInfo ; + assign wsi_Es_mReqInfo_w__whas = 1'b1 ; + assign wsi_Es_mDataInfo_w__whas = 1'b1 ; + assign wsiM_reqFifo_enqueueing__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + assign wsiM_reqFifo_x_wire__whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wsipass_doMessagePush ; + assign wci_Es_mCmd_w__wget = wciS0_MCmd ; + assign wci_Es_mCmd_w__whas = 1'b1 ; + assign wci_Es_mAddrSpace_w__wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w__whas = 1'b1 ; + assign wci_Es_mAddr_w__wget = wciS0_MAddr ; + assign wci_Es_mAddr_w__whas = 1'b1 ; + assign wci_Es_mData_w__wget = wciS0_MData ; + assign wci_Es_mByteEn_w__wget = wciS0_MByteEn ; + assign wci_Es_mData_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__whas = 1'b1 ; + assign wmemi_reqF_dequeueing__whas = + wmemiM_SCmdAccept && wmemi_reqF_c_r != 2'b00 ; + assign wmemi_dhF_enqueueing__whas = CAN_FIRE_RL_delay_write_req ; + assign wmemi_dhF_x_wire__wget = MUX_wmemi_dhF_q_0__write_1__VAL_2 ; + assign wmemi_dhF_x_wire__whas = CAN_FIRE_RL_delay_write_req ; + assign wmemi_dhF_dequeueing__whas = + wmemiM_SDataAccept && wmemi_dhF_c_r != 2'b00 ; + assign wmemi_wmemiResponse__wget = + { wmemiM_SResp, wmemiM_SRespLast, wmemiM_SData } ; + assign wmemi_wmemiResponse__whas = 1'b1 ; + assign wmemi_sDataAccept_w__wget = 1'b1 ; + assign wmemi_sCmdAccept_w__wget = 1'b1 ; + assign wmemi_sCmdAccept_w__whas = wmemiM_SCmdAccept ; + assign wmemi_sDataAccept_w__whas = wmemiM_SDataAccept ; + assign mesgWF_wDataIn__wget = wsiS_reqFifo__D_OUT[295:40] ; + assign mesgWF_wDataOut__wget = + (mesgWF_rCache[267] && mesgWF_rCache[266:256] == mesgWF_rRdPtr) ? + mesgWF_rCache[255:0] : + mesgWF_memory__DOB ; + assign mesgRF_wDataIn__whas = CAN_FIRE_RL_rdSer_body ; + assign mesgWF_wDataOut__whas = 1'b1 ; + assign mesgRF_pwDequeue__whas = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign mesgRF_pwEnqueue__whas = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_wDataOut__wget = + (mesgRF_rCache[267] && mesgRF_rCache[266:256] == mesgRF_rRdPtr) ? + mesgRF_rCache[255:0] : + mesgRF_memory__DOB ; + assign mesgRF_wDataOut__whas = 1'b1 ; + assign dlyWordsStored_acc_v1__wget = 20'b00000000000000000001 ; + assign dlyWordsStored_acc_v1__whas = CAN_FIRE_RL_delay_write_req ; + assign dlyWordsStored_acc_v2__wget = 20'b00000000000000000001 ; + assign dlyReadCredit_acc_v1__wget = 8'b11111111 ; + assign dlyReadCredit_acc_v2__wget = 8'b00000001 ; + assign dlyReadCredit_acc_v2__whas = CAN_FIRE_RL_delay_read_resp ; + assign wmemi_Em_sResp_w__wget = wmemiM_SResp ; + assign wmemi_Em_sRespLast_w__whas = wmemiM_SRespLast ; + assign wmemi_Em_sResp_w__whas = 1'b1 ; + assign wmemi_Em_sData_w__wget = wmemiM_SData ; + assign wmemi_Em_sData_w__whas = 1'b1 ; + assign wci_respF_x_wire__wget = MUX_wci_respF_q_0__write_1__VAL_2 ; + assign mesgRF_wDataIn__wget = { 224'b000000000000000000000000, v__h22720 } ; + assign wsiM_reqFifo_x_wire__wget = MUX_wsiM_reqFifo_q_0__write_1__VAL_2 ; + assign wmemi_reqF_enqueueing__whas = + WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_delay_write_req ; + assign wmemi_reqF_x_wire__wget = MUX_wmemi_reqF_q_0__write_1__VAL_2 ; + assign wmemi_reqF_x_wire__whas = wmemi_reqF_enqueueing__whas ; + assign dlyWordsStored_acc_v2__whas = WILL_FIRE_RL_delay_read_req ; + assign dlyReadCredit_acc_v1__whas = WILL_FIRE_RL_delay_read_req ; + assign wsiS_reqFifo_r_deq__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign mesgWF_pwEnqueue__whas = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign mesgWF_wDataIn__whas = mesgWF_pwEnqueue__whas ; + assign mesgWF_pwDequeue__whas = CAN_FIRE_RL_wrtSer_body ; + + // register abortCount + assign abortCount__D_IN = abortCount + 32'b00000000000000000000000000000001 ; + assign abortCount__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register blockDelayWrite + assign blockDelayWrite__D_IN = + WILL_FIRE_RL_delay_write_req && wrtDutyCount == 3'b111 ; + assign blockDelayWrite__EN = + WILL_FIRE_RL_delay_write_req || + WILL_FIRE_RL_delay_write_unblock ; + + // register bytesRead + assign bytesRead__D_IN = bytesRead + 32'b00000000000000000000000000100000 ; + assign bytesRead__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && bytesRead != 32'hFFFFFFFF ; + + // register bytesWritten + assign bytesWritten__D_IN = bytesWritten + 32'b00000000000000000000000000100000 ; + assign bytesWritten__EN = + _dor1bytesWritten__EN_write && bytesWritten != 32'hFFFFFFFF ; + + // register cyclesPassed + assign cyclesPassed__D_IN = cyclesPassed + 32'b000000000000000000000000001000001 ; + assign cyclesPassed__EN = wsiS_statusR[0] && cyclesPassed != 32'hFFFFFFFF ; + + // register dlyCtrl + assign dlyCtrl__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyCtrl__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h0 ; + + // register dlyHoldoffBytes + assign dlyHoldoffBytes__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyHoldoffBytes__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h00004 ; + + // register dlyHoldoffCycles + assign dlyHoldoffCycles__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyHoldoffCycles__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h00008 ; + + // register dlyRAG + assign dlyRAG__D_IN = + WILL_FIRE_RL_delay_read_req ? MUX_dlyRAG__write_1__VAL_1 : 20'b00000000000000000000 ; + assign dlyRAG__EN = + WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register dlyReadCredit_value + assign dlyReadCredit_value__EN = 1'b1 ; + assign dlyReadCredit_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 8'b00000001 : + MUX_dlyReadCredit_value__write_1__VAL_2 ; + + // register dlyWAG + assign dlyWAG__D_IN = + WILL_FIRE_RL_delay_write_req ? + MUX_dlyWAG__write_1__VAL_1 : + 20'b00000000000000000000 ; + assign dlyWAG__EN = + WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register dlyWordsStored_value + assign dlyWordsStored_value__EN = 1'b1 ; + assign dlyWordsStored_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 20'b00000000000000000000 : + MUX_dlyWordsStored_value__write_1__VAL_2 ; + + // register doAbort + assign doAbort__D_IN = 1'b0 ; + assign doAbort__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register endOfMessage + assign endOfMessage__D_IN = MUX_endOfMessage__write_1__SEL_1 ; + assign endOfMessage__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_messageFinalize ; + + // register errCount - jluu: removed because never used +// assign errCount__D_IN = errCount + 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ; +// assign errCount__EN = +// WILL_FIRE_RL_wmwt_messagePushImprecise && +// wsiS_reqFifo__D_OUT[295:40] != valExpect && +// (wsiS_reqFifo__D_OUT[307:296] != 12'b01 || +// wsiS_reqFifo__D_OUT[39:8] != 32'b00000000000000000000000000000000) ; + + // register impreciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: impreciseBurst__D_IN = 1'b0; + default: impreciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign impreciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLength + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or + MUX_mesgLength__write_1__VAL_2 or + MUX_endOfMessage__write_1__SEL_1 or + MUX_mesgLength__write_1__VAL_3 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; + MUX_mesgLength__write_1__SEL_2: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_2; + MUX_endOfMessage__write_1__SEL_1: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_3; + WILL_FIRE_RL_wmwt_messageFinalize: mesgLength__D_IN = 15'b010101010101010; + default: mesgLength__D_IN = 15'b010101010101010 /* unspecified value */ ; + endcase + assign mesgLength__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLengthSoFar + assign mesgLengthSoFar__D_IN = + MUX_impreciseBurst__write_1__SEL_2 ? + 14'b00000000000000 : + MUX_mesgLengthSoFar__write_1__VAL_2 ; + assign mesgLengthSoFar__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // register mesgRF_rCache + assign mesgRF_rCache__EN = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_rCache__D_IN = { 1'b1, mesgRF_rWrPtr, x__h16160 } ; + + // register mesgRF_rRdPtr + assign mesgRF_rRdPtr__D_IN = x__h16052 ; + assign mesgRF_rRdPtr__EN = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // register mesgRF_rWrPtr + assign mesgRF_rWrPtr__D_IN = mesgRF_rWrPtr + 11'b1 ; + assign mesgRF_rWrPtr__EN = CAN_FIRE_RL_rdSer_body ; + + // register mesgRdCount + assign mesgRdCount__D_IN = + MUX_mesgRdCount__write_1__SEL_1 ? + MUX_mesgRdCount__write_1__VAL_1 : + 32'b00000000000000000000000000000000 ; + assign mesgRdCount__EN = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgReqValid + assign mesgReqValid__D_IN = !WILL_FIRE_RL_wmwt_messageFinalize ; + assign mesgReqValid__EN = + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register mesgWF_rCache + assign mesgWF_rCache__D_IN = { 1'b1, mesgWF_rWrPtr, x__h15234 } ; + assign mesgWF_rCache__EN = mesgWF_pwEnqueue__whas ; + + // register mesgWF_rRdPtr + assign mesgWF_rRdPtr__D_IN = x__h15126 ; + assign mesgWF_rRdPtr__EN = CAN_FIRE_RL_wrtSer_body ; + + // register mesgWF_rWrPtr + assign mesgWF_rWrPtr__D_IN = mesgWF_rWrPtr + 11'b1 ; + assign mesgWF_rWrPtr__EN = mesgWF_pwEnqueue__whas ; + + // register mesgWtCount + assign mesgWtCount__D_IN = + WILL_FIRE_RL_wmwt_messageFinalize ? + MUX_mesgWtCount__write_1__VAL_1 : + 32'b00000000000000000000000000000000 ; + assign mesgWtCount__EN = + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register opcode + always@(WILL_FIRE_RL_wmwt_doAbort or + WILL_FIRE_RL_wmwt_mesgBegin or + MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; + WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: opcode__D_IN = 9'b010101010; + default: opcode__D_IN = 9'b010101010 /* unspecified value */ ; + endcase + assign opcode__EN = + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wmwt_doAbort || + WILL_FIRE_RL_wmwt_mesgBegin ; + + // register preciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; + MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: preciseBurst__D_IN = 1'b0; + default: preciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign preciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register rdSerAddr + assign rdSerAddr__D_IN = 32'h0 ; + assign rdSerAddr__EN = 1'b0 ; + + // register rdSerEmpty + assign rdSerEmpty__D_IN = !MUX_rdSerEmpty__write_1__SEL_1 ; + assign rdSerEmpty__EN = + (WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body) && + (rdSerEmpty || rdSerPos == 2'b00) || + WILL_FIRE_RL_rdSer_sync ; + + // register rdSerMeta + assign rdSerMeta__D_IN = metaRF__D_IN ; + assign rdSerMeta__EN = CAN_FIRE_RL_rdSer_begin ; + + // register rdSerPos + assign rdSerPos__D_IN = + MUX_rdSerEmpty__write_1__PSEL_1 ? + MUX_rdSerPos__write_1__VAL_1 : + 2'b00 ; + assign rdSerPos__EN = + WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body || + WILL_FIRE_RL_rdSer_sync ; + + // register rdSerStage + assign rdSerStage__D_IN = wide16Fb__D_OUT[31:0] ; + assign rdSerStage__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_1 + assign rdSerStage_1__D_IN = wide16Fb__D_OUT[63:32] ; + assign rdSerStage_1__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_2 + assign rdSerStage_2__D_IN = wide16Fb__D_OUT[95:64] ; + assign rdSerStage_2__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_3 + assign rdSerStage_3__D_IN = wide16Fb__D_OUT[127:96] ; + assign rdSerStage_3__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerUnroll + assign rdSerUnroll__D_IN = + WILL_FIRE_RL_rdSer_begin ? + v__h22720[20:5] : + MUX_rdSerUnroll__write_1__VAL_2 ; + assign rdSerUnroll__EN = MUX_rdSerEmpty__write_1__PSEL_1 ; + + // register rdSyncWord + always@(WILL_FIRE_RL_rdSer_body or + MUX_rdSyncWord__write_1__VAL_1 or + WILL_FIRE_RL_rdSer_begin or + MUX_rdSyncWord__write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rdSer_body: + rdSyncWord__D_IN = MUX_rdSyncWord__write_1__VAL_1; + WILL_FIRE_RL_rdSer_begin: + rdSyncWord__D_IN = MUX_rdSyncWord__write_1__VAL_2; + WILL_FIRE_RL_rdSer_sync: rdSyncWord__D_IN = 1'b0; + default: rdSyncWord__D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign rdSyncWord__EN = + WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin || + WILL_FIRE_RL_rdSer_sync ; + + // register readMeta + assign readMeta__D_IN = metaRF__D_OUT ; + assign readMeta__EN = CAN_FIRE_RL_wmrd_mesgBegin ; + + // register readyToPush + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + MUX_endOfMessage__write_1__SEL_1) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; + MUX_endOfMessage__write_1__SEL_1: readyToPush__D_IN = 1'b0; + default: readyToPush__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign readyToPush__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToRequest + assign readyToRequest__D_IN = MUX_mesgLength__write_1__SEL_2 ; + assign readyToRequest__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register unrollCnt + assign unrollCnt__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_unrollCnt__write_1__VAL_1 : + MUX_unrollCnt__write_1__VAL_2 ; + assign unrollCnt__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register valExpect : jluu removed because never used +// assign valExpect__D_IN = valExpect + 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ; +// assign valExpect__EN = +// WILL_FIRE_RL_wmwt_messagePushImprecise && +// (wsiS_reqFifo__D_OUT[307:296] != 12'b01 || +// wsiS_reqFifo__D_OUT[39:8] != 32'b00000000000000000000000000000000) ; + + // register wci_cEdge + assign wci_cEdge__D_IN = wci_reqF__D_OUT[36:34] ; + assign wci_cEdge__EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState__D_IN = wci_nState ; + assign wci_cState__EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg__D_IN = wci_ctlAckReg_1__whas ; + assign wci_ctlAckReg__EN = 1'b1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive__D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive__EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge__D_IN = + !MUX_wci_illegalEdge__write_1__SEL_1 && + MUX_wci_illegalEdge__write_1__VAL_2 ; + assign wci_illegalEdge__EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge__write_1__SEL_2 ; + + // register wci_nState + always@(wci_reqF__D_OUT) + begin + case (wci_reqF__D_OUT[36:34]) + 3'b000: wci_nState__D_IN = 3'b001; + 3'b001: wci_nState__D_IN = 3'b010; + 3'b010: wci_nState__D_IN = 3'b011; + default: wci_nState__D_IN = 3'b000; + endcase + end + assign wci_nState__EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState == 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && + (wci_cState == 3'b001 || wci_cState == 3'b011) || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState == 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && + (wci_cState == 3'b011 || wci_cState == 3'b010 || + wci_cState == 3'b001)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg__D_IN = + (wci_wciReq__wget[59:57] != 3'b000) ? + wci_reqF_countReg + 2'b01 : + wci_reqF_countReg - 2'b01 ; + assign wci_reqF_countReg__EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // register wci_respF_c_r + assign wci_respF_c_r__D_IN = + WILL_FIRE_RL_wci_respF_decCtr ? + MUX_wci_respF_c_r__write_1__VAL_1 : + MUX_wci_respF_c_r__write_1__VAL_2 ; + assign wci_respF_c_r__EN = + WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ; + + // register wci_respF_q_0 + assign wci_respF_q_0__EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0__write_1__VAL_1 or + MUX_wci_respF_q_0__write_1__SEL_2 or + MUX_wci_respF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + MUX_wci_respF_q_0__write_1__SEL_2: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0__D_IN = wci_respF_q_1; + default: wci_respF_q_0__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_respF_q_1 + assign wci_respF_q_1__EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1__write_1__VAL_1 or + MUX_wci_respF_q_1__write_1__SEL_2 or + MUX_wci_respF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1__D_IN = MUX_wci_respF_q_1__write_1__VAL_1; + MUX_wci_respF_q_1__write_1__SEL_2: + wci_respF_q_1__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1__D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_sFlagReg + assign wci_sFlagReg__D_IN = 1'b0 ; + assign wci_sFlagReg__EN = 1'b1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d__D_IN = 1'b0 ; + assign wci_sThreadBusy_d__EN = 1'b1 ; + + // register wmemiRdReq + assign wmemiRdReq__D_IN = wmemiRdReq + 32'b00000000000000000000000000000001 ; + assign wmemiRdReq__EN = WILL_FIRE_RL_delay_read_req ; + + // register wmemiRdResp + assign wmemiRdResp__D_IN = wmemiRdResp + 32'b00000000000000000000000000000001 ; + assign wmemiRdResp__EN = CAN_FIRE_RL_delay_read_resp ; + + // register wmemiWrReq + assign wmemiWrReq__D_IN = wmemiWrReq + 32'b00000000000000000000000000000001 ; + assign wmemiWrReq__EN = CAN_FIRE_RL_delay_write_req ; + + // register wmemi_busyWithMessage + assign wmemi_busyWithMessage__D_IN = 1'b0 ; + assign wmemi_busyWithMessage__EN = 1'b0 ; + + // register wmemi_dhF_c_r + assign wmemi_dhF_c_r__D_IN = + WILL_FIRE_RL_wmemi_dhF_decCtr ? + MUX_wmemi_dhF_c_r__write_1__VAL_1 : + MUX_wmemi_dhF_c_r__write_1__VAL_2 ; + assign wmemi_dhF_c_r__EN = + WILL_FIRE_RL_wmemi_dhF_decCtr || WILL_FIRE_RL_wmemi_dhF_incCtr ; + + // register wmemi_dhF_q_0 + always@(WILL_FIRE_RL_wmemi_dhF_both or + MUX_wmemi_dhF_q_0__write_1__VAL_1 or + MUX_wmemi_dhF_q_0__write_1__SEL_2 or + MUX_wmemi_dhF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_dhF_both: + wmemi_dhF_q_0__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_1; + MUX_wmemi_dhF_q_0__write_1__SEL_2: + wmemi_dhF_q_0__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0__D_IN = wmemi_dhF_q_1; + default: wmemi_dhF_q_0__D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_dhF_q_0__EN = + WILL_FIRE_RL_wmemi_dhF_both || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b00 || + WILL_FIRE_RL_wmemi_dhF_decCtr ; + + // register wmemi_dhF_q_1 + always@(WILL_FIRE_RL_wmemi_dhF_both or + MUX_wmemi_dhF_q_1__write_1__VAL_1 or + MUX_wmemi_dhF_q_1__write_1__SEL_2 or + MUX_wmemi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_dhF_both: + wmemi_dhF_q_1__D_IN = MUX_wmemi_dhF_q_1__write_1__VAL_1; + MUX_wmemi_dhF_q_1__write_1__SEL_2: + wmemi_dhF_q_1__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_dhF_decCtr: + wmemi_dhF_q_1__D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + default: wmemi_dhF_q_1__D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_dhF_q_1__EN = + WILL_FIRE_RL_wmemi_dhF_both || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b01 || + WILL_FIRE_RL_wmemi_dhF_decCtr ; + + // register wmemi_errorSticky + assign wmemi_errorSticky__D_IN = 1'b0 ; + assign wmemi_errorSticky__EN = 1'b0 ; + + // register wmemi_operateD + assign wmemi_operateD__D_IN = wci_cState == 3'b010 ; + assign wmemi_operateD__EN = 1'b1 ; + + // register wmemi_peerIsReady + assign wmemi_peerIsReady__D_IN = 1'b1 ; + assign wmemi_peerIsReady__EN = 1'b1 ; + + // register wmemi_reqF_c_r + assign wmemi_reqF_c_r__D_IN = + WILL_FIRE_RL_wmemi_reqF_decCtr ? + MUX_wmemi_reqF_c_r__write_1__VAL_1 : + MUX_wmemi_reqF_c_r__write_1__VAL_2 ; + assign wmemi_reqF_c_r__EN = + WILL_FIRE_RL_wmemi_reqF_decCtr || + WILL_FIRE_RL_wmemi_reqF_incCtr ; + + // register wmemi_reqF_q_0 + always@(WILL_FIRE_RL_wmemi_reqF_both or + MUX_wmemi_reqF_q_0__write_1__VAL_1 or + MUX_wmemi_reqF_q_0__write_1__SEL_2 or + MUX_wmemi_reqF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_reqF_both: + wmemi_reqF_q_0__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_1; + MUX_wmemi_reqF_q_0__write_1__SEL_2: + wmemi_reqF_q_0__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_0__D_IN = wmemi_reqF_q_1; + default: wmemi_reqF_q_0__D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_reqF_q_0__EN = + WILL_FIRE_RL_wmemi_reqF_both || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b00 || + WILL_FIRE_RL_wmemi_reqF_decCtr ; + + // register wmemi_reqF_q_1 + always@(WILL_FIRE_RL_wmemi_reqF_both or + MUX_wmemi_reqF_q_1__write_1__VAL_1 or + MUX_wmemi_reqF_q_1__write_1__SEL_2 or + MUX_wmemi_reqF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_reqF_both: + wmemi_reqF_q_1__D_IN = MUX_wmemi_reqF_q_1__write_1__VAL_1; + MUX_wmemi_reqF_q_1__write_1__SEL_2: + wmemi_reqF_q_1__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1__D_IN = 52'h0AAAAAAAAAAAA; + default: wmemi_reqF_q_1__D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_reqF_q_1__EN = + WILL_FIRE_RL_wmemi_reqF_both || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b01 || + WILL_FIRE_RL_wmemi_reqF_decCtr ; + + // register wmemi_statusR + assign wmemi_statusR__D_IN = + { wmemi_isReset__VAL, + !wmemi_peerIsReady, + !wmemi_operateD, + wmemi_errorSticky, + 3'b000, + wmemi_trafficSticky } ; + assign wmemi_statusR__EN = 1'b1 ; + + // register wmemi_trafficSticky + assign wmemi_trafficSticky__D_IN = 1'b1 ; + assign wmemi_trafficSticky__EN = wmemiM_SCmdAccept ; + + // register wrtDutyCount + assign wrtDutyCount__D_IN = wrtDutyCount + 3'b001 ; + assign wrtDutyCount__EN = CAN_FIRE_RL_delay_write_req ; + + // register wrtSerAddr + assign wrtSerAddr__D_IN = 32'h0 ; + assign wrtSerAddr__EN = 1'b0 ; + + // register wrtSerMeta + assign wrtSerMeta__D_IN = metaWF__D_OUT ; + assign wrtSerMeta__EN = CAN_FIRE_RL_wrtSer_begin ; + + // register wrtSerPos + assign wrtSerPos__D_IN = + WILL_FIRE_RL_wrtSer_body ? + MUX_wrtSerPos__write_1__VAL_1 : + MUX_wrtSerPos__write_1__VAL_2 ; + assign wrtSerPos__EN = + WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ; + + // register wrtSerStage + assign wrtSerStage__D_IN = + MUX_wrtSerStage__write_1__SEL_1 ? x__h19905[31:0] : metaWF__D_OUT ; + assign wrtSerStage__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b00 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b00 ; + + // register wrtSerStage_1 + assign wrtSerStage_1__D_IN = + MUX_wrtSerStage_1__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_1__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b01 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b01 ; + + // register wrtSerStage_2 + assign wrtSerStage_2__D_IN = + MUX_wrtSerStage_2__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_2__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b10 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b10 ; + + // register wrtSerStage_3 + assign wrtSerStage_3__D_IN = + MUX_wrtSerStage_3__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_3__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b11 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b11 ; + + // register wrtSerUnroll + assign wrtSerUnroll__D_IN = + WILL_FIRE_RL_wrtSer_body ? + MUX_wrtSerUnroll__write_1__VAL_1 : + metaWF__D_OUT[20:5] ; + assign wrtSerUnroll__EN = + WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ; + + // register wsiM_burstKind + assign wsiM_burstKind__D_IN = + (wsiM_burstKind == 2'b00) ? + (wsiM_reqFifo_q_0[308] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiM_burstKind__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + (wsiM_burstKind == 2'b00 || + wsiM_burstKind == 2'b01 && wsiM_reqFifo_q_0[309] || + wsiM_burstKind == 2'b10 && wsiM_reqFifo_q_0[307:296] == 12'b01) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky__D_IN = 1'b0 ; + assign wsiM_errorSticky__EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount__D_IN = wsiM_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_iMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + wsiM_burstKind == 2'b10 && + wsiM_reqFifo_q_0[307:296] == 12'b01 ; + + // register wsiM_operateD + assign wsiM_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiM_operateD__EN = 1'b1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount__D_IN = wsiM_pMesgCount + 32'b00000000000000000000000000000001; + assign wsiM_pMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + wsiM_burstKind == 2'b01 && + wsiM_reqFifo_q_0[309] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady__D_IN = wsiM1_SReset_n ; + assign wsiM_peerIsReady__EN = 1'b1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r__D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_c_r__write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r__write_1__VAL_2 ; + assign wsiM_reqFifo_c_r__EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; + + // register wsiM_reqFifo_q_0 + assign wsiM_reqFifo_q_0__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_1; + MUX_wsiM_reqFifo_q_0__write_1__SEL_2: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0__D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0__D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_reqFifo_q_1 + assign wsiM_reqFifo_q_1__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_1__write_1__VAL_1; + MUX_wsiM_reqFifo_q_1__write_1__SEL_2: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1__D_IN = + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsiM_reqFifo_q_1__D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d__D_IN = wsiM1_SThreadBusy ; + assign wsiM_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_statusR + assign wsiM_statusR__D_IN = + { wsiM_isReset__VAL, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'b00, + wsiM_sThreadBusy_d, + 1'b0, + wsiM_trafficSticky } ; + assign wsiM_statusR__EN = 1'b1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount__D_IN = wsiM_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiM_tBusyCount__EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky__D_IN = 1'b1 ; + assign wsiM_trafficSticky__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 ; + + // register wsiS_burstKind + assign wsiS_burstKind__D_IN = + (wsiS_burstKind == 2'b00) ? + (wsiS_wsiReq__wget[308] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiS_burstKind__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'b00 || + wsiS_burstKind == 2'b01 && wsiS_wsiReq__wget[309] || + wsiS_burstKind == 2'b10 && wsiS_wsiReq__wget[307:296] == 12'b01) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky__D_IN = 1'b1 ; + assign wsiS_errorSticky__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo__FULL_N ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount__D_IN = wsiS_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_iMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b10 && + wsiS_wsiReq__wget[307:296] == 12'b01 ; + + // register wsiS_operateD + assign wsiS_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiS_operateD__EN = 1'b1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount__D_IN = wsiS_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_pMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b01 && + wsiS_wsiReq__wget[309] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady__D_IN = wsiS1_MReset_n ; + assign wsiS_peerIsReady__EN = 1'b1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg__D_IN = + CAN_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'b01 : + wsiS_reqFifo_countReg - 2'b01 ; + assign wsiS_reqFifo_countReg__EN = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // register wsiS_statusR + assign wsiS_statusR__EN = 1'b1 ; + assign wsiS_statusR__D_IN = + { wsiS_isReset__VAL, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'b00, + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady, + 1'b0, + wsiS_trafficSticky } ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount__D_IN = wsiS_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiS_tBusyCount__EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky__D_IN = 1'b1 ; + assign wsiS_trafficSticky__EN = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiWordsRemain + assign wsiWordsRemain__D_IN = + MUX_mesgLength__write_1__SEL_2 ? + wsiS_reqFifo__D_OUT[307:296] : + MUX_wsiWordsRemain__write_1__VAL_2 ; + assign wsiWordsRemain__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messagePushPrecise ; + + // register zeroLengthMesg + assign zeroLengthMesg__D_IN = wsiS_reqFifo__D_OUT[39:8] == 32'b00000000000000000000000000000000 ; + assign zeroLengthMesg__EN = MUX_mesgLength__write_1__SEL_2 ; + + // submodule mesgRF_memory + assign mesgRF_memory__WEA = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_memory__ADDRA = mesgRF_rWrPtr[9:0] ; + assign mesgRF_memory__WEB = 1'b0 ; + assign mesgRF_memory__ADDRB = + CAN_FIRE_RL_wmrd_mesgBodyResponse ? + x__h16052[9:0] : + mesgRF_rRdPtr[9:0] ; + assign mesgRF_memory__DIB = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign mesgRF_memory__ENA = 1'b1 ; + assign mesgRF_memory__ENB = 1'b1 ; + assign mesgRF_memory__DIA = x__h16160 ; + + // submodule mesgWF_memory + assign mesgWF_memory__ADDRA = mesgWF_rWrPtr[9:0] ; + assign mesgWF_memory__WEB = 1'b0 ; + assign mesgWF_memory__DIB = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign mesgWF_memory__ENA = 1'b1 ; + assign mesgWF_memory__ENB = 1'b1 ; + assign mesgWF_memory__WEA = mesgWF_pwEnqueue__whas ; + assign mesgWF_memory__DIA = x__h15234 ; + assign mesgWF_memory__ADDRB = + CAN_FIRE_RL_wrtSer_body ? x__h15126[9:0] : mesgWF_rRdPtr[9:0] ; + + // submodule metaRF + always@(rdSerPos or + rdSerStage_3 or wide16Fb__D_OUT or rdSerStage_1 or rdSerStage_2) + begin + case (rdSerPos) + 2'b00: metaRF__D_IN = wide16Fb__D_OUT[31:0]; + 2'b01: metaRF__D_IN = rdSerStage_1; + 2'b10: metaRF__D_IN = rdSerStage_2; + 2'b11: metaRF__D_IN = rdSerStage_3; + endcase + end + assign metaRF__DEQ = CAN_FIRE_RL_wmrd_mesgBegin ; + assign metaRF__CLR = 1'b0 ; + assign metaRF__ENQ = CAN_FIRE_RL_rdSer_begin ; + + // submodule metaWF + assign metaWF__CLR = 1'b0 ; + assign metaWF__D_IN = + MUX_metaWF__enq_1__SEL_1 ? + MUX_metaWF__enq_1__VAL_1 : + MUX_metaWF__enq_1__VAL_1 ; + assign metaWF__ENQ = + WILL_FIRE_RL_wmwt_messageFinalize && impreciseBurst || + WILL_FIRE_RL_wmwt_requestPrecise ; + assign metaWF__DEQ = CAN_FIRE_RL_wrtSer_begin ; + + // submodule wci_reqF + assign wci_reqF__D_IN = wci_wciReq__wget ; + assign wci_reqF__DEQ = wci_reqF_r_deq__whas ; + assign wci_reqF__ENQ = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF__CLR = 1'b0 ; + + // submodule wide16Fa + assign wide16Fa__DEQ = CAN_FIRE_RL_delay_write_req ; + assign wide16Fa__CLR = 1'b0 ; + assign wide16Fa__D_IN = + MUX_wide16Fa__enq_1__SEL_1 ? + MUX_wide16Fa__enq_1__VAL_1 : + MUX_wide16Fa__enq_1__VAL_2 ; + assign wide16Fa__ENQ = + WILL_FIRE_RL_wrtSer_begin && + (wrtSerPos == 2'b11 || metaWF__D_OUT[23:0] == 24'b000000000000000000000000) || + WILL_FIRE_RL_wrtSer_body && + (wrtSerPos == 2'b11 || wrtSerUnroll == 16'b0000000000000001) ; + + // submodule wide16Fb + assign wide16Fb__D_IN = wmemi_respF__D_OUT[127:0] ; + assign wide16Fb__ENQ = CAN_FIRE_RL_delay_read_resp ; + assign wide16Fb__CLR = 1'b0 ; + assign wide16Fb__DEQ = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // submodule wmemi_respF + assign wmemi_respF__D_IN = wmemi_wmemiResponse__wget ; + assign wmemi_respF__DEQ = CAN_FIRE_RL_delay_read_resp ; + assign wmemi_respF__ENQ = CAN_FIRE_RL_wmemi_respAdvance ; + assign wmemi_respF__CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo__D_IN = wsiS_wsiReq__wget ; + assign wsiS_reqFifo__ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo__CLR = 1'b0 ; + assign wsiS_reqFifo__DEQ = wsiS_reqFifo_r_deq__whas ; + + // remaining internal signals + assign IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354 = + { (wrtSerPos == 2'b10) ? 32'h0 : x__h19905[31:0], + (wrtSerPos == 2'b10) ? x__h19905[31:0] : wrtSerStage_2, + wrtSerStage_1, + wrtSerStage } ; + assign IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377 = + { (wrtSerPos == 2'b10) ? 32'h0 : metaWF__D_OUT, + (wrtSerPos == 2'b10) ? metaWF__D_OUT : wrtSerStage_2, + wrtSerStage_1, + wrtSerStage } ; + assign NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272 = + (dlyWordsStored_value ^ 20'h80000) > 20'b10000000000000000000 && + dlyHoldoffBytes >= bytesWritten && + dlyHoldoffCycles >= cyclesPassed ; + assign NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208 = + mesgRF_rRdPtr + 11'b01000000000 != mesgRF_rWrPtr && + (!rdSerEmpty && rdSerPos != 2'b00 || wide16Fb__EMPTY_N) ; + assign NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 = + wsiS_reqFifo_countReg > 2'b01 ; + assign _dor1bytesWritten__EN_write = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign addr__h20994 = { 12'b00, x__h21052 } ; + assign addr__h21166 = { 12'b00, x__h21211 } ; + assign mesg__h22346 = mesgRF_wDataOut__wget ; + assign metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242 = + metaRF__FULL_N && + (!rdSerEmpty && rdSerPos != 2'b00 || wide16Fb__EMPTY_N) ; + assign metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365 = + metaWF__EMPTY_N && + (wrtSerPos != 2'b11 && metaWF__D_OUT[23:0] != 24'b000000000000000000000000 || + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904) ; + assign mlp1__h17953 = MUX_mesgLengthSoFar__write_1__VAL_2 ; + assign rdat__h21847 = { 8'b00000000, x__h21850 } ; + assign rdat__h22030 = { 12'b00, dlyWordsStored_value } ; + assign rdat__h22038 = { 24'b000000000000000000000000, dlyReadCredit_value } ; + assign rdat__h22046 = { 12'b00, dlyWAG } ; + assign rdat__h22054 = { 12'b00, dlyRAG } ; + assign v__h22720 = metaRF__D_IN ; + assign wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397 = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && mesgLength[14] && + !doAbort && + (preciseBurst && wsiWordsRemain == 12'b00 || + impreciseBurst && endOfMessage) ; + assign wrtSerPos_11_PLUS_1___d1014 = wrtSerPos + 2'b01 ; + assign x1__h19969 = { 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, x__h19905[31:0] } ; + assign x1__h19978 = { 64'b0000000000000000000000000000000000000000000000000000000000000000, x__h19905[31:0], wrtSerStage } ; + assign x1__h20492 = { 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, metaWF__D_OUT } ; + assign x1__h20501 = { 64'b0000000000000000000000000000000000000000000000000000000000000000, metaWF__D_OUT, wrtSerStage } ; + assign x1_length__h17254 = { 10'b0000000000, x__h17298 } ; + assign x1_opcode__h17253 = opcode[8] ? opcode[7:0] : 8'b00000000 ; + assign x__h15126 = mesgWF_rRdPtr + 11'b1 ; + assign x__h15234 = + mesgWF_pwEnqueue__whas ? wsiS_reqFifo__D_OUT[295:40] : 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; + assign x__h16052 = mesgRF_rRdPtr + 11'b1 ; + assign x__h16160 = CAN_FIRE_RL_rdSer_body ? mesgRF_wDataIn__wget : 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; + assign x__h17298 = mesgLength[14] ? mesgLength[13:0] : 14'b00000000000000 ; + assign x__h19905 = mesgWF_wDataOut__wget ; + assign x__h21052 = { dlyRAG, 4'h0 } ; + assign x__h21211 = { dlyWAG, 4'h0 } ; + assign x__h21850 = { wmemi_statusR, wsiS_statusR, wsiM_statusR } ; + assign x_burstLength__h22437 = + (readMeta[23:0] == 24'b000000000000000000000000) ? 12'b01 : readMeta[16:5] ; + assign x_byteEn__h22438 = (readMeta[23:0] == 24'b000000000000000000000000) ? 32'b00000000000000000000000000000000 : 32'hFFFFFFFF ; + always@(wci_reqF__D_OUT or + dlyCtrl or + dlyHoldoffBytes or + dlyHoldoffCycles or + mesgWtCount or + mesgRdCount or + bytesWritten or + rdat__h21847 or + wsiS_extStatusW__wget or + wsiM_extStatusW__wget or + wmemiWrReq or + wmemiRdReq or + wmemiRdResp or + rdat__h22030 or rdat__h22038 or rdat__h22046 or rdat__h22054) + begin + case (wci_reqF__D_OUT[51:32]) + 20'h0: x_data__h21804 = dlyCtrl; + 20'h00004: x_data__h21804 = dlyHoldoffBytes; + 20'h00008: x_data__h21804 = dlyHoldoffCycles; + 20'h0000C: x_data__h21804 = mesgWtCount; + 20'h00010: x_data__h21804 = mesgRdCount; + 20'h00014: x_data__h21804 = bytesWritten; + 20'h00018: x_data__h21804 = rdat__h21847; + 20'h0001C: x_data__h21804 = 32'b00000000000000000000000000000000; + 20'h00020: x_data__h21804 = wsiS_extStatusW__wget[95:64]; + 20'h00024: x_data__h21804 = wsiS_extStatusW__wget[63:32]; + 20'h00028: x_data__h21804 = wsiS_extStatusW__wget[31:0]; + 20'h0002C: x_data__h21804 = wsiM_extStatusW__wget[95:64]; + 20'h00030: x_data__h21804 = wsiM_extStatusW__wget[63:32]; + 20'h00034: x_data__h21804 = wsiM_extStatusW__wget[31:0]; + 20'h00038: x_data__h21804 = wmemiWrReq; + 20'h0003C: x_data__h21804 = wmemiRdReq; + 20'h00040: x_data__h21804 = wmemiRdResp; + 20'h00044: x_data__h21804 = rdat__h22030; + 20'h00048: x_data__h21804 = rdat__h22038; + 20'h0004C: x_data__h21804 = rdat__h22046; + 20'h00050: x_data__h21804 = rdat__h22054; + default: x_data__h21804 = 32'b00000000000000000000000000000000; + endcase + end + always@(wrtSerPos or wide16Fa__FULL_N) + begin + case (wrtSerPos) + // 2'b00, 2'b01, 2'b10 + 2'b10: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b00: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b01: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b11: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wrtSerPos != 2'b11 || wide16Fa__FULL_N; + endcase + end + always@(wrtSerPos) + begin + case (wrtSerPos) + // 2'b00, 2'b01, 2'b10, 2'b11: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b00: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b01: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b10: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b11: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (!wciS0_MReset_n) + begin + abortCount <= 32'b00000000000000000000000000000000; + blockDelayWrite <= 1'b0; + bytesRead <= 32'b00; + bytesWritten <= 32'b00000000000000000000000000000000; + cyclesPassed <= 32'b00000000000000000000000000000000; + dlyCtrl <= dlyCtrlInit; + dlyHoldoffBytes <= 32'b00000000000000000000000000000000; + dlyHoldoffCycles <= 32'b00000000000000000000000000000000; + dlyRAG <= 20'b00000000000000000000; + dlyReadCredit_value <= 8'b00000000; + dlyWAG <= 20'b00000000000000000000; + dlyWordsStored_value <= 20'b00000000000000000000; + doAbort <= 1'b0; + endOfMessage <= 1'b0; +// errCount <= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + impreciseBurst <= 1'b0; + mesgLength <= 15'b010101010101010; + mesgLengthSoFar <= 14'b00000000000000; + mesgRF_rCache <= + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mesgRF_rRdPtr <= 11'b0; + mesgRF_rWrPtr <= 11'b0; + mesgRdCount <= 32'b00000000000000000000000000000000; + mesgReqValid <= 1'b0; + mesgWF_rCache <= + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mesgWF_rRdPtr <= 11'b0; + mesgWF_rWrPtr <= 11'b0; + mesgWtCount <= 32'b00000000000000000000000000000000; + opcode <= 9'b010101010; + preciseBurst <= 1'b0; + rdSerAddr <= 32'b00000000000000000000000000000000; + rdSerEmpty <= 1'b1; + rdSerPos <= 2'b00; + rdSerUnroll <= 16'b0000000000000000; + rdSyncWord <= 1'b0; + readyToPush <= 1'b0; + readyToRequest <= 1'b0; + unrollCnt <= 16'b0000000000000000; +// valExpect <= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + wci_cEdge <= 3'b111; + wci_cState <= 3'b000; + wci_ctlAckReg <= 1'b0; + wci_ctlOpActive <= 1'b0; + wci_illegalEdge <= 1'b0; + wci_nState <= 3'b000; + wci_reqF_countReg <= 2'b00; + wci_respF_c_r <= 2'b00; + wci_respF_q_0 <= 34'h0AAAAAAAA; + wci_respF_q_1 <= 34'h0AAAAAAAA; + wci_sFlagReg <= 1'b0; + wci_sThreadBusy_d <= 1'b1; + wmemiRdReq <= 32'b00000000000000000000000000000000; + wmemiRdResp <= 32'b00000000000000000000000000000000; + wmemiWrReq <= 32'b00000000000000000000000000000000; + wmemi_busyWithMessage <= 1'b0; + wmemi_dhF_c_r <= 2'b00; + wmemi_dhF_q_0 <= + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_dhF_q_1 <= + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_errorSticky <= 1'b0; + wmemi_operateD <= 1'b0; + wmemi_peerIsReady <= 1'b1; + wmemi_reqF_c_r <= 2'b00; + wmemi_reqF_q_0 <= 52'h0AAAAAAAAAAAA; + wmemi_reqF_q_1 <= 52'h0AAAAAAAAAAAA; + wmemi_trafficSticky <= 1'b0; + wrtDutyCount <= 3'b000; + wrtSerAddr <= 32'b00000000000000000000000000000000; + wrtSerPos <= 2'b00; + wrtSerUnroll <= 16'b0000000000000000; + wsiM_burstKind <= 2'b00; + wsiM_errorSticky <= 1'b0; + wsiM_iMesgCount <= 32'b00000000000000000000000000000000; + wsiM_operateD <= 1'b0; + wsiM_pMesgCount <= 32'b00000000000000000000000000000000; + wsiM_peerIsReady <= 1'b0; + wsiM_reqFifo_c_r <= 2'b00; + wsiM_reqFifo_q_0 <= + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_reqFifo_q_1 <= + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_sThreadBusy_d <= 1'b1; + wsiM_tBusyCount <= 32'b00000000000000000000000000000000; + wsiM_trafficSticky <= 1'b0; + wsiS_burstKind <= 2'b00; + wsiS_errorSticky <= 1'b0; + wsiS_iMesgCount <= 32'b00000000000000000000000000000000; + wsiS_operateD <= 1'b0; + wsiS_pMesgCount <= 32'b00000000000000000000000000000000; + wsiS_peerIsReady <= 1'b0; + wsiS_reqFifo_countReg <= 2'b00; + wsiS_tBusyCount <= 32'b00000000000000000000000000000000; + wsiS_trafficSticky <= 1'b0; + wsiWordsRemain <= 12'b00; + zeroLengthMesg <= 1'b0; + end + else + begin + if (abortCount__EN) + abortCount <= abortCount__D_IN; + if (blockDelayWrite__EN) + blockDelayWrite <= blockDelayWrite__D_IN; + if (bytesRead__EN) bytesRead <= bytesRead__D_IN; + if (bytesWritten__EN) + bytesWritten <= bytesWritten__D_IN; + if (cyclesPassed__EN) + cyclesPassed <= cyclesPassed__D_IN; + if (dlyCtrl__EN) dlyCtrl <= dlyCtrl__D_IN; + if (dlyHoldoffBytes__EN) + dlyHoldoffBytes <= dlyHoldoffBytes__D_IN; + if (dlyHoldoffCycles__EN) + dlyHoldoffCycles <= dlyHoldoffCycles__D_IN; + if (dlyRAG__EN) dlyRAG <= dlyRAG__D_IN; + if (dlyReadCredit_value__EN) + dlyReadCredit_value <= + dlyReadCredit_value__D_IN; + if (dlyWAG__EN) dlyWAG <= dlyWAG__D_IN; + if (dlyWordsStored_value__EN) + dlyWordsStored_value <= + dlyWordsStored_value__D_IN; + if (doAbort__EN) doAbort <= doAbort__D_IN; + if (endOfMessage__EN) + endOfMessage <= endOfMessage__D_IN; +// if (errCount__EN) errCount <= errCount__D_IN; + if (impreciseBurst__EN) + impreciseBurst <= impreciseBurst__D_IN; + if (mesgLength__EN) + mesgLength <= mesgLength__D_IN; + if (mesgLengthSoFar__EN) + mesgLengthSoFar <= mesgLengthSoFar__D_IN; + if (mesgRF_rCache__EN) + mesgRF_rCache <= mesgRF_rCache__D_IN; + if (mesgRF_rRdPtr__EN) + mesgRF_rRdPtr <= mesgRF_rRdPtr__D_IN; + if (mesgRF_rWrPtr__EN) + mesgRF_rWrPtr <= mesgRF_rWrPtr__D_IN; + if (mesgRdCount__EN) + mesgRdCount <= mesgRdCount__D_IN; + if (mesgReqValid__EN) + mesgReqValid <= mesgReqValid__D_IN; + if (mesgWF_rCache__EN) + mesgWF_rCache <= mesgWF_rCache__D_IN; + if (mesgWF_rRdPtr__EN) + mesgWF_rRdPtr <= mesgWF_rRdPtr__D_IN; + if (mesgWF_rWrPtr__EN) + mesgWF_rWrPtr <= mesgWF_rWrPtr__D_IN; + if (mesgWtCount__EN) + mesgWtCount <= mesgWtCount__D_IN; + if (opcode__EN) opcode <= opcode__D_IN; + if (preciseBurst__EN) + preciseBurst <= preciseBurst__D_IN; + if (rdSerAddr__EN) rdSerAddr <= rdSerAddr__D_IN; + if (rdSerEmpty__EN) + rdSerEmpty <= rdSerEmpty__D_IN; + if (rdSerPos__EN) rdSerPos <= rdSerPos__D_IN; + if (rdSerUnroll__EN) + rdSerUnroll <= rdSerUnroll__D_IN; + if (rdSyncWord__EN) + rdSyncWord <= rdSyncWord__D_IN; + if (readyToPush__EN) + readyToPush <= readyToPush__D_IN; + if (readyToRequest__EN) + readyToRequest <= readyToRequest__D_IN; + if (unrollCnt__EN) unrollCnt <= unrollCnt__D_IN; +// if (valExpect__EN) valExpect <= valExpect__D_IN; + if (wci_cEdge__EN) wci_cEdge <= wci_cEdge__D_IN; + if (wci_cState__EN) + wci_cState <= wci_cState__D_IN; + if (wci_ctlAckReg__EN) + wci_ctlAckReg <= wci_ctlAckReg__D_IN; + if (wci_ctlOpActive__EN) + wci_ctlOpActive <= wci_ctlOpActive__D_IN; + if (wci_illegalEdge__EN) + wci_illegalEdge <= wci_illegalEdge__D_IN; + if (wci_nState__EN) + wci_nState <= wci_nState__D_IN; + if (wci_reqF_countReg__EN) + wci_reqF_countReg <= wci_reqF_countReg__D_IN; + if (wci_respF_c_r__EN) + wci_respF_c_r <= wci_respF_c_r__D_IN; + if (wci_respF_q_0__EN) + wci_respF_q_0 <= wci_respF_q_0__D_IN; + if (wci_respF_q_1__EN) + wci_respF_q_1 <= wci_respF_q_1__D_IN; + if (wci_sFlagReg__EN) + wci_sFlagReg <= wci_sFlagReg__D_IN; + if (wci_sThreadBusy_d__EN) + wci_sThreadBusy_d <= wci_sThreadBusy_d__D_IN; + if (wmemiRdReq__EN) + wmemiRdReq <= wmemiRdReq__D_IN; + if (wmemiRdResp__EN) + wmemiRdResp <= wmemiRdResp__D_IN; + if (wmemiWrReq__EN) + wmemiWrReq <= wmemiWrReq__D_IN; + if (wmemi_busyWithMessage__EN) + wmemi_busyWithMessage <= + wmemi_busyWithMessage__D_IN; + if (wmemi_dhF_c_r__EN) + wmemi_dhF_c_r <= wmemi_dhF_c_r__D_IN; + if (wmemi_dhF_q_0__EN) + wmemi_dhF_q_0 <= wmemi_dhF_q_0__D_IN; + if (wmemi_dhF_q_1__EN) + wmemi_dhF_q_1 <= wmemi_dhF_q_1__D_IN; + if (wmemi_errorSticky__EN) + wmemi_errorSticky <= wmemi_errorSticky__D_IN; + if (wmemi_operateD__EN) + wmemi_operateD <= wmemi_operateD__D_IN; + if (wmemi_peerIsReady__EN) + wmemi_peerIsReady <= wmemi_peerIsReady__D_IN; + if (wmemi_reqF_c_r__EN) + wmemi_reqF_c_r <= wmemi_reqF_c_r__D_IN; + if (wmemi_reqF_q_0__EN) + wmemi_reqF_q_0 <= wmemi_reqF_q_0__D_IN; + if (wmemi_reqF_q_1__EN) + wmemi_reqF_q_1 <= wmemi_reqF_q_1__D_IN; + if (wmemi_trafficSticky__EN) + wmemi_trafficSticky <= + wmemi_trafficSticky__D_IN; + if (wrtDutyCount__EN) + wrtDutyCount <= wrtDutyCount__D_IN; + if (wrtSerAddr__EN) + wrtSerAddr <= wrtSerAddr__D_IN; + if (wrtSerPos__EN) wrtSerPos <= wrtSerPos__D_IN; + if (wrtSerUnroll__EN) + wrtSerUnroll <= wrtSerUnroll__D_IN; + if (wsiM_burstKind__EN) + wsiM_burstKind <= wsiM_burstKind__D_IN; + if (wsiM_errorSticky__EN) + wsiM_errorSticky <= wsiM_errorSticky__D_IN; + if (wsiM_iMesgCount__EN) + wsiM_iMesgCount <= wsiM_iMesgCount__D_IN; + if (wsiM_operateD__EN) + wsiM_operateD <= wsiM_operateD__D_IN; + if (wsiM_pMesgCount__EN) + wsiM_pMesgCount <= wsiM_pMesgCount__D_IN; + if (wsiM_peerIsReady__EN) + wsiM_peerIsReady <= wsiM_peerIsReady__D_IN; + if (wsiM_reqFifo_c_r__EN) + wsiM_reqFifo_c_r <= wsiM_reqFifo_c_r__D_IN; + if (wsiM_reqFifo_q_0__EN) + wsiM_reqFifo_q_0 <= wsiM_reqFifo_q_0__D_IN; + if (wsiM_reqFifo_q_1__EN) + wsiM_reqFifo_q_1 <= wsiM_reqFifo_q_1__D_IN; + if (wsiM_sThreadBusy_d__EN) + wsiM_sThreadBusy_d <= wsiM_sThreadBusy_d__D_IN; + if (wsiM_tBusyCount__EN) + wsiM_tBusyCount <= wsiM_tBusyCount__D_IN; + if (wsiM_trafficSticky__EN) + wsiM_trafficSticky <= wsiM_trafficSticky__D_IN; + if (wsiS_burstKind__EN) + wsiS_burstKind <= wsiS_burstKind__D_IN; + if (wsiS_errorSticky__EN) + wsiS_errorSticky <= wsiS_errorSticky__D_IN; + if (wsiS_iMesgCount__EN) + wsiS_iMesgCount <= wsiS_iMesgCount__D_IN; + if (wsiS_operateD__EN) + wsiS_operateD <= wsiS_operateD__D_IN; + if (wsiS_pMesgCount__EN) + wsiS_pMesgCount <= wsiS_pMesgCount__D_IN; + if (wsiS_peerIsReady__EN) + wsiS_peerIsReady <= wsiS_peerIsReady__D_IN; + if (wsiS_reqFifo_countReg__EN) + wsiS_reqFifo_countReg <= + wsiS_reqFifo_countReg__D_IN; + if (wsiS_tBusyCount__EN) + wsiS_tBusyCount <= wsiS_tBusyCount__D_IN; + if (wsiS_trafficSticky__EN) + wsiS_trafficSticky <= wsiS_trafficSticky__D_IN; + if (wsiWordsRemain__EN) + wsiWordsRemain <= wsiWordsRemain__D_IN; + if (zeroLengthMesg__EN) + zeroLengthMesg <= zeroLengthMesg__D_IN; + end + if (rdSerMeta__EN) rdSerMeta <= rdSerMeta__D_IN; + if (rdSerStage__EN) rdSerStage <= rdSerStage__D_IN; + if (rdSerStage_1__EN) + rdSerStage_1 <= rdSerStage_1__D_IN; + if (rdSerStage_2__EN) + rdSerStage_2 <= rdSerStage_2__D_IN; + if (rdSerStage_3__EN) + rdSerStage_3 <= rdSerStage_3__D_IN; + if (readMeta__EN) readMeta <= readMeta__D_IN; + if (wmemi_statusR__EN) + wmemi_statusR <= wmemi_statusR__D_IN; + if (wrtSerMeta__EN) wrtSerMeta <= wrtSerMeta__D_IN; + if (wrtSerStage__EN) wrtSerStage <= wrtSerStage__D_IN; + if (wrtSerStage_1__EN) + wrtSerStage_1 <= wrtSerStage_1__D_IN; + if (wrtSerStage_2__EN) + wrtSerStage_2 <= wrtSerStage_2__D_IN; + if (wrtSerStage_3__EN) + wrtSerStage_3 <= wrtSerStage_3__D_IN; + if (wsiM_statusR__EN) + wsiM_statusR <= wsiM_statusR__D_IN; + if (wsiS_statusR__EN) + wsiS_statusR <= wsiS_statusR__D_IN; + end + + // handling of system tasks + + +endmodule // mkDelayWorker32B + + + + +module ResetToBool (RST, VAL); + +input RST; +output VAL; +reg VAL; + +always @ (RST or VAL) +begin + +if (RST == 1) +VAL=1'b0; + +end +endmodule + + +module arSRLFIFO_a (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + +module arSRLFIFO_b (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module arSRLFIFO_c (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [127:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [127:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + + +module arSRLFIFO_d (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [127:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [127:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_d fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module SizedFIFO_a (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [59:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [59:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_f fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + +module SizedFIFO_b (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [312:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [312:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_g fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module SizedFIFO_x (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [130:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [130:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_x fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + +//--------------------------------------- +// A dual-port RAM 1024x256 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_1024x256 ( + input clk, + input we1, + input we2, + input [10 - 1 : 0] addr1, + input [256 - 1 : 0] data1, + output [256 - 1 : 0] out1, + input [10 - 1 : 0] addr2, + input [256 - 1 : 0] data2, + output [256 - 1 : 0] out2 +); + reg [256 - 1 : 0] ram[2**10 - 1 : 0]; + reg [256 - 1 : 0] data_out1; + reg [256 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 16x32 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_16x32 ( + input clk, + input we1, + input we2, + input [4 - 1 : 0] addr1, + input [32 - 1 : 0] data1, + output [32 - 1 : 0] out1, + input [4 - 1 : 0] addr2, + input [32 - 1 : 0] data2, + output [32 - 1 : 0] out2 +); + reg [32 - 1 : 0] ram[2**4 - 1 : 0]; + reg [32 - 1 : 0] data_out1; + reg [32 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 16x128 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_16x128 ( + input clk, + input we1, + input we2, + input [4 - 1 : 0] addr1, + input [128 - 1 : 0] data1, + output [128 - 1 : 0] out1, + input [4 - 1 : 0] addr2, + input [128 - 1 : 0] data2, + output [128 - 1 : 0] out2 +); + reg [128 - 1 : 0] ram[2**4 - 1 : 0]; + reg [128 - 1 : 0] data_out1; + reg [128 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 8x60 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_8x60 ( + input clk, + input we1, + input we2, + input [3 - 1 : 0] addr1, + input [60 - 1 : 0] data1, + output [60 - 1 : 0] out1, + input [3 - 1 : 0] addr2, + input [60 - 1 : 0] data2, + output [60 - 1 : 0] out2 +); + reg [60 - 1 : 0] ram[2**3 - 1 : 0]; + reg [60 - 1 : 0] data_out1; + reg [60 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 8x313 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_8x313 ( + input clk, + input we1, + input we2, + input [3 - 1 : 0] addr1, + input [313 - 1 : 0] data1, + output [313 - 1 : 0] out1, + input [3 - 1 : 0] addr2, + input [313 - 1 : 0] data2, + output [313 - 1 : 0] out2 +); + reg [313 - 1 : 0] ram[2**3 - 1 : 0]; + reg [313 - 1 : 0] data_out1; + reg [313 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 4x131 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_4x131 ( + input clk, + input we1, + input we2, + input [2 - 1 : 0] addr1, + input [131 - 1 : 0] data1, + output [131 - 1 : 0] out1, + input [2 - 1 : 0] addr2, + input [131 - 1 : 0] data2, + output [131 - 1 : 0] out2 +); + reg [131 - 1 : 0] ram[2**2 - 1 : 0]; + reg [131 - 1 : 0] data_out1; + reg [131 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v b/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v new file mode 100755 index 000000000..d410baeb3 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v @@ -0,0 +1,1538 @@ +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:41:53 EDT 2010 +// +// +// Ports: +// Name I/O size props +// RDY_iport0_put O 1 +// RDY_iport1_put O 1 +// oport_get O 153 +// RDY_oport_get O 1 +// CLK I 1 clock +// RST_N I 1 reset +// iport0_put I 153 +// iport1_put I 153 +// EN_iport0_put I 1 +// EN_iport1_put I 1 +// EN_oport_get I 1 +// +// No combinational paths from inputs to outputs +// +// + + + +module mkPktMerge(CLK, + RST_N, + + iport0_put, + EN_iport0_put, + RDY_iport0_put, + + iport1_put, + EN_iport1_put, + RDY_iport1_put, + + EN_oport_get, + oport_get, + RDY_oport_get); + input CLK; + input RST_N; + + // action method iport0_put + input [152 : 0] iport0_put; + input EN_iport0_put; + output RDY_iport0_put; + + // action method iport1_put + input [152 : 0] iport1_put; + input EN_iport1_put; + output RDY_iport1_put; + + // actionvalue method oport_get + input EN_oport_get; + output [152 : 0] oport_get; + output RDY_oport_get; + + // signals for module outputs + wire [152 : 0] oport_get; + wire RDY_iport0_put, RDY_iport1_put, RDY_oport_get; + + // register fi0Active + reg fi0Active; + wire fi0Active__D_IN; + wire fi0Active__EN; + + // register fi0HasPrio + reg fi0HasPrio; + reg fi0HasPrio__D_IN; + wire fi0HasPrio__EN; + + // register fi1Active + reg fi1Active; + wire fi1Active__D_IN, fi1Active__EN; + + // ports of submodule fi0 + wire [152 : 0] fi0__D_IN, fi0__D_OUT; + wire fi0__CLR, fi0__DEQ, fi0__EMPTY_N, fi0__ENQ, fi0__FULL_N; + + // ports of submodule fi1 + wire [152 : 0] fi1__D_IN, fi1__D_OUT; + wire fi1__CLR, fi1__DEQ, fi1__EMPTY_N, fi1__ENQ, fi1__FULL_N; + + // ports of submodule fo + reg [152 : 0] fo__D_IN; + wire [152 : 0] fo__D_OUT; + wire fo__CLR, fo__DEQ, fo__EMPTY_N, fo__ENQ, fo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_arbitrate, + CAN_FIRE_RL_fi0_advance, + CAN_FIRE_RL_fi1_advance, + CAN_FIRE_iport0_put, + CAN_FIRE_iport1_put, + CAN_FIRE_oport_get, + WILL_FIRE_RL_arbitrate, + WILL_FIRE_RL_fi0_advance, + WILL_FIRE_RL_fi1_advance, + WILL_FIRE_iport0_put, + WILL_FIRE_iport1_put, + WILL_FIRE_oport_get; + + // inputs to muxes for submodule ports + wire [152 : 0] MUX_fo__enq_1__VAL_1; + wire MUX_fi0Active__write_1__SEL_1, + MUX_fi0Active__write_1__VAL_1, + MUX_fi1Active__write_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h679; + wire fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10; + + // action method iport0_put + assign RDY_iport0_put = fi0__FULL_N ; + assign CAN_FIRE_iport0_put = fi0__FULL_N ; + assign WILL_FIRE_iport0_put = EN_iport0_put ; + + // action method iport1_put + assign RDY_iport1_put = fi1__FULL_N ; + assign CAN_FIRE_iport1_put = fi1__FULL_N ; + assign WILL_FIRE_iport1_put = EN_iport1_put ; + + // actionvalue method oport_get + assign oport_get = fo__D_OUT ; + assign RDY_oport_get = fo__EMPTY_N ; + assign CAN_FIRE_oport_get = fo__EMPTY_N ; + assign WILL_FIRE_oport_get = EN_oport_get ; + + // submodule fi0 + arSRLFIFO_a fi0 (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fi0__D_IN), + .ENQ(fi0__ENQ), + .DEQ(fi0__DEQ), + .CLR(fi0__CLR), + .D_OUT(fi0__D_OUT), + .EMPTY_N(fi0__EMPTY_N), + .FULL_N(fi0__FULL_N)); + + // submodule fi1 + arSRLFIFO_b fi1 + (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fi1__D_IN), + .ENQ(fi1__ENQ), + .DEQ(fi1__DEQ), + .CLR(fi1__CLR), + .D_OUT(fi1__D_OUT), + .EMPTY_N(fi1__EMPTY_N), + .FULL_N(fi1__FULL_N)); + + // submodule fo + arSRLFIFO_c fo + (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fo__D_IN), + .ENQ(fo__ENQ), + .DEQ(fo__DEQ), + .CLR(fo__CLR), + .D_OUT(fo__D_OUT), + .EMPTY_N(fo__EMPTY_N), + .FULL_N(fo__FULL_N)); + + // rule RL_arbitrate + assign CAN_FIRE_RL_arbitrate = + fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 && + fi0__EMPTY_N && + fi1__EMPTY_N && + !fi0Active && + !fi1Active ; + assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; + + // rule RL_fi0_advance + assign CAN_FIRE_RL_fi0_advance = fi0__EMPTY_N && fo__FULL_N && !fi1Active ; + assign WILL_FIRE_RL_fi0_advance = + CAN_FIRE_RL_fi0_advance && !WILL_FIRE_RL_arbitrate ; + + // rule RL_fi1_advance + assign CAN_FIRE_RL_fi1_advance = fi1__EMPTY_N && fo__FULL_N && !fi0Active ; + assign WILL_FIRE_RL_fi1_advance = + CAN_FIRE_RL_fi1_advance && !WILL_FIRE_RL_fi0_advance && + !WILL_FIRE_RL_arbitrate ; + + // inputs to muxes for submodule ports + assign MUX_fi0Active__write_1__SEL_1 = WILL_FIRE_RL_arbitrate && fi0HasPrio ; + assign MUX_fi1Active__write_1__SEL_1 = + WILL_FIRE_RL_arbitrate && !fi0HasPrio ; + assign MUX_fi0Active__write_1__VAL_1 = + fi0HasPrio ? !fi0__D_OUT[151] : !fi1__D_OUT[151] ; + assign MUX_fo__enq_1__VAL_1 = fi0HasPrio ? fi0__D_OUT : fi1__D_OUT ; + + // register fi0Active + assign fi0Active__D_IN = + MUX_fi0Active__write_1__SEL_1 ? + MUX_fi0Active__write_1__VAL_1 : + !fi0__D_OUT[151] ; + assign fi0Active__EN = + WILL_FIRE_RL_arbitrate && fi0HasPrio || + WILL_FIRE_RL_fi0_advance ; + + // register fi0HasPrio + always@(WILL_FIRE_RL_arbitrate or + fi0HasPrio or WILL_FIRE_RL_fi0_advance or WILL_FIRE_RL_fi1_advance) + begin + // case (1'b1) // synopsys parallel_case + // WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio; + // WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0; + // WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1; + //case (1'b1) // synopsys parallel_case + // WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio; + fi0HasPrio__D_IN = !fi0HasPrio; + // WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0; + // WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1; + +// endcase + //endcase + end + assign fi0HasPrio__EN = + WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || + WILL_FIRE_RL_fi1_advance ; + + // register fi1Active + assign fi1Active__D_IN = + MUX_fi1Active__write_1__SEL_1 ? + MUX_fi0Active__write_1__VAL_1 : + !fi1__D_OUT[151] ; + assign fi1Active__EN = + WILL_FIRE_RL_arbitrate && !fi0HasPrio || + WILL_FIRE_RL_fi1_advance ; + + // submodule fi0 + assign fi0__D_IN = iport0_put ; + assign fi0__DEQ = + WILL_FIRE_RL_arbitrate && fi0HasPrio || + WILL_FIRE_RL_fi0_advance ; + assign fi0__ENQ = EN_iport0_put ; + assign fi0__CLR = 1'b0 ; + + // submodule fi1 + assign fi1__D_IN = iport1_put ; + assign fi1__DEQ = + WILL_FIRE_RL_arbitrate && !fi0HasPrio || + WILL_FIRE_RL_fi1_advance ; + assign fi1__ENQ = EN_iport1_put ; + assign fi1__CLR = 1'b0 ; + + // submodule fo + always@(WILL_FIRE_RL_arbitrate or + MUX_fo__enq_1__VAL_1 or + WILL_FIRE_RL_fi0_advance or + fi0__D_OUT or WILL_FIRE_RL_fi1_advance or fi1__D_OUT) + begin + // case (1'b1) // synopsys parallel_case + //WILL_FIRE_RL_arbitrate: fo__D_IN = MUX_fo__enq_1__VAL_1; + fo__D_IN = MUX_fo__enq_1__VAL_1; + // WILL_FIRE_RL_fi0_advance: fo__D_IN = fi0__D_OUT; + // WILL_FIRE_RL_fi1_advance: fo__D_IN = fi1__D_OUT; + + // endcase + end + assign fo__DEQ = EN_oport_get ; + assign fo__ENQ = + WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || + WILL_FIRE_RL_fi1_advance ; + assign fo__CLR = 1'b0 ; + + // remaining internal signals + assign fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 = + fo__FULL_N && (fi0HasPrio ? fi0__EMPTY_N : fi1__EMPTY_N) ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (!RST_N) + begin + fi0Active <= 1'd0; + fi0HasPrio <= 1'd1; + fi1Active <= 1'd0; + end + else + begin + if (fi0Active__EN) fi0Active <= fi0Active__D_IN; + if (fi0HasPrio__EN) + fi0HasPrio <= fi0HasPrio__D_IN; + if (fi1Active__EN) fi1Active <= fi1Active__D_IN; + end + end + + + // handling of system tasks + + +endmodule // mkPktMerge + + + + +module arSRLFIFO_a (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset +`define dw 153 +`define aw 4 +`define n 32 +`define max_size 30 + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + + +module arSRLFIFO_b (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + + + + +module arSRLFIFO_c (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + +//--------------------------------------- +// A dual-port RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram ( + input clk, + input we1, + input we2, + input [`aw - 1 : 0] addr1, + input [`dw - 1 : 0] data1, + output [`dw - 1 : 0] out1, + input [`aw - 1 : 0] addr2, + input [`dw - 1 : 0] data2, + output [`dw - 1 : 0] out2 +); + + reg [`dw - 1 : 0] ram[2**`aw - 1 : 0]; + reg [`dw - 1 : 0] data_out1; + reg [`dw - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v b/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v new file mode 100755 index 000000000..d5c26e2bf --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v @@ -0,0 +1,4512 @@ +`define n 32 +`define max_size 30 + +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:43:05 EDT 2010 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wmiM_MCmd O 3 +// wmiM_MReqLast O 1 reg +// wmiM_MReqInfo O 1 reg +// wmiM_MAddrSpace O 1 reg +// wmiM_MAddr O 14 reg +// wmiM_MBurstLength O 12 reg +// wmiM_MDataValid O 1 +// wmiM_MDataLast O 1 reg +// wmiM_MData O 32 reg +// wmiM_MDataByteEn O 4 reg +// wmiM_MFlag O 32 +// wmiM_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 32 reg +// wsiM1_MByteEn O 4 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 20 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wmiM_SResp I 2 +// wmiM_SData I 32 +// wmiM_SFlag I 32 reg +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 32 +// wsiS1_MByteEn I 4 +// wsiS1_MReqInfo I 8 +// wmiM_SThreadBusy I 1 reg +// wmiM_SDataThreadBusy I 1 reg +// wmiM_SRespLast I 1 unused +// wmiM_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +module mkSMAdapter4B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wmiM_MCmd, + + wmiM_MReqLast, + + wmiM_MReqInfo, + + wmiM_MAddrSpace, + + wmiM_MAddr, + + wmiM_MBurstLength, + + wmiM_MDataValid, + + wmiM_MDataLast, + + wmiM_MData, + + wmiM_MDataByteEn, + + wmiM_SResp, + + wmiM_SData, + + wmiM_SThreadBusy, + + wmiM_SDataThreadBusy, + + wmiM_SRespLast, + + wmiM_SFlag, + + wmiM_MFlag, + + wmiM_MReset_n, + + wmiM_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + prevent_sweep_node); + parameter [31 : 0] smaCtrlInit = 32'b0; + input wciS0_Clk; + input wciS0_MReset_n; + output prevent_sweep_node; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [19 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // value method wmiM_mCmd + output [2 : 0] wmiM_MCmd; + + // value method wmiM_mReqLast + output wmiM_MReqLast; + + // value method wmiM_mReqInfo + output wmiM_MReqInfo; + + // value method wmiM_mAddrSpace + output wmiM_MAddrSpace; + + // value method wmiM_mAddr + output [13 : 0] wmiM_MAddr; + + // value method wmiM_mBurstLength + output [11 : 0] wmiM_MBurstLength; + + // value method wmiM_mDataValid + output wmiM_MDataValid; + + // value method wmiM_mDataLast + output wmiM_MDataLast; + + // value method wmiM_mData + output [31 : 0] wmiM_MData; + + // value method wmiM_mDataInfo + + // value method wmiM_mDataByteEn + output [3 : 0] wmiM_MDataByteEn; + + // action method wmiM_sResp + input [1 : 0] wmiM_SResp; + + // action method wmiM_sData + input [31 : 0] wmiM_SData; + + // action method wmiM_sThreadBusy + input wmiM_SThreadBusy; + + // action method wmiM_sDataThreadBusy + input wmiM_SDataThreadBusy; + + // action method wmiM_sRespLast + input wmiM_SRespLast; + + // action method wmiM_sFlag + input [31 : 0] wmiM_SFlag; + + // value method wmiM_mFlag + output [31 : 0] wmiM_MFlag; + + // value method wmiM_mReset_n + output wmiM_MReset_n; + + // action method wmiM_sReset_n + input wmiM_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [31 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [3 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [31 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [3 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // signals for module outputs + wire [31 : 0] wciS0_SData, wmiM_MData, wmiM_MFlag, wsiM1_MData; + wire [13 : 0] wmiM_MAddr; + wire [11 : 0] wmiM_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM1_MReqInfo; + wire [3 : 0] wmiM_MDataByteEn, wsiM1_MByteEn; + wire [2 : 0] wmiM_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wmiM_MAddrSpace, + wmiM_MDataLast, + wmiM_MDataValid, + wmiM_MReqInfo, + wmiM_MReqLast, + wmiM_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [95 : 0] wsiM_extStatusW__wget, wsiS_extStatusW__wget; + wire [60 : 0] wsiM_reqFifo_x_wire__wget, wsiS_wsiReq__wget; + wire [59 : 0] wci_wciReq__wget; + wire [37 : 0] wmi_dhF_x_wire__wget; + wire [33 : 0] wci_respF_x_wire__wget, wmi_wmiResponse__wget; + wire [31 : 0] wci_Es_mData_w__wget, + wmi_Em_sData_w__wget, + wmi_mFlagF_x_wire__wget, + wmi_reqF_x_wire__wget, + wsi_Es_mData_w__wget; + wire [19 : 0] wci_Es_mAddr_w__wget; + wire [11 : 0] wsi_Es_mBurstLength_w__wget; + wire [7 : 0] wsi_Es_mReqInfo_w__wget; + wire [3 : 0] fabRespCredit_acc_v1__wget, + fabRespCredit_acc_v2__wget, + wci_Es_mByteEn_w__wget, + wsi_Es_mByteEn_w__wget; + wire [2 : 0] wci_Es_mCmd_w__wget, wci_wEdge__wget, wsi_Es_mCmd_w__wget; + wire [1 : 0] wmi_Em_sResp_w__wget; + wire fabRespCredit_acc_v1__whas, + fabRespCredit_acc_v2__whas, + mesgPreRequest_1__wget, + mesgPreRequest_1__whas, + wci_Es_mAddrSpace_w__wget, + wci_Es_mAddrSpace_w__whas, + wci_Es_mAddr_w__whas, + wci_Es_mByteEn_w__whas, + wci_Es_mCmd_w__whas, + wci_Es_mData_w__whas, + wci_ctlAckReg_1__wget, + wci_ctlAckReg_1__whas, + wci_reqF_r_clr__whas, + wci_reqF_r_deq__whas, + wci_reqF_r_enq__whas, + wci_respF_dequeueing__whas, + wci_respF_enqueueing__whas, + wci_respF_x_wire__whas, + wci_sFlagReg_1__wget, + wci_sFlagReg_1__whas, + wci_sThreadBusy_pw__whas, + wci_wEdge__whas, + wci_wciReq__whas, + wci_wci_cfrd_pw__whas, + wci_wci_cfwr_pw__whas, + wci_wci_ctrl_pw__whas, + wmi_Em_sData_w__whas, + wmi_Em_sResp_w__whas, + wmi_dhF_dequeueing__whas, + wmi_dhF_enqueueing__whas, + wmi_dhF_x_wire__whas, + wmi_mFlagF_dequeueing__whas, + wmi_mFlagF_enqueueing__whas, + wmi_mFlagF_x_wire__whas, + wmi_operateD_1__wget, + wmi_operateD_1__whas, + wmi_peerIsReady_1__wget, + wmi_peerIsReady_1__whas, + wmi_reqF_dequeueing__whas, + wmi_reqF_enqueueing__whas, + wmi_reqF_x_wire__whas, + wmi_sDataThreadBusy_d_1__wget, + wmi_sDataThreadBusy_d_1__whas, + wmi_sThreadBusy_d_1__wget, + wmi_sThreadBusy_d_1__whas, + wmi_wmiResponse__whas, + wsiM_operateD_1__wget, + wsiM_operateD_1__whas, + wsiM_peerIsReady_1__wget, + wsiM_peerIsReady_1__whas, + wsiM_reqFifo_dequeueing__whas, + wsiM_reqFifo_enqueueing__whas, + wsiM_reqFifo_x_wire__whas, + wsiM_sThreadBusy_pw__whas, + wsiS_operateD_1__wget, + wsiS_operateD_1__whas, + wsiS_peerIsReady_1__wget, + wsiS_peerIsReady_1__whas, + wsiS_reqFifo_r_clr__whas, + wsiS_reqFifo_r_deq__whas, + wsiS_reqFifo_r_enq__whas, + wsiS_wsiReq__whas, + wsi_Es_mBurstLength_w__whas, + wsi_Es_mBurstPrecise_w__whas, + wsi_Es_mByteEn_w__whas, + wsi_Es_mCmd_w__whas, + wsi_Es_mDataInfo_w__whas, + wsi_Es_mData_w__whas, + wsi_Es_mReqInfo_w__whas, + wsi_Es_mReqLast_w__whas; + + // register abortCount + reg [31 : 0] abortCount; + wire [31 : 0] abortCount__D_IN; + wire abortCount__EN; + + // register doAbort + reg doAbort; + wire doAbort__D_IN, doAbort__EN; + + // register endOfMessage + reg endOfMessage; + wire endOfMessage__D_IN, endOfMessage__EN; + + // register errCount + reg [31 : 0] errCount; + wire [31 : 0] errCount__D_IN; + wire errCount__EN; + + // register fabRespCredit_value + reg [3 : 0] fabRespCredit_value; + wire [3 : 0] fabRespCredit_value__D_IN; + wire fabRespCredit_value__EN; + + // register fabWordsCurReq + reg [13 : 0] fabWordsCurReq; + wire [13 : 0] fabWordsCurReq__D_IN; + wire fabWordsCurReq__EN; + + // register fabWordsRemain + reg [13 : 0] fabWordsRemain; + wire [13 : 0] fabWordsRemain__D_IN; + wire fabWordsRemain__EN; + + // register firstMsgReq + reg firstMsgReq; + wire firstMsgReq__D_IN, firstMsgReq__EN; + + // register impreciseBurst + reg impreciseBurst; + reg impreciseBurst__D_IN; + wire impreciseBurst__EN; + + // register lastMesg + reg [31 : 0] lastMesg; + wire [31 : 0] lastMesg__D_IN; + wire lastMesg__EN; + + // register mesgCount + reg [31 : 0] mesgCount; + reg [31 : 0] mesgCount__D_IN; + wire mesgCount__EN; + + // register mesgLength + reg [14 : 0] mesgLength; + reg [14 : 0] mesgLength__D_IN; + wire mesgLength__EN; + + // register mesgLengthSoFar + reg [13 : 0] mesgLengthSoFar; + wire [13 : 0] mesgLengthSoFar__D_IN; + wire mesgLengthSoFar__EN; + + // register mesgPreRequest + reg mesgPreRequest; + wire mesgPreRequest__D_IN, mesgPreRequest__EN; + + // register mesgReqAddr + reg [13 : 0] mesgReqAddr; + wire [13 : 0] mesgReqAddr__D_IN; + wire mesgReqAddr__EN; + + // register mesgReqOK + reg mesgReqOK; + wire mesgReqOK__D_IN, mesgReqOK__EN; + + // register mesgReqValid + reg mesgReqValid; + wire mesgReqValid__D_IN, mesgReqValid__EN; + + // register opcode + reg [8 : 0] opcode; + reg [8 : 0] opcode__D_IN; + wire opcode__EN; + + // register preciseBurst + reg preciseBurst; + reg preciseBurst__D_IN; + wire preciseBurst__EN; + + // register readyToPush + reg readyToPush; + reg readyToPush__D_IN; + wire readyToPush__EN; + + // register readyToRequest + reg readyToRequest; + wire readyToRequest__D_IN, readyToRequest__EN; + + // register smaCtrl + reg [31 : 0] smaCtrl; + wire [31 : 0] smaCtrl__D_IN; + wire smaCtrl__EN; + + // register thisMesg + reg [31 : 0] thisMesg; + reg [31 : 0] thisMesg__D_IN; + wire thisMesg__EN; + + // register unrollCnt + reg [15 : 0] unrollCnt; + wire [15 : 0] unrollCnt__D_IN; + wire unrollCnt__EN; + + // register valExpect + reg [31 : 0] valExpect; + wire [31 : 0] valExpect__D_IN; + wire valExpect__EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge__D_IN; + wire wci_cEdge__EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState__D_IN; + wire wci_cState__EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg__D_IN, wci_ctlAckReg__EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive__D_IN, wci_ctlOpActive__EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge__D_IN, wci_illegalEdge__EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState__D_IN; + wire wci_nState__EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg__D_IN; + wire wci_reqF_countReg__EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r__D_IN; + wire wci_respF_c_r__EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0__D_IN; + wire wci_respF_q_0__EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1__D_IN; + wire wci_respF_q_1__EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg__D_IN, wci_sFlagReg__EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d__D_IN, wci_sThreadBusy_d__EN; + + // register wmi_busyWithMessage + reg wmi_busyWithMessage; + wire wmi_busyWithMessage__D_IN, wmi_busyWithMessage__EN; + + // register wmi_dhF_c_r + reg [1 : 0] wmi_dhF_c_r; + wire [1 : 0] wmi_dhF_c_r__D_IN; + wire wmi_dhF_c_r__EN; + + // register wmi_dhF_q_0 + reg [37 : 0] wmi_dhF_q_0; + reg [37 : 0] wmi_dhF_q_0__D_IN; + wire wmi_dhF_q_0__EN; + + // register wmi_dhF_q_1 + reg [37 : 0] wmi_dhF_q_1; + reg [37 : 0] wmi_dhF_q_1__D_IN; + wire wmi_dhF_q_1__EN; + + // register wmi_mFlagF_c_r + reg [1 : 0] wmi_mFlagF_c_r; + wire [1 : 0] wmi_mFlagF_c_r__D_IN; + wire wmi_mFlagF_c_r__EN; + + // register wmi_mFlagF_q_0 + reg [31 : 0] wmi_mFlagF_q_0; + reg [31 : 0] wmi_mFlagF_q_0__D_IN; + wire wmi_mFlagF_q_0__EN; + + // register wmi_mFlagF_q_1 + reg [31 : 0] wmi_mFlagF_q_1; + reg [31 : 0] wmi_mFlagF_q_1__D_IN; + wire wmi_mFlagF_q_1__EN; + + // register wmi_operateD + reg wmi_operateD; + wire wmi_operateD__D_IN, wmi_operateD__EN; + + // register wmi_peerIsReady + reg wmi_peerIsReady; + wire wmi_peerIsReady__D_IN, wmi_peerIsReady__EN; + + // register wmi_reqF_c_r + reg [1 : 0] wmi_reqF_c_r; + wire [1 : 0] wmi_reqF_c_r__D_IN; + wire wmi_reqF_c_r__EN; + + // register wmi_reqF_q_0 + reg [31 : 0] wmi_reqF_q_0; + reg [31 : 0] wmi_reqF_q_0__D_IN; + wire wmi_reqF_q_0__EN; + + // register wmi_reqF_q_1 + reg [31 : 0] wmi_reqF_q_1; + reg [31 : 0] wmi_reqF_q_1__D_IN; + wire wmi_reqF_q_1__EN; + + // register wmi_sDataThreadBusy_d + reg wmi_sDataThreadBusy_d; + wire wmi_sDataThreadBusy_d__D_IN, wmi_sDataThreadBusy_d__EN; + + // register wmi_sFlagReg + reg [31 : 0] wmi_sFlagReg; + wire [31 : 0] wmi_sFlagReg__D_IN; + wire wmi_sFlagReg__EN; + + // register wmi_sThreadBusy_d + reg wmi_sThreadBusy_d; + wire wmi_sThreadBusy_d__D_IN, wmi_sThreadBusy_d__EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind__D_IN; + wire wsiM_burstKind__EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky__D_IN, wsiM_errorSticky__EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount__D_IN; + wire wsiM_iMesgCount__EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD__D_IN, wsiM_operateD__EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount__D_IN; + wire wsiM_pMesgCount__EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady__D_IN, wsiM_peerIsReady__EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r__D_IN; + wire wsiM_reqFifo_c_r__EN; + + // register wsiM_reqFifo_q_0 + reg [60 : 0] wsiM_reqFifo_q_0; + reg [60 : 0] wsiM_reqFifo_q_0__D_IN; + wire wsiM_reqFifo_q_0__EN; + + // register wsiM_reqFifo_q_1 + reg [60 : 0] wsiM_reqFifo_q_1; + reg [60 : 0] wsiM_reqFifo_q_1__D_IN; + wire wsiM_reqFifo_q_1__EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d__D_IN, wsiM_sThreadBusy_d__EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR__D_IN; + wire wsiM_statusR__EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount__D_IN; + wire wsiM_tBusyCount__EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky__D_IN, wsiM_trafficSticky__EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind__D_IN; + wire wsiS_burstKind__EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky__D_IN, wsiS_errorSticky__EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount__D_IN; + wire wsiS_iMesgCount__EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD__D_IN, wsiS_operateD__EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount__D_IN; + wire wsiS_pMesgCount__EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady__D_IN, wsiS_peerIsReady__EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg__D_IN; + wire wsiS_reqFifo_countReg__EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR__D_IN; + wire wsiS_statusR__EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount__D_IN; + wire wsiS_tBusyCount__EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky__D_IN, wsiS_trafficSticky__EN; + + // register wsiWordsRemain + reg [11 : 0] wsiWordsRemain; + wire [11 : 0] wsiWordsRemain__D_IN; + wire wsiWordsRemain__EN; + + // register zeroLengthMesg + reg zeroLengthMesg; + wire zeroLengthMesg__D_IN, zeroLengthMesg__EN; + + // ports of submodule wci_isReset + wire wci_isReset__VAL; + + // ports of submodule wci_reqF + wire [59 : 0] wci_reqF__D_IN, wci_reqF__D_OUT; + wire wci_reqF__CLR, wci_reqF__DEQ, wci_reqF__EMPTY_N, wci_reqF__ENQ; + + // ports of submodule wmi_isReset + wire wmi_isReset__VAL; + + // ports of submodule wmi_respF + wire [31 : 0] wmi_respF__D_IN; + wire [31:0] wmi_respF__D_OUT; + wire wmi_respF__CLR, + wmi_respF__DEQ, + wmi_respF__EMPTY_N, + wmi_respF__ENQ, + wmi_respF__FULL_N; + + // ports of submodule wsiM_isReset + wire wsiM_isReset__VAL; + + // ports of submodule wsiS_isReset + wire wsiS_isReset__VAL; + + // ports of submodule wsiS_reqFifo + wire [60 : 0] wsiS_reqFifo__D_IN, wsiS_reqFifo__D_OUT; + wire wsiS_reqFifo__CLR, + wsiS_reqFifo__DEQ, + wsiS_reqFifo__EMPTY_N, + wsiS_reqFifo__ENQ, + wsiS_reqFifo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_fabRespCredit_accumulate, + CAN_FIRE_RL_mesgPreRequest__dreg_update, + CAN_FIRE_RL_operating_actions, + CAN_FIRE_RL_wci_Es_doAlways_Req, + CAN_FIRE_RL_wci_cfrd, + CAN_FIRE_RL_wci_cfwr, + CAN_FIRE_RL_wci_ctlAckReg__dreg_update, + CAN_FIRE_RL_wci_ctl_op_complete, + CAN_FIRE_RL_wci_ctl_op_start, + CAN_FIRE_RL_wci_ctrl_EiI, + CAN_FIRE_RL_wci_ctrl_IsO, + CAN_FIRE_RL_wci_ctrl_OrE, + CAN_FIRE_RL_wci_reqF__updateLevelCounter, + CAN_FIRE_RL_wci_reqF_enq, + CAN_FIRE_RL_wci_request_decode, + CAN_FIRE_RL_wci_respF_both, + CAN_FIRE_RL_wci_respF_decCtr, + CAN_FIRE_RL_wci_respF_deq, + CAN_FIRE_RL_wci_respF_incCtr, + CAN_FIRE_RL_wci_sFlagReg__dreg_update, + CAN_FIRE_RL_wci_sThreadBusy_reg, + CAN_FIRE_RL_wmi_Em_doAlways, + CAN_FIRE_RL_wmi_dhF_both, + CAN_FIRE_RL_wmi_dhF_decCtr, + CAN_FIRE_RL_wmi_dhF_deq, + CAN_FIRE_RL_wmi_dhF_incCtr, + CAN_FIRE_RL_wmi_mFlagF_both, + CAN_FIRE_RL_wmi_mFlagF_decCtr, + CAN_FIRE_RL_wmi_mFlagF_incCtr, + CAN_FIRE_RL_wmi_operateD__dreg_update, + CAN_FIRE_RL_wmi_peerIsReady__dreg_update, + CAN_FIRE_RL_wmi_reqF_both, + CAN_FIRE_RL_wmi_reqF_decCtr, + CAN_FIRE_RL_wmi_reqF_deq, + CAN_FIRE_RL_wmi_reqF_incCtr, + CAN_FIRE_RL_wmi_respAdvance, + CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update, + CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update, + CAN_FIRE_RL_wmrd_mesgBegin, + CAN_FIRE_RL_wmrd_mesgBodyPreRequest, + CAN_FIRE_RL_wmrd_mesgBodyRequest, + CAN_FIRE_RL_wmrd_mesgBodyResponse, + CAN_FIRE_RL_wmwt_doAbort, + CAN_FIRE_RL_wmwt_mesgBegin, + CAN_FIRE_RL_wmwt_messageFinalize, + CAN_FIRE_RL_wmwt_messagePushImprecise, + CAN_FIRE_RL_wmwt_messagePushPrecise, + CAN_FIRE_RL_wmwt_requestPrecise, + CAN_FIRE_RL_wsiM_ext_status_assign, + CAN_FIRE_RL_wsiM_inc_tBusyCount, + CAN_FIRE_RL_wsiM_operateD__dreg_update, + CAN_FIRE_RL_wsiM_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiM_reqFifo_both, + CAN_FIRE_RL_wsiM_reqFifo_decCtr, + CAN_FIRE_RL_wsiM_reqFifo_deq, + CAN_FIRE_RL_wsiM_reqFifo_incCtr, + CAN_FIRE_RL_wsiM_sThreadBusy_reg, + CAN_FIRE_RL_wsiM_update_statusR, + CAN_FIRE_RL_wsiS_ext_status_assign, + CAN_FIRE_RL_wsiS_inc_tBusyCount, + CAN_FIRE_RL_wsiS_operateD__dreg_update, + CAN_FIRE_RL_wsiS_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + CAN_FIRE_RL_wsiS_reqFifo_enq, + CAN_FIRE_RL_wsiS_update_statusR, + CAN_FIRE_RL_wsi_Es_doAlways, + CAN_FIRE_RL_wsipass_doMessagePush, + CAN_FIRE_wciS0_mAddr, + CAN_FIRE_wciS0_mAddrSpace, + CAN_FIRE_wciS0_mByteEn, + CAN_FIRE_wciS0_mCmd, + CAN_FIRE_wciS0_mData, + CAN_FIRE_wciS0_mFlag, + CAN_FIRE_wmiM_sData, + CAN_FIRE_wmiM_sDataThreadBusy, + CAN_FIRE_wmiM_sFlag, + CAN_FIRE_wmiM_sReset_n, + CAN_FIRE_wmiM_sResp, + CAN_FIRE_wmiM_sRespLast, + CAN_FIRE_wmiM_sThreadBusy, + CAN_FIRE_wsiM1_sReset_n, + CAN_FIRE_wsiM1_sThreadBusy, + CAN_FIRE_wsiS1_mBurstLength, + CAN_FIRE_wsiS1_mBurstPrecise, + CAN_FIRE_wsiS1_mByteEn, + CAN_FIRE_wsiS1_mCmd, + CAN_FIRE_wsiS1_mData, + CAN_FIRE_wsiS1_mDataInfo, + CAN_FIRE_wsiS1_mReqInfo, + CAN_FIRE_wsiS1_mReqLast, + CAN_FIRE_wsiS1_mReset_n, + WILL_FIRE_RL_fabRespCredit_accumulate, + WILL_FIRE_RL_mesgPreRequest__dreg_update, + WILL_FIRE_RL_operating_actions, + WILL_FIRE_RL_wci_Es_doAlways_Req, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctlAckReg__dreg_update, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_reqF__updateLevelCounter, + WILL_FIRE_RL_wci_reqF_enq, + WILL_FIRE_RL_wci_request_decode, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_deq, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wci_sFlagReg__dreg_update, + WILL_FIRE_RL_wci_sThreadBusy_reg, + WILL_FIRE_RL_wmi_Em_doAlways, + WILL_FIRE_RL_wmi_dhF_both, + WILL_FIRE_RL_wmi_dhF_decCtr, + WILL_FIRE_RL_wmi_dhF_deq, + WILL_FIRE_RL_wmi_dhF_incCtr, + WILL_FIRE_RL_wmi_mFlagF_both, + WILL_FIRE_RL_wmi_mFlagF_decCtr, + WILL_FIRE_RL_wmi_mFlagF_incCtr, + WILL_FIRE_RL_wmi_operateD__dreg_update, + WILL_FIRE_RL_wmi_peerIsReady__dreg_update, + WILL_FIRE_RL_wmi_reqF_both, + WILL_FIRE_RL_wmi_reqF_decCtr, + WILL_FIRE_RL_wmi_reqF_deq, + WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmi_respAdvance, + WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update, + WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update, + WILL_FIRE_RL_wmrd_mesgBegin, + WILL_FIRE_RL_wmrd_mesgBodyPreRequest, + WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, + WILL_FIRE_RL_wmwt_doAbort, + WILL_FIRE_RL_wmwt_mesgBegin, + WILL_FIRE_RL_wmwt_messageFinalize, + WILL_FIRE_RL_wmwt_messagePushImprecise, + WILL_FIRE_RL_wmwt_messagePushPrecise, + WILL_FIRE_RL_wmwt_requestPrecise, + WILL_FIRE_RL_wsiM_ext_status_assign, + WILL_FIRE_RL_wsiM_inc_tBusyCount, + WILL_FIRE_RL_wsiM_operateD__dreg_update, + WILL_FIRE_RL_wsiM_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiM_sThreadBusy_reg, + WILL_FIRE_RL_wsiM_update_statusR, + WILL_FIRE_RL_wsiS_ext_status_assign, + WILL_FIRE_RL_wsiS_inc_tBusyCount, + WILL_FIRE_RL_wsiS_operateD__dreg_update, + WILL_FIRE_RL_wsiS_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_update_statusR, + WILL_FIRE_RL_wsi_Es_doAlways, + WILL_FIRE_RL_wsipass_doMessagePush, + WILL_FIRE_wciS0_mAddr, + WILL_FIRE_wciS0_mAddrSpace, + WILL_FIRE_wciS0_mByteEn, + WILL_FIRE_wciS0_mCmd, + WILL_FIRE_wciS0_mData, + WILL_FIRE_wciS0_mFlag, + WILL_FIRE_wmiM_sData, + WILL_FIRE_wmiM_sDataThreadBusy, + WILL_FIRE_wmiM_sFlag, + WILL_FIRE_wmiM_sReset_n, + WILL_FIRE_wmiM_sResp, + WILL_FIRE_wmiM_sRespLast, + WILL_FIRE_wmiM_sThreadBusy, + WILL_FIRE_wsiM1_sReset_n, + WILL_FIRE_wsiM1_sThreadBusy, + WILL_FIRE_wsiS1_mBurstLength, + WILL_FIRE_wsiS1_mBurstPrecise, + WILL_FIRE_wsiS1_mByteEn, + WILL_FIRE_wsiS1_mCmd, + WILL_FIRE_wsiS1_mData, + WILL_FIRE_wsiS1_mDataInfo, + WILL_FIRE_wsiS1_mReqInfo, + WILL_FIRE_wsiS1_mReqLast, + WILL_FIRE_wsiS1_mReset_n; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0__write_1__VAL_1; + reg [31 : 0] MUX_wmi_reqF_q_0__write_1__VAL_1; + wire [60 : 0] MUX_wsiM_reqFifo_q_0__write_1__VAL_1, + MUX_wsiM_reqFifo_q_0__write_1__VAL_2, + MUX_wsiM_reqFifo_q_1__write_1__VAL_1, + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1; + wire [37 : 0] MUX_wmi_dhF_q_0__write_1__VAL_1, + MUX_wmi_dhF_q_0__write_1__VAL_2, + MUX_wmi_dhF_q_1__write_1__VAL_1, + MUX_wmi_dhF_x_wire__wset_1__VAL_1, + MUX_wmi_dhF_x_wire__wset_1__VAL_2; + wire [33 : 0] MUX_wci_respF_q_0__write_1__VAL_2, + MUX_wci_respF_q_1__write_1__VAL_2, + MUX_wci_respF_x_wire__wset_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_2; + wire [31 : 0] MUX_mesgCount__write_1__VAL_1, + MUX_thisMesg__write_1__VAL_1, + MUX_thisMesg__write_1__VAL_2, + MUX_wmi_mFlagF_q_0__write_1__VAL_1, + MUX_wmi_mFlagF_q_1__write_1__VAL_1, + MUX_wmi_mFlagF_x_wire__wset_1__VAL_1, + MUX_wmi_mFlagF_x_wire__wset_1__VAL_3, + MUX_wmi_reqF_q_0__write_1__VAL_2, + MUX_wmi_reqF_q_1__write_1__VAL_2, + MUX_wmi_reqF_x_wire__wset_1__VAL_1, + MUX_wmi_reqF_x_wire__wset_1__VAL_2, + MUX_wmi_reqF_x_wire__wset_1__VAL_3; + wire [15 : 0] MUX_unrollCnt__write_1__VAL_1, MUX_unrollCnt__write_1__VAL_2; + wire [14 : 0] MUX_mesgLength__write_1__VAL_2, MUX_mesgLength__write_1__VAL_4; + wire [13 : 0] MUX_fabWordsRemain__write_1__VAL_1, + MUX_fabWordsRemain__write_1__VAL_2, + MUX_mesgReqAddr__write_1__VAL_2; + wire [11 : 0] MUX_wsiWordsRemain__write_1__VAL_2; + wire [8 : 0] MUX_opcode__write_1__VAL_2; + wire [3 : 0] MUX_fabRespCredit_value__write_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_2, + MUX_wmi_dhF_c_r__write_1__VAL_1, + MUX_wmi_dhF_c_r__write_1__VAL_2, + MUX_wmi_mFlagF_c_r__write_1__VAL_1, + MUX_wmi_mFlagF_c_r__write_1__VAL_2, + MUX_wmi_reqF_c_r__write_1__VAL_1, + MUX_wmi_reqF_c_r__write_1__VAL_2, + MUX_wsiM_reqFifo_c_r__write_1__VAL_1, + MUX_wsiM_reqFifo_c_r__write_1__VAL_2; + wire MUX_endOfMessage__write_1__SEL_1, + MUX_impreciseBurst__write_1__SEL_2, + MUX_lastMesg__write_1__SEL_2, + MUX_mesgCount__write_1__SEL_1, + MUX_mesgLength__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__SEL_1, + MUX_wci_illegalEdge__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__VAL_2, + MUX_wci_respF_q_0__write_1__SEL_1, + MUX_wci_respF_q_1__write_1__SEL_1, + MUX_wmi_dhF_q_0__write_1__SEL_2, + MUX_wmi_dhF_q_1__write_1__SEL_2, + MUX_wmi_mFlagF_q_0__write_1__SEL_2, + MUX_wmi_mFlagF_q_1__write_1__SEL_2, + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2, + MUX_wmi_reqF_q_0__write_1__SEL_1, + MUX_wmi_reqF_q_1__write_1__SEL_1, + MUX_wsiM_reqFifo_q_0__write_1__SEL_2, + MUX_wsiM_reqFifo_q_1__write_1__SEL_2, + MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h15314, + v__h16237, + v__h16483, + v__h18176, + v__h18253, + v__h19470, + v__h2653, + v__h2800, + v__h3699; + reg [31 : 0] value__h6065, x_data__h15447; + wire [31 : 0] rdat__h15540; + wire [23 : 0] mesgMetaF_length__h16810, mesgMetaF_length__h17723; + wire [15 : 0] wsiBurstLength__h18454, x__h15543, x_length__h17087; + wire [13 : 0] IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753, + addr__h16647, + b__h19084, + mlp1B__h16631, + mlp1__h16630; + wire [11 : 0] bl__h17580, x_burstLength__h18559; + wire [7 : 0] mesgMetaF_opcode__h16809; + wire [3 : 0] b__h13937, x_byteEn__h18561; + wire NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290, + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355, + wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165, + x__h16715, + x__h18884; + + // action method wciS0_mCmd + assign CAN_FIRE_wciS0_mCmd = 1'b1 ; + assign WILL_FIRE_wciS0_mCmd = 1'b1 ; + + // action method wciS0_mAddrSpace + assign CAN_FIRE_wciS0_mAddrSpace = 1'b1 ; + assign WILL_FIRE_wciS0_mAddrSpace = 1'b1 ; + + // action method wciS0_mByteEn + assign CAN_FIRE_wciS0_mByteEn = 1'b1 ; + assign WILL_FIRE_wciS0_mByteEn = 1'b1 ; + + // action method wciS0_mAddr + assign CAN_FIRE_wciS0_mAddr = 1'b1 ; + assign WILL_FIRE_wciS0_mAddr = 1'b1 ; + + // action method wciS0_mData + assign CAN_FIRE_wciS0_mData = 1'b1 ; + assign WILL_FIRE_wciS0_mData = 1'b1 ; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = wci_reqF_countReg > 2'b01 || wci_isReset__VAL ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'b1, wci_sFlagReg } ; + + // action method wciS0_mFlag + assign CAN_FIRE_wciS0_mFlag = 1'b1 ; + assign WILL_FIRE_wciS0_mFlag = 1'b1 ; + + // value method wmiM_mCmd + assign wmiM_MCmd = wmi_sThreadBusy_d ? 3'b000 : wmi_reqF_q_0[31:29] ; + + // value method wmiM_mReqLast + assign wmiM_MReqLast = wmi_reqF_q_0[28] ; + + // value method wmiM_mReqInfo + assign wmiM_MReqInfo = wmi_reqF_q_0[27] ; + + // value method wmiM_mAddrSpace + assign wmiM_MAddrSpace = wmi_reqF_q_0[26] ; + + // value method wmiM_mAddr + assign wmiM_MAddr = wmi_reqF_q_0[25:12] ; + + // value method wmiM_mBurstLength + assign wmiM_MBurstLength = wmi_reqF_q_0[11:0] ; + + // value method wmiM_mDataValid + assign wmiM_MDataValid = !wmi_sDataThreadBusy_d && wmi_dhF_q_0[37] ; + + // value method wmiM_mDataLast + assign wmiM_MDataLast = wmi_dhF_q_0[36] ; + + // value method wmiM_mData + assign wmiM_MData = wmi_dhF_q_0[35:4] ; + + // value method wmiM_mDataByteEn + assign wmiM_MDataByteEn = wmi_dhF_q_0[3:0] ; + + // action method wmiM_sResp + assign CAN_FIRE_wmiM_sResp = 1'b1 ; + assign WILL_FIRE_wmiM_sResp = 1'b1 ; + + // action method wmiM_sData + assign CAN_FIRE_wmiM_sData = 1'b1 ; + assign WILL_FIRE_wmiM_sData = 1'b1 ; + + // action method wmiM_sThreadBusy + assign CAN_FIRE_wmiM_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wmiM_sThreadBusy = wmiM_SThreadBusy ; + + // action method wmiM_sDataThreadBusy + assign CAN_FIRE_wmiM_sDataThreadBusy = 1'b1 ; + assign WILL_FIRE_wmiM_sDataThreadBusy = wmiM_SDataThreadBusy ; + + // action method wmiM_sRespLast + assign CAN_FIRE_wmiM_sRespLast = 1'b1 ; + assign WILL_FIRE_wmiM_sRespLast = wmiM_SRespLast ; + + // action method wmiM_sFlag + assign CAN_FIRE_wmiM_sFlag = 1'b1 ; + assign WILL_FIRE_wmiM_sFlag = 1'b1 ; + + // value method wmiM_mFlag + assign wmiM_MFlag = wmi_sThreadBusy_d ? 32'b00000000000000000000000000000000 : wmi_mFlagF_q_0 ; + + // value method wmiM_mReset_n + assign wmiM_MReset_n = !wmi_isReset__VAL && wmi_operateD ; + + // action method wmiM_sReset_n + assign CAN_FIRE_wmiM_sReset_n = 1'b1 ; + assign WILL_FIRE_wmiM_sReset_n = wmiM_SReset_n ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'b000 : wsiM_reqFifo_q_0[60:58] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsiM_sThreadBusy_d ? 12'b000000000000 : wsiM_reqFifo_q_0[55:44] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsiM_reqFifo_q_0[43:12] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsiM_reqFifo_q_0[11:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'b00000000 : wsiM_reqFifo_q_0[7:0] ; + + // action method wsiM1_sThreadBusy + assign CAN_FIRE_wsiM1_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsiM_isReset__VAL && wsiM_operateD ; + + // action method wsiM1_sReset_n + assign CAN_FIRE_wsiM1_sReset_n = 1'b1 ; + assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ; + + // action method wsiS1_mCmd + assign CAN_FIRE_wsiS1_mCmd = 1'b1 ; + assign WILL_FIRE_wsiS1_mCmd = 1'b1 ; + + // action method wsiS1_mReqLast + assign CAN_FIRE_wsiS1_mReqLast = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ; + + // action method wsiS1_mBurstPrecise + assign CAN_FIRE_wsiS1_mBurstPrecise = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ; + + // action method wsiS1_mBurstLength + assign CAN_FIRE_wsiS1_mBurstLength = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstLength = 1'b1 ; + + // action method wsiS1_mData + assign CAN_FIRE_wsiS1_mData = 1'b1 ; + assign WILL_FIRE_wsiS1_mData = 1'b1 ; + + // action method wsiS1_mByteEn + assign CAN_FIRE_wsiS1_mByteEn = 1'b1 ; + assign WILL_FIRE_wsiS1_mByteEn = 1'b1 ; + + // action method wsiS1_mReqInfo + assign CAN_FIRE_wsiS1_mReqInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqInfo = 1'b1 ; + + // action method wsiS1_mDataInfo + assign CAN_FIRE_wsiS1_mDataInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mDataInfo = 1'b1 ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsiS_isReset__VAL && wsiS_operateD ; + + // action method wsiS1_mReset_n + assign CAN_FIRE_wsiS1_mReset_n = 1'b1 ; + assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ; + + // submodule wci_isReset + ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset__VAL)); + + +wire full_not_used; + // submodule wci_reqF + SizedFIFO_a size_fifoA( + + .CLK(wciS0_Clk), + .D_IN(wci_reqF__D_IN), + .ENQ(wci_reqF__ENQ), + .DEQ(wci_reqF__DEQ), + .CLR(wci_reqF__CLR), + .D_OUT(wci_reqF__D_OUT), + .FULL_N(full_not_used), + .EMPTY_N(wci_reqF__EMPTY_N) + ); + +wire dummy1; +assign dummy1 = &wci_reqF__D_OUT; +assign prevent_sweep_node = dummy1 & dummy2 & dummy3; + + // submodule wmi_isReset + ResetToBool wmi_isReset(.RST(wciS0_MReset_n), .VAL(wmi_isReset__VAL)); + + // submodule wmi_respF + //34 width + SizedFIFO_b size_fifoB ( + .CLK(wciS0_Clk), + .D_IN(wmi_respF__D_IN), + .ENQ(wmi_respF__ENQ), + .DEQ(wmi_respF__DEQ), + .CLR(wmi_respF__CLR), + .D_OUT(wmi_respF__D_OUT), + .FULL_N(wmi_respF__FULL_N), + .EMPTY_N(wmi_respF__EMPTY_N) + ); +wire dummy2; +assign dummy2 = &wmi_respF__D_OUT; + + // submodule wsiM_isReset + ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset__VAL)); + + // submodule wsiS_isReset + ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset__VAL)); + + // submodule wsiS_reqFifo + // SizedFIFO #(.p1width(32'd61), +// .p2depth(32'd3), + // .p3cntr_width(32'b00000000000000000000000000000001), + // .guarded(32'b00000000000000000000000000000001)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + + + SizedFIFO_c size_fifoc( + + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo__D_IN), + .ENQ(wsiS_reqFifo__ENQ), + .DEQ(wsiS_reqFifo__DEQ), + .CLR(wsiS_reqFifo__CLR), + .D_OUT(wsiS_reqFifo__D_OUT), + .FULL_N(wsiS_reqFifo__FULL_N), + .EMPTY_N(wsiS_reqFifo__EMPTY_N) + ); + +wire dummy3; +assign dummy3 = &wsiS_reqFifo__D_OUT; + + + // rule RL_wci_request_decode + assign CAN_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + assign WILL_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + + // rule RL_wsiS_ext_status_assign + assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + + // rule RL_wsiM_ext_status_assign + assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + + // rule RL_wci_cfrd + assign CAN_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfrd_pw__whas ; + assign WILL_FIRE_RL_wci_cfrd = + CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wmrd_mesgBodyRequest + assign CAN_FIRE_RL_wmrd_mesgBodyRequest = + NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + mesgPreRequest ; + assign WILL_FIRE_RL_wmrd_mesgBodyRequest = + CAN_FIRE_RL_wmrd_mesgBodyRequest ; + + // rule RL_wmrd_mesgBodyPreRequest + assign CAN_FIRE_RL_wmrd_mesgBodyPreRequest = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + fabWordsRemain != 14'b00000000000000 && + (fabRespCredit_value ^ 4'h8) > 4'b1000 && + mesgReqOK ; + assign WILL_FIRE_RL_wmrd_mesgBodyPreRequest = + CAN_FIRE_RL_wmrd_mesgBodyPreRequest && + !WILL_FIRE_RL_wmrd_mesgBodyRequest ; + + // rule RL_wmrd_mesgBegin + assign CAN_FIRE_RL_wmrd_mesgBegin = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ; + + // rule RL_wci_ctl_op_start + assign CAN_FIRE_RL_wci_ctl_op_start = + wci_reqF__EMPTY_N && wci_wci_ctrl_pw__whas ; + assign WILL_FIRE_RL_wci_ctl_op_start = + CAN_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign CAN_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b000 && + wci_reqF__D_OUT[36:34] == 3'b000 ; + assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ; + + // rule RL_wci_ctrl_OrE + assign CAN_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b010 && + wci_reqF__D_OUT[36:34] == 3'b011 ; + assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ; + + // rule RL_wci_respF_deq + assign CAN_FIRE_RL_wci_respF_deq = 1'b1 ; + assign WILL_FIRE_RL_wci_respF_deq = 1'b1 ; + + // rule RL_wci_sThreadBusy_reg + assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + + // rule RL_wci_sFlagReg__dreg_update + assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + + // rule RL_wsi_Es_doAlways + assign CAN_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + + // rule RL_wsiS_update_statusR + assign CAN_FIRE_RL_wsiS_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiS_update_statusR = 1'b1 ; + + // rule RL_wsiS_inc_tBusyCount + assign CAN_FIRE_RL_wsiS_inc_tBusyCount = + wsiS_operateD && wsiS_peerIsReady && + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 ; + assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // rule RL_wsiS_reqFifo_enq + assign CAN_FIRE_RL_wsiS_reqFifo_enq = + wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq__wget[60:58] == 3'b001 ; + assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // rule RL_wsiS_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wsiM_update_statusR + assign CAN_FIRE_RL_wsiM_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiM_update_statusR = 1'b1 ; + + // rule RL_wsiM_inc_tBusyCount + assign CAN_FIRE_RL_wsiM_inc_tBusyCount = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // rule RL_wsiM_reqFifo_deq + assign CAN_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'b00 && !wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_sThreadBusy_reg + assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + + // rule RL_wsiM_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_operating_actions + assign CAN_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + assign WILL_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + + // rule RL_wsiS_operateD__dreg_update + assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + + // rule RL_wsiM_operateD__dreg_update + assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + + // rule RL_wmrd_mesgBodyResponse + assign CAN_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF__EMPTY_N && (smaCtrl[4] || wsiM_reqFifo_c_r != 2'b10) && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // rule RL_wmwt_messagePushImprecise + assign CAN_FIRE_RL_wmwt_messagePushImprecise = + wmi_reqF_c_r != 2'b10 && wmi_dhF_c_r != 2'b10 && + wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + readyToPush && + impreciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushImprecise = + CAN_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_messagePushPrecise + assign CAN_FIRE_RL_wmwt_messagePushPrecise = + wmi_dhF_c_r != 2'b10 && wsiS_reqFifo__EMPTY_N && wmi_operateD && + wmi_peerIsReady && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + wsiWordsRemain != 12'b000000000000 && + mesgReqValid && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushPrecise = + CAN_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_requestPrecise + assign CAN_FIRE_RL_wmwt_requestPrecise = + wmi_reqF_c_r != 2'b10 && wmi_mFlagF_c_r != 2'b10 && wmi_operateD && + wmi_peerIsReady && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + readyToRequest && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_requestPrecise = + CAN_FIRE_RL_wmwt_requestPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // rule RL_wmwt_messageFinalize + assign CAN_FIRE_RL_wmwt_messageFinalize = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + mesgLength[14] && + !doAbort && + (preciseBurst && wsiWordsRemain == 12'b000000000000 || + impreciseBurst && endOfMessage) ; + assign WILL_FIRE_RL_wmwt_messageFinalize = + CAN_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_mesgBegin + assign CAN_FIRE_RL_wmwt_mesgBegin = + wsiS_reqFifo__EMPTY_N && wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + !opcode[8] ; + assign WILL_FIRE_RL_wmwt_mesgBegin = + CAN_FIRE_RL_wmwt_mesgBegin && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_doAbort + assign CAN_FIRE_RL_wmwt_doAbort = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + doAbort ; + assign WILL_FIRE_RL_wmwt_doAbort = CAN_FIRE_RL_wmwt_doAbort ; + + // rule RL_wmi_Em_doAlways + assign CAN_FIRE_RL_wmi_Em_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wmi_Em_doAlways = 1'b1 ; + + // rule RL_wci_Es_doAlways_Req + assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + + // rule RL_wci_reqF_enq + assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq__wget[59:57] != 3'b000 ; + assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ; + + // rule RL_wsipass_doMessagePush + assign CAN_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo__EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'b10) && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h0 || smaCtrl[3:0] == 4'h3) ; + assign WILL_FIRE_RL_wsipass_doMessagePush = + CAN_FIRE_RL_wsipass_doMessagePush && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // rule RL_wci_cfwr + assign CAN_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfwr_pw__whas ; + assign WILL_FIRE_RL_wci_cfwr = + CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_reqF__updateLevelCounter + assign CAN_FIRE_RL_wci_reqF__updateLevelCounter = + (wci_wciReq__wget[59:57] != 3'b000) != wci_reqF_r_deq__whas ; + assign WILL_FIRE_RL_wci_reqF__updateLevelCounter = + CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // rule RL_wsiS_reqFifo__updateLevelCounter + assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq__whas ; + assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // rule RL_wsiM_reqFifo_both + assign CAN_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'b01) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b10 || wsiM_reqFifo_x_wire__whas) && + CAN_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ; + + // rule RL_wsiM_reqFifo_decCtr + assign CAN_FIRE_RL_wsiM_reqFifo_decCtr = + CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ; + + // rule RL_wsiM_reqFifo_incCtr + assign CAN_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'b00) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b01 || wsiM_reqFifo_x_wire__whas) && + wsiM_reqFifo_enqueueing__whas && + !CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ; + + // rule RL_mesgPreRequest__dreg_update + assign CAN_FIRE_RL_mesgPreRequest__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_mesgPreRequest__dreg_update = 1'b1 ; + + // rule RL_fabRespCredit_accumulate + assign CAN_FIRE_RL_fabRespCredit_accumulate = 1'b1 ; + assign WILL_FIRE_RL_fabRespCredit_accumulate = 1'b1 ; + + // rule RL_wci_ctrl_IsO + assign CAN_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b001 && + wci_reqF__D_OUT[36:34] == 3'b001 ; + assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ; + + // rule RL_wci_ctl_op_complete + assign CAN_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'b10 && wci_ctlOpActive && wci_ctlAckReg ; + assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctlAckReg__dreg_update + assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + + // rule RL_wci_respF_both + assign CAN_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'b01) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b10 || wci_respF_x_wire__whas) && + wci_respF_c_r != 2'b00 && + wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ; + + // rule RL_wci_respF_decCtr + assign CAN_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'b00 && !wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ; + + // rule RL_wci_respF_incCtr + assign CAN_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'b00) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b01 || wci_respF_x_wire__whas) && + wci_respF_enqueueing__whas && + !(wci_respF_c_r != 2'b00) ; + assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ; + + // rule RL_wmi_dhF_deq + assign CAN_FIRE_RL_wmi_dhF_deq = !wmi_sDataThreadBusy_d ; + assign WILL_FIRE_RL_wmi_dhF_deq = CAN_FIRE_RL_wmi_dhF_deq ; + + // rule RL_wmi_respAdvance + assign CAN_FIRE_RL_wmi_respAdvance = + wmi_respF__FULL_N && wmi_operateD && wmi_peerIsReady && + wmi_wmiResponse__wget[33:32] != 2'b00 ; + assign WILL_FIRE_RL_wmi_respAdvance = CAN_FIRE_RL_wmi_respAdvance ; + + // rule RL_wmi_reqF_deq + assign CAN_FIRE_RL_wmi_reqF_deq = !wmi_sThreadBusy_d ; + assign WILL_FIRE_RL_wmi_reqF_deq = CAN_FIRE_RL_wmi_reqF_deq ; + + // rule RL_wmi_peerIsReady__dreg_update + assign CAN_FIRE_RL_wmi_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wmi_operateD__dreg_update + assign CAN_FIRE_RL_wmi_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_operateD__dreg_update = 1'b1 ; + + // rule RL_wmi_sDataThreadBusy_d__dreg_update + assign CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'b1 ; + + // rule RL_wmi_sThreadBusy_d__dreg_update + assign CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'b1 ; + + // rule RL_wmi_dhF_decCtr + assign CAN_FIRE_RL_wmi_dhF_decCtr = + wmi_dhF_dequeueing__whas && !wmi_dhF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_decCtr = CAN_FIRE_RL_wmi_dhF_decCtr ; + + // rule RL_wmi_dhF_both + assign CAN_FIRE_RL_wmi_dhF_both = + ((wmi_dhF_c_r == 2'b01) ? + wmi_dhF_enqueueing__whas : + wmi_dhF_c_r != 2'b10 || wmi_dhF_enqueueing__whas) && + wmi_dhF_dequeueing__whas && + wmi_dhF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_both = CAN_FIRE_RL_wmi_dhF_both ; + + // rule RL_wmi_dhF_incCtr + assign CAN_FIRE_RL_wmi_dhF_incCtr = + ((wmi_dhF_c_r == 2'b00) ? + wmi_dhF_enqueueing__whas : + wmi_dhF_c_r != 2'b01 || wmi_dhF_enqueueing__whas) && + wmi_dhF_enqueueing__whas && + !wmi_dhF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_incCtr = CAN_FIRE_RL_wmi_dhF_incCtr ; + + // rule RL_wmi_mFlagF_both + assign CAN_FIRE_RL_wmi_mFlagF_both = + ((wmi_mFlagF_c_r == 2'b01) ? + wmi_mFlagF_enqueueing__whas : + wmi_mFlagF_c_r != 2'b10 || wmi_mFlagF_enqueueing__whas) && + wmi_mFlagF_dequeueing__whas && + wmi_mFlagF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_both = CAN_FIRE_RL_wmi_mFlagF_both ; + + // rule RL_wmi_mFlagF_decCtr + assign CAN_FIRE_RL_wmi_mFlagF_decCtr = + wmi_mFlagF_dequeueing__whas && !wmi_mFlagF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_decCtr = CAN_FIRE_RL_wmi_mFlagF_decCtr ; + + // rule RL_wmi_mFlagF_incCtr + assign CAN_FIRE_RL_wmi_mFlagF_incCtr = + ((wmi_mFlagF_c_r == 2'b00) ? + wmi_mFlagF_enqueueing__whas : + wmi_mFlagF_c_r != 2'b01 || wmi_mFlagF_enqueueing__whas) && + wmi_mFlagF_enqueueing__whas && + !wmi_mFlagF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_incCtr = CAN_FIRE_RL_wmi_mFlagF_incCtr ; + + // rule RL_wmi_reqF_both + assign CAN_FIRE_RL_wmi_reqF_both = + ((wmi_reqF_c_r == 2'b01) ? + wmi_reqF_x_wire__whas : + wmi_reqF_c_r != 2'b10 || wmi_reqF_x_wire__whas) && + wmi_reqF_dequeueing__whas && + wmi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_both = CAN_FIRE_RL_wmi_reqF_both ; + + // rule RL_wmi_reqF_incCtr + assign CAN_FIRE_RL_wmi_reqF_incCtr = + ((wmi_reqF_c_r == 2'b00) ? + wmi_reqF_x_wire__whas : + wmi_reqF_c_r != 2'b01 || wmi_reqF_x_wire__whas) && + wmi_reqF_enqueueing__whas && + !wmi_reqF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_incCtr = CAN_FIRE_RL_wmi_reqF_incCtr ; + + // rule RL_wmi_reqF_decCtr + assign CAN_FIRE_RL_wmi_reqF_decCtr = + wmi_reqF_dequeueing__whas && !wmi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_decCtr = CAN_FIRE_RL_wmi_reqF_decCtr ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge__write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge__write_1__VAL_2 = + wci_reqF__D_OUT[36:34] != 3'b100 && wci_reqF__D_OUT[36:34] != 3'b101 && + wci_reqF__D_OUT[36:34] != 3'b110 ; + assign MUX_wci_respF_c_r__write_1__VAL_1 = wci_respF_c_r - 2'b01 ; + assign MUX_wci_respF_c_r__write_1__VAL_2 = wci_respF_c_r + 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_illegalEdge__write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState != 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && wci_cState != 3'b001 && + wci_cState != 3'b011 || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState != 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && wci_cState != 3'b011 && + wci_cState != 3'b010 && + wci_cState != 3'b001 || + wci_reqF__D_OUT[36:34] == 3'b100 || + wci_reqF__D_OUT[36:34] == 3'b101 || + wci_reqF__D_OUT[36:34] == 3'b110 || + wci_reqF__D_OUT[36:34] == 3'b111) ; + assign MUX_wci_respF_q_0__write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 ; + assign MUX_wci_respF_q_1__write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_1 = wsiM_reqFifo_c_r - 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_2 = wsiM_reqFifo_c_r + 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_2 = { 2'b01, x_data__h15447 } ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0__write_1__VAL_1 = + MUX_wci_respF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0__write_1__VAL_1 = + MUX_wci_respF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0__write_1__VAL_1 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0__write_1__VAL_1 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_0__write_1__VAL_2 = + (wci_respF_c_r == 2'b01) ? + MUX_wci_respF_q_0__write_1__VAL_1 : + wci_respF_q_1 ; + assign MUX_wci_respF_q_1__write_1__VAL_2 = + (wci_respF_c_r == 2'b10) ? + MUX_wci_respF_q_0__write_1__VAL_1 : + 34'h0AAAAAAAA ; + assign MUX_wsiM_reqFifo_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 ; + assign MUX_wsiM_reqFifo_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 ; + assign MUX_endOfMessage__write_1__SEL_1 = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ; + assign MUX_impreciseBurst__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] ; + assign MUX_lastMesg__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_requestPrecise || WILL_FIRE_RL_wmrd_mesgBegin ; + assign MUX_mesgCount__write_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 ; + assign MUX_mesgLength__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] ; + assign MUX_wmi_mFlagF_x_wire__wset_1__SEL_2 = + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18884 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; + assign MUX_fabRespCredit_value__write_1__VAL_2 = + fabRespCredit_value + + (CAN_FIRE_RL_wmrd_mesgBodyRequest ? b__h13937 : 4'b0000) + + (CAN_FIRE_RL_wmrd_mesgBodyResponse ? 4'b0001 : 4'b0000) ; + assign MUX_fabWordsRemain__write_1__VAL_1 = + (wmi_sFlagReg[23:0] == 24'b000000000000000000000000) ? 14'b00000000000001 : wmi_sFlagReg[15:2] ; + assign MUX_fabWordsRemain__write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; + assign MUX_mesgCount__write_1__VAL_1 = mesgCount + 32'b00000000000000000000000000000001 ; + assign MUX_mesgLength__write_1__VAL_2 = + (wsiS_reqFifo__D_OUT[11:8] == 4'b0000) ? + 15'b100000000000000 : + { 1'b1, wsiS_reqFifo__D_OUT[55:44], 2'b00 } ; + assign MUX_mesgLength__write_1__VAL_4 = { 1'b1, mlp1B__h16631 } ; + assign MUX_mesgReqAddr__write_1__VAL_2 = + mesgReqAddr + { fabWordsCurReq[11:0], 2'b00 } ; + assign MUX_opcode__write_1__VAL_2 = { 1'b1, wsiS_reqFifo__D_OUT[7:0] } ; + assign MUX_thisMesg__write_1__VAL_1 = + { mesgCount[7:0], mesgMetaF_opcode__h16809, x_length__h17087 } ; + assign MUX_thisMesg__write_1__VAL_2 = + { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; + assign MUX_unrollCnt__write_1__VAL_2 = unrollCnt - 16'b0000000000000001 ; + assign MUX_unrollCnt__write_1__VAL_1 = + (wmi_sFlagReg[23:0] == 24'b000000000000000000000000) ? 16'b0000000000000001 : wmi_sFlagReg[17:2] ; + assign MUX_wmi_dhF_c_r__write_1__VAL_1 = wmi_dhF_c_r - 2'b01 ; + assign MUX_wmi_dhF_c_r__write_1__VAL_2 = wmi_dhF_c_r + 2'b01 ; + assign MUX_wmi_dhF_x_wire__wset_1__VAL_1 = + { 1'b1, + wsiWordsRemain == 12'b000000000001, + wsiS_reqFifo__D_OUT[43:12], + 4'b1111 } ; + assign MUX_wmi_dhF_x_wire__wset_1__VAL_2 = + { 1'b1, x__h16715, wsiS_reqFifo__D_OUT[43:12], 4'b1111 } ; + assign MUX_wmi_dhF_q_0__write_1__VAL_2 = + WILL_FIRE_RL_wmwt_messagePushPrecise ? + MUX_wmi_dhF_x_wire__wset_1__VAL_1 : + MUX_wmi_dhF_x_wire__wset_1__VAL_2 ; + assign MUX_wmi_dhF_q_0__write_1__VAL_1 = + (wmi_dhF_c_r == 2'b01) ? + MUX_wmi_dhF_q_0__write_1__VAL_2 : + wmi_dhF_q_1 ; + assign MUX_wmi_dhF_q_1__write_1__VAL_1 = + (wmi_dhF_c_r == 2'b10) ? + MUX_wmi_dhF_q_0__write_1__VAL_2 : + 38'h0AAAAAAAAA ; + assign MUX_wmi_mFlagF_c_r__write_1__VAL_1 = wmi_mFlagF_c_r - 2'b01 ; + assign MUX_wmi_mFlagF_c_r__write_1__VAL_2 = wmi_mFlagF_c_r + 2'b01 ; + assign MUX_wmi_mFlagF_x_wire__wset_1__VAL_1 = + { mesgMetaF_opcode__h16809, mesgMetaF_length__h16810 } ; + assign MUX_wmi_mFlagF_x_wire__wset_1__VAL_3 = + { mesgMetaF_opcode__h16809, mesgMetaF_length__h17723 } ; + assign MUX_wmi_mFlagF_q_0__write_1__VAL_1 = + (wmi_mFlagF_c_r == 2'b01) ? value__h6065 : wmi_mFlagF_q_1 ; + assign MUX_wmi_mFlagF_q_1__write_1__VAL_1 = + (wmi_mFlagF_c_r == 2'b10) ? value__h6065 : 32'b00000000000000000000000000000000 ; + assign MUX_wmi_reqF_c_r__write_1__VAL_1 = wmi_reqF_c_r - 2'b01 ; + assign MUX_wmi_reqF_c_r__write_1__VAL_2 = wmi_reqF_c_r + 2'b01 ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_1 = { 20'b00111000000000000000, bl__h17580 } ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_2 = + { 4'b0101, x__h18884, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_3 = + { 4'b0011, x__h16715, 1'b0, addr__h16647, 12'b000000000001 } ; + always@(WILL_FIRE_RL_wmwt_requestPrecise or + MUX_wmi_reqF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wmrd_mesgBodyRequest or + MUX_wmi_reqF_x_wire__wset_1__VAL_2 or + WILL_FIRE_RL_wmwt_messagePushImprecise or + MUX_wmi_reqF_x_wire__wset_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmwt_requestPrecise: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wmrd_mesgBodyRequest: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wmwt_messagePushImprecise: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_3; + default: MUX_wmi_reqF_q_0__write_1__VAL_1 = + 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wmi_reqF_q_0__write_1__VAL_2 = + (wmi_reqF_c_r == 2'b01) ? + MUX_wmi_reqF_q_0__write_1__VAL_1 : + wmi_reqF_q_1 ; + assign MUX_wmi_reqF_q_1__write_1__VAL_2 = + (wmi_reqF_c_r == 2'b10) ? + MUX_wmi_reqF_q_0__write_1__VAL_1 : + 32'b00001010101010101010101010101010 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 = + { 3'b001, + unrollCnt == 16'b0000000000000001, + !smaCtrl[5], + x_burstLength__h18559, + wmi_respF__D_OUT[31:0], + x_byteEn__h18561, + thisMesg[23:16] } ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_2 = + MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1 ? + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 : + wsiS_reqFifo__D_OUT ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b01) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b10) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + assign MUX_wsiWordsRemain__write_1__VAL_2 = wsiWordsRemain - 12'b000000000001 ; + assign MUX_wmi_reqF_q_0__write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b00 ; + assign MUX_wmi_reqF_q_1__write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b01 ; + assign MUX_wmi_mFlagF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b00 ; + assign MUX_wmi_mFlagF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b01 ; + assign MUX_wmi_dhF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b00 ; + assign MUX_wmi_dhF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b01 ; + + // inlined wires + assign wci_wciReq__wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq__whas = 1'b1 ; + assign wci_reqF_r_enq__whas = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF_r_clr__whas = 1'b0 ; + assign wci_respF_dequeueing__whas = wci_respF_c_r != 2'b00 ; + assign wci_wEdge__wget = wci_reqF__D_OUT[36:34] ; + assign wci_sThreadBusy_pw__whas = 1'b0 ; + assign wci_sFlagReg_1__wget = 1'b0 ; + assign wci_sFlagReg_1__whas = 1'b0 ; + assign wci_wci_cfwr_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b001 ; + assign wci_wci_cfrd_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_wci_ctrl_pw__whas = + wci_reqF__EMPTY_N && !wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_reqF_r_deq__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_respF_enqueueing__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_respF_x_wire__whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_ctlAckReg_1__wget = 1'b1 ; + assign wci_wEdge__whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_ctlAckReg_1__whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiM_reqFifo_dequeueing__whas = CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw__whas = wsiM1_SThreadBusy ; + assign wsiM_operateD_1__wget = 1'b1 ; + assign wsiM_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiM_peerIsReady_1__wget = 1'b1 ; + assign wsiM_peerIsReady_1__whas = wsiM1_SReset_n ; + assign wsiM_extStatusW__wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + assign wsiS_wsiReq__wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsiS_wsiReq__whas = 1'b1 ; + assign wsiS_reqFifo_r_enq__whas = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_clr__whas = 1'b0 ; + assign wsiS_operateD_1__wget = 1'b1 ; + assign wsiS_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiS_peerIsReady_1__wget = 1'b1 ; + assign wsiS_extStatusW__wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiS_peerIsReady_1__whas = wsiS1_MReset_n ; + assign wsi_Es_mCmd_w__wget = wsiS1_MCmd ; + assign wsi_Es_mReqLast_w__whas = wsiS1_MReqLast ; + assign wsi_Es_mCmd_w__whas = 1'b1 ; + assign wsi_Es_mBurstPrecise_w__whas = wsiS1_MBurstPrecise ; + assign wsi_Es_mBurstLength_w__whas = 1'b1 ; + assign wsi_Es_mBurstLength_w__wget = wsiS1_MBurstLength ; + assign wsi_Es_mData_w__wget = wsiS1_MData ; + assign wsi_Es_mData_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__wget = wsiS1_MByteEn ; + assign wsi_Es_mByteEn_w__whas = 1'b1 ; + assign wsi_Es_mReqInfo_w__whas = 1'b1 ; + assign wsi_Es_mReqInfo_w__wget = wsiS1_MReqInfo ; + assign wsi_Es_mDataInfo_w__whas = 1'b1 ; + assign wci_respF_x_wire__wget = MUX_wci_respF_q_0__write_1__VAL_1 ; + assign wsiM_reqFifo_enqueueing__whas = + (WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmrd_mesgBodyResponse) && + !smaCtrl[4] ; + assign wsiM_reqFifo_x_wire__whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign wsiS_reqFifo_r_deq__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wsiM_reqFifo_x_wire__wget = MUX_wsiM_reqFifo_q_0__write_1__VAL_2 ; + assign wmi_reqF_enqueueing__whas = + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise || + WILL_FIRE_RL_wmrd_mesgBodyRequest ; + assign wmi_reqF_x_wire__wget = MUX_wmi_reqF_q_0__write_1__VAL_1 ; + assign wmi_reqF_x_wire__whas = + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmrd_mesgBodyRequest || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wmi_reqF_dequeueing__whas = + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'b00 ; + assign wmi_mFlagF_x_wire__wget = value__h6065 ; + assign wmi_mFlagF_enqueueing__whas = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18884 || + WILL_FIRE_RL_wmwt_requestPrecise ; + assign wmi_mFlagF_x_wire__whas = wmi_mFlagF_enqueueing__whas ; + assign wmi_mFlagF_dequeueing__whas = + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && + wmi_mFlagF_c_r != 2'b00 ; + assign wmi_dhF_enqueueing__whas = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wmi_dhF_x_wire__wget = MUX_wmi_dhF_q_0__write_1__VAL_2 ; + assign wmi_dhF_x_wire__whas = wmi_dhF_enqueueing__whas ; + assign wmi_dhF_dequeueing__whas = + WILL_FIRE_RL_wmi_dhF_deq && wmi_dhF_c_r != 2'b00 ; + assign wmi_wmiResponse__wget = { wmiM_SResp, wmiM_SData } ; + assign wmi_wmiResponse__whas = 1'b1 ; + assign wmi_sThreadBusy_d_1__wget = 1'b1 ; + assign wmi_sThreadBusy_d_1__whas = wmiM_SThreadBusy ; + assign wmi_sDataThreadBusy_d_1__wget = 1'b1 ; + assign wmi_operateD_1__wget = 1'b1 ; + assign wmi_sDataThreadBusy_d_1__whas = wmiM_SDataThreadBusy ; + assign wmi_operateD_1__whas = wci_cState == 3'b010 ; + assign wmi_peerIsReady_1__whas = wmiM_SReset_n ; + assign wmi_peerIsReady_1__wget = 1'b1 ; + assign fabRespCredit_acc_v1__wget = b__h13937 ; + assign fabRespCredit_acc_v2__wget = 4'b0001 ; + assign fabRespCredit_acc_v1__whas = CAN_FIRE_RL_wmrd_mesgBodyRequest ; + assign fabRespCredit_acc_v2__whas = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign mesgPreRequest_1__wget = 1'b1 ; + assign mesgPreRequest_1__whas = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + assign wci_Es_mCmd_w__wget = wciS0_MCmd ; + assign wci_Es_mAddrSpace_w__wget = wciS0_MAddrSpace ; + assign wci_Es_mCmd_w__whas = 1'b1 ; + assign wci_Es_mAddrSpace_w__whas = 1'b1 ; + assign wci_Es_mAddr_w__wget = wciS0_MAddr ; + assign wci_Es_mAddr_w__whas = 1'b1 ; + assign wci_Es_mData_w__wget = wciS0_MData ; + assign wci_Es_mData_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__wget = wciS0_MByteEn ; + assign wmi_Em_sResp_w__wget = wmiM_SResp ; + assign wmi_Em_sResp_w__whas = 1'b1 ; + assign wmi_Em_sData_w__wget = wmiM_SData ; + assign wmi_Em_sData_w__whas = 1'b1 ; + + // register abortCount + assign abortCount__D_IN = abortCount + 32'b00000000000000000000000000000001 ; + assign abortCount__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register doAbort + assign doAbort__D_IN = 1'b0 ; + assign doAbort__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register endOfMessage + assign endOfMessage__D_IN = MUX_endOfMessage__write_1__SEL_1 ; + assign endOfMessage__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_messageFinalize ; + + // register errCount + assign errCount__D_IN = errCount + 32'b00000000000000000000000000000001 ; + assign errCount__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[43:12] != valExpect && + (!x__h16715 || wsiS_reqFifo__D_OUT[11:8] != 4'b0000) ; + + // register fabRespCredit_value + assign fabRespCredit_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 4'b0010 : + MUX_fabRespCredit_value__write_1__VAL_2 ; + assign fabRespCredit_value__EN = 1'b1 ; + + // register fabWordsCurReq + assign fabWordsCurReq__D_IN = + (fabWordsRemain <= b__h19084) ? fabWordsRemain : b__h19084 ; + assign fabWordsCurReq__EN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + + // register fabWordsRemain + assign fabWordsRemain__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_fabWordsRemain__write_1__VAL_1 : + MUX_fabWordsRemain__write_1__VAL_2 ; + assign fabWordsRemain__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyRequest ; + + // register firstMsgReq + assign firstMsgReq__EN = 1'b0 ; + assign firstMsgReq__D_IN = 1'b0 ; + + // register impreciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: impreciseBurst__D_IN = 1'b0; + default: impreciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign impreciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register lastMesg + assign lastMesg__D_IN = + (MUX_endOfMessage__write_1__SEL_1 || + MUX_lastMesg__write_1__SEL_2) ? + thisMesg : + 32'hFEFEFFFE ; + assign lastMesg__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgCount + always@(MUX_mesgCount__write_1__SEL_1 or + MUX_mesgCount__write_1__VAL_1 or + WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) + begin + case (1'b1) // synopsys parallel_case + MUX_mesgCount__write_1__SEL_1: + mesgCount__D_IN = MUX_mesgCount__write_1__VAL_1; + WILL_FIRE_RL_wmwt_messageFinalize: + mesgCount__D_IN = MUX_mesgCount__write_1__VAL_1; + WILL_FIRE_RL_wci_ctrl_IsO: mesgCount__D_IN = 32'b00000000000000000000000000000000; + default: mesgCount__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign mesgCount__EN = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgLength + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or + MUX_mesgLength__write_1__VAL_2 or + WILL_FIRE_RL_wmwt_messageFinalize or + MUX_endOfMessage__write_1__SEL_1 or MUX_mesgLength__write_1__VAL_4) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; + MUX_mesgLength__write_1__SEL_2: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: mesgLength__D_IN = 15'b010101010101010; + MUX_endOfMessage__write_1__SEL_1: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_4; + default: mesgLength__D_IN = 15'b010101010101010 /* unspecified value */ ; + endcase + assign mesgLength__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLengthSoFar + assign mesgLengthSoFar__D_IN = + MUX_impreciseBurst__write_1__SEL_2 ? 14'b00000000000000 : mlp1__h16630 ; + assign mesgLengthSoFar__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // register mesgPreRequest + assign mesgPreRequest__D_IN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + assign mesgPreRequest__EN = 1'b1 ; + + // register mesgReqAddr + assign mesgReqAddr__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + 14'b00000000000000 : + MUX_mesgReqAddr__write_1__VAL_2 ; + assign mesgReqAddr__EN = + WILL_FIRE_RL_wmrd_mesgBodyRequest || + WILL_FIRE_RL_wmrd_mesgBegin ; + + // register mesgReqOK + assign mesgReqOK__D_IN = + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; + assign mesgReqOK__EN = + WILL_FIRE_RL_wmrd_mesgBodyPreRequest || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register mesgReqValid + assign mesgReqValid__D_IN = !WILL_FIRE_RL_wmwt_messageFinalize ; + assign mesgReqValid__EN = + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register opcode + always@(WILL_FIRE_RL_wmwt_doAbort or + WILL_FIRE_RL_wmwt_mesgBegin or + MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; + WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: opcode__D_IN = 9'b010101010; + default: opcode__D_IN = 9'b010101010 /* unspecified value */ ; + endcase + assign opcode__EN = + WILL_FIRE_RL_wmwt_mesgBegin || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register preciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; + MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: preciseBurst__D_IN = 1'b0; + default: preciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign preciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToPush + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + MUX_endOfMessage__write_1__SEL_1) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; + MUX_endOfMessage__write_1__SEL_1: readyToPush__D_IN = 1'b0; + default: readyToPush__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign readyToPush__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToRequest + assign readyToRequest__D_IN = MUX_mesgLength__write_1__SEL_2 ; + assign readyToRequest__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register smaCtrl + assign smaCtrl__D_IN = wci_reqF__D_OUT[31:0] ; + assign smaCtrl__EN = WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[39:32] == 8'h0 ; + + // register thisMesg + always@(MUX_endOfMessage__write_1__SEL_1 or + MUX_thisMesg__write_1__VAL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or + MUX_thisMesg__write_1__VAL_2 or + WILL_FIRE_RL_wmwt_requestPrecise or WILL_FIRE_RL_wci_ctrl_IsO) + begin + case (1'b1) // synopsys parallel_case + MUX_endOfMessage__write_1__SEL_1: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_1; + WILL_FIRE_RL_wmrd_mesgBegin: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_2; + WILL_FIRE_RL_wmwt_requestPrecise: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_1; + WILL_FIRE_RL_wci_ctrl_IsO: thisMesg__D_IN = 32'hFEFEFFFE; + default: thisMesg__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign thisMesg__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register unrollCnt + assign unrollCnt__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_unrollCnt__write_1__VAL_1 : + MUX_unrollCnt__write_1__VAL_2 ; + assign unrollCnt__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register valExpect + assign valExpect__D_IN = valExpect + 32'b00000000000000000000000000000001 ; + assign valExpect__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + (!x__h16715 || wsiS_reqFifo__D_OUT[11:8] != 4'b0000) ; + + // register wci_cEdge + assign wci_cEdge__D_IN = wci_reqF__D_OUT[36:34] ; + assign wci_cEdge__EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState__D_IN = wci_nState ; + assign wci_cState__EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg__D_IN = wci_ctlAckReg_1__whas ; + assign wci_ctlAckReg__EN = 1'b1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive__D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive__EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge__D_IN = + !MUX_wci_illegalEdge__write_1__SEL_1 && + MUX_wci_illegalEdge__write_1__VAL_2 ; + assign wci_illegalEdge__EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge__write_1__SEL_2 ; + + // register wci_nState + always@(wci_reqF__D_OUT) + begin + case (wci_reqF__D_OUT[36:34]) + 3'b000: wci_nState__D_IN = 3'b001; + 3'b001: wci_nState__D_IN = 3'b010; + 3'b010: wci_nState__D_IN = 3'b011; + default: wci_nState__D_IN = 3'b000; + endcase + end + assign wci_nState__EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState == 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && + (wci_cState == 3'b001 || wci_cState == 3'b011) || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState == 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && + (wci_cState == 3'b011 || wci_cState == 3'b010 || + wci_cState == 3'b001)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg__D_IN = + (wci_wciReq__wget[59:57] != 3'b000) ? + wci_reqF_countReg + 2'b01 : + wci_reqF_countReg - 2'b01 ; + assign wci_reqF_countReg__EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // register wci_respF_c_r + assign wci_respF_c_r__D_IN = + WILL_FIRE_RL_wci_respF_decCtr ? + MUX_wci_respF_c_r__write_1__VAL_1 : + MUX_wci_respF_c_r__write_1__VAL_2 ; + assign wci_respF_c_r__EN = + WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ; + + // register wci_respF_q_0 + assign wci_respF_q_0__EN = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(MUX_wci_respF_q_0__write_1__SEL_1 or + MUX_wci_respF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_respF_q_0__write_1__SEL_1: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0__D_IN = wci_respF_q_1; + default: wci_respF_q_0__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_respF_q_1 + assign wci_respF_q_1__EN = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(MUX_wci_respF_q_1__write_1__SEL_1 or + MUX_wci_respF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_respF_q_1__write_1__SEL_1: + wci_respF_q_1__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1__D_IN = MUX_wci_respF_q_1__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1__D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_sFlagReg + assign wci_sFlagReg__D_IN = 1'b0 ; + assign wci_sFlagReg__EN = 1'b1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d__D_IN = 1'b0 ; + assign wci_sThreadBusy_d__EN = 1'b1 ; + + // register wmi_busyWithMessage + assign wmi_busyWithMessage__D_IN = 1'b0 ; + assign wmi_busyWithMessage__EN = 1'b0 ; + + // register wmi_dhF_c_r + assign wmi_dhF_c_r__D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + MUX_wmi_dhF_c_r__write_1__VAL_1 : + MUX_wmi_dhF_c_r__write_1__VAL_2 ; + assign wmi_dhF_c_r__EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; + + // register wmi_dhF_q_0 + always@(WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_0__write_1__VAL_1 or + MUX_wmi_dhF_q_0__write_1__SEL_2 or + MUX_wmi_dhF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_dhF_both: + wmi_dhF_q_0__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_1; + MUX_wmi_dhF_q_0__write_1__SEL_2: + wmi_dhF_q_0__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0__D_IN = wmi_dhF_q_1; + default: wmi_dhF_q_0__D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_dhF_q_0__EN = + WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_dhF_decCtr ; + + // register wmi_dhF_q_1 + always@(WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_1__write_1__VAL_1 or + MUX_wmi_dhF_q_1__write_1__SEL_2 or + MUX_wmi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_dhF_both: + wmi_dhF_q_1__D_IN = MUX_wmi_dhF_q_1__write_1__VAL_1; + MUX_wmi_dhF_q_1__write_1__SEL_2: + wmi_dhF_q_1__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1__D_IN = 38'h0AAAAAAAAA; + default: wmi_dhF_q_1__D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_dhF_q_1__EN = + WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_dhF_decCtr ; + + // register wmi_mFlagF_c_r + assign wmi_mFlagF_c_r__D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + MUX_wmi_mFlagF_c_r__write_1__VAL_1 : + MUX_wmi_mFlagF_c_r__write_1__VAL_2 ; + assign wmi_mFlagF_c_r__EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; + + // register wmi_mFlagF_q_0 + always@(WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_0__write_1__VAL_1 or + MUX_wmi_mFlagF_q_0__write_1__SEL_2 or + value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_mFlagF_both: + wmi_mFlagF_q_0__D_IN = MUX_wmi_mFlagF_q_0__write_1__VAL_1; + MUX_wmi_mFlagF_q_0__write_1__SEL_2: wmi_mFlagF_q_0__D_IN = value__h6065; + WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0__D_IN = wmi_mFlagF_q_1; + default: wmi_mFlagF_q_0__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_mFlagF_q_0__EN = + WILL_FIRE_RL_wmi_mFlagF_both || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_mFlagF_decCtr ; + + // register wmi_mFlagF_q_1 + always@(WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_1__write_1__VAL_1 or + MUX_wmi_mFlagF_q_1__write_1__SEL_2 or + value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_mFlagF_both: + wmi_mFlagF_q_1__D_IN = MUX_wmi_mFlagF_q_1__write_1__VAL_1; + MUX_wmi_mFlagF_q_1__write_1__SEL_2: wmi_mFlagF_q_1__D_IN = value__h6065; + WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1__D_IN = 32'b00000000000000000000000000000000; + default: wmi_mFlagF_q_1__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_mFlagF_q_1__EN = + WILL_FIRE_RL_wmi_mFlagF_both || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_mFlagF_decCtr ; + + // register wmi_operateD + assign wmi_operateD__D_IN = wci_cState == 3'b010 ; + assign wmi_operateD__EN = 1'b1 ; + + // register wmi_peerIsReady + assign wmi_peerIsReady__D_IN = wmiM_SReset_n ; + assign wmi_peerIsReady__EN = 1'b1 ; + + // register wmi_reqF_c_r + assign wmi_reqF_c_r__D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + MUX_wmi_reqF_c_r__write_1__VAL_1 : + MUX_wmi_reqF_c_r__write_1__VAL_2 ; + assign wmi_reqF_c_r__EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; + + // register wmi_reqF_q_0 + always@(MUX_wmi_reqF_q_0__write_1__SEL_1 or + MUX_wmi_reqF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wmi_reqF_both or + MUX_wmi_reqF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmi_reqF_q_0__write_1__SEL_1: + wmi_reqF_q_0__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wmi_reqF_both: + wmi_reqF_q_0__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_0__D_IN = wmi_reqF_q_1; + default: wmi_reqF_q_0__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_reqF_q_0__EN = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_reqF_both || + WILL_FIRE_RL_wmi_reqF_decCtr ; + + // register wmi_reqF_q_1 + always@(MUX_wmi_reqF_q_1__write_1__SEL_1 or + MUX_wmi_reqF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wmi_reqF_both or + MUX_wmi_reqF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmi_reqF_q_1__write_1__SEL_1: + wmi_reqF_q_1__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wmi_reqF_both: + wmi_reqF_q_1__D_IN = MUX_wmi_reqF_q_1__write_1__VAL_2; + WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_1__D_IN = 32'b00001010101010101010101010101010; + default: wmi_reqF_q_1__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_reqF_q_1__EN = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_reqF_both || + WILL_FIRE_RL_wmi_reqF_decCtr ; + + // register wmi_sDataThreadBusy_d + assign wmi_sDataThreadBusy_d__D_IN = wmiM_SDataThreadBusy ; + assign wmi_sDataThreadBusy_d__EN = 1'b1 ; + + // register wmi_sFlagReg + assign wmi_sFlagReg__D_IN = wmiM_SFlag ; + assign wmi_sFlagReg__EN = 1'b1 ; + + // register wmi_sThreadBusy_d + assign wmi_sThreadBusy_d__D_IN = wmiM_SThreadBusy ; + assign wmi_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_burstKind + assign wsiM_burstKind__D_IN = + (wsiM_burstKind == 2'b00) ? + (wsiM_reqFifo_q_0[56] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiM_burstKind__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + (wsiM_burstKind == 2'b00 || + wsiM_burstKind == 2'b01 && wsiM_reqFifo_q_0[57] || + wsiM_burstKind == 2'b10 && wsiM_reqFifo_q_0[55:44] == 12'b000000000001) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky__D_IN = 1'b0 ; + assign wsiM_errorSticky__EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount__D_IN = wsiM_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_iMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + wsiM_burstKind == 2'b10 && + wsiM_reqFifo_q_0[55:44] == 12'b000000000001 ; + + // register wsiM_operateD + assign wsiM_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiM_operateD__EN = 1'b1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount__D_IN = wsiM_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_pMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + wsiM_burstKind == 2'b01 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady__D_IN = wsiM1_SReset_n ; + assign wsiM_peerIsReady__EN = 1'b1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r__D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_c_r__write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r__write_1__VAL_2 ; + assign wsiM_reqFifo_c_r__EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; + + // register wsiM_reqFifo_q_0 + assign wsiM_reqFifo_q_0__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_1; + MUX_wsiM_reqFifo_q_0__write_1__SEL_2: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0__D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0__D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_reqFifo_q_1 + assign wsiM_reqFifo_q_1__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_1__write_1__VAL_1; + MUX_wsiM_reqFifo_q_1__write_1__SEL_2: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1__D_IN = 61'h00000AAAAAAAAA00; + default: wsiM_reqFifo_q_1__D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d__D_IN = wsiM1_SThreadBusy ; + assign wsiM_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_statusR + assign wsiM_statusR__D_IN = + { wsiM_isReset__VAL, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'b00, + wsiM_sThreadBusy_d, + 1'b0, + wsiM_trafficSticky } ; + assign wsiM_statusR__EN = 1'b1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount__D_IN = wsiM_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiM_tBusyCount__EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky__D_IN = 1'b1 ; + assign wsiM_trafficSticky__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 ; + + // register wsiS_burstKind + assign wsiS_burstKind__D_IN = + (wsiS_burstKind == 2'b00) ? + (wsiS_wsiReq__wget[56] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiS_burstKind__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'b00 || + wsiS_burstKind == 2'b01 && wsiS_wsiReq__wget[57] || + wsiS_burstKind == 2'b10 && wsiS_wsiReq__wget[55:44] == 12'b000000000001) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky__D_IN = 1'b1 ; + assign wsiS_errorSticky__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo__FULL_N ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount__D_IN = wsiS_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_iMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b10 && + wsiS_wsiReq__wget[55:44] == 12'b000000000001 ; + + // register wsiS_operateD + assign wsiS_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiS_operateD__EN = 1'b1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount__D_IN = wsiS_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_pMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b01 && + wsiS_wsiReq__wget[57] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady__D_IN = wsiS1_MReset_n ; + assign wsiS_peerIsReady__EN = 1'b1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg__D_IN = + CAN_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'b01 : + wsiS_reqFifo_countReg - 2'b01 ; + assign wsiS_reqFifo_countReg__EN = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // register wsiS_statusR + assign wsiS_statusR__EN = 1'b1 ; + assign wsiS_statusR__D_IN = + { wsiS_isReset__VAL, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'b00, + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady, + 1'b0, + wsiS_trafficSticky } ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount__D_IN = wsiS_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiS_tBusyCount__EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky__D_IN = 1'b1 ; + assign wsiS_trafficSticky__EN = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiWordsRemain + assign wsiWordsRemain__D_IN = + MUX_mesgLength__write_1__SEL_2 ? + wsiS_reqFifo__D_OUT[55:44] : + MUX_wsiWordsRemain__write_1__VAL_2 ; + assign wsiWordsRemain__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messagePushPrecise ; + + // register zeroLengthMesg + assign zeroLengthMesg__D_IN = wsiS_reqFifo__D_OUT[11:8] == 4'b0000 ; + assign zeroLengthMesg__EN = MUX_mesgLength__write_1__SEL_2 ; + + // submodule wci_reqF + assign wci_reqF__D_IN = wci_wciReq__wget ; + assign wci_reqF__DEQ = wci_reqF_r_deq__whas ; + assign wci_reqF__ENQ = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF__CLR = 1'b0 ; + + // submodule wmi_respF + assign wmi_respF__D_IN = wmi_wmiResponse__wget ; + assign wmi_respF__DEQ = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign wmi_respF__ENQ = CAN_FIRE_RL_wmi_respAdvance ; + assign wmi_respF__CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo__D_IN = wsiS_wsiReq__wget ; + assign wsiS_reqFifo__ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo__CLR = 1'b0 ; + assign wsiS_reqFifo__DEQ = wsiS_reqFifo_r_deq__whas ; + + // remaining internal signals + assign IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 = + mesgLength[14] ? mesgLength[13:0] : 14'b00000000000000 ; + assign NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 = + wmi_reqF_c_r != 2'b10 && wmi_operateD && wmi_peerIsReady && + (!x__h18884 || wmi_mFlagF_c_r != 2'b10) ; + assign NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 = + wsiS_reqFifo_countReg > 2'b01 ; + assign addr__h16647 = { mesgLengthSoFar[11:0], 2'b00 } ; + // assign b__h13937 = -fabWordsCurReq[3:0] ; + assign b__h13937 = fabWordsCurReq[3:0] ; +// assign b__h19084 = { {10{fabRespCredit_value[3]}}, fabRespCredit_value } ; +assign b__h19084 = { {fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3]}, fabRespCredit_value } ; + assign bl__h17580 = + zeroLengthMesg ? + 12'b000000000001 : + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753[13:2] ; + assign mesgMetaF_length__h16810 = { 10'b0000000000, mlp1B__h16631 } ; + assign mesgMetaF_length__h17723 = + { 10'b0000000000, + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ; + assign mesgMetaF_opcode__h16809 = opcode[8] ? opcode[7:0] : 8'b00000000 ; + assign mlp1B__h16631 = { mlp1__h16630[11:0], 2'b00 } ; + assign mlp1__h16630 = mesgLengthSoFar + 14'b00000000000001 ; + assign rdat__h15540 = { 16'b0000000000000000, x__h15543 } ; + assign wsiBurstLength__h18454 = + smaCtrl[5] ? 16'b0000000000000010 : { 2'b00, thisMesg[15:2] } ; + assign wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 = + wsiS_reqFifo__EMPTY_N && wmi_operateD && wmi_peerIsReady && + (!x__h16715 || wmi_mFlagF_c_r != 2'b10) ; + assign x__h15543 = { wsiS_statusR, wsiM_statusR } ; + assign x__h16715 = wsiS_reqFifo__D_OUT[55:44] == 12'b000000000001 ; + assign x__h18884 = fabWordsRemain == fabWordsCurReq ; + assign x_burstLength__h18559 = + (thisMesg[15:0] == 16'b0000000000000000 || smaCtrl[5] && unrollCnt == 16'b0000000000000001) ? + 12'b000000000001 : + (smaCtrl[5] ? 12'b111111111111 : wsiBurstLength__h18454[11:0]) ; + assign x_byteEn__h18561 = (thisMesg[15:0] == 16'b0000000000000000) ? 4'b0000 : 4'b1111 ; + assign x_length__h17087 = + { 2'b00, + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ; + always@(wci_reqF__D_OUT or + smaCtrl or + mesgCount or + abortCount or + thisMesg or + lastMesg or + rdat__h15540 or wsiS_extStatusW__wget or wsiM_extStatusW__wget) + begin + case (wci_reqF__D_OUT[39:32]) + 8'h0: x_data__h15447 = smaCtrl; + 8'h04: x_data__h15447 = mesgCount; + 8'h08: x_data__h15447 = abortCount; + 8'h10: x_data__h15447 = thisMesg; + 8'h14: x_data__h15447 = lastMesg; + 8'h18: x_data__h15447 = rdat__h15540; + 8'h20: x_data__h15447 = wsiS_extStatusW__wget[95:64]; + 8'h24: x_data__h15447 = wsiS_extStatusW__wget[63:32]; + 8'h28: x_data__h15447 = wsiS_extStatusW__wget[31:0]; + 8'h2C: x_data__h15447 = wsiM_extStatusW__wget[95:64]; + 8'h30: x_data__h15447 = wsiM_extStatusW__wget[63:32]; + 8'h34: x_data__h15447 = wsiM_extStatusW__wget[31:0]; + default: x_data__h15447 = 32'b00000000000000000000000000000000; + endcase + end + always@(MUX_endOfMessage__write_1__SEL_1 or + MUX_wmi_mFlagF_x_wire__wset_1__VAL_1 or + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2 or + WILL_FIRE_RL_wmwt_requestPrecise or + MUX_wmi_mFlagF_x_wire__wset_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_endOfMessage__write_1__SEL_1: + value__h6065 = MUX_wmi_mFlagF_x_wire__wset_1__VAL_1; + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2: + value__h6065 = 32'hAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_wmwt_requestPrecise: + value__h6065 = MUX_wmi_mFlagF_x_wire__wset_1__VAL_3; + default: value__h6065 = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (!wciS0_MReset_n) + begin + abortCount <= 32'b00000000000000000000000000000000; + doAbort <= 1'b0; + endOfMessage <= 1'b0; + errCount <= 32'b00000000000000000000000000000000; + fabRespCredit_value <= 4'b0000; + fabWordsRemain <= 14'b00000000000000; + firstMsgReq <= 1'b0; + impreciseBurst <= 1'b0; + lastMesg <= 32'hFEFEFFFE; + mesgCount <= 32'b00000000000000000000000000000000; + mesgLength <= 15'b010101010101010; + mesgLengthSoFar <= 14'b00000000000000; + mesgPreRequest <= 1'b0; + mesgReqOK <= 1'b0; + mesgReqValid <= 1'b0; + opcode <= 9'b010101010; + preciseBurst <= 1'b0; + readyToPush <= 1'b0; + readyToRequest <= 1'b0; + smaCtrl <= smaCtrlInit; + thisMesg <= 32'hFEFEFFFE; + unrollCnt <= 16'b0000000000000000; + valExpect <= 32'b00000000000000000000000000000000; + wci_cEdge <= 3'b111; + wci_cState <= 3'b000; + wci_ctlAckReg <= 1'b0; + wci_ctlOpActive <= 1'b0; + wci_illegalEdge <= 1'b0; + wci_nState <= 3'b000; + wci_reqF_countReg <= 2'b00; + wci_respF_c_r <= 2'b00; + wci_respF_q_0 <= 34'h0AAAAAAAA; + wci_respF_q_1 <= 34'h0AAAAAAAA; + wci_sFlagReg <= 1'b0; + wci_sThreadBusy_d <= 1'b1; + wmi_busyWithMessage <= 1'b0; + wmi_dhF_c_r <= 2'b00; + wmi_dhF_q_0 <= 38'h0AAAAAAAAA; + wmi_dhF_q_1 <= 38'h0AAAAAAAAA; + wmi_mFlagF_c_r <= 2'b00; + wmi_mFlagF_q_0 <= 32'b00000000000000000000000000000000; + wmi_mFlagF_q_1 <= 32'b00000000000000000000000000000000; + wmi_operateD <= 1'b0; + wmi_peerIsReady <= 1'b0; + wmi_reqF_c_r <= 2'b00; + wmi_reqF_q_0 <= 32'b00001010101010101010101010101010; + wmi_reqF_q_1 <= 32'b00001010101010101010101010101010; + wmi_sDataThreadBusy_d <= 1'b0; + wmi_sFlagReg <= 32'b00000000000000000000000000000000; + wmi_sThreadBusy_d <= 1'b0; + wsiM_burstKind <= 2'b00; + wsiM_errorSticky <= 1'b0; + wsiM_iMesgCount <= 32'b00000000000000000000000000000000; + wsiM_operateD <= 1'b0; + wsiM_pMesgCount <= 32'b00000000000000000000000000000000; + wsiM_peerIsReady <= 1'b0; + wsiM_reqFifo_c_r <= 2'b00; + wsiM_reqFifo_q_0 <= 61'h00000AAAAAAAAA00; + wsiM_reqFifo_q_1 <= 61'h00000AAAAAAAAA00; + wsiM_sThreadBusy_d <= 1'b1; + wsiM_tBusyCount <= 32'b00000000000000000000000000000000; + wsiM_trafficSticky <= 1'b0; + wsiS_burstKind <= 2'b00; + wsiS_errorSticky <= 1'b0; + wsiS_iMesgCount <= 32'b00000000000000000000000000000000; + wsiS_operateD <= 1'b0; + wsiS_pMesgCount <= 32'b00000000000000000000000000000000; + wsiS_peerIsReady <= 1'b0; + wsiS_reqFifo_countReg <= 2'b00; + wsiS_tBusyCount <= 32'b00000000000000000000000000000000; + wsiS_trafficSticky <= 1'b0; + wsiWordsRemain <= 12'b000000000000; + zeroLengthMesg <= 1'b0; + end + else + begin + if (abortCount__EN) + abortCount <= abortCount__D_IN; + if (doAbort__EN) doAbort <= doAbort__D_IN; + if (endOfMessage__EN) + endOfMessage <= endOfMessage__D_IN; + if (errCount__EN) errCount <= errCount__D_IN; + if (fabRespCredit_value__EN) + fabRespCredit_value <= + fabRespCredit_value__D_IN; + if (fabWordsRemain__EN) + fabWordsRemain <= fabWordsRemain__D_IN; + if (firstMsgReq__EN) + firstMsgReq <= firstMsgReq__D_IN; + if (impreciseBurst__EN) + impreciseBurst <= impreciseBurst__D_IN; + if (lastMesg__EN) lastMesg <= lastMesg__D_IN; + if (mesgCount__EN) mesgCount <= mesgCount__D_IN; + if (mesgLength__EN) + mesgLength <= mesgLength__D_IN; + if (mesgLengthSoFar__EN) + mesgLengthSoFar <= mesgLengthSoFar__D_IN; + if (mesgPreRequest__EN) + mesgPreRequest <= mesgPreRequest__D_IN; + if (mesgReqOK__EN) mesgReqOK <= mesgReqOK__D_IN; + if (mesgReqValid__EN) + mesgReqValid <= mesgReqValid__D_IN; + if (opcode__EN) opcode <= opcode__D_IN; + if (preciseBurst__EN) + preciseBurst <= preciseBurst__D_IN; + if (readyToPush__EN) + readyToPush <= readyToPush__D_IN; + if (readyToRequest__EN) + readyToRequest <= readyToRequest__D_IN; + if (smaCtrl__EN) smaCtrl <= smaCtrl__D_IN; + if (thisMesg__EN) thisMesg <= thisMesg__D_IN; + if (unrollCnt__EN) unrollCnt <= unrollCnt__D_IN; + if (valExpect__EN) valExpect <= valExpect__D_IN; + if (wci_cEdge__EN) wci_cEdge <= wci_cEdge__D_IN; + if (wci_cState__EN) + wci_cState <= wci_cState__D_IN; + if (wci_ctlAckReg__EN) + wci_ctlAckReg <= wci_ctlAckReg__D_IN; + if (wci_ctlOpActive__EN) + wci_ctlOpActive <= wci_ctlOpActive__D_IN; + if (wci_illegalEdge__EN) + wci_illegalEdge <= wci_illegalEdge__D_IN; + if (wci_nState__EN) + wci_nState <= wci_nState__D_IN; + if (wci_reqF_countReg__EN) + wci_reqF_countReg <= wci_reqF_countReg__D_IN; + if (wci_respF_c_r__EN) + wci_respF_c_r <= wci_respF_c_r__D_IN; + if (wci_respF_q_0__EN) + wci_respF_q_0 <= wci_respF_q_0__D_IN; + if (wci_respF_q_1__EN) + wci_respF_q_1 <= wci_respF_q_1__D_IN; + if (wci_sFlagReg__EN) + wci_sFlagReg <= wci_sFlagReg__D_IN; + if (wci_sThreadBusy_d__EN) + wci_sThreadBusy_d <= wci_sThreadBusy_d__D_IN; + if (wmi_busyWithMessage__EN) + wmi_busyWithMessage <= + wmi_busyWithMessage__D_IN; + if (wmi_dhF_c_r__EN) + wmi_dhF_c_r <= wmi_dhF_c_r__D_IN; + if (wmi_dhF_q_0__EN) + wmi_dhF_q_0 <= wmi_dhF_q_0__D_IN; + if (wmi_dhF_q_1__EN) + wmi_dhF_q_1 <= wmi_dhF_q_1__D_IN; + if (wmi_mFlagF_c_r__EN) + wmi_mFlagF_c_r <= wmi_mFlagF_c_r__D_IN; + if (wmi_mFlagF_q_0__EN) + wmi_mFlagF_q_0 <= wmi_mFlagF_q_0__D_IN; + if (wmi_mFlagF_q_1__EN) + wmi_mFlagF_q_1 <= wmi_mFlagF_q_1__D_IN; + if (wmi_operateD__EN) + wmi_operateD <= wmi_operateD__D_IN; + if (wmi_peerIsReady__EN) + wmi_peerIsReady <= wmi_peerIsReady__D_IN; + if (wmi_reqF_c_r__EN) + wmi_reqF_c_r <= wmi_reqF_c_r__D_IN; + if (wmi_reqF_q_0__EN) + wmi_reqF_q_0 <= wmi_reqF_q_0__D_IN; + if (wmi_reqF_q_1__EN) + wmi_reqF_q_1 <= wmi_reqF_q_1__D_IN; + if (wmi_sDataThreadBusy_d__EN) + wmi_sDataThreadBusy_d <= + wmi_sDataThreadBusy_d__D_IN; + if (wmi_sFlagReg__EN) + wmi_sFlagReg <= wmi_sFlagReg__D_IN; + if (wmi_sThreadBusy_d__EN) + wmi_sThreadBusy_d <= wmi_sThreadBusy_d__D_IN; + if (wsiM_burstKind__EN) + wsiM_burstKind <= wsiM_burstKind__D_IN; + if (wsiM_errorSticky__EN) + wsiM_errorSticky <= wsiM_errorSticky__D_IN; + if (wsiM_iMesgCount__EN) + wsiM_iMesgCount <= wsiM_iMesgCount__D_IN; + if (wsiM_operateD__EN) + wsiM_operateD <= wsiM_operateD__D_IN; + if (wsiM_pMesgCount__EN) + wsiM_pMesgCount <= wsiM_pMesgCount__D_IN; + if (wsiM_peerIsReady__EN) + wsiM_peerIsReady <= wsiM_peerIsReady__D_IN; + if (wsiM_reqFifo_c_r__EN) + wsiM_reqFifo_c_r <= wsiM_reqFifo_c_r__D_IN; + if (wsiM_reqFifo_q_0__EN) + wsiM_reqFifo_q_0 <= wsiM_reqFifo_q_0__D_IN; + if (wsiM_reqFifo_q_1__EN) + wsiM_reqFifo_q_1 <= wsiM_reqFifo_q_1__D_IN; + if (wsiM_sThreadBusy_d__EN) + wsiM_sThreadBusy_d <= wsiM_sThreadBusy_d__D_IN; + if (wsiM_tBusyCount__EN) + wsiM_tBusyCount <= wsiM_tBusyCount__D_IN; + if (wsiM_trafficSticky__EN) + wsiM_trafficSticky <= wsiM_trafficSticky__D_IN; + if (wsiS_burstKind__EN) + wsiS_burstKind <= wsiS_burstKind__D_IN; + if (wsiS_errorSticky__EN) + wsiS_errorSticky <= wsiS_errorSticky__D_IN; + if (wsiS_iMesgCount__EN) + wsiS_iMesgCount <= wsiS_iMesgCount__D_IN; + if (wsiS_operateD__EN) + wsiS_operateD <= wsiS_operateD__D_IN; + if (wsiS_pMesgCount__EN) + wsiS_pMesgCount <= wsiS_pMesgCount__D_IN; + if (wsiS_peerIsReady__EN) + wsiS_peerIsReady <= wsiS_peerIsReady__D_IN; + if (wsiS_reqFifo_countReg__EN) + wsiS_reqFifo_countReg <= + wsiS_reqFifo_countReg__D_IN; + if (wsiS_tBusyCount__EN) + wsiS_tBusyCount <= wsiS_tBusyCount__D_IN; + if (wsiS_trafficSticky__EN) + wsiS_trafficSticky <= wsiS_trafficSticky__D_IN; + if (wsiWordsRemain__EN) + wsiWordsRemain <= wsiWordsRemain__D_IN; + if (zeroLengthMesg__EN) + zeroLengthMesg <= zeroLengthMesg__D_IN; + end + if (fabWordsCurReq__EN) + fabWordsCurReq <= fabWordsCurReq__D_IN; + if (mesgReqAddr__EN) mesgReqAddr <= mesgReqAddr__D_IN; + if (wsiM_statusR__EN) + wsiM_statusR <= wsiM_statusR__D_IN; + if (wsiS_statusR__EN) + wsiS_statusR <= wsiS_statusR__D_IN; + end + + +endmodule // mkSMAdapter4B + + + + + +module SizedFIFO_a (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [59:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [59:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(CLR), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + +module SizedFIFO_b (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(CLR), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter awb=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + + +module SizedFIFO_c (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [60:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [60:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + +module ResetToBool (RST, VAL); + +input RST; +output VAL; +reg VAL; + +always @ (RST or VAL) +begin + +if (RST == 1) +VAL=1'b0; + +end +endmodule + +//--------------------------------------- +// A dual-port RAM 64x60 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_64x60 ( + input clk, + input we1, + input we2, + input [6 - 1 : 0] addr1, + input [60 - 1 : 0] data1, + output [60 - 1 : 0] out1, + input [6 - 1 : 0] addr2, + input [60 - 1 : 0] data2, + output [60 - 1 : 0] out2 +); + reg [60 - 1 : 0] ram[2**6 - 1 : 0]; + reg [60 - 1 : 0] data_out1; + reg [60 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 4x32 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_4x32 ( + input clk, + input we1, + input we2, + input [2 - 1 : 0] addr1, + input [32 - 1 : 0] data1, + output [32 - 1 : 0] out1, + input [2 - 1 : 0] addr2, + input [32 - 1 : 0] data2, + output [32 - 1 : 0] out2 +); + reg [32 - 1 : 0] ram[2**2 - 1 : 0]; + reg [32 - 1 : 0] data_out1; + reg [32 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule + +//--------------------------------------- +// A dual-port RAM 8x61 +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram_8x61 ( + input clk, + input we1, + input we2, + input [3 - 1 : 0] addr1, + input [61 - 1 : 0] data1, + output [61 - 1 : 0] out1, + input [3 - 1 : 0] addr2, + input [61 - 1 : 0] data2, + output [61 - 1 : 0] out2 +); + reg [61 - 1 : 0] ram[2**3 - 1 : 0]; + reg [61 - 1 : 0] data_out1; + reg [61 - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/or1200.v b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v new file mode 100755 index 000000000..df164e27a --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v @@ -0,0 +1,5282 @@ +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. + +`define OR1200_DCFGR_RES1 28'h0000000 + + + + +`define OR1200_M2R_BYTE0 4'b0000 +`define OR1200_M2R_BYTE1 4'b0001 +`define OR1200_M2R_BYTE2 4'b0010 +`define OR1200_M2R_BYTE3 4'b0011 +`define OR1200_M2R_EXTB0 4'b0100 +`define OR1200_M2R_EXTB1 4'b0101 +`define OR1200_M2R_EXTB2 4'b0110 +`define OR1200_M2R_EXTB3 4'b0111 +`define OR1200_M2R_ZERO 4'b0000 + + +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS 9 // Num cache sets +`define OR1200_ICCFGR_CBS 9 // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 + +//`define OR1200_ICCFGR_NCW_BITS 2:0 +//`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +//`define OR1200_ICCFGR_RES1_BITS 31:15 + + +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS 9 // Num cache sets +`define OR1200_DCCFGR_CBS 9 // 16 byte cache block +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 + + + +//`define OR1200_DCCFGR_NCW_BITS 2:0 +//`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +//`define OR1200_DCCFGR_RES1_BITS 31:15 + + +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'b101 // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 + +// CPUCFGR fields +//`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +//`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +/* +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +*/ +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +//`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values + +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'b110 // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 + + +// IMMUCFGR fields +/* +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +*/ +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 + +//`define OR1200_IMMUCFGR_RES1_BITS 31:12 + + + +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +/* +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 +*/ +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +/* +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 +*/ + +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + + +`define OR1200_DU_DSR_WIDTH 14 + + +`define OR1200_EXCEPT_UNUSED 3'hf +`define OR1200_EXCEPT_TRAP 3'he +`define OR1200_EXCEPT_BREAK 3'hd +`define OR1200_EXCEPT_SYSCALL 3'hc +`define OR1200_EXCEPT_RANGE 3'hb +`define OR1200_EXCEPT_ITLBMISS 3'ha +`define OR1200_EXCEPT_DTLBMISS 3'h9 +`define OR1200_EXCEPT_INT 3'h8 +`define OR1200_EXCEPT_ILLEGAL 3'h7 +`define OR1200_EXCEPT_ALIGN 3'h6 +`define OR1200_EXCEPT_TICK 3'h5 +`define OR1200_EXCEPT_IPF 3'h4 +`define OR1200_EXCEPT_DPF 3'h3 +`define OR1200_EXCEPT_BUSERR 3'h2 +`define OR1200_EXCEPT_RESET 3'h1 +`define OR1200_EXCEPT_NONE 3'h0 + +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'b000 + +`define OR1200_ALUOP_ADD 4'b0000 +`define OR1200_ALUOP_ADDC 4'b0001 +`define OR1200_ALUOP_SUB 4'b0010 +`define OR1200_ALUOP_AND 4'b0011 +`define OR1200_ALUOP_OR 4'b0100 +`define OR1200_ALUOP_XOR 4'b0101 +`define OR1200_ALUOP_MUL 4'b0110 +`define OR1200_ALUOP_CUST5 4'b0111 +`define OR1200_ALUOP_SHROT 4'b1000 +`define OR1200_ALUOP_DIV 4'b1001 +`define OR1200_ALUOP_DIVU 4'b1010 + +`define OR1200_ALUOP_IMM 4'b1011 +`define OR1200_ALUOP_MOVHI 4'b1100 +`define OR1200_ALUOP_COMP 4'b1101 +`define OR1200_ALUOP_MTSR 4'b1110 +`define OR1200_ALUOP_MFSR 4'b1111 +`define OR1200_ALUOP_CMOV 4'b1110 +`define OR1200_ALUOP_FF1 4'b1111 + +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + + +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'b00 +`define OR1200_SHROTOP_SLL 2'b00 +`define OR1200_SHROTOP_SRL 2'b01 +`define OR1200_SHROTOP_SRA 2'b10 +`define OR1200_SHROTOP_ROR 2'b11 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'b00 +`define OR1200_TWO_CYCLES 2'b01 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'b00 +`define OR1200_SEL_IMM 2'b01 +`define OR1200_SEL_EX_FORW 2'b10 +`define OR1200_SEL_WB_FORW 2'b11 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'b000 +`define OR1200_BRANCHOP_J 3'b001 +`define OR1200_BRANCHOP_JR 3'b010 +`define OR1200_BRANCHOP_BAL 3'b011 +`define OR1200_BRANCHOP_BF 3'b100 +`define OR1200_BRANCHOP_BNF 3'b101 +`define OR1200_BRANCHOP_RFE 3'b110 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 3'b011 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + + +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +//`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +//`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +`define OR1200_OR32_CUST5 6'b111100 + + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +`define OR1200_SPR_GROUP_SYS 5'b00000 +`define OR1200_SPR_GROUP_DMMU 5'b00001 +`define OR1200_SPR_GROUP_IMMU 5'b00010 +`define OR1200_SPR_GROUP_DC 5'b00011 +`define OR1200_SPR_GROUP_IC 5'b00100 +`define OR1200_SPR_GROUP_MAC 5'b00101 +`define OR1200_SPR_GROUP_DU 5'b00110 +`define OR1200_SPR_GROUP_PM 5'b01000 +`define OR1200_SPR_GROUP_PIC 5'b01001 +`define OR1200_SPR_GROUP_TT 5'b01010 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'b0000000 +`define OR1200_SPR_RF 6'b100000 // 1024 >> 5 +`define OR1200_SPR_NPC 11'b00000010000 +`define OR1200_SPR_SR 11'b00000010001 +`define OR1200_SPR_PPC 11'b00000010010 +`define OR1200_SPR_EPCR 11'b00000100000 +`define OR1200_SPR_EEAR 11'b00000110000 +`define OR1200_SPR_ESR 11'b00001000000 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 + + +// +// Bits that define offset inside the group + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// +// Bit positions inside PMR (don't change) + +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 + + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'b01000 + + + +// Define it if you want PIC implemented + + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'b00 +`define OR1200_PIC_OFS_PICSR 2'b10 + +// Position of offset bits inside SPR address + + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'b0 +`define OR1200_TT_OFS_TTCR 1'b1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// TTMR bits +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 + + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// +// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which +// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer +// default setup, but if you need to remain backward compatible, define your shift bits, which were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 +`define OR1200_ITLB_INDXW 6 + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +`define OR1200_DCSIZE 12 // 4096 + +`define OR1200_DCTAG_W 21 + + + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h00800000 +`define OR1200_QMEM_IMASK 32'hfff00000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h00800000 +`define OR1200_QMEM_DMASK 32'hfff00000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + + +// UPR values +`define OR1200_UPR_UP 1'b1 +`define OR1200_UPR_DCP 1'b1 + +`define OR1200_UPR_ICP 1'b1 + +`define OR1200_UPR_DMP 1'b1 + +`define OR1200_UPR_IMP 1'b1 + +`define OR1200_UPR_MP 1'b1 // MAC always present + +`define OR1200_UPR_DUP 1'b1 + + +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present + +`define OR1200_UPR_PMP 1'b1 + +`define OR1200_UPR_PICP 1'b1 + +`define OR1200_UPR_TTP 1'b1 + +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + + +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 + +// DMMUCFGR values +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 + + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +// IMMUCFGR values +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 + + +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 + +// DCCFGR values +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 + + +// ICCFGR fields +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 + +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 + + +// DCFGR fields +`define OR1200_DCFGR_WPCI_BITS 3 + +// DCFGR values + +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. + +`define OR1200_DCFGR_RES1 28'h0000000 + + +module or1200_flat( // or1200_cpu + // Clk & Rst + clk, rst, + + // Insn interface + ic_en, + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + immu_en, + + // Debug unit + ex_insn, ex_freeze, id_pc, branch_op, + spr_dat_npc, rf_dataw, + du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt, + du_except, du_dat_cpu, + + // Data interface + dc_en, + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i, + dmmu_en, + + // Interrupt & tick exceptions + sig_int, sig_tick, + + // SPR interface + supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we +); + +//parameter dw = `OR1200_OPERAND_WIDTH; +//parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O ports +// + +// +// Clk & Rst +// +input clk; +input rst; + +// +// Insn (IC) interface +// +output ic_en; +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_rty_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Insn (IMMU) interface +// +output immu_en; + +// +// Debug interface +// +output [31:0] ex_insn; +output ex_freeze; +output [31:0] id_pc; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; + +input du_stall; +input [`OR1200_OPERAND_WIDTH-1:0] du_addr; +input [`OR1200_OPERAND_WIDTH-1:0] du_dat_du; +input du_read; +input du_write; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +input du_hwbkpt; +output [12:0] du_except; +output [`OR1200_OPERAND_WIDTH-1:0] du_dat_cpu; +output [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; + +// +// Data (DC) interface +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; +output dc_en; + +// +// Data (DMMU) interface +// +output dmmu_en; + +// +// SPR interface +// +output supv; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_pic; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_tt; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_pm; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_dmmu; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_immu; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_du; +output [`OR1200_OPERAND_WIDTH-1:0] spr_addr; +output [`OR1200_OPERAND_WIDTH-1:0] spr_dat_cpu; +output [`OR1200_OPERAND_WIDTH-1:0] spr_dat_npc; +output [31:0] spr_cs; +output spr_we; + +// +// Interrupt exceptions +// +input sig_int; +input sig_tick; + +// +// Internal wires +// +wire [31:0] if_insn; +wire [31:0] if_pc; +wire [31:2] lr_sav; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb; +wire rf_rda; +wire rf_rdb; +wire [`OR1200_OPERAND_WIDTH-1:0] simm; +wire [`OR1200_OPERAND_WIDTH-1:2] branch_addrofs; +wire [`OR1200_ALUOP_WIDTH-1:0] alu_op; +wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +wire [`OR1200_COMPOP_WIDTH-1:0] comp_op; +wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +wire genpc_freeze; +wire if_freeze; +wire id_freeze; +wire ex_freeze; +wire wb_freeze; +wire [`OR1200_SEL_WIDTH-1:0] sel_a; +wire [`OR1200_SEL_WIDTH-1:0] sel_b; +wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataa; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_datab; +wire [`OR1200_OPERAND_WIDTH-1:0] muxed_b; +wire [`OR1200_OPERAND_WIDTH-1:0] wb_forw; +wire wbforw_valid; +wire [`OR1200_OPERAND_WIDTH-1:0] operand_a; +wire [`OR1200_OPERAND_WIDTH-1:0] operand_b; +wire [`OR1200_OPERAND_WIDTH-1:0] alu_dataout; +wire [`OR1200_OPERAND_WIDTH-1:0] lsu_dataout; +wire [`OR1200_OPERAND_WIDTH-1:0] sprs_dataout; +wire [31:0] lsu_addrofs; +wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +wire [`OR1200_EXCEPT_WIDTH-1:0] except_type; +wire [4:0] cust5_op; +wire [5:0] cust5_limm; +wire flushpipe; +wire extend_flush; +wire branch_taken; +wire flag; +wire flagforw; +wire flag_we; +wire k_carry; +wire cyforw; +wire cy_we; +wire lsu_stall; +wire epcr_we; +wire eear_we; +wire esr_we; +wire pc_we; +wire [31:0] epcr; +wire [31:0] eear; +wire [`OR1200_SR_WIDTH-1:0] esr; +wire sr_we; +wire [`OR1200_SR_WIDTH-1:0] to_sr; +wire [`OR1200_SR_WIDTH-1:0] sr; +wire except_start; +wire except_started; +wire [31:0] wb_insn; +wire [15:0] spr_addrimm; +wire sig_syscall; +wire sig_trap; +wire [31:0] spr_dat_cfgr; +wire [31:0] spr_dat_rf; +wire [31:0] spr_dat_npc; +wire [31:0] spr_dat_ppc; +wire [31:0] spr_dat_mac; +wire force_dslot_fetch; +wire no_more_dslot; +wire ex_void; +wire if_stall; +wire id_macrc_op; +wire ex_macrc_op; +wire [`OR1200_MACOP_WIDTH-1:0] mac_op; +wire [31:0] mult_mac_result; +wire mac_stall; +wire [12:0] except_stop; +wire genpc_refetch; +wire rfe; +wire lsu_unstall; +wire except_align; +wire except_dtlbmiss; +wire except_dmmufault; +wire except_illegal; +wire except_itlbmiss; +wire except_immufault; +wire except_ibuserr; +wire except_dbuserr; +wire abort_ex; + +// +// Send exceptions to Debug Unit +// +assign du_except = except_stop; + +// +// Data cache enable +// +assign dc_en = sr[`OR1200_SR_DCE]; + +// +// Instruction cache enable +// +assign ic_en = sr[`OR1200_SR_ICE]; + +// +// DMMU enable +// +assign dmmu_en = sr[`OR1200_SR_DME]; + +// +// IMMU enable +// +assign immu_en = sr[`OR1200_SR_IME]; + +// +// SUPV bit +// +assign supv = sr[`OR1200_SR_SM]; + +// +// Instantiation of instruction fetch block +// +or1200_genpc or1200_genpc( + .clk(clk), + .rst(rst), + .icpu_adr_o(icpu_adr_o), + .icpu_cycstb_o(icpu_cycstb_o), + .icpu_sel_o(icpu_sel_o), + .icpu_tag_o(icpu_tag_o), + .icpu_rty_i(icpu_rty_i), + .icpu_adr_i(icpu_adr_i), + + .branch_op(branch_op), + .except_type(except_type), + .except_start(except_start), + .except_prefix(sr[`OR1200_SR_EPH]), + .branch_addrofs(branch_addrofs), + .lr_restor(operand_b), + .flag(flag), + .taken(branch_taken), + .binsn_addr(lr_sav), + .epcr(epcr), + .spr_dat_i(spr_dat_cpu), + .spr_pc_we(pc_we), + .genpc_refetch(genpc_refetch), + .genpc_freeze(genpc_freeze), + .genpc_stop_prefetch(1'b0), + .no_more_dslot(no_more_dslot) +); + +// +// Instantiation of instruction fetch block +// +or1200_if or1200_if( + .clk(clk), + .rst(rst), + .icpu_dat_i(icpu_dat_i), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .icpu_adr_i(icpu_adr_i), + .icpu_tag_i(icpu_tag_i), + + .if_freeze(if_freeze), + .if_insn(if_insn), + .if_pc(if_pc), + .flushpipe(flushpipe), + .if_stall(if_stall), + .no_more_dslot(no_more_dslot), + .genpc_refetch(genpc_refetch), + .rfe(rfe), + .except_itlbmiss(except_itlbmiss), + .except_immufault(except_immufault), + .except_ibuserr(except_ibuserr) +); + +// +// Instantiation of instruction decode/control logic +// +or1200_ctrl or1200_ctrl( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .flushpipe(flushpipe), + .if_insn(if_insn), + .ex_insn(ex_insn), + .branch_op(branch_op), + .branch_taken(branch_taken), + .rf_addra(rf_addra), + .rf_addrb(rf_addrb), + .rf_rda(rf_rda), + .rf_rdb(rf_rdb), + .alu_op(alu_op), + .mac_op(mac_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .rf_addrw(rf_addrw), + .rfwb_op(rfwb_op), + .wb_insn(wb_insn), + .simm(simm), + .branch_addrofs(branch_addrofs), + .lsu_addrofs(lsu_addrofs), + .sel_a(sel_a), + .sel_b(sel_b), + .lsu_op(lsu_op), + .cust5_op(cust5_op), + .cust5_limm(cust5_limm), + .multicycle(multicycle), + .spr_addrimm(spr_addrimm), + .wbforw_valid(wbforw_valid), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .force_dslot_fetch(force_dslot_fetch), + .no_more_dslot(no_more_dslot), + .ex_void(ex_void), + .id_macrc_op(id_macrc_op), + .ex_macrc_op(ex_macrc_op), + .rfe(rfe), + .du_hwbkpt(du_hwbkpt), + .except_illegal(except_illegal) +); + +// +// Instantiation of register file +// +or1200_rf or1200_rf( + .clk(clk), + .rst(rst), + .supv(sr[`OR1200_SR_SM]), + .wb_freeze(wb_freeze), + .addrw(rf_addrw), + .dataw(rf_dataw), + .id_freeze(id_freeze), + .we(rfwb_op[0]), + .flushpipe(flushpipe), + .addra(rf_addra), + .rda(rf_rda), + .dataa(rf_dataa), + .addrb(rf_addrb), + .rdb(rf_rdb), + .datab(rf_datab), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_rf) +); + +// +// Instantiation of operand muxes +// +or1200_operandmuxes or1200_operandmuxes( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .rf_dataa(rf_dataa), + .rf_datab(rf_datab), + .ex_forw(rf_dataw), + .wb_forw(wb_forw), + .simm(simm), + .sel_a(sel_a), + .sel_b(sel_b), + .operand_a(operand_a), + .operand_b(operand_b), + .muxed_b(muxed_b) +); + +// +// Instantiation of CPU's ALU +// +or1200_alu or1200_alu( + .a(operand_a), + .b(operand_b), + .mult_mac_result(mult_mac_result), + .macrc_op(ex_macrc_op), + .alu_op(alu_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .cust5_op(cust5_op), + .cust5_limm(cust5_limm), + .result(alu_dataout), + .flagforw(flagforw), + .flag_we(flag_we), + .cyforw(cyforw), + .cy_we(cy_we), + .flag(flag), + .k_carry(k_carry) +); + +// +// Instantiation of CPU's ALU +// +or1200_mult_mac or1200_mult_mac( + .clk(clk), + .rst(rst), + .ex_freeze(ex_freeze), + .id_macrc_op(id_macrc_op), + .macrc_op(ex_macrc_op), + .a(operand_a), + .b(operand_b), + .mac_op(mac_op), + .alu_op(alu_op), + .result(mult_mac_result), + .mac_stall_r(mac_stall), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_mac) +); + +// +// Instantiation of CPU's SPRS block +// +or1200_sprs or1200_sprs( + .clk(clk), + .rst(rst), + .addrbase(operand_a), + .addrofs(spr_addrimm), + .dat_i(operand_b), + .alu_op(alu_op), + .flagforw(flagforw), + .flag_we(flag_we), + .flag(flag), + .cyforw(cyforw), + .cy_we(cy_we), + .carry(k_carry), + .to_wbmux(sprs_dataout), + + .du_addr(du_addr), + .du_dat_du(du_dat_du), + .du_read(du_read), + .du_write(du_write), + .du_dat_cpu(du_dat_cpu), + + .spr_addr(spr_addr), + .spr_dat_pic(spr_dat_pic), + .spr_dat_tt(spr_dat_tt), + .spr_dat_pm(spr_dat_pm), + .spr_dat_cfgr(spr_dat_cfgr), + .spr_dat_rf(spr_dat_rf), + .spr_dat_npc(spr_dat_npc), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_mac(spr_dat_mac), + .spr_dat_dmmu(spr_dat_dmmu), + .spr_dat_immu(spr_dat_immu), + .spr_dat_du(spr_dat_du), + .spr_dat_o(spr_dat_cpu), + .spr_cs(spr_cs), + .spr_we(spr_we), + + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + .except_started(except_started), + + .sr_we(sr_we), + .to_sr(to_sr), + .sr(sr), + .branch_op(branch_op) +); + +// +// Instantiation of load/store unit +// +or1200_lsu or1200_lsu( + .addrbase(operand_a), + .addrofs(lsu_addrofs), + .lsu_op(lsu_op), + .lsu_datain(operand_b), + .lsu_dataout(lsu_dataout), + .lsu_stall(lsu_stall), + .lsu_unstall(lsu_unstall), + .du_stall(du_stall), + .except_align(except_align), + .except_dtlbmiss(except_dtlbmiss), + .except_dmmufault(except_dmmufault), + .except_dbuserr(except_dbuserr), + + .dcpu_adr_o(dcpu_adr_o), + .dcpu_cycstb_o(dcpu_cycstb_o), + .dcpu_we_o(dcpu_we_o), + .dcpu_sel_o(dcpu_sel_o), + .dcpu_tag_o(dcpu_tag_o), + .dcpu_dat_o(dcpu_dat_o), + .dcpu_dat_i(dcpu_dat_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_rty_i(dcpu_rty_i), + .dcpu_err_i(dcpu_err_i), + .dcpu_tag_i(dcpu_tag_i) +); + +// +// Instantiation of write-back muxes +// +or1200_wbmux or1200_wbmux( + .clk(clk), + .rst(rst), + .wb_freeze(wb_freeze), + .rfwb_op(rfwb_op), + .muxin_a(alu_dataout), + .muxin_b(lsu_dataout), + .muxin_c(sprs_dataout), + .muxin_d({lr_sav, 2'b0}), + .muxout(rf_dataw), + .muxreg(wb_forw), + .muxreg_valid(wbforw_valid) +); + +// +// Instantiation of freeze logic +// +or1200_freeze or1200_freeze( + .clk(clk), + .rst(rst), + .multicycle(multicycle), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .lsu_stall(lsu_stall), + .if_stall(if_stall), + .lsu_unstall(lsu_unstall), + .force_dslot_fetch(force_dslot_fetch), + .abort_ex(abort_ex), + .du_stall(du_stall), + .mac_stall(mac_stall), + .genpc_freeze(genpc_freeze), + .if_freeze(if_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i) +); + +// +// Instantiation of exception block +// +or1200_except or1200_except( + .clk(clk), + .rst(rst), + .sig_ibuserr(except_ibuserr), + .sig_dbuserr(except_dbuserr), + .sig_illegal(except_illegal), + .sig_align(except_align), + .sig_range(1'b0), + .sig_dtlbmiss(except_dtlbmiss), + .sig_dmmufault(except_dmmufault), + .sig_int(sig_int), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .sig_itlbmiss(except_itlbmiss), + .sig_immufault(except_immufault), + .sig_tick(sig_tick), + .branch_taken(branch_taken), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_err_i(dcpu_err_i), + .genpc_freeze(genpc_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .if_stall(if_stall), + .if_pc(if_pc), + .id_pc(id_pc), + .lr_sav(lr_sav), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .except_type(except_type), + .except_start(except_start), + .except_started(except_started), + .except_stop(except_stop), + .ex_void(ex_void), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_npc(spr_dat_npc), + + .datain(operand_b), + .du_dsr(du_dsr), + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + + .lsu_addr(dcpu_adr_o), + .sr_we(sr_we), + .to_sr(to_sr), + .sr(sr), + .abort_ex(abort_ex) +); + +// +// Instantiation of configuration registers +// +or1200_cfgr or1200_cfgr( + .spr_addr(spr_addr), + .spr_dat_o(spr_dat_cfgr) +); + +endmodule + + + +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'b000 +`define OR1200_BRANCHOP_J 3'b001 +`define OR1200_BRANCHOP_JR 3'b010 +`define OR1200_BRANCHOP_BAL 3'b011 +`define OR1200_BRANCHOP_BF 3'b100 +`define OR1200_BRANCHOP_BNF 3'b101 +`define OR1200_BRANCHOP_RFE 3'b110 +`define OR1200_EXCEPT_WIDTH 4 +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +module or1200_genpc( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_rty_i, icpu_adr_i, + + // Internal i/f + branch_op, except_type,except_start, except_prefix, + branch_addrofs, lr_restor, flag, taken, + binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch, + genpc_freeze, genpc_stop_prefetch, no_more_dslot +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input icpu_rty_i; +input [31:0] icpu_adr_i; + +// +// Internal i/f +// +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input [`OR1200_EXCEPT_WIDTH-1:0] except_type; +input except_start; +input except_prefix; +input [31:2] branch_addrofs; +input [31:0] lr_restor; +input flag; +output taken; + +input [31:2] binsn_addr; +input [31:0] epcr; +input [31:0] spr_dat_i; +input spr_pc_we; +input genpc_refetch; +input genpc_freeze; +input genpc_stop_prefetch; +input no_more_dslot; + +// +// Internal wires and regs +// +reg [31:2] pcreg; +reg [31:0] pc; +reg taken; /* Set to in case of jump or taken branch */ +reg genpc_refetch_r; + +// +// Address of insn to be fecthed +// +assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; +// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; + +// +// Control access to IC subsystem +// +// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot; +assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store +//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r); +//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch); +assign icpu_sel_o = 4'b1111; +assign icpu_tag_o = `OR1200_ITAG_NI; + +// +// genpc_freeze_r +// +always @(posedge clk ) + if (rst) + genpc_refetch_r <= 1'b0; + else if (genpc_refetch) + genpc_refetch_r <= 1'b1; + else + genpc_refetch_r <= 1'b0; + +// +// Async calculation of new PC value. This value is used for addressing the IC. +// +always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type + or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin + case ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case + {2'b00, `OR1200_BRANCHOP_NOP}: begin + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_J}: begin + + pc = {branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_JR}: begin + + pc = lr_restor; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BAL}: begin + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BF}: + if (flag) begin + + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + else begin + + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_BNF}: + if (flag) begin + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + + taken = 1'b0; + end + else begin pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_RFE}: begin + + pc = epcr; + taken = 1'b1; + end + {2'b01, 3'b000}: begin + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b001}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b010}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b011}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b100}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b101}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b110}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b111}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + default: begin + + pc = spr_dat_i; + taken = 1'b0; + end + endcase +end + +// +// PC register +// +always @(posedge clk ) + if (rst) +// pcreg <= 30'd63; + pcreg <= ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),8'b11111111, `OR1200_EXCEPT_V} - 1) >> 2; + else if (spr_pc_we) + pcreg <= spr_dat_i[31:2]; + else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) +// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) + pcreg <= pc[31:2]; + + wire unused; + assign unused = |except_prefix & | binsn_addr | genpc_stop_prefetch ; +endmodule + +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +//`define OR1200_OR32_CUST5 6'b111100 + + +module or1200_if( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + + // Internal i/f + if_freeze, if_insn, if_pc, flushpipe, + if_stall, no_more_dslot, genpc_refetch, rfe, + except_itlbmiss, except_immufault, except_ibuserr +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Internal i/f +// +input if_freeze; +output [31:0] if_insn; +output [31:0] if_pc; +input flushpipe; +output if_stall; +input no_more_dslot; +output genpc_refetch; +input rfe; +output except_itlbmiss; +output except_immufault; +output except_ibuserr; + +// +// Internal wires and regs +// +reg [31:0] insn_saved; +reg [31:0] addr_saved; +reg saved; + +// +// IF stage insn +// +assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h0410000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h0610000}; +assign if_pc = saved ? addr_saved : icpu_adr_i; +// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot; +assign if_stall = !icpu_err_i & !icpu_ack_i & !saved; +assign genpc_refetch = saved & icpu_ack_i; +assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot; +assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot; +assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot; + +// +// Flag for saved insn/address +// +always @(posedge clk ) + if (rst) + saved <= 1'b0; + else if (flushpipe) + saved <= 1'b0; + else if (icpu_ack_i & if_freeze & !saved) + saved <= 1'b1; + else if (!if_freeze) + saved <= 1'b0; + +// +// Store fetched instruction +// +always @(posedge clk ) + if (rst) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (icpu_ack_i & if_freeze & !saved) + insn_saved <= icpu_dat_i; + else if (!if_freeze) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + +// +// Store fetched instruction's address +// +always @(posedge clk ) + if (rst) + addr_saved <= 32'h00000000; + else if (flushpipe) + addr_saved <= 32'h00000000; + else if (icpu_ack_i & if_freeze & !saved) + addr_saved <= icpu_adr_i; + else if (!if_freeze) + addr_saved <= icpu_adr_i; + +endmodule + +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction decode //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Majority of instruction decoding is performed here. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.12 2005/01/07 09:31:07 andreje +// sign/zero extension for l.sfxxi instructions corrected +// +// Revision 1.11 2004/06/08 18:17:36 lampret +// Non-functional changes. Coding style fixes. +// +// Revision 1.10 2004/05/09 19:49:04 lampret +// Added some l.cust5 custom instructions as example +// +// Revision 1.9 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.8.4.1 2004/02/11 01:40:11 lampret +// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. +// +// Revision 1.8 2003/04/24 00:16:07 lampret +// No functional changes. Added defines to disable implementation of multiplier/MAC +// +// Revision 1.7 2002/09/07 05:42:02 lampret +// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. +// +// Revision 1.6 2002/03/29 15:16:54 lampret +// Some of the warnings fixed. +// +// Revision 1.5 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.4 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.3 2002/01/18 14:21:43 lampret +// Fixed 'the NPC single-step fix'. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.14 2001/11/30 18:59:17 simons +// force_dslot_fetch does not work - allways zero. +// +// Revision 1.13 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.12 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.11 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.10 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.9 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + + +module or1200_ctrl( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken, + rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op, + wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op, + cust5_op, cust5_limm, + multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap, + force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe,du_hwbkpt, except_illegal +); + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input wb_freeze; +input flushpipe; +input [31:0] if_insn; +output [31:0] ex_insn; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input branch_taken; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb; +output rf_rda; +output rf_rdb; +output [`OR1200_ALUOP_WIDTH-1:0] alu_op; +output [`OR1200_MACOP_WIDTH-1:0] mac_op; +output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +output [31:0] wb_insn; +output [31:0] simm; +output [31:2] branch_addrofs; +output [31:0] lsu_addrofs; +output [`OR1200_SEL_WIDTH-1:0] sel_a; +output [`OR1200_SEL_WIDTH-1:0] sel_b; +output [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +output [`OR1200_COMPOP_WIDTH-1:0] comp_op; +output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +output [4:0] cust5_op; +output [5:0] cust5_limm; +output [15:0] spr_addrimm; +input wbforw_valid; +input du_hwbkpt; +output sig_syscall; +output sig_trap; +output force_dslot_fetch; +output no_more_dslot; +output ex_void; +output id_macrc_op; +output ex_macrc_op; +output rfe; +output except_illegal; + +// +// Internal wires and regs +// +reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; +reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +reg [`OR1200_ALUOP_WIDTH-1:0] alu_op; + +reg [`OR1200_MACOP_WIDTH-1:0] mac_op; +reg ex_macrc_op; + +reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +reg [31:0] id_insn; +reg [31:0] ex_insn; +reg [31:0] wb_insn; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw; +reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +reg [31:0] lsu_addrofs; +reg [`OR1200_SEL_WIDTH-1:0] sel_a; +reg [`OR1200_SEL_WIDTH-1:0] sel_b; +reg sel_imm; +reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +reg [`OR1200_COMPOP_WIDTH-1:0] comp_op; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +reg imm_signextend; +reg [15:0] spr_addrimm; +reg sig_syscall; +reg sig_trap; +reg except_illegal; +wire id_void; + +// +// Register file read addresses +// +assign rf_addra = if_insn[20:16]; +assign rf_addrb = if_insn[15:11]; +assign rf_rda = if_insn[31]; +assign rf_rdb = if_insn[30]; + +// +// Force fetch of delay slot instruction when jump/branch is preceeded by load/store +// instructions +// +// SIMON +// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op)); +assign force_dslot_fetch = 1'b0; +assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE); +assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16]; +assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]; + +// +// Sign/Zero extension of immediates +// +assign simm = (imm_signextend == 1'b1) ? {{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]}; + +// +// Sign extension of branch offset +// +assign branch_addrofs = {{ex_insn[25]},{ex_insn[25]},{ex_insn[25]},{ex_insn[25]},{ex_insn[25]}, ex_insn[25:0]}; + +// +// l.macrc in ID stage +// + +assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16]; + +// +// cust5_op, cust5_limm (L immediate) +// +assign cust5_op = ex_insn[4:0]; +assign cust5_limm = ex_insn[10:5]; + +// +// +// +assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE); + +// +// Generation of sel_a +// +always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if ((id_insn[20:16] == rf_addrw) && rfwb_op[0]) + sel_a = `OR1200_SEL_EX_FORW; + else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid) + sel_a = `OR1200_SEL_WB_FORW; + else + sel_a = `OR1200_SEL_RF; + +// +// Generation of sel_b +// +always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if (sel_imm) + sel_b = `OR1200_SEL_IMM; + else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0]) + sel_b = `OR1200_SEL_EX_FORW; + else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid) + sel_b = `OR1200_SEL_WB_FORW; + else + sel_b = `OR1200_SEL_RF; + +// +// l.macrc in EX stage +// + +always @(posedge clk ) begin + if (rst) + ex_macrc_op <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + ex_macrc_op <= 1'b0; + else if (!ex_freeze) + ex_macrc_op <= id_macrc_op; +end +// +// Decode of spr_addrimm +// +always @(posedge clk ) begin + if (rst) + spr_addrimm <= 16'h0000; + else if (!ex_freeze & id_freeze | flushpipe) + spr_addrimm <= 16'h0000; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + // l.mfspr + `OR1200_OR32_MFSPR: + spr_addrimm <= id_insn[15:0]; + // l.mtspr + default: + spr_addrimm <= {id_insn[25:21], id_insn[10:0]}; + endcase + end +end + +// +// Decode of multicycle +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.lwz + `OR1200_OR32_LWZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbz + `OR1200_OR32_LBZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbs + `OR1200_OR32_LBS: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhz + `OR1200_OR32_LHZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhs + `OR1200_OR32_LHS: + multicycle = `OR1200_TWO_CYCLES; + + // l.sw + `OR1200_OR32_SW: + multicycle = `OR1200_TWO_CYCLES; + + // l.sb + `OR1200_OR32_SB: + multicycle = `OR1200_TWO_CYCLES; + + // l.sh + `OR1200_OR32_SH: + multicycle = `OR1200_TWO_CYCLES; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + multicycle = id_insn[9:8]; + + // Single cycle instructions + default: begin + multicycle = `OR1200_ONE_CYCLE; + end + + endcase + +end + +// +// Decode of imm_signextend +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.addi + `OR1200_OR32_ADDI: + imm_signextend = 1'b1; + + // l.addic + `OR1200_OR32_ADDIC: + imm_signextend = 1'b1; + + // l.xori + `OR1200_OR32_XORI: + imm_signextend = 1'b1; + + // l.muli + + `OR1200_OR32_MULI: + imm_signextend = 1'b1; + + + // l.maci + + `OR1200_OR32_MACI: + imm_signextend = 1'b1; + + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + imm_signextend = 1'b1; + + // Instructions with no or zero extended immediate + default: begin + imm_signextend = 1'b0; + end + +endcase + +end + +// +// LSU addr offset +// +always @(lsu_op or ex_insn) begin + lsu_addrofs[10:0] = ex_insn[10:0]; + case(lsu_op) // synopsys parallel_case + `OR1200_LSUOP_SB : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + `OR1200_LSUOP_SH : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + + `OR1200_LSUOP_SW : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + + default : + lsu_addrofs[31:11] = {{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}}, ex_insn[15:11]}; + endcase +end + +// +// Register file write address +// +always @(posedge clk) begin + if (rst) + rf_addrw <= 5'b00000; + else if (!ex_freeze & id_freeze) + rf_addrw <= 5'b00000; + else if (!ex_freeze) + case (pre_branch_op) // synopsys parallel_case +`OR1200_BRANCHOP_BAL: + rf_addrw <= 5'b01001; // link register r9 + `OR1200_BRANCHOP_JR: + rf_addrw <= 5'b01001; + default: + rf_addrw <= id_insn[25:21]; + endcase +end + +// +// rf_addrw in wb stage (used in forwarding logic) +// +always @(posedge clk ) begin + if (rst) + wb_rfaddrw <= 5'b00000; + else if (!wb_freeze) + wb_rfaddrw <= rf_addrw; +end + +// +// Instruction latch in id_insn +// +always @(posedge clk ) begin + if (rst) + id_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + id_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // id_insn[16] must be 1 + else if (!id_freeze) begin + id_insn <= if_insn; + + end +end + +// +// Instruction latch in ex_insn +// +always @(posedge clk ) begin + if (rst) + ex_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (!ex_freeze & id_freeze | flushpipe) + ex_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // ex_insn[16] must be 1 + else if (!ex_freeze) begin + ex_insn <= id_insn; + end +end + +// +// Instruction latch in wb_insn +// +always @(posedge clk ) begin + if (rst) + wb_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + wb_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // wb_insn[16] must be 1 + else if (!wb_freeze) begin + wb_insn <= ex_insn; + end +end + +// +// Decode of sel_imm +// +always @(posedge clk ) begin + if (rst) + sel_imm <= 1'b0; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // j.jalr + `OR1200_OR32_JALR: + sel_imm <= 1'b0; + + // l.jr + `OR1200_OR32_JR: + sel_imm <= 1'b0; + + // l.rfe + `OR1200_OR32_RFE: + sel_imm <= 1'b0; + + // l.mfspr + `OR1200_OR32_MFSPR: + sel_imm <= 1'b0; + + // l.mtspr + `OR1200_OR32_MTSPR: + sel_imm <= 1'b0; + + // l.sys, l.brk and all three sync insns + `OR1200_OR32_XSYNC: + sel_imm <= 1'b0; + + // l.mac/l.msb + + `OR1200_OR32_MACMSB: + sel_imm <= 1'b0; + + // l.sw + `OR1200_OR32_SW: + sel_imm <= 1'b0; + + // l.sb + `OR1200_OR32_SB: + sel_imm <= 1'b0; + + // l.sh + `OR1200_OR32_SH: + sel_imm <= 1'b0; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + sel_imm <= 1'b0; + + // SFXX instructions + `OR1200_OR32_SFXX: + sel_imm <= 1'b0; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + sel_imm <= 1'b0; + + + // l.nop + `OR1200_OR32_NOP: + sel_imm <= 1'b0; + + // All instructions with immediates + default: begin + sel_imm <= 1'b1; + end + + endcase + + end +end + +// +// Decode of except_illegal +// +always @(posedge clk ) begin + if (rst) + except_illegal <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + except_illegal <= 1'b0; + else if (!ex_freeze) begin + except_illegal <= 1'b1; + end +end + +// +// Decode of alu_op +// +always @(posedge clk ) begin + if (rst) + alu_op <= `OR1200_ALUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + alu_op <= `OR1200_ALUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + alu_op <= `OR1200_ALUOP_IMM; + + // j.jal + `OR1200_OR32_JAL: + alu_op <= `OR1200_ALUOP_IMM; + + // l.bnf + `OR1200_OR32_BNF: + alu_op <= `OR1200_ALUOP_NOP; + + // l.bf + `OR1200_OR32_BF: + alu_op <= `OR1200_ALUOP_NOP; + + // l.movhi + `OR1200_OR32_MOVHI: + alu_op <= `OR1200_ALUOP_MOVHI; + + // l.mfspr + `OR1200_OR32_MFSPR: + alu_op <= `OR1200_ALUOP_MFSR; + + // l.mtspr + `OR1200_OR32_MTSPR: + alu_op <= `OR1200_ALUOP_MTSR; + + // l.addi + `OR1200_OR32_ADDI: + alu_op <= `OR1200_ALUOP_ADD; + + // l.addic + `OR1200_OR32_ADDIC: + alu_op <= `OR1200_ALUOP_ADDC; + + // l.andi + `OR1200_OR32_ANDI: + alu_op <= `OR1200_ALUOP_AND; + + // l.ori + `OR1200_OR32_ORI: + alu_op <= `OR1200_ALUOP_OR; + + // l.xori + `OR1200_OR32_XORI: + alu_op <= `OR1200_ALUOP_XOR; + + // l.muli + + `OR1200_OR32_MULI: + alu_op <= `OR1200_ALUOP_MUL; + + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + alu_op <= `OR1200_ALUOP_SHROT; + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + alu_op <= `OR1200_ALUOP_COMP; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + alu_op <= id_insn[3:0]; + + // SFXX instructions + `OR1200_OR32_SFXX: + alu_op <= `OR1200_ALUOP_COMP; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + alu_op <= `OR1200_ALUOP_CUST5; + // Default + default: begin + alu_op <= `OR1200_ALUOP_NOP; + end + + endcase + + end +end + +// +// Decode of mac_op + +always @(posedge clk ) begin + if (rst) + mac_op <= `OR1200_MACOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + mac_op <= `OR1200_MACOP_NOP; + else if (!ex_freeze) + case (id_insn[31:26]) // synopsys parallel_case + + // l.maci + `OR1200_OR32_MACI: + mac_op <= `OR1200_MACOP_MAC; + + // l.nop + `OR1200_OR32_MACMSB: + mac_op <= id_insn[1:0]; + + // Illegal and OR1200 unsupported instructions + default: begin + mac_op <= `OR1200_MACOP_NOP; + end + + endcase + else + mac_op <= `OR1200_MACOP_NOP; +end + +// +// Decode of shrot_op +// +always @(posedge clk ) begin + if (rst) + shrot_op <= `OR1200_SHROTOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + shrot_op <= `OR1200_SHROTOP_NOP; + else if (!ex_freeze) begin + shrot_op <= id_insn[7:6]; + end +end + +// +// Decode of rfwb_op +// +always @(posedge clk ) begin + if (rst) + rfwb_op <= `OR1200_RFWBOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + rfwb_op <= `OR1200_RFWBOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // j.jal + `OR1200_OR32_JAL: + rfwb_op <= `OR1200_RFWBOP_LR; + + // j.jalr + `OR1200_OR32_JALR: + rfwb_op <= `OR1200_RFWBOP_LR; + + // l.movhi + `OR1200_OR32_MOVHI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.mfspr + `OR1200_OR32_MFSPR: + rfwb_op <= `OR1200_RFWBOP_SPRS; + + // l.lwz + `OR1200_OR32_LWZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lbz + `OR1200_OR32_LBZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lbs + `OR1200_OR32_LBS: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lhz + `OR1200_OR32_LHZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lhs + `OR1200_OR32_LHS: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.addi + `OR1200_OR32_ADDI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.addic + `OR1200_OR32_ADDIC: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.andi + `OR1200_OR32_ANDI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.ori + `OR1200_OR32_ORI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.xori + `OR1200_OR32_XORI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.muli + + `OR1200_OR32_MULI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // Instructions w/o register-file write-back + default: begin + rfwb_op <= `OR1200_RFWBOP_NOP; + end + + endcase + end +end + +// +// Decode of pre_branch_op +// +always @(posedge clk ) begin + if (rst) + pre_branch_op <= `OR1200_BRANCHOP_NOP; + else if (flushpipe) + pre_branch_op <= `OR1200_BRANCHOP_NOP; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + pre_branch_op <= `OR1200_BRANCHOP_BAL; + + // j.jal + `OR1200_OR32_JAL: + pre_branch_op <= `OR1200_BRANCHOP_BAL; + + // j.jalr + `OR1200_OR32_JALR: + pre_branch_op <= `OR1200_BRANCHOP_JR; + + // l.jr + `OR1200_OR32_JR: + pre_branch_op <= `OR1200_BRANCHOP_JR; + + // l.bnf + `OR1200_OR32_BNF: + pre_branch_op <= `OR1200_BRANCHOP_BNF; + + // l.bf + `OR1200_OR32_BF: + pre_branch_op <= `OR1200_BRANCHOP_BF; + + // l.rfe + `OR1200_OR32_RFE: + pre_branch_op <= `OR1200_BRANCHOP_RFE; + + // Non branch instructions + default: begin + pre_branch_op <= `OR1200_BRANCHOP_NOP; + end + endcase + end +end + +// +// Generation of branch_op +// +always @(posedge clk ) + if (rst) + branch_op <= `OR1200_BRANCHOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + branch_op <= `OR1200_BRANCHOP_NOP; + else if (!ex_freeze) + branch_op <= pre_branch_op; + +// +// Decode of lsu_op +// +always @(posedge clk ) begin + if (rst) + lsu_op <= `OR1200_LSUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + lsu_op <= `OR1200_LSUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.lwz + `OR1200_OR32_LWZ: + lsu_op <= `OR1200_LSUOP_LWZ; + + // l.lbz + `OR1200_OR32_LBZ: + lsu_op <= `OR1200_LSUOP_LBZ; + + // l.lbs + `OR1200_OR32_LBS: + lsu_op <= `OR1200_LSUOP_LBS; + + // l.lhz + `OR1200_OR32_LHZ: + lsu_op <= `OR1200_LSUOP_LHZ; + + // l.lhs + `OR1200_OR32_LHS: + lsu_op <= `OR1200_LSUOP_LHS; + + // l.sw + `OR1200_OR32_SW: + lsu_op <= `OR1200_LSUOP_SW; + + // l.sb + `OR1200_OR32_SB: + lsu_op <= `OR1200_LSUOP_SB; + + // l.sh + `OR1200_OR32_SH: + lsu_op <= `OR1200_LSUOP_SH; + + // Non load/store instructions + default: begin + lsu_op <= `OR1200_LSUOP_NOP; + end + endcase + end +end + +// +// Decode of comp_op +// +always @(posedge clk ) begin + if (rst) begin + comp_op <= 4'b0000; + end else if (!ex_freeze & id_freeze | flushpipe) + comp_op <= 4'b0000; + else if (!ex_freeze) + comp_op <= id_insn[24:21]; +end + +// +// Decode of l.sys +// +always @(posedge clk ) begin + if (rst) + sig_syscall <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_syscall <= 1'b0; + else if (!ex_freeze) begin + + sig_syscall <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000}); + end +end + +// +// Decode of l.trap +// +always @(posedge clk ) begin + if (rst) + sig_trap <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_trap <= 1'b0; + else if (!ex_freeze) begin + + sig_trap <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010}) + | du_hwbkpt; + end +end + +endmodule + + +module or1200_rf( + // Clock and reset + clk, rst, + + // Write i/f + supv, wb_freeze, addrw, dataw,id_freeze, we, flushpipe, + + // Read i/f + addra, rda, dataa, addrb,rdb, datab, + // Debug + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +//parameter aw = `OR1200_OPERAND_WIDTH; +//parameter dw= `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Write i/f +// +input supv; +input wb_freeze; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addrw; +input [`OR1200_OPERAND_WIDTH-1:0] dataw; +input we; +input flushpipe; + +// +// Read i/f +// +input id_freeze; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addra; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addrb; +output [`OR1200_OPERAND_WIDTH-1:0] dataa; +output [`OR1200_OPERAND_WIDTH-1:0] datab; +input rda; +input rdb; + +// +// SPR access for debugging purposes +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// +wire [`OR1200_OPERAND_WIDTH-1:0] from_rfa; +wire [`OR1200_OPERAND_WIDTH-1:0] from_rfb; +reg [`OR1200_OPERAND_WIDTH:0] dataa_saved; +reg [`OR1200_OPERAND_WIDTH:0] datab_saved; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; +wire rf_we; +wire spr_valid; +wire rf_ena; +wire rf_enb; +reg rf_we_allow; + +// +// SPR access is valid when spr_cs is asserted and +// SPR address matches GPR addresses +// +assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF); + +// +// SPR data output is always from RF A +// +assign spr_dat_o = from_rfa; + +// +// Operand A comes from RF or from saved A register +// +assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa; + +// +// Operand B comes from RF or from saved B register +// +assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb; + +// +// RF A read address is either from SPRS or normal from CPU control +// +assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra; + +// +// RF write address is either from SPRS or normal from CPU control +// +assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw; + +// +// RF write data is either from SPRS or normal from CPU datapath +// +assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; + +// +// RF write enable is either from SPRS or normal from CPU control +// +always @(posedge clk) + if (rst) + rf_we_allow <= 1'b1; + else if (~wb_freeze) + rf_we_allow <= ~flushpipe; + +assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw)); + +// +// CS RF A asserted when instruction reads operand A and ID stage +// is not stalled +// +assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils +// assign rf_ena = 1'b1; // does not work with single-stepping +//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils + +// +// CS RF B asserted when instruction reads operand B and ID stage +// is not stalled +// +assign rf_enb = rdb & ~id_freeze | spr_valid; +// assign rf_enb = 1'b1; +//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils + +// +// Stores operand from RF_A into temp reg when pipeline is frozen +// +always @(posedge clk ) + if (rst) begin + dataa_saved <=33'b000000000000000000000000000000000; + end + else if (id_freeze & !dataa_saved[32]) begin + dataa_saved <= {1'b1, from_rfa}; + end + else if (!id_freeze) + dataa_saved <=33'b000000000000000000000000000000000; + +// +// Stores operand from RF_B into temp reg when pipeline is frozen +// +always @(posedge clk) + if (rst) begin + datab_saved <= 33'b000000000000000000000000000000000; + end + else if (id_freeze & !datab_saved[32]) begin + datab_saved <= {1'b1, from_rfb}; + end + else if (!id_freeze) + datab_saved <= 33'b000000000000000000000000000000000; + + + + +// Black-box memory instead of the or1200 memory implementation + +wire const_one; +wire const_zero; +assign const_one = 1'b1; +assign const_zero = 1'b0; +wire [31:0] const_zero_data; +assign const_zero_data = 32'b00000000000000000000000000000000; +wire [31:0] dont_care_out; +wire [31:0] dont_care_out2; + +dual_port_ram rf_a( + + .clk (clk), + .we1(const_zero), + .we2(rf_we), + .data1(const_zero_data), + .data2(rf_dataw), + .out1(from_rfa), + .out2 (dont_care_out), + .addr1(rf_addra), + .addr2(rf_addrw)); +// +// Instantiation of register file two-port RAM A +// +/* +or1200_tpram_32x32 rf_a( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_ena), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(rf_addra), + .di_a(32'h00000000), + .do_a(from_rfa), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); +*/ +// +// Instantiation of register file two-port RAM B +// + +dual_port_ram rf_b( + .clk (clk), + .we1(const_zero), + .we2(rf_we), + .data1(const_zero_data), + .data2(rf_dataw), + .out1(from_rfb), + .out2 (dont_care_out2), + .addr1(addrb), + .addr2(rf_addrw)); +/* +or1200_tpram_32x32 rf_b( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_enb), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(addrb), + .di_a(32'h00000000), + .do_a(from_rfb), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); +*/ +wire unused; +assign unused = |spr_addr; +endmodule + + + +module or1200_operandmuxes( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw, + simm, sel_a, sel_b, operand_a, operand_b, muxed_b +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input [`OR1200_OPERAND_WIDTH-1:0] rf_dataa; +input [`OR1200_OPERAND_WIDTH-1:0] rf_datab; +input [`OR1200_OPERAND_WIDTH-1:0] ex_forw; +input [`OR1200_OPERAND_WIDTH-1:0] wb_forw; +input [`OR1200_OPERAND_WIDTH-1:0] simm; +input [`OR1200_SEL_WIDTH-1:0] sel_a; +input [`OR1200_SEL_WIDTH-1:0] sel_b; +output [`OR1200_OPERAND_WIDTH-1:0] operand_a; +output [`OR1200_OPERAND_WIDTH-1:0] operand_b; +output [`OR1200_OPERAND_WIDTH-1:0] muxed_b; + +// +// Internal wires and regs +// +reg [`OR1200_OPERAND_WIDTH-1:0] operand_a; +reg [`OR1200_OPERAND_WIDTH-1:0] operand_b; +reg [`OR1200_OPERAND_WIDTH-1:0] muxed_a; +reg [`OR1200_OPERAND_WIDTH-1:0] muxed_b; +reg saved_a; +reg saved_b; + +// +// Operand A register +// +always @(posedge clk ) begin + if (rst) begin + operand_a <= 32'b0000000000000000000000000000; + saved_a <= 1'b0; + end else if (!ex_freeze && id_freeze && !saved_a) begin + operand_a <= muxed_a; + saved_a <= 1'b1; + end else if (!ex_freeze && !saved_a) begin + operand_a <= muxed_a; + end else if (!ex_freeze && !id_freeze) + saved_a <= 1'b0; +end + +// +// Operand B register +// +always @(posedge clk ) begin + if (rst) begin + operand_b <= 32'b0000000000000000000000000000; + saved_b <= 1'b0; + end else if (!ex_freeze && id_freeze && !saved_b) begin + operand_b <= muxed_b; + saved_b <= 1'b1; + end else if (!ex_freeze && !saved_b) begin + operand_b <= muxed_b; + end else if (!ex_freeze && !id_freeze) + saved_b <= 1'b0; +end + +// +// Forwarding logic for operand A register +// +always @(ex_forw or wb_forw or rf_dataa or sel_a) begin + + case (sel_a) + `OR1200_SEL_EX_FORW: + muxed_a = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_a = wb_forw; + default: + muxed_a = rf_dataa; + endcase +end + +// +// Forwarding logic for operand B register +// +always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin + + case (sel_b) // synopsys parallel_case + + `OR1200_SEL_IMM: + muxed_b = simm; + `OR1200_SEL_EX_FORW: + muxed_b = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_b = wb_forw; + default: + muxed_b = rf_datab; + endcase +end + +endmodule + + + + + +module or1200_alu( + a, b, mult_mac_result, macrc_op, + alu_op, shrot_op, comp_op, + cust5_op, cust5_limm, + result, flagforw, flag_we, + cyforw, cy_we, flag,k_carry +); + +// +// I/O +// +input [32-1:0] a; +input [32-1:0] b; +input [32-1:0] mult_mac_result; +input macrc_op; +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; +input [2-1:0] shrot_op; +input [4-1:0] comp_op; +input [4:0] cust5_op; +input [5:0] cust5_limm; +output [32-1:0] result; +output flagforw; +output flag_we; +output cyforw; +output cy_we; +input k_carry; +input flag; + +// +// Internal wires and regs +// +reg [32-1:0] result; +reg [32-1:0] shifted_rotated; +reg [32-1:0] result_cust5; +reg flagforw; +reg flagcomp; +reg flag_we; +reg cy_we; +wire [32-1:0] comp_a; +wire [32-1:0] comp_b; + +wire a_eq_b; +wire a_lt_b; + +wire [32-1:0] result_sum; + +wire [32-1:0] result_csum; +wire cy_csum; + +wire [32-1:0] result_and; +wire cy_sum; +reg cyforw; + +// +// Combinatorial logic +// +assign comp_a [31:3]= a[31] ^ comp_op[3]; +assign comp_a [2:0] = a[30:0]; + +assign comp_b [31:3] = b[31] ^ comp_op[3] ; +assign comp_b [2:0] = b[32-2:0]; + +assign a_eq_b = (comp_a == comp_b); +assign a_lt_b = (comp_a < comp_b); + +assign cy_sum= a + b; +assign result_sum = a+b; +assign cy_csum =a + b + {32'b00000000000000000000000000000000, k_carry}; +assign result_csum = a + b + {32'b00000000000000000000000000000000, k_carry}; + +assign result_and = a & b; + + + +// Central part of the ALU +// +always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) +begin + + case (alu_op) // synopsys parallel_case + + 4'b1111: begin + result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0; + end + `OR1200_ALUOP_CUST5 : begin + result = result_cust5; + end + `OR1200_ALUOP_SHROT : begin + result = shifted_rotated; + end + `OR1200_ALUOP_ADD : begin + result = result_sum; + end + + `OR1200_ALUOP_ADDC : begin + result = result_csum; + end + + `OR1200_ALUOP_SUB : begin + result = a - b; + end + `OR1200_ALUOP_XOR : begin + result = a ^ b; + end + `OR1200_ALUOP_OR : begin + result = a | b; + end + `OR1200_ALUOP_IMM : begin + result = b; + end + `OR1200_ALUOP_MOVHI : begin + if (macrc_op) begin + result = mult_mac_result; + end + else begin + result = b << 16; + end + end + + `OR1200_ALUOP_MUL : begin + result = mult_mac_result; + end + + 4'b1110: begin + result = flag ? a : b; + end + + default: + begin + result=result_and; + end + endcase +end + +// +// l.cust5 custom instructions +// +// Examples for move byte, set bit and clear bit +// +always @(cust5_op or cust5_limm or a or b) begin + case (cust5_op) // synopsys parallel_case + 5'h1 : begin + case (cust5_limm[1:0]) + 2'h0: result_cust5 = {a[31:8], b[7:0]}; + 2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]}; + 2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]}; + 2'h3: result_cust5 = {b[7:0], a[23:0]}; + endcase + end + 5'h2 : + result_cust5 = a | (1 << 4); + 5'h3 : + result_cust5 = a & (32'b11111111111111111111111111111111^ (cust5_limm)); +// +// *** Put here new l.cust5 custom instructions *** +// + default: begin + result_cust5 = a; + end + endcase +end + +// +// Generate flag and flag write enable +// +always @(alu_op or result_sum or result_and or flagcomp) begin + case (alu_op) // synopsys parallel_case + + `OR1200_ALUOP_ADD : begin + flagforw = (result_sum == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_ADDC : begin + flagforw = (result_csum == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_AND: begin + flagforw = (result_and == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_COMP: begin + flagforw = flagcomp; + flag_we = 1'b1; + end + default: begin + flagforw = 1'b0; + flag_we = 1'b0; + end + endcase +end + +// +// Generate SR[CY] write enable +// +always @(alu_op or cy_sum + + + ) begin + case (alu_op) // synopsys parallel_case + + `OR1200_ALUOP_ADD : begin + cyforw = cy_sum; + cy_we = 1'b1; + end + + `OR1200_ALUOP_ADDC: begin + cyforw = cy_csum; + cy_we = 1'b1; + end + + default: begin + cyforw = 1'b0; + cy_we = 1'b0; + end + endcase +end + +// +// Shifts and rotation +// +always @(shrot_op or a or b) begin + case (shrot_op) // synopsys parallel_case + 2'b00 : + shifted_rotated = (a << 2); + `OR1200_SHROTOP_SRL : + shifted_rotated = (a >> 2); + + + `OR1200_SHROTOP_ROR : + shifted_rotated = (a << 1'b1); + default: + shifted_rotated = (a << 1); + endcase +end + +// +// First type of compare implementation +// +always @(comp_op or a_eq_b or a_lt_b) begin + case(comp_op[2:0]) // synopsys parallel_case + `OR1200_COP_SFEQ: + flagcomp = a_eq_b; + `OR1200_COP_SFNE: + flagcomp = ~a_eq_b; + `OR1200_COP_SFGT: + flagcomp = ~(a_eq_b | a_lt_b); + `OR1200_COP_SFGE: + flagcomp = ~a_lt_b; + `OR1200_COP_SFLT: + flagcomp = a_lt_b; + `OR1200_COP_SFLE: + flagcomp = a_eq_b | a_lt_b; + default: + flagcomp = 1'b0; + endcase +end + +// + +endmodule + + + + +module or1200_mult_mac( + // Clock and reset + clk, rst, + + // Multiplier/MAC interface + ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r, + + // SPR interface + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Multiplier/MAC interface +// +input ex_freeze; +input id_macrc_op; +input macrc_op; +input [`OR1200_OPERAND_WIDTH-1:0] a; +input [`OR1200_OPERAND_WIDTH-1:0] b; +input [`OR1200_MACOP_WIDTH-1:0] mac_op; +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; +output [`OR1200_OPERAND_WIDTH-1:0] result; +output mac_stall_r; + +// +// SPR interface +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// + +reg [`OR1200_OPERAND_WIDTH-1:0] result; +reg [2*`OR1200_OPERAND_WIDTH-1:0] mul_prod_r; + +wire [2*`OR1200_OPERAND_WIDTH-1:0] mul_prod; +wire [`OR1200_MACOP_WIDTH-1:0] mac_op; + +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1; +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2; +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3; +reg mac_stall_r; +reg [2*`OR1200_OPERAND_WIDTH-1:0] mac_r; + +wire [`OR1200_OPERAND_WIDTH-1:0] x; +wire [`OR1200_OPERAND_WIDTH-1:0] y; +wire spr_maclo_we; +wire spr_machi_we; +wire alu_op_div_divu; +wire alu_op_div; +reg div_free; + +wire [`OR1200_OPERAND_WIDTH-1:0] div_tmp; +reg [5:0] div_cntr; + + +// +// Combinatorial logic +// + +assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR]; +assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR]; +assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32]; + +assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h00000000; +assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h00000000; +assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV); +assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU); +assign div_tmp = mul_prod_r[63:32] - y; + + + + +// +// Select result of current ALU operation to be forwarded +// to next instruction and to WB stage +// +always @(alu_op or mul_prod_r or mac_r or a or b) + case(alu_op) + + `OR1200_ALUOP_DIV: + result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0]; + `OR1200_ALUOP_DIVU: + begin + result = mul_prod_r[31:0]; + end + + `OR1200_ALUOP_MUL: begin + result = mul_prod_r[31:0]; + end + default: + + result = mac_r[31:0]; + + endcase + +// +// Instantiation of the multiplier +// + +// doing an implicit multiply here +assign mul_prod = x * y; +/* +or1200_gmultp2_32x32 or1200_gmultp2_32x32( + .X(x), + .Y(y), + .RST(rst), + .CLK(clk), + .P(mul_prod) +); +*/ + + +// +// Registered output from the multiplier and +// an optional divider +// +always @(posedge clk) + if (rst) begin + mul_prod_r <= 64'h0000000000000000; + div_free <= 1'b1; + + div_cntr <= 6'b000000; + + end + + else if (|div_cntr) begin + if (div_tmp[31]) + mul_prod_r <= {mul_prod_r[62:0], 1'b0}; + else + mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1}; + div_cntr <= div_cntr - 1'b1; + end + else if (alu_op_div_divu && div_free) begin + mul_prod_r <= {31'b0000000000000000000000000000000, x[31:0], 1'b0}; + div_cntr <= 6'b100000; + div_free <= 1'b0; + end + + else if (div_free | !ex_freeze) begin + mul_prod_r <= mul_prod[63:0]; + div_free <= 1'b1; + end + + +// Propagation of l.mac opcode +// +always @(posedge clk) + if (rst) + mac_op_r1 <= 2'b00; + else + mac_op_r1 <= mac_op; + +// +// Propagation of l.mac opcode +// +always @(posedge clk) + if (rst) + mac_op_r2 <= 2'b00; + else + mac_op_r2 <= mac_op_r1; + +// +// Propagation of l.mac opcode +// +always @(posedge clk ) + if (rst) + mac_op_r3 <= 2'b00; + else + mac_op_r3 <= mac_op_r2; + +// +// Implementation of MAC +// +always @(posedge clk) + if (rst) + mac_r <= 64'h0000000000000000; + + else if (spr_maclo_we) + mac_r[31:0] <= spr_dat_i; + else if (spr_machi_we) + mac_r[63:32] <= spr_dat_i; + + else if (mac_op_r3 == `OR1200_MACOP_MAC) + mac_r <= mac_r + mul_prod_r; + else if (mac_op_r3 == `OR1200_MACOP_MSB) + mac_r <= mac_r - mul_prod_r; + else if (macrc_op & !ex_freeze) + mac_r <= 64'h0000000000000000; + +// +// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions +// in EX stage (e.g. inside multiplier) +// This stall signal is also used by the divider. +// + +wire unused; +assign unused = |spr_addr; +always @( posedge clk) + if (rst) + mac_stall_r <= 1'b0; + else + mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op + + | (|div_cntr) + + ; + + + + +endmodule + + + + +module or1200_sprs( + // Clk & Rst + clk, rst, + + // Internal CPU interface + addrbase, addrofs, dat_i, alu_op, + flagforw, flag_we, flag, cyforw, cy_we, carry, to_wbmux, + + du_addr, du_dat_du, du_read, + du_write, du_dat_cpu, + + spr_addr,spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_dat_o, spr_cs, spr_we, + + epcr_we, eear_we,esr_we, pc_we,epcr, eear, esr, except_started, + + sr_we, to_sr, sr,branch_op + +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O Ports +// + +// +// Internal CPU interface +// +input clk; // Clock +input rst; // Reset +input flagforw; // From ALU +input flag_we; // From ALU +output flag; // SR[F] +input cyforw; // From ALU +input cy_we; // From ALU +output carry; // SR[CY] +input [`OR1200_OPERAND_WIDTH-1:0] addrbase; // SPR base address +input [15:0] addrofs; // SPR offset +input [`OR1200_OPERAND_WIDTH-1:0] dat_i; // SPR write data +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation +input [`OR1200_OPERAND_WIDTH-1:0] epcr; // EPCR0 +input [`OR1200_OPERAND_WIDTH-1:0] eear; // EEAR0 +input [`OR1200_SR_WIDTH-1:0] esr; // ESR0 +input except_started; // Exception was started +output [`OR1200_OPERAND_WIDTH-1:0] to_wbmux; // For l.mfspr +output epcr_we; // EPCR0 write enable +output eear_we; // EEAR0 write enable +output esr_we; // ESR0 write enable +output pc_we; // PC write enable +output sr_we; // Write enable SR +output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR +output [`OR1200_SR_WIDTH-1:0] sr; // SR +input [31:0] spr_dat_cfgr; // Data from CFGR +input [31:0] spr_dat_rf; // Data from RF +input [31:0] spr_dat_npc; // Data from NPC +input [31:0] spr_dat_ppc; // Data from PPC +input [31:0] spr_dat_mac; // Data from MAC + +// +// To/from other RISC units +// +input [31:0] spr_dat_pic; // Data from PIC +input [31:0] spr_dat_tt; // Data from TT +input [31:0] spr_dat_pm; // Data from PM +input [31:0] spr_dat_dmmu; // Data from DMMU +input [31:0] spr_dat_immu; // Data from IMMU +input [31:0] spr_dat_du; // Data from DU +output [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // Data to unit +output [31:0] spr_cs; // Unit select +output spr_we; // SPR write enable + +// +// To/from Debug Unit +// +input [`OR1200_OPERAND_WIDTH-1:0] du_addr; // Address +input [`OR1200_OPERAND_WIDTH-1:0] du_dat_du; // Data from DU to SPRS +input du_read; // Read qualifier +input du_write; // Write qualifier +output [`OR1200_OPERAND_WIDTH-1:0] du_dat_cpu; // Data from SPRS to DU + +// +// Internal regs & wires +// +reg [`OR1200_SR_WIDTH-1:0] sr; // SR +reg write_spr; // Write SPR +reg read_spr; // Read SPR +reg [`OR1200_OPERAND_WIDTH-1:0] to_wbmux; // For l.mfspr +wire cfgr_sel; // Select for cfg regs +wire rf_sel; // Select for RF +wire npc_sel; // Select for NPC +wire ppc_sel; // Select for PPC +wire sr_sel; // Select for SR +wire epcr_sel; // Select for EPCR0 +wire eear_sel; // Select for EEAR0 +wire esr_sel; // Select for ESR0 +wire [31:0] sys_data; // Read data from system SPRs +wire du_access; // Debug unit access +wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation +reg [31:0] unqualified_cs; // Unqualified chip selects + +// +// Decide if it is debug unit access +// +assign du_access = du_read | du_write; + +// +// Generate sprs opcode +// +assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op; + +// +// Generate SPR address from base address and offset +// OR from debug unit address +// +assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs}; + +// +// SPR is written by debug unit or by l.mtspr +// +assign spr_dat_o = du_write ? du_dat_du : dat_i; + +// +// debug unit data input: +// - write into debug unit SPRs by debug unit itself +// - read of SPRS by debug unit +// - write into debug unit SPRs by l.mtspr +// +assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i; + +// +// Write into SPRs when l.mtspr +// +assign spr_we = du_write | write_spr; + +// +// Qualify chip selects +// +assign spr_cs = unqualified_cs & {{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr}}; + +// +// Decoding of groups +// +always @(spr_addr) + case (spr_addr[15:11]) + 5'b00000: unqualified_cs = 32'b00000000000000000000000000000001; + 5'b00001: unqualified_cs = 32'b00000000000000000000000000000010; + 5'b00010: unqualified_cs = 32'b00000000000000000000000000000100; + 5'b00011: unqualified_cs = 32'b00000000000000000000000000001000; + 5'b00100: unqualified_cs = 32'b00000000000000000000000000010000; + 5'b00101: unqualified_cs = 32'b00000000000000000000000000100000; + 5'b00110: unqualified_cs = 32'b00000000000000000000000001000000; + 5'b00111: unqualified_cs = 32'b00000000000000000000000010000000; + 5'b01000: unqualified_cs = 32'b00000000000000000000000100000000; + 5'b01001: unqualified_cs = 32'b00000000000000000000001000000000; + 5'b01010: unqualified_cs = 32'b00000000000000000000010000000000; + 5'b01011: unqualified_cs = 32'b00000000000000000000100000000000; + 5'b01100: unqualified_cs = 32'b00000000000000000001000000000000; + 5'b01101: unqualified_cs = 32'b00000000000000000010000000000000; + 5'b01110: unqualified_cs = 32'b00000000000000000100000000000000; + 5'b01111: unqualified_cs = 32'b00000000000000001000000000000000; + 5'b10000: unqualified_cs = 32'b00000000000000010000000000000000; + 5'b10001: unqualified_cs = 32'b00000000000000100000000000000000; + 5'b10010: unqualified_cs = 32'b00000000000001000000000000000000; + 5'b10011: unqualified_cs = 32'b00000000000010000000000000000000; + 5'b10100: unqualified_cs = 32'b00000000000100000000000000000000; + 5'b10101: unqualified_cs = 32'b00000000001000000000000000000000; + 5'b10110: unqualified_cs = 32'b00000000010000000000000000000000; + 5'b10111: unqualified_cs = 32'b00000000100000000000000000000000; + 5'b11000: unqualified_cs = 32'b00000001000000000000000000000000; + 5'b11001: unqualified_cs = 32'b00000010000000000000000000000000; + 5'b11010: unqualified_cs = 32'b00000100000000000000000000000000; + 5'b11011: unqualified_cs = 32'b00001000000000000000000000000000; + 5'b11100: unqualified_cs = 32'b00010000000000000000000000000000; + 5'b11101: unqualified_cs = 32'b00100000000000000000000000000000; + 5'b11110: unqualified_cs = 32'b01000000000000000000000000000000; + 5'b11111: unqualified_cs = 32'b10000000000000000000000000000000; + endcase + +// +// SPRs System Group +// + +// +// What to write into SR +// +assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] : + (write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}: + sr[`OR1200_SR_FO:`OR1200_SR_OV]; +assign to_sr[`OR1200_SR_CY] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] : + cy_we ? cyforw : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] : + sr[`OR1200_SR_CY]; +assign to_sr[`OR1200_SR_F] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] : + flag_we ? flagforw : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] : + sr[`OR1200_SR_F]; +assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]: + sr[`OR1200_SR_CE:`OR1200_SR_SM]; + +// +// Selects for system SPRs +// +assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR)); +assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF)); +assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC)); +assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC)); +assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR)); +assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR)); +assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR)); +assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR)); + +// +// Write enables for system SPRs +// +assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we; +assign pc_we = (write_spr && (npc_sel | ppc_sel)); +assign epcr_we = (write_spr && epcr_sel); +assign eear_we = (write_spr && eear_sel); +assign esr_we = (write_spr && esr_sel); + +// +// Output from system SPRs +// +assign sys_data = (spr_dat_cfgr & {{read_spr & cfgr_sel}}) | + (spr_dat_rf & {{read_spr & rf_sel}}) | + (spr_dat_npc & {{read_spr & npc_sel}}) | + (spr_dat_ppc & {{read_spr & ppc_sel}}) | + ({{{16'b0000000000000000}},sr} & {{read_spr & sr_sel}}) | + (epcr & {{read_spr & epcr_sel}}) | + (eear & {{read_spr & eear_sel}}) | + ({{{16'b0000000000000000}},esr} & {{read_spr & esr_sel}}); + +// +// Flag alias +// +assign flag = sr[`OR1200_SR_F]; + +// +// Carry alias +// +assign carry = sr[`OR1200_SR_CY]; + +// +// Supervision register +// +always @(posedge clk) + if (rst) + sr <= {1'b1, `OR1200_SR_EPH_DEF, {{13'b0000000000000}}, 1'b1}; + else if (except_started) begin + sr[`OR1200_SR_SM] <= 1'b1; + sr[`OR1200_SR_TEE] <= 1'b0; + sr[`OR1200_SR_IEE] <= 1'b0; + sr[`OR1200_SR_DME] <= 1'b0; + sr[`OR1200_SR_IME] <= 1'b0; + end + else if (sr_we) + sr <= to_sr[`OR1200_SR_WIDTH-1:0]; + +// +// MTSPR/MFSPR interface +// +always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or + spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin + case (sprs_op) // synopsys parallel_case + `OR1200_ALUOP_MTSR : begin + write_spr = 1'b1; + read_spr = 1'b0; + to_wbmux = 32'b00000000000000000000000000000000; + end + `OR1200_ALUOP_MFSR : begin + case (spr_addr[15:11]) // synopsys parallel_case + `OR1200_SPR_GROUP_TT: + to_wbmux = spr_dat_tt; + `OR1200_SPR_GROUP_PIC: + to_wbmux = spr_dat_pic; + `OR1200_SPR_GROUP_PM: + to_wbmux = spr_dat_pm; + `OR1200_SPR_GROUP_DMMU: + to_wbmux = spr_dat_dmmu; + `OR1200_SPR_GROUP_IMMU: + to_wbmux = spr_dat_immu; + `OR1200_SPR_GROUP_MAC: + to_wbmux = spr_dat_mac; + `OR1200_SPR_GROUP_DU: + to_wbmux = spr_dat_du; + `OR1200_SPR_GROUP_SYS: + to_wbmux = sys_data; + default: + to_wbmux = 32'b00000000000000000000000000000000; + endcase + write_spr = 1'b0; + read_spr = 1'b1; + end + default : begin + write_spr = 1'b0; + read_spr = 1'b0; + to_wbmux = 32'b00000000000000000000000000000000; + end + endcase +end + +endmodule + + + + + +`define OR1200_NO_FREEZE 3'b000 +`define OR1200_FREEZE_BYDC 3'b001 +`define OR1200_FREEZE_BYMULTICYCLE 3'b010 +`define OR1200_WAIT_LSU_TO_FINISH 3'b011 +`define OR1200_WAIT_IC 3'b100 + +// +// Freeze logic (stalls CPU pipeline, ifetcher etc.) +// +module or1200_freeze( + // Clock and reset + clk, rst, + + // Internal i/f + multicycle, flushpipe, extend_flush, lsu_stall, if_stall, + lsu_unstall, + force_dslot_fetch, abort_ex, du_stall, mac_stall, + genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, + icpu_ack_i, icpu_err_i +); + +// +// I/O +// +input clk; +input rst; +input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +input flushpipe; +input extend_flush; +input lsu_stall; +input if_stall; +input lsu_unstall; +input force_dslot_fetch; +input abort_ex; +input du_stall; +input mac_stall; +output genpc_freeze; +output if_freeze; +output id_freeze; +output ex_freeze; +output wb_freeze; +input icpu_ack_i; +input icpu_err_i; + +// +// Internal wires and regs +// +wire multicycle_freeze; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt; +reg flushpipe_r; + +// +// Pipeline freeze +// +// Rules how to create freeze signals: +// 1. Not overwriting pipeline stages: +// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more +// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never +// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc. +// +// 2. Inserting NOPs in the middle of pipeline only if supported: +// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted. +// This way NOP is asserted from stage ID into EX stage. +// +//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall; +assign genpc_freeze = du_stall | flushpipe_r; +assign if_freeze = id_freeze | extend_flush; +//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall; +assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall; +assign ex_freeze = wb_freeze; +//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall; +assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex; + +// +// registered flushpipe +// +always @(posedge clk ) + if (rst) + flushpipe_r <= 1'b0; + else if (icpu_ack_i | icpu_err_i) +// else if (!if_stall) + flushpipe_r <= flushpipe; + else if (!flushpipe) + flushpipe_r <= 1'b0; + +// +// Multicycle freeze +// +assign multicycle_freeze = |multicycle_cnt; + +// +// Multicycle counter +// +always @(posedge clk ) + if (rst) + multicycle_cnt <= 2'b00; + else if (|multicycle_cnt) + multicycle_cnt <= multicycle_cnt - 2'b01; + else if (|multicycle & !ex_freeze) + multicycle_cnt <= multicycle; + +endmodule + + + + +`define OR1200_EXCEPTFSM_WIDTH 3 + +`define OR1200_EXCEPTFSM_IDLE 3'b000 +`define OR1200_EXCEPTFSM_FLU1 3'b001 +`define OR1200_EXCEPTFSM_FLU2 3'b010 +`define OR1200_EXCEPTFSM_FLU3 3'b011 +`define OR1200_EXCEPTFSM_FLU5 3'b101 +`define OR1200_EXCEPTFSM_FLU4 3'b100 + +// +// Exception recognition and sequencing +// + +module or1200_except( + // Clock and reset + clk, rst, + + // Internal i/f + sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault, + sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick, + branch_taken,icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, + genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall, + if_pc, id_pc, lr_sav, flushpipe, extend_flush, except_type, except_start, + except_started, except_stop, ex_void, + spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, + esr, lsu_addr, sr_we, to_sr, sr, abort_ex +); + +// +// I/O +// +input clk; +input rst; +input sig_ibuserr; +input sig_dbuserr; +input sig_illegal; +input sig_align; +input sig_range; +input sig_dtlbmiss; +input sig_dmmufault; +input sig_int; +input sig_syscall; +input sig_trap; +input sig_itlbmiss; +input sig_immufault; +input sig_tick; +input branch_taken; +input genpc_freeze; +input id_freeze; +input ex_freeze; +input wb_freeze; +input if_stall; +input [31:0] if_pc; +output [31:0] id_pc; +output [31:2] lr_sav; +input [31:0] datain; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +input epcr_we; +input eear_we; +input esr_we; +input pc_we; +output [31:0] epcr; +output [31:0] eear; +output [`OR1200_SR_WIDTH-1:0] esr; +input [`OR1200_SR_WIDTH-1:0] to_sr; +input sr_we; +input [`OR1200_SR_WIDTH-1:0] sr; +input [31:0] lsu_addr; +output flushpipe; +output extend_flush; +output [`OR1200_EXCEPT_WIDTH-1:0] except_type; +output except_start; +output except_started; +output [12:0] except_stop; +input ex_void; +output [31:0] spr_dat_ppc; +output [31:0] spr_dat_npc; +output abort_ex; +input icpu_ack_i; +input icpu_err_i; +input dcpu_ack_i; +input dcpu_err_i; + +// +// Internal regs and wires +// +reg [`OR1200_EXCEPT_WIDTH-1:0] except_type; +reg [31:0] id_pc; +reg [31:0] ex_pc; +reg [31:0] wb_pc; +reg [31:0] epcr; +reg [31:0] eear; +reg [`OR1200_SR_WIDTH-1:0] esr; +reg [2:0] id_exceptflags; +reg [2:0] ex_exceptflags; +reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state; +reg extend_flush; +reg extend_flush_last; +reg ex_dslot; +reg delayed1_ex_dslot; +reg delayed2_ex_dslot; +wire except_started; +wire [12:0] except_trig; +wire except_flushpipe; +reg [2:0] delayed_iee; +reg [2:0] delayed_tee; +wire int_pending; +wire tick_pending; + +// +// Simple combinatorial logic +// +assign except_started = extend_flush & except_start; +assign lr_sav = ex_pc[31:2]; +assign spr_dat_ppc = wb_pc; +assign spr_dat_npc = ex_void ? id_pc : ex_pc; +assign except_start = (except_type != 4'b0000) & extend_flush; +assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we; +assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we; +assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions + +// +// Order defines exception detection priority +// +assign except_trig = { + tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE], + int_pending & ~du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE], + sig_align & ~du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & ~du_dsr[`OR1200_DU_DSR_RE], + sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; +assign except_stop = { + tick_pending & du_dsr[`OR1200_DU_DSR_TTE], + int_pending & du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & du_dsr[`OR1200_DU_DSR_IIE], + sig_align & du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & du_dsr[`OR1200_DU_DSR_RE], + sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + id_pc <= 32'b00000000000000000000000000000000; + id_exceptflags <= 3'b000; + end + else if (flushpipe) begin + id_pc <= 32'h00000000; + id_exceptflags <= 3'b000; + end + else if (!id_freeze) begin + id_pc <= if_pc; + id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault }; + end +end + +// +// delayed_iee +// +// SR[IEE] should not enable interrupts right away +// when it is restored with l.rfe. Instead delayed_iee +// together with SR[IEE] enables interrupts once +// pipeline is again ready. +// +always @(posedge clk) + if (rst) + delayed_iee <= 3'b000; + else if (!sr[`OR1200_SR_IEE]) + delayed_iee <= 3'b000; + else + delayed_iee <= {delayed_iee[1:0], 1'b1}; + +// +// delayed_tee +// +// SR[TEE] should not enable tick exceptions right away +// when it is restored with l.rfe. Instead delayed_tee +// together with SR[TEE] enables tick exceptions once +// pipeline is again ready. +// +always @( posedge clk) + if (rst) + delayed_tee <= 3'b000; + else if (!sr[`OR1200_SR_TEE]) + delayed_tee <= 3'b000; + else + delayed_tee <= {delayed_tee[1:0], 1'b1}; + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + ex_dslot <= 1'b0; + ex_pc <= 32'd0; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= 1'b0; + delayed2_ex_dslot <= 1'b0; + end + else if (flushpipe) begin + ex_dslot <= 1'b0; + ex_pc <= 32'h00000000; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= 1'b0; + delayed2_ex_dslot <= 1'b0; + end + else if (!ex_freeze & id_freeze) begin + ex_dslot <= 1'b0; + ex_pc <= id_pc; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= ex_dslot; + delayed2_ex_dslot <= delayed1_ex_dslot; + end + else if (!ex_freeze) begin + ex_dslot <= branch_taken; + ex_pc <= id_pc; + ex_exceptflags <= id_exceptflags; + delayed1_ex_dslot <= ex_dslot; + delayed2_ex_dslot <= delayed1_ex_dslot; + end +end + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + wb_pc <= 32'b00000000000000000000000000000000; + end + else if (!wb_freeze) begin + wb_pc <= ex_pc; + end +end + +// +// Flush pipeline +// +assign flushpipe = except_flushpipe | pc_we | extend_flush; + +// +// We have started execution of exception handler: +// 1. Asserted for 3 clock cycles +// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler +// +assign except_flushpipe = |except_trig & ~|state; + +// +// Exception FSM that sequences execution of exception handler +// +// except_type signals which exception handler we start fetching in: +// 1. Asserted in next clock cycle after exception is recognized +// +always @(posedge clk ) begin + if (rst) begin + state <= `OR1200_EXCEPTFSM_IDLE; + except_type <= 4'b0000; + extend_flush <= 1'b0; + epcr <= 32'b00000000000000000000000000000000; + eear <= 32'b00000000000000000000000000000000; + esr <= {{1'b1, 1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0}, {1'b1}}; + extend_flush_last <= 1'b0; + end + else begin + + case (state) + `OR1200_EXCEPTFSM_IDLE: + if (except_flushpipe) begin + state <= `OR1200_EXCEPTFSM_FLU1; + extend_flush <= 1'b1; + esr <= sr_we ? to_sr : sr; + + if (except_trig[12] == 1) + begin + except_type <= `OR1200_EXCEPT_TICK; + epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else if (except_trig[12] == 0 && except_trig[11] == 0) + begin + except_type <= `OR1200_EXCEPT_INT; + epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else if (except_trig[12] == 0 && except_trig[11] == 0 && except_trig[10] == 1) + begin + except_type <= `OR1200_EXCEPT_ITLBMISS; +// +// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?) +// eear <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + eear <= ex_dslot ? ex_pc : ex_pc; + epcr <= ex_dslot ? wb_pc : ex_pc; +// eear <= ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else + begin + except_type <= 4'b0000; + end + end + else if (pc_we) begin + state <= `OR1200_EXCEPTFSM_FLU1; + extend_flush <= 1'b1; + end + else begin + if (epcr_we) + epcr <= datain; + if (eear_we) + eear <= datain; + if (esr_we) + esr <= {1'b1, datain[`OR1200_SR_WIDTH-2:0]}; + end + `OR1200_EXCEPTFSM_FLU1: + if (icpu_ack_i | icpu_err_i | genpc_freeze) + state <= `OR1200_EXCEPTFSM_FLU2; + `OR1200_EXCEPTFSM_FLU2: + state <= `OR1200_EXCEPTFSM_FLU3; + `OR1200_EXCEPTFSM_FLU3: + begin + state <= `OR1200_EXCEPTFSM_FLU4; + end + `OR1200_EXCEPTFSM_FLU4: begin + state <= `OR1200_EXCEPTFSM_FLU5; + extend_flush <= 1'b0; + extend_flush_last <= 1'b0; // damjan + end + + default: begin + if (!if_stall && !id_freeze) begin + state <= `OR1200_EXCEPTFSM_IDLE; + except_type <= 4'b0000; + extend_flush_last <= 1'b0; + end + end + endcase + end +end + +wire unused; +assign unused = sig_range | sig_syscall | sig_trap | dcpu_ack_i| dcpu_err_i | du_dsr | lsu_addr; +endmodule + + + + + +module or1200_cfgr( + // RISC Internal Interface + spr_addr, spr_dat_o +); + +// +// RISC Internal Interface +// +input [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // SPR Read Data + +// +// Internal wires & registers +// +reg [31:0] spr_dat_o; // SPR Read Data + + + +// +// Implementation of VR, UPR and configuration registers +// +always @(spr_addr) + if (~|spr_addr[31:4]) + + case(spr_addr[3:0]) // synopsys parallel_case + `OR1200_SPRGRP_SYS_VR: begin + spr_dat_o[5:0] = `OR1200_VR_REV; + spr_dat_o[16:6] = `OR1200_VR_RES1; + spr_dat_o[23:17] = `OR1200_VR_CFG; + spr_dat_o[31:24] = `OR1200_VR_VER; + end + `OR1200_SPRGRP_SYS_UPR: begin + spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP; + spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP; + spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP; + spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP; + spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP; + spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP; + spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP; + spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP; + spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP; + spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP; + spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP; + spr_dat_o[23:11] = `OR1200_UPR_RES1; + spr_dat_o[31:24] = `OR1200_UPR_CUP; + end + `OR1200_SPRGRP_SYS_CPUCFGR: begin + spr_dat_o[3:0] = `OR1200_CPUCFGR_NSGF; + spr_dat_o[`OR1200_CPUCFGR_HGF_BITS] = `OR1200_CPUCFGR_HGF; + spr_dat_o[`OR1200_CPUCFGR_OB32S_BITS] = `OR1200_CPUCFGR_OB32S; + spr_dat_o[`OR1200_CPUCFGR_OB64S_BITS] = `OR1200_CPUCFGR_OB64S; + spr_dat_o[`OR1200_CPUCFGR_OF32S_BITS] = `OR1200_CPUCFGR_OF32S; + spr_dat_o[`OR1200_CPUCFGR_OF64S_BITS] = `OR1200_CPUCFGR_OF64S; + spr_dat_o[`OR1200_CPUCFGR_OV64S_BITS] = `OR1200_CPUCFGR_OV64S; + spr_dat_o[31:10] = `OR1200_CPUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DMMUCFGR: begin + spr_dat_o[1:0] = `OR1200_DMMUCFGR_NTW; + spr_dat_o[4:2] = `OR1200_DMMUCFGR_NTS; + spr_dat_o[7:5] = `OR1200_DMMUCFGR_NAE; + spr_dat_o[`OR1200_DMMUCFGR_CRI_BITS] = `OR1200_DMMUCFGR_CRI; + spr_dat_o[`OR1200_DMMUCFGR_PRI_BITS] = `OR1200_DMMUCFGR_PRI; + spr_dat_o[`OR1200_DMMUCFGR_TEIRI_BITS] = `OR1200_DMMUCFGR_TEIRI; + spr_dat_o[`OR1200_DMMUCFGR_HTR_BITS] = `OR1200_DMMUCFGR_HTR; + spr_dat_o[31:12] = `OR1200_DMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_IMMUCFGR: begin + spr_dat_o[1:0] = `OR1200_IMMUCFGR_NTW; + spr_dat_o[4:2] = `OR1200_IMMUCFGR_NTS; + spr_dat_o[7:5] = `OR1200_IMMUCFGR_NAE; + spr_dat_o[`OR1200_IMMUCFGR_CRI_BITS] = `OR1200_IMMUCFGR_CRI; + spr_dat_o[`OR1200_IMMUCFGR_PRI_BITS] = `OR1200_IMMUCFGR_PRI; + spr_dat_o[`OR1200_IMMUCFGR_TEIRI_BITS] = `OR1200_IMMUCFGR_TEIRI; + spr_dat_o[`OR1200_IMMUCFGR_HTR_BITS] = `OR1200_IMMUCFGR_HTR; + spr_dat_o[31:12] = `OR1200_IMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCCFGR: begin + spr_dat_o[2:0] = `OR1200_DCCFGR_NCW; + spr_dat_o[6:3] = `OR1200_DCCFGR_NCS; + spr_dat_o[`OR1200_DCCFGR_CBS_BITS] = `OR1200_DCCFGR_CBS; + spr_dat_o[`OR1200_DCCFGR_CWS_BITS] = `OR1200_DCCFGR_CWS; + spr_dat_o[`OR1200_DCCFGR_CCRI_BITS] = `OR1200_DCCFGR_CCRI; + spr_dat_o[`OR1200_DCCFGR_CBIRI_BITS] = `OR1200_DCCFGR_CBIRI; + spr_dat_o[`OR1200_DCCFGR_CBPRI_BITS] = `OR1200_DCCFGR_CBPRI; + spr_dat_o[`OR1200_DCCFGR_CBLRI_BITS] = `OR1200_DCCFGR_CBLRI; + spr_dat_o[`OR1200_DCCFGR_CBFRI_BITS] = `OR1200_DCCFGR_CBFRI; + spr_dat_o[`OR1200_DCCFGR_CBWBRI_BITS] = `OR1200_DCCFGR_CBWBRI; + spr_dat_o[31:15] = `OR1200_DCCFGR_RES1; + end + `OR1200_SPRGRP_SYS_ICCFGR: begin + spr_dat_o[2:0] = `OR1200_ICCFGR_NCW; + spr_dat_o[6:3] = `OR1200_ICCFGR_NCS; + spr_dat_o[`OR1200_ICCFGR_CBS_BITS] = `OR1200_ICCFGR_CBS; + spr_dat_o[`OR1200_ICCFGR_CWS_BITS] = `OR1200_ICCFGR_CWS; + spr_dat_o[`OR1200_ICCFGR_CCRI_BITS] = `OR1200_ICCFGR_CCRI; + spr_dat_o[`OR1200_ICCFGR_CBIRI_BITS] = `OR1200_ICCFGR_CBIRI; + spr_dat_o[`OR1200_ICCFGR_CBPRI_BITS] = `OR1200_ICCFGR_CBPRI; + spr_dat_o[`OR1200_ICCFGR_CBLRI_BITS] = `OR1200_ICCFGR_CBLRI; + spr_dat_o[`OR1200_ICCFGR_CBFRI_BITS] = `OR1200_ICCFGR_CBFRI; + spr_dat_o[`OR1200_ICCFGR_CBWBRI_BITS] = `OR1200_ICCFGR_CBWBRI; + spr_dat_o[31:15] = `OR1200_ICCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCFGR: begin + spr_dat_o[2:0] = `OR1200_DCFGR_NDP; + spr_dat_o[3] = `OR1200_DCFGR_WPCI; + spr_dat_o[31:4] = `OR1200_DCFGR_RES1; + end + default: spr_dat_o = 32'h00000000; + endcase + + + +// + +endmodule + +module or1200_wbmux( + // Clock and reset + clk, rst, + + // Internal i/f + wb_freeze, rfwb_op, + muxin_a, muxin_b, muxin_c, muxin_d, + muxout, muxreg, muxreg_valid +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Internal i/f +// +input wb_freeze; +input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +input [32-1:0] muxin_a; +input [32-1:0] muxin_b; +input [32-1:0] muxin_c; +input [32-1:0] muxin_d; +output [32-1:0] muxout; +output [32-1:0] muxreg; +output muxreg_valid; + +// +// Internal wires and regs +// +reg [32-1:0] muxout; +reg [32-1:0] muxreg; +reg muxreg_valid; + +// +// Registered output from the write-back multiplexer +// +always @(posedge clk) begin + if (rst) begin + muxreg <= 32'b00000000000000000000000000000000; + muxreg_valid <= 1'b0; + end + else if (!wb_freeze) begin + muxreg <= muxout; + muxreg_valid <= rfwb_op[0]; + end +end + +// +// Write-back multiplexer +// +always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin + case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) + 2'b00: muxout = muxin_a; + 2'b01: begin + muxout = muxin_b; + end + 2'b10: begin + muxout = muxin_c; + end + 2'b11: begin + muxout = muxin_d + 32'b00000000000000000000000000001000; + end + endcase +end + +endmodule + + + +module or1200_lsu( + + // Internal i/f + addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall, + du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr, + + // External i/f to DC + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i +); + +//parameter dw = `OR1200_OPERAND_WIDTH; +//parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Internal i/f +// +input [31:0] addrbase; +input [31:0] addrofs; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [`OR1200_OPERAND_WIDTH-1:0] lsu_datain; +output [`OR1200_OPERAND_WIDTH-1:0] lsu_dataout; +output lsu_stall; +output lsu_unstall; +input du_stall; +output except_align; +output except_dtlbmiss; +output except_dmmufault; +output except_dbuserr; + +// +// External i/f to DC +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; + +// +// Internal wires/regs +// +reg [3:0] dcpu_sel_o; + +// +// Internal I/F assignments +// +assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o; +assign lsu_unstall = dcpu_ack_i; +assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0] + | ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0]; +assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE); +assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE); +assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE); + +// +// External I/F assignments +// +assign dcpu_adr_o = addrbase + addrofs; +assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op; +assign dcpu_we_o = lsu_op[3]; +assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE; +always @(lsu_op or dcpu_adr_o) + case({lsu_op, dcpu_adr_o[1:0]}) + {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111; + {`OR1200_LSUOP_LBZ, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_LBZ, 2'b01}: dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_LBZ, 2'b10}: dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_LBZ, 2'b11}: dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_LHZ, 2'b00}: dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_LHZ, 2'b10}: dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_LWZ, 2'b00}: dcpu_sel_o = 4'b1111; + {4'b1111, 2'b00} : dcpu_sel_o = 4'b1111; + default : dcpu_sel_o = 4'b0000; + endcase + +// +// Instantiation of Memory-to-regfile aligner +// +or1200_mem2reg or1200_mem2reg( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .memdata(dcpu_dat_i), + .regdata(lsu_dataout) +); + +// +// Instantiation of Regfile-to-memory aligner +// +or1200_reg2mem or1200_reg2mem( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .regdata(lsu_datain), + .memdata(dcpu_dat_o) +); + +endmodule + + + + +module or1200_reg2mem(addr, lsu_op, regdata, memdata); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [32-1:0] regdata; +output [32-1:0] memdata; + +// +// Internal regs and wires +// +reg [7:0] memdata_hh; +reg [7:0] memdata_hl; +reg [7:0] memdata_lh; +reg [7:0] memdata_ll; + +assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll}; + +// +// Mux to memdata[31:24] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0]; + {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8]; + default : memdata_hh = regdata[31:24]; + endcase +end + +// +// Mux to memdata[23:16] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16]; + default : memdata_hl = regdata[7:0]; + endcase +end + +// +// Mux to memdata[15:8] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0]; + default : memdata_lh = regdata[15:8]; + endcase +end + +// +// Mux to memdata[7:0] +// +always @(regdata) + memdata_ll = regdata[7:0]; + +endmodule + + + +module or1200_mem2reg(addr, lsu_op, memdata, regdata); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [32-1:0] memdata; +output [32-1:0] regdata; +wire [32-1:0] regdata; + +// +// In the past faster implementation of mem2reg (today probably slower) +// +reg [7:0] regdata_hh; +reg [7:0] regdata_hl; +reg [7:0] regdata_lh; +reg [7:0] regdata_ll; +reg [32-1:0] aligned; +reg [3:0] sel_byte0, sel_byte1, + sel_byte2, sel_byte3; + +assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll}; + +// +// Byte select 0 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b011, 2'b00}: // lbz/lbs 0 + sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3 + {3'b011, 2'b01}: +sel_byte0 = `OR1200_M2R_BYTE2; + {3'b101, 2'b00}: // lhz/lhs 0 + sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2 + {3'b011, 2'b10}: // lbz/lbs 2 + sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1 + default: // all other cases + sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0 + endcase +end + +// +// Byte select 1 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: // lbz + sel_byte1 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: // lbs 0 + sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: // lbs 2 + sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + {3'b100, 2'b00}: // lhz/lhs 0 + sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3 + default: // all other cases + sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1 + endcase +end + +// +// Byte select 2 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: +sel_byte2 = `OR1200_M2R_ZERO; // lbz + {3'b100, 2'b00}: // lhz + sel_byte2 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: + sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b101, 2'b00}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: + sel_byte2 = `OR1200_M2R_EXTB1; + {3'b101, 2'b10}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2 + endcase +end + +// +// Byte select 3 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: + sel_byte3 = `OR1200_M2R_ZERO; // zero extend // lbz + {3'b100, 2'b00}: // lhz + sel_byte3 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: +sel_byte3 = `OR1200_M2R_EXTB3; + {3'b101, 2'b00}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: + sel_byte3 = `OR1200_M2R_EXTB1; + {3'b101, 2'b10}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3 + endcase +end + +// +// Byte 0 +// +always @(sel_byte0 or memdata) + begin + case(sel_byte0) + `OR1200_M2R_BYTE0: begin + regdata_ll = memdata[7:0]; + end + `OR1200_M2R_BYTE1: begin + regdata_ll = memdata[15:8]; + end + `OR1200_M2R_BYTE2: begin + regdata_ll = memdata[23:16]; + end + + default: begin + + regdata_ll = memdata[31:24]; + end + endcase +end + +// +// Byte 1 +// +always @(sel_byte1 or memdata) begin + + case(sel_byte1) + + `OR1200_M2R_ZERO: begin + regdata_lh = 8'h00; + end + `OR1200_M2R_BYTE1: begin + regdata_lh = memdata[15:8]; + end + `OR1200_M2R_BYTE3: begin + regdata_lh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_lh = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_lh = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_lh = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + default: begin + + regdata_lh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Byte 2 +// +always @(sel_byte2 or memdata) begin + + + case(sel_byte2) + + `OR1200_M2R_ZERO: begin + regdata_hl = 8'h00; + end + `OR1200_M2R_BYTE2: begin + regdata_hl = memdata[23:16]; + end + `OR1200_M2R_EXTB0: begin + regdata_hl = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hl = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hl = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + default: begin + regdata_hl = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Byte 3 +// +always @(sel_byte3 or memdata) begin + + case(sel_byte3) + `OR1200_M2R_ZERO: begin + regdata_hh = 8'h00; + end + `OR1200_M2R_BYTE3: begin + regdata_hh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_hh = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hh = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hh = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + `OR1200_M2R_EXTB3: begin + regdata_hh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Straightforward implementation of mem2reg +// + +// reg [32-1:0] regdata; + +// +// Alignment +// +always @(addr or memdata) begin + case(addr) + 2'b00: + aligned = memdata; + 2'b01: + aligned = {memdata[23:0], 8'b00000000}; + 2'b10: + aligned = {memdata[15:0], 16'b0000000000000000}; + 2'b11: + aligned = {memdata[7:0], 24'b000000000000000000000000}; + endcase +end + +// +// Bytes +// +/* +always @(lsu_op or aligned) begin + case(lsu_op) + `OR1200_LSUOP_LBZ: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = 24'b000000000000000000000000; + end + `OR1200_LSUOP_LBS: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = {24'b000000000000000000000000}; + end + `OR1200_LSUOP_LHZ: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = 16'b0000000000000000; + end + `OR1200_LSUOP_LHS: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = {16'b0000000000000000}; + end + default: + regdata = aligned; + endcase +end +*/ +wire[8:0] unused_signal; +assign unused_signal = lsu_op; +endmodule + +//--------------------------------------- +// A dual-port RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module dual_port_ram ( + input clk, + input we1, + input we2, + input [`OR1200_REGFILE_ADDR_WIDTH - 1 : 0] addr1, + input [`OR1200_OPERAND_WIDTH - 1 : 0] data1, + output [`OR1200_OPERAND_WIDTH - 1 : 0] out1, + input [`OR1200_REGFILE_ADDR_WIDTH - 1 : 0] addr2, + input [`OR1200_OPERAND_WIDTH - 1 : 0] data2, + output [`OR1200_OPERAND_WIDTH - 1 : 0] out2 +); + + reg [`OR1200_OPERAND_WIDTH - 1 : 0] ram[2**`OR1200_REGFILE_ADDR_WIDTH - 1 : 0]; + reg [`OR1200_OPERAND_WIDTH - 1 : 0] data_out1; + reg [`OR1200_OPERAND_WIDTH - 1 : 0] data_out2; + + assign out1 = data_out1; + assign out2 = data_out2; + + // If writen enable 1 is activated, + // data1 will be loaded through addr1 + // Otherwise, data will be read out through addr1 + always @(posedge clk) begin + if (we1) begin + ram[addr1] <= data1; + end else begin + data_out1 <= ram[addr1]; + end + end + + // If writen enable 2 is activated, + // data1 will be loaded through addr2 + // Otherwise, data will be read out through addr2 + always @(posedge clk) begin + if (we2) begin + ram[addr2] <= data2; + end else begin + data_out2 <= ram[addr2]; + end + end +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v new file mode 100755 index 000000000..0f4a66b43 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v @@ -0,0 +1,3003 @@ + module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, tm3_clk_v0, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource); + + output rgwant_addr; + wire rgwant_addr; + output rgwant_data; + wire rgwant_data; + output rgread_ready; + wire rgread_ready; + input rgaddr_ready; + input rgdata_ready; + + input rgwant_read; + input[63:0] rgdatain; + output[63:0] rgdataout; + wire[63:0] rgdataout; + input[17:0] rgaddrin; + input[31:0] rgCont; + output[31:0] rgStat; + wire[31:0] rgStat; + input[31:0] rgCfgData; + output rgwant_CfgData; + wire rgwant_CfgData; + input rgCfgData_ready; + + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input tm3_clk_v0; + + output[63:0] fbdata; + wire[63:0] fbdata; + output fbdatavalid; + wire fbdatavalid; + input fbnextscanline; + output[1:0] raygroup01; + wire[1:0] raygroup01; + output raygroupvalid01; + wire raygroupvalid01; + input busy01; + output[1:0] raygroup10; + wire[1:0] raygroup10; + + output raygroupvalid10; + wire raygroupvalid10; + input busy10; + input globalreset; + output[31:0] rgData; + wire[31:0] rgData; + output[3:0] rgAddr; + wire[3:0] rgAddr; + output[2:0] rgWE; + wire[2:0] rgWE; + output rgAddrValid; + wire rgAddrValid; + + input rgDone; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + + wire[2:0] statepeek2; + wire as01; + wire ack01; + + wire[3:0] addr01; + wire[47:0] dir01; + wire[47:0] dir; + wire[47:0] sramdatal; + wire wantDir; + wire dirReady; + wire dirReadyl; + wire[14:0] address; + wire[30:0] cyclecounter; + + wire nas01; + wire nas10; + wire go; + reg page; + wire[2:0] statepeekct; + // result Signals + wire valid01; + wire valid10; + wire[15:0] id01a; + wire[15:0] id01b; + wire[15:0] id01c; + wire[15:0] id10a; + + wire[15:0] id10b; + wire[15:0] id10c; + wire hit01a; + wire hit01b; + wire hit01c; + wire hit10a; + wire hit10b; + wire hit10c; + wire[7:0] u01a; + wire[7:0] u01b; + wire[7:0] u01c; + wire[7:0] v01a; + + wire[7:0] v01b; + wire[7:0] v01c; + wire[7:0] u10a; + wire[7:0] u10b; + wire[7:0] u10c; + wire[7:0] v10a; + wire[7:0] v10b; + wire[7:0] v10c; + wire wantwriteback; + wire writebackack; + wire[63:0] writebackdata; + wire[17:0] writebackaddr; + + wire[17:0] nextaddr01; + // Shading Signals + wire[63:0] shadedata; + wire[15:0] triID; + wire wantshadedata; + wire shadedataready; + // CfgData Signals + wire[27:0] origx; + wire[27:0] origy; + wire[27:0] origz; + wire[15:0] m11; + wire[15:0] m12; + + wire[15:0] m13; + wire[15:0] m21; + wire[15:0] m22; + wire[15:0] m23; + wire[15:0] m31; + wire[15:0] m32; + wire[15:0] m33; + wire[20:0] bkcolour; + // Texture signals + wire[20:0] texinfo; + wire[3:0] texaddr; + wire[63:0] texel; + + wire[17:0] texeladdr; + wire wanttexel; + wire texelready; + // Frame Buffer Read Signals + wire fbpage; + // debug signals + wire wantcfg; + wire debugglobalreset; + + assign rgwant_CfgData = wantcfg ; + + onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, tm3_clk_v0); + + always @(posedge tm3_clk_v0) + begin + if (globalreset == 1'b1) + begin + page <= 1'b1 ; // Reset to 1 such that first flip sets to 0 + end + else + + begin + page <= ~page ; + end + end + assign fbpage = ~page ; + + matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], tm3_clk_v0); + + delay1x3 dir01delay(dirReady, dirReadyl, tm3_clk_v0); + rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, tm3_clk_v0); + + rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, tm3_clk_v0); + raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, tm3_clk_v0, statepeek2); + + raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, tm3_clk_v0, statepeekct); + resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, tm3_clk_v0); + assign debugglobalreset = globalreset | go ; + resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, tm3_clk_v0); + assign rgStat[30:0] = cyclecounter ; + endmodule + + +module delay1x3 (datain, dataout, clk); + + input datain; + output dataout; + wire dataout; + input clk; + + reg buff0; + reg buff1; + reg buff2; + + assign dataout = buff2 ; + + always @(posedge clk) + begin +/* PAJ expanded for loop to hard definition the size of `depth */ + buff0 <= datain ; + buff1 <= buff0; + buff2 <= buff1; + end + endmodule + + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg count; + reg temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(state or trigger or count) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + end + endcase + end + endmodule + +module matmult (Ax, Ay, Az, m11, m12, m13, m21, m22, m23, m31, m32, m33, Cx, Cy, Cz, clk); + + input[16 - 1:0] Ax; + input[16 - 1:0] Ay; + input[16 - 1:0] Az; + input[16 - 1:0] m11; + input[16 - 1:0] m12; + + input[16 - 1:0] m13; + input[16 - 1:0] m21; + input[16 - 1:0] m22; + input[16 - 1:0] m23; + input[16 - 1:0] m31; + input[16 - 1:0] m32; + input[16 - 1:0] m33; + output[16 - 1:0] Cx; + reg[16 - 1:0] Cx; + output[16 - 1:0] Cy; + reg[16 - 1:0] Cy; + output[16 - 1:0] Cz; + + reg[16 - 1:0] Cz; + input clk; + + reg[16 + 16 - 1:0] am11; + reg[16 + 16 - 1:0] am12; + reg[16 + 16 - 1:0] am13; + reg[16 + 16 - 1:0] am21; + reg[16 + 16 - 1:0] am22; + reg[16 + 16 - 1:0] am23; + reg[16 + 16 - 1:0] am31; + reg[16 + 16 - 1:0] am32; + reg[16 + 16 - 1:0] am33; + + + always @(posedge clk) + begin + am11 <= Ax * m11 ; + am12 <= Ay * m12 ; + am13 <= Az * m13 ; + am21 <= Ax * m21 ; + am22 <= Ay * m22 ; + am23 <= Az * m23 ; + am31 <= Ax * m31 ; + am32 <= Ay * m32 ; + am33 <= Az * m33 ; + + // Cx <= (am11 + am12 + am13) (`widthA+`widthB-2 downto `widthB-1); + // Cy <= (am21 + am22 + am23) (`widthA+`widthB-2 downto `widthB-1); + // Cz <= (am31 + am32 + am33) (`widthA+`widthB-2 downto `widthB-1); + Cx <= (am11[16+16-2:16-1] + am12[16+16-2:16-1] + am13[16+16-2:16-1]) ; + Cy <= (am21[16+16-2:16-1] + am22[16+16-2:16-1] + am23[16+16-2:16-1]); + Cz <= (am31[16+16-2:16-1] + am32[16+16-2:16-1] + am33[16+16-2:16-1]) ; + end + endmodule + + + + +module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk); + + + input[3:0] CfgAddr; + input[27:0] CfgData; + input CfgData_Ready; + output want_CfgData; + reg want_CfgData; + output[27:0] origx; + reg[27:0] origx; + output[27:0] origy; + reg[27:0] origy; + output[27:0] origz; + reg[27:0] origz; + output[15:0] m11; + reg[15:0] m11; + output[15:0] m12; + reg[15:0] m12; + output[15:0] m13; + reg[15:0] m13; + output[15:0] m21; + reg[15:0] m21; + output[15:0] m22; + reg[15:0] m22; + output[15:0] m23; + reg[15:0] m23; + output[15:0] m31; + reg[15:0] m31; + output[15:0] m32; + reg[15:0] m32; + output[15:0] m33; + reg[15:0] m33; + output[20:0] bkcolour; + reg[20:0] bkcolour; + output[20:0] texinfo; + + wire[20:0] texinfo; + input globalreset; + input clk; + + reg state; + reg next_state; + wire we; + + reg[27:0] temp_origx; + reg[27:0] temp_origy; + reg[27:0] temp_origz; + reg[15:0] temp_m11; + reg[15:0] temp_m12; + reg[15:0] temp_m13; + reg[15:0] temp_m21; + reg[15:0] temp_m22; + reg[15:0] temp_m23; + reg[15:0] temp_m31; + reg[15:0] temp_m32; + reg[15:0] temp_m33; + reg[20:0] temp_bkcolour; + + // <> Can't find translated component 'spram'. Module name may not match + spram21x4 spraminst(we, texinfo, CfgData[20:0], clk); + assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + origx <= 0; + origy <= 0; + + origz <= 0; + m11 <= 1; + m12 <= 0; + m13 <= 0; + m21 <= 0; + m22 <= 1; + m23 <= 0; + m31 <= 0; + m32 <= 0; + m33 <= 1; + bkcolour <= 0; + end + else + begin + state <= next_state ; + origx <= temp_origx; + origy <= temp_origy; + origz <= temp_origz; + m11 <= temp_m11; + m12 <= temp_m12; + m13 <= temp_m13; + m21 <= temp_m21; + m22 <= temp_m22; + m23 <= temp_m23; + m31 <= temp_m31; + m32 <= temp_m32; + m33 <= temp_m33; + bkcolour <= bkcolour; + end + end + + always @(state or CfgData_Ready) + begin + case (state) + 0 : + begin + want_CfgData = 1'b1 ; + if (CfgData_Ready == 1'b1) + begin + next_state = 1 ; + end + + else + begin + next_state = 0 ; + end + + if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0001)) + begin + temp_origx = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0010)) + begin + temp_origy = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0011)) + begin + temp_origz = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0100)) + begin + temp_m11 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0101)) + begin + temp_m12 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0110)) + begin + temp_m13 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0111)) + begin + temp_m21 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1000)) + begin + temp_m22 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1001)) + begin + temp_m23 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1010)) + begin + temp_m31 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1011)) + begin + temp_m32 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1100)) + begin + temp_m33 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1101)) + begin + temp_bkcolour = CfgData[20:0] ; + end + end + 1 : + begin + want_CfgData = 1'b0 ; + if (CfgData_Ready == 1'b0) + begin + next_state = 0 ; + end + + else + begin + next_state = 1 ; + end + end + endcase + end + endmodule + + + + module spram21x4 (we, dataout, datain, clk); + + input we; + output[21 - 1:0] dataout; + wire[21 - 1:0] dataout; + input[21 - 1:0] datain; + input clk; + + reg [7:0] addr; + + always @ (posedge clk) + begin + addr[0] <= we; + addr [1] <= addr[0]; + addr [2] <= addr[1]; + addr [3] <= addr[2]; + addr [4] <= addr[3]; + addr [5] <= addr[4]; + addr [6] <= addr[5]; + addr [7] <= addr[6]; + end +//changed to odin 2 ram specifications + +single_port_ram new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + + + + + + + + + + + + +module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, want_read, read_ready, dataout, dirReady, wantDir, sramdatal, addr, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input want_read; + output read_ready; + + reg read_ready; + output[63:0] dataout; + wire[63:0] dataout; + output dirReady; + reg dirReady; + input wantDir; + output[47:0] sramdatal; + reg[47:0] sramdatal; + output[14:0] addr; + wire[14:0] addr; + input wantwriteback; + output writebackack; + + reg writebackack; + input[63:0] writebackdata; + input[17:0] writebackaddr; + output[63:0] fbdata; + reg[63:0] fbdata; + input fbnextscanline; + output fbdatavalid; + reg fbdatavalid; + input fbpage; + output[63:0] shadedata; + wire[63:0] shadedata; + input[15:0] triID; + + input wantshadedata; + output shadedataready; + reg shadedataready; + input[17:0] texeladdr; + output[63:0] texel; + wire[63:0] texel; + input wanttexel; + output texelready; + reg texelready; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg[17:0] waddress; + reg[14:0] faddress; + reg[6:0] fcount; + reg fbdatavalidl; + + reg[17:0] temp_waddress; + reg[14:0] temp_faddress; + reg[6:0] temp_fcount; + reg temp_fbdatavalidl; + reg temp_texelready; + reg temp_shadedataready; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + assign dataout = tm3_sram_data_in ; + assign addr = tm3_sram_data_in[62:48] ; + assign shadedata = tm3_sram_data_in ; + assign texel = tm3_sram_data_in ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + + state <= 0 ; + waddress <= 0; + faddress <= 0; + fcount <= 7'b1101011 ; + fbdatavalid <= 1'b0 ; + fbdatavalidl <= 1'b0 ; + shadedataready <= 1'b0 ; + texelready <= 1'b0 ; + sramdatal <= 0; + fbdata <= 0; + end + else + + begin + state <= next_state ; + sramdatal <= tm3_sram_data_in[47:0] ; + fbdata <= tm3_sram_data_in ; + fbdatavalid <= fbdatavalidl ; + +fbdatavalidl <= temp_fbdatavalidl; +texelready <= temp_texelready; +shadedataready <= temp_shadedataready; +fcount <= temp_fcount; +faddress <= temp_faddress; +waddress <= temp_waddress; + + end + end + + always @(state or addr_ready or data_ready or waddress or datain or wantDir or + want_read or wantwriteback or writebackdata or writebackaddr or + fcount or fbpage or faddress or fbnextscanline or triID or wantshadedata or + wanttexel or texeladdr) + + begin + case (state) + + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (want_read == 1'b1) + begin + next_state = 2 ; + end + else if (data_ready == 1'b1) + begin + + next_state = 3 ; + end + else if (wantDir == 1'b1) + begin + next_state = 5 ; + end + else if (wantwriteback == 1'b1) + begin + next_state = 6 ; + end + else if (wantshadedata == 1'b1) + begin + + next_state = 9 ; + end + else if (wanttexel == 1'b1) + begin + next_state = 10 ; + end + else if (fcount != 0) + begin + next_state = 7 ; + end + else if (fbnextscanline == 1'b1) + begin + + next_state = 8 ; + end + else + begin + next_state = 0 ; + end + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (addr_ready == 1'b1) + + begin + temp_waddress = addrin ; + end + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + read_ready = 1'b0 ; + if (want_read == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (want_read == 1'b0) + begin + + temp_waddress = waddress + 1 ; + end + + end + 3 : + begin + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_data_xhdl0 = datain ; + tm3_sram_we = 8'b00000000 ; + + + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + want_data = 1'b0 ; + next_state = 4 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress + 1 ; + + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (data_ready == 1'b0) + begin + + next_state = 0 ; + end + else + begin + next_state = 4 ; + end + want_data = 1'b0 ; + end + + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + writebackack = 1'b0 ; + + dirReady = 1'b1 ; + if (wantDir == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 5 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (wantDir == 1'b0) + begin + temp_waddress = waddress + 1 ; + end + + end + 6 : + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + + tm3_sram_data_xhdl0 = writebackdata ; + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_addr = {1'b0, writebackaddr} ; + writebackack = 1'b1 ; + next_state = 0 ; + end + + 7 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b011, fbpage, faddress} ; + if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) + begin + next_state = 0 ; + + end + else + begin + next_state = 7 ; + end + + + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fbdatavalidl = 1'b1 ; + if (fcount != 0) + begin + temp_faddress = faddress + 1 ; + temp_fcount = fcount - 1 ; + end + + end + 8 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + next_state = 7 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fcount = 7'b1101011 ; + if (faddress == 25680) + begin + temp_faddress = 0; + end + end + 9 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b010, triID} ; + next_state = 0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_texelready = 1'b0 ; + temp_shadedataready = 1'b1 ; + end + + 10 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {1'b0, texeladdr} ; + next_state = 0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b1 ; + end + endcase + end + endmodule + + + + + + + + + + + + + module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); + + input as; + output ack; + reg ack; + input[3:0] addr; + input[47:0] dir; + input[27:0] origx; + input[27:0] origy; + input[27:0] origz; + output[31:0] rgData; + reg[31:0] rgData; + + output[3:0] rgAddr; + reg[3:0] rgAddr; + output[2:0] rgWE; + reg[2:0] rgWE; + output rgAddrValid; + reg rgAddrValid; + input rgDone; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + reg[3:0] state; + reg[3:0] next_state; + + + + reg[31:0] temp_rgData; + reg[2:0] temp_rgWE; + reg temp_rgAddrValid; + reg temp_ack; + reg[3:0] temp_rgAddr; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + ack <= 1'b0 ; + rgWE <= 3'b000 ; + rgData <= 0; + rgAddrValid <= 1'b0 ; + rgAddr <= 0; + end + else + begin + state <= next_state ; + +rgData <= temp_rgData; +rgWE <= temp_rgWE; +rgAddrValid <= temp_rgAddrValid; +ack <= temp_ack; +rgAddr <= temp_rgAddr; + + end + end + + always @(state or ack or as or rgDone) + begin + + case (state) + 0 : + begin + if ((as == 1'b1) & (ack == 1'b0)) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + + if ((as == 1'b1) & (ack == 1'b0)) + begin + temp_rgData = {4'b0000, origx} ; + temp_rgWE = 3'b001 ; + temp_rgAddrValid = 1'b1 ; + temp_rgAddr = addr ; + end + if (as == 1'b0 & ack == 1'b1) + begin + temp_ack = 1'b0 ; + end + + end + 1 : + begin + if (rgDone == 1'b1) + begin + next_state = 6 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 2 : + begin + if (rgDone == 1'b1) + begin + next_state = 7 ; + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 3 : + begin + if (rgDone == 1'b1) + begin + next_state = 8 ; + end + else + begin + next_state = 3 ; + end + statepeek = 3'b100 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 4 : + begin + if (rgDone == 1'b1) + begin + next_state = 9 ; + end + else + begin + next_state = 4 ; + end + statepeek = 3'b101 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + end + + 5 : + begin + if (rgDone == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 5 ; + end + statepeek = 3'b110 ; + + temp_ack = 1'b1 ; + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + + 6 : + begin + next_state = 2 ; + + temp_rgData = {4'b0000, origy} ; + temp_rgWE = 3'b010 ; + temp_rgAddrValid = 1'b1 ; + + end + 7 : + begin + next_state = 3 ; + + temp_rgData = {4'b0000, origz} ; + temp_rgWE = 3'b011 ; + temp_rgAddrValid = 1'b1 ; + end + 8 : + begin + next_state = 4 ; + + temp_rgData = {dir[31:16], dir[47:32]} ; + temp_rgWE = 3'b100 ; + temp_rgAddrValid = 1'b1 ; + end + 9 : + begin + next_state = 5 ; + + temp_rgData = {16'b0000000000000000, dir[15:0]} ; + temp_rgWE = 3'b101 ; + temp_rgAddrValid = 1'b1 ; + end + endcase + end + endmodule + + + + + + + + module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek); + + input go; + input[14:0] initcount; + output busyout; + wire busyout; + reg temp_busyout; + output[30:0] cycles; + reg[30:0] cycles; + output[17:0] nextaddr; + wire[17:0] nextaddr; + output nas0; + + wire nas0; + reg temp_nas0; + output nas1; + wire nas1; + reg temp_nas1; + input page; + input dirReady; + output wantDir; + reg wantDir; + input[47:0] dirIn; + input[14:0] addrIn; + output as; + reg as; + output[3:0] addr; + + reg[3:0] addr; + input ack; + output[47:0] dir; + reg[47:0] dir; + output[1:0] raygroup0; + wire[1:0] raygroup0; + output raygroupvalid0; + reg raygroupvalid0; + input busy0; + output[1:0] raygroup1; + wire[1:0] raygroup1; + output raygroupvalid1; + + reg raygroupvalid1; + input busy1; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + + reg[2:0] state; + reg[2:0] next_state; + reg[14:0] count; + reg first; + reg[17:0] destaddr; + wire[1:0] busy; + reg[1:0] loaded; + reg[1:0] groupID; + reg active; + + reg[47:0] temp_dir; + reg[30:0] temp_cycles; + reg[1:0] temp_addr; + reg[1:0] temp_loaded; + reg[1:0] temp_groupID; + reg[14:0] temp_count; + reg temp_active; + reg temp_raygroupvalid1; + reg temp_raygroupvalid0; + + assign busy = {busy1, busy0} ; + + always @(posedge clk) + begin + + if (globalreset == 1'b1) + + begin + state <= 0 ; + cycles <= 0; + dir <= 0; + addr[1:0] <= 2'b00 ; + groupID <= 2'b00 ; + count <= 0; + first <= 1'b0 ; + destaddr <= 0; + raygroupvalid0 <= 1'b0 ; + raygroupvalid1 <= 1'b0 ; + loaded <= 2'b00 ; + + active <= 1'b0 ; + end + else + begin + addr[3:2] <= (active == 1'b0) ? {1'b0, groupID[0]} : {1'b1, groupID[1]} ; + addr[1:0] <= temp_addr[1:0]; + state <= next_state ; + + dir <= temp_dir; + cycles <= temp_cycles; + loaded <= temp_loaded; + groupID <= temp_groupID; + count <= temp_count; + active <= temp_active; + raygroupvalid0 <= temp_raygroupvalid0; + raygroupvalid1 <= temp_raygroupvalid1; + + end + end + + assign raygroup0 = {1'b0, groupID[0]} ; + assign raygroup1 = {1'b1, groupID[1]} ; + assign nextaddr = {2'b11, page, addrIn} ; + assign busyout = temp_busyout; + assign nas0 = temp_nas0; + assign nas1 = temp_nas1; + + always @(state or go or ack or busy or dirReady or addr or count or loaded) + begin + case (state) + 0 : + begin + as = 1'b0 ; + wantDir = 1'b0 ; + if (go == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + + if (go == 1'b1) + begin + temp_cycles = 0; + end + temp_addr[1:0] = 2'b00 ; + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + if (dirReady == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + + temp_dir = dirIn ; + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) + begin + temp_loaded[0] = 1'b1 ; + end + else + begin + temp_loaded[1] = 1'b1 ; + end + end + temp_cycles = cycles + 1 ; + + + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + next_state = 1 ; + end + else if (ack == 1'b1) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (loaded != 2'b11) + begin + + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_addr[1:0] = addr[1:0] + 2'b01 ; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + temp_addr[1:0] = 2'b00 ; + end + end + + temp_cycles = cycles + 1 ; + end + 4 : + begin + if ((busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if (count > 0) + begin + + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b101 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[1]) == 1'b1) + begin + temp_groupID[1] = ~groupID[1] ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + end + else + begin + temp_active = 1'b1 ; + end + end + temp_loaded[1] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + temp_cycles = cycles + 1 ; + end + 3 : + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; + + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + + end + statepeek = 3'b100 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[0]) == 1'b1) + begin + temp_groupID[0] = ~groupID[0] ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_raygroupvalid1 = 1'b1 ; + + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + end + else + begin + temp_active = 1'b0 ; + end + end + temp_loaded[0] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + + temp_cycles = cycles + 1 ; + end + endcase + end + endmodule + + + + + + + + + module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + output valid01; + reg valid01; + output valid10; + reg valid10; + output[15:0] id01a; + reg[15:0] id01a; + output[15:0] id01b; + reg[15:0] id01b; + output[15:0] id01c; + reg[15:0] id01c; + + output[15:0] id10a; + reg[15:0] id10a; + output[15:0] id10b; + reg[15:0] id10b; + output[15:0] id10c; + reg[15:0] id10c; + output hit01a; + reg hit01a; + output hit01b; + reg hit01b; + output hit01c; + reg hit01c; + + output hit10a; + reg hit10a; + output hit10b; + reg hit10b; + output hit10c; + reg hit10c; + output[7:0] u01a; + reg[7:0] u01a; + output[7:0] u01b; + reg[7:0] u01b; + output[7:0] u01c; + reg[7:0] u01c; + + output[7:0] v01a; + reg[7:0] v01a; + output[7:0] v01b; + reg[7:0] v01b; + output[7:0] v01c; + reg[7:0] v01c; + output[7:0] u10a; + reg[7:0] u10a; + output[7:0] u10b; + reg[7:0] u10b; + output[7:0] u10c; + reg[7:0] u10c; + + output[7:0] v10a; + reg[7:0] v10a; + output[7:0] v10b; + reg[7:0] v10b; + output[7:0] v10c; + reg[7:0] v10c; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + input globalreset; + input clk; + + reg temp_valid01; + reg temp_valid10; + reg[15:0] temp_id01a; + reg[15:0] temp_id01b; + reg[15:0] temp_id01c; + reg[15:0] temp_id10a; + reg[15:0] temp_id10b; + reg[15:0] temp_id10c; + reg temp_hit01a; + reg temp_hit01b; + reg temp_hit01c; + reg temp_hit10a; + reg temp_hit10b; + reg temp_hit10c; + reg[7:0] temp_u01a; + reg[7:0] temp_u01b; + reg[7:0] temp_u01c; + reg[7:0] temp_v01a; + reg[7:0] temp_v01b; + reg[7:0] temp_v01c; + reg[7:0] temp_u10a; + reg[7:0] temp_u10b; + reg[7:0] temp_u10c; + reg[7:0] temp_v10a; + reg[7:0] temp_v10b; + reg[7:0] temp_v10c; + + + reg[2:0] state; + reg[2:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + valid01 <= 1'b0 ; + valid10 <= 1'b0 ; + hit01a <= 1'b0 ; + hit01b <= 1'b0 ; + hit01c <= 1'b0 ; + hit10a <= 1'b0 ; + hit10b <= 1'b0 ; + hit10c <= 1'b0 ; + id01a <= 0; + + id01b <= 0; + id01c <= 0; + id10a <= 0; + id10b <= 0; + id10c <= 0; + u01a <= 0; + u01b <= 0; + u01c <= 0; + v01a <= 0; + v01b <= 0; + v01c <= 0; + u10a <= 0; + + u10b <= 0; + u10c <= 0; + v10a <= 0; + v10b <= 0; + v10c <= 0; + end + else + begin + state <= next_state ; + +valid01 <= temp_valid01; +valid10 <= temp_valid10; +id01a <= temp_id01a; +id01b <= temp_id01b; +id01c <= temp_id01c; +hit01a <= temp_hit01a; +hit01b <= temp_hit01b; +hit01c <= temp_hit01c; +u01a <= temp_u01a; +u01b <= temp_u01b; +u01c <= temp_u01c; +u10a <= temp_u10a; +u10b <= temp_u10b; +u10c <= temp_u10c; +v01a <= temp_v01a; +v01b <= temp_v01b; +v01c <= temp_v01c; +v10a <= temp_v10a; +v10b <= temp_v10b; +v10c <= temp_v10c; +hit10a <= temp_hit10a; +hit10b <= temp_hit10b; +hit10c <= temp_hit10c; + end + end + + + always @(state or rgResultReady or rgResultSource) + begin + case (state) + 0 : + begin + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + next_state = 1 ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + temp_id01a = rgResultData[31:16] ; + temp_id01b = rgResultData[15:0] ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + temp_id10a = rgResultData[31:16] ; + temp_id10b = rgResultData[15:0] ; + end + + end + + 1 : + begin + next_state = 2 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id01c = rgResultData[15:0] ; + temp_hit01a = rgResultData[18] ; + temp_hit01b = rgResultData[17] ; + temp_hit01c = rgResultData[16] ; + + end + 2 : + + begin + next_state = 3 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u01a = rgResultData[23:16] ; + temp_u01b = rgResultData[15:8] ; + temp_u01c = rgResultData[7:0] ; + + end + 3 : + begin + next_state = 0 ; + + temp_valid10 = 1'b0 ; + temp_v01a = rgResultData[23:16] ; + temp_v01b = rgResultData[15:8] ; + temp_v01c = rgResultData[7:0] ; + temp_valid01 = 1'b1 ; + + end + 4 : + begin + next_state = 5 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id10c = rgResultData[15:0] ; + + temp_hit10a = rgResultData[18] ; + temp_hit10b = rgResultData[17] ; + temp_hit10c = rgResultData[16] ; + + end + 5 : + + begin + next_state = 6 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u10a = rgResultData[23:16] ; + temp_u10b = rgResultData[15:8] ; + temp_u10c = rgResultData[7:0] ; + + end + 6 : + begin + next_state = 0 ; + + temp_valid01 = 1'b0 ; + temp_v10a = rgResultData[23:16] ; + temp_v10b = rgResultData[15:8] ; + temp_v10c = rgResultData[7:0] ; + temp_valid10 = 1'b1 ; + + end + endcase + end + endmodule + + + + + + + + + + + + + + + + module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + + input hit01a; + input hit01b; + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[17:0] addr; + input as01; + input as10; + input[20:0] bkcolour; + input[63:0] shadedata; + output[15:0] triID; + + reg[15:0] triID; + output wantshadedata; + reg wantshadedata; + input shadedataready; + input[20:0] texinfo; + output[3:0] texaddr; + wire[3:0] texaddr; + output[17:0] texeladdr; + wire[17:0] texeladdr; + input[63:0] texel; + output wanttexel; + reg wanttexel; + + input texelready; + output[63:0] dataout; + // PAJ see lower note wire[63:0] dataout; + reg[63:0] dataout; + output[17:0] addrout; + wire[17:0] addrout; + output write; + wire write; + reg temp_write; + input ack; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg pending01; + reg pending10; + reg process01; + wire[17:0] addrout01; + wire[17:0] addrout10; + wire shiften01; + wire shiften10; + reg temp_shiften01; + reg temp_shiften10; + reg[20:0] shadedataa; + reg[20:0] shadedatab; + reg[20:0] shadedatac; + wire hita; + wire hitb; + wire hitc; + + reg[2:0] selectuv; + wire[6:0] blr; + wire[6:0] blg; + wire[6:0] blb; + reg texmap; + reg lmenable; + wire[1:0] texelselect; + wire[6:0] texelr; + wire[6:0] texelg; + wire[6:0] texelb; + reg[20:0] texinfol; + + reg temp_pending01; + reg temp_pending10; + reg temp_process01; + reg temp_texmap; + reg[20:0] temp_texinfol; + reg[20:0] temp_shadedataa; + reg[20:0] temp_shadedatab; + reg[20:0] temp_shadedatac; + + col16to21 col16to21inst (texel, texelselect, texelr, texelg, texelb); + linearmap linearmapinst (blb, blg, texinfol[17:0], texeladdr, texelselect, texinfol[20:18], lmenable, clk); + bilinearintrp bilinearimp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, shadedata[41:35], shadedata[62:56], shadedata[20:14], shadedata[34:28], shadedata[55:49], shadedata[13:7], shadedata[27:21], shadedata[48:42], shadedata[6:0], blr, blg, blb, clk); + fifo3 fifo3insta (addr, as01, addrout01, shiften01, globalreset, clk); + fifo3 fifo3instb (addr, as10, addrout10, shiften10, globalreset, clk); + assign hita = (hit01a & process01) | (hit10a & ~process01) ; + assign hitb = (hit01b & process01) | (hit10b & ~process01) ; + assign hitc = (hit01c & process01) | (hit10c & ~process01) ; + assign texaddr = shadedata[59:56] ; + assign shiften01 = temp_shiften01; + assign shiften10 = temp_shiften10; + assign write = temp_write; + + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + shadedataa <= 0; + shadedatab <= 0; + shadedatac <= 0; + process01 <= 1'b0 ; + texmap <= 1'b0 ; + + texinfol <= 0; + end + else + begin + state <= next_state ; + +process01 <= temp_process01; +pending01 <= temp_pending01; +pending10 <= temp_pending10; +texmap <= temp_texmap; +texinfol <= temp_texinfol; +shadedataa <= temp_shadedataa; +shadedatab <= temp_shadedatab; +shadedatac <= temp_shadedatac; + + dataout <= {1'b0, + shadedataa[20], + shadedataa[19], + shadedataa[18], + shadedataa[17], + shadedataa[16], + shadedataa[15], + shadedataa[14], + shadedataa[13], + shadedataa[12], + shadedataa[11], + shadedataa[10], + shadedataa[9], + shadedataa[8], + shadedataa[7], + shadedataa[6], + shadedataa[5], + shadedataa[4], + shadedataa[3], + shadedataa[2], + shadedataa[1], + shadedataa[0], + shadedatab[20], + shadedatab[19], + shadedatab[18], + shadedatab[17], + shadedatab[16], + shadedatab[15], + shadedatab[14], + shadedatab[13], + shadedatab[12], + shadedatab[11], + shadedatab[10], + shadedatab[9], + shadedatab[8], + shadedatab[7], + shadedatab[6], + shadedatab[5], + shadedatab[4], + shadedatab[3], + shadedatab[2], + shadedatab[1], + shadedatab[0], + shadedatac[20], + shadedatac[19], + shadedatac[18], + shadedatac[17], + shadedatac[16], + shadedatac[15], + shadedatac[14], + shadedatac[13], + shadedatac[12], + shadedatac[11], + shadedatac[10], + shadedatac[9], + shadedatac[8], + shadedatac[7], + shadedatac[6], + shadedatac[5], + shadedatac[4], + shadedatac[3], + shadedatac[2], + shadedatac[1], + shadedatac[0]} ; + end +// end +// PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0, + end + assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; + + always @(state or process01 or pending10 or ack or shadedataready or id01a or + id01b or id01c or id10a or id10b or id10c or selectuv or hita or + hitb or hitc or shadedata or pending01 or texmap or texelready) + begin + case (state) + 0 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (pending01 == 1'b1 | pending10 == 1'b1) + begin + next_state = 2 ; + end + else + + begin + next_state = 0 ; + end + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_process01 = pending01 ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 2 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + if (process01 == 1'b1) + begin + triID = id01a ; + + end + else + begin + triID = id10a ; + end + if (shadedataready == 1'b1) + begin + if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 3 ; + end + else + + begin + next_state = 4 ; + end + end + else + begin + next_state = 2 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hita == 1'b1) + begin + temp_shadedataa = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedataa = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 3 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + + selectuv[1:0] = 2'b00 ; + next_state = 8 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + + end + 8 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + + next_state = 11 ; + end + else + begin + next_state = 4 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedataa[6:0] = blb ; + temp_shadedataa[13:7] = blg ; + temp_shadedataa[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 11 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 4 ; + end + else + begin + next_state = 11 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedataa[6:0] = texelb ; + temp_shadedataa[13:7] = texelg ; + temp_shadedataa[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 12 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 5 ; + end + else + begin + next_state = 12 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatab[6:0] = texelb ; + temp_shadedatab[13:7] = texelg ; + temp_shadedatab[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 13 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 13 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatac[6:0] = texelb ; + temp_shadedatac[13:7] = texelg ; + temp_shadedatac[20:14] = texelr ; + + end + 6 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + next_state = 9 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 9 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + next_state = 12 ; + + end + else + begin + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatab[6:0] = blb ; + temp_shadedatab[13:7] = blg ; + temp_shadedatab[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 7 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + next_state = 10 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + + 10 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (texmap == 1'b1) + begin + next_state = 13 ; + end + else + begin + next_state = 1 ; + end + + lmenable = 1'b1 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatac[6:0] = blb ; + temp_shadedatac[13:7] = blg ; + temp_shadedatac[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 4 : + begin + wantshadedata = 1'b0 ; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + if (process01 == 1'b1) + begin + triID = id01b ; + end + else + begin + + triID = id10b ; + end + if (shadedataready == 1'b1) + begin + if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 6 ; + end + else + begin + next_state = 5 ; + end + + end + else + begin + next_state = 4 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitb == 1'b1) + begin + temp_shadedatab = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatab = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 5 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (process01 == 1'b1) + + begin + triID = id01c ; + end + else + begin + triID = id10c ; + end + if (shadedataready == 1'b1) + begin + if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 7 ; + + end + else + begin + next_state = 1 ; + end + end + else + begin + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitc == 1'b1) + begin + temp_shadedatac = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatac = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 1 : + + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (ack == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 1 ; + end + + if (ack == 1'b1 & process01 == 1'b1) + begin + temp_pending01 = 1'b0 ; + end + + else if (ack == 1'b1 & process01 == 1'b0) + begin + temp_pending10 = 1'b0 ; + end + + if (process01 == 1'b1 & ack == 1'b1) + begin + temp_shiften01 = 1'b1; + temp_shiften10 = 1'b1; + end + temp_write = 1'b1; + end + endcase + end + endmodule + ////////////////////////////////////////////////////////////////////////////////////////////// + // + // Verilog file generated by X-HDL - Revision 3.2.38 Jan. 9, 2004 + // Sun Feb 8 14:14:35 2004 + // + // Input file : G:/jamieson/VERILOG_BENCHMARKS/RAYTRACE/col16to21.vhd + // Design name : col16to21 + // Author : + // Company : + // + // Description : + // + // + ////////////////////////////////////////////////////////////////////////////////////////////// + // + module col16to21 (dataline, texelselect, r, g, b); + + input[63:0] dataline; + input[1:0] texelselect; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + + reg[15:0] col16; + + always @(dataline or texelselect) + begin + case (texelselect) + 2'b00 : + begin + col16 = dataline[15:0] ; + end + 2'b01 : + begin + col16 = dataline[31:16] ; + end + 2'b10 : + begin + col16 = dataline[47:32] ; + end + 2'b11 : + begin + col16 = dataline[63:48] ; + end + endcase + end + assign r = {col16[15:10], 1'b0} ; + assign g = {col16[9:5], 2'b00} ; + assign b = {col16[4:0], 2'b00} ; + endmodule + module linearmap (u, v, start, addr, texelselect, factor, enable, clk); + + input[6:0] u; + input[6:0] v; + input[17:0] start; + output[17:0] addr; + reg[17:0] addr; + output[1:0] texelselect; + wire[1:0] texelselect; + + input[2:0] factor; + input enable; + input clk; + + reg[6:0] ul; + reg[6:0] vl; + + assign texelselect = ul[1:0] ; + + always @(posedge clk) + begin + if (enable == 1'b1) + begin + ul <= u ; + vl <= v ; + end + else + begin + ul <= ul ; + vl <= vl ; + end + case (factor) + 3'b000 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({11'b00000000000, vl}) ; + end + 3'b001 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({10'b0000000000, vl, 1'b0}) ; + + end + 3'b010 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({9'b000000000, vl, 2'b00}) ; + end + 3'b011 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({8'b00000000, vl, 3'b000}) ; + end + 3'b100 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({7'b0000000, vl, 4'b0000}) ; + + end + 3'b101 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({6'b000000, vl, 5'b00000}) ; + end + 3'b110 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({5'b00000, vl, 6'b000000}) ; + end + 3'b111 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({4'b0000, vl, 7'b0000000}) ; + + end + endcase + end + endmodule + module bilinearintrp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, ru, rv, rw, gu, gv, gw, bu, bv, bw, r, g, b, clk); + + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[2:0] selectuv; + input[6:0] ru; + input[6:0] rv; + input[6:0] rw; + input[6:0] gu; + input[6:0] gv; + input[6:0] gw; + input[6:0] bu; + input[6:0] bv; + input[6:0] bw; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + input clk; + + reg[7:0] u; + reg[7:0] v; + reg[7:0] ul; + reg[7:0] vl; + reg[7:0] wl; + reg[14:0] i1b; + reg[14:0] i2b; + reg[14:0] i3b; + reg[14:0] i1g; + reg[14:0] i2g; + reg[14:0] i3g; + reg[14:0] i1r; + reg[14:0] i2r; + reg[14:0] i3r; + reg[6:0] rul; + reg[6:0] rvl; + reg[6:0] rwl; + reg[6:0] gul; + reg[6:0] gvl; + reg[6:0] gwl; + reg[6:0] bul; + reg[6:0] bvl; + reg[6:0] bwl; + + always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or + u10b or u10c or v10a or v10b or v10c) + begin + case (selectuv) + 3'b000 : + begin + u = u01a ; + v = v01a ; + end + 3'b001 : + begin + u = u01b ; + v = v01b ; + end + 3'b010 : + begin + u = u01c ; + v = v01c ; + end + 3'b100 : + begin + u = u10a ; + v = v10a ; + end + 3'b101 : + begin + u = u10b ; + v = v10b ; + end + 3'b110 : + begin + u = u10c ; + v = v10c ; + end + default : + begin + u = 0; + v = 0; + end + endcase + end + + always @(posedge clk) + begin + wl <= 8'b11111111 - u - v ; + ul <= u ; + vl <= v ; + rul <= ru ; + rvl <= rv ; + rwl <= rw ; + gul <= gu ; + gvl <= gv ; + gwl <= gw ; + bul <= bu ; + bvl <= bv ; + bwl <= bw ; + i1r <= ul * rul ; + i2r <= vl * rvl ; + i3r <= wl * rwl ; + i1g <= ul * gul ; + i2g <= vl * gvl ; + i3g <= wl * gwl ; + i1b <= ul * bul ; + i2b <= vl * bvl ; + i3b <= wl * bwl ; + end + assign r = (i1r + i2r + i3r) ; + assign g = (i1g + i2g + i3g) ; + assign b = (i1b + i2b + i3b) ; + endmodule + + + +module fifo3 (datain, writeen, dataout, shiften, globalreset, clk); + + input[18 - 1:0] datain; + input writeen; + output[18 - 1:0] dataout; + wire[18 - 1:0] dataout; + input shiften; + input globalreset; + input clk; + + reg[18 - 1:0] data0; + reg[18 - 1:0] data1; + reg[18 - 1:0] data2; + + reg[1:0] pos; + + assign dataout = data0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + pos <= 2'b00 ; + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + else + begin + if (writeen == 1'b1 & shiften == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + + 2'b01 : + begin + data0 <= datain ; + data1 <= 0 ; + data2 <= 0 ; + end + 2'b10 : + begin + data0 <= data1 ; + data1 <= datain ; + data2 <= 0 ; + end + + 2'b11 : + begin + data0 <= data1 ; + data1 <= data2 ; + data2 <= datain ; + end + endcase + end + else if (shiften == 1'b1) + begin + data0 <= data1 ; + data1 <= data2 ; + pos <= pos - 1 ; + end + else if (writeen == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= datain ; + end + 2'b01 : + begin + data1 <= datain ; + end + 2'b10 : + begin + data2 <= datain ; + end + endcase + pos <= pos + 1 ; + end + end + end + endmodule + +//--------------------------------------- +// A single-port 256x21bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [7:0] addr, + input [20:0] data, + output [20:0] out ); + + reg [20:0] ram[255:0]; + reg [20:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/sha.v b/openfpga_flow/benchmarks/vtr_benchmark/sha.v new file mode 100755 index 000000000..fad9960bd --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/sha.v @@ -0,0 +1,2171 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SHA-160 //// +//// Secure Hash Algorithm (SHA-160) //// +//// //// +//// Author: marsgod //// +//// marsgod@opencores.org //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/sha_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002-2004 marsgod //// +//// marsgod@opencores.org //// +//// //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`define SHA1_H0 32'h67452301 +`define SHA1_H1 32'hefcdab89 +`define SHA1_H2 32'h98badcfe +`define SHA1_H3 32'h10325476 +`define SHA1_H4 32'hc3d2e1f0 + +`define SHA1_K0 32'h5a827999 +`define SHA1_K1 32'h6ed9eba1 +`define SHA1_K2 32'h8f1bbcdc +`define SHA1_K3 32'hca62c1d6 + +module sha1 (clk_i, rst_i, text_i, text_o, cmd_i, cmd_w_i, cmd_o); + + input clk_i; // global clock input + input rst_i; // global reset input , active high + + input [31:0] text_i; // text input 32bit + output [31:0] text_o; // text output 32bit + + input [2:0] cmd_i; // command input + input cmd_w_i;// command input write enable + output [3:0] cmd_o; // command output(status) + + /* + cmd + Busy Round W R + + bit3 bit2 bit1 bit0 + Busy Round W R + + Busy: + 0 idle + 1 busy + + Round: + 0 first round + 1 internal round + + W: + 0 No-op + 1 write data + + R: + 0 No-op + 1 read data + + */ + + + reg [3:0] cmd; + wire [3:0] cmd_o; + + reg [31:0] text_o; + + reg [6:0] round; + wire [6:0] round_plus_1; + + reg [2:0] read_counter; + + reg [31:0] H0,H1,H2,H3,H4; + reg [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14; + reg [31:0] Wt,Kt; + reg [31:0] A,B,C,D,E; + + reg busy; + + assign cmd_o = cmd; + always @ (posedge clk_i) + begin + if (rst_i) + cmd <= 4'b0000; + else + if (cmd_w_i) + cmd[2:0] <= cmd_i[2:0]; // busy bit can't write + else + begin + cmd[3] <= busy; // update busy bit + if (~busy) + cmd[1:0] <= 2'b00; // hardware auto clean R/W bits + end + end + + // Hash functions + wire [31:0] SHA1_f1_BCD,SHA1_f2_BCD,SHA1_f3_BCD,SHA1_Wt_1; + wire [31:0] SHA1_ft_BCD; + wire [31:0] next_Wt,next_A,next_C; + wire [159:0] SHA1_result; + + assign SHA1_f1_BCD = (B & C) ^ (~B & D); + assign SHA1_f2_BCD = B ^ C ^ D; + assign SHA1_f3_BCD = (B & C) ^ (C & D) ^ (B & D); + + assign SHA1_ft_BCD = (round < 7'b0100101) ? SHA1_f1_BCD : (round < 7'b101001) ? SHA1_f2_BCD : (round < 7'b1111101) ? SHA1_f3_BCD : SHA1_f2_BCD; + + // Odin II doesn't support binary operations inside concatenations presently. + //assign SHA1_Wt_1 = {W13 ^ W8 ^ W2 ^ W0}; + assign SHA1_Wt_1 = W13 ^ W8 ^ W2 ^ W0; + + assign next_Wt = {SHA1_Wt_1[30:0],SHA1_Wt_1[31]}; // NSA fix added + assign next_A = {A[26:0],A[31:27]} + SHA1_ft_BCD + E + Kt + Wt; + assign next_C = {B[1:0],B[31:2]}; + + assign SHA1_result = {A,B,C,D,E}; + + assign round_plus_1 = round + 1; + + //------------------------------------------------------------------ + // SHA round + //------------------------------------------------------------------ + always @(posedge clk_i) + begin + if (rst_i) + begin + round <= 7'b0000000; + busy <= 1'b0; + + W0 <= 32'b00000000000000000000000000000000; + W1 <= 32'b00000000000000000000000000000000; + W2 <= 32'b00000000000000000000000000000000; + W3 <= 32'b00000000000000000000000000000000; + W4 <= 32'b00000000000000000000000000000000; + W5 <= 32'b00000000000000000000000000000000; + W6 <= 32'b00000000000000000000000000000000; + W7 <= 32'b00000000000000000000000000000000; + W8 <= 32'b00000000000000000000000000000000; + W9 <= 32'b00000000000000000000000000000000; + W10 <= 32'b00000000000000000000000000000000; + W11 <= 32'b00000000000000000000000000000000; + W12 <= 32'b00000000000000000000000000000000; + W13 <= 32'b00000000000000000000000000000000; + W14 <= 32'b00000000000000000000000000000000; + Wt <= 32'b00000000000000000000000000000000; + + A <= 32'b00000000000000000000000000000000; + B <= 32'b00000000000000000000000000000000; + C <= 32'b00000000000000000000000000000000; + D <= 32'b00000000000000000000000000000000; + E <= 32'b00000000000000000000000000000000; + + H0 <= 32'b00000000000000000000000000000000; + H1 <= 32'b00000000000000000000000000000000; + H2 <= 32'b00000000000000000000000000000000; + H3 <= 32'b00000000000000000000000000000000; + H4 <= 32'b00000000000000000000000000000000; + + end + else + begin + case (round) + + 7'b0000000: + begin + if (cmd[1]) + begin + W0 <= text_i; + Wt <= text_i; + busy <= 1'b1; + round <= round_plus_1; + + case (cmd[2]) + 1'b0: // sha-1 first message + begin + A <= `SHA1_H0; + B <= `SHA1_H1; + C <= `SHA1_H2; + D <= `SHA1_H3; + E <= `SHA1_H4; + + H0 <= `SHA1_H0; + H1 <= `SHA1_H1; + H2 <= `SHA1_H2; + H3 <= `SHA1_H3; + H4 <= `SHA1_H4; + end + 1'b1: // sha-1 internal message + begin + H0 <= A; + H1 <= B; + H2 <= C; + H3 <= D; + H4 <= E; + end + endcase + end + else + begin // IDLE + round <= 7'b0000000; + end + end + 7'b0000001: + begin + W1 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000010: + begin + W2 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000011: + begin + W3 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000100: + begin + W4 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000101: + begin + W5 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000110: + begin + W6 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000111: + begin + W7 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001000: + begin + W8 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001001: + begin + W9 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001010: + begin + W10 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001011: + begin + W11 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001100: + begin + W12 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001101: + begin + W13 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001110: + begin + W14 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001111: + begin + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001111: + begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1010000: + begin + A <= next_A + H0; + B <= A + H1; + C <= next_C + H2; + D <= C + H3; + E <= D + H4; + round <= 7'b0000000; + busy <= 1'b0; + end + default: + begin + round <= 7'b0000000; + busy <= 1'b0; + end + endcase + end + end + + + //------------------------------------------------------------------ + // Kt generator + //------------------------------------------------------------------ + always @ (posedge clk_i) + begin + if (rst_i) + begin + Kt <= 32'b00000000000000000000000000000000; + end + else + begin + if (round < 7'b0100000) + Kt <= `SHA1_K0; + else + if (round < 7'b1010000) + Kt <= `SHA1_K1; + else + if (round < 7'b1111100) + Kt <= `SHA1_K2; + else + Kt <= `SHA1_K3; + end + end + + //------------------------------------------------------------------ + // read result + //------------------------------------------------------------------ + always @ (posedge clk_i) + begin + if (rst_i) + begin + text_o <= 32'b00000000000000000000000000000000; + read_counter <= 3'b000; + end + else + begin + if (cmd[0]) + begin + read_counter <= 3'b100; // sha-1 160/32=5 + end + else + begin + if (~busy) + begin + case (read_counter) + 3'b100: text_o <= SHA1_result[5*32-1:4*32]; + 3'b011: text_o <= SHA1_result[4*32-1:3*32]; + 3'b010: text_o <= SHA1_result[3*32-1:2*32]; + 3'b001: text_o <= SHA1_result[2*32-1:1*32]; + 3'b000: text_o <= SHA1_result[1*32-1:0*32]; + default:text_o <= 3'b000; + endcase + if (|read_counter) + read_counter <= read_counter - 7'b0000001; + end + else + begin + text_o <= 32'b00000000000000000000000000000000; + end + end + end + end + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/spree.v b/openfpga_flow/benchmarks/vtr_benchmark/spree.v new file mode 100755 index 000000000..4497cd7aa --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/spree.v @@ -0,0 +1,3063 @@ +/**************************************************************************** + ISA definition file + + - The MIPS I ISA has a 6 bit opcode in the upper 6 bits. + - The opcode can also specify a "class". There are two classes: + 1. SPECIAL - look in lowest 6 bits to find operation + 2. REGIMM - look in [20:16] to find type of branch + +****************************************************************************/ + +/****** OPCODES - bits 31...26 *******/ + +`define VAL 31 + +`define WIDTH 32 +`define NUMREGS 32 +`define LOG2NUMREGS 5 +`define PC_WIDTH 30 +`define I_DATAWIDTH 32 +`define I_ADDRESSWIDTH 14 +`define I_SIZE 16384 + +`define D_ADDRESSWIDTH 32 +`define DM_DATAWIDTH 32 +`define DM_BYTEENAWIDTH 4 +`define DM_ADDRESSWIDTH 10 +`define DM_SIZE 16384 + + + +`define OP_SPECIAL 6'b000000 +`define OP_REGIMM 6'b000001 +`define OP_J 6'b000010 +`define OP_JAL 6'b000011 +`define OP_BEQ 6'b000100 +`define OP_BNE 6'b000101 +`define OP_BLEZ 6'b000110 +`define OP_BGTZ 6'b000111 + +`define OP_ADDI 6'b001000 +`define OP_ADDIU 6'b001001 +`define OP_SLTI 6'b001010 +`define OP_SLTIU 6'b001011 +`define OP_ANDI 6'b001100 +`define OP_ORI 6'b001101 +`define OP_XORI 6'b001110 +`define OP_LUI 6'b001111 + +`define OP_LB 6'b100000 +`define OP_LH 6'b100001 +`define OP_LWL 6'b100010 +`define OP_LW 6'b100011 +`define OP_LBU 6'b100100 +`define OP_LHU 6'b100101 +`define OP_LWR 6'b100110 + +`define OP_SB 6'b101100 +`define OP_SH 6'b101101 +`define OP_SWL 6'b101010 +`define OP_SW 6'b101111 +`define OP_SWR 6'b101110 + +/****** FUNCTION CLASS - bits 5...0 *******/ +`define FUNC_SLL 6'b000000 +`define FUNC_SRL 6'b000010 +`define FUNC_SRA 6'b000011 +`define FUNC_SLLV 6'b000100 +`define FUNC_SRLV 6'b000110 +`define FUNC_SRAV 6'b000111 + +`define FUNC_JR 6'b001110 +`define FUNC_JALR 6'b001111 + +`define FUNC_MFHI 6'b110100 +`define FUNC_MTHI 6'b110101 +`define FUNC_MFLO 6'b110110 +`define FUNC_MTLO 6'b110111 + +`define FUNC_MULT 6'b111100 +`define FUNC_MULTU 6'b111101 +`define FUNC_DIV 6'b111110 +`define FUNC_DIVU 6'b111111 + +`define FUNC_ADD 6'b100000 +`define FUNC_ADDU 6'b100001 +`define FUNC_SUB 6'b100010 +`define FUNC_SUBU 6'b100011 +`define FUNC_AND 6'b100100 +`define FUNC_OR 6'b100101 +`define FUNC_XOR 6'b100110 +`define FUNC_NOR 6'b100111 + +`define FUNC_SLT 6'b101010 +`define FUNC_SLTU 6'b101011 + +/****** REGIMM Class - bits 20...16 *******/ +`define FUNC_BLTZ 1'b0 +`define FUNC_BGEZ 1'b1 + +`define OP_COP2 6'b010010 +`define COP2_FUNC_CFC2 6'b111000 +`define COP2_FUNC_CTC2 6'b111010 +`define COP2_FUNC_MTC2 6'b111011 + +//`define FUNC_BLTZAL 5'b10000 +//`define FUNC_BGEZAL 5'b10001 + +/****** + * Original REGIMM class, compressed above to save decode logic +`define FUNC_BLTZ 5'b00000 +`define FUNC_BGEZ 5'b00001 +`define FUNC_BLTZAL 5'b10000 +`define FUNC_BGEZAL 5'b10001 +*/ + + +module system ( + clk, + resetn, + boot_iaddr, + boot_idata, + boot_iwe, + boot_daddr, + boot_ddata, + boot_dwe, + nop7_q +); + +/************************* IO Declarations *********************/ +input clk; +input resetn; +input [31:0] boot_iaddr; +input [31:0] boot_idata; +input boot_iwe; +input [31:0] boot_daddr; +input [31:0] boot_ddata; +input boot_dwe; +output [31:0] nop7_q; + + +/*********************** Signal Declarations *******************/ +wire branch_mispred; +wire stall_2nd_delayslot; +wire has_delayslot; +wire haz_zeroer0_q_pipereg5_q; +wire haz_zeroer_q_pipereg5_q; + // Datapath signals declarations +wire addersub_result_slt; +wire [ 31 : 0 ] addersub_result; +wire [ 31 : 0 ] reg_file_b_readdataout; +wire [ 31 : 0 ] reg_file_a_readdataout; +wire [ 31 : 0 ] mul_shift_result; +wire [ 31 : 0 ] mul_lo; +wire [ 31 : 0 ] mul_hi; +wire ctrl_mul_stalled; +wire [ 31 : 0 ] ifetch_pc_out; +wire [ 31 : 0 ] ifetch_instr; +wire [ 5 : 0 ] ifetch_opcode; +wire [ 5 : 0 ] ifetch_func; +wire [4 : 0 ] ifetch_rs; +wire [ 4 : 0 ] ifetch_rt; +wire [ 4 : 0 ] ifetch_rd; +wire [ 25 : 0 ] ifetch_instr_index; +wire [ 15 : 0 ] ifetch_offset; +wire [ 4 : 0 ] ifetch_sa; +wire [ 31 : 0 ] ifetch_next_pc; +wire [ 31 : 0 ] data_mem_d_loadresult; +wire ctrl_data_mem_stalled; +wire [ 31 : 0 ] logic_unit_result; +wire [ 31 : 0 ] pcadder_result; +wire [ 31 : 0 ] signext16_out; +wire [ 31 : 0 ] merge26lo_out; +wire [ 31 : 0 ] hi_reg_q; +wire branchresolve_eqz; +wire branchresolve_gez; +wire branchresolve_gtz; +wire branchresolve_lez; +wire branchresolve_ltz; +wire branchresolve_ne; +wire branchresolve_eq; +wire [ 31 : 0 ] lo_reg_q; +wire [ 31 : 0 ] const8_out; +wire [ 31 : 0 ] const9_out; +wire [ 31 : 0 ] const_out; +wire [ 31 : 0 ] pipereg_q; +wire [ 25 : 0 ] pipereg1_q; +wire [ 4 : 0 ] pipereg2_q; +wire [ 31 : 0 ] pipereg5_q; +wire [ 31 : 0 ] pipereg14_q; +wire [ 31 : 0 ] pipereg3_q; +wire [ 31 : 0 ] nop7_q; +wire [ 31 : 0 ] nop_q; +wire [ 31 : 0 ] nop10_q; +wire [ 31 : 0 ] nop6_q; +wire [ 31 : 0 ] zeroer_q; +wire [ 31 : 0 ] zeroer0_q; +wire [ 31 : 0 ] zeroer4_q; +wire [ 31 : 0 ] fakedelay_q; +wire [ 31 : 0 ] mux3to1_ifetch_load_data_out; +wire [ 31 : 0 ] mux2to1_mul_opA_out; +wire mux6to1_ifetch_load_out; +wire [ 4 : 0 ] mux3to1_mul_sa_out; +wire [ 31 : 0 ] mux2to1_addersub_opA_out; +wire [ 31 : 0 ] mux7to1_nop10_d_out; +wire [ 31 : 0 ] mux2to1_pipereg_d_out; +wire [ 31 : 0 ] mux3to1_nop6_d_out; +wire [ 31 : 0 ] mux3to1_zeroer4_d_out; +wire [ 5 : 0 ] pipereg11_q; +wire [ 31 : 0 ] mux2to1_nop_d_out; +wire pipereg16_q; +wire pipereg15_q; +wire [ 31 : 0 ] mux2to1_nop7_d_out; +wire [ 5 : 0 ] pipereg12_q; +wire [ 4 : 0 ] pipereg13_q; +/***************** Control Signals ***************/ + //Decoded Opcode signal declarations +reg ctrl_mux2to1_pipereg_d_sel; +reg [ 2 : 0 ] ctrl_mux7to1_nop10_d_sel; +reg ctrl_mux2to1_addersub_opA_sel; +reg [ 2 : 0 ] ctrl_mux6to1_ifetch_load_sel; +reg [ 1 : 0 ] ctrl_mux3to1_nop6_d_sel; +reg ctrl_mux2to1_mul_opA_sel; +reg [ 1 : 0 ] ctrl_mux3to1_mul_sa_sel; +reg [ 1 : 0 ] ctrl_mux3to1_ifetch_load_data_sel; +reg [ 1 : 0 ] ctrl_mux3to1_zeroer4_d_sel; +reg ctrl_zeroer4_en; +reg ctrl_zeroer0_en; +reg ctrl_zeroer_en; +reg [ 3 : 0 ] ctrl_data_mem_op; +reg [ 2 : 0 ] ctrl_addersub_op; +reg ctrl_ifetch_op; +reg [ 2 : 0 ] ctrl_mul_op; +reg [ 1 : 0 ] ctrl_logic_unit_op; + //Enable signal declarations +reg ctrl_hi_reg_en; +reg ctrl_lo_reg_en; +reg ctrl_branchresolve_en; +reg ctrl_reg_file_c_we; +reg ctrl_reg_file_b_en; +reg ctrl_reg_file_a_en; +reg ctrl_data_mem_en; +reg ctrl_ifetch_we; +reg ctrl_ifetch_en; +reg ctrl_mul_start; + //Other Signals +wire squash_stage2; +wire stall_out_stage2; +wire squash_stage1; +wire stall_out_stage1; +wire ctrl_pipereg16_squashn; +wire ctrl_pipereg15_squashn; +wire ctrl_pipereg14_squashn; +wire ctrl_pipereg_squashn; +wire ctrl_pipereg5_squashn; +wire ctrl_pipereg2_squashn; +wire ctrl_pipereg3_squashn; +wire ctrl_pipereg1_squashn; +wire ctrl_pipereg11_squashn; +wire ctrl_pipereg12_squashn; +wire ctrl_pipereg13_squashn; +wire ctrl_pipereg16_resetn; +wire ctrl_pipereg15_resetn; +wire ctrl_pipereg14_resetn; +wire ctrl_pipereg_resetn; +wire ctrl_pipereg5_resetn; +wire ctrl_pipereg2_resetn; +wire ctrl_pipereg3_resetn; +wire ctrl_pipereg1_resetn; +wire ctrl_pipereg11_resetn; +wire ctrl_pipereg12_resetn; +wire ctrl_pipereg13_resetn; +wire ctrl_pipereg16_en; +wire ctrl_pipereg15_en; +wire ctrl_pipereg14_en; +wire ctrl_pipereg_en; +wire ctrl_pipereg5_en; +wire ctrl_pipereg2_en; +wire ctrl_pipereg3_en; +wire ctrl_pipereg1_en; +wire ctrl_pipereg11_en; +wire ctrl_pipereg12_en; +wire ctrl_pipereg13_en; +wire crtl_ifetch_squashn; + +/****************************** Control **************************/ + //Decode Logic for Opcode and Multiplex Select signals +always@(posedge clk) +begin + // Initialize control opcodes to zero + + case (ifetch_opcode) + `OP_ADDI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ADDIU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ANDI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BEQ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BGTZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BLEZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BNE: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_JAL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + end + `OP_LB: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LBU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LH: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LHU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LUI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + end + `OP_LW: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ORI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_REGIMM: + case (ifetch_rt[0]) + `FUNC_BGEZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_BLTZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + `OP_SB: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SH: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SLTI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SLTIU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SPECIAL: + case (ifetch_func) + `FUNC_ADD: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_ADDU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_AND: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_JALR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_JR: + ctrl_zeroer_en <= 1'b1; + `FUNC_MFHI: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + end + `FUNC_MFLO: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + end + `FUNC_MULT: + begin + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_MULTU: + begin + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_NOR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_OR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SLLV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLT: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLTU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SRA: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SRAV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SRL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SRLV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SUB: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SUBU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_XOR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + `OP_SW: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_XORI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + + //Logic for enable signals in Pipe Stage 1 + ctrl_reg_file_b_en <= ~stall_out_stage2; + ctrl_reg_file_a_en <= ~stall_out_stage2; + ctrl_ifetch_en <= ~stall_out_stage2; + + //Decode Logic for Opcode and Multiplex Select signals + + + // Initialize control opcodes to zero + + + case (pipereg11_q) + `OP_ADDI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b011; + end + `OP_ADDIU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b001; + end + `OP_ANDI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b00; + end + `OP_BEQ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b101; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BGTZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b000; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BLEZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b011; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BNE: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b100; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_J: + begin + ctrl_mux3to1_ifetch_load_data_sel<= 2'b01; + ctrl_ifetch_op <= 1'b1; + end + `OP_JAL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b1; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b01; + ctrl_addersub_op <= 3'b001; + ctrl_ifetch_op <= 1'b1; + end + `OP_LB: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0111; + ctrl_addersub_op <= 3'b011; + end + `OP_LBU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0011; + ctrl_addersub_op <= 3'b011; + end + `OP_LH: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0101; + ctrl_addersub_op <= 3'b011; + end + `OP_LHU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0001; + ctrl_addersub_op <= 3'b011; + end + `OP_LUI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b01; + ctrl_mul_op <= 3'b000; + end + `OP_LW: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0000; + ctrl_addersub_op <= 3'b011; + end + `OP_ORI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b01; + end + `OP_REGIMM: + case (pipereg13_q[0]) + `FUNC_BGEZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b001; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `FUNC_BLTZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b010; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + endcase + `OP_SB: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0011; + ctrl_addersub_op <= 3'b011; + end + `OP_SH: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b1001; + ctrl_addersub_op <= 3'b011; + end + `OP_SLTI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b101; + end + `OP_SLTIU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b100; + end + `OP_SPECIAL: + case (pipereg12_q) + `FUNC_ADD: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b011; + end + `FUNC_ADDU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b001; + end + `FUNC_AND: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b00; + end + `FUNC_JALR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b1; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b00; + ctrl_addersub_op <= 3'b001; + ctrl_ifetch_op <= 1'b1; + end + `FUNC_JR: + begin + ctrl_mux3to1_ifetch_load_data_sel<= 2'b00; + ctrl_ifetch_op <= 1'b1; + end + `FUNC_MFHI: + ctrl_mux7to1_nop10_d_sel <= 3'b001; + `FUNC_MFLO: + ctrl_mux7to1_nop10_d_sel <= 3'b000; + `FUNC_MULT: + begin + ctrl_mux2to1_mul_opA_sel <= 1'b1; + ctrl_mul_op <= 3'b110; + end + `FUNC_MULTU: + begin + ctrl_mux2to1_mul_opA_sel <= 1'b1; + ctrl_mul_op <= 3'b100; + end + `FUNC_NOR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b11; + end + `FUNC_OR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b01; + end + `FUNC_SLL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b000; + end + `FUNC_SLLV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b000; + end + `FUNC_SLT: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b110; + end + `FUNC_SLTU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b100; + end + `FUNC_SRA: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b011; + end + `FUNC_SRAV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b011; + end + `FUNC_SRL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b001; + end + `FUNC_SRLV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b001; + end + `FUNC_SUB: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b000; + end + `FUNC_SUBU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b010; + end + `FUNC_XOR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b10; + end + endcase + `OP_SW: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b1000; + ctrl_addersub_op <= 3'b011; + end + `OP_XORI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b10; + end + endcase + + + + //Logic for enable signals in Pipe Stage 2 + + + + case (pipereg11_q) + `OP_ADDI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_ADDIU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_ANDI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_BEQ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BGTZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BLEZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BNE: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_J: + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_JAL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_LB: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LBU: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LH: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LHU: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LUI: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `OP_LW: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_ORI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_REGIMM: + case (pipereg13_q[0]) + `FUNC_BGEZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `FUNC_BLTZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + endcase + `OP_SB: + ctrl_data_mem_en <=1'b1; + `OP_SH: + ctrl_data_mem_en <=1'b1; + `OP_SLTI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_SLTIU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_SPECIAL: + case (pipereg12_q) + `FUNC_ADD: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_ADDU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_AND: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_JALR: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `FUNC_JR: + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MFHI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MFLO: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MULT: + begin + ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_MULTU: + begin + ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_NOR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_OR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SLL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SLLV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SLT: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SLTU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SRA: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRAV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRLV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SUB: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SUBU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_XOR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + endcase + `OP_SW: + ctrl_data_mem_en <=1'b1; + `OP_XORI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + endcase +end + +/********* Stall Network & PipeReg Control ********/ +assign stall_out_stage1 = stall_out_stage2; +assign ctrl_pipereg13_en = ~stall_out_stage1; +assign ctrl_pipereg12_en = ~stall_out_stage1; +assign ctrl_pipereg11_en = ~stall_out_stage1; +assign ctrl_pipereg1_en = ~stall_out_stage1; +assign ctrl_pipereg3_en = ~stall_out_stage1; +assign ctrl_pipereg2_en = ~stall_out_stage1; +assign ctrl_pipereg5_en = ~stall_out_stage1; +assign ctrl_pipereg_en = ~stall_out_stage1; +assign ctrl_pipereg14_en = ~stall_out_stage1; +assign ctrl_pipereg15_en = ~stall_out_stage1; +assign ctrl_pipereg16_en = ~stall_out_stage1; +assign stall_out_stage2 = ctrl_data_mem_stalled|ctrl_mul_stalled; +assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && mux6to1_ifetch_load_out)) & ctrl_ifetch_we); +assign stall_2nd_delayslot = &has_delayslot; +assign has_delayslot = 0; +assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn; +assign ctrl_pipereg13_resetn = ~squash_stage1; +assign ctrl_pipereg12_resetn = ~squash_stage1; +assign ctrl_pipereg11_resetn = ~squash_stage1; +assign ctrl_pipereg1_resetn = ~squash_stage1; +assign ctrl_pipereg3_resetn = ~squash_stage1; +assign ctrl_pipereg2_resetn = ~squash_stage1; +assign ctrl_pipereg5_resetn = ~squash_stage1; +assign ctrl_pipereg_resetn = ~squash_stage1; +assign ctrl_pipereg14_resetn = ~squash_stage1; +assign ctrl_pipereg15_resetn = ~squash_stage1; +assign ctrl_pipereg16_resetn = ~squash_stage1; +assign ctrl_pipereg16_squashn = 1'b1; +assign ctrl_pipereg15_squashn = 1'b1; +assign ctrl_pipereg14_squashn = 1'b1; +assign ctrl_pipereg_squashn = 1'b1; +assign ctrl_pipereg5_squashn = 1'b1; +assign ctrl_pipereg2_squashn = 1'b1; +assign ctrl_pipereg3_squashn = 1'b1; +assign ctrl_pipereg1_squashn = 1'b1; +assign ctrl_pipereg11_squashn = 1'b1; +assign ctrl_pipereg12_squashn = 1'b1; +assign ctrl_pipereg13_squashn = 1'b1; +assign ctrl_ifetch_squashn = 1'b1; +wire ctrl_ifetch_squashn; + +assign squash_stage2 = ((stall_out_stage2))|~resetn; + +/****************************** Datapath **************************/ +/******************** Hazard Detection Logic ***********************/ +assign haz_zeroer0_q_pipereg5_q = (zeroer0_q==pipereg5_q) && (|zeroer0_q); +assign haz_zeroer_q_pipereg5_q = (zeroer_q==pipereg5_q) && (|zeroer_q); +assign const8_out = 32'b00000000000000000000000000000000; +assign const9_out = 32'b00000000000000000000000000010000; +assign const_out = 32'b00000000000000000000000000011111; + + + + +/*************** DATAPATH COMPONENTS **************/ +addersub addersub ( + .opB(nop6_q), + .opA(mux2to1_addersub_opA_out), + .op(ctrl_addersub_op), + .result_slt(addersub_result_slt), + .result(addersub_result)); +// defparam + // addersub.WIDTH=32; + +reg_file reg_file ( + .clk(clk), + .resetn(resetn), + .c_writedatain(nop10_q), + .c_reg(pipereg5_q), + .b_reg(zeroer0_q), + .a_reg(zeroer_q), + .c_we(ctrl_reg_file_c_we), + .b_en(ctrl_reg_file_b_en), + .a_en(ctrl_reg_file_a_en), + .b_readdataout(reg_file_b_readdataout), + .a_readdataout(reg_file_a_readdataout)); + +mul mul ( + .clk(clk), + .resetn(resetn), + .sa(mux3to1_mul_sa_out), + .dst(pipereg5_q), + .opB(nop7_q), + .opA(mux2to1_mul_opA_out), + .op(ctrl_mul_op), + .start(ctrl_mul_start), + .stalled(ctrl_mul_stalled), + .shift_result(mul_shift_result), + .lo(mul_lo), + .hi(mul_hi)); +// defparam + // mul.WIDTH=32; + +ifetch ifetch ( + .clk(clk), + .resetn(resetn), + .boot_iaddr(boot_iaddr), + .boot_idata(boot_idata), + .boot_iwe(boot_iwe), + .load(mux6to1_ifetch_load_out), + .load_data(mux3to1_ifetch_load_data_out), + .op(ctrl_ifetch_op), + .we(ctrl_ifetch_we), + .squashn(ctrl_ifetch_squashn), + .en(ctrl_ifetch_en), + .pc_out(ifetch_pc_out), + .instr(ifetch_instr), + .opcode(ifetch_opcode), + .func(ifetch_func), + .rs(ifetch_rs), + .rt(ifetch_rt), + .rd(ifetch_rd), + .instr_index(ifetch_instr_index), + .offset(ifetch_offset), + .sa(ifetch_sa), + .next_pc(ifetch_next_pc)); + +data_mem data_mem ( + .clk(clk), + .resetn(resetn), + .stalled(ctrl_data_mem_stalled), + .d_writedata(nop7_q), + .d_address(addersub_result), + .op(ctrl_data_mem_op), + .d_loadresult(data_mem_d_loadresult)); + +logic_unit logic_unit ( + .opB(nop6_q), + .opA(nop_q), + .op(ctrl_logic_unit_op), + .result(logic_unit_result)); +// defparam + // logic_unit.WIDTH=32; + +pcadder pcadder ( + .offset(pipereg_q), + .pc(pipereg3_q), + .result(pcadder_result)); + +signext16 signext16 ( + .in(ifetch_offset), + .out(signext16_out)); + +merge26lo merge26lo ( + .in2(pipereg1_q), + .in1(pipereg3_q), + .out(merge26lo_out)); + +hi_reg hi_reg ( + .clk(clk), + .resetn(resetn), + .d(mul_hi), + .en(ctrl_hi_reg_en), + .q(hi_reg_q)); +// defparam +// hi_reg.WIDTH=32; + +branchresolve branchresolve ( + .rt(nop7_q), + .rs(nop_q), + .en(ctrl_branchresolve_en), + .eqz(branchresolve_eqz), + .gez(branchresolve_gez), + .gtz(branchresolve_gtz), + .lez(branchresolve_lez), + .ltz(branchresolve_ltz), + .ne(branchresolve_ne), + .eq(branchresolve_eq)); +// defparam +// branchresolve.WIDTH=32; + +lo_reg lo_reg ( + .clk(clk), + .resetn(resetn), + .d(mul_lo), + .en(ctrl_lo_reg_en), + .q(lo_reg_q)); +// defparam +// lo_reg.WIDTH=32; + +/* +const const8 ( + .out(const8_out)); +// defparam + // const8.WIDTH=32, + //const8.VAL=0; + +const const9 ( + .out(const9_out)); +// defparam + // const9.WIDTH=32, + //const9.VAL=16; + +const const ( + .out(const_out)); +// defparam + // const.WIDTH=32, + //const.VAL=31; + */ + +pipereg_w32 pipereg ( + .clk(clk), + .resetn(ctrl_pipereg_resetn), + .d(mux2to1_pipereg_d_out), + .squashn(ctrl_pipereg_squashn), + .en(ctrl_pipereg_en), + .q(pipereg_q)); +// defparam + // pipereg.WIDTH=32; + +pipereg_w26 pipereg1 ( + .clk(clk), + .resetn(ctrl_pipereg1_resetn), + .d(ifetch_instr_index), + .squashn(ctrl_pipereg1_squashn), + .en(ctrl_pipereg1_en), + .q(pipereg1_q)); +// defparam + // pipereg1.WIDTH=26; + +pipereg_w5 pipereg2 ( + .clk(clk), + .resetn(ctrl_pipereg2_resetn), + .d(ifetch_sa), + .squashn(ctrl_pipereg2_squashn), + .en(ctrl_pipereg2_en), + .q(pipereg2_q)); +// defparam + // pipereg2.WIDTH=5; + +pipereg_w5 pipereg5 ( + .clk(clk), + .resetn(ctrl_pipereg5_resetn), + .d(zeroer4_q), + .squashn(ctrl_pipereg5_squashn), + .en(ctrl_pipereg5_en), + .q(pipereg5_q)); + //defparam + //pipereg5.WIDTH=5; + +pipereg_w32 pipereg14 ( + .clk(clk), + .resetn(ctrl_pipereg14_resetn), + .d(nop10_q), + .squashn(ctrl_pipereg14_squashn), + .en(ctrl_pipereg14_en), + .q(pipereg14_q)); + //defparam + // pipereg14.WIDTH=32; + +pipereg_w32 pipereg3 ( + .clk(clk), + .resetn(ctrl_pipereg3_resetn), + .d(ifetch_pc_out), + .squashn(ctrl_pipereg3_squashn), + .en(ctrl_pipereg3_en), + .q(pipereg3_q)); +// defparam +// pipereg3.WIDTH=32; + +nop nop7 ( + .d(mux2to1_nop7_d_out), + .q(nop7_q)); + //defparam +// nop7.WIDTH=32; + +nop nop ( + .d(mux2to1_nop_d_out), + .q(nop_q)); + //defparam + // nop.WIDTH=32; + +nop nop10 ( + .d(mux7to1_nop10_d_out), + .q(nop10_q)); + //defparam + // nop10.WIDTH=32; + +nop nop6 ( + .d(mux3to1_nop6_d_out), + .q(nop6_q)); + //defparam + // nop6.WIDTH=32; + +zeroer zeroer ( + .d(ifetch_rs), + .en(ctrl_zeroer_en), + .q(zeroer_q)); + //defparam + // zeroer.WIDTH=5; + +zeroer zeroer0 ( + .d(ifetch_rt), + .en(ctrl_zeroer0_en), + .q(zeroer0_q)); + //defparam + // zeroer0.WIDTH=5; + +zeroer zeroer4 ( + .d(mux3to1_zeroer4_d_out), + .en(ctrl_zeroer4_en), + .q(zeroer4_q)); + //defparam + // zeroer4.WIDTH=5; + +fakedelay fakedelay ( + .clk(clk), + .d(ifetch_pc_out), + .q(fakedelay_q)); + //defparam + // fakedelay.WIDTH=32; + + // Multiplexor mux3to1_ifetch_load_data instantiation +assign mux3to1_ifetch_load_data_out = + (ctrl_mux3to1_ifetch_load_data_sel==2) ? pcadder_result : + (ctrl_mux3to1_ifetch_load_data_sel==1) ? merge26lo_out : + nop_q; + + // Multiplexor mux2to1_mul_opA instantiation +assign mux2to1_mul_opA_out = + (ctrl_mux2to1_mul_opA_sel==1) ? nop_q : + nop6_q; + + // Multiplexor mux6to1_ifetch_load instantiation +assign mux6to1_ifetch_load_out = + (ctrl_mux6to1_ifetch_load_sel==3'd5) ? branchresolve_eq : + (ctrl_mux6to1_ifetch_load_sel==3'd4) ? branchresolve_ne : + (ctrl_mux6to1_ifetch_load_sel==3'd3) ? branchresolve_lez : + (ctrl_mux6to1_ifetch_load_sel==3'd2) ? branchresolve_ltz : + (ctrl_mux6to1_ifetch_load_sel==3'd1) ? branchresolve_gez : + branchresolve_gtz; + + // Multiplexor mux3to1_mul_sa instantiation +assign mux3to1_mul_sa_out = + (ctrl_mux3to1_mul_sa_sel==2) ? nop_q : + (ctrl_mux3to1_mul_sa_sel==1) ? const9_out : + pipereg2_q; + + // Multiplexor mux2to1_addersub_opA instantiation +assign mux2to1_addersub_opA_out = + (ctrl_mux2to1_addersub_opA_sel==1) ? fakedelay_q : + nop_q; + + // Multiplexor mux7to1_nop10_d instantiation +assign mux7to1_nop10_d_out = + (ctrl_mux7to1_nop10_d_sel==3'd6) ? addersub_result : + (ctrl_mux7to1_nop10_d_sel==3'd5) ? addersub_result_slt : + (ctrl_mux7to1_nop10_d_sel==3'd4) ? logic_unit_result : + (ctrl_mux7to1_nop10_d_sel==3'd3) ? mul_shift_result : + (ctrl_mux7to1_nop10_d_sel==3'd2) ? data_mem_d_loadresult : + (ctrl_mux7to1_nop10_d_sel==3'd1) ? hi_reg_q : + lo_reg_q; + + // Multiplexor mux2to1_pipereg_d instantiation +assign mux2to1_pipereg_d_out = + (ctrl_mux2to1_pipereg_d_sel==1) ? ifetch_offset : + signext16_out; + + // Multiplexor mux3to1_nop6_d instantiation +assign mux3to1_nop6_d_out = + (ctrl_mux3to1_nop6_d_sel==2) ? pipereg_q : + (ctrl_mux3to1_nop6_d_sel==1) ? nop7_q : + const8_out; + + // Multiplexor mux3to1_zeroer4_d instantiation +assign mux3to1_zeroer4_d_out = + (ctrl_mux3to1_zeroer4_d_sel==2) ? ifetch_rt : + (ctrl_mux3to1_zeroer4_d_sel==1) ? ifetch_rd : + const_out; + +pipereg_w6 pipereg11 ( + .clk(clk), + .resetn(ctrl_pipereg11_resetn), + .d(ifetch_opcode), + .squashn(ctrl_pipereg11_squashn), + .en(ctrl_pipereg11_en), + .q(pipereg11_q)); + //defparam + // pipereg11.WIDTH=6; + + // Multiplexor mux2to1_nop_d instantiation +assign mux2to1_nop_d_out = + (pipereg15_q==1) ? pipereg14_q : + reg_file_a_readdataout; + +pipereg_w1 pipereg16 ( + .clk(clk), + .resetn(ctrl_pipereg16_resetn), + .d(haz_zeroer0_q_pipereg5_q), + .squashn(ctrl_pipereg16_squashn), + .en(ctrl_pipereg16_en), + .q(pipereg16_q)); + //defparam + // pipereg16.WIDTH=1; + +pipereg_w1 pipereg15 ( + .clk(clk), + .resetn(ctrl_pipereg15_resetn), + .d(haz_zeroer_q_pipereg5_q), + .squashn(ctrl_pipereg15_squashn), + .en(ctrl_pipereg15_en), + .q(pipereg15_q)); + //defparam + // pipereg15.WIDTH=1; + + // Multiplexor mux2to1_nop7_d instantiation +assign mux2to1_nop7_d_out = + (pipereg16_q==1) ? pipereg14_q : + reg_file_b_readdataout; + +pipereg_w6 pipereg12 ( + .clk(clk), + .resetn(ctrl_pipereg12_resetn), + .d(ifetch_func), + .squashn(ctrl_pipereg12_squashn), + .en(ctrl_pipereg12_en), + .q(pipereg12_q)); + //defparam + // pipereg12.WIDTH=6; + +pipereg_w5 pipereg13 ( + .clk(clk), + .resetn(ctrl_pipereg13_resetn), + .d(ifetch_rt), + .squashn(ctrl_pipereg13_squashn), + .en(ctrl_pipereg13_en), + .q(pipereg13_q)); + //defparam + // pipereg13.WIDTH=5; + + + +endmodule + +/**************************************************************************** + AddSub unit +- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU + + is_slt signext addsub + op[2] op[1] op[0] | Operation +0 0 0 0 SUBU +2 0 1 0 SUB +1 0 0 1 ADDU +3 0 1 1 ADD +4 1 0 0 SLTU +6 1 1 0 SLT + +****************************************************************************/ +module addersub ( + opB, + opA, + op, + result_slt, + result +); + +//parameter WIDTH=32; +//`DEFINE WIDTH 32 + + +input [31:0] opA; +input [31:0] opB; +//input carry_in; +input [2:0] op; +output result_slt; +output [31:0] result; + + + +wire [32:0] sum; + + +wire addsub; +wire useless; +assign useless = op[1] & op[2]; + + +assign addsub=op[0]; +wire not_addsub; +assign not_addsub = ~addsub; + +assign result=sum[31:0]; + +assign result_slt=sum[32]; + +dummy_add_sub adder32bit (opA,opB,not_addsub,sum); + + +// This is an LPM from Altera, replacing with a dummy one for now +/* +lpm_add_sub adder_inst( + .dataa({signext&opA[WIDTH-1],opA}), + .datab({signext&opB[WIDTH-1],opB}), + .cin(~addsub), + .add_sub(addsub), + .result(sum) + // synopsys translate_off + , + .cout (), + .clken (), + .clock (), + .overflow (), + .aclr () + // synopsys translate_on + ); +//defparam +// adder_inst.lpm_width=WIDTH+1, +// adder_inst.lpm_representation="SIGNED"; +*/ + +endmodule + + + + + +module dummy_add_sub ( + dataa, + datab, + cin, + result +); + +//this is goign to be UUUUGGGGGGLLLYYYYY +//probably going to do some serious timing violations +// but i'm sure it will be interesting for the packing problem +input [31:0] dataa; +input [31:0] datab; +input cin; +output [32:0] result; +// +wire [31:0] carry_from; +wire [31:0] sum; + + +full_adder bit0 (cin,dataa[0],datab[0],sum[0],carry_from [0]); +full_adder bit1 (carry_from [0],dataa[1],datab[1],sum[1],carry_from [1]); +full_adder bit2 (carry_from [1],dataa[2],datab[2],sum[2],carry_from [2]); +full_adder bit3 (carry_from [2],dataa[3],datab[3],sum[3],carry_from [3]); +full_adder bit4 (carry_from [3],dataa[4],datab[4],sum[4],carry_from [4]); +full_adder bit5 (carry_from [4],dataa[5],datab[5],sum[5],carry_from [5]); +full_adder bit6 (carry_from [5],dataa[6],datab[6],sum[6],carry_from [6]); +full_adder bit7 (carry_from [6],dataa[7],datab[7],sum[7],carry_from [7]); + +full_adder bit8 (carry_from [7],dataa[8],datab[8],sum[8],carry_from [8]); +full_adder bit9 (carry_from [8],dataa[9],datab[9],sum[9],carry_from [9]); +full_adder bit10 (carry_from [9],dataa[10],datab[10],sum[10],carry_from [10]); +full_adder bit11 (carry_from [10],dataa[11],datab[11],sum[11],carry_from [11]); +full_adder bit12 (carry_from [11],dataa[12],datab[12],sum[12],carry_from [12]); +full_adder bit13 (carry_from [12],dataa[13],datab[13],sum[13],carry_from [13]); +full_adder bit14 (carry_from [13],dataa[14],datab[14],sum[14],carry_from [14]); +full_adder bit15 (carry_from [14],dataa[15],datab[15],sum[15],carry_from [15]); + +full_adder bit16 (carry_from [15],dataa[16],datab[16],sum[16],carry_from [16]); +full_adder bit17 (carry_from [16],dataa[17],datab[17],sum[17],carry_from [17]); +full_adder bit18 (carry_from [17],dataa[18],datab[18],sum[18],carry_from [18]); +full_adder bit19 (carry_from [18],dataa[19],datab[19],sum[19],carry_from [19]); +full_adder bit20 (carry_from [19],dataa[20],datab[20],sum[20],carry_from [20]); +full_adder bit21 (carry_from [20],dataa[21],datab[21],sum[21],carry_from [21]); +full_adder bit22 (carry_from [21],dataa[22],datab[22],sum[22],carry_from [22]); +full_adder bit23 (carry_from [22],dataa[23],datab[23],sum[23],carry_from [23]); + +full_adder bit24 (carry_from [23],dataa[24],datab[24],sum[24],carry_from [24]); +full_adder bit25 (carry_from [24],dataa[25],datab[25],sum[25],carry_from [25]); +full_adder bit26 (carry_from [25],dataa[26],datab[26],sum[26],carry_from [26]); +full_adder bit27 (carry_from [26],dataa[27],datab[27],sum[27],carry_from [27]); +full_adder bit28 (carry_from [27],dataa[28],datab[28],sum[28],carry_from [28]); +full_adder bit29 (carry_from [28],dataa[29],datab[29],sum[29],carry_from [29]); +full_adder bit30 (carry_from [29],dataa[30],datab[30],sum[30],carry_from [30]); +full_adder bit31 (carry_from [30],dataa[31],datab[31],sum[31],carry_from [31]); + +assign result [31:0] = sum; +assign result [32] = carry_from [31]; + +endmodule + + +module full_adder (cin,x,y,s,cout); +input cin; +input x; +input y; +output s; +output cout; +assign s = x^y^cin; +assign cout = (x&y) | (x & cin) | (y&cin); +endmodule + +/**************************************************************************** + Register File + + - Has two read ports (a and b) and one write port (c) + - sel chooses the register to be read/written +****************************************************************************/ + +module reg_file( + clk, + resetn, + c_writedatain, + c_reg, + b_reg, + a_reg, + c_we, + b_en, + a_en, + b_readdataout, + a_readdataout +); +//parameter WIDTH=32; +//parameter NUMREGS=32; +//parameter LOG2NUMREGS=5; +input clk; +input resetn; + +input a_en; +input b_en; +input [31:0] c_writedatain; +input c_we; +input [31:0] a_reg; +input [31:0] b_reg; +input [31:0] c_reg; +output [31:0] a_readdataout; +output [31:0] b_readdataout; +reg [31:0] a_readdataout; +reg [31:0] b_readdataout; + + +wire [31:0] a_readdataout_temp; +wire [31:0] b_readdataout_temp; + + +assign b_readdataout = b_readdataout_temp; +assign a_readdataout = a_readdataout_temp; + +wire wren1; +assign wren1 = (c_we & (|c_reg)); +single_port_ram regfile1_replace ( + .clk (clk), + .we(wren1), + .data(c_writedatain), + .out(a_readdataout_temp), + .addr(c_reg[4:0]) +); + +//Reg file duplicated to avoid contention +//between 2 read and 1 write +//MORE MEMORY + +single_port_ram regfile2_replace( + .clk (clk), + .we(wren1), + .data(c_writedatain), + .out(b_readdataout_temp), + .addr(c_reg[4:0]) +); + +//Odin II does not recognize that address +//registers are being used to read and +//write data, so they are assigned to an +//unused wire which is later dropped by the +//optimizer. +wire useless_inputs; +//`a_reg` and `b_reg` were not used correctly in last version +//of `spree.v` according to the comment above this module. +//Investigate whether the comment or the code is wrong +assign useless_inputs = resetn & b_en & a_en & ( | a_reg ) & ( | b_reg ); +endmodule + +/**************************************************************************** + MUL/DIV unit + +Operation table + + op sign dir +4 1 0 x | MULTU +6 1 1 x | MULT +0 0 0 0 | ShiftLeft +1 0 0 1 | ShiftRightLogic +3 0 1 1 | ShiftRightArith +****************************************************************************/ +module mul( + clk, + resetn, + sa, + dst, + opB, + opA, + op, + start, + stalled, + shift_result, + lo, + hi +); + +input clk; +input resetn; + +input start; +output stalled; + +input [4:0] dst; + +input [31:0] opA; +input [31:0] opB; +input [4:0] sa; +input [2:0] op; + +output [31:0] shift_result; +output [31:0] hi; +output [31:0] lo; + +/********* Control Signals *********/ +wire is_signed; +wire dir; +wire is_mul; +assign is_mul=op[2]; // selects between opB and the computed shift amount +assign is_signed=op[1]; +assign dir=op[0]; // selects between 2^sa and 2^(32-sa) for right shift + +/********* Circuit Body *********/ +wire dum; +wire dum2; +wire dum3; +wire [32:0] opB_mux_out; +wire [4:0] left_sa; // Amount of left shift required for both left/right +reg [32:0] decoded_sa; +wire [31:0] result; +//assign opB_mux_out= (is_mul) ? {is_signed&opB[31],opB} : decoded_sa; +assign opB_mux_out = opB; + + + +dummy_mult fake_mult_one (opA,opB_mux_out, clk, resetn, result); +assign hi = result [15:8]; +assign lo = result [7:0]; +// Cannot support this now +/* +lpm_mult lpm_mult_component ( + .dataa ({is_signed&opA[31],opA}), + .datab (opB_mux_out), + .sum(), + .clock(clk), + .clken(), + .aclr(~resetn), + .result ({dum2,dum,hi,lo})); +defparam + lpm_mult_component.lpm_32a = 32+1, + lpm_mult_component.lpm_32b = 32+1, + lpm_mult_component.lpm_32p = 2*32+2, + lpm_mult_component.lpm_32s = 1, + lpm_mult_component.lpm_pipeline = 1, + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_representation = "SIGNED", + lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6"; +*/ +assign shift_result= (dir & |sa) ? hi : lo; + + +// 1 cycle stall state machine +wire or_dst; +wire start_and_ismul; +wire request; + +assign or_dst = |dst; +assign start_and_ismul = start & is_mul; +assign request = (or_dst & start & ~is_mul) | (start_and_ismul); +onecyclestall staller(request,clk,resetn,stalled); + + +endmodule + +module dummy_mult ( + opA, + opB_mux_out, + clk, + resetn, + result +); + +input [31:0] opA; +input [31:0] opB_mux_out; +input clk; +input resetn; +output[31:0] result; +reg [31:0] result; + + +always @ (posedge clk) +begin + if (resetn) + result <= 32'b00000000000000000000000000000000; + else + //multiplier by star symbol + //though this is probably supposed to be signed + result <= opA * opB_mux_out; +end +endmodule + + +/**************************************************************************** + Fetch Unit +op + 0 Conditional PC write + 1 UnConditional PC write + +****************************************************************************/ + +module ifetch( + clk, + resetn, + boot_iaddr, + boot_idata, + boot_iwe, + load, + load_data, + op, + we, + squashn, + en, + pc_out, + instr, + opcode, + func, + rs, + rt, + rd, + instr_index, + offset, + sa, + next_pc +); + +//parameter PC_WIDTH=30; +//parameter I_DATAWIDTH=32; +//parameter I_ADDRESSWIDTH=14; +//parameter I_SIZE=16384; + +input [31:0] boot_iaddr; +input [31:0] boot_idata; +input boot_iwe; + +input clk; +input resetn; +input en; // PC increment enable +input we; // PC write enable +input squashn;// squash fetch +input op; // determines if conditional or unconditional branch +input load; +input [`I_DATAWIDTH-1:0] load_data; +output [`I_DATAWIDTH-1:0] pc_out; // output pc + 1 shifted left 2 bits +output [`PC_WIDTH-1:0] next_pc; +output [31:26] opcode; +output [25:21] rs; +output [20:16] rt; +output [15:11] rd; +output [10:6] sa; +output [15:0] offset; +output [25:0] instr_index; +output [5:0] func; +output [`I_DATAWIDTH-1:0] instr; + + +wire [`PC_WIDTH-1:0] pc_plus_1; +wire [`PC_WIDTH-1:0] pc; +assign pc_plus_1 = pc; +wire ctrl_load; +wire out_of_sync; + +assign ctrl_load=(load&~op|op); +wire notresetn; +assign notresetn = ~resetn; +wire count_en; +assign count_en = (~ctrl_load)&~out_of_sync; +wire counter_en; +assign counter_en = en | we; +wire [32:2] reg_load_data; + +assign reg_load_data = load_data [31:2]; + +wire reg_d; +wire reg_en; +assign reg_d = (we&(~en)&(squashn)); +assign reg_en = en|we; + + +register_1bit sync_pcs_up( reg_d, clk, resetn,reg_en, out_of_sync); + +wire wren1; +assign wren1 = 1'b0; +wire [9:0] next_pc_wire; +assign next_pc_wire = next_pc [9:0]; + +wire [31:0]dummyout2; + +dual_port_ram imem_replace( + .clk (clk), + .we1(wren1), + .we2(boot_iwe), + .data1(load_data), + .data2(boot_idata), + .out1(instr), + .out2(dummyout2), + .addr1(next_pc_wire), + .addr2(boot_iaddr[9:0]) +); + +wire [31:0] dummyin1; +assign dummyin1 = 32'b00000000000000000000000000000000; + +dummy_counter pc_reg ((reg_load_data),(clk),(counter_en),(count_en),(notresetn),(ctrl_load),(pc)); +assign pc_out [31:2] = pc_plus_1; +assign pc_out [1:0] = 2'b00; + +assign next_pc = ctrl_load ? load_data[31:2] : pc_plus_1; +assign opcode=instr[31:26]; +assign rs=instr[25:21]; +assign rt=instr[20:16]; +assign rd=instr[15:11]; +assign sa=instr[10:6]; +assign offset=instr[15:0]; +assign instr_index=instr[25:0]; +assign func=instr[5:0]; + +//Odin II does not recognize that boot_iaddr +//is being used to write data when system +//is given 1'b1 on the boot_iwe wire so is +//is assigned to an unused wire which is +//later dropped by the optimizer. +wire NoUse; +assign NoUse = ( |boot_iaddr ); + +endmodule + + +module dummy_counter ( + data, + clock, + clk_en, + cnt_en, + aset, + sload, + q +); + +input [31:2] data; +input clock; +input clk_en; +input cnt_en; +input aset; +input sload; +output [`PC_WIDTH-1:0] q; +reg [`PC_WIDTH-1:0] q; + +wire [2:0] sload_cnten_aset; +assign sload_cnten_aset [0] = sload; +assign sload_cnten_aset [1] = cnt_en; +assign sload_cnten_aset [2] = aset; + +always @ (posedge clock) + +//if (cnt_en == 1) +//q <= q+1; +begin + +case (sload_cnten_aset) + 3'b000: + q <= q; + 3'b011: + q <= q; + 3'b110: + q <= q; + 3'b111: + q <= q; + 3'b101: + q <= q; + 3'b100: + q <= data; + 3'b010: + begin + if (clk_en) + q <= q+1; + else + q <= q; + end + 3'b001: + q <= 29'b00000000000000000000000000000; + default: + q <= q; +endcase +end +endmodule + + + + +module data_mem( + clk, + resetn, + stalled, + d_writedata, + d_address, + op, + d_loadresult +); + +input clk; +input resetn; +output stalled; + +input [`D_ADDRESSWIDTH-1:0] d_address; +input [3:0] op; +input [31:0] d_writedata; +output [`DM_DATAWIDTH-1:0] d_loadresult; + +wire [`DM_BYTEENAWIDTH-1:0] d_byteena; +wire [`DM_DATAWIDTH-1:0] d_readdatain; +wire [`DM_DATAWIDTH-1:0] d_writedatamem; + +wire d_write; +wire [1:0] d_address_latched; + +assign d_write=op[3]; + +wire [1:0] d_small_adr; +assign d_small_adr = d_address[1:0]; + +wire one; +assign one = 1'b1; + + +wire [1:0] d_adr_one_zero; +assign d_adr_one_zero = d_address [1:0]; + +wire [1:0] opsize; +assign opsize = op[1:0]; +wire opext; +assign opext = op[2]; + + +store_data_translator sdtrans_inst( + .write_data(d_writedata), + .d_address(d_adr_one_zero), + .store_size(op[1:0]), + .d_byteena(d_byteena), + .d_writedataout(d_writedatamem) +); + + + +load_data_translator ldtrans_inst( + .d_readdatain(d_readdatain), + .d_loadresult(d_loadresult) +); + + +wire dnot_address; +assign dnot_address = ~d_address[31]; +wire will_be_wren1; +assign will_be_wren1 = d_write&(dnot_address); + +wire [9:0] memaddr_wrd; + + +assign memaddr_wrd = d_address[`DM_ADDRESSWIDTH:2]; +single_port_ram dmem_replace( + .clk (clk), + .we(will_be_wren1), + .data(d_writedatamem), + .out(d_readdatain), + .addr(memaddr_wrd) +); +// 1 cycle stall state machine + +wire en_and_not_d_write; +assign en_and_not_d_write = ~d_write; +onecyclestall staller(en_and_not_d_write,clk,resetn,stalled); + +wire useless_inputs; +assign useless_inputs = |d_address; + +endmodule + +//temp in here + + + + +/**************************************************************************** + Store data translator + - moves store data to appropriate byte/halfword + - interfaces with altera blockrams +****************************************************************************/ +module store_data_translator( + write_data, // data in least significant position + d_address, + store_size, + d_byteena, + d_writedataout // shifted data to coincide with address +); + +//parameter WIDTH=32; + +input [31:0] write_data; +input [1:0] d_address; +input [1:0] store_size; +output [3:0] d_byteena; +output [31:0] d_writedataout; + +reg [3:0] d_byteena; +reg [31:0] d_writedataout; + +always @(write_data or d_address or store_size) +begin + case (store_size) + 2'b11: + case(d_address[1:0]) + 2'b00: + begin + d_byteena=4'b1000; + d_writedataout={write_data[7:0],24'b0}; + end + 2'b01: + begin + d_byteena=4'b0100; + d_writedataout={8'b0,write_data[7:0],16'b0}; + end + 2'b10: + begin + d_byteena=4'b0010; + d_writedataout={16'b0,write_data[7:0],8'b0}; + end + default: + begin + d_byteena=4'b0001; + d_writedataout={24'b0,write_data[7:0]}; + end + endcase + 2'b01: + case(d_address[1]) + 1'b0: + begin + d_byteena=4'b1100; + d_writedataout={write_data[15:0],16'b0}; + end + default: + begin + d_byteena=4'b0011; + d_writedataout={16'b0,write_data[15:0]}; + end + endcase + default: + begin + d_byteena=4'b1111; + d_writedataout=write_data; + end + endcase +end + +endmodule + +/**************************************************************************** + Load data translator + - moves read data to appropriate byte/halfword and zero/sign extends +****************************************************************************/ + +module load_data_translator( + d_readdatain, + d_loadresult +); + +//parameter WIDTH=32; + +input [31:0] d_readdatain; + +output [31:0] d_loadresult; + +wire d_adr_one; +assign d_adr_one = d_address [1]; +reg [31:0] d_loadresult; +reg sign; +wire [1:0] d_address; +assign d_address [1:0] =d_readdatain [25:24]; + + +//assume always full-word-access +always @(d_readdatain or d_address ) +begin + d_loadresult[31:0]=d_readdatain[31:0]; +end +/* +Odin II REFUSES TO ACKNOWLEDGE THAT SIGN EXTENDING IS NOT A COMBINATIONAL LOOP +always @(d_readdatain or d_address or load_size or load_sign_ext) +begin + case (load_size) + 2'b11: + begin + case (d_address) + 2'b00: + begin + d_loadresult[7:0]=d_readdatain[31:24]; + sign = d_readdatain[31]; + end + 2'b01: + begin + d_loadresult[7:0]=d_readdatain[23:16]; + sign = d_readdatain[23]; + end + 2'b10: + begin + d_loadresult[7:0]=d_readdatain[15:8]; + sign = d_readdatain[15]; + end + default: + begin + d_loadresult[7:0]=d_readdatain[7:0]; + sign = d_readdatain[7]; + end + endcase + // peter milankov note: do this by hand + // odin II does not support multiple concatenation + //d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}}; + d_loadresult[31]= load_sign_ext&sign; + d_loadresult[30]= load_sign_ext&sign; + d_loadresult[29]= load_sign_ext&sign; + d_loadresult[28]= load_sign_ext&sign; + d_loadresult[27]= load_sign_ext&sign; + d_loadresult[26]= load_sign_ext&sign; + d_loadresult[25]= load_sign_ext&sign; + d_loadresult[24]= load_sign_ext&sign; + d_loadresult[23]= load_sign_ext&sign; + d_loadresult[22]= load_sign_ext&sign; + d_loadresult[21]= load_sign_ext&sign; + d_loadresult[20]= load_sign_ext&sign; + d_loadresult[19]= load_sign_ext&sign; + d_loadresult[18]= load_sign_ext&sign; + d_loadresult[17]= load_sign_ext&sign; + d_loadresult[16]= load_sign_ext&sign; + d_loadresult[15]= load_sign_ext&sign; + d_loadresult[14]= load_sign_ext&sign; + d_loadresult[13]= load_sign_ext&sign; + d_loadresult[12]= load_sign_ext&sign; + d_loadresult[11]= load_sign_ext&sign; + d_loadresult[10]= load_sign_ext&sign; + d_loadresult[9]= load_sign_ext&sign; + d_loadresult[8]= load_sign_ext&sign; + end + 2'b01: + begin + case (d_adr_one) + 1'b0: + begin + d_loadresult[15:0]=d_readdatain[31:16]; + sign = d_readdatain[31]; + end + default: + begin + d_loadresult[15:0]=d_readdatain[15:0]; + sign = d_readdatain[15]; + end + endcase +// peter milankov note sign extend is concat, do by hand + //d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}}; + d_loadresult[31]= load_sign_ext&sign; + d_loadresult[30]= load_sign_ext&sign; + d_loadresult[29]= load_sign_ext&sign; + d_loadresult[28]= load_sign_ext&sign; + d_loadresult[27]= load_sign_ext&sign; + d_loadresult[26]= load_sign_ext&sign; + d_loadresult[25]= load_sign_ext&sign; + d_loadresult[24]= load_sign_ext&sign; + d_loadresult[23]= load_sign_ext&sign; + d_loadresult[22]= load_sign_ext&sign; + d_loadresult[21]= load_sign_ext&sign; + d_loadresult[20]= load_sign_ext&sign; + d_loadresult[19]= load_sign_ext&sign; + d_loadresult[18]= load_sign_ext&sign; + d_loadresult[17]= load_sign_ext&sign; + d_loadresult[16]= load_sign_ext&sign; + end + default: + d_loadresult[31:0]=d_readdatain[31:0]; + endcase +end +*/ +endmodule + +/**************************************************************************** + logic unit +- note ALU must be able to increment PC for JAL type instructions + +Operation Table + op + 0 AND + 1 OR + 2 XOR + 3 NOR +****************************************************************************/ +module logic_unit ( + opB, + opA, + op, + result +); + +//parameter WIDTH=32; + +input [31:0] opA; +input [31:0] opB; +input [1:0] op; +output [31:0] result; + +reg [31:0] logic_result; + +always@(opA or opB or op ) + case(op) + 2'b00: + logic_result=opA&opB; + 2'b01: + logic_result=opA|opB; + 2'b10: + logic_result=opA^opB; + 2'b11: + logic_result=~(opA|opB); + endcase + +assign result=logic_result; + + +endmodule + +module pcadder( + offset, + pc, + result +); + +//parameter PC_WIDTH=32; + + +input [31:0] pc; +input [31:0] offset; +output [31:0] result; + +wire dum; +wire useless_inputs; +assign useless_inputs = |offset; +assign {dum,result} = pc + {offset[31:0],2'b0}; + +endmodule + + +module signext16 (in, out); + +input [15:0] in; +output [31:0] out; + + +assign out [30]= in[15]; +assign out [31]= in[15]; +assign out [29]= in[15]; +assign out [28]= in[15]; +assign out [27]= in[15]; +assign out [26]= in[15]; +assign out [25]= in[15]; +assign out [24]= in[15]; +assign out [23]= in[15]; +assign out [22]= in[15]; +assign out [21]= in[15]; +assign out [20]= in[15]; +assign out [19]= in[15]; +assign out [18]= in[15]; +assign out [17]= in[15]; +assign out [16]= in[15]; +assign out [15:0] = in [15:0]; + +endmodule + + +module merge26lo(in2, in1, out); +input [31:0] in1; +input [25:0] in2; +output [31:0] out; + +//assign out[31:0]={in1[31:28],in2[25:0],2'b0}; + +assign out [31:28] = in1 [31:28]; +assign out [27:2] = in2 [25:0]; +assign out [1:0] = 2'b00; + + +wire useless_inputs; +assign useless_inputs = |in1 & |in2; +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ +module lo_reg( + clk, + resetn, + d, + en, + q +); + +//parameter WIDTH=32; + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ +module hi_reg( + clk, + resetn, + d, + en, + q +); + +//parameter WIDTH=32; + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) //used to be asynchronous reset +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ + +//`define WIDTH 32 +/* +module register(d,clk,resetn,en,q); +//parameter WIDTH=32; + + + + + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +module register_1bit( + d, + clk, + resetn, + en, + q +); + +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input d; +output q; +reg q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +/**************************************************************************** + Generic Register - synchronous reset +****************************************************************************/ +/* +module register_sync(d,clk,resetn,en,q); +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +/**************************************************************************** + Generic Pipelined Register + + - Special component, components starting with "pipereg" have + their enables treated independently of instructrions that use them. + - They are enabled whenever the stage is active and not stalled +****************************************************************************/ +/* +module pipereg(clk,resetn,d,squashn,en,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +module pipereg_w32( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +module pipereg_w26( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [25:0] d; +output [25:0] q; +reg [25:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +module pipereg_w6( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + begin + q[5:0]<=d; + q[31:6] <= 0; + + end +end + +endmodule + + +module pipereg_w5( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + begin + q[4:0]<=d; + q[31:5] <= 0; + + end +end + +endmodule + +module pipereg_w1( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input d; +output q; +reg q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Pipelined Register 2 -OLD: If not enabled, queues squash + + - This piperegister stalls the reset signal as well +*/ +/* +module pipereg_full(d,clk,resetn,squashn,en,q); +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; +reg squash_save; + + always @(posedge clk) //synchronous reset + begin + if (resetn==0 || (squashn==0 && en==1) || (squash_save&en)) + q<=0; + else if (en==1) + q<=d; + end + + always @(posedge clk) + begin + if (resetn==1 && squashn==0 && en==0) + squash_save<=1; + else + squash_save<=0; + end +endmodule +*/ +/****************************************************************************/ + +/**************************************************************************** + One cycle Stall circuit +****************************************************************************/ +module onecyclestall( + request, + clk, + resetn, + stalled +); + +input request; +input clk; +input resetn; +output stalled; + + reg T,Tnext; + + // State machine for Stalling 1 cycle + always@(request or T) + begin + case(T) + 1'b0: Tnext=request; + 1'b1: Tnext=0; + endcase + end + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=Tnext; + assign stalled=(request&~T); +endmodule + +/**************************************************************************** + + Multi cycle Stall circuit - with wait signal + + - One FF plus one 2:1 mux to stall 1st cycle on request, then wait + - this makes wait don't care for the first cycle +****************************************************************************/ +/* +module multicyclestall(request, devwait,clk,resetn,stalled); +input request; +input devwait; +input clk; +input resetn; +output stalled; + + reg T; + + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=stalled; + + assign stalled=(T) ? devwait : request; +endmodule +*/ +/**************************************************************************** + One cycle - Pipeline delay register +****************************************************************************/ +/* +module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q); +//`define WIDTH 32 +//parameter WIDTH=32; +input [31:0] d; +input [4:0] dst; +input en; +input clk; +input resetn; +input squashn; +output stalled; +output [31:0] q; + + reg [31:0] q; + reg T,Tnext; + + // State machine for Stalling 1 cycle + always@(en or T or dst) + begin + case(T) + 0: Tnext=en&(|dst); + 1: Tnext=0; + endcase + end + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=Tnext; + + always @(posedge clk) //synchronous reset + begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; + end + + assign stalled=(en&~T&(|dst)); +endmodule +*/ + +/**************************************************************************** + Fake Delay +****************************************************************************/ +module fakedelay(clk,d,q); +//`define WIDTH 32 +//parameter WIDTH=32; +input [31:0] d; +input clk; +output [31:0] q; + +wire unused; +assign unused = clk; +assign q=d; + +endmodule + +/**************************************************************************** + Zeroer +****************************************************************************/ +module zeroer(d,en,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input en; +input [4:0] d; +output [31:0] q; +assign q[4:0]= (en) ? d : 0; +assign q [31:05] = 0; + +endmodule + +/**************************************************************************** + NOP - used to hack position of multiplexors +****************************************************************************/ +module nop(d,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input [31:0] d; +output [31:0] q; + + assign q=d; + +endmodule + +/**************************************************************************** + + Const +****************************************************************************/ + +/**************************************************************************** + Branch detector +****************************************************************************/ +/* +module branch_detector(opcode, func, is_branch); + + +input [5:0] opcode; +input [5:0] func; +output is_branch; + +wire is_special; + +assign is_special=!(|opcode); +assign is_branch=((!(|opcode[5:3])) && !is_special) || + ((is_special)&&(func[5:3]==3'b001)); + +endmodule +*/ +//`define WIDTH 32 + +module branchresolve ( + rt, + rs, + en, + eqz, + gez, + gtz, + lez, + ltz, + ne, + eq +); + +//parameter WIDTH=32; + +input en; +input [31:0] rs; +input [31:0] rt; +output eq; +output ne; +output ltz; +output lez; +output gtz; +output gez; +output eqz; + +assign eq=(en)&(rs==rt); +assign ne=(en)&~eq; +assign eqz=(en)&~(|rs); +assign ltz=(en)&rs[31]; +assign lez=(en)&rs[31] | eqz; +assign gtz=(en)&(~rs[31]) & ~eqz; +assign gez=(en)&(~rs[31]); + +endmodule + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v new file mode 100755 index 000000000..14708a142 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v @@ -0,0 +1,3905 @@ +// Ahmad Darabiha +// last updated Aug, 2002 +// this is the design for chip#0 of +// the stereo vision system. +// this is the last stage which interpolates the results of correlation +// and after LPF it takes the Max and send the final results to chip #3 to +// be displayed on the monitor. + +module sv_chip0_hierarchy_no_mem (tm3_clk_v0, bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_left_2to0, v_nd_s2_left_2to0 , v_nd_s4_left_2to0 , v_d_reg_s1_left_2to0 , v_d_reg_s2_left_2to0 , v_d_reg_s4_left_2to0 , v_nd_s1_right_2to0, v_nd_s2_right_2to0 , v_nd_s4_right_2to0 , v_d_reg_s1_right_2to0 , v_d_reg_s2_right_2to0 , v_d_reg_s4_right_2to0 , tm3_vidout_red,tm3_vidout_green,tm3_vidout_blue , tm3_vidout_clock,tm3_vidout_hsync,tm3_vidout_vsync,tm3_vidout_blank , x_in, y_in, depth_out, offchip_sram_data_in,offchip_sram_addr,offchip_sram_data_out,offchip_sram_we,offchip_sram_oe); + + + input tm3_clk_v0; + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + wire[63:0] tm3_sram_data_in; + + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + + reg tm3_sram_adsp; + input[7:0] bus_word_1_1to0; + input[7:0] bus_word_2_1to0; + input[7:0] bus_word_3_1to0; + input[7:0] bus_word_4_1to0; + input[7:0] bus_word_5_1to0; + input[7:0] bus_word_6_1to0; + input[2:0] counter_out_1to0; + input vidin_new_data_fifo; + input[7:0] vidin_rgb_reg_fifo_left; + input[7:0] vidin_rgb_reg_fifo_right; + input[3:0] vidin_addr_reg_2to0; + output v_nd_s1_left_2to0; + reg v_nd_s1_left_2to0; + output v_nd_s2_left_2to0; + reg v_nd_s2_left_2to0; + output v_nd_s4_left_2to0; + reg v_nd_s4_left_2to0; + output[7:0] v_d_reg_s1_left_2to0; + reg[7:0] v_d_reg_s1_left_2to0; + output[7:0] v_d_reg_s2_left_2to0; + reg[7:0] v_d_reg_s2_left_2to0; + output[7:0] v_d_reg_s4_left_2to0; + reg[7:0] v_d_reg_s4_left_2to0; + output v_nd_s1_right_2to0; + reg v_nd_s1_right_2to0; + output v_nd_s2_right_2to0; + reg v_nd_s2_right_2to0; + output v_nd_s4_right_2to0; + reg v_nd_s4_right_2to0; + output[7:0] v_d_reg_s1_right_2to0; + reg[7:0] v_d_reg_s1_right_2to0; + output[7:0] v_d_reg_s2_right_2to0; + reg[7:0] v_d_reg_s2_right_2to0; + output[7:0] v_d_reg_s4_right_2to0; + reg[7:0] v_d_reg_s4_right_2to0; + output[9:0] tm3_vidout_red; + reg[9:0] tm3_vidout_red; + output[9:0] tm3_vidout_green; + reg[9:0] tm3_vidout_green; + output[9:0] tm3_vidout_blue; + reg[9:0] tm3_vidout_blue; + output tm3_vidout_clock; + wire tm3_vidout_clock; + output tm3_vidout_hsync; + reg tm3_vidout_hsync; + output tm3_vidout_vsync; + reg tm3_vidout_vsync; + output tm3_vidout_blank; + reg tm3_vidout_blank; + input[15:0] x_in; + input[15:0] y_in; + output[15:0] depth_out; + reg[15:0] depth_out; + reg[15:0] x_reg_l; + reg[15:0] x_reg_r; + reg[15:0] y_reg_up; + reg[15:0] y_reg_dn; + reg[7:0] depth_out_reg; + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[63:0] vidout_buf; + reg[63:0] vidin_data_buf_sc_2; + reg[55:0] vidin_data_buf_2_sc_2; + reg[18:0] vidin_addr_buf_sc_2; + reg[63:0] vidin_data_buf_sc_4; + reg[55:0] vidin_data_buf_2_sc_4; + reg[18:0] vidin_addr_buf_sc_4; + reg video_state; + reg vidin_new_data_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_right_reg; + reg vidin_new_data_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_right_reg; + reg vidin_new_data_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_right_reg; + reg[18:0] vidin_addr_reg_2to3_reg; + wire[18:0] vidin_addr_reg; + wire svid_comp_switch_2to3; + wire vidin_new_data_scld_1_1to0; + wire vidin_new_data_scld_2_1to0; + wire vidin_new_data_scld_4_1to0; + wire[7:0] v_corr_200; + wire[7:0] v_corr_201; + wire[7:0] v_corr_202; + wire[7:0] v_corr_203; + wire[7:0] v_corr_204; + wire[7:0] v_corr_205; + wire[7:0] v_corr_206; + wire[7:0] v_corr_207; + wire[7:0] v_corr_208; + wire[7:0] v_corr_209; + wire[7:0] v_corr_2010; + wire[7:0] v_corr_2011; + wire[7:0] v_corr_2012; + wire[7:0] v_corr_2013; + wire[7:0] v_corr_2014; + wire[7:0] v_corr_2015; + wire[7:0] v_corr_2016; + wire[7:0] v_corr_2017; + wire[7:0] v_corr_2018; + wire[7:0] v_corr_2019; + wire[7:0] v_corr_2020; + wire[7:0] v_corr_100; + wire[7:0] v_corr_101; + wire[7:0] v_corr_102; + wire[7:0] v_corr_103; + wire[7:0] v_corr_104; + wire[7:0] v_corr_105; + wire[7:0] v_corr_106; + wire[7:0] v_corr_107; + wire[7:0] v_corr_108; + wire[7:0] v_corr_109; + wire[7:0] v_corr_1010; + wire[7:0] v_corr_50; + wire[7:0] v_corr_51; + wire[7:0] v_corr_52; + wire[7:0] v_corr_53; + wire[7:0] v_corr_54; + wire[7:0] v_corr_55; + wire[7:0] v_corr_20_fltr0; + wire[7:0] v_corr_20_fltr1; + wire[7:0] v_corr_20_fltr2; + wire[7:0] v_corr_20_fltr3; + wire[7:0] v_corr_20_fltr4; + wire[7:0] v_corr_20_fltr5; + wire[7:0] v_corr_20_fltr6; + wire[7:0] v_corr_20_fltr7; + wire[7:0] v_corr_20_fltr8; + wire[7:0] v_corr_20_fltr9; + wire[7:0] v_corr_20_fltr10; + wire[7:0] v_corr_20_fltr11; + wire[7:0] v_corr_20_fltr12; + wire[7:0] v_corr_20_fltr13; + wire[7:0] v_corr_20_fltr14; + wire[7:0] v_corr_20_fltr15; + wire[7:0] v_corr_20_fltr16; + wire[7:0] v_corr_20_fltr17; + wire[7:0] v_corr_20_fltr18; + wire[7:0] v_corr_20_fltr19; + wire[7:0] v_corr_20_fltr20; + wire[7:0] v_corr_10_fltr0; + wire[7:0] v_corr_10_fltr1; + wire[7:0] v_corr_10_fltr2; + wire[7:0] v_corr_10_fltr3; + wire[7:0] v_corr_10_fltr4; + wire[7:0] v_corr_10_fltr5; + wire[7:0] v_corr_10_fltr6; + wire[7:0] v_corr_10_fltr7; + wire[7:0] v_corr_10_fltr8; + wire[7:0] v_corr_10_fltr9; + wire[7:0] v_corr_10_fltr10; + wire[7:0] v_corr_5_fltr0; + wire[7:0] v_corr_5_fltr1; + wire[7:0] v_corr_5_fltr2; + wire[7:0] v_corr_5_fltr3; + wire[7:0] v_corr_5_fltr4; + wire[7:0] v_corr_5_fltr5; + wire[7:0] v_corr_20_fltr_x0; + wire[7:0] v_corr_20_fltr_x1; + wire[7:0] v_corr_20_fltr_x2; + wire[7:0] v_corr_20_fltr_x3; + wire[7:0] v_corr_20_fltr_x4; + wire[7:0] v_corr_20_fltr_x5; + wire[7:0] v_corr_20_fltr_x6; + wire[7:0] v_corr_20_fltr_x7; + wire[7:0] v_corr_20_fltr_x8; + wire[7:0] v_corr_20_fltr_x9; + wire[7:0] v_corr_20_fltr_x10; + wire[7:0] v_corr_20_fltr_x11; + wire[7:0] v_corr_20_fltr_x12; + wire[7:0] v_corr_20_fltr_x13; + wire[7:0] v_corr_20_fltr_x14; + wire[7:0] v_corr_20_fltr_x15; + wire[7:0] v_corr_20_fltr_x16; + wire[7:0] v_corr_20_fltr_x17; + wire[7:0] v_corr_20_fltr_x18; + wire[7:0] v_corr_20_fltr_x19; + wire[7:0] v_corr_20_fltr_x20; + wire[7:0] v_corr_10_fltr_x0; + wire[7:0] v_corr_10_fltr_x1; + wire[7:0] v_corr_10_fltr_x2; + wire[7:0] v_corr_10_fltr_x3; + wire[7:0] v_corr_10_fltr_x4; + wire[7:0] v_corr_10_fltr_x5; + wire[7:0] v_corr_10_fltr_x6; + wire[7:0] v_corr_10_fltr_x7; + wire[7:0] v_corr_10_fltr_x8; + wire[7:0] v_corr_10_fltr_x9; + wire[7:0] v_corr_10_fltr_x10; + wire[7:0] v_corr_5_fltr_x0; + wire[7:0] v_corr_5_fltr_x1; + wire[7:0] v_corr_5_fltr_x2; + wire[7:0] v_corr_5_fltr_x3; + wire[7:0] v_corr_5_fltr_x4; + wire[7:0] v_corr_5_fltr_x5; + wire[7:0] v_corr_20_fltr_h0; + wire[7:0] v_corr_20_fltr_h1; + wire[7:0] v_corr_20_fltr_h2; + wire[7:0] v_corr_20_fltr_h3; + wire[7:0] v_corr_20_fltr_h4; + wire[7:0] v_corr_20_fltr_h5; + wire[7:0] v_corr_20_fltr_h6; + wire[7:0] v_corr_20_fltr_h7; + wire[7:0] v_corr_20_fltr_h8; + wire[7:0] v_corr_20_fltr_h9; + wire[7:0] v_corr_20_fltr_h10; + wire[7:0] v_corr_20_fltr_h11; + wire[7:0] v_corr_20_fltr_h12; + wire[7:0] v_corr_20_fltr_h13; + wire[7:0] v_corr_20_fltr_h14; + wire[7:0] v_corr_20_fltr_h15; + wire[7:0] v_corr_20_fltr_h16; + wire[7:0] v_corr_20_fltr_h17; + wire[7:0] v_corr_20_fltr_h18; + wire[7:0] v_corr_20_fltr_h19; + wire[7:0] v_corr_20_fltr_h20; + wire[7:0] v_corr_10_fltr_h0; + wire[7:0] v_corr_10_fltr_h1; + wire[7:0] v_corr_10_fltr_h2; + wire[7:0] v_corr_10_fltr_h3; + wire[7:0] v_corr_10_fltr_h4; + wire[7:0] v_corr_10_fltr_h5; + wire[7:0] v_corr_10_fltr_h6; + wire[7:0] v_corr_10_fltr_h7; + wire[7:0] v_corr_10_fltr_h8; + wire[7:0] v_corr_10_fltr_h9; + wire[7:0] v_corr_10_fltr_h10; + wire[7:0] v_corr_5_fltr_h0; + wire[7:0] v_corr_5_fltr_h1; + wire[7:0] v_corr_5_fltr_h2; + wire[7:0] v_corr_5_fltr_h3; + wire[7:0] v_corr_5_fltr_h4; + wire[7:0] v_corr_5_fltr_h5; + wire[7:0] v_corr_20_fifo0; + wire[7:0] v_corr_20_fifo1; + wire[7:0] v_corr_20_fifo2; + wire[7:0] v_corr_20_fifo3; + wire[7:0] v_corr_20_fifo4; + wire[7:0] v_corr_20_fifo5; + wire[7:0] v_corr_20_fifo6; + wire[7:0] v_corr_20_fifo7; + wire[7:0] v_corr_20_fifo8; + wire[7:0] v_corr_20_fifo9; + wire[7:0] v_corr_20_fifo10; + wire[7:0] v_corr_20_fifo11; + wire[7:0] v_corr_20_fifo12; + wire[7:0] v_corr_20_fifo13; + wire[7:0] v_corr_20_fifo14; + wire[7:0] v_corr_20_fifo15; + wire[7:0] v_corr_20_fifo16; + wire[7:0] v_corr_20_fifo17; + wire[7:0] v_corr_20_fifo18; + wire[7:0] v_corr_20_fifo19; + wire[7:0] v_corr_20_fifo20; + wire[8:0] v_corr_10_fifo0; + wire[8:0] v_corr_10_fifo1; + wire[8:0] v_corr_10_fifo2; + wire[8:0] v_corr_10_fifo3; + wire[8:0] v_corr_10_fifo4; + wire[8:0] v_corr_10_fifo5; + wire[8:0] v_corr_10_fifo6; + wire[8:0] v_corr_10_fifo7; + wire[8:0] v_corr_10_fifo8; + wire[8:0] v_corr_10_fifo9; + wire[8:0] v_corr_10_fifo10; + wire[8:0] v_corr_10_fifo11; + wire[8:0] v_corr_10_fifo12; + wire[8:0] v_corr_10_fifo13; + wire[8:0] v_corr_10_fifo14; + wire[8:0] v_corr_10_fifo15; + wire[8:0] v_corr_10_fifo16; + wire[8:0] v_corr_10_fifo17; + wire[8:0] v_corr_10_fifo18; + wire[8:0] v_corr_10_fifo19; + wire[8:0] v_corr_10_fifo20; + wire[7:0] v_corr_20_fifo_x0; + wire[7:0] v_corr_20_fifo_x1; + wire[7:0] v_corr_20_fifo_x2; + wire[7:0] v_corr_20_fifo_x3; + wire[7:0] v_corr_20_fifo_x4; + wire[7:0] v_corr_20_fifo_x5; + wire[7:0] v_corr_20_fifo_x6; + wire[7:0] v_corr_20_fifo_x7; + wire[7:0] v_corr_20_fifo_x8; + wire[7:0] v_corr_20_fifo_x9; + wire[7:0] v_corr_20_fifo_x10; + wire[7:0] v_corr_20_fifo_x11; + wire[7:0] v_corr_20_fifo_x12; + wire[7:0] v_corr_20_fifo_x13; + wire[7:0] v_corr_20_fifo_x14; + wire[7:0] v_corr_20_fifo_x15; + wire[7:0] v_corr_20_fifo_x16; + wire[7:0] v_corr_20_fifo_x17; + wire[7:0] v_corr_20_fifo_x18; + wire[7:0] v_corr_20_fifo_x19; + wire[7:0] v_corr_20_fifo_x20; + wire[8:0] v_corr_10_fifo_x0; + wire[8:0] v_corr_10_fifo_x1; + wire[8:0] v_corr_10_fifo_x2; + wire[8:0] v_corr_10_fifo_x3; + wire[8:0] v_corr_10_fifo_x4; + wire[8:0] v_corr_10_fifo_x5; + wire[8:0] v_corr_10_fifo_x6; + wire[8:0] v_corr_10_fifo_x7; + wire[8:0] v_corr_10_fifo_x8; + wire[8:0] v_corr_10_fifo_x9; + wire[8:0] v_corr_10_fifo_x10; + wire[8:0] v_corr_10_fifo_x11; + wire[8:0] v_corr_10_fifo_x12; + wire[8:0] v_corr_10_fifo_x13; + wire[8:0] v_corr_10_fifo_x14; + wire[8:0] v_corr_10_fifo_x15; + wire[8:0] v_corr_10_fifo_x16; + wire[8:0] v_corr_10_fifo_x17; + wire[8:0] v_corr_10_fifo_x18; + wire[8:0] v_corr_10_fifo_x19; + wire[8:0] v_corr_10_fifo_x20; + wire[15:0] qs_4_out0; + wire[15:0] qs_4_out1; + wire[15:0] qs_4_out2; + wire[15:0] qs_4_out3; + wire[15:0] qs_4_out4; + wire[15:0] qs_4_out5; + wire[15:0] qs_4_out6; + wire[15:0] qs_4_out7; + wire[15:0] qs_4_out8; + wire[15:0] qs_4_out9; + wire[15:0] qs_4_out10; + wire[15:0] qs_4_out11; + wire[15:0] qs_4_out12; + wire[15:0] qs_4_out13; + wire[15:0] qs_4_out14; + wire[15:0] qs_4_out15; + wire[15:0] qs_4_out16; + wire[15:0] qs_4_out17; + wire[15:0] qs_4_out18; + wire[15:0] qs_4_out19; + wire[15:0] qs_4_out20; + wire[15:0] qs_2_out0; + wire[15:0] qs_2_out1; + wire[15:0] qs_2_out2; + wire[15:0] qs_2_out3; + wire[15:0] qs_2_out4; + wire[15:0] qs_2_out5; + wire[15:0] qs_2_out6; + wire[15:0] qs_2_out7; + wire[15:0] qs_2_out8; + wire[15:0] qs_2_out9; + wire[15:0] qs_2_out10; + wire[15:0] qs_2_out11; + wire[15:0] qs_2_out12; + wire[15:0] qs_2_out13; + wire[15:0] qs_2_out14; + wire[15:0] qs_2_out15; + wire[15:0] qs_2_out16; + wire[15:0] qs_2_out17; + wire[15:0] qs_2_out18; + wire[15:0] qs_2_out19; + wire[15:0] qs_2_out20; + wire[15:0] qs_4_out_x0; + wire[15:0] qs_4_out_x1; + wire[15:0] qs_4_out_x2; + wire[15:0] qs_4_out_x3; + wire[15:0] qs_4_out_x4; + wire[15:0] qs_4_out_x5; + wire[15:0] qs_4_out_x6; + wire[15:0] qs_4_out_x7; + wire[15:0] qs_4_out_x8; + wire[15:0] qs_4_out_x9; + wire[15:0] qs_4_out_x10; + wire[15:0] qs_4_out_x11; + wire[15:0] qs_4_out_x12; + wire[15:0] qs_4_out_x13; + wire[15:0] qs_4_out_x14; + wire[15:0] qs_4_out_x15; + wire[15:0] qs_4_out_x16; + wire[15:0] qs_4_out_x17; + wire[15:0] qs_4_out_x18; + wire[15:0] qs_4_out_x19; + wire[15:0] qs_4_out_x20; + wire[15:0] qs_2_out_x0; + wire[15:0] qs_2_out_x1; + wire[15:0] qs_2_out_x2; + wire[15:0] qs_2_out_x3; + wire[15:0] qs_2_out_x4; + wire[15:0] qs_2_out_x5; + wire[15:0] qs_2_out_x6; + wire[15:0] qs_2_out_x7; + wire[15:0] qs_2_out_x8; + wire[15:0] qs_2_out_x9; + wire[15:0] qs_2_out_x10; + wire[15:0] qs_2_out_x11; + wire[15:0] qs_2_out_x12; + wire[15:0] qs_2_out_x13; + wire[15:0] qs_2_out_x14; + wire[15:0] qs_2_out_x15; + wire[15:0] qs_2_out_x16; + wire[15:0] qs_2_out_x17; + wire[15:0] qs_2_out_x18; + wire[15:0] qs_2_out_x19; + wire[15:0] qs_2_out_x20; + wire rdy_4_out; + wire rdy_tmp3; + wire rdy_tmp2; + wire rdy_tmp1; + wire[7:0] max_data_out; + wire[4:0] max_indx_out; + wire v_nd_s1_left_2to0_tmp; + wire v_nd_s2_left_2to0_tmp; + wire v_nd_s4_left_2to0_tmp; + wire[7:0] v_d_reg_s1_left_2to0_tmp; + wire[7:0] v_d_reg_s2_left_2to0_tmp; + wire[7:0] v_d_reg_s4_left_2to0_tmp; + wire[7:0] v_d_reg_s1_left_2to0_fifo_tmp; + wire[7:0] v_d_reg_s2_left_2to0_fifo_tmp; + wire[7:0] v_d_reg_s4_left_2to0_fifo_tmp; + wire v_nd_s1_right_2to0_tmp; + wire v_nd_s2_right_2to0_tmp; + wire v_nd_s4_right_2to0_tmp; + wire[7:0] v_d_reg_s1_right_2to0_tmp; + wire[7:0] v_d_reg_s2_right_2to0_tmp; + wire[7:0] v_d_reg_s4_right_2to0_tmp; + wire[7:0] v_d_reg_s1_right_2to0_fifo_tmp; + wire[7:0] v_d_reg_s2_right_2to0_fifo_tmp; + wire[7:0] v_d_reg_s4_right_2to0_fifo_tmp; + wire[10:0] comb_out0; + wire[10:0] comb_out1; + wire[10:0] comb_out2; + wire[10:0] comb_out3; + wire[10:0] comb_out4; + wire[10:0] comb_out5; + wire[10:0] comb_out6; + wire[10:0] comb_out7; + wire[10:0] comb_out8; + wire[10:0] comb_out9; + wire[10:0] comb_out10; + wire[10:0] comb_out11; + wire[10:0] comb_out12; + wire[10:0] comb_out13; + wire[10:0] comb_out14; + wire[10:0] comb_out15; + wire[10:0] comb_out16; + wire[10:0] comb_out17; + wire[10:0] comb_out18; + wire[10:0] comb_out19; + wire[10:0] comb_out20; + // <> Unsupported Construct - attribute (source line 258) + // <> Unsupported Construct - attribute (source line 259)) + // <> Unsupported Construct - attribute (source line 273) + // <> Unsupported Construct - attribute (source line 274)) + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + scaler scaler_inst_left (tm3_clk_v0, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_addr_reg_2to0, v_nd_s1_left_2to0_tmp, v_nd_s2_left_2to0_tmp, v_nd_s4_left_2to0_tmp, v_d_reg_s1_left_2to0_tmp, v_d_reg_s2_left_2to0_tmp, v_d_reg_s4_left_2to0_tmp); + scaler scaler_inst_right (tm3_clk_v0, vidin_new_data_fifo, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_right_2to0_tmp, v_nd_s2_right_2to0_tmp, v_nd_s4_right_2to0_tmp, v_d_reg_s1_right_2to0_tmp, v_d_reg_s2_right_2to0_tmp, v_d_reg_s4_right_2to0_tmp); + v_fltr_496 v_fltr_496_l_inst(tm3_clk_v0, v_nd_s1_left_2to0_tmp, v_d_reg_s1_left_2to0_tmp, v_d_reg_s1_left_2to0_fifo_tmp); + v_fltr_496 v_fltr_496_r_inst(tm3_clk_v0, v_nd_s1_right_2to0_tmp, v_d_reg_s1_right_2to0_tmp, v_d_reg_s1_right_2to0_fifo_tmp); + v_fltr_316 v_fltr_316_l_inst(tm3_clk_v0, v_nd_s2_left_2to0_tmp, v_d_reg_s2_left_2to0_tmp, v_d_reg_s2_left_2to0_fifo_tmp); + v_fltr_316 v_fltr_316_r_inst(tm3_clk_v0, v_nd_s2_right_2to0_tmp, v_d_reg_s2_right_2to0_tmp, v_d_reg_s2_right_2to0_fifo_tmp); + port_bus_1to0_1 port_bus_1to0_1_inst(tm3_clk_v0, vidin_addr_reg, svid_comp_switch_2to3, vidin_new_data_scld_1_1to0, + v_corr_200, v_corr_201, v_corr_202, v_corr_203, v_corr_204, v_corr_205, v_corr_206, v_corr_207, v_corr_208, v_corr_209, v_corr_2010, v_corr_2011, v_corr_2012, v_corr_2013, v_corr_2014, v_corr_2015, v_corr_2016, v_corr_2017, v_corr_2018, v_corr_2019, v_corr_2020, + vidin_new_data_scld_2_1to0, + v_corr_100, v_corr_101, v_corr_102, v_corr_103, v_corr_104, v_corr_105, v_corr_106, v_corr_107, v_corr_108, v_corr_109, v_corr_1010, + vidin_new_data_scld_4_1to0, + v_corr_50, v_corr_51, v_corr_52, v_corr_53, v_corr_54, v_corr_55, + bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0); + + lp_fltr inst_fir_1_0 (tm3_clk_v0, v_corr_200, v_corr_20_fltr_h0, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_1 (tm3_clk_v0, v_corr_201, v_corr_20_fltr_h1, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_2 (tm3_clk_v0, v_corr_202, v_corr_20_fltr_h2, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_3 (tm3_clk_v0, v_corr_203, v_corr_20_fltr_h3, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_4 (tm3_clk_v0, v_corr_204, v_corr_20_fltr_h4, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_5 (tm3_clk_v0, v_corr_205, v_corr_20_fltr_h5, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_6 (tm3_clk_v0, v_corr_206, v_corr_20_fltr_h6, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_7 (tm3_clk_v0, v_corr_207, v_corr_20_fltr_h7, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_8 (tm3_clk_v0, v_corr_208, v_corr_20_fltr_h8, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_9 (tm3_clk_v0, v_corr_209, v_corr_20_fltr_h9, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_10 (tm3_clk_v0, v_corr_2010, v_corr_20_fltr_h10, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_11 (tm3_clk_v0, v_corr_2011, v_corr_20_fltr_h11, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_12 (tm3_clk_v0, v_corr_2012, v_corr_20_fltr_h12, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_13 (tm3_clk_v0, v_corr_2013, v_corr_20_fltr_h13, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_14 (tm3_clk_v0, v_corr_2014, v_corr_20_fltr_h14, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_15 (tm3_clk_v0, v_corr_2015, v_corr_20_fltr_h15, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_16 (tm3_clk_v0, v_corr_2016, v_corr_20_fltr_h16, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_17 (tm3_clk_v0, v_corr_2017, v_corr_20_fltr_h17, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_18 (tm3_clk_v0, v_corr_2018, v_corr_20_fltr_h18, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_19 (tm3_clk_v0, v_corr_2019, v_corr_20_fltr_h19, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_20 (tm3_clk_v0, v_corr_2020, v_corr_20_fltr_h20, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_2_0 (tm3_clk_v0, v_corr_100, v_corr_10_fltr_h0, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_1 (tm3_clk_v0, v_corr_101, v_corr_10_fltr_h1, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_2 (tm3_clk_v0, v_corr_102, v_corr_10_fltr_h2, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_3 (tm3_clk_v0, v_corr_103, v_corr_10_fltr_h3, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_4 (tm3_clk_v0, v_corr_104, v_corr_10_fltr_h4, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_5 (tm3_clk_v0, v_corr_105, v_corr_10_fltr_h5, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_6 (tm3_clk_v0, v_corr_106, v_corr_10_fltr_h6, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_7 (tm3_clk_v0, v_corr_107, v_corr_10_fltr_h7, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_8 (tm3_clk_v0, v_corr_108, v_corr_10_fltr_h8, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_9 (tm3_clk_v0, v_corr_109, v_corr_10_fltr_h9, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_10 (tm3_clk_v0, v_corr_1010, v_corr_10_fltr_h10, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_4_0 (tm3_clk_v0, v_corr_50, v_corr_5_fltr_h0, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_1 (tm3_clk_v0, v_corr_51, v_corr_5_fltr_h1, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_2 (tm3_clk_v0, v_corr_52, v_corr_5_fltr_h2, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_3 (tm3_clk_v0, v_corr_53, v_corr_5_fltr_h3, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_4 (tm3_clk_v0, v_corr_54, v_corr_5_fltr_h4, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_5 (tm3_clk_v0, v_corr_55, v_corr_5_fltr_h5, vidin_new_data_scld_4_1to0); + lp_fltr_v1 inst_fir_v1_0 (tm3_clk_v0, v_corr_20_fltr_h0, v_corr_20_fltr_x0, v_corr_20_fltr0, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_1 (tm3_clk_v0, v_corr_20_fltr_h1, v_corr_20_fltr_x1, v_corr_20_fltr1, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_2 (tm3_clk_v0, v_corr_20_fltr_h2, v_corr_20_fltr_x2, v_corr_20_fltr2, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_3 (tm3_clk_v0, v_corr_20_fltr_h3, v_corr_20_fltr_x3, v_corr_20_fltr3, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_4 (tm3_clk_v0, v_corr_20_fltr_h4, v_corr_20_fltr_x4, v_corr_20_fltr4, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_5 (tm3_clk_v0, v_corr_20_fltr_h5, v_corr_20_fltr_x5, v_corr_20_fltr5, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_6 (tm3_clk_v0, v_corr_20_fltr_h6, v_corr_20_fltr_x6, v_corr_20_fltr6, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_7 (tm3_clk_v0, v_corr_20_fltr_h7, v_corr_20_fltr_x7, v_corr_20_fltr7, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_8 (tm3_clk_v0, v_corr_20_fltr_h8, v_corr_20_fltr_x8, v_corr_20_fltr8, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_9 (tm3_clk_v0, v_corr_20_fltr_h9, v_corr_20_fltr_x9, v_corr_20_fltr9, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_10 (tm3_clk_v0, v_corr_20_fltr_h10, v_corr_20_fltr_x10, v_corr_20_fltr10, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_11 (tm3_clk_v0, v_corr_20_fltr_h11, v_corr_20_fltr_x11, v_corr_20_fltr11, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_12 (tm3_clk_v0, v_corr_20_fltr_h12, v_corr_20_fltr_x12, v_corr_20_fltr12, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_13 (tm3_clk_v0, v_corr_20_fltr_h13, v_corr_20_fltr_x13, v_corr_20_fltr13, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_14 (tm3_clk_v0, v_corr_20_fltr_h14, v_corr_20_fltr_x14, v_corr_20_fltr14, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_15 (tm3_clk_v0, v_corr_20_fltr_h15, v_corr_20_fltr_x15, v_corr_20_fltr15, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_16 (tm3_clk_v0, v_corr_20_fltr_h16, v_corr_20_fltr_x16, v_corr_20_fltr16, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_17 (tm3_clk_v0, v_corr_20_fltr_h17, v_corr_20_fltr_x17, v_corr_20_fltr17, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_18 (tm3_clk_v0, v_corr_20_fltr_h18, v_corr_20_fltr_x18, v_corr_20_fltr18, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_19 (tm3_clk_v0, v_corr_20_fltr_h19, v_corr_20_fltr_x19, v_corr_20_fltr19, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_20 (tm3_clk_v0, v_corr_20_fltr_h20, v_corr_20_fltr_x20, v_corr_20_fltr20, vidin_new_data_scld_1_1to0); + lp_fltr_v2 inst_fir_v2_0 (tm3_clk_v0, v_corr_10_fltr_h0, v_corr_10_fltr_x0, v_corr_10_fltr0, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_1 (tm3_clk_v0, v_corr_10_fltr_h1, v_corr_10_fltr_x1, v_corr_10_fltr1, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_2 (tm3_clk_v0, v_corr_10_fltr_h2, v_corr_10_fltr_x2, v_corr_10_fltr2, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_3 (tm3_clk_v0, v_corr_10_fltr_h3, v_corr_10_fltr_x3, v_corr_10_fltr3, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_4 (tm3_clk_v0, v_corr_10_fltr_h4, v_corr_10_fltr_x4, v_corr_10_fltr4, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_5 (tm3_clk_v0, v_corr_10_fltr_h5, v_corr_10_fltr_x5, v_corr_10_fltr5, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_6 (tm3_clk_v0, v_corr_10_fltr_h6, v_corr_10_fltr_x6, v_corr_10_fltr6, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_7 (tm3_clk_v0, v_corr_10_fltr_h7, v_corr_10_fltr_x7, v_corr_10_fltr7, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_8 (tm3_clk_v0, v_corr_10_fltr_h8, v_corr_10_fltr_x8, v_corr_10_fltr8, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_9 (tm3_clk_v0, v_corr_10_fltr_h9, v_corr_10_fltr_x9, v_corr_10_fltr9, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_10 (tm3_clk_v0, v_corr_10_fltr_h10, v_corr_10_fltr_x10, v_corr_10_fltr10, vidin_new_data_scld_2_1to0); + lp_fltr_v4 inst_fir_v4_0 (tm3_clk_v0, v_corr_5_fltr_h0, v_corr_5_fltr_x0, v_corr_5_fltr0, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_1 (tm3_clk_v0, v_corr_5_fltr_h1, v_corr_5_fltr_x1, v_corr_5_fltr1, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_2 (tm3_clk_v0, v_corr_5_fltr_h2, v_corr_5_fltr_x2, v_corr_5_fltr2, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_3 (tm3_clk_v0, v_corr_5_fltr_h3, v_corr_5_fltr_x3, v_corr_5_fltr3, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_4 (tm3_clk_v0, v_corr_5_fltr_h4, v_corr_5_fltr_x4, v_corr_5_fltr4, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_5 (tm3_clk_v0, v_corr_5_fltr_h5, v_corr_5_fltr_x5, v_corr_5_fltr5, vidin_new_data_scld_4_1to0); + + wrapper_qs_intr_5_20 wrapper_qs_intr_inst_5 (tm3_clk_v0, + v_corr_5_fltr0, + v_corr_5_fltr1, + v_corr_5_fltr2, + v_corr_5_fltr3, + v_corr_5_fltr4, + v_corr_5_fltr5, + vidin_new_data_scld_4_1to0, vidin_addr_reg, + qs_4_out0, + qs_4_out1, + qs_4_out2, + qs_4_out3, + qs_4_out4, + qs_4_out5, + qs_4_out6, + qs_4_out7, + qs_4_out8, + qs_4_out9, + qs_4_out10, + qs_4_out11, + qs_4_out12, + qs_4_out13, + qs_4_out14, + qs_4_out15, + qs_4_out16, + qs_4_out17, + qs_4_out18, + qs_4_out19, + qs_4_out20, + rdy_4_out); + wrapper_qs_intr_10_20 wrapper_qs_intr_inst_10 (tm3_clk_v0, + v_corr_10_fltr0, + v_corr_10_fltr1, + v_corr_10_fltr2, + v_corr_10_fltr3, + v_corr_10_fltr4, + v_corr_10_fltr5, + v_corr_10_fltr6, + v_corr_10_fltr7, + v_corr_10_fltr8, + v_corr_10_fltr9, + v_corr_10_fltr10, + vidin_new_data_scld_2_1to0, vidin_addr_reg, + qs_2_out0, + qs_2_out1, + qs_2_out2, + qs_2_out3, + qs_2_out4, + qs_2_out5, + qs_2_out6, + qs_2_out7, + qs_2_out8, + qs_2_out9, + qs_2_out10, + qs_2_out11, + qs_2_out12, + qs_2_out13, + qs_2_out14, + qs_2_out15, + qs_2_out16, + qs_2_out17, + qs_2_out18, + qs_2_out19, + qs_2_out20, + rdy_tmp3); + wrapper_qs_intr_5_20 wrapper_qs_intr_inst_5_more (tm3_clk_v0, + v_corr_5_fltr_x0, + v_corr_5_fltr_x1, + v_corr_5_fltr_x2, + v_corr_5_fltr_x3, + v_corr_5_fltr_x4, + v_corr_5_fltr_x5, + vidin_new_data_scld_4_1to0, vidin_addr_reg, + qs_4_out_x0, + qs_4_out_x1, + qs_4_out_x2, + qs_4_out_x3, + qs_4_out_x4, + qs_4_out_x5, + qs_4_out_x6, + qs_4_out_x7, + qs_4_out_x8, + qs_4_out_x9, + qs_4_out_x10, + qs_4_out_x11, + qs_4_out_x12, + qs_4_out_x13, + qs_4_out_x14, + qs_4_out_x15, + qs_4_out_x16, + qs_4_out_x17, + qs_4_out_x18, + qs_4_out_x19, + qs_4_out_x20, + rdy_tmp2); + wrapper_qs_intr_10_20 wrapper_qs_intr_inst_10_more (tm3_clk_v0, + v_corr_10_fltr_x0, + v_corr_10_fltr_x1, + v_corr_10_fltr_x2, + v_corr_10_fltr_x3, + v_corr_10_fltr_x4, + v_corr_10_fltr_x5, + v_corr_10_fltr_x6, + v_corr_10_fltr_x7, + v_corr_10_fltr_x8, + v_corr_10_fltr_x9, + v_corr_10_fltr_x10, + vidin_new_data_scld_2_1to0, vidin_addr_reg, + qs_2_out_x0, + qs_2_out_x1, + qs_2_out_x2, + qs_2_out_x3, + qs_2_out_x4, + qs_2_out_x5, + qs_2_out_x6, + qs_2_out_x7, + qs_2_out_x8, + qs_2_out_x9, + qs_2_out_x10, + qs_2_out_x11, + qs_2_out_x12, + qs_2_out_x13, + qs_2_out_x14, + qs_2_out_x15, + qs_2_out_x16, + qs_2_out_x17, + qs_2_out_x18, + qs_2_out_x19, + qs_2_out_x20, + rdy_tmp1); + + my_fifo_1 ints_fifo_1_gen_1_0 (tm3_clk_v0, v_corr_20_fltr0, v_corr_20_fifo0, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_1 (tm3_clk_v0, v_corr_20_fltr1, v_corr_20_fifo1, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_2 (tm3_clk_v0, v_corr_20_fltr2, v_corr_20_fifo2, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_3 (tm3_clk_v0, v_corr_20_fltr3, v_corr_20_fifo3, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_4 (tm3_clk_v0, v_corr_20_fltr4, v_corr_20_fifo4, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_5 (tm3_clk_v0, v_corr_20_fltr5, v_corr_20_fifo5, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_6 (tm3_clk_v0, v_corr_20_fltr6, v_corr_20_fifo6, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_7 (tm3_clk_v0, v_corr_20_fltr7, v_corr_20_fifo7, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_8 (tm3_clk_v0, v_corr_20_fltr8, v_corr_20_fifo8, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_9 (tm3_clk_v0, v_corr_20_fltr9, v_corr_20_fifo9, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_10 (tm3_clk_v0, v_corr_20_fltr10, v_corr_20_fifo10, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_11 (tm3_clk_v0, v_corr_20_fltr11, v_corr_20_fifo11, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_12 (tm3_clk_v0, v_corr_20_fltr12, v_corr_20_fifo12, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_13 (tm3_clk_v0, v_corr_20_fltr13, v_corr_20_fifo13, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_14 (tm3_clk_v0, v_corr_20_fltr14, v_corr_20_fifo14, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_15 (tm3_clk_v0, v_corr_20_fltr15, v_corr_20_fifo15, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_16 (tm3_clk_v0, v_corr_20_fltr16, v_corr_20_fifo16, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_17 (tm3_clk_v0, v_corr_20_fltr17, v_corr_20_fifo17, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_18 (tm3_clk_v0, v_corr_20_fltr18, v_corr_20_fifo18, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_19 (tm3_clk_v0, v_corr_20_fltr19, v_corr_20_fifo19, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_20 (tm3_clk_v0, v_corr_20_fltr20, v_corr_20_fifo20, rdy_4_out); + // <> Can't find translated component 'my_fifo_2'. Module name may not match + my_fifo_2 ints_fifo_2_gen_1_0 (tm3_clk_v0, qs_2_out0[8:0], v_corr_10_fifo0, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_1 (tm3_clk_v0, qs_2_out1[8:0], v_corr_10_fifo1, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_2 (tm3_clk_v0, qs_2_out2[8:0], v_corr_10_fifo2, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_3 (tm3_clk_v0, qs_2_out3[8:0], v_corr_10_fifo3, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_4 (tm3_clk_v0, qs_2_out4[8:0], v_corr_10_fifo4, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_5 (tm3_clk_v0, qs_2_out5[8:0], v_corr_10_fifo5, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_6 (tm3_clk_v0, qs_2_out6[8:0], v_corr_10_fifo6, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_7 (tm3_clk_v0, qs_2_out7[8:0], v_corr_10_fifo7, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_8 (tm3_clk_v0, qs_2_out8[8:0], v_corr_10_fifo8, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_9 (tm3_clk_v0, qs_2_out9[8:0], v_corr_10_fifo9, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_10 (tm3_clk_v0, qs_2_out10[8:0], v_corr_10_fifo10, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_11 (tm3_clk_v0, qs_2_out11[8:0], v_corr_10_fifo11, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_12 (tm3_clk_v0, qs_2_out12[8:0], v_corr_10_fifo12, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_13 (tm3_clk_v0, qs_2_out13[8:0], v_corr_10_fifo13, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_14 (tm3_clk_v0, qs_2_out14[8:0], v_corr_10_fifo14, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_15 (tm3_clk_v0, qs_2_out15[8:0], v_corr_10_fifo15, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_16 (tm3_clk_v0, qs_2_out16[8:0], v_corr_10_fifo16, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_17 (tm3_clk_v0, qs_2_out17[8:0], v_corr_10_fifo17, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_18 (tm3_clk_v0, qs_2_out18[8:0], v_corr_10_fifo18, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_19 (tm3_clk_v0, qs_2_out19[8:0], v_corr_10_fifo19, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_20 (tm3_clk_v0, qs_2_out20[8:0], v_corr_10_fifo20, rdy_4_out); + combine_res combine_res_inst_0 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo0, v_corr_10_fifo0, qs_4_out0[8:0], comb_out0); + combine_res combine_res_inst_1 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo1, v_corr_10_fifo1, qs_4_out0[8:0], comb_out1); + combine_res combine_res_inst_2 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo2, v_corr_10_fifo2, qs_4_out0[8:0], comb_out2); + combine_res combine_res_inst_3 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo3, v_corr_10_fifo3, qs_4_out0[8:0], comb_out3); + combine_res combine_res_inst_4 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo4, v_corr_10_fifo4, qs_4_out0[8:0], comb_out4); + combine_res combine_res_inst_5 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo5, v_corr_10_fifo5, qs_4_out0[8:0], comb_out5); + combine_res combine_res_inst_6 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo6, v_corr_10_fifo6, qs_4_out0[8:0], comb_out6); + combine_res combine_res_inst_7 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo7, v_corr_10_fifo7, qs_4_out0[8:0], comb_out7); + combine_res combine_res_inst_8 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo8, v_corr_10_fifo8, qs_4_out0[8:0], comb_out8); + combine_res combine_res_inst_9 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo9, v_corr_10_fifo9, qs_4_out0[8:0], comb_out9); + combine_res combine_res_inst_10 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo10, v_corr_10_fifo10, qs_4_out0[8:0], comb_out10); + combine_res combine_res_inst_11 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo11, v_corr_10_fifo11, qs_4_out0[8:0], comb_out11); + combine_res combine_res_inst_12 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo12, v_corr_10_fifo12, qs_4_out0[8:0], comb_out12); + combine_res combine_res_inst_13 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo13, v_corr_10_fifo13, qs_4_out0[8:0], comb_out13); + combine_res combine_res_inst_14 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo14, v_corr_10_fifo14, qs_4_out0[8:0], comb_out14); + combine_res combine_res_inst_15 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo15, v_corr_10_fifo15, qs_4_out0[8:0], comb_out15); + combine_res combine_res_inst_16 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo16, v_corr_10_fifo16, qs_4_out0[8:0], comb_out16); + combine_res combine_res_inst_17 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo17, v_corr_10_fifo17, qs_4_out0[8:0], comb_out17); + combine_res combine_res_inst_18 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo18, v_corr_10_fifo18, qs_4_out0[8:0], comb_out18); + combine_res combine_res_inst_19 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo19, v_corr_10_fifo19, qs_4_out0[8:0], comb_out19); + combine_res combine_res_inst_20 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo20, v_corr_10_fifo20, qs_4_out0[8:0], comb_out20); + find_max find_max_inst (tm3_clk_v0, rdy_4_out, comb_out0, comb_out1, comb_out2, comb_out3, comb_out4, comb_out5, comb_out6, comb_out7, comb_out8, comb_out9, comb_out10, comb_out11, comb_out12, comb_out13, comb_out14, comb_out15, comb_out16, comb_out17, comb_out18, comb_out19, comb_out20, max_data_out, max_indx_out); + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1_2to3_left_reg <= rdy_4_out ; + vidin_new_data_scld_2_2to3_left_reg <= rdy_4_out ; + vidin_new_data_scld_4_2to3_left_reg <= rdy_4_out ; + vidin_data_reg_scld_1_2to3_left_reg <= v_corr_20_fifo0 ; + + vidin_data_reg_scld_1_2to3_right_reg <= v_corr_10_fifo0[8:1] ; + vidin_data_reg_scld_2_2to3_left_reg <= qs_4_out0[8:1] ; + vidin_data_reg_scld_2_2to3_right_reg <= comb_out0[8:1] ; + vidin_data_reg_scld_4_2to3_left_reg <= comb_out4[8:1] ; + vidin_data_reg_scld_4_2to3_right_reg <= {max_indx_out, 3'b000} ; + if (vidin_addr_reg[8:0] >= 9'b001001000) + begin + vidin_addr_reg_2to3_reg <= vidin_addr_reg - 19'b0000000000001001000 ; + end + else + begin + vidin_addr_reg_2to3_reg <= vidin_addr_reg + 19'b0000000000100100000 ; + end + end + + always @(posedge tm3_clk_v0) + begin + v_nd_s1_left_2to0 <= v_nd_s1_left_2to0_tmp ; + v_nd_s2_left_2to0 <= v_nd_s2_left_2to0_tmp ; + v_nd_s4_left_2to0 <= v_nd_s4_left_2to0_tmp ; + v_nd_s1_right_2to0 <= v_nd_s1_right_2to0_tmp ; + v_nd_s2_right_2to0 <= v_nd_s2_right_2to0_tmp ; + v_nd_s4_right_2to0 <= v_nd_s4_right_2to0_tmp ; + if (v_nd_s1_left_2to0_tmp == 1'b1) + begin + v_d_reg_s1_left_2to0 <= v_d_reg_s1_left_2to0_fifo_tmp ; + v_d_reg_s1_right_2to0 <= v_d_reg_s1_right_2to0_fifo_tmp ; + end + if (v_nd_s2_left_2to0_tmp == 1'b1) + begin + v_d_reg_s2_left_2to0 <= v_d_reg_s2_left_2to0_fifo_tmp ; + v_d_reg_s2_right_2to0 <= v_d_reg_s2_right_2to0_fifo_tmp ; + end + if (v_nd_s4_left_2to0_tmp == 1'b1) + begin + v_d_reg_s4_left_2to0 <= v_d_reg_s4_left_2to0_tmp ; + v_d_reg_s4_right_2to0 <= v_d_reg_s4_right_2to0_tmp ; + end + end + assign tm3_vidout_clock = ~(video_state) ; + + always @(posedge tm3_clk_v0) + begin + x_reg_l <= x_in ; + y_reg_up <= y_in ; + x_reg_r <= x_in + 8 ; + y_reg_dn <= y_in + 8 ; + depth_out <= {8'b00000000, depth_out_reg} ; + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + if ((vert >= 491) & (vert <= 493)) + begin + tm3_vidout_vsync <= 1'b1 ; + end + else + begin + tm3_vidout_vsync <= 1'b0 ; + end + if ((horiz >= 664) & (horiz <= 760)) + begin + tm3_vidout_hsync <= 1'b1 ; + end + else + begin + tm3_vidout_hsync <= 1'b0 ; + end + if ((horiz < 640) & (vert < 480)) + begin + tm3_vidout_blank <= 1'b1 ; + end + else + begin + tm3_vidout_blank <= 1'b0 ; + end + tm3_sram_adsp <= 1'b1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_data_xhdl0 <= 0; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[15:8] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[15:8], 2'b00} ; + tm3_vidout_green <= {vidout_buf[15:8], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[15:8], 2'b00} ; + end + end + 3'b001 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[23:16] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[23:16], 2'b00} ; + tm3_vidout_green <= {vidout_buf[23:16], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[23:16], 2'b00} ; + end + end + 3'b010 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[31:24] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[31:24], 2'b00} ; + tm3_vidout_green <= {vidout_buf[31:24], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[31:24], 2'b00} ; + end + end + 3'b011 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[39:32] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[39:32], 2'b00} ; + tm3_vidout_green <= {vidout_buf[39:32], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[39:32], 2'b00} ; + end + end + 3'b100 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[47:40] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[47:40], 2'b00} ; + tm3_vidout_green <= {vidout_buf[47:40], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[47:40], 2'b00} ; + end + end + 3'b101 : + begin + tm3_sram_oe <= 2'b10 ; + + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[55:48] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[55:48], 2'b00} ; + tm3_vidout_green <= {vidout_buf[55:48], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[55:48], 2'b00} ; + end + end + 3'b110 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[63:56] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[63:56], 2'b00} ; + tm3_vidout_green <= {vidout_buf[63:56], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[63:56], 2'b00} ; + end + end + 3'b111 : + begin + tm3_sram_oe <= 2'b11 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[7:0] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[7:0], 2'b00} ; + tm3_vidout_green <= {vidout_buf[7:0], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[7:0], 2'b00} ; + end + end + endcase + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_2 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_2 ; + end + 3'b100 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_4 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_4 ; + + end + 3'b110 : + begin + tm3_sram_addr <= {5'b00101, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b111 : + begin + vidout_buf <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + default : + begin + tm3_sram_addr <= 19'b0000000000000000000 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0 ; + end + endcase + end + if (vidin_new_data_scld_1_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[2:0]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_left_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_left_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_left_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_2 <= {4'b0001, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_4 <= {4'b0010, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_right_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_right_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_right_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_2 <= {4'b0001, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_4 <= {4'b0010, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + endcase + end + end +endmodule +module combine_res (clk, wen, din_1, din_2, din_3, dout); + + input clk; + input wen; + input[7:0] din_1; + input[8:0] din_2; + input[8:0] din_3; + output[10:0] dout; + reg[10:0] dout; + reg[8:0] din_1_reg; + reg[8:0] din_2_reg; + reg[8:0] din_3_reg; + reg[10:0] add_tmp; + reg[10:0] dout_reg; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + din_1_reg <= {din_1[7], din_1} ; + din_2_reg <= din_2 ; + din_3_reg <= din_3 ; + dout <= dout_reg ; + end + add_tmp <= ({din_1_reg[8], din_1_reg[8], din_1_reg}) + ({din_2_reg[8], din_2_reg[8], din_2_reg}) ; + dout_reg <= add_tmp + ({din_3_reg[8], din_3_reg[8], din_3_reg}) ; + end + endmodule +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_496 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out); + + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[7:0] vidin_out; + wire[7:0] vidin_out; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + wire[7:0] buff_out8; + wire[7:0] buff_out9; + wire[7:0] buff_out10; + wire[7:0] buff_out11; + + assign buff_out0 = vidin_in ; + + my_fifo_496 fifo0(tm3_clk_v0, buff_out0, buff_out1, vidin_new_data); + my_fifo_496 fifo1(tm3_clk_v0, buff_out1, buff_out2, vidin_new_data); + my_fifo_496 fifo2(tm3_clk_v0, buff_out2, buff_out3, vidin_new_data); + my_fifo_496 fifo3(tm3_clk_v0, buff_out3, buff_out4, vidin_new_data); + my_fifo_496 fifo4(tm3_clk_v0, buff_out4, buff_out5, vidin_new_data); + my_fifo_496 fifo5(tm3_clk_v0, buff_out5, buff_out6, vidin_new_data); + my_fifo_496 fifo6(tm3_clk_v0, buff_out6, buff_out7, vidin_new_data); + my_fifo_496 fifo7(tm3_clk_v0, buff_out7, buff_out8, vidin_new_data); + my_fifo_496 fifo8(tm3_clk_v0, buff_out8, buff_out9, vidin_new_data); + my_fifo_496 fifo9(tm3_clk_v0, buff_out9, buff_out10, vidin_new_data); + my_fifo_496 fifo10(tm3_clk_v0, buff_out10, buff_out11, vidin_new_data); + + my_fifo_496 more_inst (tm3_clk_v0, buff_out11, vidin_out, vidin_new_data); +endmodule +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_316 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out); + + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[7:0] vidin_out; + wire[7:0] vidin_out; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + + assign buff_out0 = vidin_in ; + + my_fifo_316 fifo0(tm3_clk_v0, buff_out0, buff_out1, vidin_new_data); + my_fifo_316 fifo1(tm3_clk_v0, buff_out1, buff_out2, vidin_new_data); + my_fifo_316 fifo2(tm3_clk_v0, buff_out2, buff_out3, vidin_new_data); + + my_fifo_316 more_inst (tm3_clk_v0, buff_out3, vidin_out, vidin_new_data); +endmodule + +module lp_fltr_v1 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + + my_fifo_359 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_359 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + + + + + +module lp_fltr_v2 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + // <> Unsupported Construct - attribute (source line 31) + // <> Unsupported Construct - attribute (source line 32)) + + my_fifo_179 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_179 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + +module lp_fltr_v4 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + + my_fifo_89 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_89 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + +module scaler ( + tm3_clk_v0, + vidin_new_data, + vidin_rgb_reg, + vidin_addr_reg, + vidin_new_data_scld_1, + vidin_new_data_scld_2, + vidin_new_data_scld_4, + vidin_gray_scld_1, + vidin_gray_scld_2, + vidin_gray_scld_4 +); + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_rgb_reg; + input[3:0] vidin_addr_reg; + output vidin_new_data_scld_1; + reg vidin_new_data_scld_1; + output vidin_new_data_scld_2; + reg vidin_new_data_scld_2; + output vidin_new_data_scld_4; + reg vidin_new_data_scld_4; + output[7:0] vidin_gray_scld_1; + reg[7:0] vidin_gray_scld_1; + output[7:0] vidin_gray_scld_2; + reg[7:0] vidin_gray_scld_2; + output[7:0] vidin_gray_scld_4; + reg[7:0] vidin_gray_scld_4; + + wire[7:0] v_fltr_sc_1; + wire[7:0] v_fltr_sc_2; + wire[7:0] v_fltr_sc_4; + wire[7:0] h_fltr_sc_1; + wire[7:0] h_fltr_sc_2; + wire[7:0] h_fltr_sc_4; + + scl_v_fltr scl_v_fltr_inst (tm3_clk_v0, vidin_new_data, vidin_rgb_reg, v_fltr_sc_1, v_fltr_sc_2, v_fltr_sc_4); + scl_h_fltr scl_h_fltr_inst (tm3_clk_v0, vidin_new_data, v_fltr_sc_1, v_fltr_sc_2, v_fltr_sc_4, h_fltr_sc_1, h_fltr_sc_2, h_fltr_sc_4); + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1 <= vidin_new_data ; + if (vidin_new_data == 1'b1) + begin + vidin_gray_scld_1 <= h_fltr_sc_1 ; + if ((vidin_addr_reg[0]) == 1'b0 & (vidin_addr_reg[2]) == 1'b0) + begin + vidin_gray_scld_2 <= h_fltr_sc_2 ; + vidin_new_data_scld_2 <= 1'b1 ; + if ((vidin_addr_reg[1]) == 1'b0 & (vidin_addr_reg[3]) == 1'b0) + begin + vidin_gray_scld_4 <= h_fltr_sc_4 ; + vidin_new_data_scld_4 <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_2 <= 1'b0; + vidin_new_data_scld_4 <= 1'b0; + end + end + else + begin + vidin_new_data_scld_2 <= 1'b0; + vidin_new_data_scld_4 <= 1'b0 ; + end + end +endmodule + + + + +module scl_v_fltr (clk, nd, d_in, d_out_1, d_out_2, d_out_4); + + // <> : Warning - included file work/basic_type does not exist - this may affect translation + + input clk; + input nd; + input[7:0] d_in; + output[7:0] d_out_1; + reg[7:0] d_out_1; + output[7:0] d_out_2; + reg[7:0] d_out_2; + output[7:0] d_out_4; + reg[7:0] d_out_4; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + reg[7:0] buff_out_reg0; + reg[7:0] buff_out_reg1; + reg[7:0] buff_out_reg2; + reg[7:0] buff_out_reg3; + reg[7:0] buff_out_reg4; + reg[7:0] buff_out_reg5; + reg[7:0] buff_out_reg6; + reg[7:0] buff_out_reg7; + reg[9:0] add_2_tmp_1; + reg[9:0] add_2_tmp_2; + reg[9:0] add_2_tmp; + reg[11:0] add_4_tmp_1; + reg[11:0] add_4_tmp_2; + reg[11:0] add_4_tmp_3; + reg[11:0] add_4_tmp_4; + reg[11:0] add_4_tmp_5; + reg[11:0] add_4_tmp_6; + reg[11:0] add_4_tmp_7; + reg[11:0] add_4_tmp_8; + reg[11:0] add_4_tmp; + // <> Unsupported Construct - attribute (source line 33) + // <> Unsupported Construct - attribute (source line 34)) + + assign buff_out0 = d_in ; + + my_fifo_496 ints_fifo_gen_0 (clk, buff_out0, buff_out1, nd); + my_fifo_496 ints_fifo_gen_1 (clk, buff_out1, buff_out2, nd); + my_fifo_496 ints_fifo_gen_2 (clk, buff_out2, buff_out3, nd); + my_fifo_496 ints_fifo_gen_3 (clk, buff_out3, buff_out4, nd); + my_fifo_496 ints_fifo_gen_4 (clk, buff_out4, buff_out5, nd); + my_fifo_496 ints_fifo_gen_5 (clk, buff_out5, buff_out6, nd); + my_fifo_496 ints_fifo_gen_6 (clk, buff_out6, buff_out7, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + buff_out_reg1 <= buff_out1 ; + buff_out_reg2 <= buff_out2 ; + buff_out_reg3 <= buff_out3 ; + buff_out_reg4 <= buff_out4 ; + buff_out_reg5 <= buff_out5 ; + buff_out_reg6 <= buff_out6 ; + buff_out_reg7 <= buff_out7 ; + d_out_1 <= buff_out_reg1 ; + d_out_2 <= add_2_tmp[9:2] ; + d_out_4 <= add_4_tmp[11:4] ; + end + add_2_tmp_1 <= ({2'b00, buff_out_reg1}) + ({2'b00, buff_out_reg3}) ; + add_2_tmp_2 <= {1'b0, buff_out_reg2, 1'b0} ; + add_2_tmp <= add_2_tmp_1 + add_2_tmp_2 ; + add_4_tmp_1 <= ({4'b0000, buff_out_reg1}) + ({4'b0000, buff_out_reg7}) ; + add_4_tmp_2 <= ({3'b000, buff_out_reg2, 1'b0}) + ({3'b000, buff_out_reg6, 1'b0}) ; + add_4_tmp_3 <= ({3'b000, buff_out_reg3, 1'b0}) + ({3'b000, buff_out_reg5, 1'b0}) ; + add_4_tmp_4 <= ({4'b0000, buff_out_reg3}) + ({4'b0000, buff_out_reg5}) ; + add_4_tmp_5 <= ({2'b00, buff_out_reg4, 2'b00}) ; + add_4_tmp_6 <= add_4_tmp_1 + add_4_tmp_2 ; + add_4_tmp_7 <= add_4_tmp_3 + add_4_tmp_4 ; + add_4_tmp_8 <= add_4_tmp_5 + add_4_tmp_6 ; + add_4_tmp <= add_4_tmp_7 + add_4_tmp_8 ; + end +endmodule +module scl_h_fltr (clk, nd, d_in_1, d_in_2, d_in_4, d_out_1, d_out_2, d_out_4); + + input clk; + input nd; + input[7:0] d_in_1; + input[7:0] d_in_2; + input[7:0] d_in_4; + output[7:0] d_out_1; + reg[7:0] d_out_1; + output[7:0] d_out_2; + reg[7:0] d_out_2; + output[7:0] d_out_4; + reg[7:0] d_out_4; + + wire[7:0] buff_out_20; + wire[7:0] buff_out_21; + wire[7:0] buff_out_22; + wire[7:0] buff_out_23; + reg[7:0] buff_out_reg_21; + reg[7:0] buff_out_reg_22; + reg[7:0] buff_out_reg_23; + wire[7:0] buff_out_40; + wire[7:0] buff_out_41; + wire[7:0] buff_out_42; + wire[7:0] buff_out_43; + wire[7:0] buff_out_44; + wire[7:0] buff_out_45; + wire[7:0] buff_out_46; + wire[7:0] buff_out_47; + reg[7:0] buff_out_reg_41; + reg[7:0] buff_out_reg_42; + reg[7:0] buff_out_reg_43; + reg[7:0] buff_out_reg_44; + reg[7:0] buff_out_reg_45; + reg[7:0] buff_out_reg_46; + reg[7:0] buff_out_reg_47; + reg[9:0] add_2_tmp_1; + reg[9:0] add_2_tmp_2; + reg[9:0] add_2_tmp; + reg[11:0] add_4_tmp_1; + reg[11:0] add_4_tmp_2; + reg[11:0] add_4_tmp_3; + reg[11:0] add_4_tmp_4; + reg[11:0] add_4_tmp_5; + reg[11:0] add_4_tmp_6; + reg[11:0] add_4_tmp_7; + reg[11:0] add_4_tmp_8; + reg[11:0] add_4_tmp; + + assign buff_out_20 = d_in_2 ; + assign buff_out_40 = d_in_4 ; + + sh_reg_1 ints_sh_reg_2_0(clk, nd, buff_out_20, buff_out_21); + sh_reg_1 ints_sh_reg_2_1(clk, nd, buff_out_21, buff_out_22); + sh_reg_1 ints_sh_reg_2_2(clk, nd, buff_out_22, buff_out_23); + sh_reg_1 ints_sh_reg_4_0(clk, nd, buff_out_40, buff_out_41); + sh_reg_1 ints_sh_reg_4_1(clk, nd, buff_out_41, buff_out_42); + sh_reg_1 ints_sh_reg_4_2(clk, nd, buff_out_42, buff_out_43); + sh_reg_1 ints_sh_reg_4_3(clk, nd, buff_out_43, buff_out_44); + sh_reg_1 ints_sh_reg_4_4(clk, nd, buff_out_44, buff_out_45); + sh_reg_1 ints_sh_reg_4_5(clk, nd, buff_out_45, buff_out_46); + sh_reg_1 ints_sh_reg_4_6(clk, nd, buff_out_46, buff_out_47); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + buff_out_reg_41 <= buff_out_41 ; + buff_out_reg_42 <= buff_out_42 ; + buff_out_reg_43 <= buff_out_43 ; + buff_out_reg_44 <= buff_out_44 ; + buff_out_reg_45 <= buff_out_45 ; + buff_out_reg_46 <= buff_out_46 ; + buff_out_reg_47 <= buff_out_47 ; + buff_out_reg_21 <= buff_out_21 ; + buff_out_reg_22 <= buff_out_22 ; + buff_out_reg_23 <= buff_out_23 ; + d_out_1 <= d_in_1 ; + d_out_2 <= add_2_tmp[9:2] ; + d_out_4 <= add_4_tmp[11:4] ; + end + add_2_tmp_1 <= ({2'b00, buff_out_reg_21}) + ({2'b00, buff_out_reg_23}) ; + add_2_tmp_2 <= {1'b0, buff_out_reg_22, 1'b0} ; + add_2_tmp <= add_2_tmp_1 + add_2_tmp_2 ; + add_4_tmp_1 <= ({4'b0000, buff_out_reg_41}) + ({4'b0000, buff_out_reg_47}) ; + add_4_tmp_2 <= ({3'b000, buff_out_reg_42, 1'b0}) + ({3'b000, buff_out_reg_46, 1'b0}) ; + add_4_tmp_3 <= ({3'b000, buff_out_reg_43, 1'b0}) + ({3'b000, buff_out_reg_45, 1'b0}) ; + add_4_tmp_4 <= ({4'b0000, buff_out_reg_43}) + ({4'b0000, buff_out_reg_45}) ; + add_4_tmp_5 <= ({2'b00, buff_out_reg_44, 2'b00}) ; + add_4_tmp_6 <= add_4_tmp_1 + add_4_tmp_2 ; + add_4_tmp_7 <= add_4_tmp_3 + add_4_tmp_4 ; + add_4_tmp_8 <= add_4_tmp_5 + add_4_tmp_6 ; + add_4_tmp <= add_4_tmp_7 + add_4_tmp_8 ; + end +endmodule +// Discription: this block creates a simple +// shift register +// date: July 27 ,2002 +// By: Ahmad darabiha +// copy from sh_reg.vhd changed to only 1-in-1-out +module sh_reg_1 (clk, wen, din_1, dout_1); + + input clk; + input wen; + input[8 - 1:0] din_1; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + dout_1 <= din_1 ; + end + end +endmodule +module wrapper_qs_intr_10_20 (clk, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, +wen_4, addrin, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20, +rdy); + + input clk; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input[7:0] din6; + input[7:0] din7; + input[7:0] din8; + input[7:0] din9; + input[7:0] din10; + input wen_4; + input[18:0] addrin; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + wire[15:0] dout0; + wire[15:0] dout1; + wire[15:0] dout2; + wire[15:0] dout3; + wire[15:0] dout4; + wire[15:0] dout5; + wire[15:0] dout6; + wire[15:0] dout7; + wire[15:0] dout8; + wire[15:0] dout9; + wire[15:0] dout10; + wire[15:0] dout11; + wire[15:0] dout12; + wire[15:0] dout13; + wire[15:0] dout14; + wire[15:0] dout15; + wire[15:0] dout16; + wire[15:0] dout17; + wire[15:0] dout18; + wire[15:0] dout19; + wire[15:0] dout20; + output rdy; + wire rdy; + wire[15:0] dout_tmp0; + wire[15:0] dout_tmp1; + wire[15:0] dout_tmp2; + wire[15:0] dout_tmp3; + wire[15:0] dout_tmp4; + wire[15:0] dout_tmp5; + wire[15:0] dout_tmp6; + wire[15:0] dout_tmp7; + wire[15:0] dout_tmp8; + wire[15:0] dout_tmp9; + wire[15:0] dout_tmp10; + wire[15:0] dout_tmp11; + wire[15:0] dout_tmp12; + wire[15:0] dout_tmp13; + wire[15:0] dout_tmp14; + wire[15:0] dout_tmp15; + wire[15:0] dout_tmp16; + wire[15:0] dout_tmp17; + wire[15:0] dout_tmp18; + wire[15:0] dout_tmp19; + wire[15:0] dout_tmp20; + wire[7:0] addr_tmp; + wire[15:0] dout_tt; + + reg [15:0]tmy_ram0; + reg [15:0]tmy_ram1; + reg [15:0]tmy_ram2; + reg [15:0]tmy_ram3; + reg [15:0]tmy_ram4; + reg [15:0]tmy_ram5; + reg [15:0]tmy_ram6; + reg [15:0]tmy_ram7; + reg [15:0]tmy_ram8; + reg [15:0]tmy_ram9; + reg [15:0]tmy_ram10; + reg [15:0]tmy_ram11; + reg [15:0]tmy_ram12; + reg [15:0]tmy_ram13; + reg [15:0]tmy_ram14; + reg [15:0]tmy_ram15; + reg [15:0]tmy_ram16; + reg [15:0]tmy_ram17; + reg [15:0]tmy_ram18; + reg [15:0]tmy_ram19; + reg [15:0]tmy_ram20; + reg [15:0]my_ram0; + reg [15:0]my_ram1; + reg [15:0]my_ram2; + reg [15:0]my_ram3; + reg [15:0]my_ram4; + reg [15:0]my_ram5; + reg [15:0]my_ram6; + reg [15:0]my_ram7; + reg [15:0]my_ram8; + reg [15:0]my_ram9; + reg [15:0]my_ram10; + reg [15:0]my_ram11; + reg [15:0]my_ram12; + reg [15:0]my_ram13; + reg [15:0]my_ram14; + reg [15:0]my_ram15; + reg [15:0]my_ram16; + reg [15:0]my_ram17; + reg [15:0]my_ram18; + reg [15:0]my_ram19; + reg [15:0]my_ram20; + + assign rdy = 1'b1; + assign dout0 = my_ram0; + assign dout1 = my_ram1; + assign dout2 = my_ram2; + assign dout3 = my_ram3; + assign dout4 = my_ram4; + assign dout5 = my_ram5; + assign dout6 = my_ram6; + assign dout7 = my_ram7; + assign dout8 = my_ram8; + assign dout9 = my_ram9; + assign dout10 = my_ram10; + assign dout11 = my_ram11; + assign dout12 = my_ram12; + assign dout13 = my_ram13; + assign dout14 = my_ram14; + assign dout15 = my_ram15; + assign dout16 = my_ram16; + assign dout17 = my_ram17; + assign dout18 = my_ram18; + assign dout19 = my_ram19; + assign dout20 = my_ram20; + always @(posedge clk) + begin + if (wen_4 == 1'b1) + begin + tmy_ram0 <= dout_tmp0; + tmy_ram1 <= dout_tmp1; + tmy_ram2 <= dout_tmp2; + tmy_ram3 <= dout_tmp3; + tmy_ram4 <= dout_tmp4; + tmy_ram5 <= dout_tmp5; + tmy_ram6 <= dout_tmp6; + tmy_ram7 <= dout_tmp7; + tmy_ram8 <= dout_tmp8; + tmy_ram9 <= dout_tmp9; + tmy_ram10 <= dout_tmp10; + tmy_ram11 <= dout_tmp11; + tmy_ram12 <= dout_tmp12; + tmy_ram13 <= dout_tmp13; + tmy_ram14 <= dout_tmp14; + tmy_ram15 <= dout_tmp15; + tmy_ram16 <= dout_tmp16; + tmy_ram17 <= dout_tmp17; + tmy_ram18 <= dout_tmp18; + tmy_ram19 <= dout_tmp19; + tmy_ram20 <= dout_tmp20; + my_ram0 <= tmy_ram0; + my_ram1 <= tmy_ram1; + my_ram2 <= tmy_ram2; + my_ram3 <= tmy_ram3; + my_ram4 <= tmy_ram4; + my_ram5 <= tmy_ram5; + my_ram6 <= tmy_ram6; + my_ram7 <= tmy_ram7; + my_ram8 <= tmy_ram8; + my_ram9 <= tmy_ram9; + my_ram10 <= tmy_ram10; + my_ram11 <= tmy_ram11; + my_ram12 <= tmy_ram12; + my_ram13 <= tmy_ram13; + my_ram14 <= tmy_ram14; + my_ram15 <= tmy_ram15; + my_ram16 <= tmy_ram16; + my_ram17 <= tmy_ram17; + my_ram18 <= tmy_ram18; + my_ram19 <= tmy_ram19; + my_ram20 <= tmy_ram20; + end + end + + assign addr_tmp = addrin; + + quadintr_10_20 my_inst_quadintr(clk, wen_4, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, + dout_tmp0, + dout_tmp1, + dout_tmp2, + dout_tmp3, + dout_tmp4, + dout_tmp5, + dout_tmp6, + dout_tmp7, + dout_tmp8, + dout_tmp9, + dout_tmp10, + dout_tmp11, + dout_tmp12, + dout_tmp13, + dout_tmp14, + dout_tmp15, + dout_tmp16, + dout_tmp17, + dout_tmp18, + dout_tmp19, + dout_tmp20); + +endmodule + + + +module wrapper_qs_intr_5_20 (clk, + din0, + din1, + din2, + din3, + din4, + din5, +wen_4, addrin, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20, +rdy); + + input clk; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input wen_4; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + wire[15:0] dout0; + wire[15:0] dout1; + wire[15:0] dout2; + wire[15:0] dout3; + wire[15:0] dout4; + wire[15:0] dout5; + wire[15:0] dout6; + wire[15:0] dout7; + wire[15:0] dout8; + wire[15:0] dout9; + wire[15:0] dout10; + wire[15:0] dout11; + wire[15:0] dout12; + wire[15:0] dout13; + wire[15:0] dout14; + wire[15:0] dout15; + wire[15:0] dout16; + wire[15:0] dout17; + wire[15:0] dout18; + wire[15:0] dout19; + wire[15:0] dout20; + input[18:0] addrin; + output rdy; + wire rdy; + wire[15:0] dout_tmp0; + wire[15:0] dout_tmp1; + wire[15:0] dout_tmp2; + wire[15:0] dout_tmp3; + wire[15:0] dout_tmp4; + wire[15:0] dout_tmp5; + wire[15:0] dout_tmp6; + wire[15:0] dout_tmp7; + wire[15:0] dout_tmp8; + wire[15:0] dout_tmp9; + wire[15:0] dout_tmp10; + wire[15:0] dout_tmp11; + wire[15:0] dout_tmp12; + wire[15:0] dout_tmp13; + wire[15:0] dout_tmp14; + wire[15:0] dout_tmp15; + wire[15:0] dout_tmp16; + wire[15:0] dout_tmp17; + wire[15:0] dout_tmp18; + wire[15:0] dout_tmp19; + wire[15:0] dout_tmp20; + wire[7:0] addr_tmp; + wire[15:0] dout_tt; + + reg [15:0]tmy_ram0; + reg [15:0]tmy_ram1; + reg [15:0]tmy_ram2; + reg [15:0]tmy_ram3; + reg [15:0]tmy_ram4; + reg [15:0]tmy_ram5; + reg [15:0]tmy_ram6; + reg [15:0]tmy_ram7; + reg [15:0]tmy_ram8; + reg [15:0]tmy_ram9; + reg [15:0]tmy_ram10; + reg [15:0]tmy_ram11; + reg [15:0]tmy_ram12; + reg [15:0]tmy_ram13; + reg [15:0]tmy_ram14; + reg [15:0]tmy_ram15; + reg [15:0]tmy_ram16; + reg [15:0]tmy_ram17; + reg [15:0]tmy_ram18; + reg [15:0]tmy_ram19; + reg [15:0]tmy_ram20; + reg [15:0]my_ram0; + reg [15:0]my_ram1; + reg [15:0]my_ram2; + reg [15:0]my_ram3; + reg [15:0]my_ram4; + reg [15:0]my_ram5; + reg [15:0]my_ram6; + reg [15:0]my_ram7; + reg [15:0]my_ram8; + reg [15:0]my_ram9; + reg [15:0]my_ram10; + reg [15:0]my_ram11; + reg [15:0]my_ram12; + reg [15:0]my_ram13; + reg [15:0]my_ram14; + reg [15:0]my_ram15; + reg [15:0]my_ram16; + reg [15:0]my_ram17; + reg [15:0]my_ram18; + reg [15:0]my_ram19; + reg [15:0]my_ram20; + + assign rdy = 1'b1; + assign dout0 = my_ram0; + assign dout1 = my_ram1; + assign dout2 = my_ram2; + assign dout3 = my_ram3; + assign dout4 = my_ram4; + assign dout5 = my_ram5; + assign dout6 = my_ram6; + assign dout7 = my_ram7; + assign dout8 = my_ram8; + assign dout9 = my_ram9; + assign dout10 = my_ram10; + assign dout11 = my_ram11; + assign dout12 = my_ram12; + assign dout13 = my_ram13; + assign dout14 = my_ram14; + assign dout15 = my_ram15; + assign dout16 = my_ram16; + assign dout17 = my_ram17; + assign dout18 = my_ram18; + assign dout19 = my_ram19; + assign dout20 = my_ram20; + always @(posedge clk) + begin + if (wen_4 == 1'b1) + begin + tmy_ram0 <= dout_tmp0; + tmy_ram1 <= dout_tmp1; + tmy_ram2 <= dout_tmp2; + tmy_ram3 <= dout_tmp3; + tmy_ram4 <= dout_tmp4; + tmy_ram5 <= dout_tmp5; + tmy_ram6 <= dout_tmp6; + tmy_ram7 <= dout_tmp7; + tmy_ram8 <= dout_tmp8; + tmy_ram9 <= dout_tmp9; + tmy_ram10 <= dout_tmp10; + tmy_ram11 <= dout_tmp11; + tmy_ram12 <= dout_tmp12; + tmy_ram13 <= dout_tmp13; + tmy_ram14 <= dout_tmp14; + tmy_ram15 <= dout_tmp15; + tmy_ram16 <= dout_tmp16; + tmy_ram17 <= dout_tmp17; + tmy_ram18 <= dout_tmp18; + tmy_ram19 <= dout_tmp19; + tmy_ram20 <= dout_tmp20; + my_ram0 <= tmy_ram0; + my_ram1 <= tmy_ram1; + my_ram2 <= tmy_ram2; + my_ram3 <= tmy_ram3; + my_ram4 <= tmy_ram4; + my_ram5 <= tmy_ram5; + my_ram6 <= tmy_ram6; + my_ram7 <= tmy_ram7; + my_ram8 <= tmy_ram8; + my_ram9 <= tmy_ram9; + my_ram10 <= tmy_ram10; + my_ram11 <= tmy_ram11; + my_ram12 <= tmy_ram12; + my_ram13 <= tmy_ram13; + my_ram14 <= tmy_ram14; + my_ram15 <= tmy_ram15; + my_ram16 <= tmy_ram16; + my_ram17 <= tmy_ram17; + my_ram18 <= tmy_ram18; + my_ram19 <= tmy_ram19; + my_ram20 <= tmy_ram20; + end + end + + assign addr_tmp = {1'b0, addrin} ; + + + quadintr_5_20 my_inst_quadintr(clk, wen_4, + din0, + din1, + din2, + din3, + din4, + din5, + dout_tmp0, + dout_tmp1, + dout_tmp2, + dout_tmp3, + dout_tmp4, + dout_tmp5, + dout_tmp6, + dout_tmp7, + dout_tmp8, + dout_tmp9, + dout_tmp10, + dout_tmp11, + dout_tmp12, + dout_tmp13, + dout_tmp14, + dout_tmp15, + dout_tmp16, + dout_tmp17, + dout_tmp18, + dout_tmp19, + dout_tmp20); +endmodule + + + +module quadintr_10_20 (clk, new_data, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20); + + + input clk; + input new_data; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input[7:0] din6; + input[7:0] din7; + input[7:0] din8; + input[7:0] din9; + input[7:0] din10; + reg[7:0] dinr0; + reg[7:0] dinr1; + reg[7:0] dinr2; + reg[7:0] dinr3; + reg[7:0] dinr4; + reg[7:0] dinr5; + reg[7:0] dinr6; + reg[7:0] dinr7; + reg[7:0] dinr8; + reg[7:0] dinr9; + reg[7:0] dinr10; + + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + reg[15:0] dout0; + reg[15:0] dout1; + reg[15:0] dout2; + reg[15:0] dout3; + reg[15:0] dout4; + reg[15:0] dout5; + reg[15:0] dout6; + reg[15:0] dout7; + reg[15:0] dout8; + reg[15:0] dout9; + reg[15:0] dout10; + reg[15:0] dout11; + reg[15:0] dout12; + reg[15:0] dout13; + reg[15:0] dout14; + reg[15:0] dout15; + reg[15:0] dout16; + reg[15:0] dout17; + reg[15:0] dout18; + reg[15:0] dout19; + reg[15:0] dout20; + + reg[7:0] tmp_10; + reg[7:0] tmp_11; + reg[7:0] tmp_12; + reg[7:0] tmp_13; + reg[7:0] tmp_14; + reg[7:0] tmp_15; + reg[7:0] tmp_16; + reg[7:0] tmp_17; + reg[7:0] tmp_18; + reg[7:0] tmp_19; + reg[7:0] tmp_110; + reg[7:0] tmp_111; + reg[7:0] tmp_112; + reg[7:0] tmp_113; + reg[7:0] tmp_114; + reg[7:0] tmp_115; + reg[7:0] tmp_116; + reg[7:0] tmp_117; + reg[7:0] tmp_118; + reg[7:0] tmp_119; + reg[7:0] tmp_120; + reg[7:0] tmp_20; + reg[7:0] tmp_21; + reg[7:0] tmp_22; + reg[7:0] tmp_23; + reg[7:0] tmp_24; + reg[7:0] tmp_25; + reg[7:0] tmp_26; + reg[7:0] tmp_27; + reg[7:0] tmp_28; + reg[7:0] tmp_29; + reg[7:0] tmp_210; + reg[7:0] tmp_211; + reg[7:0] tmp_212; + reg[7:0] tmp_213; + reg[7:0] tmp_214; + reg[7:0] tmp_215; + reg[7:0] tmp_216; + reg[7:0] tmp_217; + reg[7:0] tmp_218; + reg[7:0] tmp_219; + reg[7:0] tmp_220; + reg[7:0] tmp_30; + reg[7:0] tmp_31; + reg[7:0] tmp_32; + reg[7:0] tmp_33; + reg[7:0] tmp_34; + reg[7:0] tmp_35; + reg[7:0] tmp_36; + reg[7:0] tmp_37; + reg[7:0] tmp_38; + reg[7:0] tmp_39; + reg[7:0] tmp_310; + reg[7:0] tmp_311; + reg[7:0] tmp_312; + reg[7:0] tmp_313; + reg[7:0] tmp_314; + reg[7:0] tmp_315; + reg[7:0] tmp_316; + reg[7:0] tmp_317; + reg[7:0] tmp_318; + reg[7:0] tmp_319; + reg[7:0] tmp_320; + reg[8:0] add_tmp0; + reg[8:0] add_tmp1; + reg[8:0] add_tmp2; + reg[8:0] add_tmp3; + reg[8:0] add_tmp4; + reg[8:0] add_tmp5; + reg[8:0] add_tmp6; + reg[8:0] add_tmp7; + reg[8:0] add_tmp8; + reg[8:0] add_tmp9; + reg[8:0] add_tmp10; + reg[8:0] add_tmp11; + reg[8:0] add_tmp12; + reg[8:0] add_tmp13; + reg[8:0] add_tmp14; + reg[8:0] add_tmp15; + reg[8:0] add_tmp16; + reg[8:0] add_tmp17; + reg[8:0] add_tmp18; + reg[8:0] add_tmp19; + reg[8:0] add_tmp20; + reg[8:0] doutr0; + reg[8:0] doutr1; + reg[8:0] doutr2; + reg[8:0] doutr3; + reg[8:0] doutr4; + reg[8:0] doutr5; + reg[8:0] doutr6; + reg[8:0] doutr7; + reg[8:0] doutr8; + reg[8:0] doutr9; + reg[8:0] doutr10; + reg[8:0] doutr11; + reg[8:0] doutr12; + reg[8:0] doutr13; + reg[8:0] doutr14; + reg[8:0] doutr15; + reg[8:0] doutr16; + reg[8:0] doutr17; + reg[8:0] doutr18; + reg[8:0] doutr19; + reg[8:0] doutr20; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + dinr0 <= din0; + dinr1 <= din1; + dinr2 <= din2; + dinr3 <= din3; + dinr4 <= din4; + dinr5 <= din5; + dinr6 <= din6; + dinr7 <= din7; + dinr8 <= din8; + dinr9 <= din9; + dinr10 <= din10; + + dout0[15:9] <= {doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8]}; + dout1[15:9] <= {doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8]}; + dout2[15:9] <= {doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8]}; + dout3[15:9] <= {doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8]}; + dout4[15:9] <= {doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8]}; + dout5[15:9] <= {doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8]}; + dout6[15:9] <= {doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8]}; + dout7[15:9] <= {doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8]}; + dout8[15:9] <= {doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8]}; + dout9[15:9] <= {doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8]}; + dout10[15:9] <= {doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8]}; + dout11[15:9] <= {doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8]}; + dout12[15:9] <= {doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8]}; + dout13[15:9] <= {doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8]}; + dout14[15:9] <= {doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8]}; + dout15[15:9] <= {doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8]}; + dout16[15:9] <= {doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8]}; + dout17[15:9] <= {doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8]}; + dout18[15:9] <= {doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8]}; + dout19[15:9] <= {doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8]}; + dout20[15:9] <= {doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8]}; + dout0[8:0] <= doutr0; + dout1[8:0] <= doutr1; + dout2[8:0] <= doutr2; + dout3[8:0] <= doutr3; + dout4[8:0] <= doutr4; + dout5[8:0] <= doutr5; + dout6[8:0] <= doutr6; + dout7[8:0] <= doutr7; + dout8[8:0] <= doutr8; + dout9[8:0] <= doutr9; + dout10[8:0] <= doutr10; + dout11[8:0] <= doutr11; + dout12[8:0] <= doutr12; + dout13[8:0] <= doutr13; + dout14[8:0] <= doutr14; + dout15[8:0] <= doutr15; + dout16[8:0] <= doutr16; + dout17[8:0] <= doutr17; + dout18[8:0] <= doutr18; + dout19[8:0] <= doutr19; + dout20[8:0] <= doutr20; + end + doutr0 <= {dinr0[8-1], dinr0}; + doutr2 <= {dinr1[8-1], dinr1}; + doutr4 <= {dinr2[8-1], dinr2}; + doutr6 <= {dinr3[8-1], dinr3}; + doutr8 <= {dinr4[8-1], dinr4}; + doutr10 <= {dinr5[8-1], dinr5}; + doutr12 <= {dinr6[8-1], dinr6}; + doutr14 <= {dinr7[8-1], dinr7}; + doutr16 <= {dinr8[8-1], dinr8}; + + tmp_11 <= {dinr0[8-1], dinr0[8-1], dinr0[8-1:2]} + {dinr0[8-1], dinr0[8-1], dinr0[8-1], dinr0[8-1:3]}; + tmp_13 <= {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1], dinr1[8-1:3]}; + tmp_15 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_17 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_19 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_111 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1:2]} + {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + tmp_113 <= {dinr6[8-1], dinr6[8-1], dinr6[8-1:2]} + {dinr6[8-1], dinr6[8-1], dinr6[8-1], dinr6[8-1:3]}; + tmp_115 <= {dinr7[8-1], dinr7[8-1], dinr7[8-1:2]} + {dinr7[8-1], dinr7[8-1], dinr7[8-1], dinr7[8-1:3]}; + tmp_117 <= {dinr8[8-1], dinr8[8-1], dinr8[8-1:2]} + {dinr8[8-1], dinr8[8-1], dinr8[8-1], dinr8[8-1:3]}; + + tmp_21 <= {dinr1[8-1], dinr1[8-1:1]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]}; + tmp_23 <= {dinr2[8-1], dinr2[8-1:1]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]}; + tmp_25 <= {dinr3[8-1], dinr3[8-1:1]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]}; + tmp_27 <= {dinr4[8-1], dinr4[8-1:1]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]}; + tmp_29 <= {dinr5[8-1], dinr5[8-1:1]} + {dinr5[8-1], dinr5[8-1], dinr5[8-1:2]}; + tmp_211 <= {dinr6[8-1], dinr6[8-1:1]} + {dinr6[8-1], dinr6[8-1], dinr6[8-1:2]}; + tmp_213 <= {dinr7[8-1], dinr7[8-1:1]} + {dinr7[8-1], dinr7[8-1], dinr7[8-1:2]}; + tmp_215 <= {dinr8[8-1], dinr8[8-1:1]} + {dinr8[8-1], dinr8[8-1], dinr8[8-1:2]}; + tmp_217 <= {dinr9[8-1], dinr9[8-1:1]} + {dinr9[8-1], dinr9[8-1], dinr9[8-1:2]}; + + tmp_31 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_33 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_35 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_37 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + tmp_39 <= {dinr6[8-1], dinr6[8-1], dinr6[8-1], dinr6[8-1:3]}; + tmp_311 <= {dinr7[8-1], dinr7[8-1], dinr7[8-1], dinr7[8-1:3]}; + tmp_313 <= {dinr8[8-1], dinr8[8-1], dinr8[8-1], dinr8[8-1:3]}; + tmp_315 <= {dinr9[8-1], dinr9[8-1], dinr9[8-1], dinr9[8-1:3]}; + tmp_317 <= {dinr10[8-1], dinr10[8-1], dinr10[8-1], dinr10[8-1:3]}; + + add_tmp1 <= {tmp_11[8-1], tmp_11} + {tmp_21[8-1], tmp_21}; + add_tmp3 <= {tmp_13[8-1], tmp_13} + {tmp_23[8-1], tmp_23}; + add_tmp5 <= {tmp_15[8-1], tmp_15} + {tmp_25[8-1], tmp_25}; + add_tmp7 <= {tmp_17[8-1], tmp_17} + {tmp_27[8-1], tmp_27}; + add_tmp9 <= {tmp_19[8-1], tmp_19} + {tmp_29[8-1], tmp_29}; + add_tmp11 <= {tmp_111[8-1], tmp_111} + {tmp_211[8-1], tmp_211}; + add_tmp13 <= {tmp_113[8-1], tmp_113} + {tmp_213[8-1], tmp_213}; + add_tmp15 <= {tmp_115[8-1], tmp_115} + {tmp_215[8-1], tmp_215}; + add_tmp17 <= {tmp_117[8-1], tmp_117} + {tmp_217[8-1], tmp_217}; + + doutr1 <= add_tmp1 - {tmp_31[8-1], tmp_31}; + doutr3 <= add_tmp3 - {tmp_33[8-1], tmp_33}; + doutr5 <= add_tmp5 - {tmp_35[8-1], tmp_35}; + doutr7 <= add_tmp7 - {tmp_37[8-1], tmp_37}; + doutr9 <= add_tmp9 - {tmp_39[8-1], tmp_39}; + doutr11 <= add_tmp11 - {tmp_311[8-1], tmp_311}; + doutr13 <= add_tmp13 - {tmp_313[8-1], tmp_313}; + doutr15 <= add_tmp15 - {tmp_315[8-1], tmp_315}; + doutr17 <= add_tmp17 - {tmp_317[8-1], tmp_317}; + + doutr18 <= {dinr9[8-1] , dinr9}; + + tmp_119 <= {dinr8[8-1], dinr8[8-1] , dinr8[8-1] , dinr8[8-1 : 3]}; + + tmp_219 <= {dinr9[8-1], dinr9[8-1 : 1]} + {dinr9[8-1], dinr9[8-1] , dinr9[8-1 : 2]}; + + tmp_319 <= {dinr10[8-1] , dinr10[8-1] , dinr10[8-1 : 2]} + {dinr10[8-1] , dinr10[8-1] , dinr10[8-1] , dinr10[8-1 : 3]}; + + add_tmp19 <= {tmp_219[8-1] , tmp_219} + {tmp_319[8-1] , tmp_319}; + + doutr19 <= add_tmp19 - {tmp_119[8-1] , tmp_119}; + + doutr20 <= {dinr10[8-1] , dinr10}; + end +endmodule + + + +module quadintr_5_20 (clk, new_data, + din0, + din1, + din2, + din3, + din4, + din5, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20); + + input clk; + input new_data; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + reg[7:0] dinr0; + reg[7:0] dinr1; + reg[7:0] dinr2; + reg[7:0] dinr3; + reg[7:0] dinr4; + reg[7:0] dinr5; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + reg[15:0] dout0; + reg[15:0] dout1; + reg[15:0] dout2; + reg[15:0] dout3; + reg[15:0] dout4; + reg[15:0] dout5; + reg[15:0] dout6; + reg[15:0] dout7; + reg[15:0] dout8; + reg[15:0] dout9; + reg[15:0] dout10; + reg[15:0] dout11; + reg[15:0] dout12; + reg[15:0] dout13; + reg[15:0] dout14; + reg[15:0] dout15; + reg[15:0] dout16; + reg[15:0] dout17; + reg[15:0] dout18; + reg[15:0] dout19; + reg[15:0] dout20; + + reg[7:0] tmp_10; + reg[7:0] tmp_11; + reg[7:0] tmp_12; + reg[7:0] tmp_13; + reg[7:0] tmp_14; + reg[7:0] tmp_15; + reg[7:0] tmp_16; + reg[7:0] tmp_17; + reg[7:0] tmp_18; + reg[7:0] tmp_19; + reg[7:0] tmp_110; + reg[7:0] tmp_20; + reg[7:0] tmp_21; + reg[7:0] tmp_22; + reg[7:0] tmp_23; + reg[7:0] tmp_24; + reg[7:0] tmp_25; + reg[7:0] tmp_26; + reg[7:0] tmp_27; + reg[7:0] tmp_28; + reg[7:0] tmp_29; + reg[7:0] tmp_210; + reg[7:0] tmp_30; + reg[7:0] tmp_31; + reg[7:0] tmp_32; + reg[7:0] tmp_33; + reg[7:0] tmp_34; + reg[7:0] tmp_35; + reg[7:0] tmp_36; + reg[7:0] tmp_37; + reg[7:0] tmp_38; + reg[7:0] tmp_39; + reg[7:0] tmp_310; + reg[8:0] add_tmp0; + reg[8:0] add_tmp1; + reg[8:0] add_tmp2; + reg[8:0] add_tmp3; + reg[8:0] add_tmp4; + reg[8:0] add_tmp5; + reg[8:0] add_tmp6; + reg[8:0] add_tmp7; + reg[8:0] add_tmp8; + reg[8:0] add_tmp9; + reg[8:0] add_tmp10; + reg[8:0] doutr0; + reg[8:0] doutr1; + reg[8:0] doutr2; + reg[8:0] doutr3; + reg[8:0] doutr4; + reg[8:0] doutr5; + reg[8:0] doutr6; + reg[8:0] doutr7; + reg[8:0] doutr8; + reg[8:0] doutr9; + reg[8:0] doutr10; + reg[8:0] doutr11; + reg[8:0] doutr12; + reg[8:0] doutr13; + reg[8:0] doutr14; + reg[8:0] doutr15; + reg[8:0] doutr16; + reg[8:0] doutr17; + reg[8:0] doutr18; + reg[8:0] doutr19; + reg[8:0] doutr20; + + + reg[8:0] tmp_1_100; + reg[8:0] tmp_1_101; + reg[8:0] tmp_1_102; + reg[8:0] tmp_1_103; + reg[8:0] tmp_1_104; + reg[8:0] tmp_1_105; + reg[8:0] tmp_1_106; + reg[8:0] tmp_1_107; + reg[8:0] tmp_1_108; + reg[8:0] tmp_1_109; + reg[8:0] tmp_1_1010; + reg[8:0] tmp_1_1011; + reg[8:0] tmp_1_1012; + reg[8:0] tmp_1_1013; + reg[8:0] tmp_1_1014; + reg[8:0] tmp_1_1015; + reg[8:0] tmp_1_1016; + reg[8:0] tmp_1_1017; + reg[8:0] tmp_1_1018; + reg[8:0] tmp_1_1019; + reg[8:0] tmp_1_1020; + reg[8:0] tmp_2_100; + reg[8:0] tmp_2_101; + reg[8:0] tmp_2_102; + reg[8:0] tmp_2_103; + reg[8:0] tmp_2_104; + reg[8:0] tmp_2_105; + reg[8:0] tmp_2_106; + reg[8:0] tmp_2_107; + reg[8:0] tmp_2_108; + reg[8:0] tmp_2_109; + reg[8:0] tmp_2_1010; + reg[8:0] tmp_2_1011; + reg[8:0] tmp_2_1012; + reg[8:0] tmp_2_1013; + reg[8:0] tmp_2_1014; + reg[8:0] tmp_2_1015; + reg[8:0] tmp_2_1016; + reg[8:0] tmp_2_1017; + reg[8:0] tmp_2_1018; + reg[8:0] tmp_2_1019; + reg[8:0] tmp_2_1020; + reg[8:0] tmp_3_100; + reg[8:0] tmp_3_101; + reg[8:0] tmp_3_102; + reg[8:0] tmp_3_103; + reg[8:0] tmp_3_104; + reg[8:0] tmp_3_105; + reg[8:0] tmp_3_106; + reg[8:0] tmp_3_107; + reg[8:0] tmp_3_108; + reg[8:0] tmp_3_109; + reg[8:0] tmp_3_1010; + reg[8:0] tmp_3_1011; + reg[8:0] tmp_3_1012; + reg[8:0] tmp_3_1013; + reg[8:0] tmp_3_1014; + reg[8:0] tmp_3_1015; + reg[8:0] tmp_3_1016; + reg[8:0] tmp_3_1017; + reg[8:0] tmp_3_1018; + reg[8:0] tmp_3_1019; + reg[8:0] tmp_3_1020; + reg[8:0] add_tmp_100; + reg[8:0] add_tmp_101; + reg[8:0] add_tmp_102; + reg[8:0] add_tmp_103; + reg[8:0] add_tmp_104; + reg[8:0] add_tmp_105; + reg[8:0] add_tmp_106; + reg[8:0] add_tmp_107; + reg[8:0] add_tmp_108; + reg[8:0] add_tmp_109; + reg[8:0] add_tmp_1010; + reg[8:0] add_tmp_1011; + reg[8:0] add_tmp_1012; + reg[8:0] add_tmp_1013; + reg[8:0] add_tmp_1014; + reg[8:0] add_tmp_1015; + reg[8:0] add_tmp_1016; + reg[8:0] add_tmp_1017; + reg[8:0] add_tmp_1018; + reg[8:0] add_tmp_1019; + reg[8:0] add_tmp_1020; + + reg[8:0] doutr_100; + reg[8:0] doutr_101; + reg[8:0] doutr_102; + reg[8:0] doutr_103; + reg[8:0] doutr_104; + reg[8:0] doutr_105; + reg[8:0] doutr_106; + reg[8:0] doutr_107; + reg[8:0] doutr_108; + reg[8:0] doutr_109; + reg[8:0] doutr_1010; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + dinr0 <= din0; + dinr1 <= din1; + dinr2 <= din2; + dinr3 <= din3; + dinr4 <= din4; + dinr5 <= din5; + + dout0[15:9] <= {doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8]}; + dout1[15:9] <= {doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8]}; + dout2[15:9] <= {doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8]}; + dout3[15:9] <= {doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8]}; + dout4[15:9] <= {doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8]}; + dout5[15:9] <= {doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8]}; + dout6[15:9] <= {doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8]}; + dout7[15:9] <= {doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8]}; + dout8[15:9] <= {doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8]}; + dout9[15:9] <= {doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8]}; + dout10[15:9] <= {doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8]}; + dout11[15:9] <= {doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8]}; + dout12[15:9] <= {doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8]}; + dout13[15:9] <= {doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8]}; + dout14[15:9] <= {doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8]}; + dout15[15:9] <= {doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8]}; + dout16[15:9] <= {doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8]}; + dout17[15:9] <= {doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8]}; + dout18[15:9] <= {doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8]}; + dout19[15:9] <= {doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8]}; + dout20[15:9] <= {doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8]}; + dout0[8:0] <= doutr0; + dout1[8:0] <= doutr1; + dout2[8:0] <= doutr2; + dout3[8:0] <= doutr3; + dout4[8:0] <= doutr4; + dout5[8:0] <= doutr5; + dout6[8:0] <= doutr6; + dout7[8:0] <= doutr7; + dout8[8:0] <= doutr8; + dout9[8:0] <= doutr9; + dout10[8:0] <= doutr10; + dout11[8:0] <= doutr11; + dout12[8:0] <= doutr12; + dout13[8:0] <= doutr13; + dout14[8:0] <= doutr14; + dout15[8:0] <= doutr15; + dout16[8:0] <= doutr16; + dout17[8:0] <= doutr17; + dout18[8:0] <= doutr18; + dout19[8:0] <= doutr19; + dout20[8:0] <= doutr20; + end + + doutr_100 <= {dinr0[8-1], dinr0}; + doutr_102 <= {dinr1[8-1], dinr1}; + doutr_104 <= {dinr2[8-1], dinr2}; + doutr_106 <= {dinr3[8-1], dinr3}; + + tmp_11 <= {dinr0[8-1], dinr0[8-1], dinr0[8-1:2]} + {dinr0[8-1], dinr0[8-1], dinr0[8-1], dinr0[8-1:3]}; + tmp_13 <= {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1], dinr1[8-1:3]}; + tmp_15 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_17 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + + tmp_21 <= {dinr1[8-1], dinr1[8-1:1]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]}; + tmp_23 <= {dinr2[8-1], dinr2[8-1:1]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]}; + tmp_25 <= {dinr3[8-1], dinr3[8-1:1]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]}; + tmp_27 <= {dinr4[8-1], dinr4[8-1:1]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]}; + + tmp_31 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_33 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_35 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_37 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + + add_tmp1 <= {tmp_11[8-1], tmp_11} + {tmp_21[8-1], tmp_21}; + add_tmp3 <= {tmp_13[8-1], tmp_13} + {tmp_23[8-1], tmp_23}; + add_tmp5 <= {tmp_15[8-1], tmp_15} + {tmp_25[8-1], tmp_25}; + add_tmp7 <= {tmp_17[8-1], tmp_17} + {tmp_27[8-1], tmp_27}; + + doutr_101 <= add_tmp1 - {tmp_31[8-1], tmp_31}; + doutr_103 <= add_tmp3 - {tmp_33[8-1], tmp_33}; + doutr_105 <= add_tmp5 - {tmp_35[8-1], tmp_35}; + doutr_107 <= add_tmp7 - {tmp_37[8-1], tmp_37}; + + doutr_108 <= {dinr4[8-1] , dinr4}; + + tmp_19 <= {dinr3[8-1], dinr3[8-1] , dinr3[8-1] , dinr3[8-1:3]}; + + tmp_29 <= {dinr4[8-1], dinr4[8-1:1]} + + {dinr4[8-1], dinr4[8-1] , dinr4[8-1:2]}; + + tmp_39 <= {dinr5[8-1] , dinr5[8-1] , dinr5[8-1:2]} + + {dinr5[8-1] , dinr5[8-1] , dinr5[8-1] , dinr5[8-1:3]}; + + add_tmp9 <= {tmp_29[8-1] , tmp_29} + + {tmp_39[8-1] , tmp_39}; + + doutr_109 <= add_tmp9 - {tmp_19[8-1] , tmp_19}; + + doutr_1010 <= {dinr5[8-1] , dinr5}; + + doutr0 <= doutr_100; + doutr2 <= doutr_101; + doutr4 <= doutr_102; + doutr6 <= doutr_103; + doutr8 <= doutr_104; + doutr10 <= doutr_105; + doutr12 <= doutr_106; + doutr14 <= doutr_107; + doutr16 <= doutr_108; + + tmp_1_101 <= {doutr_100[8] , doutr_100[8] , doutr_100[8:2]} + {doutr_100[8] , doutr_100[8] , doutr_100[8] , doutr_100[8:3]}; + tmp_1_103 <= {doutr_101[8] , doutr_101[8] , doutr_101[8:2]} + {doutr_101[8] , doutr_101[8] , doutr_101[8] , doutr_101[8:3]}; + tmp_1_105 <= {doutr_102[8] , doutr_102[8] , doutr_102[8:2]} + {doutr_102[8] , doutr_102[8] , doutr_102[8] , doutr_102[8:3]}; + tmp_1_107 <= {doutr_103[8] , doutr_103[8] , doutr_103[8:2]} + {doutr_103[8] , doutr_103[8] , doutr_103[8] , doutr_103[8:3]}; + tmp_1_109 <= {doutr_104[8] , doutr_104[8] , doutr_104[8:2]} + {doutr_104[8] , doutr_104[8] , doutr_104[8] , doutr_104[8:3]}; + tmp_1_1011 <= {doutr_105[8] , doutr_105[8] , doutr_105[8:2]} + {doutr_105[8] , doutr_105[8] , doutr_105[8] , doutr_105[8:3]}; + tmp_1_1013 <= {doutr_106[8] , doutr_106[8] , doutr_106[8:2]} + {doutr_106[8] , doutr_106[8] , doutr_106[8] , doutr_106[8:3]}; + tmp_1_1015 <= {doutr_107[8] , doutr_107[8] , doutr_107[8:2]} + {doutr_107[8] , doutr_107[8] , doutr_107[8] , doutr_107[8:3]}; + tmp_1_1017 <= {doutr_108[8] , doutr_108[8] , doutr_108[8:2]} + {doutr_108[8] , doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + + tmp_2_101 <= {doutr_101[8], doutr_101[8:1]} + {doutr_101[8], doutr_101[8] , doutr_101[8:2]}; + tmp_2_103 <= {doutr_102[8], doutr_102[8:1]} + {doutr_102[8], doutr_102[8] , doutr_102[8:2]}; + tmp_2_105 <= {doutr_103[8], doutr_103[8:1]} + {doutr_103[8], doutr_103[8] , doutr_103[8:2]}; + tmp_2_107 <= {doutr_104[8], doutr_104[8:1]} + {doutr_104[8], doutr_104[8] , doutr_104[8:2]}; + tmp_2_109 <= {doutr_105[8], doutr_105[8:1]} + {doutr_105[8], doutr_105[8] , doutr_105[8:2]}; + tmp_2_1011 <= {doutr_106[8], doutr_106[8:1]} + {doutr_106[8], doutr_106[8] , doutr_106[8:2]}; + tmp_2_1013 <= {doutr_107[8], doutr_107[8:1]} + {doutr_107[8], doutr_107[8] , doutr_107[8:2]}; + tmp_2_1015 <= {doutr_108[8], doutr_108[8:1]} + {doutr_108[8], doutr_108[8] , doutr_108[8:2]}; + tmp_2_1017 <= {doutr_109[8], doutr_109[8:1]} + {doutr_109[8], doutr_109[8] , doutr_109[8:2]}; + + tmp_3_101 <= {doutr_102[8], doutr_102[8] , doutr_102[8] , doutr_102[8:3]}; + tmp_3_103 <= {doutr_103[8], doutr_103[8] , doutr_103[8] , doutr_103[8:3]}; + tmp_3_105 <= {doutr_104[8], doutr_104[8] , doutr_104[8] , doutr_104[8:3]}; + tmp_3_107 <= {doutr_105[8], doutr_105[8] , doutr_105[8] , doutr_105[8:3]}; + tmp_3_109 <= {doutr_106[8], doutr_106[8] , doutr_106[8] , doutr_106[8:3]}; + tmp_3_1011 <= {doutr_107[8], doutr_107[8] , doutr_107[8] , doutr_107[8:3]}; + tmp_3_1013 <= {doutr_108[8], doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + tmp_3_1015 <= {doutr_109[8], doutr_109[8] , doutr_109[8] , doutr_109[8:3]}; + tmp_3_1017 <= {doutr_1010[8], doutr_1010[8] , doutr_1010[8] , doutr_1010[8:3]}; + + add_tmp_101 <= tmp_1_101 + tmp_2_101; + add_tmp_103 <= tmp_1_103 + tmp_2_103; + add_tmp_105 <= tmp_1_105 + tmp_2_105; + add_tmp_107 <= tmp_1_107 + tmp_2_107; + add_tmp_109 <= tmp_1_109 + tmp_2_109; + add_tmp_1011 <= tmp_1_1011 + tmp_2_1011; + add_tmp_1013 <= tmp_1_1013 + tmp_2_1013; + add_tmp_1015 <= tmp_1_1015 + tmp_2_1015; + add_tmp_1017 <= tmp_1_1017 + tmp_2_1017; + + doutr1 <= add_tmp_101 - tmp_3_101; + doutr3 <= add_tmp_103 - tmp_3_103; + doutr5 <= add_tmp_105 - tmp_3_105; + doutr7 <= add_tmp_107 - tmp_3_107; + doutr9 <= add_tmp_109 - tmp_3_109; + doutr11 <= add_tmp_1011 - tmp_3_1011; + doutr13 <= add_tmp_1013 - tmp_3_1013; + doutr15 <= add_tmp_1015 - tmp_3_1015; + doutr17 <= add_tmp_1017 - tmp_3_1017; + + doutr18 <= doutr_109; + + tmp_1_1019 <= {doutr_108[8], doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + + tmp_2_1019 <= {doutr_109[8], doutr_109[8:1]} + + {doutr_109[8], doutr_109[8] , doutr_109[8:2]}; + + tmp_3_1019 <= {doutr_1010[8] , doutr_1010[8] , doutr_1010[8:2]} + + {doutr_1010[8] , doutr_1010[8] , doutr_1010[8] , doutr_1010[8:3]}; + + add_tmp_1019 <= tmp_2_1019 + tmp_3_1019; + + doutr19 <= add_tmp_1019 - tmp_1_1019; + + doutr20 <= doutr_1010; + end +endmodule + + + +module find_max (clk, wen, + d_in0, + d_in1, + d_in2, + d_in3, + d_in4, + d_in5, + d_in6, + d_in7, + d_in8, + d_in9, + d_in10, + d_in11, + d_in12, + d_in13, + d_in14, + d_in15, + d_in16, + d_in17, + d_in18, + d_in19, + d_in20, +d_out, indx_out); + + input clk; + input wen; + input[10:0] d_in0; + input[10:0] d_in1; + input[10:0] d_in2; + input[10:0] d_in3; + input[10:0] d_in4; + input[10:0] d_in5; + input[10:0] d_in6; + input[10:0] d_in7; + input[10:0] d_in8; + input[10:0] d_in9; + input[10:0] d_in10; + input[10:0] d_in11; + input[10:0] d_in12; + input[10:0] d_in13; + input[10:0] d_in14; + input[10:0] d_in15; + input[10:0] d_in16; + input[10:0] d_in17; + input[10:0] d_in18; + input[10:0] d_in19; + input[10:0] d_in20; + reg[10:0] d_in_tmp0; + reg[10:0] d_in_tmp1; + reg[10:0] d_in_tmp2; + reg[10:0] d_in_tmp3; + reg[10:0] d_in_tmp4; + reg[10:0] d_in_tmp5; + reg[10:0] d_in_tmp6; + reg[10:0] d_in_tmp7; + reg[10:0] d_in_tmp8; + reg[10:0] d_in_tmp9; + reg[10:0] d_in_tmp10; + reg[10:0] d_in_tmp11; + reg[10:0] d_in_tmp12; + reg[10:0] d_in_tmp13; + reg[10:0] d_in_tmp14; + reg[10:0] d_in_tmp15; + reg[10:0] d_in_tmp16; + reg[10:0] d_in_tmp17; + reg[10:0] d_in_tmp18; + reg[10:0] d_in_tmp19; + reg[10:0] d_in_tmp20; + output[7:0] d_out; + reg[7:0] d_out; + output[4:0] indx_out; + reg[4:0] indx_out; + reg[10:0] res_1_1; + reg[10:0] res_1_2; + reg[10:0] res_1_3; + reg[10:0] res_1_4; + reg[10:0] res_1_5; + reg[10:0] res_1_6; + reg[10:0] res_1_7; + reg[10:0] res_1_8; + reg[10:0] res_1_9; + reg[10:0] res_1_10; + reg[10:0] res_1_11; + reg[10:0] res_2_1; + reg[10:0] res_2_2; + reg[10:0] res_2_3; + reg[10:0] res_2_4; + reg[10:0] res_2_5; + reg[10:0] res_2_6; + reg[10:0] res_3_1; + reg[10:0] res_3_2; + reg[10:0] res_3_3; + reg[10:0] res_4_1; + reg[10:0] res_4_2; + reg[10:0] res_5_1; + reg[4:0] indx_1_1; + reg[4:0] indx_1_2; + reg[4:0] indx_1_3; + reg[4:0] indx_1_4; + reg[4:0] indx_1_5; + reg[4:0] indx_1_6; + reg[4:0] indx_1_7; + reg[4:0] indx_1_8; + reg[4:0] indx_1_9; + reg[4:0] indx_1_10; + reg[4:0] indx_1_11; + reg[4:0] indx_2_1; + reg[4:0] indx_2_2; + reg[4:0] indx_2_3; + reg[4:0] indx_2_4; + reg[4:0] indx_2_5; + reg[4:0] indx_2_6; + reg[4:0] indx_3_1; + reg[4:0] indx_3_2; + reg[4:0] indx_3_3; + reg[4:0] indx_4_1; + reg[4:0] indx_4_2; + reg[4:0] indx_5_1; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + d_in_tmp0 <= d_in0 ; + d_in_tmp1 <= d_in1 ; + d_in_tmp2 <= d_in2 ; + d_in_tmp3 <= d_in3 ; + d_in_tmp4 <= d_in4 ; + d_in_tmp5<= d_in5 ; + d_in_tmp6 <= d_in6 ; + d_in_tmp7 <= d_in7 ; + d_in_tmp8 <= d_in8 ; + d_in_tmp9 <= d_in9 ; + d_in_tmp10 <= d_in10 ; + d_in_tmp11 <= d_in11 ; + d_in_tmp12 <= d_in12 ; + d_in_tmp13 <= d_in13 ; + d_in_tmp14 <= d_in14 ; + d_in_tmp15 <= d_in15; + d_in_tmp16 <= d_in16 ; + d_in_tmp17 <= d_in17 ; + d_in_tmp18 <= d_in18 ; + d_in_tmp19 <= d_in19 ; + d_in_tmp20 <= d_in20 ; + d_out <= res_5_1[10:3] ; + indx_out <= indx_5_1 ; + end + + if (d_in0 > d_in1) + begin + res_1_1 <= d_in0 ; + indx_1_1 <= 5'b00000 ; + end + else + begin + res_1_1 <= d_in1 ; + indx_1_1 <= 5'b00001 ; + end + if (d_in2 > d_in3) + begin + res_1_2 <= d_in2 ; + indx_1_2 <= 5'b00010 ; + end + else + begin + res_1_2 <= d_in3 ; + indx_1_2 <= 5'b00011 ; + end + if (d_in4 > d_in5) + begin + res_1_3 <= d_in4 ; + indx_1_3 <= 5'b00100 ; + end + else + begin + res_1_3 <= d_in5 ; + indx_1_3 <= 5'b00101 ; + end + if (d_in6 > d_in7) + begin + + res_1_4 <= d_in6 ; + indx_1_4 <= 5'b00110 ; + end + else + begin + res_1_4 <= d_in7 ; + indx_1_4 <= 5'b00111 ; + end + if (d_in8 > d_in9) + begin + res_1_5 <= d_in8 ; + indx_1_5 <= 5'b01000 ; + end + else + begin + res_1_5 <= d_in9 ; + indx_1_5 <= 5'b01001 ; + end + if (d_in10 > d_in11) + begin + res_1_6 <= d_in10 ; + indx_1_6 <= 5'b01010 ; + end + else + begin + res_1_6 <= d_in11 ; + indx_1_6 <= 5'b01011 ; + end + if (d_in12 > d_in13) + begin + res_1_7 <= d_in12 ; + indx_1_7 <= 5'b01100 ; + end + else + begin + res_1_7 <= d_in13 ; + indx_1_7 <= 5'b01101 ; + end + if (d_in14 > d_in15) + begin + res_1_8 <= d_in14 ; + indx_1_8 <= 5'b01110 ; + end + else + begin + res_1_8 <= d_in15 ; + indx_1_8 <= 5'b01111 ; + end + if (d_in16 > d_in17) + begin + res_1_9 <= d_in16 ; + indx_1_9 <= 5'b10000 ; + end + else + begin + res_1_9 <= d_in17 ; + indx_1_9 <= 5'b10001 ; + end + if (d_in18 > d_in19) + begin + res_1_10 <= d_in18 ; + indx_1_10 <= 5'b10010 ; + end + else + begin + res_1_10 <= d_in19 ; + indx_1_10 <= 5'b10011 ; + end + res_1_11 <= d_in20 ; + indx_1_11 <= 5'b10100 ; + if (res_1_1 > res_1_2) + begin + res_2_1 <= res_1_1 ; + indx_2_1 <= indx_1_1 ; + end + else + begin + res_2_1 <= res_1_2 ; + indx_2_1 <= indx_1_2 ; + end + if (res_1_3 > res_1_4) + begin + res_2_2 <= res_1_3 ; + indx_2_2 <= indx_1_3 ; + end + else + begin + res_2_2 <= res_1_4 ; + indx_2_2 <= indx_1_4 ; + end + if (res_1_5 > res_1_6) + begin + res_2_3 <= res_1_5 ; + indx_2_3 <= indx_1_5 ; + end + else + begin + res_2_3 <= res_1_6 ; + indx_2_3 <= indx_1_6 ; + end + if (res_1_7 > res_1_8) + begin + res_2_4 <= res_1_7 ; + indx_2_4 <= indx_1_7 ; + end + else + begin + res_2_4 <= res_1_8 ; + indx_2_4 <= indx_1_8 ; + end + if (res_1_9 > res_1_10) + begin + res_2_5 <= res_1_9 ; + indx_2_5 <= indx_1_9 ; + end + else + begin + res_2_5 <= res_1_10 ; + indx_2_5 <= indx_1_10 ; + end + res_2_6 <= res_1_11 ; + indx_2_6 <= indx_1_11 ; + if (res_2_1 > res_2_2) + begin + res_3_1 <= res_2_1 ; + indx_3_1 <= indx_2_1 ; + end + else + begin + res_3_1 <= res_2_2 ; + indx_3_1 <= indx_2_2 ; + end + if (res_2_3 > res_2_4) + begin + res_3_2 <= res_2_3 ; + indx_3_2 <= indx_2_3 ; + end + else + begin + res_3_2 <= res_2_4 ; + indx_3_2 <= indx_2_4 ; + end + if (res_2_5 > res_2_6) + begin + res_3_3 <= res_2_5 ; + indx_3_3 <= indx_2_5 ; + end + else + begin + res_3_3 <= res_2_6 ; + indx_3_3 <= indx_2_6 ; + end + if (res_3_1 > res_3_2) + begin + res_4_1 <= res_3_1 ; + indx_4_1 <= indx_3_1 ; + end + else + begin + res_4_1 <= res_3_2 ; + indx_4_1 <= indx_3_2 ; + end + res_4_2 <= res_3_3 ; + indx_4_2 <= indx_3_3 ; + if (res_4_1 > res_4_2) + begin + res_5_1 <= res_4_1 ; + indx_5_1 <= indx_4_1 ; + end + else + begin + res_5_1 <= res_4_2 ; + indx_5_1 <= indx_4_2 ; + end + end + endmodule + +module lp_fltr (clk, din, dout, ce); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input ce; + + reg[8 - 1:0] din_tmp_1; + reg[8 - 1:0] din_tmp_2; + reg[8 - 1:0] din_tmp_3; + reg[(8 + 2) - 1:0] sum_tmp_1; + reg[(8 + 2) - 1:0] sum_tmp_2; + reg[(8 + 2) - 1:0] sum_tmp_3; + reg[(8 + 2) - 1:0] add_tmp_1; + reg[(8 + 2) - 1:0] add_tmp_2; + + always @(posedge clk) + begin + if (ce == 1'b1) + begin + din_tmp_1 <= din ; + din_tmp_2 <= din_tmp_1 ; + din_tmp_3 <= din_tmp_2 ; + dout <= add_tmp_2[(8 + 2) - 1:2] ; + end + sum_tmp_1 <= {din_tmp_1[8 - 1], din_tmp_1[8 - 1], din_tmp_1} ; + sum_tmp_2 <= {din_tmp_2[8 - 1], din_tmp_2, 1'b0} ; + sum_tmp_3 <= {din_tmp_3[8 - 1], din_tmp_3[8 - 1], din_tmp_3} ; + add_tmp_1 <= sum_tmp_1 + sum_tmp_2 ; + add_tmp_2 <= add_tmp_1 + sum_tmp_3 ; + end +endmodule + + + + + +module port_bus_1to0_1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_1to0, + v_corr_200, + v_corr_201, + v_corr_202, + v_corr_203, + v_corr_204, + v_corr_205, + v_corr_206, + v_corr_207, + v_corr_208, + v_corr_209, + v_corr_2010, + v_corr_2011, + v_corr_2012, + v_corr_2013, + v_corr_2014, + v_corr_2015, + v_corr_2016, + v_corr_2017, + v_corr_2018, + v_corr_2019, + v_corr_2020, +vidin_new_data_scld_2_1to0, + v_corr_100, + v_corr_101, + v_corr_102, + v_corr_103, + v_corr_104, + v_corr_105, + v_corr_106, + v_corr_107, + v_corr_108, + v_corr_109, + v_corr_1010, +vidin_new_data_scld_4_1to0, + v_corr_50, + v_corr_51, + v_corr_52, + v_corr_53, + v_corr_54, + v_corr_55, +bus_word_1, bus_word_2, bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out); + + + input clk; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + output svid_comp_switch; + reg svid_comp_switch; + output vidin_new_data_scld_1_1to0; + reg vidin_new_data_scld_1_1to0; + output[7:0] v_corr_200; + output[7:0] v_corr_201; + output[7:0] v_corr_202; + output[7:0] v_corr_203; + output[7:0] v_corr_204; + output[7:0] v_corr_205; + output[7:0] v_corr_206; + output[7:0] v_corr_207; + output[7:0] v_corr_208; + output[7:0] v_corr_209; + output[7:0] v_corr_2010; + output[7:0] v_corr_2011; + output[7:0] v_corr_2012; + output[7:0] v_corr_2013; + output[7:0] v_corr_2014; + output[7:0] v_corr_2015; + output[7:0] v_corr_2016; + output[7:0] v_corr_2017; + output[7:0] v_corr_2018; + output[7:0] v_corr_2019; + output[7:0] v_corr_2020; + reg[7:0] v_corr_200; + reg[7:0] v_corr_201; + reg[7:0] v_corr_202; + reg[7:0] v_corr_203; + reg[7:0] v_corr_204; + reg[7:0] v_corr_205; + reg[7:0] v_corr_206; + reg[7:0] v_corr_207; + reg[7:0] v_corr_208; + reg[7:0] v_corr_209; + reg[7:0] v_corr_2010; + reg[7:0] v_corr_2011; + reg[7:0] v_corr_2012; + reg[7:0] v_corr_2013; + reg[7:0] v_corr_2014; + reg[7:0] v_corr_2015; + reg[7:0] v_corr_2016; + reg[7:0] v_corr_2017; + reg[7:0] v_corr_2018; + reg[7:0] v_corr_2019; + reg[7:0] v_corr_2020; + output vidin_new_data_scld_2_1to0; + reg vidin_new_data_scld_2_1to0; + output[7:0] v_corr_100; + output[7:0] v_corr_101; + output[7:0] v_corr_102; + output[7:0] v_corr_103; + output[7:0] v_corr_104; + output[7:0] v_corr_105; + output[7:0] v_corr_106; + output[7:0] v_corr_107; + output[7:0] v_corr_108; + output[7:0] v_corr_109; + output[7:0] v_corr_1010; + reg[7:0] v_corr_100; + reg[7:0] v_corr_101; + reg[7:0] v_corr_102; + reg[7:0] v_corr_103; + reg[7:0] v_corr_104; + reg[7:0] v_corr_105; + reg[7:0] v_corr_106; + reg[7:0] v_corr_107; + reg[7:0] v_corr_108; + reg[7:0] v_corr_109; + reg[7:0] v_corr_1010; + output vidin_new_data_scld_4_1to0; + reg vidin_new_data_scld_4_1to0; + output[7:0] v_corr_50; + output[7:0] v_corr_51; + output[7:0] v_corr_52; + output[7:0] v_corr_53; + output[7:0] v_corr_54; + output[7:0] v_corr_55; + reg[7:0] v_corr_50; + reg[7:0] v_corr_51; + reg[7:0] v_corr_52; + reg[7:0] v_corr_53; + reg[7:0] v_corr_54; + reg[7:0] v_corr_55; + input[7:0] bus_word_1; + input[7:0] bus_word_2; + input[7:0] bus_word_3; + input[7:0] bus_word_4; + input[7:0] bus_word_5; + input[7:0] bus_word_6; + input[2:0] counter_out; + + reg[7:0] bus_word_1_tmp; + reg[7:0] bus_word_2_tmp; + reg[7:0] bus_word_3_tmp; + reg[7:0] bus_word_4_tmp; + reg[7:0] bus_word_5_tmp; + reg[7:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_1to0_tmp; + wire vidin_new_data_scld_2_1to0_tmp; + wire vidin_new_data_scld_4_1to0_tmp; + reg[2:0] counter_out_tmp; + reg[7:0] v_corr_20_tmp0; + reg[7:0] v_corr_20_tmp1; + reg[7:0] v_corr_20_tmp2; + reg[7:0] v_corr_20_tmp3; + reg[7:0] v_corr_20_tmp4; + reg[7:0] v_corr_20_tmp5; + reg[7:0] v_corr_20_tmp6; + reg[7:0] v_corr_20_tmp7; + reg[7:0] v_corr_20_tmp8; + reg[7:0] v_corr_20_tmp9; + reg[7:0] v_corr_20_tmp10; + reg[7:0] v_corr_20_tmp11; + reg[7:0] v_corr_20_tmp12; + reg[7:0] v_corr_20_tmp13; + reg[7:0] v_corr_20_tmp14; + reg[7:0] v_corr_20_tmp15; + reg[7:0] v_corr_20_tmp16; + reg[7:0] v_corr_20_tmp17; + reg[7:0] v_corr_20_tmp18; + reg[7:0] v_corr_20_tmp19; + reg[7:0] v_corr_20_tmp20; + reg[7:0] v_corr_10_tmp0; + reg[7:0] v_corr_10_tmp1; + reg[7:0] v_corr_10_tmp2; + reg[7:0] v_corr_10_tmp3; + reg[7:0] v_corr_10_tmp4; + reg[7:0] v_corr_10_tmp5; + reg[7:0] v_corr_10_tmp6; + reg[7:0] v_corr_10_tmp7; + reg[7:0] v_corr_10_tmp8; + reg[7:0] v_corr_10_tmp9; + reg[7:0] v_corr_10_tmp10; + reg[7:0] v_corr_5_tmp0; + reg[7:0] v_corr_5_tmp1; + reg[7:0] v_corr_5_tmp2; + reg[7:0] v_corr_5_tmp3; + reg[7:0] v_corr_5_tmp4; + reg[7:0] v_corr_5_tmp5; + + always @(posedge clk) + begin + case (counter_out_tmp[2:0]) + 3'b001 : + begin + vidin_addr_reg_tmp[7:0] <= bus_word_1_tmp ; + vidin_addr_reg_tmp[15:8] <= bus_word_2_tmp ; + vidin_addr_reg_tmp[18:16] <= bus_word_3_tmp[7:5] ; + svid_comp_switch_tmp <= bus_word_3_tmp[4] ; + v_corr_5_tmp0 <= bus_word_4_tmp ; + v_corr_5_tmp1 <= bus_word_5_tmp ; + v_corr_5_tmp2 <= bus_word_6_tmp ; + end + 3'b010 : + begin + v_corr_5_tmp3 <= bus_word_1_tmp ; + v_corr_5_tmp4 <= bus_word_2_tmp ; + v_corr_5_tmp5 <= bus_word_3_tmp ; + v_corr_10_tmp0 <= bus_word_4_tmp ; + v_corr_10_tmp1 <= bus_word_5_tmp ; + v_corr_10_tmp2 <= bus_word_6_tmp ; + end + 3'b011 : + begin + v_corr_10_tmp3 <= bus_word_1_tmp ; + v_corr_10_tmp4 <= bus_word_2_tmp ; + v_corr_10_tmp5 <= bus_word_3_tmp ; + v_corr_10_tmp6 <= bus_word_4_tmp ; + v_corr_10_tmp7 <= bus_word_5_tmp ; + v_corr_10_tmp8 <= bus_word_6_tmp ; + end + 3'b100 : + begin + v_corr_10_tmp9 <= bus_word_1_tmp ; + v_corr_10_tmp10 <= bus_word_2_tmp ; + v_corr_20_tmp0 <= bus_word_3_tmp ; + v_corr_20_tmp1 <= bus_word_4_tmp ; + v_corr_20_tmp2 <= bus_word_5_tmp ; + v_corr_20_tmp3 <= bus_word_6_tmp ; + end + 3'b101 : + begin + v_corr_20_tmp4 <= bus_word_1_tmp ; + v_corr_20_tmp5 <= bus_word_2_tmp ; + v_corr_20_tmp6 <= bus_word_3_tmp ; + v_corr_20_tmp7 <= bus_word_4_tmp ; + v_corr_20_tmp8 <= bus_word_5_tmp ; + v_corr_20_tmp9 <= bus_word_6_tmp ; + end + 3'b110 : + begin + v_corr_20_tmp10 <= bus_word_1_tmp ; + v_corr_20_tmp11 <= bus_word_2_tmp ; + v_corr_20_tmp12 <= bus_word_3_tmp ; + v_corr_20_tmp13 <= bus_word_4_tmp ; + v_corr_20_tmp14 <= bus_word_5_tmp ; + v_corr_20_tmp15 <= bus_word_6_tmp ; + end + 3'b111 : + begin + v_corr_20_tmp16 <= bus_word_1_tmp ; + v_corr_20_tmp17 <= bus_word_2_tmp ; + v_corr_20_tmp18 <= bus_word_3_tmp ; + v_corr_20_tmp19 <= bus_word_4_tmp ; + v_corr_20_tmp20 <= bus_word_5_tmp ; + end + default : + begin + v_corr_20_tmp16 <= bus_word_1_tmp ; + v_corr_20_tmp17 <= bus_word_2_tmp ; + v_corr_20_tmp18 <= bus_word_3_tmp ; + v_corr_20_tmp19 <= bus_word_4_tmp ; + v_corr_20_tmp20 <= bus_word_5_tmp ; + end + endcase + end + + always @(posedge clk) + begin + counter_out_tmp <= counter_out ; + bus_word_1_tmp <= bus_word_1 ; + bus_word_2_tmp <= bus_word_2 ; + bus_word_3_tmp <= bus_word_3 ; + bus_word_4_tmp <= bus_word_4 ; + bus_word_5_tmp <= bus_word_5 ; + bus_word_6_tmp <= bus_word_6 ; + end + + always @(posedge clk) + begin + if (counter_out_tmp == 3'b001) + begin + vidin_addr_reg <= vidin_addr_reg_tmp ; + svid_comp_switch <= svid_comp_switch_tmp ; + if (vidin_addr_reg_tmp[8:0] != 9'b000000000) + begin + vidin_new_data_scld_1_1to0 <= 1'b1 ; + if ((vidin_addr_reg_tmp[0]) == 1'b0 & (vidin_addr_reg_tmp[9]) == 1'b0) + begin + vidin_new_data_scld_2_1to0 <= 1'b1 ; + if ((vidin_addr_reg_tmp[1]) == 1'b0 & (vidin_addr_reg_tmp[10]) == 1'b0) + begin + vidin_new_data_scld_4_1to0 <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_2_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_1_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + vidin_new_data_scld_2_1to0 <= 1'b0 ; + end + v_corr_50 <= v_corr_5_tmp0 ; + v_corr_51 <= v_corr_5_tmp1 ; + v_corr_52 <= v_corr_5_tmp2 ; + v_corr_53 <= v_corr_5_tmp3 ; + v_corr_54 <= v_corr_5_tmp4 ; + v_corr_55 <= v_corr_5_tmp5 ; + v_corr_100 <= v_corr_10_tmp0 ; + v_corr_101 <= v_corr_10_tmp1 ; + v_corr_102 <= v_corr_10_tmp2 ; + v_corr_103 <= v_corr_10_tmp3 ; + v_corr_104 <= v_corr_10_tmp4 ; + v_corr_105 <= v_corr_10_tmp5 ; + v_corr_106 <= v_corr_10_tmp6 ; + v_corr_107 <= v_corr_10_tmp7 ; + v_corr_108 <= v_corr_10_tmp8 ; + v_corr_109 <= v_corr_10_tmp9 ; + v_corr_1010 <= v_corr_10_tmp10 ; + v_corr_200 <= v_corr_20_tmp0 ; + v_corr_201 <= v_corr_20_tmp1 ; + v_corr_202 <= v_corr_20_tmp2 ; + v_corr_203 <= v_corr_20_tmp3 ; + v_corr_204 <= v_corr_20_tmp4 ; + v_corr_205 <= v_corr_20_tmp5 ; + v_corr_206 <= v_corr_20_tmp6 ; + v_corr_207 <= v_corr_20_tmp7 ; + v_corr_208 <= v_corr_20_tmp8 ; + v_corr_209 <= v_corr_20_tmp9 ; + v_corr_2010 <= v_corr_20_tmp10 ; + v_corr_2011 <= v_corr_20_tmp11 ; + v_corr_2012 <= v_corr_20_tmp12 ; + v_corr_2013 <= v_corr_20_tmp13 ; + v_corr_2014 <= v_corr_20_tmp14 ; + v_corr_2015 <= v_corr_20_tmp15 ; + v_corr_2016 <= v_corr_20_tmp16 ; + v_corr_2017 <= v_corr_20_tmp17 ; + v_corr_2018 <= v_corr_20_tmp18 ; + v_corr_2019 <= v_corr_20_tmp19 ; + v_corr_2020 <= v_corr_20_tmp20 ; + end + else + begin + vidin_new_data_scld_1_1to0 <= 1'b0 ; + vidin_new_data_scld_2_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end +endmodule + + + +module my_fifo_496 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + // Fifo size log(FIFO_SIZE)/log2 + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_316 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_2 (clk, din, dout, rdy); + + + input clk; + input[9 - 1:0] din; + output[9 - 1:0] dout; + reg[9 - 1:0] dout; + input rdy; + + reg[9-1:0]buff1; + reg[9-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_1 (clk, din, dout, rdy); + + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_89 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_179 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_359 (clk, din, dout, rdy); + + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v new file mode 100755 index 000000000..5a9765831 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v @@ -0,0 +1,2553 @@ +// created by Ahmad darabiha +// last updated Aug. 2002 +// this is the design for chip #1 of stereo +// vision system. this chip mainly performs the +// normalization and correlation in two orienations +// and 3 scales. + + +module sv_chip1_hierarchy_no_mem ( + tm3_clk_v0, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1, + bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, + counter_out_1to0,q, offchip_sram_data_in, offchip_sram_addr, offchip_sram_data_out, offchip_sram_we, offchip_sram_oe, rst +); + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + input rst; + input tm3_clk_v0; + wire[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + output q; + assign q = |tm3_sram_data_in; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + + reg tm3_sram_adsp; + input[15:0] bus_word_3_2to1; + input[15:0] bus_word_4_2to1; + input[15:0] bus_word_5_2to1; + input[15:0] bus_word_6_2to1; + input[2:0] counter_out_2to1; + output[7:0] bus_word_1_1to0; + wire[7:0] bus_word_1_1to0; + output[7:0] bus_word_2_1to0; + wire[7:0] bus_word_2_1to0; + output[7:0] bus_word_3_1to0; + wire[7:0] bus_word_3_1to0; + output[7:0] bus_word_4_1to0; + wire[7:0] bus_word_4_1to0; + output[7:0] bus_word_5_1to0; + wire[7:0] bus_word_5_1to0; + output[7:0] bus_word_6_1to0; + wire[7:0] bus_word_6_1to0; + output[2:0] counter_out_1to0; + wire[2:0] counter_out_1to0; + + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[63:0] vidin_data_buf_sc_2; + reg[55:0] vidin_data_buf_2_sc_2; + reg[18:0] vidin_addr_buf_sc_2; + reg[63:0] vidin_data_buf_sc_4; + reg[55:0] vidin_data_buf_2_sc_4; + reg[18:0] vidin_addr_buf_sc_4; + reg video_state; + + reg vidin_new_data_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_left_reg; + reg vidin_new_data_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_left_reg; + reg vidin_new_data_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_left_reg; + reg vidin_new_data_scld_1_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_right_reg; + reg vidin_new_data_scld_2_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_right_reg; + reg vidin_new_data_scld_4_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_right_reg; + reg[18:0] vidin_addr_reg_2to3_reg; + wire vidin_new_data_scld_1_2to3_left; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_1_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_1_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_1_2to3_left_in; + wire vidin_new_data_scld_2_2to3_left; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_2_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_2_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_2_2to3_left_in; + wire vidin_new_data_scld_4_2to3_left; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_4_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_4_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_4_2to3_left_in; + wire vidin_new_data_scld_1_2to3_right; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_1_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_1_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_1_2to3_right_in; + wire vidin_new_data_scld_2_2to3_right; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_2_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_2_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_2_2to3_right_in; + wire vidin_new_data_scld_4_2to3_right; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_4_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_4_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_4_2to3_right_in; + wire[18:0] vidin_addr_reg_2to3; + wire svid_comp_switch_2to3; + wire[15:0] corr_out_1_p0; + wire[15:0] corr_out_1_p1; + wire[15:0] corr_out_1_p2; + wire[15:0] corr_out_1_p3; + wire[15:0] corr_out_1_p4; + wire[15:0] corr_out_1_p5; + wire[15:0] corr_out_1_p6; + wire[15:0] corr_out_1_p7; + wire[15:0] corr_out_1_p8; + wire[15:0] corr_out_1_p9; + wire[15:0] corr_out_1_p10; + wire[15:0] corr_out_1_p11; + wire[15:0] corr_out_1_p12; + wire[15:0] corr_out_1_p13; + wire[15:0] corr_out_1_p14; + wire[15:0] corr_out_1_p15; + wire[15:0] corr_out_1_p16; + wire[15:0] corr_out_1_p17; + wire[15:0] corr_out_1_p18; + wire[15:0] corr_out_1_p19; + wire[15:0] corr_out_1_p20; + wire[15:0] corr_out_1_n0; + wire[15:0] corr_out_1_n1; + wire[15:0] corr_out_1_n2; + wire[15:0] corr_out_1_n3; + wire[15:0] corr_out_1_n4; + wire[15:0] corr_out_1_n5; + wire[15:0] corr_out_1_n6; + wire[15:0] corr_out_1_n7; + wire[15:0] corr_out_1_n8; + wire[15:0] corr_out_1_n9; + wire[15:0] corr_out_1_n10; + wire[15:0] corr_out_1_n11; + wire[15:0] corr_out_1_n12; + wire[15:0] corr_out_1_n13; + wire[15:0] corr_out_1_n14; + wire[15:0] corr_out_1_n15; + wire[15:0] corr_out_1_n16; + wire[15:0] corr_out_1_n17; + wire[15:0] corr_out_1_n18; + wire[15:0] corr_out_1_n19; + wire[15:0] corr_out_1_n20; + reg[17:0] corr_out_10; + reg[17:0] corr_out_11; + reg[17:0] corr_out_12; + reg[17:0] corr_out_13; + reg[17:0] corr_out_14; + reg[17:0] corr_out_15; + reg[17:0] corr_out_16; + reg[17:0] corr_out_17; + reg[17:0] corr_out_18; + reg[17:0] corr_out_19; + reg[17:0] corr_out_110; + reg[17:0] corr_out_111; + reg[17:0] corr_out_112; + reg[17:0] corr_out_113; + reg[17:0] corr_out_114; + reg[17:0] corr_out_115; + reg[17:0] corr_out_116; + reg[17:0] corr_out_117; + reg[17:0] corr_out_118; + reg[17:0] corr_out_119; + reg[17:0] corr_out_120; + wire[15:0] corr_out_2_p0; + wire[15:0] corr_out_2_p1; + wire[15:0] corr_out_2_p2; + wire[15:0] corr_out_2_p3; + wire[15:0] corr_out_2_p4; + wire[15:0] corr_out_2_p5; + wire[15:0] corr_out_2_p6; + wire[15:0] corr_out_2_p7; + wire[15:0] corr_out_2_p8; + wire[15:0] corr_out_2_p9; + wire[15:0] corr_out_2_p10; + wire[15:0] corr_out_2_n0; + wire[15:0] corr_out_2_n1; + wire[15:0] corr_out_2_n2; + wire[15:0] corr_out_2_n3; + wire[15:0] corr_out_2_n4; + wire[15:0] corr_out_2_n5; + wire[15:0] corr_out_2_n6; + wire[15:0] corr_out_2_n7; + wire[15:0] corr_out_2_n8; + wire[15:0] corr_out_2_n9; + wire[15:0] corr_out_2_n10; + reg[17:0] corr_out_20; + reg[17:0] corr_out_21; + reg[17:0] corr_out_22; + reg[17:0] corr_out_23; + reg[17:0] corr_out_24; + reg[17:0] corr_out_25; + reg[17:0] corr_out_26; + reg[17:0] corr_out_27; + reg[17:0] corr_out_28; + reg[17:0] corr_out_29; + reg[17:0] corr_out_210; + wire[15:0] corr_out_4_p0; + wire[15:0] corr_out_4_p1; + wire[15:0] corr_out_4_p2; + wire[15:0] corr_out_4_p3; + wire[15:0] corr_out_4_p4; + wire[15:0] corr_out_4_p5; + wire[15:0] corr_out_4_n0; + wire[15:0] corr_out_4_n1; + wire[15:0] corr_out_4_n2; + wire[15:0] corr_out_4_n3; + wire[15:0] corr_out_4_n4; + wire[15:0] corr_out_4_n5; + reg[17:0] corr_out_40; + reg[17:0] corr_out_41; + reg[17:0] corr_out_42; + reg[17:0] corr_out_43; + reg[17:0] corr_out_44; + reg[17:0] corr_out_45; + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + port_bus_2to1_1 port_bus_2to1_1_inst (tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, vidin_data_reg_scld_1_2to3_left_rn, + vidin_data_reg_scld_1_2to3_left_in, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_left_rp, + vidin_data_reg_scld_2_2to3_left_ip, vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, + vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, vidin_new_data_scld_1_2to3_right, + vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_new_data_scld_2_2to3_right, vidin_data_reg_scld_2_2to3_right_rp, + vidin_data_reg_scld_2_2to3_right_ip, vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_new_data_scld_4_2to3_right, vidin_data_reg_scld_4_2to3_right_rp, vidin_data_reg_scld_4_2to3_right_ip, + vidin_data_reg_scld_4_2to3_right_rn, vidin_data_reg_scld_4_2to3_right_in, bus_word_3_2to1, bus_word_4_2to1, + bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1, rst); + + wrapper_norm_corr_20 wrapper_norm_corr_20_inst_p( + tm3_clk_v0, vidin_new_data_scld_1_2to3_left, vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_left_rp, + vidin_data_reg_scld_1_2to3_left_ip, corr_out_1_p0, corr_out_1_p1, corr_out_1_p2, corr_out_1_p3, corr_out_1_p4, corr_out_1_p5, corr_out_1_p6, + corr_out_1_p7, corr_out_1_p8, corr_out_1_p9, corr_out_1_p10, corr_out_1_p11, corr_out_1_p12, corr_out_1_p13, corr_out_1_p14, corr_out_1_p15, + corr_out_1_p16, corr_out_1_p17, corr_out_1_p18, corr_out_1_p19, corr_out_1_p20 + ); + + wrapper_norm_corr_20 wrapper_norm_corr_20_inst_n(tm3_clk_v0, vidin_new_data_scld_1_2to3_left, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, corr_out_1_n0, + corr_out_1_n1, corr_out_1_n2, corr_out_1_n3, corr_out_1_n4, corr_out_1_n5, corr_out_1_n6, corr_out_1_n7, corr_out_1_n8, + corr_out_1_n9, corr_out_1_n10, corr_out_1_n11, corr_out_1_n12, corr_out_1_n13, corr_out_1_n14, corr_out_1_n15, corr_out_1_n16, + corr_out_1_n17, corr_out_1_n18, corr_out_1_n19, corr_out_1_n20 + ); + + wrapper_norm_corr_10 wrapper_norm_corr_10_inst_p(tm3_clk_v0, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_right_rp, + vidin_data_reg_scld_2_2to3_right_ip, vidin_data_reg_scld_2_2to3_left_rp, vidin_data_reg_scld_2_2to3_left_ip, corr_out_2_p0, + corr_out_2_p1, corr_out_2_p2, corr_out_2_p3, corr_out_2_p4, corr_out_2_p5, corr_out_2_p6, corr_out_2_p7, corr_out_2_p8, + corr_out_2_p9, corr_out_2_p10 + ); + + wrapper_norm_corr_10 wrapper_norm_corr_10_inst_n(tm3_clk_v0, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_right_rn, + vidin_data_reg_scld_2_2to3_right_in, vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, corr_out_2_n0, + corr_out_2_n1, corr_out_2_n2, corr_out_2_n3, corr_out_2_n4, corr_out_2_n5, corr_out_2_n6, corr_out_2_n7, corr_out_2_n8, + corr_out_2_n9, corr_out_2_n10 + ); + + wrapper_norm_corr_5_seq wrapper_norm_corr_5_inst_p(tm3_clk_v0, vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_right_rp, + vidin_data_reg_scld_4_2to3_right_ip, vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, corr_out_4_p0, + corr_out_4_p1, corr_out_4_p2, corr_out_4_p3, corr_out_4_p4, corr_out_4_p5 + ); + + wrapper_norm_corr_5_seq wrapper_norm_corr_5_inst_n(tm3_clk_v0, vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_right_rn, + vidin_data_reg_scld_4_2to3_right_in, vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, corr_out_4_n0, + corr_out_4_n1, corr_out_4_n2, corr_out_4_n3, corr_out_4_n4, corr_out_4_n5); + + port_bus_1to0 port_bus_1to0_inst(tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, vidin_new_data_scld_1_2to3_left, + {corr_out_40[17], corr_out_40[15:9]}, {corr_out_41[17], corr_out_41[15:9]}, {corr_out_42[17], corr_out_42[15:9]}, + {corr_out_43[17], corr_out_43[15:9]}, {corr_out_44[17], corr_out_44[15:9]}, {corr_out_45[17], corr_out_45[15:9]}, + {corr_out_20[17], corr_out_20[15:9]}, {corr_out_21[17], corr_out_21[15:9]}, {corr_out_22[17], corr_out_22[15:9]}, + {corr_out_23[17], corr_out_23[15:9]}, {corr_out_24[17], corr_out_24[15:9]}, {corr_out_25[17], corr_out_25[15:9]}, + {corr_out_26[17], corr_out_26[15:9]}, {corr_out_27[17], corr_out_27[15:9]}, {corr_out_28[17], corr_out_28[15:9]}, + {corr_out_29[17], corr_out_29[15:9]}, {corr_out_210[17], corr_out_210[15:9]}, {corr_out_10[17], corr_out_10[15:9]}, + {corr_out_11[17], corr_out_11[15:9]}, {corr_out_12[17], corr_out_12[15:9]}, {corr_out_13[17], corr_out_13[15:9]}, + {corr_out_14[17], corr_out_14[15:9]}, {corr_out_15[17], corr_out_15[15:9]}, {corr_out_16[17], corr_out_16[15:9]}, + {corr_out_17[17], corr_out_17[15:9]}, {corr_out_18[17], corr_out_18[15:9]}, {corr_out_19[17], corr_out_19[15:9]}, + {corr_out_110[17], corr_out_110[15:9]}, {corr_out_111[17], corr_out_111[15:9]}, {corr_out_112[17], corr_out_112[15:9]}, + {corr_out_113[17], corr_out_113[15:9]}, {corr_out_114[17], corr_out_114[15:9]}, {corr_out_115[17], corr_out_115[15:9]}, + {corr_out_116[17], corr_out_116[15:9]}, {corr_out_117[17], corr_out_117[15:9]}, {corr_out_118[17], corr_out_118[15:9]}, + {corr_out_119[17], corr_out_119[15:9]}, {corr_out_120[17], corr_out_120[15:9]}, bus_word_1_1to0, bus_word_2_1to0, + bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0, rst); + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + corr_out_10 <= ({ corr_out_1_p0[15], corr_out_1_p0[15], corr_out_1_p0}) + ({corr_out_1_n0[15], corr_out_1_n0[15], corr_out_1_n0}) ; + corr_out_11 <= ({ corr_out_1_p1[15], corr_out_1_p1[15], corr_out_1_p1}) + ({corr_out_1_n1[15], corr_out_1_n1[15], corr_out_1_n1}) ; + corr_out_12 <= ({ corr_out_1_p2[15], corr_out_1_p2[15], corr_out_1_p2}) + ({corr_out_1_n2[15], corr_out_1_n2[15], corr_out_1_n2}) ; + corr_out_13 <= ({ corr_out_1_p3[15], corr_out_1_p3[15], corr_out_1_p3}) + ({corr_out_1_n3[15], corr_out_1_n3[15], corr_out_1_n3}) ; + corr_out_14 <= ({ corr_out_1_p4[15], corr_out_1_p4[15], corr_out_1_p4}) + ({corr_out_1_n4[15], corr_out_1_n4[15], corr_out_1_n4}) ; + corr_out_15 <= ({ corr_out_1_p5[15], corr_out_1_p5[15], corr_out_1_p5}) + ({corr_out_1_n5[15], corr_out_1_n5[15], corr_out_1_n5}) ; + corr_out_16 <= ({ corr_out_1_p6[15], corr_out_1_p6[15], corr_out_1_p6}) + ({corr_out_1_n6[15], corr_out_1_n6[15], corr_out_1_n6}) ; + corr_out_17 <= ({ corr_out_1_p7[15], corr_out_1_p7[15], corr_out_1_p7}) + ({corr_out_1_n7[15], corr_out_1_n7[15], corr_out_1_n7}) ; + corr_out_18 <= ({ corr_out_1_p8[15], corr_out_1_p8[15], corr_out_1_p8}) + ({corr_out_1_n8[15], corr_out_1_n8[15], corr_out_1_n8}) ; + corr_out_19 <= ({ corr_out_1_p9[15], corr_out_1_p9[15], corr_out_1_p9}) + ({corr_out_1_n9[15], corr_out_1_n9[15], corr_out_1_n9}) ; + corr_out_110 <= ({ corr_out_1_p10[15], corr_out_1_p10[15], corr_out_1_p10}) + ({corr_out_1_n10[15], corr_out_1_n10[15], corr_out_1_n10}) ; + corr_out_111 <= ({ corr_out_1_p11[15], corr_out_1_p11[15], corr_out_1_p11}) + ({corr_out_1_n11[15], corr_out_1_n11[15], corr_out_1_n11}) ; + corr_out_112 <= ({ corr_out_1_p12[15], corr_out_1_p12[15], corr_out_1_p12}) + ({corr_out_1_n12[15], corr_out_1_n12[15], corr_out_1_n12}) ; + corr_out_113 <= ({ corr_out_1_p13[15], corr_out_1_p13[15], corr_out_1_p13}) + ({corr_out_1_n13[15], corr_out_1_n13[15], corr_out_1_n13}) ; + corr_out_114 <= ({ corr_out_1_p14[15], corr_out_1_p14[15], corr_out_1_p14}) + ({corr_out_1_n14[15], corr_out_1_n14[15], corr_out_1_n14}) ; + corr_out_115 <= ({ corr_out_1_p15[15], corr_out_1_p15[15], corr_out_1_p15}) + ({corr_out_1_n15[15], corr_out_1_n15[15], corr_out_1_n15}) ; + corr_out_116 <= ({ corr_out_1_p16[15], corr_out_1_p16[15], corr_out_1_p16}) + ({corr_out_1_n16[15], corr_out_1_n16[15], corr_out_1_n16}) ; + corr_out_117 <= ({ corr_out_1_p17[15], corr_out_1_p17[15], corr_out_1_p17}) + ({corr_out_1_n17[15], corr_out_1_n17[15], corr_out_1_n17}) ; + corr_out_118 <= ({ corr_out_1_p18[15], corr_out_1_p18[15], corr_out_1_p18}) + ({corr_out_1_n18[15], corr_out_1_n18[15], corr_out_1_n18}) ; + corr_out_119 <= ({ corr_out_1_p19[15], corr_out_1_p19[15], corr_out_1_p19}) + ({corr_out_1_n19[15], corr_out_1_n19[15], corr_out_1_n19}) ; + corr_out_120 <= ({ corr_out_1_p20[15], corr_out_1_p20[15], corr_out_1_p20}) + ({corr_out_1_n20[15], corr_out_1_n20[15], corr_out_1_n20}) ; + end + else + begin + corr_out_10 <= corr_out_10; + corr_out_11 <= corr_out_11; + corr_out_12 <= corr_out_12; + corr_out_13 <= corr_out_13; + corr_out_14 <= corr_out_14; + corr_out_15 <= corr_out_15; + corr_out_16 <= corr_out_16; + corr_out_17 <= corr_out_17; + corr_out_18 <= corr_out_18; + corr_out_19 <= corr_out_19; + corr_out_110 <= corr_out_110; + corr_out_111 <= corr_out_111; + corr_out_112 <= corr_out_112; + corr_out_113 <= corr_out_113; + corr_out_114 <= corr_out_114; + corr_out_115 <= corr_out_115; + corr_out_116 <= corr_out_116; + corr_out_117 <= corr_out_117; + corr_out_118 <= corr_out_118; + corr_out_119 <= corr_out_119; + corr_out_120 <= corr_out_120; + end + end + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_2_2to3_left == 1'b1) + begin + corr_out_20 <= ({ corr_out_2_p0[15], corr_out_2_p0[15], corr_out_2_p0}) + ({corr_out_2_n0[15], corr_out_2_n0[15], corr_out_2_n0}) ; + corr_out_21 <= ({ corr_out_2_p1[15], corr_out_2_p1[15], corr_out_2_p1}) + ({corr_out_2_n1[15], corr_out_2_n1[15], corr_out_2_n1}) ; + corr_out_22 <= ({ corr_out_2_p2[15], corr_out_2_p2[15], corr_out_2_p2}) + ({corr_out_2_n2[15], corr_out_2_n2[15], corr_out_2_n2}) ; + corr_out_23 <= ({ corr_out_2_p3[15], corr_out_2_p3[15], corr_out_2_p3}) + ({corr_out_2_n3[15], corr_out_2_n3[15], corr_out_2_n3}) ; + corr_out_24 <= ({ corr_out_2_p4[15], corr_out_2_p4[15], corr_out_2_p4}) + ({corr_out_2_n4[15], corr_out_2_n4[15], corr_out_2_n4}) ; + corr_out_25 <= ({ corr_out_2_p5[15], corr_out_2_p5[15], corr_out_2_p5}) + ({corr_out_2_n5[15], corr_out_2_n5[15], corr_out_2_n5}) ; + corr_out_26 <= ({ corr_out_2_p6[15], corr_out_2_p6[15], corr_out_2_p6}) + ({corr_out_2_n6[15], corr_out_2_n6[15], corr_out_2_n6}) ; + corr_out_27 <= ({ corr_out_2_p7[15], corr_out_2_p7[15], corr_out_2_p7}) + ({corr_out_2_n7[15], corr_out_2_n7[15], corr_out_2_n7}) ; + corr_out_28 <= ({ corr_out_2_p8[15], corr_out_2_p8[15], corr_out_2_p8}) + ({corr_out_2_n8[15], corr_out_2_n8[15], corr_out_2_n8}) ; + corr_out_29 <= ({ corr_out_2_p9[15], corr_out_2_p9[15], corr_out_2_p9}) + ({corr_out_2_n9[15], corr_out_2_n9[15], corr_out_2_n9}) ; + corr_out_210 <= ({ corr_out_2_p10[15], corr_out_2_p10[15], corr_out_2_p10}) + ({corr_out_2_n10[15], corr_out_2_n10[15], corr_out_2_n10}) ; + end + else + begin + corr_out_20 <= corr_out_20; + corr_out_21 <= corr_out_21; + corr_out_22 <= corr_out_22; + corr_out_23 <= corr_out_23; + corr_out_24 <= corr_out_24; + corr_out_25 <= corr_out_25; + corr_out_26 <= corr_out_26; + corr_out_27 <= corr_out_27; + corr_out_28 <= corr_out_28; + corr_out_29 <= corr_out_29; + corr_out_210 <= corr_out_210; + end + end + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_2_2to3_left == 1'b1) + begin + corr_out_40 <= ({ corr_out_4_p0[15], corr_out_4_p0[15], corr_out_4_p0}) + ({corr_out_4_n0[15], corr_out_4_n0[15], corr_out_4_n0}) ; + corr_out_41 <= ({ corr_out_4_p1[15], corr_out_4_p1[15], corr_out_4_p1}) + ({corr_out_4_n1[15], corr_out_4_n1[15], corr_out_4_n1}) ; + corr_out_42 <= ({ corr_out_4_p2[15], corr_out_4_p2[15], corr_out_4_p2}) + ({corr_out_4_n2[15], corr_out_4_n2[15], corr_out_4_n2}) ; + corr_out_43 <= ({ corr_out_4_p3[15], corr_out_4_p3[15], corr_out_4_p3}) + ({corr_out_4_n3[15], corr_out_4_n3[15], corr_out_4_n3}) ; + corr_out_44 <= ({ corr_out_4_p4[15], corr_out_4_p4[15], corr_out_4_p4}) + ({corr_out_4_n4[15], corr_out_4_n4[15], corr_out_4_n4}) ; + corr_out_45 <= ({ corr_out_4_p5[15], corr_out_4_p5[15], corr_out_4_p5}) + ({corr_out_4_n5[15], corr_out_4_n5[15], corr_out_4_n5}) ; + end + else + begin + corr_out_40 <= corr_out_40; + corr_out_41 <= corr_out_41; + corr_out_42 <= corr_out_42; + corr_out_43 <= corr_out_43; + corr_out_44 <= corr_out_44; + corr_out_45 <= corr_out_45; + end + end + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1_2to3_left_reg <= vidin_new_data_scld_1_2to3_left ; + vidin_data_reg_scld_1_2to3_left_reg <= vidin_data_reg_scld_1_2to3_left_rp[15:8] ; + vidin_new_data_scld_2_2to3_left_reg <= vidin_new_data_scld_2_2to3_left ; + vidin_data_reg_scld_2_2to3_left_reg <= vidin_data_reg_scld_2_2to3_left_rp[15:8] ; + vidin_new_data_scld_4_2to3_left_reg <= vidin_new_data_scld_4_2to3_left ; + vidin_data_reg_scld_4_2to3_left_reg <= vidin_data_reg_scld_4_2to3_left_rp[15:8] ; + vidin_new_data_scld_1_2to3_right_reg <= vidin_new_data_scld_1_2to3_right ; + vidin_data_reg_scld_1_2to3_right_reg <= vidin_data_reg_scld_1_2to3_right_rp[15:8] ; + vidin_new_data_scld_2_2to3_right_reg <= vidin_new_data_scld_2_2to3_right ; + vidin_data_reg_scld_2_2to3_right_reg <= vidin_data_reg_scld_2_2to3_right_rp[15:8] ; + vidin_new_data_scld_4_2to3_right_reg <= vidin_new_data_scld_4_2to3_right ; + vidin_data_reg_scld_4_2to3_right_reg <= vidin_data_reg_scld_4_2to3_right_rp[15:8] ; + vidin_addr_reg_2to3_reg <= vidin_addr_reg_2to3 ; + end + + always @(posedge tm3_clk_v0) + begin + if (rst) + begin + horiz <= 10'b0000000000; + vert <= 10'b0000000000; + video_state <= 1'b0; + tm3_sram_adsp <= 1'b0; + vidin_data_buf_2_sc_1 <= 0; + vidin_data_buf_2_sc_2 <= 0; + vidin_data_buf_2_sc_4 <= 0; + vidin_addr_buf_sc_1 <= 19'b0; + vidin_addr_buf_sc_2 <= 19'b0; + vidin_addr_buf_sc_4 <= 19'b0; + end + else + begin + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + tm3_sram_adsp <= 1'b1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_data_xhdl0 <= 64'b0000000000000000000000000000000000000000000000000000000000000000; + tm3_sram_oe <= 2'b11 ; + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_2[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_2 ; + end + 3'b100 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_4[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_4 ; + end + 3'b111 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + default : + begin + tm3_sram_addr <= 19'b0000000000000000000 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 64'b0000000000000000000000000000000000000000000000000000000000000000; + end + endcase + end + if (vidin_new_data_scld_1_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[2:0]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + + 4'b0101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_left_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_right_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + endcase + end + if (vidin_new_data_scld_2_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[3:1]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0100 : + + begin + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_left_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_addr_buf_sc_2 <= {4'b0000, svid_comp_switch_2to3, 1'b0, vidin_addr_reg_2to3_reg[16:10], (6'b101101 + ({1'b0, vidin_addr_reg_2to3_reg[8:4]}))} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_right_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_addr_buf_sc_2 <= {4'b0000, svid_comp_switch_2to3, 1'b0, vidin_addr_reg_2to3_reg[16:10], (6'b101101 + ({1'b0, vidin_addr_reg_2to3_reg[8:4]}))} ; + end + endcase + end + if (vidin_new_data_scld_4_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[4:2]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_left_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_4 <= { + 4'b0000, svid_comp_switch_2to3, + (8'b10000000 + ({2'b00, vidin_addr_reg_2to3_reg[16:11]})), + (6'b101101 + ({2'b00, vidin_addr_reg_2to3_reg[8:5]})) + }; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_right_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_4 <= {4'b0000, svid_comp_switch_2to3, (8'b10000000 + ({2'b00, vidin_addr_reg_2to3_reg[16:11]})), (6'b101101 + ({2'b00, vidin_addr_reg_2to3_reg[8:5]}))}; + end + endcase + end + end + end +endmodule +module port_bus_2to1_1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, + vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, + vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_left_rp, + vidin_data_reg_scld_2_2to3_left_ip, vidin_data_reg_scld_2_2to3_left_rn, + vidin_data_reg_scld_2_2to3_left_in, vidin_new_data_scld_4_2to3_left, + vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, + vidin_new_data_scld_1_2to3_right, vidin_data_reg_scld_1_2to3_right_rp, + vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_new_data_scld_2_2to3_right, + vidin_data_reg_scld_2_2to3_right_rp, vidin_data_reg_scld_2_2to3_right_ip, + vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_new_data_scld_4_2to3_right, vidin_data_reg_scld_4_2to3_right_rp, + vidin_data_reg_scld_4_2to3_right_ip, vidin_data_reg_scld_4_2to3_right_rn, + vidin_data_reg_scld_4_2to3_right_in, bus_word_3, bus_word_4, bus_word_5, + bus_word_6, counter_out, rst); + input clk; + input rst; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + output svid_comp_switch; + reg svid_comp_switch; + output vidin_new_data_scld_1_2to3_left; + reg vidin_new_data_scld_1_2to3_left; + output[15:0] vidin_data_reg_scld_1_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp; + output[15:0] vidin_data_reg_scld_1_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip; + output[15:0] vidin_data_reg_scld_1_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn; + output[15:0] vidin_data_reg_scld_1_2to3_left_in; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in; + output vidin_new_data_scld_2_2to3_left; + reg vidin_new_data_scld_2_2to3_left; + output[15:0] vidin_data_reg_scld_2_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp; + output[15:0] vidin_data_reg_scld_2_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip; + output[15:0] vidin_data_reg_scld_2_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn; + output[15:0] vidin_data_reg_scld_2_2to3_left_in; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in; + output vidin_new_data_scld_4_2to3_left; + reg vidin_new_data_scld_4_2to3_left; + output[15:0] vidin_data_reg_scld_4_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp; + output[15:0] vidin_data_reg_scld_4_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip; + output[15:0] vidin_data_reg_scld_4_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn; + output[15:0] vidin_data_reg_scld_4_2to3_left_in; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in; + output vidin_new_data_scld_1_2to3_right; + reg vidin_new_data_scld_1_2to3_right; + output[15:0] vidin_data_reg_scld_1_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp; + output[15:0] vidin_data_reg_scld_1_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip; + output[15:0] vidin_data_reg_scld_1_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn; + output[15:0] vidin_data_reg_scld_1_2to3_right_in; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in; + output vidin_new_data_scld_2_2to3_right; + reg vidin_new_data_scld_2_2to3_right; + output[15:0] vidin_data_reg_scld_2_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp; + output[15:0] vidin_data_reg_scld_2_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip; + output[15:0] vidin_data_reg_scld_2_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn; + output[15:0] vidin_data_reg_scld_2_2to3_right_in; + + reg[15:0] vidin_data_reg_scld_2_2to3_right_in; + output vidin_new_data_scld_4_2to3_right; + reg vidin_new_data_scld_4_2to3_right; + output[15:0] vidin_data_reg_scld_4_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp; + output[15:0] vidin_data_reg_scld_4_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip; + output[15:0] vidin_data_reg_scld_4_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn; + output[15:0] vidin_data_reg_scld_4_2to3_right_in; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in; + input[15:0] bus_word_3; + input[15:0] bus_word_4; + input[15:0] bus_word_5; + input[15:0] bus_word_6; + input[2:0] counter_out; + + reg[15:0] bus_word_3_tmp; + reg[15:0] bus_word_4_tmp; + reg[15:0] bus_word_5_tmp; + reg[15:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; +/* + reg vidin_new_data_scld_1_2to3_left_tmp; + reg vidin_new_data_scld_2_2to3_left_tmp; + reg vidin_new_data_scld_4_2to3_left_tmp; + reg vidin_new_data_scld_1_2to3_right_tmp; + reg vidin_new_data_scld_2_2to3_right_tmp; + reg vidin_new_data_scld_4_2to3_right_tmp; +*/ + reg[2:0] counter_out_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in_tmp; + + always @(posedge clk) + begin + case (counter_out_tmp[2:0]) +// took out noop case 3'b000 + 3'b001 : + begin + vidin_addr_reg_tmp[15:0] <= bus_word_3_tmp ; + vidin_addr_reg_tmp[18:16] <= bus_word_4_tmp[15:13] ; + + svid_comp_switch_tmp <= bus_word_4_tmp[12] ; +/* + vidin_new_data_scld_1_2to3_left_tmp <= bus_word_4_tmp[11] ; + vidin_new_data_scld_2_2to3_left_tmp <= bus_word_4_tmp[10] ; + vidin_new_data_scld_4_2to3_left_tmp <= bus_word_4_tmp[9] ; + vidin_new_data_scld_1_2to3_right_tmp <= bus_word_4_tmp[8] ; + vidin_new_data_scld_2_2to3_right_tmp <= bus_word_4_tmp[7] ; + vidin_new_data_scld_4_2to3_right_tmp <= bus_word_4_tmp[6] ; +*/ + end + 3'b010 : + begin + vidin_data_reg_scld_1_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_1_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_1_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_1_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b011 : + begin + vidin_data_reg_scld_1_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_1_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_1_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_1_2to3_right_in_tmp <= bus_word_6_tmp ; + end + 3'b100 : + begin + vidin_data_reg_scld_2_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_2_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_2_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_2_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b101 : + begin + vidin_data_reg_scld_2_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_2_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_2_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_2_2to3_right_in_tmp <= bus_word_6_tmp ; + end + 3'b110 : + begin + vidin_data_reg_scld_4_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_4_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_4_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_4_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b111 : + begin + vidin_data_reg_scld_4_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_4_2to3_right_in_tmp <= bus_word_6_tmp ; + end + default: + begin + vidin_data_reg_scld_4_2to3_right_rp_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_in_tmp <= 0; + vidin_addr_reg_tmp <= 0; + svid_comp_switch_tmp <=0; + end + endcase + end + + always @(posedge clk) + begin + if (rst) + begin + counter_out_tmp <= 0; + bus_word_3_tmp <= 0; + bus_word_4_tmp <= 0; + bus_word_5_tmp <= 0; + bus_word_6_tmp <= 0; + end + else + begin + counter_out_tmp <= counter_out ; + bus_word_3_tmp <= bus_word_3 ; + bus_word_4_tmp <= bus_word_4 ; + bus_word_5_tmp <= bus_word_5 ; + bus_word_6_tmp <= bus_word_6 ; + end + end + + always @(posedge clk) + begin + if (counter_out_tmp == 3'b001) + begin + vidin_addr_reg <= vidin_addr_reg_tmp ; + svid_comp_switch <= svid_comp_switch_tmp ; + vidin_new_data_scld_1_2to3_left <= 1'b1 ; + if (((vidin_addr_reg_tmp[0]) == 1'b0) && ((vidin_addr_reg_tmp[9]) == 1'b0)) + begin + vidin_new_data_scld_2_2to3_left <= 1'b1 ; + if (((vidin_addr_reg_tmp[1]) == 1'b0) && ((vidin_addr_reg_tmp[10]) == 1'b0)) + begin + vidin_new_data_scld_4_2to3_left <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4_2to3_left <= vidin_new_data_scld_4_2to3_left; + end + end + else + begin + vidin_new_data_scld_2_2to3_left <= vidin_new_data_scld_4_2to3_left ; + vidin_new_data_scld_4_2to3_left <= vidin_new_data_scld_4_2to3_left; + end + vidin_new_data_scld_1_2to3_right <= 1'b1 ; + vidin_new_data_scld_2_2to3_right <= 1'b1 ; + vidin_new_data_scld_4_2to3_right <= 1'b1 ; + vidin_data_reg_scld_1_2to3_left_rp <= vidin_data_reg_scld_1_2to3_left_rp_tmp ; + vidin_data_reg_scld_1_2to3_left_ip <= vidin_data_reg_scld_1_2to3_left_ip_tmp ; + vidin_data_reg_scld_1_2to3_left_rn <= vidin_data_reg_scld_1_2to3_left_rn_tmp ; + vidin_data_reg_scld_1_2to3_left_in <= vidin_data_reg_scld_1_2to3_left_in_tmp ; + vidin_data_reg_scld_2_2to3_left_rp <= vidin_data_reg_scld_2_2to3_left_rp_tmp ; + vidin_data_reg_scld_2_2to3_left_ip <= vidin_data_reg_scld_2_2to3_left_ip_tmp ; + vidin_data_reg_scld_2_2to3_left_rn <= vidin_data_reg_scld_2_2to3_left_rn_tmp ; + vidin_data_reg_scld_2_2to3_left_in <= vidin_data_reg_scld_2_2to3_left_in_tmp ; + vidin_data_reg_scld_4_2to3_left_rp <= vidin_data_reg_scld_4_2to3_left_rp_tmp ; + vidin_data_reg_scld_4_2to3_left_ip <= vidin_data_reg_scld_4_2to3_left_ip_tmp ; + vidin_data_reg_scld_4_2to3_left_rn <= vidin_data_reg_scld_4_2to3_left_rn_tmp ; + vidin_data_reg_scld_4_2to3_left_in <= vidin_data_reg_scld_4_2to3_left_in_tmp ; + vidin_data_reg_scld_1_2to3_right_rp <= vidin_data_reg_scld_1_2to3_right_rp_tmp ; + vidin_data_reg_scld_1_2to3_right_ip <= vidin_data_reg_scld_1_2to3_right_ip_tmp ; + vidin_data_reg_scld_1_2to3_right_rn <= vidin_data_reg_scld_1_2to3_right_rn_tmp ; + vidin_data_reg_scld_1_2to3_right_in <= vidin_data_reg_scld_1_2to3_right_in_tmp ; + vidin_data_reg_scld_2_2to3_right_rp <= vidin_data_reg_scld_2_2to3_right_rp_tmp ; + vidin_data_reg_scld_2_2to3_right_ip <= vidin_data_reg_scld_2_2to3_right_ip_tmp ; + vidin_data_reg_scld_2_2to3_right_rn <= vidin_data_reg_scld_2_2to3_right_rn_tmp ; + vidin_data_reg_scld_2_2to3_right_in <= vidin_data_reg_scld_2_2to3_right_in_tmp ; + vidin_data_reg_scld_4_2to3_right_rp <= vidin_data_reg_scld_4_2to3_right_rp_tmp ; + vidin_data_reg_scld_4_2to3_right_ip <= vidin_data_reg_scld_4_2to3_right_ip_tmp ; + vidin_data_reg_scld_4_2to3_right_rn <= vidin_data_reg_scld_4_2to3_right_rn_tmp ; + vidin_data_reg_scld_4_2to3_right_in <= vidin_data_reg_scld_4_2to3_right_in_tmp ; + end + else + begin + vidin_new_data_scld_1_2to3_left <= 1'b0 ; + vidin_new_data_scld_2_2to3_left <= 1'b0 ; + vidin_new_data_scld_4_2to3_left <= 1'b0 ; + vidin_new_data_scld_1_2to3_right <= 1'b0 ; + vidin_new_data_scld_2_2to3_right <= 1'b0 ; + vidin_new_data_scld_4_2to3_right <= 1'b0 ; + vidin_addr_reg <= vidin_addr_reg; + svid_comp_switch <= svid_comp_switch; + vidin_data_reg_scld_1_2to3_left_rp <= vidin_data_reg_scld_1_2to3_left_rp; + vidin_data_reg_scld_1_2to3_left_ip <= vidin_data_reg_scld_1_2to3_left_ip; + vidin_data_reg_scld_1_2to3_left_rn <= vidin_data_reg_scld_1_2to3_left_rn; + vidin_data_reg_scld_1_2to3_left_in <= vidin_data_reg_scld_1_2to3_left_in; + vidin_data_reg_scld_2_2to3_left_rp <= vidin_data_reg_scld_2_2to3_left_rp; + vidin_data_reg_scld_2_2to3_left_ip <= vidin_data_reg_scld_2_2to3_left_ip; + vidin_data_reg_scld_2_2to3_left_rn <= vidin_data_reg_scld_2_2to3_left_rn; + vidin_data_reg_scld_2_2to3_left_in <= vidin_data_reg_scld_2_2to3_left_in; + vidin_data_reg_scld_4_2to3_left_rp <= vidin_data_reg_scld_4_2to3_left_rp; + vidin_data_reg_scld_4_2to3_left_ip <= vidin_data_reg_scld_4_2to3_left_ip; + vidin_data_reg_scld_4_2to3_left_rn <= vidin_data_reg_scld_4_2to3_left_rn; + vidin_data_reg_scld_4_2to3_left_in <= vidin_data_reg_scld_4_2to3_left_in; + vidin_data_reg_scld_1_2to3_right_rp <= vidin_data_reg_scld_1_2to3_right_rp; + vidin_data_reg_scld_1_2to3_right_ip <= vidin_data_reg_scld_1_2to3_right_ip; + vidin_data_reg_scld_1_2to3_right_rn <= vidin_data_reg_scld_1_2to3_right_rn; + vidin_data_reg_scld_1_2to3_right_in <= vidin_data_reg_scld_1_2to3_right_in; + vidin_data_reg_scld_2_2to3_right_rp <= vidin_data_reg_scld_2_2to3_right_rp; + vidin_data_reg_scld_2_2to3_right_ip <= vidin_data_reg_scld_2_2to3_right_ip; + vidin_data_reg_scld_2_2to3_right_rn <= vidin_data_reg_scld_2_2to3_right_rn; + vidin_data_reg_scld_2_2to3_right_in <= vidin_data_reg_scld_2_2to3_right_in; + vidin_data_reg_scld_4_2to3_right_rp <= vidin_data_reg_scld_4_2to3_right_rp; + vidin_data_reg_scld_4_2to3_right_ip <= vidin_data_reg_scld_4_2to3_right_ip; + vidin_data_reg_scld_4_2to3_right_rn <= vidin_data_reg_scld_4_2to3_right_rn; + vidin_data_reg_scld_4_2to3_right_in <= vidin_data_reg_scld_4_2to3_right_in; + end + end +endmodule + +module wrapper_norm_corr_20 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10, corr_out_11, corr_out_12, corr_out_13, corr_out_14, corr_out_15, corr_out_16, corr_out_17, corr_out_18, corr_out_19, corr_out_20); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + wire[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + wire[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + wire[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + wire[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + wire[2 * sh_reg_w - 1:0] corr_out_10; + output[2 * sh_reg_w - 1:0] corr_out_11; + wire[2 * sh_reg_w - 1:0] corr_out_11; + output[2 * sh_reg_w - 1:0] corr_out_12; + wire[2 * sh_reg_w - 1:0] corr_out_12; + output[2 * sh_reg_w - 1:0] corr_out_13; + wire[2 * sh_reg_w - 1:0] corr_out_13; + output[2 * sh_reg_w - 1:0] corr_out_14; + wire[2 * sh_reg_w - 1:0] corr_out_14; + output[2 * sh_reg_w - 1:0] corr_out_15; + wire[2 * sh_reg_w - 1:0] corr_out_15; + output[2 * sh_reg_w - 1:0] corr_out_16; + wire[2 * sh_reg_w - 1:0] corr_out_16; + output[2 * sh_reg_w - 1:0] corr_out_17; + wire[2 * sh_reg_w - 1:0] corr_out_17; + output[2 * sh_reg_w - 1:0] corr_out_18; + wire[2 * sh_reg_w - 1:0] corr_out_18; + output[2 * sh_reg_w - 1:0] corr_out_19; + wire[2 * sh_reg_w - 1:0] corr_out_19; + output[2 * sh_reg_w - 1:0] corr_out_20; + wire[2 * sh_reg_w - 1:0] corr_out_20; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_20 corr_20_inst(.clk(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5), .corr_out_6(corr_out_6), .corr_out_7(corr_out_7), .corr_out_8(corr_out_8), .corr_out_9(corr_out_9), .corr_out_10(corr_out_10), .corr_out_11(corr_out_11), .corr_out_12(corr_out_12), .corr_out_13(corr_out_13), .corr_out_14(corr_out_14), .corr_out_15(corr_out_15), .corr_out_16(corr_out_16), .corr_out_17(corr_out_17), .corr_out_18(corr_out_18), .corr_out_19(corr_out_19), .corr_out_20(corr_out_20)); +endmodule +module wrapper_corr_20 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10, corr_out_11, corr_out_12, corr_out_13, corr_out_14, corr_out_15, corr_out_16, corr_out_17, corr_out_18, corr_out_19, corr_out_20); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + reg[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + reg[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + reg[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + reg[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + reg[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + reg[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + reg[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + reg[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + reg[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + reg[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + reg[2 * sh_reg_w - 1:0] corr_out_10; + output[2 * sh_reg_w - 1:0] corr_out_11; + reg[2 * sh_reg_w - 1:0] corr_out_11; + output[2 * sh_reg_w - 1:0] corr_out_12; + reg[2 * sh_reg_w - 1:0] corr_out_12; + output[2 * sh_reg_w - 1:0] corr_out_13; + reg[2 * sh_reg_w - 1:0] corr_out_13; + output[2 * sh_reg_w - 1:0] corr_out_14; + reg[2 * sh_reg_w - 1:0] corr_out_14; + output[2 * sh_reg_w - 1:0] corr_out_15; + reg[2 * sh_reg_w - 1:0] corr_out_15; + output[2 * sh_reg_w - 1:0] corr_out_16; + reg[2 * sh_reg_w - 1:0] corr_out_16; + output[2 * sh_reg_w - 1:0] corr_out_17; + reg[2 * sh_reg_w - 1:0] corr_out_17; + output[2 * sh_reg_w - 1:0] corr_out_18; + reg[2 * sh_reg_w - 1:0] corr_out_18; + output[2 * sh_reg_w - 1:0] corr_out_19; + reg[2 * sh_reg_w - 1:0] corr_out_19; + output[2 * sh_reg_w - 1:0] corr_out_20; + reg[2 * sh_reg_w - 1:0] corr_out_20; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_61; + wire[sh_reg_w - 1:0] out_71; + wire[sh_reg_w - 1:0] out_81; + wire[sh_reg_w - 1:0] out_91; + wire[sh_reg_w - 1:0] out_101; + wire[sh_reg_w - 1:0] out_111; + wire[sh_reg_w - 1:0] out_121; + wire[sh_reg_w - 1:0] out_131; + wire[sh_reg_w - 1:0] out_141; + wire[sh_reg_w - 1:0] out_151; + wire[sh_reg_w - 1:0] out_161; + wire[sh_reg_w - 1:0] out_171; + wire[sh_reg_w - 1:0] out_181; + wire[sh_reg_w - 1:0] out_191; + wire[sh_reg_w - 1:0] out_201; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[sh_reg_w - 1:0] out_62; + wire[sh_reg_w - 1:0] out_72; + wire[sh_reg_w - 1:0] out_82; + wire[sh_reg_w - 1:0] out_92; + wire[sh_reg_w - 1:0] out_102; + wire[sh_reg_w - 1:0] out_112; + wire[sh_reg_w - 1:0] out_122; + wire[sh_reg_w - 1:0] out_132; + wire[sh_reg_w - 1:0] out_142; + wire[sh_reg_w - 1:0] out_152; + wire[sh_reg_w - 1:0] out_162; + wire[sh_reg_w - 1:0] out_172; + wire[sh_reg_w - 1:0] out_182; + wire[sh_reg_w - 1:0] out_192; + wire[sh_reg_w - 1:0] out_202; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_6_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_7_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_8_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_9_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_10_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_11_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_12_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_13_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_14_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_15_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_16_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_17_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_18_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_19_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_20_tmp; + + sh_reg inst_sh_reg_r_1(clk, wen, d_r_1, d_r_2, out_r1, out_r2); + sh_reg inst_sh_reg_0(clk, wen, d_l_1, d_l_2, out_01, out_02); + sh_reg inst_sh_reg_1(clk, wen, out_01, out_02, out_11, out_12); + sh_reg inst_sh_reg_2(clk, wen, out_11, out_12, out_21, out_22); + sh_reg inst_sh_reg_3(clk, wen, out_21, out_22, out_31, out_32); + sh_reg inst_sh_reg_4(clk, wen, out_31, out_32, out_41, out_42); + sh_reg inst_sh_reg_5(clk, wen, out_41, out_42, out_51, out_52); + sh_reg inst_sh_reg_6(clk, wen, out_51, out_52, out_61, out_62); + sh_reg inst_sh_reg_7(clk, wen, out_61, out_62, out_71, out_72); + sh_reg inst_sh_reg_8(clk, wen, out_71, out_72, out_81, out_82); + sh_reg inst_sh_reg_9(clk, wen, out_81, out_82, out_91, out_92); + sh_reg inst_sh_reg_10(clk, wen, out_91, out_92, out_101, out_102); + sh_reg inst_sh_reg_11(clk, wen, out_101, out_102, out_111, out_112); + sh_reg inst_sh_reg_12(clk, wen, out_111, out_112, out_121, out_122); + sh_reg inst_sh_reg_13(clk, wen, out_121, out_122, out_131, out_132); + sh_reg inst_sh_reg_14(clk, wen, out_131, out_132, out_141, out_142); + sh_reg inst_sh_reg_15(clk, wen, out_141, out_142, out_151, out_152); + sh_reg inst_sh_reg_16(clk, wen, out_151, out_152, out_161, out_162); + sh_reg inst_sh_reg_17(clk, wen, out_161, out_162, out_171, out_172); + sh_reg inst_sh_reg_18(clk, wen, out_171, out_172, out_181, out_182); + sh_reg inst_sh_reg_19(clk, wen, out_181, out_182, out_191, out_192); + sh_reg inst_sh_reg_20(clk, wen, out_191, out_192, out_201, out_202); + corr inst_corr_0(clk, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + corr inst_corr_1(clk, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + corr inst_corr_2(clk, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + corr inst_corr_3(clk, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + corr inst_corr_4(clk, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + corr inst_corr_5(clk, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + corr inst_corr_6(clk, wen, out_61, out_62, out_r1, out_r2, corr_out_6_tmp); + corr inst_corr_7(clk, wen, out_71, out_72, out_r1, out_r2, corr_out_7_tmp); + corr inst_corr_8(clk, wen, out_81, out_82, out_r1, out_r2, corr_out_8_tmp); + corr inst_corr_9(clk, wen, out_91, out_92, out_r1, out_r2, corr_out_9_tmp); + corr inst_corr_10(clk, wen, out_101, out_102, out_r1, out_r2, corr_out_10_tmp); + corr inst_corr_11(clk, wen, out_111, out_112, out_r1, out_r2, corr_out_11_tmp); + corr inst_corr_12(clk, wen, out_121, out_122, out_r1, out_r2, corr_out_12_tmp); + corr inst_corr_13(clk, wen, out_131, out_132, out_r1, out_r2, corr_out_13_tmp); + corr inst_corr_14(clk, wen, out_141, out_142, out_r1, out_r2, corr_out_14_tmp); + corr inst_corr_15(clk, wen, out_151, out_152, out_r1, out_r2, corr_out_15_tmp); + corr inst_corr_16(clk, wen, out_161, out_162, out_r1, out_r2, corr_out_16_tmp); + corr inst_corr_17(clk, wen, out_171, out_172, out_r1, out_r2, corr_out_17_tmp); + corr inst_corr_18(clk, wen, out_181, out_182, out_r1, out_r2, corr_out_18_tmp); + corr inst_corr_19(clk, wen, out_191, out_192, out_r1, out_r2, corr_out_19_tmp); + corr inst_corr_20(clk, wen, out_201, out_202, out_r1, out_r2, corr_out_20_tmp); + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + corr_out_6 <= corr_out_6_tmp ; + corr_out_7 <= corr_out_7_tmp ; + corr_out_8 <= corr_out_8_tmp ; + corr_out_9 <= corr_out_9_tmp ; + corr_out_10 <= corr_out_10_tmp ; + corr_out_11 <= corr_out_11_tmp ; + corr_out_12 <= corr_out_12_tmp ; + corr_out_13 <= corr_out_13_tmp ; + corr_out_14 <= corr_out_14_tmp ; + corr_out_15 <= corr_out_15_tmp ; + corr_out_16 <= corr_out_16_tmp ; + corr_out_17 <= corr_out_17_tmp ; + corr_out_18 <= corr_out_18_tmp ; + corr_out_19 <= corr_out_19_tmp ; + corr_out_20 <= corr_out_20_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + corr_out_6 <= corr_out_6; + corr_out_7 <= corr_out_7; + corr_out_8 <= corr_out_8; + corr_out_9 <= corr_out_9; + corr_out_10 <= corr_out_10; + corr_out_11 <= corr_out_11; + corr_out_12 <= corr_out_12; + corr_out_13 <= corr_out_13; + corr_out_14 <= corr_out_14; + corr_out_15 <= corr_out_15; + corr_out_16 <= corr_out_16; + corr_out_17 <= corr_out_17; + corr_out_18 <= corr_out_18; + corr_out_19 <= corr_out_19; + corr_out_20 <= corr_out_20; + end + end +endmodule +// Discription: this block creates a simple +// shift register +// date: Oct.7 ,2001 +// revised : April 8, 2002 +// By: Ahmad darabiha +module sh_reg (clk, wen, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[sh_reg_w - 1:0] din_1; + input[sh_reg_w - 1:0] din_2; + output[sh_reg_w - 1:0] dout_1; + reg[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + reg[sh_reg_w - 1:0] dout_2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + dout_1 <= din_1 ; + dout_2 <= din_2 ; + end + else + begin + dout_1 <= dout_1 ; + dout_2 <= dout_2 ; + end + end +endmodule +module corr (clk, new_data, in_l_re, in_l_im, in_r_re, in_r_im, corr_out); + + parameter sh_reg_w = 4'b1000; + input clk; + input new_data; + input[sh_reg_w - 1:0] in_l_re; + input[sh_reg_w - 1:0] in_l_im; + input[sh_reg_w - 1:0] in_r_re; + input[sh_reg_w - 1:0] in_r_im; + output[2 * sh_reg_w - 1:0] corr_out; + reg[2 * sh_reg_w - 1:0] corr_out; + wire[sh_reg_w - 1:0] in_l_re_reg; + wire[sh_reg_w - 1:0] in_l_im_reg; + wire[sh_reg_w - 1:0] in_r_re_reg; + wire[sh_reg_w - 1:0] in_r_im_reg; + reg[2 * sh_reg_w - 1:0] lrexrre_reg; + reg[2 * sh_reg_w - 1:0] limxrim_reg; + reg[2 * sh_reg_w - 1:0] corr_out_tmp; + + always @(posedge clk) + begin + // PAJ - edf xilinx files converted to multiply + lrexrre_reg <= in_l_re * in_r_re; + limxrim_reg <= in_l_im * in_r_im; + + if (new_data == 1'b1) + begin + corr_out <= corr_out_tmp ; + end + else + begin + corr_out <= corr_out; + end + corr_out_tmp <= lrexrre_reg + limxrim_reg ; + end + endmodule +module wrapper_norm (clk, nd, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input nd; + input[15:0] din_1; + input[15:0] din_2; + output[sh_reg_w - 1:0] dout_1; + wire[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + wire[sh_reg_w - 1:0] dout_2; + + reg[15:0] din_1_reg; + reg[15:0] din_2_reg; + reg[15:0] din_1_tmp1; + reg[15:0] din_2_tmp1; + reg[15:0] din_1_tmp2; + reg[15:0] din_2_tmp2; + reg[15:0] addin_1; + reg[15:0] addin_2; + reg[16:0] add_out; + + my_wrapper_divider my_div_inst_1 (nd, clk, din_1_tmp2, add_out, dout_1); + my_wrapper_divider my_div_inst_2 (nd, clk, din_2_tmp2, add_out, dout_2); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din_1 ; + din_2_reg <= din_2 ; + end + else + begin + din_1_reg <= din_1_reg ; + din_2_reg <= din_2_reg; + end + din_1_tmp1 <= din_1_reg ; + din_1_tmp2 <= din_1_tmp1 ; + din_2_tmp1 <= din_2_reg ; + din_2_tmp2 <= din_2_tmp1 ; + if ((din_1_reg[15]) == 1'b0) + begin + addin_1 <= din_1_reg ; + end + else + begin + addin_1 <= 16'b0000000000000000 - din_1_reg ; + end + if ((din_2_reg[15]) == 1'b0) + begin + addin_2 <= din_2_reg + 16'b0000000000000001 ; + end + else + begin + addin_2 <= 16'b0000000000000001 - din_2_reg ; + end + add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2}) ; + end +endmodule + + + + +module wrapper_norm_corr_10 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + wire[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + wire[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + wire[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + wire[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + wire[2 * sh_reg_w - 1:0] corr_out_10; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_10 corr_5_inst(.clk(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5), .corr_out_6(corr_out_6), .corr_out_7(corr_out_7), .corr_out_8(corr_out_8), .corr_out_9(corr_out_9), .corr_out_10(corr_out_10)); +endmodule + + + + +module wrapper_corr_10 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + reg[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + reg[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + reg[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + reg[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + reg[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + reg[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + reg[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + reg[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + reg[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + reg[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + reg[2 * sh_reg_w - 1:0] corr_out_10; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_61; + wire[sh_reg_w - 1:0] out_71; + wire[sh_reg_w - 1:0] out_81; + wire[sh_reg_w - 1:0] out_91; + wire[sh_reg_w - 1:0] out_101; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[sh_reg_w - 1:0] out_62; + wire[sh_reg_w - 1:0] out_72; + wire[sh_reg_w - 1:0] out_82; + wire[sh_reg_w - 1:0] out_92; + + wire[sh_reg_w - 1:0] out_102; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_6_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_7_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_8_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_9_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_10_tmp; + + sh_reg inst_sh_reg_r_1(clk, wen, d_r_1, d_r_2, out_r1, out_r2); + + sh_reg inst_sh_reg_0(clk, wen, d_l_1, d_l_2, out_01, out_02); + + sh_reg inst_sh_reg_1(clk, wen, out_01, out_02, out_11, out_12); + + sh_reg inst_sh_reg_2(clk, wen, out_11, out_12, out_21, out_22); + + sh_reg inst_sh_reg_3(clk, wen, out_21, out_22, out_31, out_32); + + sh_reg inst_sh_reg_4(clk, wen, out_31, out_32, out_41, out_42); + + sh_reg inst_sh_reg_5(clk, wen, out_41, out_42, out_51, out_52); + + sh_reg inst_sh_reg_6(clk, wen, out_51, out_52, out_61, out_62); + + sh_reg inst_sh_reg_7(clk, wen, out_61, out_62, out_71, out_72); + + sh_reg inst_sh_reg_8(clk, wen, out_71, out_72, out_81, out_82); + + sh_reg inst_sh_reg_9(clk, wen, out_81, out_82, out_91, out_92); + + sh_reg inst_sh_reg_10(clk, wen, out_91, out_92, out_101, out_102); + + corr inst_corr_0(clk, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + + corr inst_corr_1(clk, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + + corr inst_corr_2(clk, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + + corr inst_corr_3(clk, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + + corr inst_corr_4(clk, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + + corr inst_corr_5(clk, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + + corr inst_corr_6(clk, wen, out_61, out_62, out_r1, out_r2, corr_out_6_tmp); + + corr inst_corr_7(clk, wen, out_71, out_72, out_r1, out_r2, corr_out_7_tmp); + + corr inst_corr_8(clk, wen, out_81, out_82, out_r1, out_r2, corr_out_8_tmp); + + corr inst_corr_9(clk, wen, out_91, out_92, out_r1, out_r2, corr_out_9_tmp); + + corr inst_corr_10(clk, wen, out_101, out_102, out_r1, out_r2, corr_out_10_tmp); + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + corr_out_6 <= corr_out_6_tmp ; + corr_out_7 <= corr_out_7_tmp ; + corr_out_8 <= corr_out_8_tmp ; + corr_out_9 <= corr_out_9_tmp ; + corr_out_10 <= corr_out_10_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + corr_out_6 <= corr_out_6; + corr_out_7 <= corr_out_7; + corr_out_8 <= corr_out_8; + corr_out_9 <= corr_out_9; + corr_out_10 <= corr_out_10; + end + + end +endmodule + + + +module wrapper_norm_corr_5_seq (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm_seq norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm_seq norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_5_seq corr_5_inst (.tm3_clk_v0(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5)); +endmodule + + + + +module wrapper_corr_5_seq (tm3_clk_v0, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5); + + parameter sh_reg_w = 4'b1000; + + input tm3_clk_v0; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[15:0] corr_out_0; + reg[15:0] corr_out_0; + output[15:0] corr_out_1; + reg[15:0] corr_out_1; + output[15:0] corr_out_2; + reg[15:0] corr_out_2; + output[15:0] corr_out_3; + reg[15:0] corr_out_3; + output[15:0] corr_out_4; + reg[15:0] corr_out_4; + output[15:0] corr_out_5; + reg[15:0] corr_out_5; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + + sh_reg inst_sh_reg_r_1(tm3_clk_v0, wen, d_r_1, d_r_2, out_r1, out_r2); + sh_reg inst_sh_reg_0(tm3_clk_v0, wen, d_l_1, d_l_2, out_01, out_02); + sh_reg inst_sh_reg_1(tm3_clk_v0, wen, out_01, out_02, out_11, out_12); + sh_reg inst_sh_reg_2(tm3_clk_v0, wen, out_11, out_12, out_21, out_22); + sh_reg inst_sh_reg_3(tm3_clk_v0, wen, out_21, out_22, out_31, out_32); + sh_reg inst_sh_reg_4(tm3_clk_v0, wen, out_31, out_32, out_41, out_42); + sh_reg inst_sh_reg_5(tm3_clk_v0, wen, out_41, out_42, out_51, out_52); + corr_seq inst_corr_0(tm3_clk_v0, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + corr_seq inst_corr_1(tm3_clk_v0, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + corr_seq inst_corr_2(tm3_clk_v0, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + corr_seq inst_corr_3(tm3_clk_v0, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + corr_seq inst_corr_4(tm3_clk_v0, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + corr_seq inst_corr_5(tm3_clk_v0, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + + always @(posedge tm3_clk_v0) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + end + end +endmodule + +module wrapper_norm_seq (clk, nd, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input nd; + input[15:0] din_1; + input[15:0] din_2; + output[sh_reg_w - 1:0] dout_1; + wire[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + wire[sh_reg_w - 1:0] dout_2; + + reg[15:0] din_1_reg; + reg[15:0] din_2_reg; + reg[15:0] din_1_tmp1; + reg[15:0] din_2_tmp1; + reg[15:0] din_1_tmp2; + reg[15:0] din_2_tmp2; + reg[15:0] addin_1; + reg[15:0] addin_2; + reg[16:0] add_out; + + my_wrapper_divider my_div_inst_1 (nd, clk, din_1_tmp2, add_out, dout_1); + my_wrapper_divider my_div_inst_2 (nd, clk, din_2_tmp2, add_out, dout_2); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din_1 ; + din_2_reg <= din_2 ; + end + else + begin + din_1_reg <= din_1_reg ; + din_2_reg <= din_2_reg ; + end + + din_1_tmp1 <= din_1_reg ; + din_1_tmp2 <= din_1_tmp1 ; + din_2_tmp1 <= din_2_reg ; + din_2_tmp2 <= din_2_tmp1 ; + + if ((din_1_reg[15]) == 1'b0) + begin + addin_1 <= din_1_reg ; + end + else + begin + addin_1 <= 16'b0000000000000000 - din_1_reg ; + end + + if ((din_2_reg[15]) == 1'b0) + begin + addin_2 <= din_2_reg + 16'b0000000000000001 ; + end + else + begin + addin_2 <= 16'b0000000000000001 - din_2_reg ; + end + + add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2}) ; + end +endmodule + +module corr_seq (clk, new_data, in_l_re, in_l_im, in_r_re, in_r_im, corr_out); + + parameter sh_reg_w = 4'b1000; + input clk; + input new_data; + input[sh_reg_w - 1:0] in_l_re; + input[sh_reg_w - 1:0] in_l_im; + input[sh_reg_w - 1:0] in_r_re; + input[sh_reg_w - 1:0] in_r_im; + output[2 * sh_reg_w - 1:0] corr_out; + reg[2 * sh_reg_w - 1:0] corr_out; + reg[sh_reg_w - 1:0] in_l_re_reg; + reg[sh_reg_w - 1:0] in_l_im_reg; + reg[sh_reg_w - 1:0] in_r_re_reg; + reg[sh_reg_w - 1:0] in_r_im_reg; + reg[2 * sh_reg_w - 1:0] lrexrre_reg; + reg[2 * sh_reg_w - 1:0] limxrim_reg; + reg[2 * sh_reg_w - 1:0] corr_out_tmp; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + in_l_re_reg <= in_l_re ; + in_l_im_reg <= in_l_im ; + in_r_re_reg <= in_r_re ; + in_r_im_reg <= in_r_im ; + corr_out <= corr_out_tmp ; + end + else + begin + in_l_re_reg <= in_l_re_reg ; + in_l_im_reg <= in_l_im_reg ; + in_r_re_reg <= in_r_re_reg ; + in_r_im_reg <= in_r_im_reg ; + corr_out <= corr_out; + end + // PAJ - replaced by me, but called mult_slow + lrexrre_reg <= in_l_re_reg*in_r_re_reg ; + limxrim_reg <= in_l_im_reg*in_r_im_reg ; + corr_out_tmp <= lrexrre_reg + limxrim_reg ; + end + endmodule +module port_bus_1to0 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, v_corr_05_00, v_corr_05_01, v_corr_05_02, v_corr_05_03, v_corr_05_04, v_corr_05_05, v_corr_10_00, v_corr_10_01, v_corr_10_02, v_corr_10_03, v_corr_10_04, v_corr_10_05, v_corr_10_06, v_corr_10_07, v_corr_10_08, v_corr_10_09, v_corr_10_10, v_corr_20_00, v_corr_20_01, v_corr_20_02, v_corr_20_03, v_corr_20_04, v_corr_20_05, v_corr_20_06, v_corr_20_07, v_corr_20_08, v_corr_20_09, v_corr_20_10, v_corr_20_11, v_corr_20_12, v_corr_20_13, v_corr_20_14, v_corr_20_15, v_corr_20_16, v_corr_20_17, v_corr_20_18, v_corr_20_19, v_corr_20_20, bus_word_1, bus_word_2, bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out, rst); + + parameter corr_res_w = 4'b1000; + input rst; + input clk; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + input vidin_new_data_scld_1_2to3_left; + input[corr_res_w - 1:0] v_corr_05_00; + input[corr_res_w - 1:0] v_corr_05_01; + input[corr_res_w - 1:0] v_corr_05_02; + input[corr_res_w - 1:0] v_corr_05_03; + input[corr_res_w - 1:0] v_corr_05_04; + input[corr_res_w - 1:0] v_corr_05_05; + input[corr_res_w - 1:0] v_corr_10_00; + input[corr_res_w - 1:0] v_corr_10_01; + input[corr_res_w - 1:0] v_corr_10_02; + input[corr_res_w - 1:0] v_corr_10_03; + input[corr_res_w - 1:0] v_corr_10_04; + input[corr_res_w - 1:0] v_corr_10_05; + input[corr_res_w - 1:0] v_corr_10_06; + input[corr_res_w - 1:0] v_corr_10_07; + input[corr_res_w - 1:0] v_corr_10_08; + input[corr_res_w - 1:0] v_corr_10_09; + input[corr_res_w - 1:0] v_corr_10_10; + input[corr_res_w - 1:0] v_corr_20_00; + input[corr_res_w - 1:0] v_corr_20_01; + input[corr_res_w - 1:0] v_corr_20_02; + input[corr_res_w - 1:0] v_corr_20_03; + input[corr_res_w - 1:0] v_corr_20_04; + input[corr_res_w - 1:0] v_corr_20_05; + input[corr_res_w - 1:0] v_corr_20_06; + input[corr_res_w - 1:0] v_corr_20_07; + input[corr_res_w - 1:0] v_corr_20_08; + input[corr_res_w - 1:0] v_corr_20_09; + input[corr_res_w - 1:0] v_corr_20_10; + input[corr_res_w - 1:0] v_corr_20_11; + input[corr_res_w - 1:0] v_corr_20_12; + input[corr_res_w - 1:0] v_corr_20_13; + input[corr_res_w - 1:0] v_corr_20_14; + input[corr_res_w - 1:0] v_corr_20_15; + input[corr_res_w - 1:0] v_corr_20_16; + input[corr_res_w - 1:0] v_corr_20_17; + input[corr_res_w - 1:0] v_corr_20_18; + input[corr_res_w - 1:0] v_corr_20_19; + input[corr_res_w - 1:0] v_corr_20_20; + output[7:0] bus_word_1; + reg[7:0] bus_word_1; + output[7:0] bus_word_2; + reg[7:0] bus_word_2; + output[7:0] bus_word_3; + reg[7:0] bus_word_3; + output[7:0] bus_word_4; + reg[7:0] bus_word_4; + output[7:0] bus_word_5; + reg[7:0] bus_word_5; + output[7:0] bus_word_6; + reg[7:0] bus_word_6; + output[2:0] counter_out; + reg[2:0] counter_out; + + reg[7:0] bus_word_1_tmp; + reg[7:0] bus_word_2_tmp; + reg[7:0] bus_word_3_tmp; + reg[7:0] bus_word_4_tmp; + reg[7:0] bus_word_5_tmp; + reg[7:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_2to3_left_tmp; + reg[3:0] counter; + reg[2:0] counter_out_tmp; + reg[corr_res_w - 1:0] v_corr_05_00_tmp; + reg[corr_res_w - 1:0] v_corr_05_01_tmp; + reg[corr_res_w - 1:0] v_corr_05_02_tmp; + reg[corr_res_w - 1:0] v_corr_05_03_tmp; + reg[corr_res_w - 1:0] v_corr_05_04_tmp; + reg[corr_res_w - 1:0] v_corr_05_05_tmp; + reg[corr_res_w - 1:0] v_corr_10_00_tmp; + reg[corr_res_w - 1:0] v_corr_10_01_tmp; + reg[corr_res_w - 1:0] v_corr_10_02_tmp; + reg[corr_res_w - 1:0] v_corr_10_03_tmp; + reg[corr_res_w - 1:0] v_corr_10_04_tmp; + reg[corr_res_w - 1:0] v_corr_10_05_tmp; + reg[corr_res_w - 1:0] v_corr_10_06_tmp; + reg[corr_res_w - 1:0] v_corr_10_07_tmp; + reg[corr_res_w - 1:0] v_corr_10_08_tmp; + reg[corr_res_w - 1:0] v_corr_10_09_tmp; + reg[corr_res_w - 1:0] v_corr_10_10_tmp; + reg[corr_res_w - 1:0] v_corr_20_00_tmp; + reg[corr_res_w - 1:0] v_corr_20_01_tmp; + reg[corr_res_w - 1:0] v_corr_20_02_tmp; + reg[corr_res_w - 1:0] v_corr_20_03_tmp; + reg[corr_res_w - 1:0] v_corr_20_04_tmp; + reg[corr_res_w - 1:0] v_corr_20_05_tmp; + reg[corr_res_w - 1:0] v_corr_20_06_tmp; + reg[corr_res_w - 1:0] v_corr_20_07_tmp; + reg[corr_res_w - 1:0] v_corr_20_08_tmp; + reg[corr_res_w - 1:0] v_corr_20_09_tmp; + reg[corr_res_w - 1:0] v_corr_20_10_tmp; + reg[corr_res_w - 1:0] v_corr_20_11_tmp; + reg[corr_res_w - 1:0] v_corr_20_12_tmp; + reg[corr_res_w - 1:0] v_corr_20_13_tmp; + reg[corr_res_w - 1:0] v_corr_20_14_tmp; + reg[corr_res_w - 1:0] v_corr_20_15_tmp; + reg[corr_res_w - 1:0] v_corr_20_16_tmp; + reg[corr_res_w - 1:0] v_corr_20_17_tmp; + reg[corr_res_w - 1:0] v_corr_20_18_tmp; + reg[corr_res_w - 1:0] v_corr_20_19_tmp; + reg[corr_res_w - 1:0] v_corr_20_20_tmp; + + always @(posedge clk) + begin + if (rst) + begin + counter <= 0; + counter_out_tmp <= 3'b000 ; + bus_word_1_tmp <= 8'b00000000 ; + bus_word_2_tmp <= 8'b00000000 ; + bus_word_3_tmp <= 8'b00000000 ; + bus_word_4_tmp <= 8'b00000000 ; + bus_word_5_tmp <= 8'b00000000 ; + bus_word_6_tmp <= 8'b00000000 ; + end + else + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + counter <= 4'b0001 ; + end + else + begin + if (counter == 4'b1000) + begin + counter <= 4'b1000 ; + end + else + begin + counter <= counter + 1 ; + end + end + case (counter[2:0]) + 3'b000 : + begin + counter_out_tmp <= 3'b000 ; + bus_word_1_tmp <= 8'b00000000 ; + bus_word_2_tmp <= 8'b00000000 ; + bus_word_3_tmp <= 8'b00000000 ; + bus_word_4_tmp <= 8'b00000000 ; + bus_word_5_tmp <= 8'b00000000 ; + bus_word_6_tmp <= 8'b00000000 ; + end + 3'b001 : + begin + counter_out_tmp <= 3'b001 ; + bus_word_1_tmp <= vidin_addr_reg_tmp[7:0] ; + bus_word_2_tmp <= vidin_addr_reg_tmp[15:8] ; + bus_word_3_tmp <= {vidin_addr_reg_tmp[18:16], svid_comp_switch_tmp, 4'b0000} ; + bus_word_4_tmp <= v_corr_05_00_tmp ; + bus_word_5_tmp <= v_corr_05_01_tmp ; + bus_word_6_tmp <= v_corr_05_02_tmp ; + end + 3'b010 : + begin + counter_out_tmp <= 3'b010 ; + bus_word_1_tmp <= v_corr_05_03_tmp ; + bus_word_2_tmp <= v_corr_05_04_tmp ; + bus_word_3_tmp <= v_corr_05_05_tmp ; + bus_word_4_tmp <= v_corr_10_00_tmp ; + bus_word_5_tmp <= v_corr_10_01_tmp ; + bus_word_6_tmp <= v_corr_10_02_tmp ; + end + 3'b011 : + begin + counter_out_tmp <= 3'b011 ; + bus_word_1_tmp <= v_corr_10_03_tmp ; + bus_word_2_tmp <= v_corr_10_04_tmp ; + bus_word_3_tmp <= v_corr_10_05_tmp ; + bus_word_4_tmp <= v_corr_10_06_tmp ; + bus_word_5_tmp <= v_corr_10_07_tmp ; + bus_word_6_tmp <= v_corr_10_08_tmp ; + end + 3'b100 : + begin + counter_out_tmp <= 3'b100 ; + bus_word_1_tmp <= v_corr_10_09_tmp ; + bus_word_2_tmp <= v_corr_10_10_tmp ; + bus_word_3_tmp <= v_corr_20_00_tmp ; + bus_word_4_tmp <= v_corr_20_01_tmp ; + bus_word_5_tmp <= v_corr_20_02_tmp ; + bus_word_6_tmp <= v_corr_20_03_tmp ; + end + 3'b101 : + + begin + counter_out_tmp <= 3'b101 ; + bus_word_1_tmp <= v_corr_20_04_tmp ; + bus_word_2_tmp <= v_corr_20_05_tmp ; + bus_word_3_tmp <= v_corr_20_06_tmp ; + bus_word_4_tmp <= v_corr_20_07_tmp ; + bus_word_5_tmp <= v_corr_20_08_tmp ; + bus_word_6_tmp <= v_corr_20_09_tmp ; + end + 3'b110 : + begin + counter_out_tmp <= 3'b110 ; + bus_word_1_tmp <= v_corr_20_10_tmp ; + bus_word_2_tmp <= v_corr_20_11_tmp ; + bus_word_3_tmp <= v_corr_20_12_tmp ; + bus_word_4_tmp <= v_corr_20_13_tmp ; + bus_word_5_tmp <= v_corr_20_14_tmp ; + bus_word_6_tmp <= v_corr_20_15_tmp ; + end + 3'b111 : + begin + counter_out_tmp <= 3'b111 ; + bus_word_1_tmp <= v_corr_20_16_tmp ; + bus_word_2_tmp <= v_corr_20_17_tmp ; + bus_word_3_tmp <= v_corr_20_18_tmp ; + bus_word_4_tmp <= v_corr_20_19_tmp ; + bus_word_5_tmp <= v_corr_20_20_tmp ; + bus_word_6_tmp <= 8'b00000000 ; + end + default : + begin + counter_out_tmp <= 3'b111 ; + bus_word_1_tmp <= v_corr_20_16_tmp ; + bus_word_2_tmp <= v_corr_20_17_tmp ; + bus_word_3_tmp <= v_corr_20_18_tmp ; + bus_word_4_tmp <= v_corr_20_19_tmp ; + bus_word_5_tmp <= v_corr_20_20_tmp ; + bus_word_6_tmp <= 8'b00000000 ; + end + endcase + end + end + + always @(posedge clk) + begin + if (rst) + begin + counter_out <= 0; + bus_word_1 <= 0; + bus_word_2 <= 0; + bus_word_3 <= 0; + bus_word_4 <= 0; + bus_word_5 <= 0; + bus_word_6 <= 0; + end + else + begin + counter_out <= counter_out_tmp ; + bus_word_1 <= bus_word_1_tmp ; + bus_word_2 <= bus_word_2_tmp ; + bus_word_3 <= bus_word_3_tmp ; + bus_word_4 <= bus_word_4_tmp ; + bus_word_5 <= bus_word_5_tmp ; + bus_word_6 <= bus_word_6_tmp ; + end + + + if (rst) + begin + vidin_addr_reg_tmp <= 0; + svid_comp_switch_tmp <= 0; + v_corr_05_00_tmp <= 0 ; + v_corr_05_01_tmp <= 0 ; + v_corr_05_02_tmp <= 0 ; + v_corr_05_03_tmp <= 0; + v_corr_05_04_tmp <= 0 ; + v_corr_05_05_tmp <= 0 ; + v_corr_10_00_tmp <= 0 ; + v_corr_10_01_tmp <= 0 ; + v_corr_10_02_tmp <= 0 ; + v_corr_10_03_tmp <= 0 ; + v_corr_10_04_tmp <= 0 ; + v_corr_10_05_tmp <= 0 ; + v_corr_10_06_tmp <= 0 ; + v_corr_10_07_tmp <= 0; + v_corr_10_08_tmp <= 0; + v_corr_10_09_tmp <= 0; + v_corr_10_10_tmp <= 0; + v_corr_20_00_tmp <= 0; + v_corr_20_01_tmp <= 0; + v_corr_20_02_tmp <= 0; + v_corr_20_03_tmp <= 0; + v_corr_20_04_tmp <= 0; + v_corr_20_05_tmp <= 0; + v_corr_20_06_tmp <= 0; + v_corr_20_07_tmp <= 0; + v_corr_20_08_tmp <= 0; + v_corr_20_09_tmp <= 0; + v_corr_20_10_tmp <= 0; + v_corr_20_11_tmp <= 0; + v_corr_20_12_tmp <= 0; + v_corr_20_13_tmp <= 0; + v_corr_20_14_tmp <= 0; + v_corr_20_15_tmp <= 0; + v_corr_20_16_tmp <= 0; + v_corr_20_17_tmp <= 0; + v_corr_20_18_tmp <= 0; + v_corr_20_19_tmp <= 0; + v_corr_20_20_tmp <= 0; + end + else if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + vidin_addr_reg_tmp <= vidin_addr_reg ; + svid_comp_switch_tmp <= svid_comp_switch ; + v_corr_05_00_tmp <= v_corr_05_00 ; + v_corr_05_01_tmp <= v_corr_05_01 ; + v_corr_05_02_tmp <= v_corr_05_02 ; + v_corr_05_03_tmp <= v_corr_05_03 ; + v_corr_05_04_tmp <= v_corr_05_04 ; + v_corr_05_05_tmp <= v_corr_05_05 ; + v_corr_10_00_tmp <= v_corr_10_00 ; + v_corr_10_01_tmp <= v_corr_10_01 ; + v_corr_10_02_tmp <= v_corr_10_02 ; + v_corr_10_03_tmp <= v_corr_10_03 ; + v_corr_10_04_tmp <= v_corr_10_04 ; + v_corr_10_05_tmp <= v_corr_10_05 ; + v_corr_10_06_tmp <= v_corr_10_06 ; + v_corr_10_07_tmp <= v_corr_10_07 ; + v_corr_10_08_tmp <= v_corr_10_08 ; + v_corr_10_09_tmp <= v_corr_10_09 ; + v_corr_10_10_tmp <= v_corr_10_10 ; + v_corr_20_00_tmp <= v_corr_20_00 ; + v_corr_20_01_tmp <= v_corr_20_01 ; + v_corr_20_02_tmp <= v_corr_20_02 ; + v_corr_20_03_tmp <= v_corr_20_03 ; + v_corr_20_04_tmp <= v_corr_20_04 ; + v_corr_20_05_tmp <= v_corr_20_05 ; + v_corr_20_06_tmp <= v_corr_20_06 ; + v_corr_20_07_tmp <= v_corr_20_07 ; + v_corr_20_08_tmp <= v_corr_20_08 ; + v_corr_20_09_tmp <= v_corr_20_09 ; + v_corr_20_10_tmp <= v_corr_20_10 ; + v_corr_20_11_tmp <= v_corr_20_11 ; + v_corr_20_12_tmp <= v_corr_20_12 ; + v_corr_20_13_tmp <= v_corr_20_13 ; + v_corr_20_14_tmp <= v_corr_20_14 ; + v_corr_20_15_tmp <= v_corr_20_15 ; + v_corr_20_16_tmp <= v_corr_20_16 ; + v_corr_20_17_tmp <= v_corr_20_17 ; + v_corr_20_18_tmp <= v_corr_20_18 ; + v_corr_20_19_tmp <= v_corr_20_19 ; + v_corr_20_20_tmp <= v_corr_20_20 ; + end + else + begin + vidin_addr_reg_tmp <= vidin_addr_reg_tmp ; + svid_comp_switch_tmp <= svid_comp_switch_tmp ; + v_corr_05_00_tmp <= v_corr_05_00_tmp ; + v_corr_05_01_tmp <= v_corr_05_01_tmp ; + v_corr_05_02_tmp <= v_corr_05_02_tmp ; + v_corr_05_03_tmp <= v_corr_05_03_tmp ; + v_corr_05_04_tmp <= v_corr_05_04_tmp ; + v_corr_05_05_tmp <= v_corr_05_05_tmp ; + v_corr_10_00_tmp <= v_corr_10_00_tmp ; + v_corr_10_01_tmp <= v_corr_10_01_tmp ; + v_corr_10_02_tmp <= v_corr_10_02_tmp ; + v_corr_10_03_tmp <= v_corr_10_03_tmp ; + v_corr_10_04_tmp <= v_corr_10_04_tmp ; + v_corr_10_05_tmp <= v_corr_10_05_tmp ; + v_corr_10_06_tmp <= v_corr_10_06_tmp ; + v_corr_10_07_tmp <= v_corr_10_07_tmp ; + v_corr_10_08_tmp <= v_corr_10_08_tmp ; + v_corr_10_09_tmp <= v_corr_10_09_tmp ; + v_corr_10_10_tmp <= v_corr_10_10_tmp ; + v_corr_20_00_tmp <= v_corr_20_00_tmp ; + v_corr_20_01_tmp <= v_corr_20_01_tmp ; + v_corr_20_02_tmp <= v_corr_20_02_tmp ; + v_corr_20_03_tmp <= v_corr_20_03_tmp ; + v_corr_20_04_tmp <= v_corr_20_04_tmp ; + v_corr_20_05_tmp <= v_corr_20_05_tmp ; + v_corr_20_06_tmp <= v_corr_20_06_tmp ; + v_corr_20_07_tmp <= v_corr_20_07_tmp ; + v_corr_20_08_tmp <= v_corr_20_08_tmp ; + v_corr_20_09_tmp <= v_corr_20_09_tmp ; + v_corr_20_10_tmp <= v_corr_20_10_tmp ; + v_corr_20_11_tmp <= v_corr_20_11_tmp ; + v_corr_20_12_tmp <= v_corr_20_12_tmp ; + v_corr_20_13_tmp <= v_corr_20_13_tmp ; + v_corr_20_14_tmp <= v_corr_20_14_tmp ; + v_corr_20_15_tmp <= v_corr_20_15_tmp ; + v_corr_20_16_tmp <= v_corr_20_16_tmp ; + v_corr_20_17_tmp <= v_corr_20_17_tmp ; + v_corr_20_18_tmp <= v_corr_20_18_tmp ; + v_corr_20_19_tmp <= v_corr_20_19_tmp ; + v_corr_20_20_tmp <= v_corr_20_20_tmp ; + end + end +endmodule +module my_wrapper_divider(rst, clk, data_in_a, data_in_b, data_out); + parameter INPUT_WIDTH_A = 5'b10000; + parameter INPUT_WIDTH_B = 5'b10001; + parameter OUTPUT_WIDTH = 4'b1000; + + parameter S1 = 2'b00; + parameter S2 = 2'b01; + parameter S3 = 2'b10; + parameter S4 = 2'b11; + + input rst; + input clk; + input [INPUT_WIDTH_A-1:0]data_in_a; + input [INPUT_WIDTH_B-1:0]data_in_b; + output [OUTPUT_WIDTH-1:0]data_out; + wire [OUTPUT_WIDTH-1:0]data_out; + + wire [OUTPUT_WIDTH-1:0]Remainder; + + reg start, LA, EB; + wire Done; + reg[1:0] y, Y; + + my_divider my_divider_inst(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data_out, Done); + + always @(posedge clk) + begin + if (rst == 0) + y <= S1; + else + y <= Y; + end + + always @(y) + begin + case (y) + S1 : + begin + LA = 0; + EB = 0; + start = 0; + Y = S2; + end + S2 : + begin + LA = 1; + EB = 1; + start = 0; + Y = S3; + end + S3 : + begin + LA = 0; + EB = 0; + start = 1; + Y = S4; + end + S4 : + begin + LA = 0; + EB = 0; + start = 0; + if (Done == 1'b1) + begin + Y = S1; + end + else + begin + Y = S4; + end + end + endcase + end +endmodule + +module my_divider(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data_out, Done); + + parameter INPUT_WIDTH_A = 5'b10000; + parameter INPUT_WIDTH_B = 5'b10001; + parameter OUTPUT_WIDTH = 4'b1000; + parameter LOGN = 3'b100; + + parameter S1 = 2'b00; + parameter S2 = 2'b01; + parameter S3 = 2'b10; + + input clk; + input [INPUT_WIDTH_A-1:0]data_in_a; + input [INPUT_WIDTH_B-1:0]data_in_b; + input rst; + input start; + input LA; + input EB; + output [OUTPUT_WIDTH-1:0]data_out; + wire [OUTPUT_WIDTH-1:0]data_out; + output [OUTPUT_WIDTH-1:0]Remainder; + reg [OUTPUT_WIDTH-1:0]Remainder; + output Done; + reg Done; + + wire Cout, zero; + wire [INPUT_WIDTH_A-1:0] Sum; + reg [1:0] y, Y; + reg [LOGN-1:0] Count; + reg EA, Rsel, LR, ER, ER0, LC, EC; + reg [INPUT_WIDTH_B-1:0] RegB; + reg [INPUT_WIDTH_A-1:0] DataA; + reg ff0; + + always @(start or y or zero) + begin + case(y) + S1: + begin + if (start == 0) + Y = S1; + else + Y = S2; + end + S2: + begin + if (zero == 0) + Y = S2; + else + Y = S3; + end + S3: + begin + if (start == 1) + Y = S3; + else + Y = S1; + end + default: + begin + Y = 2'b00; + end + endcase + end + + always @(posedge clk) + begin + if (rst == 0) + y <= S1; + else + y <= Y; + end + + always @(y or start or Cout or zero) + begin + case (y) + S1: + begin + LC = 1; + ER = 1; + EC = 0; + Rsel = 0; + Done = 0; + if (start == 0) + begin + LR = 1; + ER0 = 1; + EA = 0; + end + else + begin + LR = 0; + EA = 1; + ER0 = 1; + end + end + S2: + begin + LC = 0; + ER = 1; + Rsel = 1; + Done = 0; + ER0 = 1; + EA = 1; + if (Cout) + LR = 1; + else + LR = 0; + if (zero == 0) + EC = 1; + else + EC = 0; + end + S3: + begin + Done = 1; + LR = 0; + LC = 0; + ER = 0; + EC = 0; + Rsel = 0; + ER0 = 0; + EA = 0; + end + default: + begin + Done = 0; + LR = 0; + LC = 0; + ER = 0; + EC = 0; + Rsel = 0; + ER0 = 0; + EA = 0; + end + endcase + end + + always @(posedge clk) + begin + if (rst == 1) + begin + RegB <= 0; + Remainder <= 0; + DataA <= 0; + ff0 <= 0; + Count <= 0; + end + else + begin + if (EB == 1) + begin + RegB <= data_in_b; + end + else + begin + RegB <= RegB; + end + + if (LR == 1) + begin + Remainder <= Rsel ? Sum : 0; + end + else if (ER == 1) + begin + Remainder <= (Remainder << 1) | ff0; + end + else + begin + Remainder <= Remainder; + end + + if (LA == 1) + begin + DataA <= data_in_a; + end + else if (EA == 1) + begin + DataA <= (DataA << 1) | Cout; + end + else + begin + DataA <= DataA; + end + + if (ER0 == 1) + begin + ff0 <= DataA[INPUT_WIDTH_A-1]; + end + else + begin + ff0 <= 0; + end + + if (LC == 1) + begin + Count <= 0; + end + else if (EC == 1) + begin + Count <= Count + 1; + end + else + begin + Count <= Count; + end + end + end + + assign zero = (Count == 0); + assign Sum = {Remainder, ff0} + (~RegB + 1); + assign Cout = Sum[INPUT_WIDTH_A-1:0]; + assign data_out = DataA; + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v new file mode 100755 index 000000000..dba6741aa --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v @@ -0,0 +1,1846 @@ +module sv_chip2_hierarchy_no_mem (reset, tm3_clk_v0, vidin_new_data, vidin_rgb_reg, vidin_addr_reg, svid_comp_switch, counter_out_2to1, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_left_2to0, v_nd_s2_left_2to0 , v_nd_s4_left_2to0 , v_d_reg_s1_left_2to0 , v_d_reg_s2_left_2to0 , v_d_reg_s4_left_2to0 , v_nd_s1_right_2to0, v_nd_s2_right_2to0 , v_nd_s4_right_2to0 , v_d_reg_s1_right_2to0 , v_d_reg_s2_right_2to0 , v_d_reg_s4_right_2to0,offchip_sram_data_in,offchip_sram_addr,offchip_sram_data_out,offchip_sram_we,offchip_sram_oe,tm3_sram_adsp); + + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + input reset; + input tm3_clk_v0; + + wire[63:0] tm3_sram_data_in; + + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input vidin_new_data; + input[7:0] vidin_rgb_reg; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + output[2:0] counter_out_2to1; + wire[2:0] counter_out_2to1; + output[15:0] bus_word_3_2to1; + wire[15:0] bus_word_3_2to1; + output[15:0] bus_word_4_2to1; + wire[15:0] bus_word_4_2to1; + output[15:0] bus_word_5_2to1; + wire[15:0] bus_word_5_2to1; + output[15:0] bus_word_6_2to1; + wire[15:0] bus_word_6_2to1; + output vidin_new_data_fifo; + reg vidin_new_data_fifo; + output[7:0] vidin_rgb_reg_fifo_left; + reg[7:0] vidin_rgb_reg_fifo_left; + output[7:0] vidin_rgb_reg_fifo_right; + reg[7:0] vidin_rgb_reg_fifo_right; + output[3:0] vidin_addr_reg_2to0; + reg[3:0] vidin_addr_reg_2to0; + input v_nd_s1_left_2to0; + input v_nd_s2_left_2to0; + input v_nd_s4_left_2to0; + input[7:0] v_d_reg_s1_left_2to0; + input[7:0] v_d_reg_s2_left_2to0; + input[7:0] v_d_reg_s4_left_2to0; + input v_nd_s1_right_2to0; + input v_nd_s2_right_2to0; + input v_nd_s4_right_2to0; + input[7:0] v_d_reg_s1_right_2to0; + input[7:0] v_d_reg_s2_right_2to0; + input[7:0] v_d_reg_s4_right_2to0; + + wire v_nd_s1; + wire vidin_new_data_v_fltr; + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[13:0] vidin_addr_buf_sc_1_fifo; + wire[18:0] vidin_addr_reg_scld; + reg video_state; + wire[7:0] vidin_gray_scld_1; + reg[63:0] vidout_buf_fifo_1_left; + reg[63:0] vidout_buf_fifo_1_right; + reg[7:0] vidin_rgb_reg_tmp; + reg[7:0] vidin_data_buf_fifo_sc_1_l; + reg[7:0] vidin_data_buf_fifo_sc_1_r; + reg[63:0] vidout_buf_fifo_2_1_left; + reg[63:0] vidout_buf_fifo_2_1_right; + wire vidin_new_data_tmp; + reg[18:0] vidin_addr_reg_reg; + reg v_nd_s1_left; + reg v_nd_s1_right; + reg v_nd_s2_left; + reg v_nd_s2_right; + reg v_nd_s4_left; + reg v_nd_s4_right; + reg[7:0] v_d_reg_s1_left; + reg[7:0] v_d_reg_s1_right; + reg[7:0] v_d_reg_s2_left; + reg[7:0] v_d_reg_s2_right; + reg[7:0] v_d_reg_s4_left; + reg[7:0] v_d_reg_s4_right; + wire[15:0] vidin_v_out_1_f1_left; + wire[15:0] vidin_v_out_1_f2_left; + wire[15:0] vidin_v_out_1_f3_left; + wire[15:0] vidin_v_out_1_h1_left; + wire[15:0] vidin_v_out_1_h2_left; + wire[15:0] vidin_v_out_1_h3_left; + wire[15:0] vidin_v_out_1_h4_left; + wire[15:0] vidin_v_out_2_f1_left; + wire[15:0] vidin_v_out_2_f2_left; + wire[15:0] vidin_v_out_2_f3_left; + wire[15:0] vidin_v_out_2_h1_left; + wire[15:0] vidin_v_out_2_h2_left; + wire[15:0] vidin_v_out_2_h3_left; + wire[15:0] vidin_v_out_2_h4_left; + wire[15:0] vidin_v_out_4_f1_left; + wire[15:0] vidin_v_out_4_f2_left; + wire[15:0] vidin_v_out_4_f3_left; + wire[15:0] vidin_v_out_4_h1_left; + wire[15:0] vidin_v_out_4_h2_left; + wire[15:0] vidin_v_out_4_h3_left; + wire[15:0] vidin_v_out_4_h4_left; + wire[15:0] vidin_v_out_1_f1_right; + wire[15:0] vidin_v_out_1_f2_right; + wire[15:0] vidin_v_out_1_f3_right; + wire[15:0] vidin_v_out_1_h1_right; + wire[15:0] vidin_v_out_1_h2_right; + wire[15:0] vidin_v_out_1_h3_right; + wire[15:0] vidin_v_out_1_h4_right; + wire[15:0] vidin_v_out_2_f1_right; + wire[15:0] vidin_v_out_2_f2_right; + wire[15:0] vidin_v_out_2_f3_right; + wire[15:0] vidin_v_out_2_h1_right; + wire[15:0] vidin_v_out_2_h2_right; + wire[15:0] vidin_v_out_2_h3_right; + wire[15:0] vidin_v_out_2_h4_right; + wire[15:0] vidin_v_out_4_f1_right; + wire[15:0] vidin_v_out_4_f2_right; + wire[15:0] vidin_v_out_4_f3_right; + wire[15:0] vidin_v_out_4_h1_right; + wire[15:0] vidin_v_out_4_h2_right; + wire[15:0] vidin_v_out_4_h3_right; + wire[15:0] vidin_v_out_4_h4_right; + wire[7:0] v_d_reg_s1_2to3_left; + wire[7:0] v_d_reg_s2_2to3_left; + wire[7:0] v_d_reg_s4_2to3_left; + wire[7:0] v_d_reg_s1_2to3_right; + wire[7:0] v_d_reg_s2_2to3_right; + wire[7:0] v_d_reg_s4_2to3_right; + reg[18:0] vidin_addr_reg_2to3; + reg svid_comp_switch_2to3; + wire[15:0] real_z_4_left; + wire[15:0] imag_z_4_left; + wire[15:0] real_p_4_left; + wire[15:0] imag_p_4_left; + wire[15:0] real_n_4_left; + wire[15:0] imag_n_4_left; + wire[15:0] real_z_4_right; + wire[15:0] imag_z_4_right; + wire[15:0] real_p_4_right; + wire[15:0] imag_p_4_right; + wire[15:0] real_n_4_right; + wire[15:0] imag_n_4_right; + wire[15:0] real_z_2_left; + wire[15:0] imag_z_2_left; + wire[15:0] real_p_2_left; + wire[15:0] imag_p_2_left; + wire[15:0] real_n_2_left; + wire[15:0] imag_n_2_left; + wire[15:0] real_z_2_right; + wire[15:0] imag_z_2_right; + wire[15:0] real_p_2_right; + wire[15:0] imag_p_2_right; + wire[15:0] real_n_2_right; + wire[15:0] imag_n_2_right; + wire[15:0] real_z_1_left; + wire[15:0] imag_z_1_left; + wire[15:0] real_p_1_left; + wire[15:0] imag_p_1_left; + wire[15:0] real_n_1_left; + wire[15:0] imag_n_1_left; + wire[15:0] real_z_1_right; + wire[15:0] imag_z_1_right; + wire[15:0] real_p_1_right; + wire[15:0] imag_p_1_right; + wire[15:0] real_n_1_right; + wire[15:0] imag_n_1_right; + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + v_fltr_496x7 v_fltr_1_left(tm3_clk_v0, v_nd_s1_left, v_d_reg_s1_left, vidin_v_out_1_f1_left, vidin_v_out_1_f2_left, vidin_v_out_1_f3_left, vidin_v_out_1_h1_left, vidin_v_out_1_h2_left, vidin_v_out_1_h3_left, vidin_v_out_1_h4_left); + v_fltr_316x7 v_fltr_2_left(tm3_clk_v0, v_nd_s2_left, v_d_reg_s2_left, vidin_v_out_2_f1_left, vidin_v_out_2_f2_left, vidin_v_out_2_f3_left, vidin_v_out_2_h1_left, vidin_v_out_2_h2_left, vidin_v_out_2_h3_left, vidin_v_out_2_h4_left); + v_fltr_226x7 v_fltr_4_left(tm3_clk_v0, v_nd_s4_left, v_d_reg_s4_left, vidin_v_out_4_f1_left, vidin_v_out_4_f2_left, vidin_v_out_4_f3_left, vidin_v_out_4_h1_left, vidin_v_out_4_h2_left, vidin_v_out_4_h3_left, vidin_v_out_4_h4_left); + h_fltr h_fltr_1_left (tm3_clk_v0, v_nd_s1_left, vidin_v_out_1_f1_left, vidin_v_out_1_f2_left, vidin_v_out_1_f3_left, vidin_v_out_1_h1_left, vidin_v_out_1_h2_left, vidin_v_out_1_h3_left, vidin_v_out_1_h4_left, real_z_1_left, imag_z_1_left, real_p_1_left, imag_p_1_left, real_n_1_left, imag_n_1_left); + h_fltr h_fltr_2_left (tm3_clk_v0, v_nd_s2_left, vidin_v_out_2_f1_left, vidin_v_out_2_f2_left, vidin_v_out_2_f3_left, vidin_v_out_2_h1_left, vidin_v_out_2_h2_left, vidin_v_out_2_h3_left, vidin_v_out_2_h4_left, real_z_2_left, imag_z_2_left, real_p_2_left, imag_p_2_left, real_n_2_left, imag_n_2_left); + h_fltr h_fltr_4_left (tm3_clk_v0, v_nd_s4_left, vidin_v_out_4_f1_left, vidin_v_out_4_f2_left, vidin_v_out_4_f3_left, vidin_v_out_4_h1_left, vidin_v_out_4_h2_left, vidin_v_out_4_h3_left, vidin_v_out_4_h4_left, real_z_4_left, imag_z_4_left, real_p_4_left, imag_p_4_left, real_n_4_left, imag_n_4_left); + + v_fltr_496x7 v_fltr_1_right(tm3_clk_v0, v_nd_s1_right, v_d_reg_s1_right, vidin_v_out_1_f1_right, vidin_v_out_1_f2_right, vidin_v_out_1_f3_right, vidin_v_out_1_h1_right, vidin_v_out_1_h2_right, vidin_v_out_1_h3_right, vidin_v_out_1_h4_right); + v_fltr_316x7 v_fltr_2_right(tm3_clk_v0, v_nd_s2_right, v_d_reg_s2_right, vidin_v_out_2_f1_right, vidin_v_out_2_f2_right, vidin_v_out_2_f3_right, vidin_v_out_2_h1_right, vidin_v_out_2_h2_right, vidin_v_out_2_h3_right, vidin_v_out_2_h4_right); + v_fltr_226x7 v_fltr_4_right(tm3_clk_v0, v_nd_s4_right, v_d_reg_s4_right, vidin_v_out_4_f1_right, vidin_v_out_4_f2_right, vidin_v_out_4_f3_right, vidin_v_out_4_h1_right, vidin_v_out_4_h2_right, vidin_v_out_4_h3_right, vidin_v_out_4_h4_right); + h_fltr h_fltr_1_right (tm3_clk_v0, v_nd_s1_right, vidin_v_out_1_f1_right, vidin_v_out_1_f2_right, vidin_v_out_1_f3_right, vidin_v_out_1_h1_right, vidin_v_out_1_h2_right, vidin_v_out_1_h3_right, vidin_v_out_1_h4_right, real_z_1_right, imag_z_1_right, real_p_1_right, imag_p_1_right, real_n_1_right, imag_n_1_right); + h_fltr h_fltr_2_right (tm3_clk_v0, v_nd_s2_right, vidin_v_out_2_f1_right, vidin_v_out_2_f2_right, vidin_v_out_2_f3_right, vidin_v_out_2_h1_right, vidin_v_out_2_h2_right, vidin_v_out_2_h3_right, vidin_v_out_2_h4_right, real_z_2_right, imag_z_2_right, real_p_2_right, imag_p_2_right, real_n_2_right, imag_n_2_right); + h_fltr h_fltr_4_right (tm3_clk_v0, v_nd_s4_right, vidin_v_out_4_f1_right, vidin_v_out_4_f2_right, vidin_v_out_4_f3_right, vidin_v_out_4_h1_right, vidin_v_out_4_h2_right, vidin_v_out_4_h3_right, vidin_v_out_4_h4_right, real_z_4_right, imag_z_4_right, real_p_4_right, imag_p_4_right, real_n_4_right, imag_n_4_right); + + port_bus_2to1 port_bus_2to1_inst (tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, v_nd_s1_left, real_p_1_left, imag_p_1_left, real_n_1_left, imag_n_1_left, real_p_2_left, imag_p_2_left, real_n_2_left, imag_n_2_left, real_p_4_left, imag_p_4_left, real_n_4_left, imag_n_4_left, real_p_1_right, imag_p_1_right, real_n_1_right, imag_n_1_right, real_p_2_right, imag_p_2_right, real_n_2_right, imag_n_2_right, real_p_4_right, imag_p_4_right, real_n_4_right, imag_n_4_right, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1); + + always @(posedge tm3_clk_v0) + begin + if (reset == 1'b0) + begin + video_state <= 1'b0; + tm3_sram_adsp <= 1'b0 ; + horiz <= 10'b0000000000; + vert <= 10'b0000000000 ; + end + else + begin + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + tm3_sram_data_xhdl0 <= 64'b0; + + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + tm3_sram_adsp <= 1'b1; + tm3_sram_we <= 8'b11111111; + + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_oe <= 2'b10 ; + end + 3'b001 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b010 : + begin + tm3_sram_oe <= 2'b10 ; + end + 3'b011 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b100 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b101 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b110 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b111 : + begin + tm3_sram_oe <= 2'b11 ; + end + endcase + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= {5'b00000, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b001 : + begin + vidout_buf_fifo_1_left <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b010 : + begin + tm3_sram_addr <= {5'b00001, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b011 : + begin + vidout_buf_fifo_1_right <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b100 : + begin + tm3_sram_addr <= {5'b00000, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b101 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b110 : + begin + if ((vert[8]) == 1'b0) + begin + tm3_sram_addr <= {5'b00000, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + else + begin + tm3_sram_addr <= {5'b00001, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + end + 3'b111 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + endcase + end + if (vidin_new_data_fifo == 1'b1) + begin + case (vidin_addr_reg_reg[2:0]) + 3'b000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[7:0] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[7:0] ; + end + 3'b001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[15:8] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[15:8] ; + end + 3'b010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[23:16] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[23:16] ; + end + 3'b011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[31:24] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[31:24] ; + end + 3'b100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[39:32] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[39:32] ; + end + 3'b101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[47:40] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[47:40] ; + end + 3'b110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[55:48] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[55:48] ; + end + 3'b111 : + begin + vidin_data_buf_sc_1 <= {vidin_rgb_reg_tmp, vidin_data_buf_2_sc_1[55:0]} ; + vidout_buf_fifo_2_1_left <= vidout_buf_fifo_1_left ; + vidout_buf_fifo_2_1_right <= vidout_buf_fifo_1_right ; + + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[63:56] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[63:56] ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch, vidin_addr_reg_reg[16:3]} ; + if (vidin_addr_reg_reg[8:3] == 43) + begin + vidin_addr_buf_sc_1_fifo <= {(vidin_addr_reg_reg[16:9] + 8'b00000001), 6'b000000} ; + end + else + begin + if (vidin_addr_reg_reg[8:3] == 44) + begin + vidin_addr_buf_sc_1_fifo <= {(vidin_addr_reg_reg[16:9] + 8'b00000001), 6'b000001} ; + end + else + begin + vidin_addr_buf_sc_1_fifo <= (vidin_addr_reg_reg[16:3]) + 2 ; + end + end + end + endcase + end + end +end + +always @(posedge tm3_clk_v0) + begin + vidin_rgb_reg_tmp <= vidin_rgb_reg ; + vidin_addr_reg_2to3 <= vidin_addr_reg ; + vidin_addr_reg_reg <= vidin_addr_reg ; + vidin_addr_reg_2to0 <= {vidin_addr_reg[1:0], vidin_addr_reg[10:9]} ; + vidin_new_data_fifo <= vidin_new_data ; + svid_comp_switch_2to3 <= svid_comp_switch ; + vidin_rgb_reg_fifo_left <= vidin_data_buf_fifo_sc_1_l ; + vidin_rgb_reg_fifo_right <= vidin_data_buf_fifo_sc_1_r ; + v_nd_s1_left <= v_nd_s1_left_2to0 ; + v_nd_s2_left <= v_nd_s2_left_2to0 ; + v_nd_s4_left <= v_nd_s4_left_2to0 ; + v_d_reg_s1_left <= v_d_reg_s1_left_2to0 ; + v_d_reg_s2_left <= v_d_reg_s2_left_2to0 ; + v_d_reg_s4_left <= v_d_reg_s4_left_2to0 ; + v_nd_s1_right <= v_nd_s1_right_2to0 ; + v_nd_s2_right <= v_nd_s2_right_2to0 ; + v_nd_s4_right <= v_nd_s4_right_2to0 ; + v_d_reg_s1_right <= v_d_reg_s1_right_2to0 ; + v_d_reg_s2_right <= v_d_reg_s2_right_2to0 ; + v_d_reg_s4_right <= v_d_reg_s4_right_2to0 ; + end +endmodule + + + +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.7 ,2001 +// By: Ahmad darabiha +module h_fltr (tm3_clk_v0, vidin_new_data, vidin_in_f1, vidin_in_f2, vidin_in_f3, vidin_in_h1, vidin_in_h2, vidin_in_h3, vidin_in_h4, real_z_reg, imag_z_reg, real_p_reg, imag_p_reg, real_n_reg, imag_n_reg); + + input tm3_clk_v0; + input vidin_new_data; + input[15:0] vidin_in_f1; + input[15:0] vidin_in_f2; + input[15:0] vidin_in_f3; + input[15:0] vidin_in_h1; + input[15:0] vidin_in_h2; + input[15:0] vidin_in_h3; + input[15:0] vidin_in_h4; + output[15:0] real_z_reg; + reg[15:0] real_z_reg; + output[15:0] imag_z_reg; + reg[15:0] imag_z_reg; + output[15:0] real_p_reg; + reg[15:0] real_p_reg; + output[15:0] imag_p_reg; + reg[15:0] imag_p_reg; + output[15:0] real_n_reg; + reg[15:0] real_n_reg; + output[15:0] imag_n_reg; + reg[15:0] imag_n_reg; + + wire[27:0] vidin_out_temp_f1; + reg[27:0] vidin_out_reg_f1; + wire my_fir_rdy_f1; + wire[27:0] vidin_out_temp_f2; + reg[27:0] vidin_out_reg_f2; + wire my_fir_rdy_f2; + wire[27:0] vidin_out_temp_f3; + reg[27:0] vidin_out_reg_f3; + wire my_fir_rdy_f3; + wire[27:0] vidin_out_temp_h1; + reg[27:0] vidin_out_reg_h1; + wire my_fir_rdy_h1; + wire[27:0] vidin_out_temp_h2; + reg[27:0] vidin_out_reg_h2; + wire my_fir_rdy_h2; + wire[27:0] vidin_out_temp_h3; + reg[27:0] vidin_out_reg_h3; + wire my_fir_rdy_h3; + wire[27:0] vidin_out_temp_h4; + reg[27:0] vidin_out_reg_h4; + wire my_fir_rdy_h4; + wire[28:0] sum_tmp_1; + wire[28:0] sum_tmp_2; + + wire[28:0] sum_tmp_3; + wire[28:0] sum_tmp_4; + wire[30:0] sum_tmp_5; + wire[15:0] real_p; + wire[15:0] imag_p; + wire[15:0] real_z; + wire[15:0] imag_z; + wire[15:0] real_n; + wire[15:0] imag_n; + wire[16:0] tmp; + + my_fir_f1 your_instance_name_f1 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f1, vidin_in_f2, vidin_out_temp_f1); + my_fir_f2 your_instance_name_f2 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f2, vidin_in_f1, vidin_out_temp_f2); + my_fir_f3 your_instance_name_f3 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f3, vidin_in_f3, vidin_out_temp_f3); + my_fir_h1 your_instance_name_h1 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h1, vidin_in_h2, vidin_out_temp_h1); + my_fir_h2 your_instance_name_h2 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h2, vidin_in_h1, vidin_out_temp_h2); + my_fir_h3 your_instance_name_h3 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h3, vidin_in_h4, vidin_out_temp_h3); + my_fir_h4 your_instance_name_h4 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h4, vidin_in_h3, vidin_out_temp_h4); + steer_fltr my_steer_fltr_inst (tm3_clk_v0, vidin_new_data, vidin_out_reg_f1, vidin_out_reg_f2, vidin_out_reg_f3, vidin_out_reg_h1, vidin_out_reg_h2, vidin_out_reg_h3, vidin_out_reg_h4, real_z, imag_z, real_p, imag_p, real_n, imag_n); + + always @(posedge tm3_clk_v0) + begin + if (my_fir_rdy_f1 == 1'b1) + begin + vidin_out_reg_f1 <= vidin_out_temp_f1 ; + end + if (my_fir_rdy_f2 == 1'b1) + begin + vidin_out_reg_f2 <= vidin_out_temp_f2 ; + end + if (my_fir_rdy_f3 == 1'b1) + begin + vidin_out_reg_f3 <= vidin_out_temp_f3 ; + end + if (my_fir_rdy_h1 == 1'b1) + begin + vidin_out_reg_h1 <= vidin_out_temp_h1 ; + end + if (my_fir_rdy_h2 == 1'b1) + begin + vidin_out_reg_h2 <= vidin_out_temp_h2 ; + end + if (my_fir_rdy_h3 == 1'b1) + begin + vidin_out_reg_h3 <= vidin_out_temp_h3 ; + + end + if (my_fir_rdy_h4 == 1'b1) + begin + vidin_out_reg_h4 <= vidin_out_temp_h4 ; + end + end + + always @(posedge tm3_clk_v0) + begin + real_z_reg <= real_z ; + imag_z_reg <= imag_z ; + real_p_reg <= real_p ; + imag_p_reg <= imag_p ; + real_n_reg <= real_n ; + imag_n_reg <= imag_n ; + end +endmodule +module steer_fltr (clk, new_data, f1, f2, f3, h1, h2, h3, h4, re_z, im_z, re_p, im_p, re_n, im_n); + + input clk; + input new_data; + input[27:0] f1; + input[27:0] f2; + input[27:0] f3; + input[27:0] h1; + input[27:0] h2; + input[27:0] h3; + input[27:0] h4; + output[15:0] re_z; + reg[15:0] re_z; + output[15:0] im_z; + reg[15:0] im_z; + output[15:0] re_p; + reg[15:0] re_p; + output[15:0] im_p; + reg[15:0] im_p; + output[15:0] re_n; + reg[15:0] re_n; + output[15:0] im_n; + reg[15:0] im_n; + + reg[27:0] f1_reg; + reg[27:0] f2_reg; + reg[27:0] f3_reg; + reg[27:0] h1_reg; + reg[27:0] h2_reg; + reg[27:0] h3_reg; + reg[27:0] h4_reg; + reg[28:0] re_z_tmp_1; + reg[28:0] im_z_tmp_1; + reg[28:0] re_p_tmp_1; + reg[28:0] re_p_tmp_2; + reg[28:0] re_p_tmp_3; + reg[28:0] im_p_tmp_1; + reg[28:0] im_p_tmp_2; + reg[28:0] im_p_tmp_3; + reg[28:0] im_p_tmp_4; + reg[30:0] re_z_tmp; + reg[30:0] im_z_tmp; + reg[30:0] re_p_tmp; + reg[30:0] im_p_tmp; + reg[30:0] re_n_tmp; + reg[30:0] im_n_tmp; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + f1_reg <= f1 ; + f2_reg <= f2 ; + f3_reg <= f3 ; + h1_reg <= h1 ; + h2_reg <= h2 ; + h3_reg <= h3 ; + h4_reg <= h4 ; + end + end + + always @(posedge clk) + begin + re_z_tmp_1 <= {f1_reg[27], f1_reg} ; + im_z_tmp_1 <= {h1_reg[27], h1_reg} ; + re_p_tmp_1 <= {f1_reg[27], f1_reg[27], f1_reg[27:1]} ; + re_p_tmp_2 <= {f3_reg[27], f3_reg[27:0]} ; + re_p_tmp_3 <= {f2_reg[27], f2_reg[27], f2_reg[27:1]} ; + im_p_tmp_1 <= ({h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27:2]}) + ({h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27:3]}) ; + im_p_tmp_2 <= ({h4_reg[27], h4_reg}) + ({h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27:4]}) ; + im_p_tmp_3 <= ({h3_reg[27], h3_reg}) + ({h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27:4]}) ; + im_p_tmp_4 <= ({h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27:2]}) + ({h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27:3]}) ; + re_z_tmp <= {re_z_tmp_1[28], re_z_tmp_1[28], re_z_tmp_1} ; + im_z_tmp <= {im_z_tmp_1[28], im_z_tmp_1[28], im_z_tmp_1} ; + re_p_tmp <= ({re_p_tmp_1[28], re_p_tmp_1[28], re_p_tmp_1}) - ({re_p_tmp_2[28], re_p_tmp_2[28], re_p_tmp_2}) + ({re_p_tmp_3[28], re_p_tmp_3[28], re_p_tmp_3}) ; + im_p_tmp <= ({im_p_tmp_1[28], im_p_tmp_1[28], im_p_tmp_1}) - ({im_p_tmp_2[28], im_p_tmp_2[28], im_p_tmp_2}) + ({im_p_tmp_3[28], im_p_tmp_3[28], im_p_tmp_3}) - ({im_p_tmp_4[28], im_p_tmp_4[28], im_p_tmp_4}) ; + re_n_tmp <= ({re_p_tmp_1[28], re_p_tmp_1[28], re_p_tmp_1}) + ({re_p_tmp_2[28], re_p_tmp_2[28], re_p_tmp_2}) + ({re_p_tmp_3[28], re_p_tmp_3[28], re_p_tmp_3}) ; + im_n_tmp <= ({im_p_tmp_1[28], im_p_tmp_1[28], im_p_tmp_1}) + ({im_p_tmp_2[28], im_p_tmp_2[28], im_p_tmp_2}) + ({im_p_tmp_3[28], im_p_tmp_3[28], im_p_tmp_3}) + ({im_p_tmp_4[28], im_p_tmp_4[28], im_p_tmp_4}) ; + re_z <= re_z_tmp[30:15] ; + im_z <= im_z_tmp[30:15] ; + re_p <= re_p_tmp[30:15] ; + im_p <= im_p_tmp[30:15] ; + re_n <= re_n_tmp[30:15] ; + im_n <= im_n_tmp[30:15] ; + end +endmodule + + + + +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_496x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 9'b111110000; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo496 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo496 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo496 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo496 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo496 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo496 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo496 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module v_fltr_316x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 9'b100111100; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo316 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo316 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo316 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo316 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo316 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo316 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo316 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module v_fltr_226x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 8'b11100010; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo226 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo226 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo226 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo226 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo226 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo226 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo226 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module fltr_compute_f1 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b11101; + q2 <= din[47:40] * 7'b1100101; + q3 <= din[39:32] * 5'b10001; + q4 <= din[31:24] * 9'b100010101; + q5 <= din[23:16] * 5'b10001; + q6 <= din[15:8] * 7'b1100101; + q7 <= din[7:0] * 5'b11101; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule +module fltr_compute_f2 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 3'b100; + q2 <= din[47:40] * 6'b101010; + q3 <= din[39:32] * 8'b10100011; + q4 <= din[31:24] * 8'b11111111; + q5 <= din[23:16] * 8'b10100011; + q6 <= din[15:8] * 6'b101010; + q7 <= din[7:0] * 3'b100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule + + + + + + + + + +module fltr_compute_f3 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10100; + q2 <= din[47:40] * 8'b10110011; + q3 <= din[39:32] * 9'b101101100; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 9'b101101100; + q6 <= din[15:8] * 8'b10110011; + q7 <= din[7:0] * 5'b10100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + + endmodule +module fltr_compute_h1 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10001; + q2 <= din[47:40] * 5'b11001; + q3 <= din[39:32] * 8'b11000001; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 8'b11000001; + q6 <= din[15:8] * 5'b11001; + q7 <= din[7:0] * 5'b10001; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule + + +module fltr_compute_h2 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 3'b100; + q2 <= din[47:40] * 6'b101010; + q3 <= din[39:32] * 8'b10100011; + q4 <= din[31:24] * 8'b11111111; + q5 <= din[23:16] * 8'b10100011; + q6 <= din[15:8] * 6'b101010; + q7 <= din[7:0] * 3'b100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + + + + +module fltr_compute_h3 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10111; + q2 <= din[47:40] * 7'b1001000; + q3 <= din[39:32] * 8'b10010011; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 8'b10010011; + q6 <= din[15:8] * 7'b1001000; + q7 <= din[7:0] * 5'b10111; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + +module fltr_compute_h4 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 4'b1110; + q2 <= din[47:40] * 6'b101011; + q3 <= din[39:32] * 7'b1010000; + q4 <= din[31:24] * 9'b101000100; + q5 <= din[23:16] * 7'b1010000; + q6 <= din[15:8] * 6'b101011; + q7 <= din[7:0] * 4'b1110; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + + + +// Discription: this block creates a long fifo + + // of lengh of the specified length as an input + // parameter and with a specified width + + // date: Oct.7 ,2001 + // By: Ahmad darabiha + + `define WIDTH_4B 4'b1000 + + +module fifo496 (clk, wen, din, dout); + +// parameter WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + + + + + + + + + + + + + + + + + + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module fifo316 (clk, wen, din, dout); + +// parameter `WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module fifo226 (clk, wen, din, dout); + +// parameter `WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module port_bus_2to1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, + vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, + vidin_data_reg_scld_2_2to3_left_rp, vidin_data_reg_scld_2_2to3_left_ip, + vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, + vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, + vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, + vidin_data_reg_scld_1_2to3_right_rn, vidin_data_reg_scld_1_2to3_right_in, + vidin_data_reg_scld_2_2to3_right_rp, vidin_data_reg_scld_2_2to3_right_ip, + vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_data_reg_scld_4_2to3_right_rp, vidin_data_reg_scld_4_2to3_right_ip, + vidin_data_reg_scld_4_2to3_right_rn, vidin_data_reg_scld_4_2to3_right_in, + bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out); + input clk; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + input vidin_new_data_scld_1_2to3_left; + input[15:0] vidin_data_reg_scld_1_2to3_left_rp; + input[15:0] vidin_data_reg_scld_1_2to3_left_ip; + input[15:0] vidin_data_reg_scld_1_2to3_left_rn; + input[15:0] vidin_data_reg_scld_1_2to3_left_in; + input[15:0] vidin_data_reg_scld_2_2to3_left_rp; + input[15:0] vidin_data_reg_scld_2_2to3_left_ip; + input[15:0] vidin_data_reg_scld_2_2to3_left_rn; + input[15:0] vidin_data_reg_scld_2_2to3_left_in; + input[15:0] vidin_data_reg_scld_4_2to3_left_rp; + input[15:0] vidin_data_reg_scld_4_2to3_left_ip; + input[15:0] vidin_data_reg_scld_4_2to3_left_rn; + input[15:0] vidin_data_reg_scld_4_2to3_left_in; + input[15:0] vidin_data_reg_scld_1_2to3_right_rp; + input[15:0] vidin_data_reg_scld_1_2to3_right_ip; + input[15:0] vidin_data_reg_scld_1_2to3_right_rn; + input[15:0] vidin_data_reg_scld_1_2to3_right_in; + input[15:0] vidin_data_reg_scld_2_2to3_right_rp; + input[15:0] vidin_data_reg_scld_2_2to3_right_ip; + input[15:0] vidin_data_reg_scld_2_2to3_right_rn; + input[15:0] vidin_data_reg_scld_2_2to3_right_in; + input[15:0] vidin_data_reg_scld_4_2to3_right_rp; + input[15:0] vidin_data_reg_scld_4_2to3_right_ip; + input[15:0] vidin_data_reg_scld_4_2to3_right_rn; + input[15:0] vidin_data_reg_scld_4_2to3_right_in; + output[15:0] bus_word_3; + reg[15:0] bus_word_3; + output[15:0] bus_word_4; + reg[15:0] bus_word_4; + output[15:0] bus_word_5; + reg[15:0] bus_word_5; + output[15:0] bus_word_6; + reg[15:0] bus_word_6; + output[2:0] counter_out; + reg[2:0] counter_out; + + reg[15:0] bus_word_3_tmp; + reg[15:0] bus_word_4_tmp; + reg[15:0] bus_word_5_tmp; + reg[15:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_2to3_left_tmp; + wire vidin_new_data_scld_2_2to3_left_tmp; + wire vidin_new_data_scld_4_2to3_left_tmp; + wire vidin_new_data_scld_1_2to3_right_tmp; + wire vidin_new_data_scld_2_2to3_right_tmp; + wire vidin_new_data_scld_4_2to3_right_tmp; + reg[3:0] counter; + reg[2:0] counter_out_tmp; + + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in_tmp; + + always @(posedge clk) + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + counter <= 4'b0001 ; + end + else + begin + case (counter) + 4'b0000 : + begin + counter <= 4'b1000 ; + end + 4'b0001 : + begin + counter <= 4'b0010 ; + end + 4'b0010 : + begin + counter <= 4'b0011 ; + end + 4'b0011 : + begin + counter <= 4'b0100 ; + end + 4'b0100 : + begin + counter <= 4'b0101 ; + end + 4'b0101 : + begin + counter <= 4'b0110 ; + end + 4'b0110 : + begin + counter <= 4'b0111 ; + end + 4'b0111 : + begin + counter <= 4'b1000 ; + end + 4'b1000 : + begin + counter <= 4'b1000 ; + end + default : + begin + counter <= 4'b1000 ; + end + endcase + end + end + + always @(posedge clk) + begin + case (counter[2:0]) + 3'b000 : + begin + counter_out_tmp <= 3'b000 ; + bus_word_3_tmp <= 16'b0000000000000000 ; + bus_word_4_tmp <= 16'b0000000000000000 ; + bus_word_5_tmp <= 16'b0000000000000000 ; + bus_word_6_tmp <= 16'b0000000000000000 ; + end + 3'b001 : + begin + counter_out_tmp <= 3'b001 ; + bus_word_3_tmp <= vidin_addr_reg_tmp[15:0] ; + bus_word_4_tmp <= {vidin_addr_reg_tmp[18:16], svid_comp_switch_tmp, 12'b000000000000} ; + bus_word_5_tmp <= 16'b0000000000000000 ; + bus_word_6_tmp <= 16'b0000000000000000 ; + end + 3'b010 : + begin + counter_out_tmp <= 3'b010 ; + bus_word_3_tmp <= vidin_data_reg_scld_1_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_1_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_1_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_1_2to3_left_in_tmp ; + end + 3'b011 : + begin + counter_out_tmp <= 3'b011 ; + bus_word_3_tmp <= vidin_data_reg_scld_1_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_1_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_1_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_1_2to3_right_in_tmp ; + end + 3'b100 : + begin + counter_out_tmp <= 3'b100 ; + bus_word_3_tmp <= vidin_data_reg_scld_2_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_2_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_2_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_2_2to3_left_in_tmp ; + end + 3'b101 : + begin + counter_out_tmp <= 3'b101 ; + bus_word_3_tmp <= vidin_data_reg_scld_2_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_2_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_2_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_2_2to3_right_in_tmp ; + end + + 3'b110 : + begin + counter_out_tmp <= 3'b110 ; + bus_word_3_tmp <= vidin_data_reg_scld_4_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_4_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_4_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_4_2to3_left_in_tmp ; + end + 3'b111 : + begin + counter_out_tmp <= 3'b111 ; + bus_word_3_tmp <= vidin_data_reg_scld_4_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_4_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_4_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_4_2to3_right_in_tmp ; + end + endcase + end + + always @(posedge clk) + begin + counter_out <= counter_out_tmp ; + bus_word_3 <= bus_word_3_tmp ; + bus_word_4 <= bus_word_4_tmp ; + bus_word_5 <= bus_word_5_tmp ; + bus_word_6 <= bus_word_6_tmp ; + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + vidin_addr_reg_tmp <= vidin_addr_reg ; + svid_comp_switch_tmp <= svid_comp_switch ; + vidin_data_reg_scld_1_2to3_left_rp_tmp <= vidin_data_reg_scld_1_2to3_left_rp ; + vidin_data_reg_scld_2_2to3_left_rp_tmp <= vidin_data_reg_scld_2_2to3_left_rp ; + vidin_data_reg_scld_4_2to3_left_rp_tmp <= vidin_data_reg_scld_4_2to3_left_rp ; + vidin_data_reg_scld_1_2to3_right_rp_tmp <= vidin_data_reg_scld_1_2to3_right_rp ; + vidin_data_reg_scld_2_2to3_right_rp_tmp <= vidin_data_reg_scld_2_2to3_right_rp ; + vidin_data_reg_scld_4_2to3_right_rp_tmp <= vidin_data_reg_scld_4_2to3_right_rp ; + vidin_data_reg_scld_1_2to3_left_ip_tmp <= vidin_data_reg_scld_1_2to3_left_ip ; + vidin_data_reg_scld_2_2to3_left_ip_tmp <= vidin_data_reg_scld_2_2to3_left_ip ; + vidin_data_reg_scld_4_2to3_left_ip_tmp <= vidin_data_reg_scld_4_2to3_left_ip ; + vidin_data_reg_scld_1_2to3_right_ip_tmp <= vidin_data_reg_scld_1_2to3_right_ip ; + vidin_data_reg_scld_2_2to3_right_ip_tmp <= vidin_data_reg_scld_2_2to3_right_ip ; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= vidin_data_reg_scld_4_2to3_right_ip ; + vidin_data_reg_scld_1_2to3_left_rn_tmp <= vidin_data_reg_scld_1_2to3_left_rn ; + vidin_data_reg_scld_2_2to3_left_rn_tmp <= vidin_data_reg_scld_2_2to3_left_rn ; + vidin_data_reg_scld_4_2to3_left_rn_tmp <= vidin_data_reg_scld_4_2to3_left_rn ; + vidin_data_reg_scld_1_2to3_right_rn_tmp <= vidin_data_reg_scld_1_2to3_right_rn ; + vidin_data_reg_scld_2_2to3_right_rn_tmp <= vidin_data_reg_scld_2_2to3_right_rn ; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= vidin_data_reg_scld_4_2to3_right_rn ; + vidin_data_reg_scld_1_2to3_left_in_tmp <= vidin_data_reg_scld_1_2to3_left_in ; + vidin_data_reg_scld_2_2to3_left_in_tmp <= vidin_data_reg_scld_2_2to3_left_in ; + vidin_data_reg_scld_4_2to3_left_in_tmp <= vidin_data_reg_scld_4_2to3_left_in ; + vidin_data_reg_scld_1_2to3_right_in_tmp <= vidin_data_reg_scld_1_2to3_right_in ; + vidin_data_reg_scld_2_2to3_right_in_tmp <= vidin_data_reg_scld_2_2to3_right_in ; + vidin_data_reg_scld_4_2to3_right_in_tmp <= vidin_data_reg_scld_4_2to3_right_in ; + end + end +endmodule + + +`define COEF0_b 29 + `define COEF1_b 101 +// `define COEF2_b -15 +// `define COEF3_b -235 +// `define COEF4_b -15 + `define COEF2_b 15 + `define COEF3_b 235 + `define COEF4_b 15 + `define COEF5_b 101 + `define COEF6_b 29 + + `define WIDTH_5B 5'b10000 + +module my_fir_f1 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=29,101,-15,-235,-15,101,29; + + //parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_b) + + (n_delay_reg1 * `COEF1_b) + + (n_delay_reg2 * `COEF2_b) + + (n_delay_reg3 * `COEF3_b) + + (n_delay_reg4 * `COEF4_b) + + (n_delay_reg5 * `COEF5_b) + + (n_delay_reg6 * `COEF6_b); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + `define COEF0_c 4 + `define COEF1_c 42 + `define COEF2_c 163 + `define COEF3_c 255 + `define COEF4_c 163 + `define COEF5_c 42 + `define COEF6_c 4 + +module my_fir_f2 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=4,42,163,255,163,42,4; + + +// parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_c) + + (n_delay_reg1 * `COEF1_c) + + (n_delay_reg2 * `COEF2_c) + + (n_delay_reg3 * `COEF3_c) + + (n_delay_reg4 * `COEF4_c) + + (n_delay_reg5 * `COEF5_c) + + (n_delay_reg6 * `COEF6_c); + + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_d -12 +// `define COEF1_d -77 +// `define COEF2_d -148 + `define COEF0_d 12 + `define COEF1_d 77 + `define COEF2_d 148 + `define COEF3_d 0 + `define COEF4_d 148 + `define COEF5_d 77 + `define COEF6_d 12 + +module my_fir_f3 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-12,-77,-148,0,148,77,12; + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_d) + + (n_delay_reg1 * `COEF1_d) + + (n_delay_reg2 * `COEF2_d) + + (n_delay_reg4 * `COEF4_d) + + (n_delay_reg5 * `COEF5_d) + + (n_delay_reg6 * `COEF6_d); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + + `define COEF0_1 15 +//`define COEF0_1 -15 + `define COEF1_1 25 + `define COEF2_1 193 + `define COEF3_1 0 +// `define COEF4_1 -193 +// `define COEF5_1 -25 + `define COEF4_1 193 + `define COEF5_1 25 + `define COEF6_1 15 + +module my_fir_h1 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-15,25,193,0,-193,-25,15; + + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_1) + + (n_delay_reg1 * `COEF1_1) + + (n_delay_reg2 * `COEF2_1) + + (n_delay_reg4 * `COEF4_1) + + (n_delay_reg5 * `COEF5_1) + + (n_delay_reg6 * `COEF6_1); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + + `define COEF0_2 4 + `define COEF1_2 42 + `define COEF2_2 163 + `define COEF3_2 255 + `define COEF4_2 163 + `define COEF5_2 42 + `define COEF6_2 4 + +module my_fir_h2 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=4,42,163,255,163,42,4; + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_2) + + (n_delay_reg1 * `COEF1_2) + + (n_delay_reg2 * `COEF2_2) + + (n_delay_reg3 * `COEF3_2) + + (n_delay_reg4 * `COEF4_2) + + (n_delay_reg5 * `COEF5_2) + + (n_delay_reg6 * `COEF6_2); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_3 -9 +// `define COEF1_3 -56 +// `define COEF2_3 -109 + `define COEF0_3 9 + `define COEF1_3 56 + `define COEF2_3 109 + `define COEF3_3 0 + `define COEF4_3 109 + `define COEF5_3 56 + `define COEF6_3 9 + + +module my_fir_h3 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-9,-56,-109,0,109,56,9; +// parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_3) + + (n_delay_reg1 * `COEF1_3) + + (n_delay_reg2 * `COEF2_3) + + (n_delay_reg4 * `COEF4_3) + + (n_delay_reg5 * `COEF5_3) + + (n_delay_reg6 * `COEF6_3); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_4 -9 +// `define COEF1_4 -56 +// `define COEF2_4 -109 + `define COEF0_4 9 + `define COEF1_4 56 + `define COEF2_4 109 + `define COEF3_4 0 + `define COEF4_4 109 + `define COEF5_4 56 + `define COEF6_4 9 + + +module my_fir_h4 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-9,-56,-109,0,109,56,9; + // parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_4) + + (n_delay_reg1 * `COEF1_4) + + (n_delay_reg2 * `COEF2_4) + + (n_delay_reg4 * `COEF4_4) + + (n_delay_reg5 * `COEF5_4) + + (n_delay_reg6 * `COEF6_4); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v new file mode 100755 index 000000000..1b3e343a2 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v @@ -0,0 +1,1054 @@ +// originally created by Marcus van Ierssel +// modified by Ahmad Darabiha, Feb. 2002 +// this circuit receives the rgbvideo signal +// from video input and send it to chip #2 +// for buffring and processing. +module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vidin_vs, tm3_vidin_href, tm3_vidin_cref, tm3_vidin_rts0, tm3_vidin_vpo, tm3_vidin_sda, tm3_vidin_scl, vidin_new_data, vidin_rgb_reg, vidin_addr_reg); + + input tm3_clk_v0; + input tm3_clk_v2; + input tm3_vidin_llc; + input tm3_vidin_vs; + input tm3_vidin_href; + input tm3_vidin_cref; + input tm3_vidin_rts0; + input[15:0] tm3_vidin_vpo; + output tm3_vidin_sda; + wire tm3_vidin_sda; + reg tm3_vidin_sda_xhdl0; + output tm3_vidin_scl; + reg tm3_vidin_scl; + output vidin_new_data; + reg vidin_new_data; + output[7:0] vidin_rgb_reg; + reg[7:0] vidin_rgb_reg; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + + reg temp_reg1; + reg temp_reg2; + reg[9:0] horiz; + reg[7:0] vert; + reg creg1; + reg creg2; + reg creg3; + reg[18:0] vidin_addr_reg1; + reg[23:0] vidin_rgb_reg1; + reg[23:0] vidin_rgb_reg2; + parameter[4:0] reg_prog1 = 5'b00001; + parameter[4:0] reg_prog2 = 5'b00010; + parameter[4:0] reg_prog3 = 5'b00011; + parameter[4:0] reg_prog4 = 5'b00100; + parameter[4:0] reg_prog5 = 5'b00101; + parameter[4:0] reg_prog6 = 5'b00110; + parameter[4:0] reg_prog7 = 5'b00111; + parameter[4:0] reg_prog8 = 5'b01000; + parameter[4:0] reg_prog9 = 5'b01001; + parameter[4:0] reg_prog10 = 5'b01010; + parameter[4:0] reg_prog11 = 5'b01011; + parameter[4:0] reg_prog12 = 5'b01100; + parameter[4:0] reg_prog13 = 5'b01101; + parameter[4:0] reg_prog14 = 5'b01110; + parameter[4:0] reg_prog15 = 5'b01111; + parameter[4:0] reg_prog16 = 5'b10000; + parameter[4:0] reg_prog17 = 5'b10001; + parameter[4:0] reg_prog18 = 5'b10010; + parameter[4:0] reg_prog19 = 5'b10011; + parameter[4:0] reg_prog20 = 5'b10100; + parameter[4:0] reg_prog21 = 5'b10101; + parameter[4:0] reg_prog22 = 5'b10110; + parameter[4:0] reg_prog23 = 5'b10111; + parameter[4:0] reg_prog24 = 5'b11000; + parameter[4:0] reg_prog25 = 5'b11001; + parameter[4:0] reg_prog26 = 5'b11010; + parameter[4:0] reg_prog_end = 5'b11011; + reg rst; + reg rst_done; + reg[7:0] iicaddr; + reg[7:0] iicdata; +// wire vidin_llc; +// wire vidin_llc_int; + reg[6:0] iic_state; + reg iic_stop; + reg iic_start; + reg[4:0] reg_prog_state; + reg[4:0] reg_prog_nextstate; + + assign tm3_vidin_sda = tm3_vidin_sda_xhdl0; + + // ibuf ibuf_inst (tm3_vidin_llc, vidin_llc_int); +// bufg bufg_inst (vidin_llc_int, vidin_llc); + + // PAJ double clock is trouble...always @(vidin_llc) + always @(posedge tm3_clk_v0) + begin + if (tm3_vidin_href == 1'b0) + begin + horiz <= 10'b0000000000 ; + end + else + begin + if (tm3_vidin_cref == 1'b0) + begin + horiz <= horiz + 1 ; + end + end + if (tm3_vidin_vs == 1'b1) + begin + vert <= 8'b00000000 ; + end + else + begin + if ((tm3_vidin_href == 1'b0) & (horiz != 10'b0000000000)) + begin + vert <= vert + 1 ; + end + end + if (tm3_vidin_cref == 1'b1) + begin + vidin_rgb_reg1[23:19] <= tm3_vidin_vpo[15:11] ; + vidin_rgb_reg1[15:13] <= tm3_vidin_vpo[10:8] ; + vidin_rgb_reg1[18:16] <= tm3_vidin_vpo[7:5] ; + vidin_rgb_reg1[9:8] <= tm3_vidin_vpo[4:3] ; + vidin_rgb_reg1[2:0] <= tm3_vidin_vpo[2:0] ; + vidin_rgb_reg2 <= vidin_rgb_reg1 ; + end + else + begin + vidin_rgb_reg1[12:10] <= tm3_vidin_vpo[7:5] ; + vidin_rgb_reg1[7:3] <= tm3_vidin_vpo[4:0] ; + vidin_addr_reg1 <= {vert, tm3_vidin_rts0, horiz} ; + end + end + + always @(posedge tm3_clk_v0) + begin + creg1 <= tm3_vidin_cref ; + creg2 <= creg1 ; + creg3 <= creg2 ; + if ((creg2 == 1'b0) & (creg3 == 1'b1) & ((vidin_addr_reg1[10]) == 1'b0) & ((vidin_addr_reg1[0]) == 1'b0)) + begin + vidin_new_data <= 1'b1 ; + vidin_rgb_reg <= vidin_rgb_reg2[7:0] ; + vidin_addr_reg <= {({2'b00, vidin_addr_reg1[18:11]}), vidin_addr_reg1[9:1]} ; + end + else + begin + vidin_new_data <= 1'b0 ; + end + end + + always @(posedge tm3_clk_v2) + begin + // A: Worked around scope issue by moving iic_stop into every case. + case (iic_state) + 7'b0000000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0100010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0100101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0111010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0111101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1010000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1010001 : + begin + iic_stop <= 1'b1 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + default : + begin + iic_stop <= 1'b1 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + endcase + end + + always @(reg_prog_state or iic_stop) + begin + case (reg_prog_state) + reg_prog1 : + begin + rst_done = 1'b1 ; + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog2 ; + end + else + begin + reg_prog_nextstate = reg_prog1 ; + end + + end + reg_prog2 : + begin + iicaddr = 8'b00000010 ; + iicdata = {5'b11000, 3'b000} ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog3 ; + end + else + begin + reg_prog_nextstate = reg_prog2 ; + end + end + reg_prog3 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog4 ; + end + else + begin + reg_prog_nextstate = reg_prog3 ; + end + end + reg_prog4 : + begin + iicaddr = 8'b00000011 ; + iicdata = 8'b00100011 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog5 ; + end + else + begin + reg_prog_nextstate = reg_prog4 ; + end + end + reg_prog5 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog6 ; + end + else + begin + reg_prog_nextstate = reg_prog5 ; + end + end + reg_prog6 : + begin + iicaddr = 8'b00000110 ; + iicdata = 8'b11101011 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog7 ; + end + else + begin + + reg_prog_nextstate = reg_prog6 ; + end + end + reg_prog7 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog8 ; + end + else + begin + reg_prog_nextstate = reg_prog7 ; + end + end + reg_prog8 : + begin + iicaddr = 8'b00000111 ; + iicdata = 8'b11100000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog9 ; + end + else + begin + reg_prog_nextstate = reg_prog8 ; + end + end + reg_prog9 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog10 ; + end + else + begin + reg_prog_nextstate = reg_prog9 ; + end + end + reg_prog10 : + begin + iicaddr = 8'b00001000 ; + iicdata = 8'b10000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog11 ; + end + else + begin + reg_prog_nextstate = reg_prog10 ; + end + end + reg_prog11 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog12 ; + end + + else + begin + reg_prog_nextstate = reg_prog11 ; + end + end + reg_prog12 : + begin + iicaddr = 8'b00001001 ; + iicdata = 8'b00000001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog13 ; + end + else + begin + reg_prog_nextstate = reg_prog12 ; + end + end + reg_prog13 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog14 ; + end + else + begin + reg_prog_nextstate = reg_prog13 ; + end + end + reg_prog14 : + begin + iicaddr = 8'b00001010 ; + iicdata = 8'b10000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog15 ; + end + else + begin + reg_prog_nextstate = reg_prog14 ; + end + end + reg_prog15 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog16 ; + end + else + begin + reg_prog_nextstate = reg_prog15 ; + end + end + reg_prog16 : + begin + iicaddr = 8'b00001011 ; + iicdata = 8'b01000111 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + + begin + reg_prog_nextstate = reg_prog17 ; + end + else + begin + reg_prog_nextstate = reg_prog16 ; + end + end + reg_prog17 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog18 ; + end + else + begin + reg_prog_nextstate = reg_prog17 ; + end + end + reg_prog18 : + begin + iicaddr = 8'b00001100 ; + iicdata = 8'b01000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog19 ; + end + else + begin + reg_prog_nextstate = reg_prog18 ; + end + end + reg_prog19 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog20 ; + end + else + begin + reg_prog_nextstate = reg_prog19 ; + end + end + reg_prog20 : + begin + iicaddr = 8'b00001110 ; + iicdata = 8'b00000001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog21 ; + end + else + begin + reg_prog_nextstate = reg_prog20 ; + end + end + reg_prog21 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog22 ; + end + else + begin + reg_prog_nextstate = reg_prog21 ; + end + end + reg_prog22 : + begin + iicaddr = 8'b00010000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog23 ; + end + else + begin + reg_prog_nextstate = reg_prog22 ; + end + end + reg_prog23 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog24 ; + end + else + begin + reg_prog_nextstate = reg_prog23 ; + end + end + reg_prog24 : + begin + iicaddr = 8'b00010001 ; + iicdata = 8'b00011100 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog25 ; + end + else + begin + reg_prog_nextstate = reg_prog24 ; + end + end + reg_prog25 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog26 ; + end + else + begin + reg_prog_nextstate = reg_prog25 ; + end + end + reg_prog26 : + begin + iicaddr = 8'b00010010 ; + iicdata = 8'b00001001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog_end ; + end + else + begin + reg_prog_nextstate = reg_prog26 ; + end + end + reg_prog_end : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b0 ; + reg_prog_nextstate = reg_prog_end ; + end + endcase + end + + always @(posedge tm3_clk_v2) + begin + if (rst_done == 1'b1) + begin + rst <= 1'b1 ; + end + temp_reg1 <= tm3_vidin_rts0 ; + temp_reg2 <= temp_reg1 ; + if (rst == 1'b0) + begin + reg_prog_state <= reg_prog1 ; + end + else if ((temp_reg1 == 1'b0) & (temp_reg2 == 1'b1)) + begin + reg_prog_state <= reg_prog1 ; + end + else + begin + reg_prog_state <= reg_prog_nextstate ; + end + if (iic_stop == 1'b0) + begin + iic_state <= iic_state + 1 ; + end + else if (iic_start == 1'b1) + begin + iic_state <= 7'b0000001 ; + end + end +endmodule + + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v b/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v new file mode 100644 index 000000000..718cd3671 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v @@ -0,0 +1,5711 @@ +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 16x16 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_16x16_systolic u_matmul (systolic 16x16 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (16x16 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 8.32 ns +// Clock frequency: 120.19 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.97532e+08 MWTAs +// Resource usage: 1556 LBs, 8 RAMs, 276 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3200 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 9.24 ns +// Clock frequency: 108.17 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 4.95598e+07 MWTAs +// Resource usage: 1477 LBs, 14 RAMs, 280 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3400 sec + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 16x16 matrix with a 16x16 matrix. +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 16 bytes of memory (i.e. 16 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 16 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020-09-27 21:12:45.762386 +// Design Name: +// Module Name: matmul_16x16_systolic +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module matmul_16x16_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + +final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_1; +wire [`DWIDTH-1:0] b4_data_delayed_2; +wire [`DWIDTH-1:0] b4_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_1; +wire [`DWIDTH-1:0] b5_data_delayed_2; +wire [`DWIDTH-1:0] b5_data_delayed_3; +wire [`DWIDTH-1:0] b5_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_1; +wire [`DWIDTH-1:0] b6_data_delayed_2; +wire [`DWIDTH-1:0] b6_data_delayed_3; +wire [`DWIDTH-1:0] b6_data_delayed_4; +wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), + +.final_mat_mul_size(final_mat_mul_size), + .matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, + +final_mat_mul_size, + matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; + input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((final_mat_mul_size<<2) - final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [16*`DWIDTH-1:0] c_data_out; +reg [16*`DWIDTH-1:0] c_data_out_1; +reg [16*`DWIDTH-1:0] c_data_out_2; +reg [16*`DWIDTH-1:0] c_data_out_3; +reg [16*`DWIDTH-1:0] c_data_out_4; +reg [16*`DWIDTH-1:0] c_data_out_5; +reg [16*`DWIDTH-1:0] c_data_out_6; +reg [16*`DWIDTH-1:0] c_data_out_7; +reg [16*`DWIDTH-1:0] c_data_out_8; +reg [16*`DWIDTH-1:0] c_data_out_9; +reg [16*`DWIDTH-1:0] c_data_out_10; +reg [16*`DWIDTH-1:0] c_data_out_11; +reg [16*`DWIDTH-1:0] c_data_out_12; +reg [16*`DWIDTH-1:0] c_data_out_13; +reg [16*`DWIDTH-1:0] c_data_out_14; +reg [16*`DWIDTH-1:0] c_data_out_15; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_1 <= {matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_2 <= {matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_3 <= {matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_4 <= {matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_5 <= {matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_6 <= {matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_7 <= {matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_8 <= {matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_9 <= {matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_10 <= {matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_11 <= {matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_12 <= {matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_13 <= {matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_14 <= {matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_15 <= {matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +assign a_data_out = {a15_15to15_16,a14_15to14_16,a13_15to13_16,a12_15to12_16,a11_15to11_16,a10_15to10_16,a9_15to9_16,a8_15to8_16,a7_15to7_16,a6_15to6_16,a5_15to5_16,a4_15to4_16,a3_15to3_16,a2_15to2_16,a1_15to1_16,a0_15to0_16}; +assign b_data_out = {b15_15to16_15,b15_14to16_14,b15_13to16_13,b15_12to16_12,b15_11to16_11,b15_10to16_10,b15_9to16_9,b15_8to16_8,b15_7to16_7,b15_6to16_6,b15_5to16_5,b15_4to16_4,b15_3to16_3,b15_2to16_2,b15_1to16_1,b15_0to16_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + out_temp <= 0; + end else begin + out_temp <= add_out; + end +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count = cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef SIMULATION + +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +reg [31:0] i; + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + + +endmodule + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count = cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count = cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_16x16_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd16), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v b/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v new file mode 100644 index 000000000..1e3f32683 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v @@ -0,0 +1,15437 @@ +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 32x32 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_32x32_systolic u_matmul (systolic 32x32 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (32x32 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 11.79 ns +// Clock frequency: 84.76 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 7.07642e+08 MWTAs +// Resource usage: 5150 LBs, 16 RAMs, 1064 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 11500 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 12.92 ns +// Clock frequency: 77.39 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.72408e+08 MWTAs +// Resource usage: 5033 LBs, 26 RAMs, 1072 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 12500 sec + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 32x32 matrix with a 32x32 matrix. +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 32 bytes of memory (i.e. 32 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 32 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020-09-27 21:12:45.762386 +// Design Name: +// Module Name: matmul_32x32_systolic +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module matmul_32x32_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + + final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((`final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_1; +wire [`DWIDTH-1:0] a16_data_delayed_2; +wire [`DWIDTH-1:0] a16_data_delayed_3; +wire [`DWIDTH-1:0] a16_data_delayed_4; +wire [`DWIDTH-1:0] a16_data_delayed_5; +wire [`DWIDTH-1:0] a16_data_delayed_6; +wire [`DWIDTH-1:0] a16_data_delayed_7; +wire [`DWIDTH-1:0] a16_data_delayed_8; +wire [`DWIDTH-1:0] a16_data_delayed_9; +wire [`DWIDTH-1:0] a16_data_delayed_10; +wire [`DWIDTH-1:0] a16_data_delayed_11; +wire [`DWIDTH-1:0] a16_data_delayed_12; +wire [`DWIDTH-1:0] a16_data_delayed_13; +wire [`DWIDTH-1:0] a16_data_delayed_14; +wire [`DWIDTH-1:0] a16_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_1; +wire [`DWIDTH-1:0] a17_data_delayed_2; +wire [`DWIDTH-1:0] a17_data_delayed_3; +wire [`DWIDTH-1:0] a17_data_delayed_4; +wire [`DWIDTH-1:0] a17_data_delayed_5; +wire [`DWIDTH-1:0] a17_data_delayed_6; +wire [`DWIDTH-1:0] a17_data_delayed_7; +wire [`DWIDTH-1:0] a17_data_delayed_8; +wire [`DWIDTH-1:0] a17_data_delayed_9; +wire [`DWIDTH-1:0] a17_data_delayed_10; +wire [`DWIDTH-1:0] a17_data_delayed_11; +wire [`DWIDTH-1:0] a17_data_delayed_12; +wire [`DWIDTH-1:0] a17_data_delayed_13; +wire [`DWIDTH-1:0] a17_data_delayed_14; +wire [`DWIDTH-1:0] a17_data_delayed_15; +wire [`DWIDTH-1:0] a17_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_1; +wire [`DWIDTH-1:0] a18_data_delayed_2; +wire [`DWIDTH-1:0] a18_data_delayed_3; +wire [`DWIDTH-1:0] a18_data_delayed_4; +wire [`DWIDTH-1:0] a18_data_delayed_5; +wire [`DWIDTH-1:0] a18_data_delayed_6; +wire [`DWIDTH-1:0] a18_data_delayed_7; +wire [`DWIDTH-1:0] a18_data_delayed_8; +wire [`DWIDTH-1:0] a18_data_delayed_9; +wire [`DWIDTH-1:0] a18_data_delayed_10; +wire [`DWIDTH-1:0] a18_data_delayed_11; +wire [`DWIDTH-1:0] a18_data_delayed_12; +wire [`DWIDTH-1:0] a18_data_delayed_13; +wire [`DWIDTH-1:0] a18_data_delayed_14; +wire [`DWIDTH-1:0] a18_data_delayed_15; +wire [`DWIDTH-1:0] a18_data_delayed_16; +wire [`DWIDTH-1:0] a18_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_1; +wire [`DWIDTH-1:0] a19_data_delayed_2; +wire [`DWIDTH-1:0] a19_data_delayed_3; +wire [`DWIDTH-1:0] a19_data_delayed_4; +wire [`DWIDTH-1:0] a19_data_delayed_5; +wire [`DWIDTH-1:0] a19_data_delayed_6; +wire [`DWIDTH-1:0] a19_data_delayed_7; +wire [`DWIDTH-1:0] a19_data_delayed_8; +wire [`DWIDTH-1:0] a19_data_delayed_9; +wire [`DWIDTH-1:0] a19_data_delayed_10; +wire [`DWIDTH-1:0] a19_data_delayed_11; +wire [`DWIDTH-1:0] a19_data_delayed_12; +wire [`DWIDTH-1:0] a19_data_delayed_13; +wire [`DWIDTH-1:0] a19_data_delayed_14; +wire [`DWIDTH-1:0] a19_data_delayed_15; +wire [`DWIDTH-1:0] a19_data_delayed_16; +wire [`DWIDTH-1:0] a19_data_delayed_17; +wire [`DWIDTH-1:0] a19_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_1; +wire [`DWIDTH-1:0] a20_data_delayed_2; +wire [`DWIDTH-1:0] a20_data_delayed_3; +wire [`DWIDTH-1:0] a20_data_delayed_4; +wire [`DWIDTH-1:0] a20_data_delayed_5; +wire [`DWIDTH-1:0] a20_data_delayed_6; +wire [`DWIDTH-1:0] a20_data_delayed_7; +wire [`DWIDTH-1:0] a20_data_delayed_8; +wire [`DWIDTH-1:0] a20_data_delayed_9; +wire [`DWIDTH-1:0] a20_data_delayed_10; +wire [`DWIDTH-1:0] a20_data_delayed_11; +wire [`DWIDTH-1:0] a20_data_delayed_12; +wire [`DWIDTH-1:0] a20_data_delayed_13; +wire [`DWIDTH-1:0] a20_data_delayed_14; +wire [`DWIDTH-1:0] a20_data_delayed_15; +wire [`DWIDTH-1:0] a20_data_delayed_16; +wire [`DWIDTH-1:0] a20_data_delayed_17; +wire [`DWIDTH-1:0] a20_data_delayed_18; +wire [`DWIDTH-1:0] a20_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_1; +wire [`DWIDTH-1:0] a21_data_delayed_2; +wire [`DWIDTH-1:0] a21_data_delayed_3; +wire [`DWIDTH-1:0] a21_data_delayed_4; +wire [`DWIDTH-1:0] a21_data_delayed_5; +wire [`DWIDTH-1:0] a21_data_delayed_6; +wire [`DWIDTH-1:0] a21_data_delayed_7; +wire [`DWIDTH-1:0] a21_data_delayed_8; +wire [`DWIDTH-1:0] a21_data_delayed_9; +wire [`DWIDTH-1:0] a21_data_delayed_10; +wire [`DWIDTH-1:0] a21_data_delayed_11; +wire [`DWIDTH-1:0] a21_data_delayed_12; +wire [`DWIDTH-1:0] a21_data_delayed_13; +wire [`DWIDTH-1:0] a21_data_delayed_14; +wire [`DWIDTH-1:0] a21_data_delayed_15; +wire [`DWIDTH-1:0] a21_data_delayed_16; +wire [`DWIDTH-1:0] a21_data_delayed_17; +wire [`DWIDTH-1:0] a21_data_delayed_18; +wire [`DWIDTH-1:0] a21_data_delayed_19; +wire [`DWIDTH-1:0] a21_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_21; +wire [`DWIDTH-1:0] a22_data_delayed_1; +wire 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[`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_1; +wire [`DWIDTH-1:0] b16_data_delayed_2; +wire [`DWIDTH-1:0] b16_data_delayed_3; +wire [`DWIDTH-1:0] b16_data_delayed_4; +wire [`DWIDTH-1:0] b16_data_delayed_5; +wire [`DWIDTH-1:0] b16_data_delayed_6; +wire [`DWIDTH-1:0] b16_data_delayed_7; +wire [`DWIDTH-1:0] b16_data_delayed_8; +wire [`DWIDTH-1:0] b16_data_delayed_9; +wire [`DWIDTH-1:0] b16_data_delayed_10; +wire [`DWIDTH-1:0] b16_data_delayed_11; +wire [`DWIDTH-1:0] b16_data_delayed_12; +wire [`DWIDTH-1:0] b16_data_delayed_13; +wire [`DWIDTH-1:0] b16_data_delayed_14; +wire [`DWIDTH-1:0] b16_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_1; +wire [`DWIDTH-1:0] b17_data_delayed_2; +wire [`DWIDTH-1:0] b17_data_delayed_3; +wire [`DWIDTH-1:0] b17_data_delayed_4; +wire [`DWIDTH-1:0] b17_data_delayed_5; +wire [`DWIDTH-1:0] b17_data_delayed_6; +wire [`DWIDTH-1:0] b17_data_delayed_7; +wire [`DWIDTH-1:0] b17_data_delayed_8; +wire [`DWIDTH-1:0] b17_data_delayed_9; +wire [`DWIDTH-1:0] b17_data_delayed_10; +wire [`DWIDTH-1:0] b17_data_delayed_11; +wire [`DWIDTH-1:0] b17_data_delayed_12; +wire [`DWIDTH-1:0] b17_data_delayed_13; +wire [`DWIDTH-1:0] b17_data_delayed_14; +wire [`DWIDTH-1:0] b17_data_delayed_15; +wire [`DWIDTH-1:0] b17_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_1; +wire [`DWIDTH-1:0] b18_data_delayed_2; +wire [`DWIDTH-1:0] b18_data_delayed_3; +wire [`DWIDTH-1:0] b18_data_delayed_4; +wire [`DWIDTH-1:0] b18_data_delayed_5; +wire [`DWIDTH-1:0] b18_data_delayed_6; +wire [`DWIDTH-1:0] b18_data_delayed_7; +wire [`DWIDTH-1:0] b18_data_delayed_8; +wire [`DWIDTH-1:0] b18_data_delayed_9; +wire [`DWIDTH-1:0] b18_data_delayed_10; +wire [`DWIDTH-1:0] b18_data_delayed_11; +wire [`DWIDTH-1:0] b18_data_delayed_12; +wire [`DWIDTH-1:0] b18_data_delayed_13; +wire [`DWIDTH-1:0] b18_data_delayed_14; +wire [`DWIDTH-1:0] b18_data_delayed_15; +wire [`DWIDTH-1:0] b18_data_delayed_16; +wire [`DWIDTH-1:0] b18_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_1; +wire [`DWIDTH-1:0] b19_data_delayed_2; +wire [`DWIDTH-1:0] b19_data_delayed_3; +wire [`DWIDTH-1:0] b19_data_delayed_4; +wire [`DWIDTH-1:0] b19_data_delayed_5; +wire [`DWIDTH-1:0] b19_data_delayed_6; +wire [`DWIDTH-1:0] b19_data_delayed_7; +wire [`DWIDTH-1:0] b19_data_delayed_8; +wire [`DWIDTH-1:0] b19_data_delayed_9; +wire [`DWIDTH-1:0] b19_data_delayed_10; +wire [`DWIDTH-1:0] b19_data_delayed_11; +wire [`DWIDTH-1:0] b19_data_delayed_12; +wire [`DWIDTH-1:0] b19_data_delayed_13; +wire [`DWIDTH-1:0] b19_data_delayed_14; +wire [`DWIDTH-1:0] b19_data_delayed_15; +wire [`DWIDTH-1:0] b19_data_delayed_16; +wire [`DWIDTH-1:0] b19_data_delayed_17; +wire [`DWIDTH-1:0] b19_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_1; +wire [`DWIDTH-1:0] b20_data_delayed_2; +wire [`DWIDTH-1:0] b20_data_delayed_3; +wire [`DWIDTH-1:0] b20_data_delayed_4; +wire [`DWIDTH-1:0] b20_data_delayed_5; +wire [`DWIDTH-1:0] b20_data_delayed_6; +wire [`DWIDTH-1:0] b20_data_delayed_7; +wire [`DWIDTH-1:0] b20_data_delayed_8; +wire [`DWIDTH-1:0] b20_data_delayed_9; +wire [`DWIDTH-1:0] b20_data_delayed_10; +wire [`DWIDTH-1:0] b20_data_delayed_11; +wire [`DWIDTH-1:0] b20_data_delayed_12; +wire [`DWIDTH-1:0] b20_data_delayed_13; +wire [`DWIDTH-1:0] b20_data_delayed_14; +wire [`DWIDTH-1:0] b20_data_delayed_15; +wire [`DWIDTH-1:0] b20_data_delayed_16; +wire [`DWIDTH-1:0] b20_data_delayed_17; +wire [`DWIDTH-1:0] b20_data_delayed_18; +wire [`DWIDTH-1:0] b20_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_1; +wire [`DWIDTH-1:0] b21_data_delayed_2; +wire [`DWIDTH-1:0] b21_data_delayed_3; +wire [`DWIDTH-1:0] b21_data_delayed_4; +wire [`DWIDTH-1:0] b21_data_delayed_5; +wire [`DWIDTH-1:0] b21_data_delayed_6; +wire [`DWIDTH-1:0] b21_data_delayed_7; +wire [`DWIDTH-1:0] b21_data_delayed_8; +wire [`DWIDTH-1:0] b21_data_delayed_9; +wire [`DWIDTH-1:0] b21_data_delayed_10; +wire [`DWIDTH-1:0] b21_data_delayed_11; +wire [`DWIDTH-1:0] b21_data_delayed_12; +wire [`DWIDTH-1:0] b21_data_delayed_13; +wire [`DWIDTH-1:0] b21_data_delayed_14; +wire [`DWIDTH-1:0] b21_data_delayed_15; +wire [`DWIDTH-1:0] b21_data_delayed_16; +wire [`DWIDTH-1:0] b21_data_delayed_17; +wire [`DWIDTH-1:0] b21_data_delayed_18; +wire [`DWIDTH-1:0] b21_data_delayed_19; +wire [`DWIDTH-1:0] b21_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_1; +wire [`DWIDTH-1:0] b22_data_delayed_2; +wire [`DWIDTH-1:0] b22_data_delayed_3; +wire [`DWIDTH-1:0] b22_data_delayed_4; +wire [`DWIDTH-1:0] b22_data_delayed_5; +wire [`DWIDTH-1:0] b22_data_delayed_6; +wire [`DWIDTH-1:0] b22_data_delayed_7; +wire [`DWIDTH-1:0] b22_data_delayed_8; +wire [`DWIDTH-1:0] b22_data_delayed_9; +wire [`DWIDTH-1:0] b22_data_delayed_10; +wire [`DWIDTH-1:0] b22_data_delayed_11; +wire [`DWIDTH-1:0] b22_data_delayed_12; +wire [`DWIDTH-1:0] b22_data_delayed_13; +wire [`DWIDTH-1:0] b22_data_delayed_14; +wire [`DWIDTH-1:0] b22_data_delayed_15; +wire [`DWIDTH-1:0] b22_data_delayed_16; +wire [`DWIDTH-1:0] b22_data_delayed_17; +wire [`DWIDTH-1:0] b22_data_delayed_18; +wire [`DWIDTH-1:0] b22_data_delayed_19; +wire [`DWIDTH-1:0] b22_data_delayed_20; +wire [`DWIDTH-1:0] b22_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_1; +wire [`DWIDTH-1:0] b23_data_delayed_2; +wire [`DWIDTH-1:0] b23_data_delayed_3; +wire [`DWIDTH-1:0] b23_data_delayed_4; +wire [`DWIDTH-1:0] b23_data_delayed_5; +wire [`DWIDTH-1:0] b23_data_delayed_6; +wire [`DWIDTH-1:0] b23_data_delayed_7; +wire [`DWIDTH-1:0] b23_data_delayed_8; +wire [`DWIDTH-1:0] b23_data_delayed_9; +wire [`DWIDTH-1:0] b23_data_delayed_10; +wire [`DWIDTH-1:0] b23_data_delayed_11; +wire [`DWIDTH-1:0] b23_data_delayed_12; +wire [`DWIDTH-1:0] b23_data_delayed_13; +wire [`DWIDTH-1:0] b23_data_delayed_14; +wire [`DWIDTH-1:0] b23_data_delayed_15; +wire [`DWIDTH-1:0] b23_data_delayed_16; +wire [`DWIDTH-1:0] b23_data_delayed_17; +wire [`DWIDTH-1:0] b23_data_delayed_18; +wire [`DWIDTH-1:0] b23_data_delayed_19; +wire [`DWIDTH-1:0] b23_data_delayed_20; +wire [`DWIDTH-1:0] b23_data_delayed_21; +wire [`DWIDTH-1:0] b23_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_1; +wire [`DWIDTH-1:0] b24_data_delayed_2; +wire [`DWIDTH-1:0] b24_data_delayed_3; +wire [`DWIDTH-1:0] b24_data_delayed_4; +wire [`DWIDTH-1:0] b24_data_delayed_5; +wire [`DWIDTH-1:0] b24_data_delayed_6; +wire [`DWIDTH-1:0] b24_data_delayed_7; +wire [`DWIDTH-1:0] b24_data_delayed_8; +wire [`DWIDTH-1:0] b24_data_delayed_9; +wire [`DWIDTH-1:0] b24_data_delayed_10; +wire [`DWIDTH-1:0] b24_data_delayed_11; +wire [`DWIDTH-1:0] b24_data_delayed_12; +wire [`DWIDTH-1:0] b24_data_delayed_13; +wire [`DWIDTH-1:0] b24_data_delayed_14; +wire [`DWIDTH-1:0] b24_data_delayed_15; +wire [`DWIDTH-1:0] b24_data_delayed_16; +wire [`DWIDTH-1:0] b24_data_delayed_17; +wire [`DWIDTH-1:0] b24_data_delayed_18; +wire [`DWIDTH-1:0] b24_data_delayed_19; +wire [`DWIDTH-1:0] b24_data_delayed_20; +wire [`DWIDTH-1:0] b24_data_delayed_21; +wire [`DWIDTH-1:0] b24_data_delayed_22; +wire [`DWIDTH-1:0] b24_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_1; +wire [`DWIDTH-1:0] b25_data_delayed_2; +wire [`DWIDTH-1:0] b25_data_delayed_3; +wire [`DWIDTH-1:0] b25_data_delayed_4; +wire [`DWIDTH-1:0] b25_data_delayed_5; +wire [`DWIDTH-1:0] b25_data_delayed_6; +wire [`DWIDTH-1:0] b25_data_delayed_7; +wire [`DWIDTH-1:0] b25_data_delayed_8; +wire [`DWIDTH-1:0] b25_data_delayed_9; +wire [`DWIDTH-1:0] b25_data_delayed_10; +wire [`DWIDTH-1:0] b25_data_delayed_11; +wire [`DWIDTH-1:0] b25_data_delayed_12; +wire [`DWIDTH-1:0] b25_data_delayed_13; +wire [`DWIDTH-1:0] b25_data_delayed_14; +wire [`DWIDTH-1:0] b25_data_delayed_15; +wire [`DWIDTH-1:0] b25_data_delayed_16; +wire [`DWIDTH-1:0] b25_data_delayed_17; +wire [`DWIDTH-1:0] b25_data_delayed_18; +wire [`DWIDTH-1:0] b25_data_delayed_19; +wire [`DWIDTH-1:0] b25_data_delayed_20; +wire [`DWIDTH-1:0] b25_data_delayed_21; +wire [`DWIDTH-1:0] b25_data_delayed_22; +wire [`DWIDTH-1:0] b25_data_delayed_23; +wire [`DWIDTH-1:0] b25_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_1; +wire [`DWIDTH-1:0] b26_data_delayed_2; +wire [`DWIDTH-1:0] b26_data_delayed_3; +wire [`DWIDTH-1:0] b26_data_delayed_4; +wire [`DWIDTH-1:0] b26_data_delayed_5; +wire [`DWIDTH-1:0] b26_data_delayed_6; +wire [`DWIDTH-1:0] b26_data_delayed_7; +wire [`DWIDTH-1:0] b26_data_delayed_8; +wire [`DWIDTH-1:0] b26_data_delayed_9; +wire [`DWIDTH-1:0] b26_data_delayed_10; +wire [`DWIDTH-1:0] b26_data_delayed_11; +wire [`DWIDTH-1:0] b26_data_delayed_12; +wire [`DWIDTH-1:0] b26_data_delayed_13; +wire [`DWIDTH-1:0] b26_data_delayed_14; +wire [`DWIDTH-1:0] b26_data_delayed_15; +wire [`DWIDTH-1:0] b26_data_delayed_16; +wire [`DWIDTH-1:0] b26_data_delayed_17; +wire [`DWIDTH-1:0] b26_data_delayed_18; +wire [`DWIDTH-1:0] b26_data_delayed_19; +wire [`DWIDTH-1:0] b26_data_delayed_20; +wire [`DWIDTH-1:0] b26_data_delayed_21; +wire [`DWIDTH-1:0] b26_data_delayed_22; +wire [`DWIDTH-1:0] b26_data_delayed_23; +wire [`DWIDTH-1:0] b26_data_delayed_24; +wire [`DWIDTH-1:0] b26_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_1; +wire [`DWIDTH-1:0] b27_data_delayed_2; +wire [`DWIDTH-1:0] b27_data_delayed_3; +wire [`DWIDTH-1:0] b27_data_delayed_4; +wire [`DWIDTH-1:0] b27_data_delayed_5; +wire [`DWIDTH-1:0] b27_data_delayed_6; +wire [`DWIDTH-1:0] b27_data_delayed_7; +wire [`DWIDTH-1:0] b27_data_delayed_8; +wire [`DWIDTH-1:0] b27_data_delayed_9; +wire [`DWIDTH-1:0] b27_data_delayed_10; +wire [`DWIDTH-1:0] b27_data_delayed_11; +wire [`DWIDTH-1:0] b27_data_delayed_12; +wire [`DWIDTH-1:0] b27_data_delayed_13; +wire [`DWIDTH-1:0] b27_data_delayed_14; +wire [`DWIDTH-1:0] b27_data_delayed_15; +wire [`DWIDTH-1:0] b27_data_delayed_16; +wire [`DWIDTH-1:0] b27_data_delayed_17; +wire [`DWIDTH-1:0] b27_data_delayed_18; +wire [`DWIDTH-1:0] b27_data_delayed_19; +wire [`DWIDTH-1:0] b27_data_delayed_20; +wire [`DWIDTH-1:0] b27_data_delayed_21; +wire [`DWIDTH-1:0] b27_data_delayed_22; +wire [`DWIDTH-1:0] b27_data_delayed_23; +wire [`DWIDTH-1:0] b27_data_delayed_24; +wire [`DWIDTH-1:0] b27_data_delayed_25; +wire [`DWIDTH-1:0] b27_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_1; +wire [`DWIDTH-1:0] b28_data_delayed_2; +wire [`DWIDTH-1:0] b28_data_delayed_3; +wire [`DWIDTH-1:0] b28_data_delayed_4; +wire [`DWIDTH-1:0] b28_data_delayed_5; +wire [`DWIDTH-1:0] b28_data_delayed_6; +wire [`DWIDTH-1:0] b28_data_delayed_7; +wire [`DWIDTH-1:0] b28_data_delayed_8; +wire [`DWIDTH-1:0] b28_data_delayed_9; +wire [`DWIDTH-1:0] b28_data_delayed_10; +wire [`DWIDTH-1:0] b28_data_delayed_11; +wire [`DWIDTH-1:0] b28_data_delayed_12; +wire [`DWIDTH-1:0] b28_data_delayed_13; +wire [`DWIDTH-1:0] b28_data_delayed_14; +wire [`DWIDTH-1:0] b28_data_delayed_15; +wire [`DWIDTH-1:0] b28_data_delayed_16; +wire [`DWIDTH-1:0] b28_data_delayed_17; +wire [`DWIDTH-1:0] b28_data_delayed_18; +wire [`DWIDTH-1:0] b28_data_delayed_19; +wire [`DWIDTH-1:0] b28_data_delayed_20; +wire [`DWIDTH-1:0] b28_data_delayed_21; +wire [`DWIDTH-1:0] b28_data_delayed_22; +wire [`DWIDTH-1:0] b28_data_delayed_23; +wire [`DWIDTH-1:0] b28_data_delayed_24; +wire [`DWIDTH-1:0] b28_data_delayed_25; +wire [`DWIDTH-1:0] b28_data_delayed_26; +wire [`DWIDTH-1:0] b28_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_1; +wire [`DWIDTH-1:0] b29_data_delayed_2; +wire [`DWIDTH-1:0] b29_data_delayed_3; +wire [`DWIDTH-1:0] b29_data_delayed_4; +wire [`DWIDTH-1:0] b29_data_delayed_5; +wire [`DWIDTH-1:0] b29_data_delayed_6; +wire [`DWIDTH-1:0] b29_data_delayed_7; +wire [`DWIDTH-1:0] b29_data_delayed_8; +wire [`DWIDTH-1:0] b29_data_delayed_9; +wire [`DWIDTH-1:0] b29_data_delayed_10; +wire [`DWIDTH-1:0] b29_data_delayed_11; +wire [`DWIDTH-1:0] b29_data_delayed_12; +wire [`DWIDTH-1:0] b29_data_delayed_13; +wire [`DWIDTH-1:0] b29_data_delayed_14; +wire [`DWIDTH-1:0] b29_data_delayed_15; +wire [`DWIDTH-1:0] b29_data_delayed_16; +wire [`DWIDTH-1:0] b29_data_delayed_17; +wire [`DWIDTH-1:0] b29_data_delayed_18; +wire [`DWIDTH-1:0] b29_data_delayed_19; +wire [`DWIDTH-1:0] b29_data_delayed_20; +wire [`DWIDTH-1:0] b29_data_delayed_21; +wire [`DWIDTH-1:0] b29_data_delayed_22; +wire [`DWIDTH-1:0] b29_data_delayed_23; +wire [`DWIDTH-1:0] b29_data_delayed_24; +wire [`DWIDTH-1:0] b29_data_delayed_25; +wire [`DWIDTH-1:0] b29_data_delayed_26; +wire [`DWIDTH-1:0] b29_data_delayed_27; +wire [`DWIDTH-1:0] b29_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_1; +wire [`DWIDTH-1:0] b30_data_delayed_2; +wire [`DWIDTH-1:0] b30_data_delayed_3; +wire [`DWIDTH-1:0] b30_data_delayed_4; +wire [`DWIDTH-1:0] b30_data_delayed_5; +wire [`DWIDTH-1:0] b30_data_delayed_6; +wire [`DWIDTH-1:0] b30_data_delayed_7; +wire [`DWIDTH-1:0] b30_data_delayed_8; +wire [`DWIDTH-1:0] b30_data_delayed_9; +wire [`DWIDTH-1:0] b30_data_delayed_10; +wire [`DWIDTH-1:0] b30_data_delayed_11; +wire [`DWIDTH-1:0] b30_data_delayed_12; +wire [`DWIDTH-1:0] b30_data_delayed_13; +wire [`DWIDTH-1:0] b30_data_delayed_14; +wire [`DWIDTH-1:0] b30_data_delayed_15; +wire [`DWIDTH-1:0] b30_data_delayed_16; +wire [`DWIDTH-1:0] b30_data_delayed_17; +wire [`DWIDTH-1:0] b30_data_delayed_18; +wire [`DWIDTH-1:0] b30_data_delayed_19; +wire [`DWIDTH-1:0] b30_data_delayed_20; +wire [`DWIDTH-1:0] b30_data_delayed_21; +wire [`DWIDTH-1:0] b30_data_delayed_22; +wire [`DWIDTH-1:0] b30_data_delayed_23; +wire [`DWIDTH-1:0] b30_data_delayed_24; +wire [`DWIDTH-1:0] b30_data_delayed_25; +wire [`DWIDTH-1:0] b30_data_delayed_26; +wire [`DWIDTH-1:0] b30_data_delayed_27; +wire [`DWIDTH-1:0] b30_data_delayed_28; +wire [`DWIDTH-1:0] b30_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_1; +wire [`DWIDTH-1:0] b31_data_delayed_2; +wire [`DWIDTH-1:0] b31_data_delayed_3; +wire [`DWIDTH-1:0] b31_data_delayed_4; +wire [`DWIDTH-1:0] b31_data_delayed_5; +wire [`DWIDTH-1:0] b31_data_delayed_6; +wire [`DWIDTH-1:0] b31_data_delayed_7; +wire [`DWIDTH-1:0] b31_data_delayed_8; +wire [`DWIDTH-1:0] b31_data_delayed_9; +wire [`DWIDTH-1:0] b31_data_delayed_10; +wire [`DWIDTH-1:0] b31_data_delayed_11; +wire [`DWIDTH-1:0] b31_data_delayed_12; +wire [`DWIDTH-1:0] b31_data_delayed_13; +wire [`DWIDTH-1:0] b31_data_delayed_14; +wire [`DWIDTH-1:0] b31_data_delayed_15; +wire [`DWIDTH-1:0] b31_data_delayed_16; +wire [`DWIDTH-1:0] b31_data_delayed_17; +wire [`DWIDTH-1:0] b31_data_delayed_18; +wire [`DWIDTH-1:0] b31_data_delayed_19; +wire [`DWIDTH-1:0] b31_data_delayed_20; +wire [`DWIDTH-1:0] b31_data_delayed_21; +wire [`DWIDTH-1:0] b31_data_delayed_22; +wire [`DWIDTH-1:0] b31_data_delayed_23; +wire [`DWIDTH-1:0] b31_data_delayed_24; +wire [`DWIDTH-1:0] b31_data_delayed_25; +wire [`DWIDTH-1:0] b31_data_delayed_26; +wire [`DWIDTH-1:0] b31_data_delayed_27; +wire [`DWIDTH-1:0] b31_data_delayed_28; +wire [`DWIDTH-1:0] b31_data_delayed_29; +wire [`DWIDTH-1:0] b31_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_31; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), +.a16_data_delayed_16(a16_data_delayed_16), +.b16_data_delayed_16(b16_data_delayed_16), +.a17_data_delayed_17(a17_data_delayed_17), +.b17_data_delayed_17(b17_data_delayed_17), +.a18_data_delayed_18(a18_data_delayed_18), +.b18_data_delayed_18(b18_data_delayed_18), +.a19_data_delayed_19(a19_data_delayed_19), +.b19_data_delayed_19(b19_data_delayed_19), +.a20_data_delayed_20(a20_data_delayed_20), +.b20_data_delayed_20(b20_data_delayed_20), +.a21_data_delayed_21(a21_data_delayed_21), +.b21_data_delayed_21(b21_data_delayed_21), +.a22_data_delayed_22(a22_data_delayed_22), +.b22_data_delayed_22(b22_data_delayed_22), +.a23_data_delayed_23(a23_data_delayed_23), +.b23_data_delayed_23(b23_data_delayed_23), +.a24_data_delayed_24(a24_data_delayed_24), +.b24_data_delayed_24(b24_data_delayed_24), +.a25_data_delayed_25(a25_data_delayed_25), +.b25_data_delayed_25(b25_data_delayed_25), +.a26_data_delayed_26(a26_data_delayed_26), +.b26_data_delayed_26(b26_data_delayed_26), +.a27_data_delayed_27(a27_data_delayed_27), +.b27_data_delayed_27(b27_data_delayed_27), +.a28_data_delayed_28(a28_data_delayed_28), +.b28_data_delayed_28(b28_data_delayed_28), +.a29_data_delayed_29(a29_data_delayed_29), +.b29_data_delayed_29(b29_data_delayed_29), +.a30_data_delayed_30(a30_data_delayed_30), +.b30_data_delayed_30(b30_data_delayed_30), +.a31_data_delayed_31(a31_data_delayed_31), +.b31_data_delayed_31(b31_data_delayed_31), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] a16; +wire [`DWIDTH-1:0] a17; +wire [`DWIDTH-1:0] a18; +wire [`DWIDTH-1:0] a19; +wire [`DWIDTH-1:0] a20; +wire [`DWIDTH-1:0] a21; +wire [`DWIDTH-1:0] a22; +wire [`DWIDTH-1:0] a23; +wire [`DWIDTH-1:0] a24; +wire [`DWIDTH-1:0] a25; +wire [`DWIDTH-1:0] a26; +wire [`DWIDTH-1:0] a27; +wire [`DWIDTH-1:0] a28; +wire [`DWIDTH-1:0] a29; +wire [`DWIDTH-1:0] a30; +wire [`DWIDTH-1:0] a31; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] b16; +wire [`DWIDTH-1:0] b17; +wire [`DWIDTH-1:0] b18; +wire [`DWIDTH-1:0] b19; +wire [`DWIDTH-1:0] b20; +wire [`DWIDTH-1:0] b21; +wire [`DWIDTH-1:0] b22; +wire [`DWIDTH-1:0] b23; +wire [`DWIDTH-1:0] b24; +wire [`DWIDTH-1:0] b25; +wire [`DWIDTH-1:0] b26; +wire [`DWIDTH-1:0] b27; +wire [`DWIDTH-1:0] b28; +wire [`DWIDTH-1:0] b29; +wire [`DWIDTH-1:0] b30; +wire [`DWIDTH-1:0] b31; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +wire [`DWIDTH-1:0] a16_data_in; +wire [`DWIDTH-1:0] a17_data_in; +wire [`DWIDTH-1:0] a18_data_in; +wire [`DWIDTH-1:0] a19_data_in; +wire [`DWIDTH-1:0] a20_data_in; +wire [`DWIDTH-1:0] a21_data_in; +wire [`DWIDTH-1:0] a22_data_in; +wire [`DWIDTH-1:0] a23_data_in; +wire [`DWIDTH-1:0] a24_data_in; +wire [`DWIDTH-1:0] a25_data_in; +wire [`DWIDTH-1:0] a26_data_in; +wire [`DWIDTH-1:0] a27_data_in; +wire [`DWIDTH-1:0] a28_data_in; +wire [`DWIDTH-1:0] a29_data_in; +wire [`DWIDTH-1:0] a30_data_in; +wire [`DWIDTH-1:0] a31_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign a16_data_in = a_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign a17_data_in = a_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign a18_data_in = a_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign a19_data_in = a_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign a20_data_in = a_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign a21_data_in = a_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign a22_data_in = a_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign a23_data_in = a_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign a24_data_in = a_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign a25_data_in = a_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign a26_data_in = a_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign a27_data_in = a_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign a28_data_in = a_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign a29_data_in = a_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign a30_data_in = a_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign a31_data_in = a_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +wire [`DWIDTH-1:0] b16_data_in; +wire [`DWIDTH-1:0] b17_data_in; +wire [`DWIDTH-1:0] b18_data_in; +wire [`DWIDTH-1:0] b19_data_in; +wire [`DWIDTH-1:0] b20_data_in; +wire [`DWIDTH-1:0] b21_data_in; +wire [`DWIDTH-1:0] b22_data_in; +wire [`DWIDTH-1:0] b23_data_in; +wire [`DWIDTH-1:0] b24_data_in; +wire [`DWIDTH-1:0] b25_data_in; +wire [`DWIDTH-1:0] b26_data_in; +wire [`DWIDTH-1:0] b27_data_in; +wire [`DWIDTH-1:0] b28_data_in; +wire [`DWIDTH-1:0] b29_data_in; +wire [`DWIDTH-1:0] b30_data_in; +wire [`DWIDTH-1:0] b31_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign b16_data_in = b_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign b17_data_in = b_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign b18_data_in = b_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign b19_data_in = b_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign b20_data_in = b_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign b21_data_in = b_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign b22_data_in = b_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign b23_data_in = b_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign b24_data_in = b_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign b25_data_in = b_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign b26_data_in = b_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign b27_data_in = b_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign b28_data_in = b_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign b29_data_in = b_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign b30_data_in = b_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign b31_data_in = b_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; +assign a16 = (b_loc==0) ? a16_data_delayed_16 : a16_data_in; +assign a17 = (b_loc==0) ? a17_data_delayed_17 : a17_data_in; +assign a18 = (b_loc==0) ? a18_data_delayed_18 : a18_data_in; +assign a19 = (b_loc==0) ? a19_data_delayed_19 : a19_data_in; +assign a20 = (b_loc==0) ? a20_data_delayed_20 : a20_data_in; +assign a21 = (b_loc==0) ? a21_data_delayed_21 : a21_data_in; +assign a22 = (b_loc==0) ? a22_data_delayed_22 : a22_data_in; +assign a23 = (b_loc==0) ? a23_data_delayed_23 : a23_data_in; +assign a24 = (b_loc==0) ? a24_data_delayed_24 : a24_data_in; +assign a25 = (b_loc==0) ? a25_data_delayed_25 : a25_data_in; +assign a26 = (b_loc==0) ? a26_data_delayed_26 : a26_data_in; +assign a27 = (b_loc==0) ? a27_data_delayed_27 : a27_data_in; +assign a28 = (b_loc==0) ? a28_data_delayed_28 : a28_data_in; +assign a29 = (b_loc==0) ? a29_data_delayed_29 : a29_data_in; +assign a30 = (b_loc==0) ? a30_data_delayed_30 : a30_data_in; +assign a31 = (b_loc==0) ? a31_data_delayed_31 : a31_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; +assign b16 = (a_loc==0) ? b16_data_delayed_16 : b16_data_in; +assign b17 = (a_loc==0) ? b17_data_delayed_17 : b17_data_in; +assign b18 = (a_loc==0) ? b18_data_delayed_18 : b18_data_in; +assign b19 = (a_loc==0) ? b19_data_delayed_19 : b19_data_in; +assign b20 = (a_loc==0) ? b20_data_delayed_20 : b20_data_in; +assign b21 = (a_loc==0) ? b21_data_delayed_21 : b21_data_in; +assign b22 = (a_loc==0) ? b22_data_delayed_22 : b22_data_in; +assign b23 = (a_loc==0) ? b23_data_delayed_23 : b23_data_in; +assign b24 = (a_loc==0) ? b24_data_delayed_24 : b24_data_in; +assign b25 = (a_loc==0) ? b25_data_delayed_25 : b25_data_in; +assign b26 = (a_loc==0) ? b26_data_delayed_26 : b26_data_in; +assign b27 = (a_loc==0) ? b27_data_delayed_27 : b27_data_in; +assign b28 = (a_loc==0) ? b28_data_delayed_28 : b28_data_in; +assign b29 = (a_loc==0) ? b29_data_delayed_29 : b29_data_in; +assign b30 = (a_loc==0) ? b30_data_delayed_30 : b30_data_in; +assign b31 = (a_loc==0) ? b31_data_delayed_31 : b31_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC0_16; +wire [`DWIDTH-1:0] matrixC0_17; +wire [`DWIDTH-1:0] matrixC0_18; +wire [`DWIDTH-1:0] matrixC0_19; +wire [`DWIDTH-1:0] matrixC0_20; +wire [`DWIDTH-1:0] matrixC0_21; +wire [`DWIDTH-1:0] matrixC0_22; +wire [`DWIDTH-1:0] matrixC0_23; +wire [`DWIDTH-1:0] matrixC0_24; +wire [`DWIDTH-1:0] matrixC0_25; +wire [`DWIDTH-1:0] matrixC0_26; +wire [`DWIDTH-1:0] matrixC0_27; +wire [`DWIDTH-1:0] matrixC0_28; +wire [`DWIDTH-1:0] matrixC0_29; +wire [`DWIDTH-1:0] matrixC0_30; +wire [`DWIDTH-1:0] matrixC0_31; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC1_16; +wire [`DWIDTH-1:0] matrixC1_17; +wire [`DWIDTH-1:0] matrixC1_18; +wire [`DWIDTH-1:0] matrixC1_19; +wire [`DWIDTH-1:0] matrixC1_20; +wire [`DWIDTH-1:0] matrixC1_21; +wire [`DWIDTH-1:0] matrixC1_22; +wire [`DWIDTH-1:0] matrixC1_23; +wire [`DWIDTH-1:0] matrixC1_24; +wire [`DWIDTH-1:0] matrixC1_25; +wire [`DWIDTH-1:0] matrixC1_26; +wire [`DWIDTH-1:0] matrixC1_27; +wire [`DWIDTH-1:0] matrixC1_28; +wire [`DWIDTH-1:0] matrixC1_29; +wire [`DWIDTH-1:0] matrixC1_30; +wire [`DWIDTH-1:0] matrixC1_31; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC2_16; +wire [`DWIDTH-1:0] matrixC2_17; +wire [`DWIDTH-1:0] matrixC2_18; +wire [`DWIDTH-1:0] matrixC2_19; +wire [`DWIDTH-1:0] matrixC2_20; +wire [`DWIDTH-1:0] matrixC2_21; +wire [`DWIDTH-1:0] matrixC2_22; +wire [`DWIDTH-1:0] matrixC2_23; +wire [`DWIDTH-1:0] matrixC2_24; +wire [`DWIDTH-1:0] matrixC2_25; +wire [`DWIDTH-1:0] matrixC2_26; +wire [`DWIDTH-1:0] matrixC2_27; +wire [`DWIDTH-1:0] matrixC2_28; +wire [`DWIDTH-1:0] matrixC2_29; +wire [`DWIDTH-1:0] matrixC2_30; +wire [`DWIDTH-1:0] matrixC2_31; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC3_16; +wire [`DWIDTH-1:0] matrixC3_17; +wire [`DWIDTH-1:0] matrixC3_18; +wire [`DWIDTH-1:0] matrixC3_19; +wire [`DWIDTH-1:0] matrixC3_20; +wire [`DWIDTH-1:0] matrixC3_21; +wire [`DWIDTH-1:0] matrixC3_22; +wire [`DWIDTH-1:0] matrixC3_23; +wire [`DWIDTH-1:0] matrixC3_24; +wire [`DWIDTH-1:0] matrixC3_25; +wire [`DWIDTH-1:0] matrixC3_26; +wire [`DWIDTH-1:0] matrixC3_27; +wire [`DWIDTH-1:0] matrixC3_28; +wire [`DWIDTH-1:0] matrixC3_29; +wire [`DWIDTH-1:0] matrixC3_30; +wire [`DWIDTH-1:0] matrixC3_31; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC4_16; +wire [`DWIDTH-1:0] matrixC4_17; +wire [`DWIDTH-1:0] matrixC4_18; +wire [`DWIDTH-1:0] matrixC4_19; +wire [`DWIDTH-1:0] matrixC4_20; +wire [`DWIDTH-1:0] matrixC4_21; +wire [`DWIDTH-1:0] matrixC4_22; +wire [`DWIDTH-1:0] matrixC4_23; +wire [`DWIDTH-1:0] matrixC4_24; +wire [`DWIDTH-1:0] matrixC4_25; +wire [`DWIDTH-1:0] matrixC4_26; +wire [`DWIDTH-1:0] matrixC4_27; +wire [`DWIDTH-1:0] matrixC4_28; +wire [`DWIDTH-1:0] matrixC4_29; +wire [`DWIDTH-1:0] matrixC4_30; +wire [`DWIDTH-1:0] matrixC4_31; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC5_16; +wire [`DWIDTH-1:0] matrixC5_17; +wire [`DWIDTH-1:0] matrixC5_18; +wire [`DWIDTH-1:0] matrixC5_19; +wire [`DWIDTH-1:0] matrixC5_20; +wire [`DWIDTH-1:0] matrixC5_21; +wire [`DWIDTH-1:0] matrixC5_22; +wire [`DWIDTH-1:0] matrixC5_23; +wire [`DWIDTH-1:0] matrixC5_24; +wire [`DWIDTH-1:0] matrixC5_25; +wire [`DWIDTH-1:0] matrixC5_26; +wire [`DWIDTH-1:0] matrixC5_27; +wire [`DWIDTH-1:0] matrixC5_28; +wire [`DWIDTH-1:0] matrixC5_29; +wire [`DWIDTH-1:0] matrixC5_30; +wire [`DWIDTH-1:0] matrixC5_31; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC6_16; +wire [`DWIDTH-1:0] matrixC6_17; +wire [`DWIDTH-1:0] matrixC6_18; +wire [`DWIDTH-1:0] matrixC6_19; +wire [`DWIDTH-1:0] matrixC6_20; +wire [`DWIDTH-1:0] matrixC6_21; +wire [`DWIDTH-1:0] matrixC6_22; +wire [`DWIDTH-1:0] matrixC6_23; +wire [`DWIDTH-1:0] matrixC6_24; +wire [`DWIDTH-1:0] matrixC6_25; +wire [`DWIDTH-1:0] matrixC6_26; +wire [`DWIDTH-1:0] matrixC6_27; +wire [`DWIDTH-1:0] matrixC6_28; +wire [`DWIDTH-1:0] matrixC6_29; +wire [`DWIDTH-1:0] matrixC6_30; +wire [`DWIDTH-1:0] matrixC6_31; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC7_16; +wire [`DWIDTH-1:0] matrixC7_17; +wire [`DWIDTH-1:0] matrixC7_18; +wire [`DWIDTH-1:0] matrixC7_19; +wire [`DWIDTH-1:0] matrixC7_20; +wire [`DWIDTH-1:0] matrixC7_21; +wire [`DWIDTH-1:0] matrixC7_22; +wire [`DWIDTH-1:0] matrixC7_23; +wire [`DWIDTH-1:0] matrixC7_24; +wire [`DWIDTH-1:0] matrixC7_25; +wire [`DWIDTH-1:0] matrixC7_26; +wire [`DWIDTH-1:0] matrixC7_27; +wire [`DWIDTH-1:0] matrixC7_28; +wire [`DWIDTH-1:0] matrixC7_29; +wire [`DWIDTH-1:0] matrixC7_30; +wire [`DWIDTH-1:0] matrixC7_31; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC8_16; +wire [`DWIDTH-1:0] matrixC8_17; +wire [`DWIDTH-1:0] matrixC8_18; +wire [`DWIDTH-1:0] matrixC8_19; +wire [`DWIDTH-1:0] matrixC8_20; +wire [`DWIDTH-1:0] matrixC8_21; +wire [`DWIDTH-1:0] matrixC8_22; +wire [`DWIDTH-1:0] matrixC8_23; +wire [`DWIDTH-1:0] matrixC8_24; +wire [`DWIDTH-1:0] matrixC8_25; +wire [`DWIDTH-1:0] matrixC8_26; +wire [`DWIDTH-1:0] matrixC8_27; +wire [`DWIDTH-1:0] matrixC8_28; +wire [`DWIDTH-1:0] matrixC8_29; +wire [`DWIDTH-1:0] matrixC8_30; +wire [`DWIDTH-1:0] matrixC8_31; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC9_16; +wire [`DWIDTH-1:0] matrixC9_17; +wire [`DWIDTH-1:0] matrixC9_18; +wire [`DWIDTH-1:0] matrixC9_19; +wire [`DWIDTH-1:0] matrixC9_20; +wire [`DWIDTH-1:0] matrixC9_21; +wire [`DWIDTH-1:0] matrixC9_22; +wire [`DWIDTH-1:0] matrixC9_23; +wire [`DWIDTH-1:0] matrixC9_24; +wire [`DWIDTH-1:0] matrixC9_25; +wire [`DWIDTH-1:0] matrixC9_26; +wire [`DWIDTH-1:0] matrixC9_27; +wire [`DWIDTH-1:0] matrixC9_28; +wire [`DWIDTH-1:0] matrixC9_29; +wire [`DWIDTH-1:0] matrixC9_30; +wire [`DWIDTH-1:0] matrixC9_31; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC10_16; +wire [`DWIDTH-1:0] matrixC10_17; +wire [`DWIDTH-1:0] matrixC10_18; +wire [`DWIDTH-1:0] matrixC10_19; +wire [`DWIDTH-1:0] matrixC10_20; +wire [`DWIDTH-1:0] matrixC10_21; +wire [`DWIDTH-1:0] matrixC10_22; +wire [`DWIDTH-1:0] matrixC10_23; +wire [`DWIDTH-1:0] matrixC10_24; +wire [`DWIDTH-1:0] matrixC10_25; +wire [`DWIDTH-1:0] matrixC10_26; +wire [`DWIDTH-1:0] matrixC10_27; +wire [`DWIDTH-1:0] matrixC10_28; +wire [`DWIDTH-1:0] matrixC10_29; +wire [`DWIDTH-1:0] matrixC10_30; +wire [`DWIDTH-1:0] matrixC10_31; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC11_16; +wire [`DWIDTH-1:0] matrixC11_17; +wire [`DWIDTH-1:0] matrixC11_18; +wire [`DWIDTH-1:0] matrixC11_19; +wire [`DWIDTH-1:0] matrixC11_20; +wire [`DWIDTH-1:0] matrixC11_21; +wire [`DWIDTH-1:0] matrixC11_22; +wire [`DWIDTH-1:0] matrixC11_23; +wire [`DWIDTH-1:0] matrixC11_24; +wire [`DWIDTH-1:0] matrixC11_25; +wire [`DWIDTH-1:0] matrixC11_26; +wire [`DWIDTH-1:0] matrixC11_27; +wire [`DWIDTH-1:0] matrixC11_28; +wire [`DWIDTH-1:0] matrixC11_29; +wire [`DWIDTH-1:0] matrixC11_30; +wire [`DWIDTH-1:0] matrixC11_31; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC12_16; +wire [`DWIDTH-1:0] matrixC12_17; +wire [`DWIDTH-1:0] matrixC12_18; +wire [`DWIDTH-1:0] matrixC12_19; +wire [`DWIDTH-1:0] matrixC12_20; +wire [`DWIDTH-1:0] matrixC12_21; +wire [`DWIDTH-1:0] matrixC12_22; +wire [`DWIDTH-1:0] matrixC12_23; +wire [`DWIDTH-1:0] matrixC12_24; +wire [`DWIDTH-1:0] matrixC12_25; +wire [`DWIDTH-1:0] matrixC12_26; +wire [`DWIDTH-1:0] matrixC12_27; +wire [`DWIDTH-1:0] matrixC12_28; +wire [`DWIDTH-1:0] matrixC12_29; +wire [`DWIDTH-1:0] matrixC12_30; +wire [`DWIDTH-1:0] matrixC12_31; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC13_16; +wire [`DWIDTH-1:0] matrixC13_17; +wire [`DWIDTH-1:0] matrixC13_18; +wire [`DWIDTH-1:0] matrixC13_19; +wire [`DWIDTH-1:0] matrixC13_20; +wire [`DWIDTH-1:0] matrixC13_21; +wire [`DWIDTH-1:0] matrixC13_22; +wire [`DWIDTH-1:0] matrixC13_23; +wire [`DWIDTH-1:0] matrixC13_24; +wire [`DWIDTH-1:0] matrixC13_25; +wire [`DWIDTH-1:0] matrixC13_26; +wire [`DWIDTH-1:0] matrixC13_27; +wire [`DWIDTH-1:0] matrixC13_28; +wire [`DWIDTH-1:0] matrixC13_29; +wire [`DWIDTH-1:0] matrixC13_30; +wire [`DWIDTH-1:0] matrixC13_31; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC14_16; +wire [`DWIDTH-1:0] matrixC14_17; +wire [`DWIDTH-1:0] matrixC14_18; +wire [`DWIDTH-1:0] matrixC14_19; +wire [`DWIDTH-1:0] matrixC14_20; +wire [`DWIDTH-1:0] matrixC14_21; +wire [`DWIDTH-1:0] matrixC14_22; +wire [`DWIDTH-1:0] matrixC14_23; +wire [`DWIDTH-1:0] matrixC14_24; +wire [`DWIDTH-1:0] matrixC14_25; +wire [`DWIDTH-1:0] matrixC14_26; +wire [`DWIDTH-1:0] matrixC14_27; +wire [`DWIDTH-1:0] matrixC14_28; +wire [`DWIDTH-1:0] matrixC14_29; +wire [`DWIDTH-1:0] matrixC14_30; +wire [`DWIDTH-1:0] matrixC14_31; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +wire [`DWIDTH-1:0] matrixC15_16; +wire [`DWIDTH-1:0] matrixC15_17; +wire [`DWIDTH-1:0] matrixC15_18; +wire [`DWIDTH-1:0] matrixC15_19; +wire [`DWIDTH-1:0] matrixC15_20; +wire [`DWIDTH-1:0] matrixC15_21; +wire [`DWIDTH-1:0] matrixC15_22; +wire [`DWIDTH-1:0] matrixC15_23; +wire [`DWIDTH-1:0] matrixC15_24; +wire [`DWIDTH-1:0] matrixC15_25; +wire [`DWIDTH-1:0] matrixC15_26; +wire [`DWIDTH-1:0] matrixC15_27; +wire [`DWIDTH-1:0] matrixC15_28; +wire [`DWIDTH-1:0] matrixC15_29; +wire [`DWIDTH-1:0] matrixC15_30; +wire [`DWIDTH-1:0] matrixC15_31; +wire [`DWIDTH-1:0] matrixC16_0; +wire [`DWIDTH-1:0] matrixC16_1; +wire [`DWIDTH-1:0] matrixC16_2; +wire [`DWIDTH-1:0] matrixC16_3; +wire [`DWIDTH-1:0] matrixC16_4; +wire [`DWIDTH-1:0] matrixC16_5; +wire [`DWIDTH-1:0] matrixC16_6; +wire [`DWIDTH-1:0] matrixC16_7; +wire [`DWIDTH-1:0] matrixC16_8; +wire [`DWIDTH-1:0] matrixC16_9; +wire [`DWIDTH-1:0] matrixC16_10; +wire [`DWIDTH-1:0] matrixC16_11; +wire [`DWIDTH-1:0] matrixC16_12; +wire [`DWIDTH-1:0] matrixC16_13; +wire [`DWIDTH-1:0] matrixC16_14; +wire [`DWIDTH-1:0] matrixC16_15; +wire [`DWIDTH-1:0] matrixC16_16; +wire [`DWIDTH-1:0] matrixC16_17; +wire [`DWIDTH-1:0] matrixC16_18; +wire [`DWIDTH-1:0] matrixC16_19; +wire [`DWIDTH-1:0] matrixC16_20; +wire [`DWIDTH-1:0] matrixC16_21; +wire [`DWIDTH-1:0] matrixC16_22; +wire [`DWIDTH-1:0] matrixC16_23; +wire [`DWIDTH-1:0] matrixC16_24; +wire [`DWIDTH-1:0] matrixC16_25; +wire [`DWIDTH-1:0] matrixC16_26; +wire [`DWIDTH-1:0] matrixC16_27; +wire [`DWIDTH-1:0] matrixC16_28; +wire [`DWIDTH-1:0] matrixC16_29; +wire [`DWIDTH-1:0] matrixC16_30; +wire [`DWIDTH-1:0] matrixC16_31; +wire [`DWIDTH-1:0] matrixC17_0; +wire [`DWIDTH-1:0] matrixC17_1; +wire [`DWIDTH-1:0] matrixC17_2; +wire [`DWIDTH-1:0] matrixC17_3; +wire [`DWIDTH-1:0] matrixC17_4; +wire [`DWIDTH-1:0] matrixC17_5; +wire [`DWIDTH-1:0] matrixC17_6; +wire [`DWIDTH-1:0] matrixC17_7; +wire [`DWIDTH-1:0] matrixC17_8; +wire [`DWIDTH-1:0] matrixC17_9; +wire [`DWIDTH-1:0] matrixC17_10; +wire [`DWIDTH-1:0] matrixC17_11; +wire [`DWIDTH-1:0] matrixC17_12; +wire [`DWIDTH-1:0] matrixC17_13; +wire [`DWIDTH-1:0] matrixC17_14; +wire [`DWIDTH-1:0] matrixC17_15; +wire [`DWIDTH-1:0] matrixC17_16; +wire [`DWIDTH-1:0] matrixC17_17; +wire [`DWIDTH-1:0] matrixC17_18; +wire [`DWIDTH-1:0] matrixC17_19; +wire [`DWIDTH-1:0] matrixC17_20; +wire [`DWIDTH-1:0] matrixC17_21; +wire [`DWIDTH-1:0] matrixC17_22; +wire [`DWIDTH-1:0] matrixC17_23; +wire [`DWIDTH-1:0] matrixC17_24; +wire [`DWIDTH-1:0] matrixC17_25; +wire [`DWIDTH-1:0] matrixC17_26; +wire [`DWIDTH-1:0] matrixC17_27; +wire [`DWIDTH-1:0] matrixC17_28; +wire [`DWIDTH-1:0] matrixC17_29; +wire [`DWIDTH-1:0] matrixC17_30; +wire [`DWIDTH-1:0] matrixC17_31; +wire [`DWIDTH-1:0] matrixC18_0; +wire [`DWIDTH-1:0] matrixC18_1; +wire [`DWIDTH-1:0] matrixC18_2; +wire [`DWIDTH-1:0] matrixC18_3; +wire [`DWIDTH-1:0] matrixC18_4; +wire [`DWIDTH-1:0] matrixC18_5; +wire [`DWIDTH-1:0] matrixC18_6; +wire [`DWIDTH-1:0] matrixC18_7; +wire [`DWIDTH-1:0] matrixC18_8; +wire [`DWIDTH-1:0] matrixC18_9; +wire [`DWIDTH-1:0] matrixC18_10; +wire [`DWIDTH-1:0] matrixC18_11; +wire [`DWIDTH-1:0] matrixC18_12; +wire [`DWIDTH-1:0] matrixC18_13; +wire [`DWIDTH-1:0] matrixC18_14; +wire [`DWIDTH-1:0] matrixC18_15; +wire [`DWIDTH-1:0] matrixC18_16; +wire [`DWIDTH-1:0] matrixC18_17; +wire [`DWIDTH-1:0] matrixC18_18; +wire [`DWIDTH-1:0] matrixC18_19; +wire [`DWIDTH-1:0] matrixC18_20; +wire [`DWIDTH-1:0] matrixC18_21; +wire [`DWIDTH-1:0] matrixC18_22; +wire [`DWIDTH-1:0] matrixC18_23; +wire [`DWIDTH-1:0] matrixC18_24; +wire [`DWIDTH-1:0] matrixC18_25; +wire [`DWIDTH-1:0] matrixC18_26; +wire [`DWIDTH-1:0] matrixC18_27; +wire [`DWIDTH-1:0] matrixC18_28; +wire [`DWIDTH-1:0] matrixC18_29; +wire [`DWIDTH-1:0] matrixC18_30; +wire [`DWIDTH-1:0] matrixC18_31; +wire [`DWIDTH-1:0] matrixC19_0; +wire [`DWIDTH-1:0] matrixC19_1; +wire [`DWIDTH-1:0] matrixC19_2; +wire [`DWIDTH-1:0] matrixC19_3; +wire [`DWIDTH-1:0] matrixC19_4; +wire [`DWIDTH-1:0] matrixC19_5; +wire [`DWIDTH-1:0] matrixC19_6; +wire [`DWIDTH-1:0] matrixC19_7; +wire [`DWIDTH-1:0] matrixC19_8; +wire [`DWIDTH-1:0] matrixC19_9; +wire [`DWIDTH-1:0] matrixC19_10; +wire [`DWIDTH-1:0] matrixC19_11; +wire [`DWIDTH-1:0] matrixC19_12; +wire [`DWIDTH-1:0] matrixC19_13; +wire [`DWIDTH-1:0] matrixC19_14; +wire [`DWIDTH-1:0] matrixC19_15; +wire [`DWIDTH-1:0] matrixC19_16; +wire [`DWIDTH-1:0] matrixC19_17; +wire [`DWIDTH-1:0] matrixC19_18; +wire [`DWIDTH-1:0] matrixC19_19; +wire [`DWIDTH-1:0] matrixC19_20; +wire [`DWIDTH-1:0] matrixC19_21; +wire [`DWIDTH-1:0] matrixC19_22; +wire [`DWIDTH-1:0] matrixC19_23; +wire [`DWIDTH-1:0] matrixC19_24; +wire [`DWIDTH-1:0] matrixC19_25; +wire [`DWIDTH-1:0] matrixC19_26; +wire [`DWIDTH-1:0] matrixC19_27; +wire [`DWIDTH-1:0] matrixC19_28; +wire [`DWIDTH-1:0] matrixC19_29; +wire [`DWIDTH-1:0] matrixC19_30; +wire [`DWIDTH-1:0] matrixC19_31; +wire [`DWIDTH-1:0] matrixC20_0; +wire [`DWIDTH-1:0] matrixC20_1; +wire [`DWIDTH-1:0] matrixC20_2; +wire [`DWIDTH-1:0] matrixC20_3; +wire [`DWIDTH-1:0] matrixC20_4; +wire [`DWIDTH-1:0] matrixC20_5; +wire [`DWIDTH-1:0] matrixC20_6; +wire [`DWIDTH-1:0] matrixC20_7; +wire [`DWIDTH-1:0] matrixC20_8; +wire [`DWIDTH-1:0] matrixC20_9; +wire [`DWIDTH-1:0] matrixC20_10; +wire [`DWIDTH-1:0] matrixC20_11; +wire [`DWIDTH-1:0] matrixC20_12; +wire [`DWIDTH-1:0] matrixC20_13; +wire [`DWIDTH-1:0] matrixC20_14; +wire [`DWIDTH-1:0] matrixC20_15; +wire [`DWIDTH-1:0] matrixC20_16; +wire [`DWIDTH-1:0] matrixC20_17; +wire [`DWIDTH-1:0] matrixC20_18; +wire [`DWIDTH-1:0] matrixC20_19; +wire [`DWIDTH-1:0] matrixC20_20; +wire [`DWIDTH-1:0] matrixC20_21; +wire [`DWIDTH-1:0] matrixC20_22; +wire [`DWIDTH-1:0] matrixC20_23; +wire [`DWIDTH-1:0] matrixC20_24; +wire [`DWIDTH-1:0] matrixC20_25; +wire [`DWIDTH-1:0] matrixC20_26; +wire [`DWIDTH-1:0] matrixC20_27; +wire [`DWIDTH-1:0] matrixC20_28; +wire [`DWIDTH-1:0] matrixC20_29; +wire [`DWIDTH-1:0] matrixC20_30; +wire [`DWIDTH-1:0] matrixC20_31; +wire [`DWIDTH-1:0] matrixC21_0; +wire [`DWIDTH-1:0] matrixC21_1; +wire [`DWIDTH-1:0] matrixC21_2; +wire [`DWIDTH-1:0] matrixC21_3; +wire [`DWIDTH-1:0] matrixC21_4; +wire [`DWIDTH-1:0] matrixC21_5; +wire [`DWIDTH-1:0] matrixC21_6; +wire [`DWIDTH-1:0] matrixC21_7; +wire [`DWIDTH-1:0] matrixC21_8; +wire [`DWIDTH-1:0] matrixC21_9; +wire [`DWIDTH-1:0] matrixC21_10; +wire [`DWIDTH-1:0] matrixC21_11; +wire [`DWIDTH-1:0] matrixC21_12; +wire [`DWIDTH-1:0] matrixC21_13; +wire [`DWIDTH-1:0] matrixC21_14; +wire [`DWIDTH-1:0] matrixC21_15; +wire [`DWIDTH-1:0] matrixC21_16; +wire [`DWIDTH-1:0] matrixC21_17; +wire [`DWIDTH-1:0] matrixC21_18; +wire [`DWIDTH-1:0] matrixC21_19; +wire [`DWIDTH-1:0] matrixC21_20; +wire [`DWIDTH-1:0] matrixC21_21; +wire [`DWIDTH-1:0] matrixC21_22; +wire [`DWIDTH-1:0] matrixC21_23; +wire [`DWIDTH-1:0] matrixC21_24; +wire [`DWIDTH-1:0] matrixC21_25; +wire [`DWIDTH-1:0] matrixC21_26; +wire [`DWIDTH-1:0] matrixC21_27; +wire [`DWIDTH-1:0] matrixC21_28; +wire [`DWIDTH-1:0] matrixC21_29; +wire [`DWIDTH-1:0] matrixC21_30; +wire [`DWIDTH-1:0] matrixC21_31; +wire [`DWIDTH-1:0] matrixC22_0; +wire [`DWIDTH-1:0] matrixC22_1; +wire [`DWIDTH-1:0] matrixC22_2; +wire [`DWIDTH-1:0] matrixC22_3; +wire [`DWIDTH-1:0] matrixC22_4; +wire [`DWIDTH-1:0] matrixC22_5; +wire [`DWIDTH-1:0] matrixC22_6; +wire [`DWIDTH-1:0] matrixC22_7; +wire [`DWIDTH-1:0] matrixC22_8; +wire [`DWIDTH-1:0] matrixC22_9; +wire [`DWIDTH-1:0] matrixC22_10; +wire [`DWIDTH-1:0] matrixC22_11; +wire [`DWIDTH-1:0] matrixC22_12; +wire [`DWIDTH-1:0] matrixC22_13; +wire [`DWIDTH-1:0] matrixC22_14; +wire [`DWIDTH-1:0] matrixC22_15; +wire [`DWIDTH-1:0] matrixC22_16; +wire [`DWIDTH-1:0] matrixC22_17; +wire [`DWIDTH-1:0] matrixC22_18; +wire [`DWIDTH-1:0] matrixC22_19; +wire [`DWIDTH-1:0] matrixC22_20; +wire [`DWIDTH-1:0] matrixC22_21; +wire [`DWIDTH-1:0] matrixC22_22; +wire [`DWIDTH-1:0] matrixC22_23; +wire [`DWIDTH-1:0] matrixC22_24; +wire [`DWIDTH-1:0] matrixC22_25; +wire [`DWIDTH-1:0] matrixC22_26; +wire [`DWIDTH-1:0] matrixC22_27; +wire [`DWIDTH-1:0] matrixC22_28; +wire [`DWIDTH-1:0] matrixC22_29; +wire [`DWIDTH-1:0] matrixC22_30; +wire [`DWIDTH-1:0] matrixC22_31; +wire [`DWIDTH-1:0] matrixC23_0; +wire [`DWIDTH-1:0] matrixC23_1; +wire [`DWIDTH-1:0] matrixC23_2; +wire [`DWIDTH-1:0] matrixC23_3; +wire [`DWIDTH-1:0] matrixC23_4; +wire [`DWIDTH-1:0] matrixC23_5; +wire [`DWIDTH-1:0] matrixC23_6; +wire [`DWIDTH-1:0] matrixC23_7; +wire [`DWIDTH-1:0] matrixC23_8; +wire [`DWIDTH-1:0] matrixC23_9; +wire [`DWIDTH-1:0] matrixC23_10; +wire [`DWIDTH-1:0] matrixC23_11; +wire [`DWIDTH-1:0] matrixC23_12; +wire [`DWIDTH-1:0] matrixC23_13; +wire [`DWIDTH-1:0] matrixC23_14; +wire [`DWIDTH-1:0] matrixC23_15; +wire [`DWIDTH-1:0] matrixC23_16; +wire [`DWIDTH-1:0] matrixC23_17; +wire [`DWIDTH-1:0] matrixC23_18; +wire [`DWIDTH-1:0] matrixC23_19; +wire [`DWIDTH-1:0] matrixC23_20; +wire [`DWIDTH-1:0] matrixC23_21; +wire [`DWIDTH-1:0] matrixC23_22; +wire [`DWIDTH-1:0] matrixC23_23; +wire [`DWIDTH-1:0] matrixC23_24; +wire [`DWIDTH-1:0] matrixC23_25; +wire [`DWIDTH-1:0] matrixC23_26; +wire [`DWIDTH-1:0] matrixC23_27; +wire [`DWIDTH-1:0] matrixC23_28; +wire [`DWIDTH-1:0] matrixC23_29; +wire [`DWIDTH-1:0] matrixC23_30; +wire [`DWIDTH-1:0] matrixC23_31; +wire [`DWIDTH-1:0] matrixC24_0; +wire [`DWIDTH-1:0] matrixC24_1; +wire [`DWIDTH-1:0] matrixC24_2; +wire [`DWIDTH-1:0] matrixC24_3; +wire [`DWIDTH-1:0] matrixC24_4; +wire [`DWIDTH-1:0] matrixC24_5; +wire [`DWIDTH-1:0] matrixC24_6; +wire [`DWIDTH-1:0] matrixC24_7; +wire [`DWIDTH-1:0] matrixC24_8; +wire [`DWIDTH-1:0] matrixC24_9; +wire [`DWIDTH-1:0] matrixC24_10; +wire [`DWIDTH-1:0] matrixC24_11; +wire [`DWIDTH-1:0] matrixC24_12; +wire [`DWIDTH-1:0] matrixC24_13; +wire [`DWIDTH-1:0] matrixC24_14; +wire [`DWIDTH-1:0] matrixC24_15; +wire [`DWIDTH-1:0] matrixC24_16; +wire [`DWIDTH-1:0] matrixC24_17; +wire [`DWIDTH-1:0] matrixC24_18; +wire [`DWIDTH-1:0] matrixC24_19; +wire [`DWIDTH-1:0] matrixC24_20; +wire [`DWIDTH-1:0] matrixC24_21; +wire [`DWIDTH-1:0] matrixC24_22; +wire [`DWIDTH-1:0] matrixC24_23; +wire [`DWIDTH-1:0] matrixC24_24; +wire [`DWIDTH-1:0] matrixC24_25; +wire [`DWIDTH-1:0] matrixC24_26; +wire [`DWIDTH-1:0] matrixC24_27; +wire [`DWIDTH-1:0] matrixC24_28; +wire [`DWIDTH-1:0] matrixC24_29; +wire [`DWIDTH-1:0] matrixC24_30; +wire [`DWIDTH-1:0] matrixC24_31; +wire [`DWIDTH-1:0] matrixC25_0; +wire [`DWIDTH-1:0] matrixC25_1; +wire [`DWIDTH-1:0] matrixC25_2; +wire [`DWIDTH-1:0] matrixC25_3; +wire [`DWIDTH-1:0] matrixC25_4; +wire [`DWIDTH-1:0] matrixC25_5; +wire [`DWIDTH-1:0] matrixC25_6; +wire [`DWIDTH-1:0] matrixC25_7; +wire [`DWIDTH-1:0] matrixC25_8; +wire [`DWIDTH-1:0] matrixC25_9; +wire [`DWIDTH-1:0] matrixC25_10; +wire [`DWIDTH-1:0] matrixC25_11; +wire [`DWIDTH-1:0] matrixC25_12; +wire [`DWIDTH-1:0] matrixC25_13; +wire [`DWIDTH-1:0] matrixC25_14; +wire [`DWIDTH-1:0] matrixC25_15; +wire [`DWIDTH-1:0] matrixC25_16; +wire [`DWIDTH-1:0] matrixC25_17; +wire [`DWIDTH-1:0] matrixC25_18; +wire [`DWIDTH-1:0] matrixC25_19; +wire [`DWIDTH-1:0] matrixC25_20; +wire [`DWIDTH-1:0] matrixC25_21; +wire [`DWIDTH-1:0] matrixC25_22; +wire [`DWIDTH-1:0] matrixC25_23; +wire [`DWIDTH-1:0] matrixC25_24; +wire [`DWIDTH-1:0] matrixC25_25; +wire [`DWIDTH-1:0] matrixC25_26; +wire [`DWIDTH-1:0] matrixC25_27; +wire [`DWIDTH-1:0] matrixC25_28; +wire [`DWIDTH-1:0] matrixC25_29; +wire [`DWIDTH-1:0] matrixC25_30; +wire [`DWIDTH-1:0] matrixC25_31; +wire [`DWIDTH-1:0] matrixC26_0; +wire [`DWIDTH-1:0] matrixC26_1; +wire [`DWIDTH-1:0] matrixC26_2; +wire [`DWIDTH-1:0] matrixC26_3; +wire [`DWIDTH-1:0] matrixC26_4; +wire [`DWIDTH-1:0] matrixC26_5; +wire [`DWIDTH-1:0] matrixC26_6; +wire [`DWIDTH-1:0] matrixC26_7; +wire [`DWIDTH-1:0] matrixC26_8; +wire [`DWIDTH-1:0] matrixC26_9; +wire [`DWIDTH-1:0] matrixC26_10; +wire [`DWIDTH-1:0] matrixC26_11; +wire [`DWIDTH-1:0] matrixC26_12; +wire [`DWIDTH-1:0] matrixC26_13; +wire [`DWIDTH-1:0] matrixC26_14; +wire [`DWIDTH-1:0] matrixC26_15; +wire [`DWIDTH-1:0] matrixC26_16; +wire [`DWIDTH-1:0] matrixC26_17; +wire [`DWIDTH-1:0] matrixC26_18; +wire [`DWIDTH-1:0] matrixC26_19; +wire [`DWIDTH-1:0] matrixC26_20; +wire [`DWIDTH-1:0] matrixC26_21; +wire [`DWIDTH-1:0] matrixC26_22; +wire [`DWIDTH-1:0] matrixC26_23; +wire [`DWIDTH-1:0] matrixC26_24; +wire [`DWIDTH-1:0] matrixC26_25; +wire [`DWIDTH-1:0] matrixC26_26; +wire [`DWIDTH-1:0] matrixC26_27; +wire [`DWIDTH-1:0] matrixC26_28; +wire [`DWIDTH-1:0] matrixC26_29; +wire [`DWIDTH-1:0] matrixC26_30; +wire [`DWIDTH-1:0] matrixC26_31; +wire [`DWIDTH-1:0] matrixC27_0; +wire [`DWIDTH-1:0] matrixC27_1; +wire [`DWIDTH-1:0] matrixC27_2; +wire [`DWIDTH-1:0] matrixC27_3; +wire [`DWIDTH-1:0] matrixC27_4; +wire [`DWIDTH-1:0] matrixC27_5; +wire [`DWIDTH-1:0] matrixC27_6; +wire [`DWIDTH-1:0] matrixC27_7; +wire [`DWIDTH-1:0] matrixC27_8; +wire [`DWIDTH-1:0] matrixC27_9; +wire [`DWIDTH-1:0] matrixC27_10; +wire [`DWIDTH-1:0] matrixC27_11; +wire [`DWIDTH-1:0] matrixC27_12; +wire [`DWIDTH-1:0] matrixC27_13; +wire [`DWIDTH-1:0] matrixC27_14; +wire [`DWIDTH-1:0] matrixC27_15; +wire [`DWIDTH-1:0] matrixC27_16; +wire [`DWIDTH-1:0] matrixC27_17; +wire [`DWIDTH-1:0] matrixC27_18; +wire [`DWIDTH-1:0] matrixC27_19; +wire [`DWIDTH-1:0] matrixC27_20; +wire [`DWIDTH-1:0] matrixC27_21; +wire [`DWIDTH-1:0] matrixC27_22; +wire [`DWIDTH-1:0] matrixC27_23; +wire [`DWIDTH-1:0] matrixC27_24; +wire [`DWIDTH-1:0] matrixC27_25; +wire [`DWIDTH-1:0] matrixC27_26; +wire [`DWIDTH-1:0] matrixC27_27; +wire [`DWIDTH-1:0] matrixC27_28; +wire [`DWIDTH-1:0] matrixC27_29; +wire [`DWIDTH-1:0] matrixC27_30; +wire [`DWIDTH-1:0] matrixC27_31; +wire [`DWIDTH-1:0] matrixC28_0; +wire [`DWIDTH-1:0] matrixC28_1; +wire [`DWIDTH-1:0] matrixC28_2; +wire [`DWIDTH-1:0] matrixC28_3; +wire [`DWIDTH-1:0] matrixC28_4; +wire [`DWIDTH-1:0] matrixC28_5; +wire [`DWIDTH-1:0] matrixC28_6; +wire [`DWIDTH-1:0] matrixC28_7; +wire [`DWIDTH-1:0] matrixC28_8; +wire [`DWIDTH-1:0] matrixC28_9; +wire [`DWIDTH-1:0] matrixC28_10; +wire [`DWIDTH-1:0] matrixC28_11; +wire [`DWIDTH-1:0] matrixC28_12; +wire [`DWIDTH-1:0] matrixC28_13; +wire [`DWIDTH-1:0] matrixC28_14; +wire [`DWIDTH-1:0] matrixC28_15; +wire [`DWIDTH-1:0] matrixC28_16; +wire [`DWIDTH-1:0] matrixC28_17; +wire [`DWIDTH-1:0] matrixC28_18; +wire [`DWIDTH-1:0] matrixC28_19; +wire [`DWIDTH-1:0] matrixC28_20; +wire [`DWIDTH-1:0] matrixC28_21; +wire [`DWIDTH-1:0] matrixC28_22; +wire [`DWIDTH-1:0] matrixC28_23; +wire [`DWIDTH-1:0] matrixC28_24; +wire [`DWIDTH-1:0] matrixC28_25; +wire [`DWIDTH-1:0] matrixC28_26; +wire [`DWIDTH-1:0] matrixC28_27; +wire [`DWIDTH-1:0] matrixC28_28; +wire [`DWIDTH-1:0] matrixC28_29; +wire [`DWIDTH-1:0] matrixC28_30; +wire [`DWIDTH-1:0] matrixC28_31; +wire [`DWIDTH-1:0] matrixC29_0; +wire [`DWIDTH-1:0] matrixC29_1; +wire [`DWIDTH-1:0] matrixC29_2; +wire [`DWIDTH-1:0] matrixC29_3; +wire [`DWIDTH-1:0] matrixC29_4; +wire [`DWIDTH-1:0] matrixC29_5; +wire [`DWIDTH-1:0] matrixC29_6; +wire [`DWIDTH-1:0] matrixC29_7; +wire [`DWIDTH-1:0] matrixC29_8; +wire [`DWIDTH-1:0] matrixC29_9; +wire [`DWIDTH-1:0] matrixC29_10; +wire [`DWIDTH-1:0] matrixC29_11; +wire [`DWIDTH-1:0] matrixC29_12; +wire [`DWIDTH-1:0] matrixC29_13; +wire [`DWIDTH-1:0] matrixC29_14; +wire [`DWIDTH-1:0] matrixC29_15; +wire [`DWIDTH-1:0] matrixC29_16; +wire [`DWIDTH-1:0] matrixC29_17; +wire [`DWIDTH-1:0] matrixC29_18; +wire [`DWIDTH-1:0] matrixC29_19; +wire [`DWIDTH-1:0] matrixC29_20; +wire [`DWIDTH-1:0] matrixC29_21; +wire [`DWIDTH-1:0] matrixC29_22; +wire [`DWIDTH-1:0] matrixC29_23; +wire [`DWIDTH-1:0] matrixC29_24; +wire [`DWIDTH-1:0] matrixC29_25; +wire [`DWIDTH-1:0] matrixC29_26; +wire [`DWIDTH-1:0] matrixC29_27; +wire [`DWIDTH-1:0] matrixC29_28; +wire [`DWIDTH-1:0] matrixC29_29; +wire [`DWIDTH-1:0] matrixC29_30; +wire [`DWIDTH-1:0] matrixC29_31; +wire [`DWIDTH-1:0] matrixC30_0; +wire [`DWIDTH-1:0] matrixC30_1; +wire [`DWIDTH-1:0] matrixC30_2; +wire [`DWIDTH-1:0] matrixC30_3; +wire [`DWIDTH-1:0] matrixC30_4; +wire [`DWIDTH-1:0] matrixC30_5; +wire [`DWIDTH-1:0] matrixC30_6; +wire [`DWIDTH-1:0] matrixC30_7; +wire [`DWIDTH-1:0] matrixC30_8; +wire [`DWIDTH-1:0] matrixC30_9; +wire [`DWIDTH-1:0] matrixC30_10; +wire [`DWIDTH-1:0] matrixC30_11; +wire [`DWIDTH-1:0] matrixC30_12; +wire [`DWIDTH-1:0] matrixC30_13; +wire [`DWIDTH-1:0] matrixC30_14; +wire [`DWIDTH-1:0] matrixC30_15; +wire [`DWIDTH-1:0] matrixC30_16; +wire [`DWIDTH-1:0] matrixC30_17; +wire [`DWIDTH-1:0] matrixC30_18; +wire [`DWIDTH-1:0] matrixC30_19; +wire [`DWIDTH-1:0] matrixC30_20; +wire [`DWIDTH-1:0] matrixC30_21; +wire [`DWIDTH-1:0] matrixC30_22; +wire [`DWIDTH-1:0] matrixC30_23; +wire [`DWIDTH-1:0] matrixC30_24; +wire [`DWIDTH-1:0] matrixC30_25; +wire [`DWIDTH-1:0] matrixC30_26; +wire [`DWIDTH-1:0] matrixC30_27; +wire [`DWIDTH-1:0] matrixC30_28; +wire [`DWIDTH-1:0] matrixC30_29; +wire [`DWIDTH-1:0] matrixC30_30; +wire [`DWIDTH-1:0] matrixC30_31; +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC0_16(matrixC0_16), +.matrixC0_17(matrixC0_17), +.matrixC0_18(matrixC0_18), +.matrixC0_19(matrixC0_19), +.matrixC0_20(matrixC0_20), +.matrixC0_21(matrixC0_21), +.matrixC0_22(matrixC0_22), +.matrixC0_23(matrixC0_23), +.matrixC0_24(matrixC0_24), +.matrixC0_25(matrixC0_25), +.matrixC0_26(matrixC0_26), +.matrixC0_27(matrixC0_27), +.matrixC0_28(matrixC0_28), +.matrixC0_29(matrixC0_29), +.matrixC0_30(matrixC0_30), +.matrixC0_31(matrixC0_31), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC1_16(matrixC1_16), +.matrixC1_17(matrixC1_17), +.matrixC1_18(matrixC1_18), +.matrixC1_19(matrixC1_19), +.matrixC1_20(matrixC1_20), +.matrixC1_21(matrixC1_21), +.matrixC1_22(matrixC1_22), +.matrixC1_23(matrixC1_23), +.matrixC1_24(matrixC1_24), +.matrixC1_25(matrixC1_25), +.matrixC1_26(matrixC1_26), +.matrixC1_27(matrixC1_27), +.matrixC1_28(matrixC1_28), +.matrixC1_29(matrixC1_29), +.matrixC1_30(matrixC1_30), +.matrixC1_31(matrixC1_31), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC2_16(matrixC2_16), +.matrixC2_17(matrixC2_17), +.matrixC2_18(matrixC2_18), +.matrixC2_19(matrixC2_19), +.matrixC2_20(matrixC2_20), +.matrixC2_21(matrixC2_21), +.matrixC2_22(matrixC2_22), +.matrixC2_23(matrixC2_23), +.matrixC2_24(matrixC2_24), +.matrixC2_25(matrixC2_25), +.matrixC2_26(matrixC2_26), +.matrixC2_27(matrixC2_27), +.matrixC2_28(matrixC2_28), +.matrixC2_29(matrixC2_29), +.matrixC2_30(matrixC2_30), +.matrixC2_31(matrixC2_31), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC3_16(matrixC3_16), +.matrixC3_17(matrixC3_17), +.matrixC3_18(matrixC3_18), +.matrixC3_19(matrixC3_19), +.matrixC3_20(matrixC3_20), +.matrixC3_21(matrixC3_21), +.matrixC3_22(matrixC3_22), +.matrixC3_23(matrixC3_23), +.matrixC3_24(matrixC3_24), +.matrixC3_25(matrixC3_25), +.matrixC3_26(matrixC3_26), +.matrixC3_27(matrixC3_27), +.matrixC3_28(matrixC3_28), +.matrixC3_29(matrixC3_29), +.matrixC3_30(matrixC3_30), +.matrixC3_31(matrixC3_31), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC4_16(matrixC4_16), +.matrixC4_17(matrixC4_17), +.matrixC4_18(matrixC4_18), +.matrixC4_19(matrixC4_19), +.matrixC4_20(matrixC4_20), +.matrixC4_21(matrixC4_21), +.matrixC4_22(matrixC4_22), +.matrixC4_23(matrixC4_23), +.matrixC4_24(matrixC4_24), +.matrixC4_25(matrixC4_25), +.matrixC4_26(matrixC4_26), +.matrixC4_27(matrixC4_27), +.matrixC4_28(matrixC4_28), +.matrixC4_29(matrixC4_29), +.matrixC4_30(matrixC4_30), +.matrixC4_31(matrixC4_31), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC5_16(matrixC5_16), +.matrixC5_17(matrixC5_17), +.matrixC5_18(matrixC5_18), +.matrixC5_19(matrixC5_19), +.matrixC5_20(matrixC5_20), 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+.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.a16(a16), +.a17(a17), +.a18(a18), +.a19(a19), +.a20(a20), +.a21(a21), +.a22(a22), +.a23(a23), +.a24(a24), +.a25(a25), +.a26(a26), +.a27(a27), +.a28(a28), +.a29(a29), +.a30(a30), +.a31(a31), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.b16(b16), +.b17(b17), +.b18(b18), +.b19(b19), +.b20(b20), +.b21(b21), +.b22(b22), +.b23(b23), +.b24(b24), +.b25(b25), +.b26(b26), +.b27(b27), +.b28(b28), +.b29(b29), +.b30(b30), +.b31(b31), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), 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+.matrixC17_31(matrixC17_31), +.matrixC18_0(matrixC18_0), +.matrixC18_1(matrixC18_1), +.matrixC18_2(matrixC18_2), +.matrixC18_3(matrixC18_3), +.matrixC18_4(matrixC18_4), +.matrixC18_5(matrixC18_5), +.matrixC18_6(matrixC18_6), +.matrixC18_7(matrixC18_7), +.matrixC18_8(matrixC18_8), +.matrixC18_9(matrixC18_9), +.matrixC18_10(matrixC18_10), +.matrixC18_11(matrixC18_11), +.matrixC18_12(matrixC18_12), +.matrixC18_13(matrixC18_13), +.matrixC18_14(matrixC18_14), +.matrixC18_15(matrixC18_15), +.matrixC18_16(matrixC18_16), +.matrixC18_17(matrixC18_17), +.matrixC18_18(matrixC18_18), +.matrixC18_19(matrixC18_19), +.matrixC18_20(matrixC18_20), +.matrixC18_21(matrixC18_21), +.matrixC18_22(matrixC18_22), +.matrixC18_23(matrixC18_23), +.matrixC18_24(matrixC18_24), +.matrixC18_25(matrixC18_25), +.matrixC18_26(matrixC18_26), +.matrixC18_27(matrixC18_27), +.matrixC18_28(matrixC18_28), +.matrixC18_29(matrixC18_29), +.matrixC18_30(matrixC18_30), +.matrixC18_31(matrixC18_31), +.matrixC19_0(matrixC19_0), +.matrixC19_1(matrixC19_1), +.matrixC19_2(matrixC19_2), +.matrixC19_3(matrixC19_3), +.matrixC19_4(matrixC19_4), +.matrixC19_5(matrixC19_5), +.matrixC19_6(matrixC19_6), +.matrixC19_7(matrixC19_7), +.matrixC19_8(matrixC19_8), +.matrixC19_9(matrixC19_9), +.matrixC19_10(matrixC19_10), +.matrixC19_11(matrixC19_11), +.matrixC19_12(matrixC19_12), +.matrixC19_13(matrixC19_13), +.matrixC19_14(matrixC19_14), +.matrixC19_15(matrixC19_15), +.matrixC19_16(matrixC19_16), +.matrixC19_17(matrixC19_17), +.matrixC19_18(matrixC19_18), +.matrixC19_19(matrixC19_19), +.matrixC19_20(matrixC19_20), +.matrixC19_21(matrixC19_21), +.matrixC19_22(matrixC19_22), +.matrixC19_23(matrixC19_23), +.matrixC19_24(matrixC19_24), +.matrixC19_25(matrixC19_25), +.matrixC19_26(matrixC19_26), +.matrixC19_27(matrixC19_27), +.matrixC19_28(matrixC19_28), +.matrixC19_29(matrixC19_29), +.matrixC19_30(matrixC19_30), +.matrixC19_31(matrixC19_31), +.matrixC20_0(matrixC20_0), +.matrixC20_1(matrixC20_1), +.matrixC20_2(matrixC20_2), +.matrixC20_3(matrixC20_3), +.matrixC20_4(matrixC20_4), +.matrixC20_5(matrixC20_5), +.matrixC20_6(matrixC20_6), +.matrixC20_7(matrixC20_7), +.matrixC20_8(matrixC20_8), +.matrixC20_9(matrixC20_9), +.matrixC20_10(matrixC20_10), +.matrixC20_11(matrixC20_11), +.matrixC20_12(matrixC20_12), +.matrixC20_13(matrixC20_13), +.matrixC20_14(matrixC20_14), +.matrixC20_15(matrixC20_15), +.matrixC20_16(matrixC20_16), +.matrixC20_17(matrixC20_17), +.matrixC20_18(matrixC20_18), +.matrixC20_19(matrixC20_19), +.matrixC20_20(matrixC20_20), +.matrixC20_21(matrixC20_21), +.matrixC20_22(matrixC20_22), +.matrixC20_23(matrixC20_23), +.matrixC20_24(matrixC20_24), +.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC0_16; +input [`DWIDTH-1:0] matrixC0_17; +input [`DWIDTH-1:0] matrixC0_18; +input [`DWIDTH-1:0] matrixC0_19; +input [`DWIDTH-1:0] matrixC0_20; +input [`DWIDTH-1:0] matrixC0_21; +input [`DWIDTH-1:0] matrixC0_22; +input [`DWIDTH-1:0] matrixC0_23; +input [`DWIDTH-1:0] matrixC0_24; +input [`DWIDTH-1:0] matrixC0_25; +input [`DWIDTH-1:0] matrixC0_26; +input [`DWIDTH-1:0] matrixC0_27; +input [`DWIDTH-1:0] matrixC0_28; +input [`DWIDTH-1:0] matrixC0_29; +input [`DWIDTH-1:0] matrixC0_30; +input [`DWIDTH-1:0] matrixC0_31; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC1_16; +input [`DWIDTH-1:0] matrixC1_17; +input [`DWIDTH-1:0] matrixC1_18; +input [`DWIDTH-1:0] matrixC1_19; +input [`DWIDTH-1:0] matrixC1_20; +input [`DWIDTH-1:0] matrixC1_21; +input [`DWIDTH-1:0] matrixC1_22; +input [`DWIDTH-1:0] matrixC1_23; +input [`DWIDTH-1:0] matrixC1_24; +input [`DWIDTH-1:0] matrixC1_25; +input [`DWIDTH-1:0] matrixC1_26; +input [`DWIDTH-1:0] matrixC1_27; +input [`DWIDTH-1:0] matrixC1_28; +input [`DWIDTH-1:0] matrixC1_29; +input [`DWIDTH-1:0] matrixC1_30; +input [`DWIDTH-1:0] matrixC1_31; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC2_16; +input [`DWIDTH-1:0] matrixC2_17; +input [`DWIDTH-1:0] matrixC2_18; +input [`DWIDTH-1:0] matrixC2_19; +input [`DWIDTH-1:0] matrixC2_20; +input [`DWIDTH-1:0] matrixC2_21; +input [`DWIDTH-1:0] matrixC2_22; +input [`DWIDTH-1:0] matrixC2_23; +input [`DWIDTH-1:0] matrixC2_24; +input [`DWIDTH-1:0] matrixC2_25; +input [`DWIDTH-1:0] matrixC2_26; +input [`DWIDTH-1:0] matrixC2_27; +input [`DWIDTH-1:0] matrixC2_28; +input [`DWIDTH-1:0] matrixC2_29; +input [`DWIDTH-1:0] matrixC2_30; +input [`DWIDTH-1:0] matrixC2_31; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC3_16; +input [`DWIDTH-1:0] matrixC3_17; +input [`DWIDTH-1:0] matrixC3_18; +input [`DWIDTH-1:0] matrixC3_19; +input [`DWIDTH-1:0] matrixC3_20; +input [`DWIDTH-1:0] matrixC3_21; +input [`DWIDTH-1:0] matrixC3_22; +input [`DWIDTH-1:0] matrixC3_23; +input [`DWIDTH-1:0] matrixC3_24; +input [`DWIDTH-1:0] matrixC3_25; +input [`DWIDTH-1:0] matrixC3_26; +input [`DWIDTH-1:0] matrixC3_27; +input [`DWIDTH-1:0] matrixC3_28; +input [`DWIDTH-1:0] matrixC3_29; +input [`DWIDTH-1:0] matrixC3_30; +input [`DWIDTH-1:0] matrixC3_31; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC4_16; +input [`DWIDTH-1:0] matrixC4_17; +input [`DWIDTH-1:0] matrixC4_18; +input [`DWIDTH-1:0] matrixC4_19; +input [`DWIDTH-1:0] matrixC4_20; +input [`DWIDTH-1:0] matrixC4_21; +input [`DWIDTH-1:0] matrixC4_22; +input [`DWIDTH-1:0] matrixC4_23; +input [`DWIDTH-1:0] matrixC4_24; +input [`DWIDTH-1:0] matrixC4_25; +input [`DWIDTH-1:0] matrixC4_26; +input [`DWIDTH-1:0] matrixC4_27; +input [`DWIDTH-1:0] matrixC4_28; +input [`DWIDTH-1:0] matrixC4_29; +input [`DWIDTH-1:0] matrixC4_30; +input [`DWIDTH-1:0] matrixC4_31; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC5_16; +input [`DWIDTH-1:0] matrixC5_17; +input [`DWIDTH-1:0] matrixC5_18; +input [`DWIDTH-1:0] matrixC5_19; +input [`DWIDTH-1:0] matrixC5_20; +input [`DWIDTH-1:0] matrixC5_21; +input [`DWIDTH-1:0] matrixC5_22; +input [`DWIDTH-1:0] matrixC5_23; +input [`DWIDTH-1:0] matrixC5_24; +input [`DWIDTH-1:0] matrixC5_25; +input [`DWIDTH-1:0] matrixC5_26; +input [`DWIDTH-1:0] matrixC5_27; +input [`DWIDTH-1:0] matrixC5_28; +input [`DWIDTH-1:0] matrixC5_29; +input [`DWIDTH-1:0] matrixC5_30; +input [`DWIDTH-1:0] matrixC5_31; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC6_16; +input [`DWIDTH-1:0] matrixC6_17; +input [`DWIDTH-1:0] matrixC6_18; +input [`DWIDTH-1:0] matrixC6_19; +input [`DWIDTH-1:0] matrixC6_20; +input [`DWIDTH-1:0] matrixC6_21; +input [`DWIDTH-1:0] matrixC6_22; +input [`DWIDTH-1:0] matrixC6_23; +input [`DWIDTH-1:0] matrixC6_24; +input [`DWIDTH-1:0] matrixC6_25; +input [`DWIDTH-1:0] matrixC6_26; +input [`DWIDTH-1:0] matrixC6_27; +input [`DWIDTH-1:0] matrixC6_28; +input [`DWIDTH-1:0] matrixC6_29; +input [`DWIDTH-1:0] matrixC6_30; +input [`DWIDTH-1:0] matrixC6_31; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC7_16; +input [`DWIDTH-1:0] matrixC7_17; +input [`DWIDTH-1:0] matrixC7_18; +input [`DWIDTH-1:0] matrixC7_19; +input [`DWIDTH-1:0] matrixC7_20; +input [`DWIDTH-1:0] matrixC7_21; +input [`DWIDTH-1:0] matrixC7_22; +input [`DWIDTH-1:0] matrixC7_23; +input [`DWIDTH-1:0] matrixC7_24; +input [`DWIDTH-1:0] matrixC7_25; +input [`DWIDTH-1:0] matrixC7_26; +input [`DWIDTH-1:0] matrixC7_27; +input [`DWIDTH-1:0] matrixC7_28; +input [`DWIDTH-1:0] matrixC7_29; +input [`DWIDTH-1:0] matrixC7_30; +input [`DWIDTH-1:0] matrixC7_31; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC8_16; +input [`DWIDTH-1:0] matrixC8_17; +input [`DWIDTH-1:0] matrixC8_18; +input [`DWIDTH-1:0] matrixC8_19; +input [`DWIDTH-1:0] matrixC8_20; +input [`DWIDTH-1:0] matrixC8_21; +input [`DWIDTH-1:0] matrixC8_22; +input [`DWIDTH-1:0] matrixC8_23; +input [`DWIDTH-1:0] matrixC8_24; +input [`DWIDTH-1:0] matrixC8_25; +input [`DWIDTH-1:0] matrixC8_26; +input [`DWIDTH-1:0] matrixC8_27; +input [`DWIDTH-1:0] matrixC8_28; +input [`DWIDTH-1:0] matrixC8_29; +input [`DWIDTH-1:0] matrixC8_30; +input [`DWIDTH-1:0] matrixC8_31; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC9_16; +input [`DWIDTH-1:0] matrixC9_17; +input [`DWIDTH-1:0] matrixC9_18; +input [`DWIDTH-1:0] matrixC9_19; +input [`DWIDTH-1:0] matrixC9_20; +input [`DWIDTH-1:0] matrixC9_21; +input [`DWIDTH-1:0] matrixC9_22; +input [`DWIDTH-1:0] matrixC9_23; +input [`DWIDTH-1:0] matrixC9_24; +input [`DWIDTH-1:0] matrixC9_25; +input [`DWIDTH-1:0] matrixC9_26; +input [`DWIDTH-1:0] matrixC9_27; +input [`DWIDTH-1:0] matrixC9_28; +input [`DWIDTH-1:0] matrixC9_29; +input [`DWIDTH-1:0] matrixC9_30; +input [`DWIDTH-1:0] matrixC9_31; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC10_16; +input [`DWIDTH-1:0] matrixC10_17; +input [`DWIDTH-1:0] matrixC10_18; +input [`DWIDTH-1:0] matrixC10_19; +input [`DWIDTH-1:0] matrixC10_20; +input [`DWIDTH-1:0] matrixC10_21; +input [`DWIDTH-1:0] matrixC10_22; +input [`DWIDTH-1:0] matrixC10_23; +input [`DWIDTH-1:0] matrixC10_24; +input [`DWIDTH-1:0] matrixC10_25; +input [`DWIDTH-1:0] matrixC10_26; +input [`DWIDTH-1:0] matrixC10_27; +input [`DWIDTH-1:0] matrixC10_28; +input [`DWIDTH-1:0] matrixC10_29; +input [`DWIDTH-1:0] matrixC10_30; +input [`DWIDTH-1:0] matrixC10_31; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC11_16; +input [`DWIDTH-1:0] matrixC11_17; +input [`DWIDTH-1:0] matrixC11_18; +input [`DWIDTH-1:0] matrixC11_19; +input [`DWIDTH-1:0] matrixC11_20; +input [`DWIDTH-1:0] matrixC11_21; +input [`DWIDTH-1:0] matrixC11_22; +input [`DWIDTH-1:0] matrixC11_23; +input [`DWIDTH-1:0] matrixC11_24; +input [`DWIDTH-1:0] matrixC11_25; +input [`DWIDTH-1:0] matrixC11_26; +input [`DWIDTH-1:0] matrixC11_27; +input [`DWIDTH-1:0] matrixC11_28; +input [`DWIDTH-1:0] matrixC11_29; +input [`DWIDTH-1:0] matrixC11_30; +input [`DWIDTH-1:0] matrixC11_31; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC12_16; +input [`DWIDTH-1:0] matrixC12_17; +input [`DWIDTH-1:0] matrixC12_18; +input [`DWIDTH-1:0] matrixC12_19; +input [`DWIDTH-1:0] matrixC12_20; +input [`DWIDTH-1:0] matrixC12_21; +input [`DWIDTH-1:0] matrixC12_22; +input [`DWIDTH-1:0] matrixC12_23; +input [`DWIDTH-1:0] matrixC12_24; +input [`DWIDTH-1:0] matrixC12_25; +input [`DWIDTH-1:0] matrixC12_26; +input [`DWIDTH-1:0] matrixC12_27; +input [`DWIDTH-1:0] matrixC12_28; +input [`DWIDTH-1:0] matrixC12_29; +input [`DWIDTH-1:0] matrixC12_30; +input [`DWIDTH-1:0] matrixC12_31; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC13_16; +input [`DWIDTH-1:0] matrixC13_17; +input [`DWIDTH-1:0] matrixC13_18; +input [`DWIDTH-1:0] matrixC13_19; +input [`DWIDTH-1:0] matrixC13_20; +input [`DWIDTH-1:0] matrixC13_21; +input [`DWIDTH-1:0] matrixC13_22; +input [`DWIDTH-1:0] matrixC13_23; +input [`DWIDTH-1:0] matrixC13_24; +input [`DWIDTH-1:0] matrixC13_25; +input [`DWIDTH-1:0] matrixC13_26; +input [`DWIDTH-1:0] matrixC13_27; +input [`DWIDTH-1:0] matrixC13_28; +input [`DWIDTH-1:0] matrixC13_29; +input [`DWIDTH-1:0] matrixC13_30; +input [`DWIDTH-1:0] matrixC13_31; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC14_16; +input [`DWIDTH-1:0] matrixC14_17; +input [`DWIDTH-1:0] matrixC14_18; +input [`DWIDTH-1:0] matrixC14_19; +input [`DWIDTH-1:0] matrixC14_20; +input [`DWIDTH-1:0] matrixC14_21; +input [`DWIDTH-1:0] matrixC14_22; +input [`DWIDTH-1:0] matrixC14_23; +input [`DWIDTH-1:0] matrixC14_24; +input [`DWIDTH-1:0] matrixC14_25; +input [`DWIDTH-1:0] matrixC14_26; +input [`DWIDTH-1:0] matrixC14_27; +input [`DWIDTH-1:0] matrixC14_28; +input [`DWIDTH-1:0] matrixC14_29; +input [`DWIDTH-1:0] matrixC14_30; +input [`DWIDTH-1:0] matrixC14_31; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +input [`DWIDTH-1:0] matrixC15_16; +input [`DWIDTH-1:0] matrixC15_17; +input [`DWIDTH-1:0] matrixC15_18; +input [`DWIDTH-1:0] matrixC15_19; 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+input [`DWIDTH-1:0] matrixC26_12; +input [`DWIDTH-1:0] matrixC26_13; +input [`DWIDTH-1:0] matrixC26_14; +input [`DWIDTH-1:0] matrixC26_15; +input [`DWIDTH-1:0] matrixC26_16; +input [`DWIDTH-1:0] matrixC26_17; +input [`DWIDTH-1:0] matrixC26_18; +input [`DWIDTH-1:0] matrixC26_19; +input [`DWIDTH-1:0] matrixC26_20; +input [`DWIDTH-1:0] matrixC26_21; +input [`DWIDTH-1:0] matrixC26_22; +input [`DWIDTH-1:0] matrixC26_23; +input [`DWIDTH-1:0] matrixC26_24; +input [`DWIDTH-1:0] matrixC26_25; +input [`DWIDTH-1:0] matrixC26_26; +input [`DWIDTH-1:0] matrixC26_27; +input [`DWIDTH-1:0] matrixC26_28; +input [`DWIDTH-1:0] matrixC26_29; +input [`DWIDTH-1:0] matrixC26_30; +input [`DWIDTH-1:0] matrixC26_31; +input [`DWIDTH-1:0] matrixC27_0; +input [`DWIDTH-1:0] matrixC27_1; +input [`DWIDTH-1:0] matrixC27_2; +input [`DWIDTH-1:0] matrixC27_3; +input [`DWIDTH-1:0] matrixC27_4; +input [`DWIDTH-1:0] matrixC27_5; +input [`DWIDTH-1:0] matrixC27_6; +input [`DWIDTH-1:0] matrixC27_7; +input [`DWIDTH-1:0] matrixC27_8; +input [`DWIDTH-1:0] matrixC27_9; +input [`DWIDTH-1:0] matrixC27_10; +input [`DWIDTH-1:0] matrixC27_11; +input [`DWIDTH-1:0] matrixC27_12; +input [`DWIDTH-1:0] matrixC27_13; +input [`DWIDTH-1:0] matrixC27_14; +input [`DWIDTH-1:0] matrixC27_15; +input [`DWIDTH-1:0] matrixC27_16; +input [`DWIDTH-1:0] matrixC27_17; +input [`DWIDTH-1:0] matrixC27_18; +input [`DWIDTH-1:0] matrixC27_19; +input [`DWIDTH-1:0] matrixC27_20; +input [`DWIDTH-1:0] matrixC27_21; +input [`DWIDTH-1:0] matrixC27_22; +input [`DWIDTH-1:0] matrixC27_23; +input [`DWIDTH-1:0] matrixC27_24; +input [`DWIDTH-1:0] matrixC27_25; +input [`DWIDTH-1:0] matrixC27_26; +input [`DWIDTH-1:0] matrixC27_27; +input [`DWIDTH-1:0] matrixC27_28; +input [`DWIDTH-1:0] matrixC27_29; +input [`DWIDTH-1:0] matrixC27_30; +input [`DWIDTH-1:0] matrixC27_31; +input [`DWIDTH-1:0] matrixC28_0; +input [`DWIDTH-1:0] matrixC28_1; +input [`DWIDTH-1:0] matrixC28_2; +input [`DWIDTH-1:0] matrixC28_3; +input [`DWIDTH-1:0] matrixC28_4; +input [`DWIDTH-1:0] matrixC28_5; +input [`DWIDTH-1:0] matrixC28_6; +input [`DWIDTH-1:0] matrixC28_7; +input [`DWIDTH-1:0] matrixC28_8; +input [`DWIDTH-1:0] matrixC28_9; +input [`DWIDTH-1:0] matrixC28_10; +input [`DWIDTH-1:0] matrixC28_11; +input [`DWIDTH-1:0] matrixC28_12; +input [`DWIDTH-1:0] matrixC28_13; +input [`DWIDTH-1:0] matrixC28_14; +input [`DWIDTH-1:0] matrixC28_15; +input [`DWIDTH-1:0] matrixC28_16; +input [`DWIDTH-1:0] matrixC28_17; +input [`DWIDTH-1:0] matrixC28_18; +input [`DWIDTH-1:0] matrixC28_19; +input [`DWIDTH-1:0] matrixC28_20; +input [`DWIDTH-1:0] matrixC28_21; +input [`DWIDTH-1:0] matrixC28_22; +input [`DWIDTH-1:0] matrixC28_23; +input [`DWIDTH-1:0] matrixC28_24; +input [`DWIDTH-1:0] matrixC28_25; +input [`DWIDTH-1:0] matrixC28_26; +input [`DWIDTH-1:0] matrixC28_27; +input [`DWIDTH-1:0] matrixC28_28; +input [`DWIDTH-1:0] matrixC28_29; +input [`DWIDTH-1:0] matrixC28_30; +input [`DWIDTH-1:0] matrixC28_31; +input [`DWIDTH-1:0] matrixC29_0; +input [`DWIDTH-1:0] matrixC29_1; +input [`DWIDTH-1:0] matrixC29_2; +input [`DWIDTH-1:0] matrixC29_3; +input [`DWIDTH-1:0] matrixC29_4; +input [`DWIDTH-1:0] matrixC29_5; +input [`DWIDTH-1:0] matrixC29_6; +input [`DWIDTH-1:0] matrixC29_7; +input [`DWIDTH-1:0] matrixC29_8; +input [`DWIDTH-1:0] matrixC29_9; +input [`DWIDTH-1:0] matrixC29_10; +input [`DWIDTH-1:0] matrixC29_11; +input [`DWIDTH-1:0] matrixC29_12; +input [`DWIDTH-1:0] matrixC29_13; +input [`DWIDTH-1:0] matrixC29_14; +input [`DWIDTH-1:0] matrixC29_15; +input [`DWIDTH-1:0] matrixC29_16; +input [`DWIDTH-1:0] matrixC29_17; +input [`DWIDTH-1:0] matrixC29_18; +input [`DWIDTH-1:0] matrixC29_19; +input [`DWIDTH-1:0] matrixC29_20; +input [`DWIDTH-1:0] matrixC29_21; +input [`DWIDTH-1:0] matrixC29_22; +input [`DWIDTH-1:0] matrixC29_23; +input [`DWIDTH-1:0] matrixC29_24; +input [`DWIDTH-1:0] matrixC29_25; +input [`DWIDTH-1:0] matrixC29_26; +input [`DWIDTH-1:0] matrixC29_27; +input [`DWIDTH-1:0] matrixC29_28; +input [`DWIDTH-1:0] matrixC29_29; +input [`DWIDTH-1:0] matrixC29_30; +input [`DWIDTH-1:0] matrixC29_31; +input [`DWIDTH-1:0] matrixC30_0; +input [`DWIDTH-1:0] matrixC30_1; +input [`DWIDTH-1:0] matrixC30_2; +input [`DWIDTH-1:0] matrixC30_3; +input [`DWIDTH-1:0] matrixC30_4; +input [`DWIDTH-1:0] matrixC30_5; +input [`DWIDTH-1:0] matrixC30_6; +input [`DWIDTH-1:0] matrixC30_7; +input [`DWIDTH-1:0] matrixC30_8; +input [`DWIDTH-1:0] matrixC30_9; +input [`DWIDTH-1:0] matrixC30_10; +input [`DWIDTH-1:0] matrixC30_11; +input [`DWIDTH-1:0] matrixC30_12; +input [`DWIDTH-1:0] matrixC30_13; +input [`DWIDTH-1:0] matrixC30_14; +input [`DWIDTH-1:0] matrixC30_15; +input [`DWIDTH-1:0] matrixC30_16; +input [`DWIDTH-1:0] matrixC30_17; +input [`DWIDTH-1:0] matrixC30_18; +input [`DWIDTH-1:0] matrixC30_19; +input [`DWIDTH-1:0] matrixC30_20; +input [`DWIDTH-1:0] matrixC30_21; +input [`DWIDTH-1:0] matrixC30_22; +input [`DWIDTH-1:0] matrixC30_23; +input [`DWIDTH-1:0] matrixC30_24; +input [`DWIDTH-1:0] matrixC30_25; +input [`DWIDTH-1:0] matrixC30_26; +input [`DWIDTH-1:0] matrixC30_27; +input [`DWIDTH-1:0] matrixC30_28; +input [`DWIDTH-1:0] matrixC30_29; +input [`DWIDTH-1:0] matrixC30_30; +input [`DWIDTH-1:0] matrixC30_31; +input [`DWIDTH-1:0] matrixC31_0; +input [`DWIDTH-1:0] matrixC31_1; +input [`DWIDTH-1:0] matrixC31_2; +input [`DWIDTH-1:0] matrixC31_3; +input [`DWIDTH-1:0] matrixC31_4; +input [`DWIDTH-1:0] matrixC31_5; +input [`DWIDTH-1:0] matrixC31_6; +input [`DWIDTH-1:0] matrixC31_7; +input [`DWIDTH-1:0] matrixC31_8; +input [`DWIDTH-1:0] matrixC31_9; +input [`DWIDTH-1:0] matrixC31_10; +input [`DWIDTH-1:0] matrixC31_11; +input [`DWIDTH-1:0] matrixC31_12; +input [`DWIDTH-1:0] matrixC31_13; +input [`DWIDTH-1:0] matrixC31_14; +input [`DWIDTH-1:0] matrixC31_15; +input [`DWIDTH-1:0] matrixC31_16; +input [`DWIDTH-1:0] matrixC31_17; +input [`DWIDTH-1:0] matrixC31_18; +input [`DWIDTH-1:0] matrixC31_19; +input [`DWIDTH-1:0] matrixC31_20; +input [`DWIDTH-1:0] matrixC31_21; +input [`DWIDTH-1:0] matrixC31_22; +input [`DWIDTH-1:0] matrixC31_23; +input [`DWIDTH-1:0] matrixC31_24; +input [`DWIDTH-1:0] matrixC31_25; +input [`DWIDTH-1:0] matrixC31_26; +input [`DWIDTH-1:0] matrixC31_27; +input [`DWIDTH-1:0] matrixC31_28; +input [`DWIDTH-1:0] matrixC31_29; +input [`DWIDTH-1:0] matrixC31_30; +input [`DWIDTH-1:0] matrixC31_31; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((`final_mat_mul_size<<2) - `final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +reg [31:0] counter; +reg [32*`DWIDTH-1:0] c_data_out; +reg [32*`DWIDTH-1:0] c_data_out_1; +reg [32*`DWIDTH-1:0] c_data_out_2; +reg [32*`DWIDTH-1:0] c_data_out_3; +reg [32*`DWIDTH-1:0] c_data_out_4; +reg [32*`DWIDTH-1:0] c_data_out_5; +reg [32*`DWIDTH-1:0] c_data_out_6; +reg [32*`DWIDTH-1:0] c_data_out_7; +reg [32*`DWIDTH-1:0] c_data_out_8; +reg [32*`DWIDTH-1:0] c_data_out_9; +reg [32*`DWIDTH-1:0] c_data_out_10; +reg [32*`DWIDTH-1:0] c_data_out_11; +reg [32*`DWIDTH-1:0] c_data_out_12; +reg [32*`DWIDTH-1:0] c_data_out_13; +reg [32*`DWIDTH-1:0] c_data_out_14; +reg [32*`DWIDTH-1:0] c_data_out_15; +reg [32*`DWIDTH-1:0] c_data_out_16; +reg [32*`DWIDTH-1:0] c_data_out_17; +reg [32*`DWIDTH-1:0] c_data_out_18; +reg [32*`DWIDTH-1:0] c_data_out_19; +reg [32*`DWIDTH-1:0] c_data_out_20; +reg [32*`DWIDTH-1:0] c_data_out_21; +reg [32*`DWIDTH-1:0] c_data_out_22; +reg [32*`DWIDTH-1:0] c_data_out_23; +reg [32*`DWIDTH-1:0] c_data_out_24; +reg [32*`DWIDTH-1:0] c_data_out_25; +reg [32*`DWIDTH-1:0] c_data_out_26; +reg [32*`DWIDTH-1:0] c_data_out_27; +reg [32*`DWIDTH-1:0] c_data_out_28; +reg [32*`DWIDTH-1:0] c_data_out_29; +reg [32*`DWIDTH-1:0] c_data_out_30; +reg [32*`DWIDTH-1:0] c_data_out_31; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC31_31, matrixC30_31, matrixC29_31, matrixC28_31, matrixC27_31, matrixC26_31, matrixC25_31, matrixC24_31, matrixC23_31, matrixC22_31, matrixC21_31, matrixC20_31, matrixC19_31, matrixC18_31, matrixC17_31, matrixC16_31, matrixC15_31, matrixC14_31, matrixC13_31, matrixC12_31, matrixC11_31, matrixC10_31, matrixC9_31, matrixC8_31, matrixC7_31, matrixC6_31, matrixC5_31, matrixC4_31, matrixC3_31, matrixC2_31, matrixC1_31, matrixC0_31}; + c_data_out_1 <= {matrixC31_30, matrixC30_30, matrixC29_30, matrixC28_30, matrixC27_30, matrixC26_30, matrixC25_30, matrixC24_30, matrixC23_30, matrixC22_30, matrixC21_30, matrixC20_30, matrixC19_30, matrixC18_30, matrixC17_30, matrixC16_30, matrixC15_30, matrixC14_30, matrixC13_30, matrixC12_30, matrixC11_30, matrixC10_30, matrixC9_30, matrixC8_30, matrixC7_30, matrixC6_30, matrixC5_30, matrixC4_30, matrixC3_30, matrixC2_30, matrixC1_30, matrixC0_30}; + c_data_out_2 <= {matrixC31_29, matrixC30_29, matrixC29_29, matrixC28_29, matrixC27_29, matrixC26_29, matrixC25_29, matrixC24_29, matrixC23_29, matrixC22_29, matrixC21_29, matrixC20_29, matrixC19_29, matrixC18_29, matrixC17_29, matrixC16_29, matrixC15_29, matrixC14_29, matrixC13_29, matrixC12_29, matrixC11_29, matrixC10_29, matrixC9_29, matrixC8_29, matrixC7_29, matrixC6_29, matrixC5_29, matrixC4_29, matrixC3_29, matrixC2_29, matrixC1_29, matrixC0_29}; + c_data_out_3 <= {matrixC31_28, matrixC30_28, matrixC29_28, matrixC28_28, matrixC27_28, matrixC26_28, matrixC25_28, matrixC24_28, matrixC23_28, matrixC22_28, matrixC21_28, matrixC20_28, matrixC19_28, matrixC18_28, matrixC17_28, matrixC16_28, matrixC15_28, matrixC14_28, matrixC13_28, matrixC12_28, matrixC11_28, matrixC10_28, matrixC9_28, matrixC8_28, matrixC7_28, matrixC6_28, matrixC5_28, matrixC4_28, matrixC3_28, matrixC2_28, matrixC1_28, matrixC0_28}; + c_data_out_4 <= {matrixC31_27, matrixC30_27, matrixC29_27, matrixC28_27, matrixC27_27, matrixC26_27, matrixC25_27, matrixC24_27, matrixC23_27, matrixC22_27, matrixC21_27, matrixC20_27, matrixC19_27, matrixC18_27, matrixC17_27, matrixC16_27, matrixC15_27, matrixC14_27, matrixC13_27, matrixC12_27, matrixC11_27, matrixC10_27, matrixC9_27, matrixC8_27, matrixC7_27, matrixC6_27, matrixC5_27, matrixC4_27, matrixC3_27, matrixC2_27, matrixC1_27, matrixC0_27}; + c_data_out_5 <= {matrixC31_26, matrixC30_26, matrixC29_26, matrixC28_26, matrixC27_26, matrixC26_26, matrixC25_26, matrixC24_26, matrixC23_26, matrixC22_26, matrixC21_26, matrixC20_26, matrixC19_26, matrixC18_26, matrixC17_26, matrixC16_26, matrixC15_26, matrixC14_26, matrixC13_26, matrixC12_26, matrixC11_26, matrixC10_26, matrixC9_26, matrixC8_26, matrixC7_26, matrixC6_26, matrixC5_26, matrixC4_26, matrixC3_26, matrixC2_26, matrixC1_26, matrixC0_26}; + c_data_out_6 <= {matrixC31_25, matrixC30_25, matrixC29_25, matrixC28_25, matrixC27_25, matrixC26_25, matrixC25_25, matrixC24_25, matrixC23_25, matrixC22_25, matrixC21_25, matrixC20_25, matrixC19_25, matrixC18_25, matrixC17_25, matrixC16_25, matrixC15_25, matrixC14_25, matrixC13_25, matrixC12_25, matrixC11_25, matrixC10_25, matrixC9_25, matrixC8_25, matrixC7_25, matrixC6_25, matrixC5_25, matrixC4_25, matrixC3_25, matrixC2_25, matrixC1_25, matrixC0_25}; + c_data_out_7 <= {matrixC31_24, matrixC30_24, matrixC29_24, matrixC28_24, matrixC27_24, matrixC26_24, matrixC25_24, matrixC24_24, matrixC23_24, matrixC22_24, matrixC21_24, matrixC20_24, matrixC19_24, matrixC18_24, matrixC17_24, matrixC16_24, matrixC15_24, matrixC14_24, matrixC13_24, matrixC12_24, matrixC11_24, matrixC10_24, matrixC9_24, matrixC8_24, matrixC7_24, matrixC6_24, matrixC5_24, matrixC4_24, matrixC3_24, matrixC2_24, matrixC1_24, matrixC0_24}; + c_data_out_8 <= {matrixC31_23, matrixC30_23, matrixC29_23, matrixC28_23, matrixC27_23, matrixC26_23, matrixC25_23, matrixC24_23, matrixC23_23, matrixC22_23, matrixC21_23, matrixC20_23, matrixC19_23, matrixC18_23, matrixC17_23, matrixC16_23, matrixC15_23, matrixC14_23, matrixC13_23, matrixC12_23, matrixC11_23, matrixC10_23, matrixC9_23, matrixC8_23, matrixC7_23, matrixC6_23, matrixC5_23, matrixC4_23, matrixC3_23, matrixC2_23, matrixC1_23, matrixC0_23}; + c_data_out_9 <= {matrixC31_22, matrixC30_22, matrixC29_22, matrixC28_22, matrixC27_22, matrixC26_22, matrixC25_22, matrixC24_22, matrixC23_22, matrixC22_22, matrixC21_22, matrixC20_22, matrixC19_22, matrixC18_22, matrixC17_22, matrixC16_22, matrixC15_22, matrixC14_22, matrixC13_22, matrixC12_22, matrixC11_22, matrixC10_22, matrixC9_22, matrixC8_22, matrixC7_22, matrixC6_22, matrixC5_22, matrixC4_22, matrixC3_22, matrixC2_22, matrixC1_22, matrixC0_22}; + c_data_out_10 <= {matrixC31_21, matrixC30_21, matrixC29_21, matrixC28_21, matrixC27_21, matrixC26_21, matrixC25_21, matrixC24_21, matrixC23_21, matrixC22_21, matrixC21_21, matrixC20_21, matrixC19_21, matrixC18_21, matrixC17_21, matrixC16_21, matrixC15_21, matrixC14_21, matrixC13_21, matrixC12_21, matrixC11_21, matrixC10_21, matrixC9_21, matrixC8_21, matrixC7_21, matrixC6_21, matrixC5_21, matrixC4_21, matrixC3_21, matrixC2_21, matrixC1_21, matrixC0_21}; + c_data_out_11 <= {matrixC31_20, matrixC30_20, matrixC29_20, matrixC28_20, matrixC27_20, matrixC26_20, matrixC25_20, matrixC24_20, matrixC23_20, matrixC22_20, matrixC21_20, matrixC20_20, matrixC19_20, matrixC18_20, matrixC17_20, matrixC16_20, matrixC15_20, matrixC14_20, matrixC13_20, matrixC12_20, matrixC11_20, matrixC10_20, matrixC9_20, matrixC8_20, matrixC7_20, matrixC6_20, matrixC5_20, matrixC4_20, matrixC3_20, matrixC2_20, matrixC1_20, matrixC0_20}; + c_data_out_12 <= {matrixC31_19, matrixC30_19, matrixC29_19, matrixC28_19, matrixC27_19, matrixC26_19, matrixC25_19, matrixC24_19, matrixC23_19, matrixC22_19, matrixC21_19, matrixC20_19, matrixC19_19, matrixC18_19, matrixC17_19, matrixC16_19, matrixC15_19, matrixC14_19, matrixC13_19, matrixC12_19, matrixC11_19, matrixC10_19, matrixC9_19, matrixC8_19, matrixC7_19, matrixC6_19, matrixC5_19, matrixC4_19, matrixC3_19, matrixC2_19, matrixC1_19, matrixC0_19}; + c_data_out_13 <= {matrixC31_18, matrixC30_18, matrixC29_18, matrixC28_18, matrixC27_18, matrixC26_18, matrixC25_18, matrixC24_18, matrixC23_18, matrixC22_18, matrixC21_18, matrixC20_18, matrixC19_18, matrixC18_18, matrixC17_18, matrixC16_18, matrixC15_18, matrixC14_18, matrixC13_18, matrixC12_18, matrixC11_18, matrixC10_18, matrixC9_18, matrixC8_18, matrixC7_18, matrixC6_18, matrixC5_18, matrixC4_18, matrixC3_18, matrixC2_18, matrixC1_18, matrixC0_18}; + c_data_out_14 <= {matrixC31_17, matrixC30_17, matrixC29_17, matrixC28_17, matrixC27_17, matrixC26_17, matrixC25_17, matrixC24_17, matrixC23_17, matrixC22_17, matrixC21_17, matrixC20_17, matrixC19_17, matrixC18_17, matrixC17_17, matrixC16_17, matrixC15_17, matrixC14_17, matrixC13_17, matrixC12_17, matrixC11_17, matrixC10_17, matrixC9_17, matrixC8_17, matrixC7_17, matrixC6_17, matrixC5_17, matrixC4_17, matrixC3_17, matrixC2_17, matrixC1_17, matrixC0_17}; + c_data_out_15 <= {matrixC31_16, matrixC30_16, matrixC29_16, matrixC28_16, matrixC27_16, matrixC26_16, matrixC25_16, matrixC24_16, matrixC23_16, matrixC22_16, matrixC21_16, matrixC20_16, matrixC19_16, matrixC18_16, matrixC17_16, matrixC16_16, matrixC15_16, matrixC14_16, matrixC13_16, matrixC12_16, matrixC11_16, matrixC10_16, matrixC9_16, matrixC8_16, matrixC7_16, matrixC6_16, matrixC5_16, matrixC4_16, matrixC3_16, matrixC2_16, matrixC1_16, matrixC0_16}; + c_data_out_16 <= {matrixC31_15, matrixC30_15, matrixC29_15, matrixC28_15, matrixC27_15, matrixC26_15, matrixC25_15, matrixC24_15, matrixC23_15, matrixC22_15, matrixC21_15, matrixC20_15, matrixC19_15, matrixC18_15, matrixC17_15, matrixC16_15, matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_17 <= {matrixC31_14, matrixC30_14, matrixC29_14, matrixC28_14, matrixC27_14, matrixC26_14, matrixC25_14, matrixC24_14, matrixC23_14, matrixC22_14, matrixC21_14, matrixC20_14, matrixC19_14, matrixC18_14, matrixC17_14, matrixC16_14, matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_18 <= {matrixC31_13, matrixC30_13, matrixC29_13, matrixC28_13, matrixC27_13, matrixC26_13, matrixC25_13, matrixC24_13, matrixC23_13, matrixC22_13, matrixC21_13, matrixC20_13, matrixC19_13, matrixC18_13, matrixC17_13, matrixC16_13, matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_19 <= {matrixC31_12, matrixC30_12, matrixC29_12, matrixC28_12, matrixC27_12, matrixC26_12, matrixC25_12, matrixC24_12, matrixC23_12, matrixC22_12, matrixC21_12, matrixC20_12, matrixC19_12, matrixC18_12, matrixC17_12, matrixC16_12, matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_20 <= {matrixC31_11, matrixC30_11, matrixC29_11, matrixC28_11, matrixC27_11, matrixC26_11, matrixC25_11, matrixC24_11, matrixC23_11, matrixC22_11, matrixC21_11, matrixC20_11, matrixC19_11, matrixC18_11, matrixC17_11, matrixC16_11, matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_21 <= {matrixC31_10, matrixC30_10, matrixC29_10, matrixC28_10, matrixC27_10, matrixC26_10, matrixC25_10, matrixC24_10, matrixC23_10, matrixC22_10, matrixC21_10, matrixC20_10, matrixC19_10, matrixC18_10, matrixC17_10, matrixC16_10, matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_22 <= {matrixC31_9, matrixC30_9, matrixC29_9, matrixC28_9, matrixC27_9, matrixC26_9, matrixC25_9, matrixC24_9, matrixC23_9, matrixC22_9, matrixC21_9, matrixC20_9, matrixC19_9, matrixC18_9, matrixC17_9, matrixC16_9, matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_23 <= {matrixC31_8, matrixC30_8, matrixC29_8, matrixC28_8, matrixC27_8, matrixC26_8, matrixC25_8, matrixC24_8, matrixC23_8, matrixC22_8, matrixC21_8, matrixC20_8, matrixC19_8, matrixC18_8, matrixC17_8, matrixC16_8, matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_24 <= {matrixC31_7, matrixC30_7, matrixC29_7, matrixC28_7, matrixC27_7, matrixC26_7, matrixC25_7, matrixC24_7, matrixC23_7, matrixC22_7, matrixC21_7, matrixC20_7, matrixC19_7, matrixC18_7, matrixC17_7, matrixC16_7, matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_25 <= {matrixC31_6, matrixC30_6, matrixC29_6, matrixC28_6, matrixC27_6, matrixC26_6, matrixC25_6, matrixC24_6, matrixC23_6, matrixC22_6, matrixC21_6, matrixC20_6, matrixC19_6, matrixC18_6, matrixC17_6, matrixC16_6, matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_26 <= {matrixC31_5, matrixC30_5, matrixC29_5, matrixC28_5, matrixC27_5, matrixC26_5, matrixC25_5, matrixC24_5, matrixC23_5, matrixC22_5, matrixC21_5, matrixC20_5, matrixC19_5, matrixC18_5, matrixC17_5, matrixC16_5, matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_27 <= {matrixC31_4, matrixC30_4, matrixC29_4, matrixC28_4, matrixC27_4, matrixC26_4, matrixC25_4, matrixC24_4, matrixC23_4, matrixC22_4, matrixC21_4, matrixC20_4, matrixC19_4, matrixC18_4, matrixC17_4, matrixC16_4, matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_28 <= {matrixC31_3, matrixC30_3, matrixC29_3, matrixC28_3, matrixC27_3, matrixC26_3, matrixC25_3, matrixC24_3, matrixC23_3, matrixC22_3, matrixC21_3, matrixC20_3, matrixC19_3, matrixC18_3, matrixC17_3, matrixC16_3, matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_29 <= {matrixC31_2, matrixC30_2, matrixC29_2, matrixC28_2, matrixC27_2, matrixC26_2, matrixC25_2, matrixC24_2, matrixC23_2, matrixC22_2, matrixC21_2, matrixC20_2, matrixC19_2, matrixC18_2, matrixC17_2, matrixC16_2, matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_30 <= {matrixC31_1, matrixC30_1, matrixC29_1, matrixC28_1, matrixC27_1, matrixC26_1, matrixC25_1, matrixC24_1, matrixC23_1, matrixC22_1, matrixC21_1, matrixC20_1, matrixC19_1, matrixC18_1, matrixC17_1, matrixC16_1, matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_31 <= {matrixC31_0, matrixC30_0, matrixC29_0, matrixC28_0, matrixC27_0, matrixC26_0, matrixC25_0, matrixC24_0, matrixC23_0, matrixC22_0, matrixC21_0, matrixC20_0, matrixC19_0, matrixC18_0, matrixC17_0, matrixC16_0, matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, +a16_data_delayed_16, +b16_data_delayed_16, +a17_data_delayed_17, +b17_data_delayed_17, +a18_data_delayed_18, +b18_data_delayed_18, +a19_data_delayed_19, +b19_data_delayed_19, +a20_data_delayed_20, +b20_data_delayed_20, +a21_data_delayed_21, +b21_data_delayed_21, +a22_data_delayed_22, +b22_data_delayed_22, +a23_data_delayed_23, +b23_data_delayed_23, +a24_data_delayed_24, +b24_data_delayed_24, +a25_data_delayed_25, +b25_data_delayed_25, +a26_data_delayed_26, +b26_data_delayed_26, +a27_data_delayed_27, +b27_data_delayed_27, +a28_data_delayed_28, +b28_data_delayed_28, +a29_data_delayed_29, +b29_data_delayed_29, +a30_data_delayed_30, +b30_data_delayed_30, +a31_data_delayed_31, +b31_data_delayed_31, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; +output [`DWIDTH-1:0] a16_data_delayed_16; +output [`DWIDTH-1:0] b16_data_delayed_16; +output [`DWIDTH-1:0] a17_data_delayed_17; +output [`DWIDTH-1:0] b17_data_delayed_17; +output [`DWIDTH-1:0] a18_data_delayed_18; +output [`DWIDTH-1:0] b18_data_delayed_18; +output [`DWIDTH-1:0] a19_data_delayed_19; +output [`DWIDTH-1:0] b19_data_delayed_19; +output [`DWIDTH-1:0] a20_data_delayed_20; +output [`DWIDTH-1:0] b20_data_delayed_20; +output [`DWIDTH-1:0] a21_data_delayed_21; +output [`DWIDTH-1:0] b21_data_delayed_21; +output [`DWIDTH-1:0] a22_data_delayed_22; +output [`DWIDTH-1:0] b22_data_delayed_22; +output [`DWIDTH-1:0] a23_data_delayed_23; +output [`DWIDTH-1:0] b23_data_delayed_23; +output [`DWIDTH-1:0] a24_data_delayed_24; +output [`DWIDTH-1:0] b24_data_delayed_24; +output [`DWIDTH-1:0] a25_data_delayed_25; +output [`DWIDTH-1:0] b25_data_delayed_25; +output [`DWIDTH-1:0] a26_data_delayed_26; +output [`DWIDTH-1:0] b26_data_delayed_26; +output [`DWIDTH-1:0] a27_data_delayed_27; +output [`DWIDTH-1:0] b27_data_delayed_27; +output [`DWIDTH-1:0] a28_data_delayed_28; +output [`DWIDTH-1:0] b28_data_delayed_28; +output [`DWIDTH-1:0] a29_data_delayed_29; +output [`DWIDTH-1:0] b29_data_delayed_29; +output [`DWIDTH-1:0] a30_data_delayed_30; +output [`DWIDTH-1:0] b30_data_delayed_30; +output [`DWIDTH-1:0] a31_data_delayed_31; +output [`DWIDTH-1:0] b31_data_delayed_31; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16) || + (validity_mask_a_cols[16]==1'b0 && a_mem_access_counter==17) || + (validity_mask_a_cols[17]==1'b0 && a_mem_access_counter==18) || + (validity_mask_a_cols[18]==1'b0 && a_mem_access_counter==19) || + (validity_mask_a_cols[19]==1'b0 && a_mem_access_counter==20) || + (validity_mask_a_cols[20]==1'b0 && a_mem_access_counter==21) || + (validity_mask_a_cols[21]==1'b0 && a_mem_access_counter==22) || + (validity_mask_a_cols[22]==1'b0 && a_mem_access_counter==23) || + (validity_mask_a_cols[23]==1'b0 && a_mem_access_counter==24) || + (validity_mask_a_cols[24]==1'b0 && a_mem_access_counter==25) || + (validity_mask_a_cols[25]==1'b0 && a_mem_access_counter==26) || + (validity_mask_a_cols[26]==1'b0 && a_mem_access_counter==27) || + (validity_mask_a_cols[27]==1'b0 && a_mem_access_counter==28) || + (validity_mask_a_cols[28]==1'b0 && a_mem_access_counter==29) || + (validity_mask_a_cols[29]==1'b0 && a_mem_access_counter==30) || + (validity_mask_a_cols[30]==1'b0 && a_mem_access_counter==31) || + (validity_mask_a_cols[31]==1'b0 && a_mem_access_counter==32)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; +assign a16_data = a_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[16]}}; +assign a17_data = a_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[17]}}; +assign a18_data = a_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[18]}}; +assign a19_data = a_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[19]}}; +assign a20_data = a_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[20]}}; +assign a21_data = a_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[21]}}; +assign a22_data = a_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[22]}}; +assign a23_data = a_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[23]}}; +assign a24_data = a_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[24]}}; +assign a25_data = a_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[25]}}; +assign a26_data = a_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[26]}}; +assign a27_data = a_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[27]}}; +assign a28_data = a_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[28]}}; +assign a29_data = a_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[29]}}; +assign a30_data = a_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[30]}}; +assign a31_data = a_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[31]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_1; +reg [`DWIDTH-1:0] a16_data_delayed_2; +reg [`DWIDTH-1:0] a16_data_delayed_3; +reg [`DWIDTH-1:0] a16_data_delayed_4; +reg [`DWIDTH-1:0] a16_data_delayed_5; +reg [`DWIDTH-1:0] a16_data_delayed_6; +reg [`DWIDTH-1:0] a16_data_delayed_7; +reg [`DWIDTH-1:0] a16_data_delayed_8; +reg [`DWIDTH-1:0] a16_data_delayed_9; +reg [`DWIDTH-1:0] a16_data_delayed_10; +reg [`DWIDTH-1:0] a16_data_delayed_11; +reg [`DWIDTH-1:0] a16_data_delayed_12; +reg [`DWIDTH-1:0] a16_data_delayed_13; +reg [`DWIDTH-1:0] a16_data_delayed_14; +reg [`DWIDTH-1:0] a16_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_1; +reg [`DWIDTH-1:0] a17_data_delayed_2; +reg [`DWIDTH-1:0] a17_data_delayed_3; +reg [`DWIDTH-1:0] a17_data_delayed_4; +reg [`DWIDTH-1:0] a17_data_delayed_5; +reg [`DWIDTH-1:0] a17_data_delayed_6; +reg [`DWIDTH-1:0] a17_data_delayed_7; +reg [`DWIDTH-1:0] a17_data_delayed_8; +reg [`DWIDTH-1:0] a17_data_delayed_9; +reg [`DWIDTH-1:0] a17_data_delayed_10; +reg [`DWIDTH-1:0] a17_data_delayed_11; +reg [`DWIDTH-1:0] a17_data_delayed_12; +reg [`DWIDTH-1:0] a17_data_delayed_13; +reg [`DWIDTH-1:0] a17_data_delayed_14; +reg [`DWIDTH-1:0] a17_data_delayed_15; +reg [`DWIDTH-1:0] a17_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_1; +reg [`DWIDTH-1:0] a18_data_delayed_2; +reg [`DWIDTH-1:0] a18_data_delayed_3; +reg [`DWIDTH-1:0] a18_data_delayed_4; +reg [`DWIDTH-1:0] a18_data_delayed_5; +reg [`DWIDTH-1:0] a18_data_delayed_6; +reg [`DWIDTH-1:0] a18_data_delayed_7; +reg [`DWIDTH-1:0] a18_data_delayed_8; +reg [`DWIDTH-1:0] a18_data_delayed_9; +reg [`DWIDTH-1:0] a18_data_delayed_10; +reg [`DWIDTH-1:0] a18_data_delayed_11; +reg [`DWIDTH-1:0] a18_data_delayed_12; +reg [`DWIDTH-1:0] a18_data_delayed_13; +reg [`DWIDTH-1:0] a18_data_delayed_14; +reg [`DWIDTH-1:0] a18_data_delayed_15; +reg [`DWIDTH-1:0] a18_data_delayed_16; +reg [`DWIDTH-1:0] a18_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_1; +reg [`DWIDTH-1:0] a19_data_delayed_2; +reg [`DWIDTH-1:0] a19_data_delayed_3; +reg [`DWIDTH-1:0] a19_data_delayed_4; +reg [`DWIDTH-1:0] a19_data_delayed_5; +reg [`DWIDTH-1:0] a19_data_delayed_6; +reg [`DWIDTH-1:0] a19_data_delayed_7; +reg [`DWIDTH-1:0] a19_data_delayed_8; +reg [`DWIDTH-1:0] a19_data_delayed_9; +reg [`DWIDTH-1:0] a19_data_delayed_10; +reg [`DWIDTH-1:0] a19_data_delayed_11; +reg [`DWIDTH-1:0] a19_data_delayed_12; +reg [`DWIDTH-1:0] a19_data_delayed_13; +reg [`DWIDTH-1:0] a19_data_delayed_14; +reg [`DWIDTH-1:0] a19_data_delayed_15; +reg [`DWIDTH-1:0] a19_data_delayed_16; +reg [`DWIDTH-1:0] a19_data_delayed_17; +reg [`DWIDTH-1:0] a19_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_1; +reg [`DWIDTH-1:0] a20_data_delayed_2; +reg [`DWIDTH-1:0] a20_data_delayed_3; +reg [`DWIDTH-1:0] a20_data_delayed_4; +reg [`DWIDTH-1:0] a20_data_delayed_5; +reg [`DWIDTH-1:0] a20_data_delayed_6; +reg [`DWIDTH-1:0] a20_data_delayed_7; +reg [`DWIDTH-1:0] a20_data_delayed_8; +reg [`DWIDTH-1:0] a20_data_delayed_9; +reg [`DWIDTH-1:0] a20_data_delayed_10; +reg [`DWIDTH-1:0] a20_data_delayed_11; +reg [`DWIDTH-1:0] a20_data_delayed_12; +reg [`DWIDTH-1:0] a20_data_delayed_13; +reg [`DWIDTH-1:0] a20_data_delayed_14; +reg [`DWIDTH-1:0] a20_data_delayed_15; +reg [`DWIDTH-1:0] a20_data_delayed_16; +reg [`DWIDTH-1:0] a20_data_delayed_17; +reg [`DWIDTH-1:0] a20_data_delayed_18; +reg [`DWIDTH-1:0] a20_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_1; +reg [`DWIDTH-1:0] a21_data_delayed_2; +reg [`DWIDTH-1:0] a21_data_delayed_3; +reg [`DWIDTH-1:0] a21_data_delayed_4; +reg [`DWIDTH-1:0] a21_data_delayed_5; +reg [`DWIDTH-1:0] a21_data_delayed_6; +reg [`DWIDTH-1:0] a21_data_delayed_7; +reg [`DWIDTH-1:0] a21_data_delayed_8; +reg [`DWIDTH-1:0] a21_data_delayed_9; +reg [`DWIDTH-1:0] a21_data_delayed_10; +reg [`DWIDTH-1:0] a21_data_delayed_11; +reg [`DWIDTH-1:0] a21_data_delayed_12; +reg [`DWIDTH-1:0] a21_data_delayed_13; +reg [`DWIDTH-1:0] a21_data_delayed_14; +reg [`DWIDTH-1:0] a21_data_delayed_15; +reg [`DWIDTH-1:0] a21_data_delayed_16; +reg [`DWIDTH-1:0] a21_data_delayed_17; +reg [`DWIDTH-1:0] a21_data_delayed_18; +reg [`DWIDTH-1:0] a21_data_delayed_19; +reg [`DWIDTH-1:0] a21_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_1; +reg [`DWIDTH-1:0] a22_data_delayed_2; +reg [`DWIDTH-1:0] a22_data_delayed_3; +reg [`DWIDTH-1:0] a22_data_delayed_4; +reg [`DWIDTH-1:0] a22_data_delayed_5; +reg [`DWIDTH-1:0] a22_data_delayed_6; +reg [`DWIDTH-1:0] a22_data_delayed_7; +reg [`DWIDTH-1:0] a22_data_delayed_8; +reg [`DWIDTH-1:0] a22_data_delayed_9; +reg [`DWIDTH-1:0] a22_data_delayed_10; +reg [`DWIDTH-1:0] a22_data_delayed_11; +reg [`DWIDTH-1:0] a22_data_delayed_12; +reg [`DWIDTH-1:0] a22_data_delayed_13; +reg [`DWIDTH-1:0] a22_data_delayed_14; +reg [`DWIDTH-1:0] a22_data_delayed_15; +reg [`DWIDTH-1:0] a22_data_delayed_16; +reg [`DWIDTH-1:0] a22_data_delayed_17; +reg [`DWIDTH-1:0] a22_data_delayed_18; +reg [`DWIDTH-1:0] a22_data_delayed_19; +reg [`DWIDTH-1:0] a22_data_delayed_20; +reg [`DWIDTH-1:0] a22_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_1; +reg [`DWIDTH-1:0] a23_data_delayed_2; +reg [`DWIDTH-1:0] a23_data_delayed_3; +reg [`DWIDTH-1:0] a23_data_delayed_4; +reg [`DWIDTH-1:0] a23_data_delayed_5; +reg [`DWIDTH-1:0] a23_data_delayed_6; +reg [`DWIDTH-1:0] a23_data_delayed_7; +reg [`DWIDTH-1:0] a23_data_delayed_8; +reg [`DWIDTH-1:0] a23_data_delayed_9; +reg [`DWIDTH-1:0] a23_data_delayed_10; +reg [`DWIDTH-1:0] a23_data_delayed_11; +reg [`DWIDTH-1:0] a23_data_delayed_12; +reg [`DWIDTH-1:0] a23_data_delayed_13; +reg [`DWIDTH-1:0] a23_data_delayed_14; +reg [`DWIDTH-1:0] a23_data_delayed_15; +reg [`DWIDTH-1:0] a23_data_delayed_16; +reg [`DWIDTH-1:0] a23_data_delayed_17; +reg [`DWIDTH-1:0] a23_data_delayed_18; +reg [`DWIDTH-1:0] a23_data_delayed_19; +reg [`DWIDTH-1:0] a23_data_delayed_20; +reg [`DWIDTH-1:0] a23_data_delayed_21; +reg [`DWIDTH-1:0] a23_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_1; +reg [`DWIDTH-1:0] a24_data_delayed_2; +reg [`DWIDTH-1:0] a24_data_delayed_3; +reg [`DWIDTH-1:0] a24_data_delayed_4; +reg [`DWIDTH-1:0] a24_data_delayed_5; +reg [`DWIDTH-1:0] a24_data_delayed_6; +reg [`DWIDTH-1:0] a24_data_delayed_7; +reg [`DWIDTH-1:0] a24_data_delayed_8; +reg [`DWIDTH-1:0] a24_data_delayed_9; +reg [`DWIDTH-1:0] a24_data_delayed_10; +reg [`DWIDTH-1:0] a24_data_delayed_11; +reg [`DWIDTH-1:0] a24_data_delayed_12; +reg [`DWIDTH-1:0] a24_data_delayed_13; +reg [`DWIDTH-1:0] a24_data_delayed_14; +reg [`DWIDTH-1:0] a24_data_delayed_15; +reg [`DWIDTH-1:0] a24_data_delayed_16; +reg [`DWIDTH-1:0] a24_data_delayed_17; +reg [`DWIDTH-1:0] a24_data_delayed_18; +reg [`DWIDTH-1:0] a24_data_delayed_19; +reg [`DWIDTH-1:0] a24_data_delayed_20; +reg [`DWIDTH-1:0] a24_data_delayed_21; +reg [`DWIDTH-1:0] a24_data_delayed_22; +reg [`DWIDTH-1:0] a24_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_1; +reg [`DWIDTH-1:0] a25_data_delayed_2; +reg [`DWIDTH-1:0] a25_data_delayed_3; +reg [`DWIDTH-1:0] a25_data_delayed_4; +reg [`DWIDTH-1:0] a25_data_delayed_5; +reg [`DWIDTH-1:0] a25_data_delayed_6; +reg [`DWIDTH-1:0] a25_data_delayed_7; +reg [`DWIDTH-1:0] a25_data_delayed_8; +reg [`DWIDTH-1:0] a25_data_delayed_9; +reg [`DWIDTH-1:0] a25_data_delayed_10; +reg [`DWIDTH-1:0] a25_data_delayed_11; +reg [`DWIDTH-1:0] a25_data_delayed_12; +reg [`DWIDTH-1:0] a25_data_delayed_13; +reg [`DWIDTH-1:0] a25_data_delayed_14; +reg [`DWIDTH-1:0] a25_data_delayed_15; +reg [`DWIDTH-1:0] a25_data_delayed_16; +reg [`DWIDTH-1:0] a25_data_delayed_17; +reg [`DWIDTH-1:0] a25_data_delayed_18; +reg [`DWIDTH-1:0] a25_data_delayed_19; +reg [`DWIDTH-1:0] a25_data_delayed_20; +reg [`DWIDTH-1:0] a25_data_delayed_21; +reg [`DWIDTH-1:0] a25_data_delayed_22; +reg [`DWIDTH-1:0] a25_data_delayed_23; +reg [`DWIDTH-1:0] a25_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_1; +reg [`DWIDTH-1:0] a26_data_delayed_2; +reg [`DWIDTH-1:0] a26_data_delayed_3; +reg [`DWIDTH-1:0] a26_data_delayed_4; +reg [`DWIDTH-1:0] a26_data_delayed_5; +reg [`DWIDTH-1:0] a26_data_delayed_6; +reg [`DWIDTH-1:0] a26_data_delayed_7; +reg [`DWIDTH-1:0] a26_data_delayed_8; +reg [`DWIDTH-1:0] a26_data_delayed_9; +reg [`DWIDTH-1:0] a26_data_delayed_10; +reg [`DWIDTH-1:0] a26_data_delayed_11; +reg [`DWIDTH-1:0] a26_data_delayed_12; +reg [`DWIDTH-1:0] a26_data_delayed_13; +reg [`DWIDTH-1:0] a26_data_delayed_14; +reg [`DWIDTH-1:0] a26_data_delayed_15; +reg [`DWIDTH-1:0] a26_data_delayed_16; +reg [`DWIDTH-1:0] a26_data_delayed_17; +reg [`DWIDTH-1:0] a26_data_delayed_18; +reg [`DWIDTH-1:0] a26_data_delayed_19; +reg [`DWIDTH-1:0] a26_data_delayed_20; +reg [`DWIDTH-1:0] a26_data_delayed_21; +reg [`DWIDTH-1:0] a26_data_delayed_22; +reg [`DWIDTH-1:0] a26_data_delayed_23; +reg [`DWIDTH-1:0] a26_data_delayed_24; +reg [`DWIDTH-1:0] a26_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_1; +reg [`DWIDTH-1:0] a27_data_delayed_2; +reg [`DWIDTH-1:0] a27_data_delayed_3; +reg [`DWIDTH-1:0] a27_data_delayed_4; +reg [`DWIDTH-1:0] a27_data_delayed_5; +reg [`DWIDTH-1:0] a27_data_delayed_6; +reg [`DWIDTH-1:0] a27_data_delayed_7; +reg [`DWIDTH-1:0] a27_data_delayed_8; +reg [`DWIDTH-1:0] a27_data_delayed_9; +reg [`DWIDTH-1:0] a27_data_delayed_10; +reg [`DWIDTH-1:0] a27_data_delayed_11; +reg [`DWIDTH-1:0] a27_data_delayed_12; +reg [`DWIDTH-1:0] a27_data_delayed_13; +reg [`DWIDTH-1:0] a27_data_delayed_14; +reg [`DWIDTH-1:0] a27_data_delayed_15; +reg [`DWIDTH-1:0] a27_data_delayed_16; +reg [`DWIDTH-1:0] a27_data_delayed_17; +reg [`DWIDTH-1:0] a27_data_delayed_18; +reg [`DWIDTH-1:0] a27_data_delayed_19; +reg [`DWIDTH-1:0] a27_data_delayed_20; +reg [`DWIDTH-1:0] a27_data_delayed_21; +reg [`DWIDTH-1:0] a27_data_delayed_22; +reg [`DWIDTH-1:0] a27_data_delayed_23; +reg [`DWIDTH-1:0] a27_data_delayed_24; +reg [`DWIDTH-1:0] a27_data_delayed_25; +reg [`DWIDTH-1:0] a27_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_1; +reg [`DWIDTH-1:0] a28_data_delayed_2; +reg [`DWIDTH-1:0] a28_data_delayed_3; +reg [`DWIDTH-1:0] a28_data_delayed_4; +reg [`DWIDTH-1:0] a28_data_delayed_5; +reg [`DWIDTH-1:0] a28_data_delayed_6; +reg [`DWIDTH-1:0] a28_data_delayed_7; +reg [`DWIDTH-1:0] a28_data_delayed_8; +reg [`DWIDTH-1:0] a28_data_delayed_9; +reg [`DWIDTH-1:0] a28_data_delayed_10; +reg [`DWIDTH-1:0] a28_data_delayed_11; +reg [`DWIDTH-1:0] a28_data_delayed_12; +reg [`DWIDTH-1:0] a28_data_delayed_13; +reg [`DWIDTH-1:0] a28_data_delayed_14; +reg [`DWIDTH-1:0] a28_data_delayed_15; +reg [`DWIDTH-1:0] a28_data_delayed_16; +reg [`DWIDTH-1:0] a28_data_delayed_17; +reg [`DWIDTH-1:0] a28_data_delayed_18; +reg [`DWIDTH-1:0] a28_data_delayed_19; +reg [`DWIDTH-1:0] a28_data_delayed_20; +reg [`DWIDTH-1:0] a28_data_delayed_21; +reg [`DWIDTH-1:0] a28_data_delayed_22; +reg [`DWIDTH-1:0] a28_data_delayed_23; +reg [`DWIDTH-1:0] a28_data_delayed_24; +reg [`DWIDTH-1:0] a28_data_delayed_25; +reg [`DWIDTH-1:0] a28_data_delayed_26; +reg [`DWIDTH-1:0] a28_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_1; +reg [`DWIDTH-1:0] a29_data_delayed_2; +reg [`DWIDTH-1:0] a29_data_delayed_3; +reg [`DWIDTH-1:0] a29_data_delayed_4; +reg [`DWIDTH-1:0] a29_data_delayed_5; +reg [`DWIDTH-1:0] a29_data_delayed_6; +reg [`DWIDTH-1:0] a29_data_delayed_7; +reg [`DWIDTH-1:0] a29_data_delayed_8; +reg [`DWIDTH-1:0] a29_data_delayed_9; +reg [`DWIDTH-1:0] a29_data_delayed_10; +reg [`DWIDTH-1:0] a29_data_delayed_11; +reg [`DWIDTH-1:0] a29_data_delayed_12; +reg [`DWIDTH-1:0] a29_data_delayed_13; +reg [`DWIDTH-1:0] a29_data_delayed_14; +reg [`DWIDTH-1:0] a29_data_delayed_15; +reg [`DWIDTH-1:0] a29_data_delayed_16; +reg [`DWIDTH-1:0] a29_data_delayed_17; +reg [`DWIDTH-1:0] a29_data_delayed_18; +reg [`DWIDTH-1:0] a29_data_delayed_19; +reg [`DWIDTH-1:0] a29_data_delayed_20; +reg [`DWIDTH-1:0] a29_data_delayed_21; +reg [`DWIDTH-1:0] a29_data_delayed_22; +reg [`DWIDTH-1:0] a29_data_delayed_23; +reg [`DWIDTH-1:0] a29_data_delayed_24; +reg [`DWIDTH-1:0] a29_data_delayed_25; +reg [`DWIDTH-1:0] a29_data_delayed_26; +reg [`DWIDTH-1:0] a29_data_delayed_27; +reg [`DWIDTH-1:0] a29_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_1; +reg [`DWIDTH-1:0] a30_data_delayed_2; +reg [`DWIDTH-1:0] a30_data_delayed_3; +reg [`DWIDTH-1:0] a30_data_delayed_4; +reg [`DWIDTH-1:0] a30_data_delayed_5; +reg [`DWIDTH-1:0] a30_data_delayed_6; +reg [`DWIDTH-1:0] a30_data_delayed_7; +reg [`DWIDTH-1:0] a30_data_delayed_8; +reg [`DWIDTH-1:0] a30_data_delayed_9; +reg [`DWIDTH-1:0] a30_data_delayed_10; +reg [`DWIDTH-1:0] a30_data_delayed_11; +reg [`DWIDTH-1:0] a30_data_delayed_12; +reg [`DWIDTH-1:0] a30_data_delayed_13; +reg [`DWIDTH-1:0] a30_data_delayed_14; +reg [`DWIDTH-1:0] a30_data_delayed_15; +reg [`DWIDTH-1:0] a30_data_delayed_16; +reg [`DWIDTH-1:0] a30_data_delayed_17; +reg [`DWIDTH-1:0] a30_data_delayed_18; +reg [`DWIDTH-1:0] a30_data_delayed_19; +reg [`DWIDTH-1:0] a30_data_delayed_20; +reg [`DWIDTH-1:0] a30_data_delayed_21; +reg [`DWIDTH-1:0] a30_data_delayed_22; +reg [`DWIDTH-1:0] a30_data_delayed_23; +reg [`DWIDTH-1:0] a30_data_delayed_24; +reg [`DWIDTH-1:0] a30_data_delayed_25; +reg [`DWIDTH-1:0] a30_data_delayed_26; +reg [`DWIDTH-1:0] a30_data_delayed_27; +reg [`DWIDTH-1:0] a30_data_delayed_28; +reg [`DWIDTH-1:0] a30_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_1; +reg [`DWIDTH-1:0] a31_data_delayed_2; +reg [`DWIDTH-1:0] a31_data_delayed_3; +reg [`DWIDTH-1:0] a31_data_delayed_4; +reg [`DWIDTH-1:0] a31_data_delayed_5; +reg [`DWIDTH-1:0] a31_data_delayed_6; +reg [`DWIDTH-1:0] a31_data_delayed_7; +reg [`DWIDTH-1:0] a31_data_delayed_8; +reg [`DWIDTH-1:0] a31_data_delayed_9; +reg [`DWIDTH-1:0] a31_data_delayed_10; +reg [`DWIDTH-1:0] a31_data_delayed_11; +reg [`DWIDTH-1:0] a31_data_delayed_12; +reg [`DWIDTH-1:0] a31_data_delayed_13; +reg [`DWIDTH-1:0] a31_data_delayed_14; +reg [`DWIDTH-1:0] a31_data_delayed_15; +reg [`DWIDTH-1:0] a31_data_delayed_16; +reg [`DWIDTH-1:0] a31_data_delayed_17; +reg [`DWIDTH-1:0] a31_data_delayed_18; +reg [`DWIDTH-1:0] a31_data_delayed_19; +reg [`DWIDTH-1:0] a31_data_delayed_20; +reg [`DWIDTH-1:0] a31_data_delayed_21; +reg [`DWIDTH-1:0] a31_data_delayed_22; +reg [`DWIDTH-1:0] a31_data_delayed_23; +reg [`DWIDTH-1:0] a31_data_delayed_24; +reg [`DWIDTH-1:0] a31_data_delayed_25; +reg [`DWIDTH-1:0] a31_data_delayed_26; +reg [`DWIDTH-1:0] a31_data_delayed_27; +reg [`DWIDTH-1:0] a31_data_delayed_28; +reg [`DWIDTH-1:0] a31_data_delayed_29; +reg [`DWIDTH-1:0] a31_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + a16_data_delayed_1 <= 0; + a16_data_delayed_2 <= 0; + a16_data_delayed_3 <= 0; + a16_data_delayed_4 <= 0; + a16_data_delayed_5 <= 0; + a16_data_delayed_6 <= 0; + a16_data_delayed_7 <= 0; + a16_data_delayed_8 <= 0; + a16_data_delayed_9 <= 0; + a16_data_delayed_10 <= 0; + a16_data_delayed_11 <= 0; + a16_data_delayed_12 <= 0; + a16_data_delayed_13 <= 0; + a16_data_delayed_14 <= 0; + a16_data_delayed_15 <= 0; + a16_data_delayed_16 <= 0; + a17_data_delayed_1 <= 0; + a17_data_delayed_2 <= 0; + a17_data_delayed_3 <= 0; + a17_data_delayed_4 <= 0; + a17_data_delayed_5 <= 0; + a17_data_delayed_6 <= 0; + a17_data_delayed_7 <= 0; + a17_data_delayed_8 <= 0; + a17_data_delayed_9 <= 0; + a17_data_delayed_10 <= 0; + a17_data_delayed_11 <= 0; + a17_data_delayed_12 <= 0; + a17_data_delayed_13 <= 0; + a17_data_delayed_14 <= 0; + a17_data_delayed_15 <= 0; + a17_data_delayed_16 <= 0; + a17_data_delayed_17 <= 0; + a18_data_delayed_1 <= 0; + a18_data_delayed_2 <= 0; + a18_data_delayed_3 <= 0; + a18_data_delayed_4 <= 0; + a18_data_delayed_5 <= 0; + a18_data_delayed_6 <= 0; + a18_data_delayed_7 <= 0; + a18_data_delayed_8 <= 0; + a18_data_delayed_9 <= 0; + a18_data_delayed_10 <= 0; + a18_data_delayed_11 <= 0; + a18_data_delayed_12 <= 0; + a18_data_delayed_13 <= 0; + a18_data_delayed_14 <= 0; + a18_data_delayed_15 <= 0; + a18_data_delayed_16 <= 0; + a18_data_delayed_17 <= 0; + a18_data_delayed_18 <= 0; + a19_data_delayed_1 <= 0; + a19_data_delayed_2 <= 0; + a19_data_delayed_3 <= 0; + a19_data_delayed_4 <= 0; + a19_data_delayed_5 <= 0; + a19_data_delayed_6 <= 0; + a19_data_delayed_7 <= 0; + a19_data_delayed_8 <= 0; + a19_data_delayed_9 <= 0; + a19_data_delayed_10 <= 0; + a19_data_delayed_11 <= 0; + a19_data_delayed_12 <= 0; + a19_data_delayed_13 <= 0; + a19_data_delayed_14 <= 0; + a19_data_delayed_15 <= 0; + a19_data_delayed_16 <= 0; + a19_data_delayed_17 <= 0; + a19_data_delayed_18 <= 0; + a19_data_delayed_19 <= 0; + a20_data_delayed_1 <= 0; + a20_data_delayed_2 <= 0; + a20_data_delayed_3 <= 0; + a20_data_delayed_4 <= 0; + a20_data_delayed_5 <= 0; + a20_data_delayed_6 <= 0; + a20_data_delayed_7 <= 0; + a20_data_delayed_8 <= 0; + a20_data_delayed_9 <= 0; + a20_data_delayed_10 <= 0; + a20_data_delayed_11 <= 0; + a20_data_delayed_12 <= 0; + a20_data_delayed_13 <= 0; + a20_data_delayed_14 <= 0; + a20_data_delayed_15 <= 0; + a20_data_delayed_16 <= 0; + a20_data_delayed_17 <= 0; + a20_data_delayed_18 <= 0; + a20_data_delayed_19 <= 0; + a20_data_delayed_20 <= 0; + a21_data_delayed_1 <= 0; + a21_data_delayed_2 <= 0; + a21_data_delayed_3 <= 0; + a21_data_delayed_4 <= 0; + a21_data_delayed_5 <= 0; + a21_data_delayed_6 <= 0; + a21_data_delayed_7 <= 0; + a21_data_delayed_8 <= 0; + a21_data_delayed_9 <= 0; + a21_data_delayed_10 <= 0; + a21_data_delayed_11 <= 0; + a21_data_delayed_12 <= 0; + a21_data_delayed_13 <= 0; + a21_data_delayed_14 <= 0; + a21_data_delayed_15 <= 0; + a21_data_delayed_16 <= 0; + a21_data_delayed_17 <= 0; + a21_data_delayed_18 <= 0; + a21_data_delayed_19 <= 0; + a21_data_delayed_20 <= 0; + a21_data_delayed_21 <= 0; + a22_data_delayed_1 <= 0; + a22_data_delayed_2 <= 0; + a22_data_delayed_3 <= 0; + a22_data_delayed_4 <= 0; + a22_data_delayed_5 <= 0; + a22_data_delayed_6 <= 0; + a22_data_delayed_7 <= 0; + a22_data_delayed_8 <= 0; + a22_data_delayed_9 <= 0; + a22_data_delayed_10 <= 0; + a22_data_delayed_11 <= 0; + a22_data_delayed_12 <= 0; + a22_data_delayed_13 <= 0; + a22_data_delayed_14 <= 0; + a22_data_delayed_15 <= 0; + a22_data_delayed_16 <= 0; + a22_data_delayed_17 <= 0; + a22_data_delayed_18 <= 0; + a22_data_delayed_19 <= 0; + a22_data_delayed_20 <= 0; + a22_data_delayed_21 <= 0; + a22_data_delayed_22 <= 0; + a23_data_delayed_1 <= 0; + a23_data_delayed_2 <= 0; + a23_data_delayed_3 <= 0; + a23_data_delayed_4 <= 0; + a23_data_delayed_5 <= 0; + a23_data_delayed_6 <= 0; + a23_data_delayed_7 <= 0; + a23_data_delayed_8 <= 0; + a23_data_delayed_9 <= 0; + a23_data_delayed_10 <= 0; + a23_data_delayed_11 <= 0; + a23_data_delayed_12 <= 0; + a23_data_delayed_13 <= 0; + a23_data_delayed_14 <= 0; + a23_data_delayed_15 <= 0; + a23_data_delayed_16 <= 0; + a23_data_delayed_17 <= 0; + a23_data_delayed_18 <= 0; + a23_data_delayed_19 <= 0; + a23_data_delayed_20 <= 0; + a23_data_delayed_21 <= 0; + a23_data_delayed_22 <= 0; + a23_data_delayed_23 <= 0; + a24_data_delayed_1 <= 0; + a24_data_delayed_2 <= 0; + a24_data_delayed_3 <= 0; + a24_data_delayed_4 <= 0; + a24_data_delayed_5 <= 0; + a24_data_delayed_6 <= 0; + a24_data_delayed_7 <= 0; + a24_data_delayed_8 <= 0; + a24_data_delayed_9 <= 0; + a24_data_delayed_10 <= 0; + a24_data_delayed_11 <= 0; + a24_data_delayed_12 <= 0; + a24_data_delayed_13 <= 0; + a24_data_delayed_14 <= 0; + a24_data_delayed_15 <= 0; + a24_data_delayed_16 <= 0; + a24_data_delayed_17 <= 0; + a24_data_delayed_18 <= 0; + a24_data_delayed_19 <= 0; + a24_data_delayed_20 <= 0; + a24_data_delayed_21 <= 0; + a24_data_delayed_22 <= 0; + a24_data_delayed_23 <= 0; + a24_data_delayed_24 <= 0; + a25_data_delayed_1 <= 0; + a25_data_delayed_2 <= 0; + a25_data_delayed_3 <= 0; + a25_data_delayed_4 <= 0; + a25_data_delayed_5 <= 0; + a25_data_delayed_6 <= 0; + a25_data_delayed_7 <= 0; + a25_data_delayed_8 <= 0; + a25_data_delayed_9 <= 0; + a25_data_delayed_10 <= 0; + a25_data_delayed_11 <= 0; + a25_data_delayed_12 <= 0; + a25_data_delayed_13 <= 0; + a25_data_delayed_14 <= 0; + a25_data_delayed_15 <= 0; + a25_data_delayed_16 <= 0; + a25_data_delayed_17 <= 0; + a25_data_delayed_18 <= 0; + a25_data_delayed_19 <= 0; + a25_data_delayed_20 <= 0; + a25_data_delayed_21 <= 0; + a25_data_delayed_22 <= 0; + a25_data_delayed_23 <= 0; + a25_data_delayed_24 <= 0; + a25_data_delayed_25 <= 0; + a26_data_delayed_1 <= 0; + a26_data_delayed_2 <= 0; + a26_data_delayed_3 <= 0; + a26_data_delayed_4 <= 0; + a26_data_delayed_5 <= 0; + a26_data_delayed_6 <= 0; + a26_data_delayed_7 <= 0; + a26_data_delayed_8 <= 0; + a26_data_delayed_9 <= 0; + a26_data_delayed_10 <= 0; + a26_data_delayed_11 <= 0; + a26_data_delayed_12 <= 0; + a26_data_delayed_13 <= 0; + a26_data_delayed_14 <= 0; + a26_data_delayed_15 <= 0; + a26_data_delayed_16 <= 0; + a26_data_delayed_17 <= 0; + a26_data_delayed_18 <= 0; + a26_data_delayed_19 <= 0; + a26_data_delayed_20 <= 0; + a26_data_delayed_21 <= 0; + a26_data_delayed_22 <= 0; + a26_data_delayed_23 <= 0; + a26_data_delayed_24 <= 0; + a26_data_delayed_25 <= 0; + a26_data_delayed_26 <= 0; + a27_data_delayed_1 <= 0; + a27_data_delayed_2 <= 0; + a27_data_delayed_3 <= 0; + a27_data_delayed_4 <= 0; + a27_data_delayed_5 <= 0; + a27_data_delayed_6 <= 0; + a27_data_delayed_7 <= 0; + a27_data_delayed_8 <= 0; + a27_data_delayed_9 <= 0; + a27_data_delayed_10 <= 0; + a27_data_delayed_11 <= 0; + a27_data_delayed_12 <= 0; + a27_data_delayed_13 <= 0; + a27_data_delayed_14 <= 0; + a27_data_delayed_15 <= 0; + a27_data_delayed_16 <= 0; + a27_data_delayed_17 <= 0; + a27_data_delayed_18 <= 0; + a27_data_delayed_19 <= 0; + a27_data_delayed_20 <= 0; + a27_data_delayed_21 <= 0; + a27_data_delayed_22 <= 0; + a27_data_delayed_23 <= 0; + a27_data_delayed_24 <= 0; + a27_data_delayed_25 <= 0; + a27_data_delayed_26 <= 0; + a27_data_delayed_27 <= 0; + a28_data_delayed_1 <= 0; + a28_data_delayed_2 <= 0; + a28_data_delayed_3 <= 0; + a28_data_delayed_4 <= 0; + a28_data_delayed_5 <= 0; + a28_data_delayed_6 <= 0; + a28_data_delayed_7 <= 0; + a28_data_delayed_8 <= 0; + a28_data_delayed_9 <= 0; + a28_data_delayed_10 <= 0; + a28_data_delayed_11 <= 0; + a28_data_delayed_12 <= 0; + a28_data_delayed_13 <= 0; + a28_data_delayed_14 <= 0; + a28_data_delayed_15 <= 0; + a28_data_delayed_16 <= 0; + a28_data_delayed_17 <= 0; + a28_data_delayed_18 <= 0; + a28_data_delayed_19 <= 0; + a28_data_delayed_20 <= 0; + a28_data_delayed_21 <= 0; + a28_data_delayed_22 <= 0; + a28_data_delayed_23 <= 0; + a28_data_delayed_24 <= 0; + a28_data_delayed_25 <= 0; + a28_data_delayed_26 <= 0; + a28_data_delayed_27 <= 0; + a28_data_delayed_28 <= 0; + a29_data_delayed_1 <= 0; + a29_data_delayed_2 <= 0; + a29_data_delayed_3 <= 0; + a29_data_delayed_4 <= 0; + a29_data_delayed_5 <= 0; + a29_data_delayed_6 <= 0; + a29_data_delayed_7 <= 0; + a29_data_delayed_8 <= 0; + a29_data_delayed_9 <= 0; + a29_data_delayed_10 <= 0; + a29_data_delayed_11 <= 0; + a29_data_delayed_12 <= 0; + a29_data_delayed_13 <= 0; + a29_data_delayed_14 <= 0; + a29_data_delayed_15 <= 0; + a29_data_delayed_16 <= 0; + a29_data_delayed_17 <= 0; + a29_data_delayed_18 <= 0; + a29_data_delayed_19 <= 0; + a29_data_delayed_20 <= 0; + a29_data_delayed_21 <= 0; + a29_data_delayed_22 <= 0; + a29_data_delayed_23 <= 0; + a29_data_delayed_24 <= 0; + a29_data_delayed_25 <= 0; + a29_data_delayed_26 <= 0; + a29_data_delayed_27 <= 0; + a29_data_delayed_28 <= 0; + a29_data_delayed_29 <= 0; + a30_data_delayed_1 <= 0; + a30_data_delayed_2 <= 0; + a30_data_delayed_3 <= 0; + a30_data_delayed_4 <= 0; + a30_data_delayed_5 <= 0; + a30_data_delayed_6 <= 0; + a30_data_delayed_7 <= 0; + a30_data_delayed_8 <= 0; + a30_data_delayed_9 <= 0; + a30_data_delayed_10 <= 0; + a30_data_delayed_11 <= 0; + a30_data_delayed_12 <= 0; + a30_data_delayed_13 <= 0; + a30_data_delayed_14 <= 0; + a30_data_delayed_15 <= 0; + a30_data_delayed_16 <= 0; + a30_data_delayed_17 <= 0; + a30_data_delayed_18 <= 0; + a30_data_delayed_19 <= 0; + a30_data_delayed_20 <= 0; + a30_data_delayed_21 <= 0; + a30_data_delayed_22 <= 0; + a30_data_delayed_23 <= 0; + a30_data_delayed_24 <= 0; + a30_data_delayed_25 <= 0; + a30_data_delayed_26 <= 0; + a30_data_delayed_27 <= 0; + a30_data_delayed_28 <= 0; + a30_data_delayed_29 <= 0; + a30_data_delayed_30 <= 0; + a31_data_delayed_1 <= 0; + a31_data_delayed_2 <= 0; + a31_data_delayed_3 <= 0; + a31_data_delayed_4 <= 0; + a31_data_delayed_5 <= 0; + a31_data_delayed_6 <= 0; + a31_data_delayed_7 <= 0; + a31_data_delayed_8 <= 0; + a31_data_delayed_9 <= 0; + a31_data_delayed_10 <= 0; + a31_data_delayed_11 <= 0; + a31_data_delayed_12 <= 0; + a31_data_delayed_13 <= 0; + a31_data_delayed_14 <= 0; + a31_data_delayed_15 <= 0; + a31_data_delayed_16 <= 0; + a31_data_delayed_17 <= 0; + a31_data_delayed_18 <= 0; + a31_data_delayed_19 <= 0; + a31_data_delayed_20 <= 0; + a31_data_delayed_21 <= 0; + a31_data_delayed_22 <= 0; + a31_data_delayed_23 <= 0; + a31_data_delayed_24 <= 0; + a31_data_delayed_25 <= 0; + a31_data_delayed_26 <= 0; + a31_data_delayed_27 <= 0; + a31_data_delayed_28 <= 0; + a31_data_delayed_29 <= 0; + a31_data_delayed_30 <= 0; + a31_data_delayed_31 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a16_data_delayed_1 <= a16_data; + a17_data_delayed_1 <= a17_data; + a18_data_delayed_1 <= a18_data; + a19_data_delayed_1 <= a19_data; + a20_data_delayed_1 <= a20_data; + a21_data_delayed_1 <= a21_data; + a22_data_delayed_1 <= a22_data; + a23_data_delayed_1 <= a23_data; + a24_data_delayed_1 <= a24_data; + a25_data_delayed_1 <= a25_data; + a26_data_delayed_1 <= a26_data; + a27_data_delayed_1 <= a27_data; + a28_data_delayed_1 <= a28_data; + a29_data_delayed_1 <= a29_data; + a30_data_delayed_1 <= a30_data; + a31_data_delayed_1 <= a31_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + a16_data_delayed_2 <= a16_data_delayed_1; + a16_data_delayed_3 <= a16_data_delayed_2; + a16_data_delayed_4 <= a16_data_delayed_3; + a16_data_delayed_5 <= a16_data_delayed_4; + a16_data_delayed_6 <= a16_data_delayed_5; + a16_data_delayed_7 <= a16_data_delayed_6; + a16_data_delayed_8 <= a16_data_delayed_7; + a16_data_delayed_9 <= a16_data_delayed_8; + a16_data_delayed_10 <= a16_data_delayed_9; + a16_data_delayed_11 <= a16_data_delayed_10; + a16_data_delayed_12 <= a16_data_delayed_11; + a16_data_delayed_13 <= a16_data_delayed_12; + a16_data_delayed_14 <= a16_data_delayed_13; + a16_data_delayed_15 <= a16_data_delayed_14; + a16_data_delayed_16 <= a16_data_delayed_15; + a17_data_delayed_2 <= a17_data_delayed_1; + a17_data_delayed_3 <= a17_data_delayed_2; + a17_data_delayed_4 <= a17_data_delayed_3; + a17_data_delayed_5 <= a17_data_delayed_4; + a17_data_delayed_6 <= a17_data_delayed_5; + a17_data_delayed_7 <= a17_data_delayed_6; + a17_data_delayed_8 <= a17_data_delayed_7; + a17_data_delayed_9 <= a17_data_delayed_8; + a17_data_delayed_10 <= a17_data_delayed_9; + a17_data_delayed_11 <= a17_data_delayed_10; + a17_data_delayed_12 <= a17_data_delayed_11; + a17_data_delayed_13 <= a17_data_delayed_12; + a17_data_delayed_14 <= a17_data_delayed_13; + a17_data_delayed_15 <= a17_data_delayed_14; + a17_data_delayed_16 <= a17_data_delayed_15; + a17_data_delayed_17 <= a17_data_delayed_16; + a18_data_delayed_2 <= a18_data_delayed_1; + a18_data_delayed_3 <= a18_data_delayed_2; + a18_data_delayed_4 <= a18_data_delayed_3; + a18_data_delayed_5 <= a18_data_delayed_4; + a18_data_delayed_6 <= a18_data_delayed_5; + a18_data_delayed_7 <= a18_data_delayed_6; + a18_data_delayed_8 <= a18_data_delayed_7; + a18_data_delayed_9 <= a18_data_delayed_8; + a18_data_delayed_10 <= a18_data_delayed_9; + a18_data_delayed_11 <= a18_data_delayed_10; + a18_data_delayed_12 <= a18_data_delayed_11; + a18_data_delayed_13 <= a18_data_delayed_12; + a18_data_delayed_14 <= a18_data_delayed_13; + a18_data_delayed_15 <= a18_data_delayed_14; + a18_data_delayed_16 <= a18_data_delayed_15; + a18_data_delayed_17 <= a18_data_delayed_16; + a18_data_delayed_18 <= a18_data_delayed_17; + a19_data_delayed_2 <= a19_data_delayed_1; + a19_data_delayed_3 <= a19_data_delayed_2; + a19_data_delayed_4 <= a19_data_delayed_3; + a19_data_delayed_5 <= a19_data_delayed_4; + a19_data_delayed_6 <= a19_data_delayed_5; + a19_data_delayed_7 <= a19_data_delayed_6; + a19_data_delayed_8 <= a19_data_delayed_7; + a19_data_delayed_9 <= a19_data_delayed_8; + a19_data_delayed_10 <= a19_data_delayed_9; + a19_data_delayed_11 <= a19_data_delayed_10; + a19_data_delayed_12 <= a19_data_delayed_11; + a19_data_delayed_13 <= a19_data_delayed_12; + a19_data_delayed_14 <= a19_data_delayed_13; + a19_data_delayed_15 <= a19_data_delayed_14; + a19_data_delayed_16 <= a19_data_delayed_15; + a19_data_delayed_17 <= a19_data_delayed_16; + a19_data_delayed_18 <= a19_data_delayed_17; + a19_data_delayed_19 <= a19_data_delayed_18; + a20_data_delayed_2 <= a20_data_delayed_1; + a20_data_delayed_3 <= a20_data_delayed_2; + a20_data_delayed_4 <= a20_data_delayed_3; + a20_data_delayed_5 <= a20_data_delayed_4; + a20_data_delayed_6 <= a20_data_delayed_5; + a20_data_delayed_7 <= a20_data_delayed_6; + a20_data_delayed_8 <= a20_data_delayed_7; + a20_data_delayed_9 <= a20_data_delayed_8; + a20_data_delayed_10 <= a20_data_delayed_9; + a20_data_delayed_11 <= a20_data_delayed_10; + a20_data_delayed_12 <= a20_data_delayed_11; + a20_data_delayed_13 <= a20_data_delayed_12; + a20_data_delayed_14 <= a20_data_delayed_13; + a20_data_delayed_15 <= a20_data_delayed_14; + a20_data_delayed_16 <= a20_data_delayed_15; + a20_data_delayed_17 <= a20_data_delayed_16; + a20_data_delayed_18 <= a20_data_delayed_17; + a20_data_delayed_19 <= a20_data_delayed_18; + a20_data_delayed_20 <= a20_data_delayed_19; + a21_data_delayed_2 <= a21_data_delayed_1; + a21_data_delayed_3 <= a21_data_delayed_2; + a21_data_delayed_4 <= a21_data_delayed_3; + a21_data_delayed_5 <= a21_data_delayed_4; + a21_data_delayed_6 <= a21_data_delayed_5; + a21_data_delayed_7 <= a21_data_delayed_6; + a21_data_delayed_8 <= a21_data_delayed_7; + a21_data_delayed_9 <= a21_data_delayed_8; + a21_data_delayed_10 <= a21_data_delayed_9; + a21_data_delayed_11 <= a21_data_delayed_10; + a21_data_delayed_12 <= a21_data_delayed_11; + a21_data_delayed_13 <= a21_data_delayed_12; + a21_data_delayed_14 <= a21_data_delayed_13; + a21_data_delayed_15 <= a21_data_delayed_14; + a21_data_delayed_16 <= a21_data_delayed_15; + a21_data_delayed_17 <= a21_data_delayed_16; + a21_data_delayed_18 <= a21_data_delayed_17; + a21_data_delayed_19 <= a21_data_delayed_18; + a21_data_delayed_20 <= a21_data_delayed_19; + a21_data_delayed_21 <= a21_data_delayed_20; + a22_data_delayed_2 <= a22_data_delayed_1; + a22_data_delayed_3 <= a22_data_delayed_2; + a22_data_delayed_4 <= a22_data_delayed_3; + a22_data_delayed_5 <= a22_data_delayed_4; + a22_data_delayed_6 <= a22_data_delayed_5; + a22_data_delayed_7 <= a22_data_delayed_6; + a22_data_delayed_8 <= a22_data_delayed_7; + a22_data_delayed_9 <= a22_data_delayed_8; + a22_data_delayed_10 <= a22_data_delayed_9; + a22_data_delayed_11 <= a22_data_delayed_10; + a22_data_delayed_12 <= a22_data_delayed_11; + a22_data_delayed_13 <= a22_data_delayed_12; + a22_data_delayed_14 <= a22_data_delayed_13; + a22_data_delayed_15 <= a22_data_delayed_14; + a22_data_delayed_16 <= a22_data_delayed_15; + a22_data_delayed_17 <= a22_data_delayed_16; + a22_data_delayed_18 <= a22_data_delayed_17; + a22_data_delayed_19 <= a22_data_delayed_18; + a22_data_delayed_20 <= a22_data_delayed_19; + a22_data_delayed_21 <= a22_data_delayed_20; + a22_data_delayed_22 <= a22_data_delayed_21; + a23_data_delayed_2 <= a23_data_delayed_1; + a23_data_delayed_3 <= a23_data_delayed_2; + a23_data_delayed_4 <= a23_data_delayed_3; + a23_data_delayed_5 <= a23_data_delayed_4; + a23_data_delayed_6 <= a23_data_delayed_5; + a23_data_delayed_7 <= a23_data_delayed_6; + a23_data_delayed_8 <= a23_data_delayed_7; + a23_data_delayed_9 <= a23_data_delayed_8; + a23_data_delayed_10 <= a23_data_delayed_9; + a23_data_delayed_11 <= a23_data_delayed_10; + a23_data_delayed_12 <= a23_data_delayed_11; + a23_data_delayed_13 <= a23_data_delayed_12; + a23_data_delayed_14 <= a23_data_delayed_13; + a23_data_delayed_15 <= a23_data_delayed_14; + a23_data_delayed_16 <= a23_data_delayed_15; + a23_data_delayed_17 <= a23_data_delayed_16; + a23_data_delayed_18 <= a23_data_delayed_17; + a23_data_delayed_19 <= a23_data_delayed_18; + a23_data_delayed_20 <= a23_data_delayed_19; + a23_data_delayed_21 <= a23_data_delayed_20; + a23_data_delayed_22 <= a23_data_delayed_21; + a23_data_delayed_23 <= a23_data_delayed_22; + a24_data_delayed_2 <= a24_data_delayed_1; + a24_data_delayed_3 <= a24_data_delayed_2; + a24_data_delayed_4 <= a24_data_delayed_3; + a24_data_delayed_5 <= a24_data_delayed_4; + a24_data_delayed_6 <= a24_data_delayed_5; + a24_data_delayed_7 <= a24_data_delayed_6; + a24_data_delayed_8 <= a24_data_delayed_7; + a24_data_delayed_9 <= a24_data_delayed_8; + a24_data_delayed_10 <= a24_data_delayed_9; + a24_data_delayed_11 <= a24_data_delayed_10; + a24_data_delayed_12 <= a24_data_delayed_11; + a24_data_delayed_13 <= a24_data_delayed_12; + a24_data_delayed_14 <= a24_data_delayed_13; + a24_data_delayed_15 <= a24_data_delayed_14; + a24_data_delayed_16 <= a24_data_delayed_15; + a24_data_delayed_17 <= a24_data_delayed_16; + a24_data_delayed_18 <= a24_data_delayed_17; + a24_data_delayed_19 <= a24_data_delayed_18; + a24_data_delayed_20 <= a24_data_delayed_19; + a24_data_delayed_21 <= a24_data_delayed_20; + a24_data_delayed_22 <= a24_data_delayed_21; + a24_data_delayed_23 <= a24_data_delayed_22; + a24_data_delayed_24 <= a24_data_delayed_23; + a25_data_delayed_2 <= a25_data_delayed_1; + a25_data_delayed_3 <= a25_data_delayed_2; + a25_data_delayed_4 <= a25_data_delayed_3; + a25_data_delayed_5 <= a25_data_delayed_4; + a25_data_delayed_6 <= a25_data_delayed_5; + a25_data_delayed_7 <= a25_data_delayed_6; + a25_data_delayed_8 <= a25_data_delayed_7; + a25_data_delayed_9 <= a25_data_delayed_8; + a25_data_delayed_10 <= a25_data_delayed_9; + a25_data_delayed_11 <= a25_data_delayed_10; + a25_data_delayed_12 <= a25_data_delayed_11; + a25_data_delayed_13 <= a25_data_delayed_12; + a25_data_delayed_14 <= a25_data_delayed_13; + a25_data_delayed_15 <= a25_data_delayed_14; + a25_data_delayed_16 <= a25_data_delayed_15; + a25_data_delayed_17 <= a25_data_delayed_16; + a25_data_delayed_18 <= a25_data_delayed_17; + a25_data_delayed_19 <= a25_data_delayed_18; + a25_data_delayed_20 <= a25_data_delayed_19; + a25_data_delayed_21 <= a25_data_delayed_20; + a25_data_delayed_22 <= a25_data_delayed_21; + a25_data_delayed_23 <= a25_data_delayed_22; + a25_data_delayed_24 <= a25_data_delayed_23; + a25_data_delayed_25 <= a25_data_delayed_24; + a26_data_delayed_2 <= a26_data_delayed_1; + a26_data_delayed_3 <= a26_data_delayed_2; + a26_data_delayed_4 <= a26_data_delayed_3; + a26_data_delayed_5 <= a26_data_delayed_4; + a26_data_delayed_6 <= a26_data_delayed_5; + a26_data_delayed_7 <= a26_data_delayed_6; + a26_data_delayed_8 <= a26_data_delayed_7; + a26_data_delayed_9 <= a26_data_delayed_8; + a26_data_delayed_10 <= a26_data_delayed_9; + a26_data_delayed_11 <= a26_data_delayed_10; + a26_data_delayed_12 <= a26_data_delayed_11; + a26_data_delayed_13 <= a26_data_delayed_12; + a26_data_delayed_14 <= a26_data_delayed_13; + a26_data_delayed_15 <= a26_data_delayed_14; + a26_data_delayed_16 <= a26_data_delayed_15; + a26_data_delayed_17 <= a26_data_delayed_16; + a26_data_delayed_18 <= a26_data_delayed_17; + a26_data_delayed_19 <= a26_data_delayed_18; + a26_data_delayed_20 <= a26_data_delayed_19; + a26_data_delayed_21 <= a26_data_delayed_20; + a26_data_delayed_22 <= a26_data_delayed_21; + a26_data_delayed_23 <= a26_data_delayed_22; + a26_data_delayed_24 <= a26_data_delayed_23; + a26_data_delayed_25 <= a26_data_delayed_24; + a26_data_delayed_26 <= a26_data_delayed_25; + a27_data_delayed_2 <= a27_data_delayed_1; + a27_data_delayed_3 <= a27_data_delayed_2; + a27_data_delayed_4 <= a27_data_delayed_3; + a27_data_delayed_5 <= a27_data_delayed_4; + a27_data_delayed_6 <= a27_data_delayed_5; + a27_data_delayed_7 <= a27_data_delayed_6; + a27_data_delayed_8 <= a27_data_delayed_7; + a27_data_delayed_9 <= a27_data_delayed_8; + a27_data_delayed_10 <= a27_data_delayed_9; + a27_data_delayed_11 <= a27_data_delayed_10; + a27_data_delayed_12 <= a27_data_delayed_11; + a27_data_delayed_13 <= a27_data_delayed_12; + a27_data_delayed_14 <= a27_data_delayed_13; + a27_data_delayed_15 <= a27_data_delayed_14; + a27_data_delayed_16 <= a27_data_delayed_15; + a27_data_delayed_17 <= a27_data_delayed_16; + a27_data_delayed_18 <= a27_data_delayed_17; + a27_data_delayed_19 <= a27_data_delayed_18; + a27_data_delayed_20 <= a27_data_delayed_19; + a27_data_delayed_21 <= a27_data_delayed_20; + a27_data_delayed_22 <= a27_data_delayed_21; + a27_data_delayed_23 <= a27_data_delayed_22; + a27_data_delayed_24 <= a27_data_delayed_23; + a27_data_delayed_25 <= a27_data_delayed_24; + a27_data_delayed_26 <= a27_data_delayed_25; + a27_data_delayed_27 <= a27_data_delayed_26; + a28_data_delayed_2 <= a28_data_delayed_1; + a28_data_delayed_3 <= a28_data_delayed_2; + a28_data_delayed_4 <= a28_data_delayed_3; + a28_data_delayed_5 <= a28_data_delayed_4; + a28_data_delayed_6 <= a28_data_delayed_5; + a28_data_delayed_7 <= a28_data_delayed_6; + a28_data_delayed_8 <= a28_data_delayed_7; + a28_data_delayed_9 <= a28_data_delayed_8; + a28_data_delayed_10 <= a28_data_delayed_9; + a28_data_delayed_11 <= a28_data_delayed_10; + a28_data_delayed_12 <= a28_data_delayed_11; + a28_data_delayed_13 <= a28_data_delayed_12; + a28_data_delayed_14 <= a28_data_delayed_13; + a28_data_delayed_15 <= a28_data_delayed_14; + a28_data_delayed_16 <= a28_data_delayed_15; + a28_data_delayed_17 <= a28_data_delayed_16; + a28_data_delayed_18 <= a28_data_delayed_17; + a28_data_delayed_19 <= a28_data_delayed_18; + a28_data_delayed_20 <= a28_data_delayed_19; + a28_data_delayed_21 <= a28_data_delayed_20; + a28_data_delayed_22 <= a28_data_delayed_21; + a28_data_delayed_23 <= a28_data_delayed_22; + a28_data_delayed_24 <= a28_data_delayed_23; + a28_data_delayed_25 <= a28_data_delayed_24; + a28_data_delayed_26 <= a28_data_delayed_25; + a28_data_delayed_27 <= a28_data_delayed_26; + a28_data_delayed_28 <= a28_data_delayed_27; + a29_data_delayed_2 <= a29_data_delayed_1; + a29_data_delayed_3 <= a29_data_delayed_2; + a29_data_delayed_4 <= a29_data_delayed_3; + a29_data_delayed_5 <= a29_data_delayed_4; + a29_data_delayed_6 <= a29_data_delayed_5; + a29_data_delayed_7 <= a29_data_delayed_6; + a29_data_delayed_8 <= a29_data_delayed_7; + a29_data_delayed_9 <= a29_data_delayed_8; + a29_data_delayed_10 <= a29_data_delayed_9; + a29_data_delayed_11 <= a29_data_delayed_10; + a29_data_delayed_12 <= a29_data_delayed_11; + a29_data_delayed_13 <= a29_data_delayed_12; + a29_data_delayed_14 <= a29_data_delayed_13; + a29_data_delayed_15 <= a29_data_delayed_14; + a29_data_delayed_16 <= a29_data_delayed_15; + a29_data_delayed_17 <= a29_data_delayed_16; + a29_data_delayed_18 <= a29_data_delayed_17; + a29_data_delayed_19 <= a29_data_delayed_18; + a29_data_delayed_20 <= a29_data_delayed_19; + a29_data_delayed_21 <= a29_data_delayed_20; + a29_data_delayed_22 <= a29_data_delayed_21; + a29_data_delayed_23 <= a29_data_delayed_22; + a29_data_delayed_24 <= a29_data_delayed_23; + a29_data_delayed_25 <= a29_data_delayed_24; + a29_data_delayed_26 <= a29_data_delayed_25; + a29_data_delayed_27 <= a29_data_delayed_26; + a29_data_delayed_28 <= a29_data_delayed_27; + a29_data_delayed_29 <= a29_data_delayed_28; + a30_data_delayed_2 <= a30_data_delayed_1; + a30_data_delayed_3 <= a30_data_delayed_2; + a30_data_delayed_4 <= a30_data_delayed_3; + a30_data_delayed_5 <= a30_data_delayed_4; + a30_data_delayed_6 <= a30_data_delayed_5; + a30_data_delayed_7 <= a30_data_delayed_6; + a30_data_delayed_8 <= a30_data_delayed_7; + a30_data_delayed_9 <= a30_data_delayed_8; + a30_data_delayed_10 <= a30_data_delayed_9; + a30_data_delayed_11 <= a30_data_delayed_10; + a30_data_delayed_12 <= a30_data_delayed_11; + a30_data_delayed_13 <= a30_data_delayed_12; + a30_data_delayed_14 <= a30_data_delayed_13; + a30_data_delayed_15 <= a30_data_delayed_14; + a30_data_delayed_16 <= a30_data_delayed_15; + a30_data_delayed_17 <= a30_data_delayed_16; + a30_data_delayed_18 <= a30_data_delayed_17; + a30_data_delayed_19 <= a30_data_delayed_18; + a30_data_delayed_20 <= a30_data_delayed_19; + a30_data_delayed_21 <= a30_data_delayed_20; + a30_data_delayed_22 <= a30_data_delayed_21; + a30_data_delayed_23 <= a30_data_delayed_22; + a30_data_delayed_24 <= a30_data_delayed_23; + a30_data_delayed_25 <= a30_data_delayed_24; + a30_data_delayed_26 <= a30_data_delayed_25; + a30_data_delayed_27 <= a30_data_delayed_26; + a30_data_delayed_28 <= a30_data_delayed_27; + a30_data_delayed_29 <= a30_data_delayed_28; + a30_data_delayed_30 <= a30_data_delayed_29; + a31_data_delayed_2 <= a31_data_delayed_1; + a31_data_delayed_3 <= a31_data_delayed_2; + a31_data_delayed_4 <= a31_data_delayed_3; + a31_data_delayed_5 <= a31_data_delayed_4; + a31_data_delayed_6 <= a31_data_delayed_5; + a31_data_delayed_7 <= a31_data_delayed_6; + a31_data_delayed_8 <= a31_data_delayed_7; + a31_data_delayed_9 <= a31_data_delayed_8; + a31_data_delayed_10 <= a31_data_delayed_9; + a31_data_delayed_11 <= a31_data_delayed_10; + a31_data_delayed_12 <= a31_data_delayed_11; + a31_data_delayed_13 <= a31_data_delayed_12; + a31_data_delayed_14 <= a31_data_delayed_13; + a31_data_delayed_15 <= a31_data_delayed_14; + a31_data_delayed_16 <= a31_data_delayed_15; + a31_data_delayed_17 <= a31_data_delayed_16; + a31_data_delayed_18 <= a31_data_delayed_17; + a31_data_delayed_19 <= a31_data_delayed_18; + a31_data_delayed_20 <= a31_data_delayed_19; + a31_data_delayed_21 <= a31_data_delayed_20; + a31_data_delayed_22 <= a31_data_delayed_21; + a31_data_delayed_23 <= a31_data_delayed_22; + a31_data_delayed_24 <= a31_data_delayed_23; + a31_data_delayed_25 <= a31_data_delayed_24; + a31_data_delayed_26 <= a31_data_delayed_25; + a31_data_delayed_27 <= a31_data_delayed_26; + a31_data_delayed_28 <= a31_data_delayed_27; + a31_data_delayed_29 <= a31_data_delayed_28; + a31_data_delayed_30 <= a31_data_delayed_29; + a31_data_delayed_31 <= a31_data_delayed_30; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16) || + (validity_mask_b_rows[16]==1'b0 && b_mem_access_counter==17) || + (validity_mask_b_rows[17]==1'b0 && b_mem_access_counter==18) || + (validity_mask_b_rows[18]==1'b0 && b_mem_access_counter==19) || + (validity_mask_b_rows[19]==1'b0 && b_mem_access_counter==20) || + (validity_mask_b_rows[20]==1'b0 && b_mem_access_counter==21) || + (validity_mask_b_rows[21]==1'b0 && b_mem_access_counter==22) || + (validity_mask_b_rows[22]==1'b0 && b_mem_access_counter==23) || + (validity_mask_b_rows[23]==1'b0 && b_mem_access_counter==24) || + (validity_mask_b_rows[24]==1'b0 && b_mem_access_counter==25) || + (validity_mask_b_rows[25]==1'b0 && b_mem_access_counter==26) || + (validity_mask_b_rows[26]==1'b0 && b_mem_access_counter==27) || + (validity_mask_b_rows[27]==1'b0 && b_mem_access_counter==28) || + (validity_mask_b_rows[28]==1'b0 && b_mem_access_counter==29) || + (validity_mask_b_rows[29]==1'b0 && b_mem_access_counter==30) || + (validity_mask_b_rows[30]==1'b0 && b_mem_access_counter==31) || + (validity_mask_b_rows[31]==1'b0 && b_mem_access_counter==32)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; +assign b16_data = b_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[16]}}; +assign b17_data = b_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[17]}}; +assign b18_data = b_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[18]}}; +assign b19_data = b_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[19]}}; +assign b20_data = b_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[20]}}; +assign b21_data = b_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[21]}}; +assign b22_data = b_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[22]}}; +assign b23_data = b_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[23]}}; +assign b24_data = b_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[24]}}; +assign b25_data = b_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[25]}}; +assign b26_data = b_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[26]}}; +assign b27_data = b_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[27]}}; +assign b28_data = b_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[28]}}; +assign b29_data = b_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[29]}}; +assign b30_data = b_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[30]}}; +assign b31_data = b_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[31]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_1; +reg [`DWIDTH-1:0] b16_data_delayed_2; +reg [`DWIDTH-1:0] b16_data_delayed_3; +reg [`DWIDTH-1:0] b16_data_delayed_4; +reg [`DWIDTH-1:0] b16_data_delayed_5; +reg [`DWIDTH-1:0] b16_data_delayed_6; +reg [`DWIDTH-1:0] b16_data_delayed_7; +reg [`DWIDTH-1:0] b16_data_delayed_8; +reg [`DWIDTH-1:0] b16_data_delayed_9; +reg [`DWIDTH-1:0] b16_data_delayed_10; +reg [`DWIDTH-1:0] b16_data_delayed_11; +reg [`DWIDTH-1:0] b16_data_delayed_12; +reg [`DWIDTH-1:0] b16_data_delayed_13; +reg [`DWIDTH-1:0] b16_data_delayed_14; +reg [`DWIDTH-1:0] b16_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_1; +reg [`DWIDTH-1:0] b17_data_delayed_2; +reg [`DWIDTH-1:0] b17_data_delayed_3; +reg [`DWIDTH-1:0] b17_data_delayed_4; +reg [`DWIDTH-1:0] b17_data_delayed_5; +reg [`DWIDTH-1:0] b17_data_delayed_6; +reg [`DWIDTH-1:0] b17_data_delayed_7; +reg [`DWIDTH-1:0] b17_data_delayed_8; +reg [`DWIDTH-1:0] b17_data_delayed_9; +reg [`DWIDTH-1:0] b17_data_delayed_10; +reg [`DWIDTH-1:0] b17_data_delayed_11; +reg [`DWIDTH-1:0] b17_data_delayed_12; +reg [`DWIDTH-1:0] b17_data_delayed_13; +reg [`DWIDTH-1:0] b17_data_delayed_14; +reg [`DWIDTH-1:0] b17_data_delayed_15; +reg [`DWIDTH-1:0] b17_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_1; +reg [`DWIDTH-1:0] b18_data_delayed_2; +reg [`DWIDTH-1:0] b18_data_delayed_3; +reg [`DWIDTH-1:0] b18_data_delayed_4; +reg [`DWIDTH-1:0] b18_data_delayed_5; +reg [`DWIDTH-1:0] b18_data_delayed_6; +reg [`DWIDTH-1:0] b18_data_delayed_7; +reg [`DWIDTH-1:0] b18_data_delayed_8; +reg [`DWIDTH-1:0] b18_data_delayed_9; +reg [`DWIDTH-1:0] b18_data_delayed_10; +reg [`DWIDTH-1:0] b18_data_delayed_11; +reg [`DWIDTH-1:0] b18_data_delayed_12; +reg [`DWIDTH-1:0] b18_data_delayed_13; +reg [`DWIDTH-1:0] b18_data_delayed_14; +reg [`DWIDTH-1:0] b18_data_delayed_15; +reg [`DWIDTH-1:0] b18_data_delayed_16; +reg [`DWIDTH-1:0] b18_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_1; +reg [`DWIDTH-1:0] b19_data_delayed_2; +reg [`DWIDTH-1:0] b19_data_delayed_3; +reg [`DWIDTH-1:0] b19_data_delayed_4; +reg [`DWIDTH-1:0] b19_data_delayed_5; +reg [`DWIDTH-1:0] b19_data_delayed_6; +reg [`DWIDTH-1:0] b19_data_delayed_7; +reg [`DWIDTH-1:0] b19_data_delayed_8; +reg [`DWIDTH-1:0] b19_data_delayed_9; +reg [`DWIDTH-1:0] b19_data_delayed_10; +reg [`DWIDTH-1:0] b19_data_delayed_11; +reg [`DWIDTH-1:0] b19_data_delayed_12; +reg [`DWIDTH-1:0] b19_data_delayed_13; +reg [`DWIDTH-1:0] b19_data_delayed_14; +reg [`DWIDTH-1:0] b19_data_delayed_15; +reg [`DWIDTH-1:0] b19_data_delayed_16; +reg [`DWIDTH-1:0] b19_data_delayed_17; +reg [`DWIDTH-1:0] b19_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_1; +reg [`DWIDTH-1:0] b20_data_delayed_2; +reg [`DWIDTH-1:0] b20_data_delayed_3; +reg [`DWIDTH-1:0] b20_data_delayed_4; +reg [`DWIDTH-1:0] b20_data_delayed_5; +reg [`DWIDTH-1:0] b20_data_delayed_6; +reg [`DWIDTH-1:0] b20_data_delayed_7; +reg [`DWIDTH-1:0] b20_data_delayed_8; +reg [`DWIDTH-1:0] b20_data_delayed_9; +reg [`DWIDTH-1:0] b20_data_delayed_10; +reg [`DWIDTH-1:0] b20_data_delayed_11; +reg [`DWIDTH-1:0] b20_data_delayed_12; +reg [`DWIDTH-1:0] b20_data_delayed_13; +reg [`DWIDTH-1:0] b20_data_delayed_14; +reg [`DWIDTH-1:0] b20_data_delayed_15; +reg [`DWIDTH-1:0] b20_data_delayed_16; +reg [`DWIDTH-1:0] b20_data_delayed_17; +reg [`DWIDTH-1:0] b20_data_delayed_18; +reg [`DWIDTH-1:0] b20_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_1; +reg [`DWIDTH-1:0] b21_data_delayed_2; +reg [`DWIDTH-1:0] b21_data_delayed_3; +reg [`DWIDTH-1:0] b21_data_delayed_4; +reg [`DWIDTH-1:0] b21_data_delayed_5; +reg [`DWIDTH-1:0] b21_data_delayed_6; +reg [`DWIDTH-1:0] b21_data_delayed_7; +reg [`DWIDTH-1:0] b21_data_delayed_8; +reg [`DWIDTH-1:0] b21_data_delayed_9; +reg [`DWIDTH-1:0] b21_data_delayed_10; +reg [`DWIDTH-1:0] b21_data_delayed_11; +reg [`DWIDTH-1:0] b21_data_delayed_12; +reg [`DWIDTH-1:0] b21_data_delayed_13; +reg [`DWIDTH-1:0] b21_data_delayed_14; +reg [`DWIDTH-1:0] b21_data_delayed_15; +reg [`DWIDTH-1:0] b21_data_delayed_16; +reg [`DWIDTH-1:0] b21_data_delayed_17; +reg [`DWIDTH-1:0] b21_data_delayed_18; +reg [`DWIDTH-1:0] b21_data_delayed_19; +reg [`DWIDTH-1:0] b21_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_1; +reg [`DWIDTH-1:0] b22_data_delayed_2; +reg [`DWIDTH-1:0] b22_data_delayed_3; +reg [`DWIDTH-1:0] b22_data_delayed_4; +reg [`DWIDTH-1:0] b22_data_delayed_5; +reg [`DWIDTH-1:0] b22_data_delayed_6; +reg [`DWIDTH-1:0] b22_data_delayed_7; +reg [`DWIDTH-1:0] b22_data_delayed_8; +reg [`DWIDTH-1:0] b22_data_delayed_9; +reg [`DWIDTH-1:0] b22_data_delayed_10; +reg [`DWIDTH-1:0] b22_data_delayed_11; +reg [`DWIDTH-1:0] b22_data_delayed_12; +reg [`DWIDTH-1:0] b22_data_delayed_13; +reg [`DWIDTH-1:0] b22_data_delayed_14; +reg [`DWIDTH-1:0] b22_data_delayed_15; +reg [`DWIDTH-1:0] b22_data_delayed_16; +reg [`DWIDTH-1:0] b22_data_delayed_17; +reg [`DWIDTH-1:0] b22_data_delayed_18; +reg [`DWIDTH-1:0] b22_data_delayed_19; +reg [`DWIDTH-1:0] b22_data_delayed_20; +reg [`DWIDTH-1:0] b22_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_1; +reg [`DWIDTH-1:0] b23_data_delayed_2; +reg [`DWIDTH-1:0] b23_data_delayed_3; +reg [`DWIDTH-1:0] b23_data_delayed_4; +reg [`DWIDTH-1:0] b23_data_delayed_5; +reg [`DWIDTH-1:0] b23_data_delayed_6; +reg [`DWIDTH-1:0] b23_data_delayed_7; +reg [`DWIDTH-1:0] b23_data_delayed_8; +reg [`DWIDTH-1:0] b23_data_delayed_9; +reg [`DWIDTH-1:0] b23_data_delayed_10; +reg [`DWIDTH-1:0] b23_data_delayed_11; +reg [`DWIDTH-1:0] b23_data_delayed_12; +reg [`DWIDTH-1:0] b23_data_delayed_13; +reg [`DWIDTH-1:0] b23_data_delayed_14; +reg [`DWIDTH-1:0] b23_data_delayed_15; +reg [`DWIDTH-1:0] b23_data_delayed_16; +reg [`DWIDTH-1:0] b23_data_delayed_17; +reg [`DWIDTH-1:0] b23_data_delayed_18; +reg [`DWIDTH-1:0] b23_data_delayed_19; +reg [`DWIDTH-1:0] b23_data_delayed_20; +reg [`DWIDTH-1:0] b23_data_delayed_21; +reg [`DWIDTH-1:0] b23_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_1; +reg [`DWIDTH-1:0] b24_data_delayed_2; +reg [`DWIDTH-1:0] b24_data_delayed_3; +reg [`DWIDTH-1:0] b24_data_delayed_4; +reg [`DWIDTH-1:0] b24_data_delayed_5; +reg [`DWIDTH-1:0] b24_data_delayed_6; +reg [`DWIDTH-1:0] b24_data_delayed_7; +reg [`DWIDTH-1:0] b24_data_delayed_8; +reg [`DWIDTH-1:0] b24_data_delayed_9; +reg [`DWIDTH-1:0] b24_data_delayed_10; +reg [`DWIDTH-1:0] b24_data_delayed_11; +reg [`DWIDTH-1:0] b24_data_delayed_12; +reg [`DWIDTH-1:0] b24_data_delayed_13; +reg [`DWIDTH-1:0] b24_data_delayed_14; +reg [`DWIDTH-1:0] b24_data_delayed_15; +reg [`DWIDTH-1:0] b24_data_delayed_16; +reg [`DWIDTH-1:0] b24_data_delayed_17; +reg [`DWIDTH-1:0] b24_data_delayed_18; +reg [`DWIDTH-1:0] b24_data_delayed_19; +reg [`DWIDTH-1:0] b24_data_delayed_20; +reg [`DWIDTH-1:0] b24_data_delayed_21; +reg [`DWIDTH-1:0] b24_data_delayed_22; +reg [`DWIDTH-1:0] b24_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_1; +reg [`DWIDTH-1:0] b25_data_delayed_2; +reg [`DWIDTH-1:0] b25_data_delayed_3; +reg [`DWIDTH-1:0] b25_data_delayed_4; +reg [`DWIDTH-1:0] b25_data_delayed_5; +reg [`DWIDTH-1:0] b25_data_delayed_6; +reg [`DWIDTH-1:0] b25_data_delayed_7; +reg [`DWIDTH-1:0] b25_data_delayed_8; +reg [`DWIDTH-1:0] b25_data_delayed_9; +reg [`DWIDTH-1:0] b25_data_delayed_10; +reg [`DWIDTH-1:0] b25_data_delayed_11; +reg [`DWIDTH-1:0] b25_data_delayed_12; +reg [`DWIDTH-1:0] b25_data_delayed_13; +reg [`DWIDTH-1:0] b25_data_delayed_14; +reg [`DWIDTH-1:0] b25_data_delayed_15; +reg [`DWIDTH-1:0] b25_data_delayed_16; +reg [`DWIDTH-1:0] b25_data_delayed_17; +reg [`DWIDTH-1:0] b25_data_delayed_18; +reg [`DWIDTH-1:0] b25_data_delayed_19; +reg [`DWIDTH-1:0] b25_data_delayed_20; +reg [`DWIDTH-1:0] b25_data_delayed_21; +reg [`DWIDTH-1:0] b25_data_delayed_22; +reg [`DWIDTH-1:0] b25_data_delayed_23; +reg [`DWIDTH-1:0] b25_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_1; +reg [`DWIDTH-1:0] b26_data_delayed_2; +reg [`DWIDTH-1:0] b26_data_delayed_3; +reg [`DWIDTH-1:0] b26_data_delayed_4; +reg [`DWIDTH-1:0] b26_data_delayed_5; +reg [`DWIDTH-1:0] b26_data_delayed_6; +reg [`DWIDTH-1:0] b26_data_delayed_7; +reg [`DWIDTH-1:0] b26_data_delayed_8; +reg [`DWIDTH-1:0] b26_data_delayed_9; +reg [`DWIDTH-1:0] b26_data_delayed_10; +reg [`DWIDTH-1:0] b26_data_delayed_11; +reg [`DWIDTH-1:0] b26_data_delayed_12; +reg [`DWIDTH-1:0] b26_data_delayed_13; +reg [`DWIDTH-1:0] b26_data_delayed_14; +reg [`DWIDTH-1:0] b26_data_delayed_15; +reg [`DWIDTH-1:0] b26_data_delayed_16; +reg [`DWIDTH-1:0] b26_data_delayed_17; +reg [`DWIDTH-1:0] b26_data_delayed_18; +reg [`DWIDTH-1:0] b26_data_delayed_19; +reg [`DWIDTH-1:0] b26_data_delayed_20; +reg [`DWIDTH-1:0] b26_data_delayed_21; +reg [`DWIDTH-1:0] b26_data_delayed_22; +reg [`DWIDTH-1:0] b26_data_delayed_23; +reg [`DWIDTH-1:0] b26_data_delayed_24; +reg [`DWIDTH-1:0] b26_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_1; +reg [`DWIDTH-1:0] b27_data_delayed_2; +reg [`DWIDTH-1:0] b27_data_delayed_3; +reg [`DWIDTH-1:0] b27_data_delayed_4; +reg [`DWIDTH-1:0] b27_data_delayed_5; +reg [`DWIDTH-1:0] b27_data_delayed_6; +reg [`DWIDTH-1:0] b27_data_delayed_7; +reg [`DWIDTH-1:0] b27_data_delayed_8; +reg [`DWIDTH-1:0] b27_data_delayed_9; +reg [`DWIDTH-1:0] b27_data_delayed_10; +reg [`DWIDTH-1:0] b27_data_delayed_11; +reg [`DWIDTH-1:0] b27_data_delayed_12; +reg [`DWIDTH-1:0] b27_data_delayed_13; +reg [`DWIDTH-1:0] b27_data_delayed_14; +reg [`DWIDTH-1:0] b27_data_delayed_15; +reg [`DWIDTH-1:0] b27_data_delayed_16; +reg [`DWIDTH-1:0] b27_data_delayed_17; +reg [`DWIDTH-1:0] b27_data_delayed_18; +reg [`DWIDTH-1:0] b27_data_delayed_19; +reg [`DWIDTH-1:0] b27_data_delayed_20; +reg [`DWIDTH-1:0] b27_data_delayed_21; +reg [`DWIDTH-1:0] b27_data_delayed_22; +reg [`DWIDTH-1:0] b27_data_delayed_23; +reg [`DWIDTH-1:0] b27_data_delayed_24; +reg [`DWIDTH-1:0] b27_data_delayed_25; +reg [`DWIDTH-1:0] b27_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_1; +reg [`DWIDTH-1:0] b28_data_delayed_2; +reg [`DWIDTH-1:0] b28_data_delayed_3; +reg [`DWIDTH-1:0] b28_data_delayed_4; +reg [`DWIDTH-1:0] b28_data_delayed_5; +reg [`DWIDTH-1:0] b28_data_delayed_6; +reg [`DWIDTH-1:0] b28_data_delayed_7; +reg [`DWIDTH-1:0] b28_data_delayed_8; +reg [`DWIDTH-1:0] b28_data_delayed_9; +reg [`DWIDTH-1:0] b28_data_delayed_10; +reg [`DWIDTH-1:0] b28_data_delayed_11; +reg [`DWIDTH-1:0] b28_data_delayed_12; +reg [`DWIDTH-1:0] b28_data_delayed_13; +reg [`DWIDTH-1:0] b28_data_delayed_14; +reg [`DWIDTH-1:0] b28_data_delayed_15; +reg [`DWIDTH-1:0] b28_data_delayed_16; +reg [`DWIDTH-1:0] b28_data_delayed_17; +reg [`DWIDTH-1:0] b28_data_delayed_18; +reg [`DWIDTH-1:0] b28_data_delayed_19; +reg [`DWIDTH-1:0] b28_data_delayed_20; +reg [`DWIDTH-1:0] b28_data_delayed_21; +reg [`DWIDTH-1:0] b28_data_delayed_22; +reg [`DWIDTH-1:0] b28_data_delayed_23; +reg [`DWIDTH-1:0] b28_data_delayed_24; +reg [`DWIDTH-1:0] b28_data_delayed_25; +reg [`DWIDTH-1:0] b28_data_delayed_26; +reg [`DWIDTH-1:0] b28_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_1; +reg [`DWIDTH-1:0] b29_data_delayed_2; +reg [`DWIDTH-1:0] b29_data_delayed_3; +reg [`DWIDTH-1:0] b29_data_delayed_4; +reg [`DWIDTH-1:0] b29_data_delayed_5; +reg [`DWIDTH-1:0] b29_data_delayed_6; +reg [`DWIDTH-1:0] b29_data_delayed_7; +reg [`DWIDTH-1:0] b29_data_delayed_8; +reg [`DWIDTH-1:0] b29_data_delayed_9; +reg [`DWIDTH-1:0] b29_data_delayed_10; +reg [`DWIDTH-1:0] b29_data_delayed_11; +reg [`DWIDTH-1:0] b29_data_delayed_12; +reg [`DWIDTH-1:0] b29_data_delayed_13; +reg [`DWIDTH-1:0] b29_data_delayed_14; +reg [`DWIDTH-1:0] b29_data_delayed_15; +reg [`DWIDTH-1:0] b29_data_delayed_16; +reg [`DWIDTH-1:0] b29_data_delayed_17; +reg [`DWIDTH-1:0] b29_data_delayed_18; +reg [`DWIDTH-1:0] b29_data_delayed_19; +reg [`DWIDTH-1:0] b29_data_delayed_20; +reg [`DWIDTH-1:0] b29_data_delayed_21; +reg [`DWIDTH-1:0] b29_data_delayed_22; +reg [`DWIDTH-1:0] b29_data_delayed_23; +reg [`DWIDTH-1:0] b29_data_delayed_24; +reg [`DWIDTH-1:0] b29_data_delayed_25; +reg [`DWIDTH-1:0] b29_data_delayed_26; +reg [`DWIDTH-1:0] b29_data_delayed_27; +reg [`DWIDTH-1:0] b29_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_1; +reg [`DWIDTH-1:0] b30_data_delayed_2; +reg [`DWIDTH-1:0] b30_data_delayed_3; +reg [`DWIDTH-1:0] b30_data_delayed_4; +reg [`DWIDTH-1:0] b30_data_delayed_5; +reg [`DWIDTH-1:0] b30_data_delayed_6; +reg [`DWIDTH-1:0] b30_data_delayed_7; +reg [`DWIDTH-1:0] b30_data_delayed_8; +reg [`DWIDTH-1:0] b30_data_delayed_9; +reg [`DWIDTH-1:0] b30_data_delayed_10; +reg [`DWIDTH-1:0] b30_data_delayed_11; +reg [`DWIDTH-1:0] b30_data_delayed_12; +reg [`DWIDTH-1:0] b30_data_delayed_13; +reg [`DWIDTH-1:0] b30_data_delayed_14; +reg [`DWIDTH-1:0] b30_data_delayed_15; +reg [`DWIDTH-1:0] b30_data_delayed_16; +reg [`DWIDTH-1:0] b30_data_delayed_17; +reg [`DWIDTH-1:0] b30_data_delayed_18; +reg [`DWIDTH-1:0] b30_data_delayed_19; +reg [`DWIDTH-1:0] b30_data_delayed_20; +reg [`DWIDTH-1:0] b30_data_delayed_21; +reg [`DWIDTH-1:0] b30_data_delayed_22; +reg [`DWIDTH-1:0] b30_data_delayed_23; +reg [`DWIDTH-1:0] b30_data_delayed_24; +reg [`DWIDTH-1:0] b30_data_delayed_25; +reg [`DWIDTH-1:0] b30_data_delayed_26; +reg [`DWIDTH-1:0] b30_data_delayed_27; +reg [`DWIDTH-1:0] b30_data_delayed_28; +reg [`DWIDTH-1:0] b30_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_1; +reg [`DWIDTH-1:0] b31_data_delayed_2; +reg [`DWIDTH-1:0] b31_data_delayed_3; +reg [`DWIDTH-1:0] b31_data_delayed_4; +reg [`DWIDTH-1:0] b31_data_delayed_5; +reg [`DWIDTH-1:0] b31_data_delayed_6; +reg [`DWIDTH-1:0] b31_data_delayed_7; +reg [`DWIDTH-1:0] b31_data_delayed_8; +reg [`DWIDTH-1:0] b31_data_delayed_9; +reg [`DWIDTH-1:0] b31_data_delayed_10; +reg [`DWIDTH-1:0] b31_data_delayed_11; +reg [`DWIDTH-1:0] b31_data_delayed_12; +reg [`DWIDTH-1:0] b31_data_delayed_13; +reg [`DWIDTH-1:0] b31_data_delayed_14; +reg [`DWIDTH-1:0] b31_data_delayed_15; +reg [`DWIDTH-1:0] b31_data_delayed_16; +reg [`DWIDTH-1:0] b31_data_delayed_17; +reg [`DWIDTH-1:0] b31_data_delayed_18; +reg [`DWIDTH-1:0] b31_data_delayed_19; +reg [`DWIDTH-1:0] b31_data_delayed_20; +reg [`DWIDTH-1:0] b31_data_delayed_21; +reg [`DWIDTH-1:0] b31_data_delayed_22; +reg [`DWIDTH-1:0] b31_data_delayed_23; +reg [`DWIDTH-1:0] b31_data_delayed_24; +reg [`DWIDTH-1:0] b31_data_delayed_25; +reg [`DWIDTH-1:0] b31_data_delayed_26; +reg [`DWIDTH-1:0] b31_data_delayed_27; +reg [`DWIDTH-1:0] b31_data_delayed_28; +reg [`DWIDTH-1:0] b31_data_delayed_29; +reg [`DWIDTH-1:0] b31_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + b16_data_delayed_1 <= 0; + b16_data_delayed_2 <= 0; + b16_data_delayed_3 <= 0; + b16_data_delayed_4 <= 0; + b16_data_delayed_5 <= 0; + b16_data_delayed_6 <= 0; + b16_data_delayed_7 <= 0; + b16_data_delayed_8 <= 0; + b16_data_delayed_9 <= 0; + b16_data_delayed_10 <= 0; + b16_data_delayed_11 <= 0; + b16_data_delayed_12 <= 0; + b16_data_delayed_13 <= 0; + b16_data_delayed_14 <= 0; + b16_data_delayed_15 <= 0; + b16_data_delayed_16 <= 0; + b17_data_delayed_1 <= 0; + b17_data_delayed_2 <= 0; + b17_data_delayed_3 <= 0; + b17_data_delayed_4 <= 0; + b17_data_delayed_5 <= 0; + b17_data_delayed_6 <= 0; + b17_data_delayed_7 <= 0; + b17_data_delayed_8 <= 0; + b17_data_delayed_9 <= 0; + b17_data_delayed_10 <= 0; + b17_data_delayed_11 <= 0; + b17_data_delayed_12 <= 0; + b17_data_delayed_13 <= 0; + b17_data_delayed_14 <= 0; + b17_data_delayed_15 <= 0; + b17_data_delayed_16 <= 0; + b17_data_delayed_17 <= 0; + b18_data_delayed_1 <= 0; + b18_data_delayed_2 <= 0; + b18_data_delayed_3 <= 0; + b18_data_delayed_4 <= 0; + b18_data_delayed_5 <= 0; + b18_data_delayed_6 <= 0; + b18_data_delayed_7 <= 0; + b18_data_delayed_8 <= 0; + b18_data_delayed_9 <= 0; + b18_data_delayed_10 <= 0; + b18_data_delayed_11 <= 0; + b18_data_delayed_12 <= 0; + b18_data_delayed_13 <= 0; + b18_data_delayed_14 <= 0; + b18_data_delayed_15 <= 0; + b18_data_delayed_16 <= 0; + b18_data_delayed_17 <= 0; + b18_data_delayed_18 <= 0; + b19_data_delayed_1 <= 0; + b19_data_delayed_2 <= 0; + b19_data_delayed_3 <= 0; + b19_data_delayed_4 <= 0; + b19_data_delayed_5 <= 0; + b19_data_delayed_6 <= 0; + b19_data_delayed_7 <= 0; + b19_data_delayed_8 <= 0; + b19_data_delayed_9 <= 0; + b19_data_delayed_10 <= 0; + b19_data_delayed_11 <= 0; + b19_data_delayed_12 <= 0; + b19_data_delayed_13 <= 0; + b19_data_delayed_14 <= 0; + b19_data_delayed_15 <= 0; + b19_data_delayed_16 <= 0; + b19_data_delayed_17 <= 0; + b19_data_delayed_18 <= 0; + b19_data_delayed_19 <= 0; + b20_data_delayed_1 <= 0; + b20_data_delayed_2 <= 0; + b20_data_delayed_3 <= 0; + b20_data_delayed_4 <= 0; + b20_data_delayed_5 <= 0; + b20_data_delayed_6 <= 0; + b20_data_delayed_7 <= 0; + b20_data_delayed_8 <= 0; + b20_data_delayed_9 <= 0; + b20_data_delayed_10 <= 0; + b20_data_delayed_11 <= 0; + b20_data_delayed_12 <= 0; + b20_data_delayed_13 <= 0; + b20_data_delayed_14 <= 0; + b20_data_delayed_15 <= 0; + b20_data_delayed_16 <= 0; + b20_data_delayed_17 <= 0; + b20_data_delayed_18 <= 0; + b20_data_delayed_19 <= 0; + b20_data_delayed_20 <= 0; + b21_data_delayed_1 <= 0; + b21_data_delayed_2 <= 0; + b21_data_delayed_3 <= 0; + b21_data_delayed_4 <= 0; + b21_data_delayed_5 <= 0; + b21_data_delayed_6 <= 0; + b21_data_delayed_7 <= 0; + b21_data_delayed_8 <= 0; + b21_data_delayed_9 <= 0; + b21_data_delayed_10 <= 0; + b21_data_delayed_11 <= 0; + b21_data_delayed_12 <= 0; + b21_data_delayed_13 <= 0; + b21_data_delayed_14 <= 0; + b21_data_delayed_15 <= 0; + b21_data_delayed_16 <= 0; + b21_data_delayed_17 <= 0; + b21_data_delayed_18 <= 0; + b21_data_delayed_19 <= 0; + b21_data_delayed_20 <= 0; + b21_data_delayed_21 <= 0; + b22_data_delayed_1 <= 0; + b22_data_delayed_2 <= 0; + b22_data_delayed_3 <= 0; + b22_data_delayed_4 <= 0; + b22_data_delayed_5 <= 0; + b22_data_delayed_6 <= 0; + b22_data_delayed_7 <= 0; + b22_data_delayed_8 <= 0; + b22_data_delayed_9 <= 0; + b22_data_delayed_10 <= 0; + b22_data_delayed_11 <= 0; + b22_data_delayed_12 <= 0; + b22_data_delayed_13 <= 0; + b22_data_delayed_14 <= 0; + b22_data_delayed_15 <= 0; + b22_data_delayed_16 <= 0; + b22_data_delayed_17 <= 0; + b22_data_delayed_18 <= 0; + b22_data_delayed_19 <= 0; + b22_data_delayed_20 <= 0; + b22_data_delayed_21 <= 0; + b22_data_delayed_22 <= 0; + b23_data_delayed_1 <= 0; + b23_data_delayed_2 <= 0; + b23_data_delayed_3 <= 0; + b23_data_delayed_4 <= 0; + b23_data_delayed_5 <= 0; + b23_data_delayed_6 <= 0; + b23_data_delayed_7 <= 0; + b23_data_delayed_8 <= 0; + b23_data_delayed_9 <= 0; + b23_data_delayed_10 <= 0; + b23_data_delayed_11 <= 0; + b23_data_delayed_12 <= 0; + b23_data_delayed_13 <= 0; + b23_data_delayed_14 <= 0; + b23_data_delayed_15 <= 0; + b23_data_delayed_16 <= 0; + b23_data_delayed_17 <= 0; + b23_data_delayed_18 <= 0; + b23_data_delayed_19 <= 0; + b23_data_delayed_20 <= 0; + b23_data_delayed_21 <= 0; + b23_data_delayed_22 <= 0; + b23_data_delayed_23 <= 0; + b24_data_delayed_1 <= 0; + b24_data_delayed_2 <= 0; + b24_data_delayed_3 <= 0; + b24_data_delayed_4 <= 0; + b24_data_delayed_5 <= 0; + b24_data_delayed_6 <= 0; + b24_data_delayed_7 <= 0; + b24_data_delayed_8 <= 0; + b24_data_delayed_9 <= 0; + b24_data_delayed_10 <= 0; + b24_data_delayed_11 <= 0; + b24_data_delayed_12 <= 0; + b24_data_delayed_13 <= 0; + b24_data_delayed_14 <= 0; + b24_data_delayed_15 <= 0; + b24_data_delayed_16 <= 0; + b24_data_delayed_17 <= 0; + b24_data_delayed_18 <= 0; + b24_data_delayed_19 <= 0; + b24_data_delayed_20 <= 0; + b24_data_delayed_21 <= 0; + b24_data_delayed_22 <= 0; + b24_data_delayed_23 <= 0; + b24_data_delayed_24 <= 0; + b25_data_delayed_1 <= 0; + b25_data_delayed_2 <= 0; + b25_data_delayed_3 <= 0; + b25_data_delayed_4 <= 0; + b25_data_delayed_5 <= 0; + b25_data_delayed_6 <= 0; + b25_data_delayed_7 <= 0; + b25_data_delayed_8 <= 0; + b25_data_delayed_9 <= 0; + b25_data_delayed_10 <= 0; + b25_data_delayed_11 <= 0; + b25_data_delayed_12 <= 0; + b25_data_delayed_13 <= 0; + b25_data_delayed_14 <= 0; + b25_data_delayed_15 <= 0; + b25_data_delayed_16 <= 0; + b25_data_delayed_17 <= 0; + b25_data_delayed_18 <= 0; + b25_data_delayed_19 <= 0; + b25_data_delayed_20 <= 0; + b25_data_delayed_21 <= 0; + b25_data_delayed_22 <= 0; + b25_data_delayed_23 <= 0; + b25_data_delayed_24 <= 0; + b25_data_delayed_25 <= 0; + b26_data_delayed_1 <= 0; + b26_data_delayed_2 <= 0; + b26_data_delayed_3 <= 0; + b26_data_delayed_4 <= 0; + b26_data_delayed_5 <= 0; + b26_data_delayed_6 <= 0; + b26_data_delayed_7 <= 0; + b26_data_delayed_8 <= 0; + b26_data_delayed_9 <= 0; + b26_data_delayed_10 <= 0; + b26_data_delayed_11 <= 0; + b26_data_delayed_12 <= 0; + b26_data_delayed_13 <= 0; + b26_data_delayed_14 <= 0; + b26_data_delayed_15 <= 0; + b26_data_delayed_16 <= 0; + b26_data_delayed_17 <= 0; + b26_data_delayed_18 <= 0; + b26_data_delayed_19 <= 0; + b26_data_delayed_20 <= 0; + b26_data_delayed_21 <= 0; + b26_data_delayed_22 <= 0; + b26_data_delayed_23 <= 0; + b26_data_delayed_24 <= 0; + b26_data_delayed_25 <= 0; + b26_data_delayed_26 <= 0; + b27_data_delayed_1 <= 0; + b27_data_delayed_2 <= 0; + b27_data_delayed_3 <= 0; + b27_data_delayed_4 <= 0; + b27_data_delayed_5 <= 0; + b27_data_delayed_6 <= 0; + b27_data_delayed_7 <= 0; + b27_data_delayed_8 <= 0; + b27_data_delayed_9 <= 0; + b27_data_delayed_10 <= 0; + b27_data_delayed_11 <= 0; + b27_data_delayed_12 <= 0; + b27_data_delayed_13 <= 0; + b27_data_delayed_14 <= 0; + b27_data_delayed_15 <= 0; + b27_data_delayed_16 <= 0; + b27_data_delayed_17 <= 0; + b27_data_delayed_18 <= 0; + b27_data_delayed_19 <= 0; + b27_data_delayed_20 <= 0; + b27_data_delayed_21 <= 0; + b27_data_delayed_22 <= 0; + b27_data_delayed_23 <= 0; + b27_data_delayed_24 <= 0; + b27_data_delayed_25 <= 0; + b27_data_delayed_26 <= 0; + b27_data_delayed_27 <= 0; + b28_data_delayed_1 <= 0; + b28_data_delayed_2 <= 0; + b28_data_delayed_3 <= 0; + b28_data_delayed_4 <= 0; + b28_data_delayed_5 <= 0; + b28_data_delayed_6 <= 0; + b28_data_delayed_7 <= 0; + b28_data_delayed_8 <= 0; + b28_data_delayed_9 <= 0; + b28_data_delayed_10 <= 0; + b28_data_delayed_11 <= 0; + b28_data_delayed_12 <= 0; + b28_data_delayed_13 <= 0; + b28_data_delayed_14 <= 0; + b28_data_delayed_15 <= 0; + b28_data_delayed_16 <= 0; + b28_data_delayed_17 <= 0; + b28_data_delayed_18 <= 0; + b28_data_delayed_19 <= 0; + b28_data_delayed_20 <= 0; + b28_data_delayed_21 <= 0; + b28_data_delayed_22 <= 0; + b28_data_delayed_23 <= 0; + b28_data_delayed_24 <= 0; + b28_data_delayed_25 <= 0; + b28_data_delayed_26 <= 0; + b28_data_delayed_27 <= 0; + b28_data_delayed_28 <= 0; + b29_data_delayed_1 <= 0; + b29_data_delayed_2 <= 0; + b29_data_delayed_3 <= 0; + b29_data_delayed_4 <= 0; + b29_data_delayed_5 <= 0; + b29_data_delayed_6 <= 0; + b29_data_delayed_7 <= 0; + b29_data_delayed_8 <= 0; + b29_data_delayed_9 <= 0; + b29_data_delayed_10 <= 0; + b29_data_delayed_11 <= 0; + b29_data_delayed_12 <= 0; + b29_data_delayed_13 <= 0; + b29_data_delayed_14 <= 0; + b29_data_delayed_15 <= 0; + b29_data_delayed_16 <= 0; + b29_data_delayed_17 <= 0; + b29_data_delayed_18 <= 0; + b29_data_delayed_19 <= 0; + b29_data_delayed_20 <= 0; + b29_data_delayed_21 <= 0; + b29_data_delayed_22 <= 0; + b29_data_delayed_23 <= 0; + b29_data_delayed_24 <= 0; + b29_data_delayed_25 <= 0; + b29_data_delayed_26 <= 0; + b29_data_delayed_27 <= 0; + b29_data_delayed_28 <= 0; + b29_data_delayed_29 <= 0; + b30_data_delayed_1 <= 0; + b30_data_delayed_2 <= 0; + b30_data_delayed_3 <= 0; + b30_data_delayed_4 <= 0; + b30_data_delayed_5 <= 0; + b30_data_delayed_6 <= 0; + b30_data_delayed_7 <= 0; + b30_data_delayed_8 <= 0; + b30_data_delayed_9 <= 0; + b30_data_delayed_10 <= 0; + b30_data_delayed_11 <= 0; + b30_data_delayed_12 <= 0; + b30_data_delayed_13 <= 0; + b30_data_delayed_14 <= 0; + b30_data_delayed_15 <= 0; + b30_data_delayed_16 <= 0; + b30_data_delayed_17 <= 0; + b30_data_delayed_18 <= 0; + b30_data_delayed_19 <= 0; + b30_data_delayed_20 <= 0; + b30_data_delayed_21 <= 0; + b30_data_delayed_22 <= 0; + b30_data_delayed_23 <= 0; + b30_data_delayed_24 <= 0; + b30_data_delayed_25 <= 0; + b30_data_delayed_26 <= 0; + b30_data_delayed_27 <= 0; + b30_data_delayed_28 <= 0; + b30_data_delayed_29 <= 0; + b30_data_delayed_30 <= 0; + b31_data_delayed_1 <= 0; + b31_data_delayed_2 <= 0; + b31_data_delayed_3 <= 0; + b31_data_delayed_4 <= 0; + b31_data_delayed_5 <= 0; + b31_data_delayed_6 <= 0; + b31_data_delayed_7 <= 0; + b31_data_delayed_8 <= 0; + b31_data_delayed_9 <= 0; + b31_data_delayed_10 <= 0; + b31_data_delayed_11 <= 0; + b31_data_delayed_12 <= 0; + b31_data_delayed_13 <= 0; + b31_data_delayed_14 <= 0; + b31_data_delayed_15 <= 0; + b31_data_delayed_16 <= 0; + b31_data_delayed_17 <= 0; + b31_data_delayed_18 <= 0; + b31_data_delayed_19 <= 0; + b31_data_delayed_20 <= 0; + b31_data_delayed_21 <= 0; + b31_data_delayed_22 <= 0; + b31_data_delayed_23 <= 0; + b31_data_delayed_24 <= 0; + b31_data_delayed_25 <= 0; + b31_data_delayed_26 <= 0; + b31_data_delayed_27 <= 0; + b31_data_delayed_28 <= 0; + b31_data_delayed_29 <= 0; + b31_data_delayed_30 <= 0; + b31_data_delayed_31 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b16_data_delayed_1 <= b16_data; + b17_data_delayed_1 <= b17_data; + b18_data_delayed_1 <= b18_data; + b19_data_delayed_1 <= b19_data; + b20_data_delayed_1 <= b20_data; + b21_data_delayed_1 <= b21_data; + b22_data_delayed_1 <= b22_data; + b23_data_delayed_1 <= b23_data; + b24_data_delayed_1 <= b24_data; + b25_data_delayed_1 <= b25_data; + b26_data_delayed_1 <= b26_data; + b27_data_delayed_1 <= b27_data; + b28_data_delayed_1 <= b28_data; + b29_data_delayed_1 <= b29_data; + b30_data_delayed_1 <= b30_data; + b31_data_delayed_1 <= b31_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + b16_data_delayed_2 <= b16_data_delayed_1; + b16_data_delayed_3 <= b16_data_delayed_2; + b16_data_delayed_4 <= b16_data_delayed_3; + b16_data_delayed_5 <= b16_data_delayed_4; + b16_data_delayed_6 <= b16_data_delayed_5; + b16_data_delayed_7 <= b16_data_delayed_6; + b16_data_delayed_8 <= b16_data_delayed_7; + b16_data_delayed_9 <= b16_data_delayed_8; + b16_data_delayed_10 <= b16_data_delayed_9; + b16_data_delayed_11 <= b16_data_delayed_10; + b16_data_delayed_12 <= b16_data_delayed_11; + b16_data_delayed_13 <= b16_data_delayed_12; + b16_data_delayed_14 <= b16_data_delayed_13; + b16_data_delayed_15 <= b16_data_delayed_14; + b16_data_delayed_16 <= b16_data_delayed_15; + b17_data_delayed_2 <= b17_data_delayed_1; + b17_data_delayed_3 <= b17_data_delayed_2; + b17_data_delayed_4 <= b17_data_delayed_3; + b17_data_delayed_5 <= b17_data_delayed_4; + b17_data_delayed_6 <= b17_data_delayed_5; + b17_data_delayed_7 <= b17_data_delayed_6; + b17_data_delayed_8 <= b17_data_delayed_7; + b17_data_delayed_9 <= b17_data_delayed_8; + b17_data_delayed_10 <= b17_data_delayed_9; + b17_data_delayed_11 <= b17_data_delayed_10; + b17_data_delayed_12 <= b17_data_delayed_11; + b17_data_delayed_13 <= b17_data_delayed_12; + b17_data_delayed_14 <= b17_data_delayed_13; + b17_data_delayed_15 <= b17_data_delayed_14; + b17_data_delayed_16 <= b17_data_delayed_15; + b17_data_delayed_17 <= b17_data_delayed_16; + b18_data_delayed_2 <= b18_data_delayed_1; + b18_data_delayed_3 <= b18_data_delayed_2; + b18_data_delayed_4 <= b18_data_delayed_3; + b18_data_delayed_5 <= b18_data_delayed_4; + b18_data_delayed_6 <= b18_data_delayed_5; + b18_data_delayed_7 <= b18_data_delayed_6; + b18_data_delayed_8 <= b18_data_delayed_7; + b18_data_delayed_9 <= b18_data_delayed_8; + b18_data_delayed_10 <= b18_data_delayed_9; + b18_data_delayed_11 <= b18_data_delayed_10; + b18_data_delayed_12 <= b18_data_delayed_11; + b18_data_delayed_13 <= b18_data_delayed_12; + b18_data_delayed_14 <= b18_data_delayed_13; + b18_data_delayed_15 <= b18_data_delayed_14; + b18_data_delayed_16 <= b18_data_delayed_15; + b18_data_delayed_17 <= b18_data_delayed_16; + b18_data_delayed_18 <= b18_data_delayed_17; + b19_data_delayed_2 <= b19_data_delayed_1; + b19_data_delayed_3 <= b19_data_delayed_2; + b19_data_delayed_4 <= b19_data_delayed_3; + b19_data_delayed_5 <= b19_data_delayed_4; + b19_data_delayed_6 <= b19_data_delayed_5; + b19_data_delayed_7 <= b19_data_delayed_6; + b19_data_delayed_8 <= b19_data_delayed_7; + b19_data_delayed_9 <= b19_data_delayed_8; + b19_data_delayed_10 <= b19_data_delayed_9; + b19_data_delayed_11 <= b19_data_delayed_10; + b19_data_delayed_12 <= b19_data_delayed_11; + b19_data_delayed_13 <= b19_data_delayed_12; + b19_data_delayed_14 <= b19_data_delayed_13; + b19_data_delayed_15 <= b19_data_delayed_14; + b19_data_delayed_16 <= b19_data_delayed_15; + b19_data_delayed_17 <= b19_data_delayed_16; + b19_data_delayed_18 <= b19_data_delayed_17; + b19_data_delayed_19 <= b19_data_delayed_18; + b20_data_delayed_2 <= b20_data_delayed_1; + b20_data_delayed_3 <= b20_data_delayed_2; + b20_data_delayed_4 <= b20_data_delayed_3; + b20_data_delayed_5 <= b20_data_delayed_4; + b20_data_delayed_6 <= b20_data_delayed_5; + b20_data_delayed_7 <= b20_data_delayed_6; + b20_data_delayed_8 <= b20_data_delayed_7; + b20_data_delayed_9 <= b20_data_delayed_8; + b20_data_delayed_10 <= b20_data_delayed_9; + b20_data_delayed_11 <= b20_data_delayed_10; + b20_data_delayed_12 <= b20_data_delayed_11; + b20_data_delayed_13 <= b20_data_delayed_12; + b20_data_delayed_14 <= b20_data_delayed_13; + b20_data_delayed_15 <= b20_data_delayed_14; + b20_data_delayed_16 <= b20_data_delayed_15; + b20_data_delayed_17 <= b20_data_delayed_16; + b20_data_delayed_18 <= b20_data_delayed_17; + b20_data_delayed_19 <= b20_data_delayed_18; + b20_data_delayed_20 <= b20_data_delayed_19; + b21_data_delayed_2 <= b21_data_delayed_1; + b21_data_delayed_3 <= b21_data_delayed_2; + b21_data_delayed_4 <= b21_data_delayed_3; + b21_data_delayed_5 <= b21_data_delayed_4; + b21_data_delayed_6 <= b21_data_delayed_5; + b21_data_delayed_7 <= b21_data_delayed_6; + b21_data_delayed_8 <= b21_data_delayed_7; + b21_data_delayed_9 <= b21_data_delayed_8; + b21_data_delayed_10 <= b21_data_delayed_9; + b21_data_delayed_11 <= b21_data_delayed_10; + b21_data_delayed_12 <= b21_data_delayed_11; + b21_data_delayed_13 <= b21_data_delayed_12; + b21_data_delayed_14 <= b21_data_delayed_13; + b21_data_delayed_15 <= b21_data_delayed_14; + b21_data_delayed_16 <= b21_data_delayed_15; + b21_data_delayed_17 <= b21_data_delayed_16; + b21_data_delayed_18 <= b21_data_delayed_17; + b21_data_delayed_19 <= b21_data_delayed_18; + b21_data_delayed_20 <= b21_data_delayed_19; + b21_data_delayed_21 <= b21_data_delayed_20; + b22_data_delayed_2 <= b22_data_delayed_1; + b22_data_delayed_3 <= b22_data_delayed_2; + b22_data_delayed_4 <= b22_data_delayed_3; + b22_data_delayed_5 <= b22_data_delayed_4; + b22_data_delayed_6 <= b22_data_delayed_5; + b22_data_delayed_7 <= b22_data_delayed_6; + b22_data_delayed_8 <= b22_data_delayed_7; + b22_data_delayed_9 <= b22_data_delayed_8; + b22_data_delayed_10 <= b22_data_delayed_9; + b22_data_delayed_11 <= b22_data_delayed_10; + b22_data_delayed_12 <= b22_data_delayed_11; + b22_data_delayed_13 <= b22_data_delayed_12; + b22_data_delayed_14 <= b22_data_delayed_13; + b22_data_delayed_15 <= b22_data_delayed_14; + b22_data_delayed_16 <= b22_data_delayed_15; + b22_data_delayed_17 <= b22_data_delayed_16; + b22_data_delayed_18 <= b22_data_delayed_17; + b22_data_delayed_19 <= b22_data_delayed_18; + b22_data_delayed_20 <= b22_data_delayed_19; + b22_data_delayed_21 <= b22_data_delayed_20; + b22_data_delayed_22 <= b22_data_delayed_21; + b23_data_delayed_2 <= b23_data_delayed_1; + b23_data_delayed_3 <= b23_data_delayed_2; + b23_data_delayed_4 <= b23_data_delayed_3; + b23_data_delayed_5 <= b23_data_delayed_4; + b23_data_delayed_6 <= b23_data_delayed_5; + b23_data_delayed_7 <= b23_data_delayed_6; + b23_data_delayed_8 <= b23_data_delayed_7; + b23_data_delayed_9 <= b23_data_delayed_8; + b23_data_delayed_10 <= b23_data_delayed_9; + b23_data_delayed_11 <= b23_data_delayed_10; + b23_data_delayed_12 <= b23_data_delayed_11; + b23_data_delayed_13 <= b23_data_delayed_12; + b23_data_delayed_14 <= b23_data_delayed_13; + b23_data_delayed_15 <= b23_data_delayed_14; + b23_data_delayed_16 <= b23_data_delayed_15; + b23_data_delayed_17 <= b23_data_delayed_16; + b23_data_delayed_18 <= b23_data_delayed_17; + b23_data_delayed_19 <= b23_data_delayed_18; + b23_data_delayed_20 <= b23_data_delayed_19; + b23_data_delayed_21 <= b23_data_delayed_20; + b23_data_delayed_22 <= b23_data_delayed_21; + b23_data_delayed_23 <= b23_data_delayed_22; + b24_data_delayed_2 <= b24_data_delayed_1; + b24_data_delayed_3 <= b24_data_delayed_2; + b24_data_delayed_4 <= b24_data_delayed_3; + b24_data_delayed_5 <= b24_data_delayed_4; + b24_data_delayed_6 <= b24_data_delayed_5; + b24_data_delayed_7 <= b24_data_delayed_6; + b24_data_delayed_8 <= b24_data_delayed_7; + b24_data_delayed_9 <= b24_data_delayed_8; + b24_data_delayed_10 <= b24_data_delayed_9; + b24_data_delayed_11 <= b24_data_delayed_10; + b24_data_delayed_12 <= b24_data_delayed_11; + b24_data_delayed_13 <= b24_data_delayed_12; + b24_data_delayed_14 <= b24_data_delayed_13; + b24_data_delayed_15 <= b24_data_delayed_14; + b24_data_delayed_16 <= b24_data_delayed_15; + b24_data_delayed_17 <= b24_data_delayed_16; + b24_data_delayed_18 <= b24_data_delayed_17; + b24_data_delayed_19 <= b24_data_delayed_18; + b24_data_delayed_20 <= b24_data_delayed_19; + b24_data_delayed_21 <= b24_data_delayed_20; + b24_data_delayed_22 <= b24_data_delayed_21; + b24_data_delayed_23 <= b24_data_delayed_22; + b24_data_delayed_24 <= b24_data_delayed_23; + b25_data_delayed_2 <= b25_data_delayed_1; + b25_data_delayed_3 <= b25_data_delayed_2; + b25_data_delayed_4 <= b25_data_delayed_3; + b25_data_delayed_5 <= b25_data_delayed_4; + b25_data_delayed_6 <= b25_data_delayed_5; + b25_data_delayed_7 <= b25_data_delayed_6; + b25_data_delayed_8 <= b25_data_delayed_7; + b25_data_delayed_9 <= b25_data_delayed_8; + b25_data_delayed_10 <= b25_data_delayed_9; + b25_data_delayed_11 <= b25_data_delayed_10; + b25_data_delayed_12 <= b25_data_delayed_11; + b25_data_delayed_13 <= b25_data_delayed_12; + b25_data_delayed_14 <= b25_data_delayed_13; + b25_data_delayed_15 <= b25_data_delayed_14; + b25_data_delayed_16 <= b25_data_delayed_15; + b25_data_delayed_17 <= b25_data_delayed_16; + b25_data_delayed_18 <= b25_data_delayed_17; + b25_data_delayed_19 <= b25_data_delayed_18; + b25_data_delayed_20 <= b25_data_delayed_19; + b25_data_delayed_21 <= b25_data_delayed_20; + b25_data_delayed_22 <= b25_data_delayed_21; + b25_data_delayed_23 <= b25_data_delayed_22; + b25_data_delayed_24 <= b25_data_delayed_23; + b25_data_delayed_25 <= b25_data_delayed_24; + b26_data_delayed_2 <= b26_data_delayed_1; + b26_data_delayed_3 <= b26_data_delayed_2; + b26_data_delayed_4 <= b26_data_delayed_3; + b26_data_delayed_5 <= b26_data_delayed_4; + b26_data_delayed_6 <= b26_data_delayed_5; + b26_data_delayed_7 <= b26_data_delayed_6; + b26_data_delayed_8 <= b26_data_delayed_7; + b26_data_delayed_9 <= b26_data_delayed_8; + b26_data_delayed_10 <= b26_data_delayed_9; + b26_data_delayed_11 <= b26_data_delayed_10; + b26_data_delayed_12 <= b26_data_delayed_11; + b26_data_delayed_13 <= b26_data_delayed_12; + b26_data_delayed_14 <= b26_data_delayed_13; + b26_data_delayed_15 <= b26_data_delayed_14; + b26_data_delayed_16 <= b26_data_delayed_15; + b26_data_delayed_17 <= b26_data_delayed_16; + b26_data_delayed_18 <= b26_data_delayed_17; + b26_data_delayed_19 <= b26_data_delayed_18; + b26_data_delayed_20 <= b26_data_delayed_19; + b26_data_delayed_21 <= b26_data_delayed_20; + b26_data_delayed_22 <= b26_data_delayed_21; + b26_data_delayed_23 <= b26_data_delayed_22; + b26_data_delayed_24 <= b26_data_delayed_23; + b26_data_delayed_25 <= b26_data_delayed_24; + b26_data_delayed_26 <= b26_data_delayed_25; + b27_data_delayed_2 <= b27_data_delayed_1; + b27_data_delayed_3 <= b27_data_delayed_2; + b27_data_delayed_4 <= b27_data_delayed_3; + b27_data_delayed_5 <= b27_data_delayed_4; + b27_data_delayed_6 <= b27_data_delayed_5; + b27_data_delayed_7 <= b27_data_delayed_6; + b27_data_delayed_8 <= b27_data_delayed_7; + b27_data_delayed_9 <= b27_data_delayed_8; + b27_data_delayed_10 <= b27_data_delayed_9; + b27_data_delayed_11 <= b27_data_delayed_10; + b27_data_delayed_12 <= b27_data_delayed_11; + b27_data_delayed_13 <= b27_data_delayed_12; + b27_data_delayed_14 <= b27_data_delayed_13; + b27_data_delayed_15 <= b27_data_delayed_14; + b27_data_delayed_16 <= b27_data_delayed_15; + b27_data_delayed_17 <= b27_data_delayed_16; + b27_data_delayed_18 <= b27_data_delayed_17; + b27_data_delayed_19 <= b27_data_delayed_18; + b27_data_delayed_20 <= b27_data_delayed_19; + b27_data_delayed_21 <= b27_data_delayed_20; + b27_data_delayed_22 <= b27_data_delayed_21; + b27_data_delayed_23 <= b27_data_delayed_22; + b27_data_delayed_24 <= b27_data_delayed_23; + b27_data_delayed_25 <= b27_data_delayed_24; + b27_data_delayed_26 <= b27_data_delayed_25; + b27_data_delayed_27 <= b27_data_delayed_26; + b28_data_delayed_2 <= b28_data_delayed_1; + b28_data_delayed_3 <= b28_data_delayed_2; + b28_data_delayed_4 <= b28_data_delayed_3; + b28_data_delayed_5 <= b28_data_delayed_4; + b28_data_delayed_6 <= b28_data_delayed_5; + b28_data_delayed_7 <= b28_data_delayed_6; + b28_data_delayed_8 <= b28_data_delayed_7; + b28_data_delayed_9 <= b28_data_delayed_8; + b28_data_delayed_10 <= b28_data_delayed_9; + b28_data_delayed_11 <= b28_data_delayed_10; + b28_data_delayed_12 <= b28_data_delayed_11; + b28_data_delayed_13 <= b28_data_delayed_12; + b28_data_delayed_14 <= b28_data_delayed_13; + b28_data_delayed_15 <= b28_data_delayed_14; + b28_data_delayed_16 <= b28_data_delayed_15; + b28_data_delayed_17 <= b28_data_delayed_16; + b28_data_delayed_18 <= b28_data_delayed_17; + b28_data_delayed_19 <= b28_data_delayed_18; + b28_data_delayed_20 <= b28_data_delayed_19; + b28_data_delayed_21 <= b28_data_delayed_20; + b28_data_delayed_22 <= b28_data_delayed_21; + b28_data_delayed_23 <= b28_data_delayed_22; + b28_data_delayed_24 <= b28_data_delayed_23; + b28_data_delayed_25 <= b28_data_delayed_24; + b28_data_delayed_26 <= b28_data_delayed_25; + b28_data_delayed_27 <= b28_data_delayed_26; + b28_data_delayed_28 <= b28_data_delayed_27; + b29_data_delayed_2 <= b29_data_delayed_1; + b29_data_delayed_3 <= b29_data_delayed_2; + b29_data_delayed_4 <= b29_data_delayed_3; + b29_data_delayed_5 <= b29_data_delayed_4; + b29_data_delayed_6 <= b29_data_delayed_5; + b29_data_delayed_7 <= b29_data_delayed_6; + b29_data_delayed_8 <= b29_data_delayed_7; + b29_data_delayed_9 <= b29_data_delayed_8; + b29_data_delayed_10 <= b29_data_delayed_9; + b29_data_delayed_11 <= b29_data_delayed_10; + b29_data_delayed_12 <= b29_data_delayed_11; + b29_data_delayed_13 <= b29_data_delayed_12; + b29_data_delayed_14 <= b29_data_delayed_13; + b29_data_delayed_15 <= b29_data_delayed_14; + b29_data_delayed_16 <= b29_data_delayed_15; + b29_data_delayed_17 <= b29_data_delayed_16; + b29_data_delayed_18 <= b29_data_delayed_17; + b29_data_delayed_19 <= b29_data_delayed_18; + b29_data_delayed_20 <= b29_data_delayed_19; + b29_data_delayed_21 <= b29_data_delayed_20; + b29_data_delayed_22 <= b29_data_delayed_21; + b29_data_delayed_23 <= b29_data_delayed_22; + b29_data_delayed_24 <= b29_data_delayed_23; + b29_data_delayed_25 <= b29_data_delayed_24; + b29_data_delayed_26 <= b29_data_delayed_25; + b29_data_delayed_27 <= b29_data_delayed_26; + b29_data_delayed_28 <= b29_data_delayed_27; + b29_data_delayed_29 <= b29_data_delayed_28; + b30_data_delayed_2 <= b30_data_delayed_1; + b30_data_delayed_3 <= b30_data_delayed_2; + b30_data_delayed_4 <= b30_data_delayed_3; + b30_data_delayed_5 <= b30_data_delayed_4; + b30_data_delayed_6 <= b30_data_delayed_5; + b30_data_delayed_7 <= b30_data_delayed_6; + b30_data_delayed_8 <= b30_data_delayed_7; + b30_data_delayed_9 <= b30_data_delayed_8; + b30_data_delayed_10 <= b30_data_delayed_9; + b30_data_delayed_11 <= b30_data_delayed_10; + b30_data_delayed_12 <= b30_data_delayed_11; + b30_data_delayed_13 <= b30_data_delayed_12; + b30_data_delayed_14 <= b30_data_delayed_13; + b30_data_delayed_15 <= b30_data_delayed_14; + b30_data_delayed_16 <= b30_data_delayed_15; + b30_data_delayed_17 <= b30_data_delayed_16; + b30_data_delayed_18 <= b30_data_delayed_17; + b30_data_delayed_19 <= b30_data_delayed_18; + b30_data_delayed_20 <= b30_data_delayed_19; + b30_data_delayed_21 <= b30_data_delayed_20; + b30_data_delayed_22 <= b30_data_delayed_21; + b30_data_delayed_23 <= b30_data_delayed_22; + b30_data_delayed_24 <= b30_data_delayed_23; + b30_data_delayed_25 <= b30_data_delayed_24; + b30_data_delayed_26 <= b30_data_delayed_25; + b30_data_delayed_27 <= b30_data_delayed_26; + b30_data_delayed_28 <= b30_data_delayed_27; + b30_data_delayed_29 <= b30_data_delayed_28; + b30_data_delayed_30 <= b30_data_delayed_29; + b31_data_delayed_2 <= b31_data_delayed_1; + b31_data_delayed_3 <= b31_data_delayed_2; + b31_data_delayed_4 <= b31_data_delayed_3; + b31_data_delayed_5 <= b31_data_delayed_4; + b31_data_delayed_6 <= b31_data_delayed_5; + b31_data_delayed_7 <= b31_data_delayed_6; + b31_data_delayed_8 <= b31_data_delayed_7; + b31_data_delayed_9 <= b31_data_delayed_8; + b31_data_delayed_10 <= b31_data_delayed_9; + b31_data_delayed_11 <= b31_data_delayed_10; + b31_data_delayed_12 <= b31_data_delayed_11; + b31_data_delayed_13 <= b31_data_delayed_12; + b31_data_delayed_14 <= b31_data_delayed_13; + b31_data_delayed_15 <= b31_data_delayed_14; + b31_data_delayed_16 <= b31_data_delayed_15; + b31_data_delayed_17 <= b31_data_delayed_16; + b31_data_delayed_18 <= b31_data_delayed_17; + b31_data_delayed_19 <= b31_data_delayed_18; + b31_data_delayed_20 <= b31_data_delayed_19; + b31_data_delayed_21 <= b31_data_delayed_20; + b31_data_delayed_22 <= b31_data_delayed_21; + b31_data_delayed_23 <= b31_data_delayed_22; + b31_data_delayed_24 <= b31_data_delayed_23; + b31_data_delayed_25 <= b31_data_delayed_24; + b31_data_delayed_26 <= b31_data_delayed_25; + b31_data_delayed_27 <= b31_data_delayed_26; + b31_data_delayed_28 <= b31_data_delayed_27; + b31_data_delayed_29 <= b31_data_delayed_28; + b31_data_delayed_30 <= b31_data_delayed_29; + b31_data_delayed_31 <= b31_data_delayed_30; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +a16, +a17, +a18, +a19, +a20, +a21, +a22, +a23, +a24, +a25, +a26, +a27, +a28, +a29, +a30, +a31, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +b16, +b17, +b18, +b19, +b20, +b21, +b22, +b23, +b24, +b25, +b26, +b27, +b28, +b29, +b30, +b31, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] a16; +input [`DWIDTH-1:0] a17; +input [`DWIDTH-1:0] a18; +input [`DWIDTH-1:0] a19; +input [`DWIDTH-1:0] a20; +input [`DWIDTH-1:0] a21; +input [`DWIDTH-1:0] a22; +input [`DWIDTH-1:0] a23; +input [`DWIDTH-1:0] a24; +input [`DWIDTH-1:0] a25; +input [`DWIDTH-1:0] a26; +input [`DWIDTH-1:0] a27; +input [`DWIDTH-1:0] a28; +input [`DWIDTH-1:0] a29; +input [`DWIDTH-1:0] a30; +input [`DWIDTH-1:0] a31; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] b16; +input [`DWIDTH-1:0] b17; +input [`DWIDTH-1:0] b18; +input [`DWIDTH-1:0] b19; +input [`DWIDTH-1:0] b20; +input [`DWIDTH-1:0] b21; +input [`DWIDTH-1:0] b22; +input [`DWIDTH-1:0] b23; +input [`DWIDTH-1:0] b24; +input [`DWIDTH-1:0] b25; +input [`DWIDTH-1:0] b26; +input [`DWIDTH-1:0] b27; +input [`DWIDTH-1:0] b28; +input [`DWIDTH-1:0] b29; +input [`DWIDTH-1:0] b30; +input [`DWIDTH-1:0] b31; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC0_16; +output [`DWIDTH-1:0] matrixC0_17; +output [`DWIDTH-1:0] matrixC0_18; +output [`DWIDTH-1:0] matrixC0_19; +output [`DWIDTH-1:0] matrixC0_20; +output [`DWIDTH-1:0] matrixC0_21; +output [`DWIDTH-1:0] matrixC0_22; +output [`DWIDTH-1:0] matrixC0_23; +output [`DWIDTH-1:0] matrixC0_24; +output [`DWIDTH-1:0] matrixC0_25; +output [`DWIDTH-1:0] matrixC0_26; +output [`DWIDTH-1:0] matrixC0_27; +output [`DWIDTH-1:0] matrixC0_28; +output [`DWIDTH-1:0] matrixC0_29; +output [`DWIDTH-1:0] matrixC0_30; +output [`DWIDTH-1:0] matrixC0_31; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC1_16; +output [`DWIDTH-1:0] matrixC1_17; +output [`DWIDTH-1:0] matrixC1_18; +output [`DWIDTH-1:0] matrixC1_19; +output [`DWIDTH-1:0] matrixC1_20; +output [`DWIDTH-1:0] matrixC1_21; +output [`DWIDTH-1:0] matrixC1_22; +output [`DWIDTH-1:0] matrixC1_23; +output [`DWIDTH-1:0] matrixC1_24; +output [`DWIDTH-1:0] matrixC1_25; +output [`DWIDTH-1:0] matrixC1_26; +output [`DWIDTH-1:0] matrixC1_27; +output [`DWIDTH-1:0] matrixC1_28; +output [`DWIDTH-1:0] matrixC1_29; +output [`DWIDTH-1:0] matrixC1_30; +output [`DWIDTH-1:0] matrixC1_31; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC2_16; +output [`DWIDTH-1:0] matrixC2_17; +output [`DWIDTH-1:0] matrixC2_18; +output [`DWIDTH-1:0] matrixC2_19; +output [`DWIDTH-1:0] matrixC2_20; +output [`DWIDTH-1:0] matrixC2_21; +output [`DWIDTH-1:0] matrixC2_22; +output [`DWIDTH-1:0] matrixC2_23; +output [`DWIDTH-1:0] matrixC2_24; +output [`DWIDTH-1:0] matrixC2_25; +output [`DWIDTH-1:0] matrixC2_26; +output [`DWIDTH-1:0] matrixC2_27; +output [`DWIDTH-1:0] matrixC2_28; +output [`DWIDTH-1:0] matrixC2_29; +output [`DWIDTH-1:0] matrixC2_30; +output [`DWIDTH-1:0] matrixC2_31; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC3_16; +output [`DWIDTH-1:0] matrixC3_17; +output [`DWIDTH-1:0] matrixC3_18; +output [`DWIDTH-1:0] matrixC3_19; +output [`DWIDTH-1:0] matrixC3_20; +output [`DWIDTH-1:0] matrixC3_21; +output [`DWIDTH-1:0] matrixC3_22; +output [`DWIDTH-1:0] matrixC3_23; +output [`DWIDTH-1:0] matrixC3_24; +output [`DWIDTH-1:0] matrixC3_25; +output [`DWIDTH-1:0] matrixC3_26; +output [`DWIDTH-1:0] matrixC3_27; +output [`DWIDTH-1:0] matrixC3_28; +output [`DWIDTH-1:0] matrixC3_29; +output [`DWIDTH-1:0] matrixC3_30; +output [`DWIDTH-1:0] matrixC3_31; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC4_16; +output [`DWIDTH-1:0] matrixC4_17; +output [`DWIDTH-1:0] matrixC4_18; +output [`DWIDTH-1:0] matrixC4_19; +output [`DWIDTH-1:0] matrixC4_20; +output [`DWIDTH-1:0] matrixC4_21; +output [`DWIDTH-1:0] matrixC4_22; +output [`DWIDTH-1:0] matrixC4_23; +output [`DWIDTH-1:0] matrixC4_24; +output [`DWIDTH-1:0] matrixC4_25; +output [`DWIDTH-1:0] matrixC4_26; +output [`DWIDTH-1:0] matrixC4_27; +output [`DWIDTH-1:0] matrixC4_28; +output [`DWIDTH-1:0] matrixC4_29; +output [`DWIDTH-1:0] matrixC4_30; +output [`DWIDTH-1:0] matrixC4_31; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC5_16; +output [`DWIDTH-1:0] matrixC5_17; +output [`DWIDTH-1:0] matrixC5_18; +output [`DWIDTH-1:0] matrixC5_19; +output [`DWIDTH-1:0] matrixC5_20; +output [`DWIDTH-1:0] matrixC5_21; +output [`DWIDTH-1:0] matrixC5_22; +output [`DWIDTH-1:0] matrixC5_23; +output [`DWIDTH-1:0] matrixC5_24; +output [`DWIDTH-1:0] matrixC5_25; +output [`DWIDTH-1:0] matrixC5_26; +output [`DWIDTH-1:0] matrixC5_27; +output [`DWIDTH-1:0] matrixC5_28; +output [`DWIDTH-1:0] matrixC5_29; +output [`DWIDTH-1:0] matrixC5_30; +output [`DWIDTH-1:0] matrixC5_31; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC6_16; +output [`DWIDTH-1:0] matrixC6_17; +output [`DWIDTH-1:0] matrixC6_18; +output [`DWIDTH-1:0] matrixC6_19; +output [`DWIDTH-1:0] matrixC6_20; +output [`DWIDTH-1:0] matrixC6_21; +output [`DWIDTH-1:0] matrixC6_22; +output [`DWIDTH-1:0] matrixC6_23; +output [`DWIDTH-1:0] matrixC6_24; +output [`DWIDTH-1:0] matrixC6_25; +output [`DWIDTH-1:0] matrixC6_26; +output [`DWIDTH-1:0] matrixC6_27; +output [`DWIDTH-1:0] matrixC6_28; +output [`DWIDTH-1:0] matrixC6_29; +output [`DWIDTH-1:0] matrixC6_30; +output [`DWIDTH-1:0] matrixC6_31; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC7_16; +output [`DWIDTH-1:0] matrixC7_17; +output [`DWIDTH-1:0] matrixC7_18; +output [`DWIDTH-1:0] matrixC7_19; +output [`DWIDTH-1:0] matrixC7_20; +output [`DWIDTH-1:0] matrixC7_21; +output [`DWIDTH-1:0] matrixC7_22; +output [`DWIDTH-1:0] matrixC7_23; +output [`DWIDTH-1:0] matrixC7_24; +output [`DWIDTH-1:0] matrixC7_25; +output [`DWIDTH-1:0] matrixC7_26; +output [`DWIDTH-1:0] matrixC7_27; +output [`DWIDTH-1:0] matrixC7_28; +output [`DWIDTH-1:0] matrixC7_29; +output [`DWIDTH-1:0] matrixC7_30; +output [`DWIDTH-1:0] matrixC7_31; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC8_16; +output [`DWIDTH-1:0] matrixC8_17; +output [`DWIDTH-1:0] matrixC8_18; +output [`DWIDTH-1:0] matrixC8_19; +output [`DWIDTH-1:0] matrixC8_20; +output [`DWIDTH-1:0] matrixC8_21; +output [`DWIDTH-1:0] matrixC8_22; +output [`DWIDTH-1:0] matrixC8_23; +output [`DWIDTH-1:0] matrixC8_24; +output [`DWIDTH-1:0] matrixC8_25; +output [`DWIDTH-1:0] matrixC8_26; +output [`DWIDTH-1:0] matrixC8_27; +output [`DWIDTH-1:0] matrixC8_28; +output [`DWIDTH-1:0] matrixC8_29; +output [`DWIDTH-1:0] matrixC8_30; +output [`DWIDTH-1:0] matrixC8_31; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC9_16; +output [`DWIDTH-1:0] matrixC9_17; +output [`DWIDTH-1:0] matrixC9_18; +output [`DWIDTH-1:0] matrixC9_19; +output [`DWIDTH-1:0] matrixC9_20; +output [`DWIDTH-1:0] matrixC9_21; +output [`DWIDTH-1:0] matrixC9_22; +output [`DWIDTH-1:0] matrixC9_23; +output [`DWIDTH-1:0] matrixC9_24; +output [`DWIDTH-1:0] matrixC9_25; +output [`DWIDTH-1:0] matrixC9_26; +output [`DWIDTH-1:0] matrixC9_27; +output [`DWIDTH-1:0] matrixC9_28; +output [`DWIDTH-1:0] matrixC9_29; +output [`DWIDTH-1:0] matrixC9_30; +output [`DWIDTH-1:0] matrixC9_31; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC10_16; +output [`DWIDTH-1:0] matrixC10_17; +output [`DWIDTH-1:0] matrixC10_18; +output [`DWIDTH-1:0] matrixC10_19; +output [`DWIDTH-1:0] matrixC10_20; +output [`DWIDTH-1:0] matrixC10_21; +output [`DWIDTH-1:0] matrixC10_22; +output [`DWIDTH-1:0] matrixC10_23; +output [`DWIDTH-1:0] matrixC10_24; +output [`DWIDTH-1:0] matrixC10_25; +output [`DWIDTH-1:0] matrixC10_26; +output [`DWIDTH-1:0] matrixC10_27; +output [`DWIDTH-1:0] matrixC10_28; +output [`DWIDTH-1:0] matrixC10_29; +output [`DWIDTH-1:0] matrixC10_30; +output [`DWIDTH-1:0] matrixC10_31; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC11_16; +output [`DWIDTH-1:0] matrixC11_17; +output [`DWIDTH-1:0] matrixC11_18; +output [`DWIDTH-1:0] matrixC11_19; +output [`DWIDTH-1:0] matrixC11_20; +output [`DWIDTH-1:0] matrixC11_21; +output [`DWIDTH-1:0] matrixC11_22; +output [`DWIDTH-1:0] matrixC11_23; +output [`DWIDTH-1:0] matrixC11_24; +output [`DWIDTH-1:0] matrixC11_25; +output [`DWIDTH-1:0] matrixC11_26; +output [`DWIDTH-1:0] matrixC11_27; +output [`DWIDTH-1:0] matrixC11_28; +output [`DWIDTH-1:0] matrixC11_29; +output [`DWIDTH-1:0] matrixC11_30; +output [`DWIDTH-1:0] matrixC11_31; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC12_16; +output [`DWIDTH-1:0] matrixC12_17; +output [`DWIDTH-1:0] matrixC12_18; +output [`DWIDTH-1:0] matrixC12_19; +output [`DWIDTH-1:0] matrixC12_20; +output [`DWIDTH-1:0] matrixC12_21; +output [`DWIDTH-1:0] matrixC12_22; +output [`DWIDTH-1:0] matrixC12_23; +output [`DWIDTH-1:0] matrixC12_24; +output [`DWIDTH-1:0] matrixC12_25; +output [`DWIDTH-1:0] matrixC12_26; +output [`DWIDTH-1:0] matrixC12_27; +output [`DWIDTH-1:0] matrixC12_28; +output [`DWIDTH-1:0] matrixC12_29; +output [`DWIDTH-1:0] matrixC12_30; +output [`DWIDTH-1:0] matrixC12_31; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC13_16; +output [`DWIDTH-1:0] matrixC13_17; +output [`DWIDTH-1:0] matrixC13_18; +output [`DWIDTH-1:0] matrixC13_19; +output [`DWIDTH-1:0] matrixC13_20; +output [`DWIDTH-1:0] matrixC13_21; +output [`DWIDTH-1:0] matrixC13_22; +output [`DWIDTH-1:0] matrixC13_23; +output [`DWIDTH-1:0] matrixC13_24; +output [`DWIDTH-1:0] matrixC13_25; +output [`DWIDTH-1:0] matrixC13_26; +output [`DWIDTH-1:0] matrixC13_27; +output [`DWIDTH-1:0] matrixC13_28; +output [`DWIDTH-1:0] matrixC13_29; +output [`DWIDTH-1:0] matrixC13_30; +output [`DWIDTH-1:0] matrixC13_31; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC14_16; +output [`DWIDTH-1:0] matrixC14_17; +output [`DWIDTH-1:0] matrixC14_18; +output [`DWIDTH-1:0] matrixC14_19; +output [`DWIDTH-1:0] matrixC14_20; +output [`DWIDTH-1:0] matrixC14_21; +output [`DWIDTH-1:0] matrixC14_22; +output [`DWIDTH-1:0] matrixC14_23; +output [`DWIDTH-1:0] matrixC14_24; +output [`DWIDTH-1:0] matrixC14_25; +output [`DWIDTH-1:0] matrixC14_26; +output [`DWIDTH-1:0] matrixC14_27; +output [`DWIDTH-1:0] matrixC14_28; +output [`DWIDTH-1:0] matrixC14_29; +output [`DWIDTH-1:0] matrixC14_30; +output [`DWIDTH-1:0] matrixC14_31; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`DWIDTH-1:0] matrixC15_16; +output [`DWIDTH-1:0] matrixC15_17; +output [`DWIDTH-1:0] matrixC15_18; +output [`DWIDTH-1:0] matrixC15_19; +output [`DWIDTH-1:0] matrixC15_20; +output [`DWIDTH-1:0] matrixC15_21; +output [`DWIDTH-1:0] matrixC15_22; +output [`DWIDTH-1:0] matrixC15_23; +output [`DWIDTH-1:0] matrixC15_24; +output [`DWIDTH-1:0] matrixC15_25; +output [`DWIDTH-1:0] matrixC15_26; +output [`DWIDTH-1:0] matrixC15_27; +output [`DWIDTH-1:0] matrixC15_28; +output [`DWIDTH-1:0] matrixC15_29; +output [`DWIDTH-1:0] matrixC15_30; +output [`DWIDTH-1:0] matrixC15_31; +output [`DWIDTH-1:0] matrixC16_0; +output [`DWIDTH-1:0] matrixC16_1; +output [`DWIDTH-1:0] matrixC16_2; +output [`DWIDTH-1:0] matrixC16_3; +output [`DWIDTH-1:0] matrixC16_4; +output [`DWIDTH-1:0] matrixC16_5; +output [`DWIDTH-1:0] matrixC16_6; +output [`DWIDTH-1:0] matrixC16_7; +output [`DWIDTH-1:0] matrixC16_8; +output [`DWIDTH-1:0] matrixC16_9; +output [`DWIDTH-1:0] matrixC16_10; +output [`DWIDTH-1:0] matrixC16_11; +output [`DWIDTH-1:0] matrixC16_12; +output [`DWIDTH-1:0] matrixC16_13; +output [`DWIDTH-1:0] matrixC16_14; +output [`DWIDTH-1:0] matrixC16_15; +output [`DWIDTH-1:0] matrixC16_16; +output [`DWIDTH-1:0] matrixC16_17; +output [`DWIDTH-1:0] matrixC16_18; +output [`DWIDTH-1:0] matrixC16_19; +output [`DWIDTH-1:0] matrixC16_20; +output [`DWIDTH-1:0] matrixC16_21; +output [`DWIDTH-1:0] matrixC16_22; +output [`DWIDTH-1:0] matrixC16_23; +output [`DWIDTH-1:0] matrixC16_24; +output [`DWIDTH-1:0] matrixC16_25; +output [`DWIDTH-1:0] matrixC16_26; +output [`DWIDTH-1:0] matrixC16_27; +output [`DWIDTH-1:0] matrixC16_28; +output [`DWIDTH-1:0] matrixC16_29; +output [`DWIDTH-1:0] matrixC16_30; +output [`DWIDTH-1:0] matrixC16_31; +output [`DWIDTH-1:0] matrixC17_0; +output [`DWIDTH-1:0] matrixC17_1; +output [`DWIDTH-1:0] matrixC17_2; +output [`DWIDTH-1:0] matrixC17_3; +output [`DWIDTH-1:0] matrixC17_4; +output [`DWIDTH-1:0] matrixC17_5; +output [`DWIDTH-1:0] matrixC17_6; +output [`DWIDTH-1:0] matrixC17_7; +output [`DWIDTH-1:0] matrixC17_8; +output [`DWIDTH-1:0] matrixC17_9; +output [`DWIDTH-1:0] matrixC17_10; +output [`DWIDTH-1:0] matrixC17_11; +output [`DWIDTH-1:0] matrixC17_12; +output [`DWIDTH-1:0] matrixC17_13; +output [`DWIDTH-1:0] matrixC17_14; +output [`DWIDTH-1:0] matrixC17_15; +output [`DWIDTH-1:0] matrixC17_16; +output [`DWIDTH-1:0] matrixC17_17; +output [`DWIDTH-1:0] matrixC17_18; +output [`DWIDTH-1:0] matrixC17_19; +output [`DWIDTH-1:0] matrixC17_20; +output [`DWIDTH-1:0] matrixC17_21; +output [`DWIDTH-1:0] matrixC17_22; +output [`DWIDTH-1:0] matrixC17_23; +output [`DWIDTH-1:0] matrixC17_24; +output [`DWIDTH-1:0] matrixC17_25; +output [`DWIDTH-1:0] matrixC17_26; +output [`DWIDTH-1:0] matrixC17_27; +output [`DWIDTH-1:0] matrixC17_28; +output [`DWIDTH-1:0] matrixC17_29; +output [`DWIDTH-1:0] matrixC17_30; +output [`DWIDTH-1:0] matrixC17_31; +output [`DWIDTH-1:0] matrixC18_0; +output [`DWIDTH-1:0] matrixC18_1; +output [`DWIDTH-1:0] matrixC18_2; +output [`DWIDTH-1:0] matrixC18_3; +output [`DWIDTH-1:0] matrixC18_4; +output [`DWIDTH-1:0] matrixC18_5; +output [`DWIDTH-1:0] matrixC18_6; +output [`DWIDTH-1:0] matrixC18_7; +output [`DWIDTH-1:0] matrixC18_8; +output [`DWIDTH-1:0] matrixC18_9; +output [`DWIDTH-1:0] matrixC18_10; +output [`DWIDTH-1:0] matrixC18_11; +output [`DWIDTH-1:0] matrixC18_12; +output [`DWIDTH-1:0] matrixC18_13; +output [`DWIDTH-1:0] matrixC18_14; +output [`DWIDTH-1:0] matrixC18_15; +output [`DWIDTH-1:0] matrixC18_16; +output [`DWIDTH-1:0] matrixC18_17; +output [`DWIDTH-1:0] matrixC18_18; +output [`DWIDTH-1:0] matrixC18_19; +output [`DWIDTH-1:0] matrixC18_20; +output [`DWIDTH-1:0] matrixC18_21; +output [`DWIDTH-1:0] matrixC18_22; +output [`DWIDTH-1:0] matrixC18_23; +output [`DWIDTH-1:0] matrixC18_24; +output [`DWIDTH-1:0] matrixC18_25; +output [`DWIDTH-1:0] matrixC18_26; +output [`DWIDTH-1:0] matrixC18_27; +output [`DWIDTH-1:0] matrixC18_28; +output [`DWIDTH-1:0] matrixC18_29; +output [`DWIDTH-1:0] matrixC18_30; +output [`DWIDTH-1:0] matrixC18_31; +output [`DWIDTH-1:0] matrixC19_0; +output [`DWIDTH-1:0] matrixC19_1; +output [`DWIDTH-1:0] matrixC19_2; +output [`DWIDTH-1:0] matrixC19_3; +output [`DWIDTH-1:0] matrixC19_4; +output [`DWIDTH-1:0] matrixC19_5; +output [`DWIDTH-1:0] matrixC19_6; +output [`DWIDTH-1:0] matrixC19_7; +output [`DWIDTH-1:0] matrixC19_8; +output [`DWIDTH-1:0] matrixC19_9; +output [`DWIDTH-1:0] matrixC19_10; +output [`DWIDTH-1:0] matrixC19_11; +output [`DWIDTH-1:0] matrixC19_12; +output [`DWIDTH-1:0] matrixC19_13; +output [`DWIDTH-1:0] matrixC19_14; +output [`DWIDTH-1:0] matrixC19_15; +output [`DWIDTH-1:0] matrixC19_16; +output [`DWIDTH-1:0] matrixC19_17; +output [`DWIDTH-1:0] matrixC19_18; +output [`DWIDTH-1:0] matrixC19_19; +output [`DWIDTH-1:0] matrixC19_20; +output [`DWIDTH-1:0] matrixC19_21; +output [`DWIDTH-1:0] matrixC19_22; +output [`DWIDTH-1:0] matrixC19_23; +output [`DWIDTH-1:0] matrixC19_24; +output [`DWIDTH-1:0] matrixC19_25; +output [`DWIDTH-1:0] matrixC19_26; +output [`DWIDTH-1:0] matrixC19_27; +output [`DWIDTH-1:0] matrixC19_28; +output [`DWIDTH-1:0] matrixC19_29; +output [`DWIDTH-1:0] matrixC19_30; +output [`DWIDTH-1:0] matrixC19_31; +output [`DWIDTH-1:0] matrixC20_0; +output [`DWIDTH-1:0] matrixC20_1; +output [`DWIDTH-1:0] matrixC20_2; +output [`DWIDTH-1:0] matrixC20_3; +output [`DWIDTH-1:0] matrixC20_4; +output [`DWIDTH-1:0] matrixC20_5; +output [`DWIDTH-1:0] matrixC20_6; +output [`DWIDTH-1:0] matrixC20_7; +output [`DWIDTH-1:0] matrixC20_8; +output [`DWIDTH-1:0] matrixC20_9; +output [`DWIDTH-1:0] matrixC20_10; +output [`DWIDTH-1:0] matrixC20_11; +output [`DWIDTH-1:0] matrixC20_12; +output [`DWIDTH-1:0] matrixC20_13; +output [`DWIDTH-1:0] matrixC20_14; +output [`DWIDTH-1:0] matrixC20_15; +output [`DWIDTH-1:0] matrixC20_16; +output [`DWIDTH-1:0] matrixC20_17; +output [`DWIDTH-1:0] matrixC20_18; +output [`DWIDTH-1:0] matrixC20_19; +output [`DWIDTH-1:0] matrixC20_20; +output [`DWIDTH-1:0] matrixC20_21; +output [`DWIDTH-1:0] matrixC20_22; +output [`DWIDTH-1:0] matrixC20_23; +output [`DWIDTH-1:0] matrixC20_24; +output [`DWIDTH-1:0] matrixC20_25; +output [`DWIDTH-1:0] matrixC20_26; +output [`DWIDTH-1:0] matrixC20_27; +output [`DWIDTH-1:0] matrixC20_28; +output [`DWIDTH-1:0] matrixC20_29; +output [`DWIDTH-1:0] matrixC20_30; +output [`DWIDTH-1:0] matrixC20_31; +output [`DWIDTH-1:0] matrixC21_0; +output [`DWIDTH-1:0] matrixC21_1; +output [`DWIDTH-1:0] matrixC21_2; +output [`DWIDTH-1:0] matrixC21_3; +output [`DWIDTH-1:0] matrixC21_4; +output [`DWIDTH-1:0] matrixC21_5; +output [`DWIDTH-1:0] matrixC21_6; +output [`DWIDTH-1:0] matrixC21_7; +output [`DWIDTH-1:0] matrixC21_8; +output [`DWIDTH-1:0] matrixC21_9; +output [`DWIDTH-1:0] matrixC21_10; +output [`DWIDTH-1:0] matrixC21_11; +output [`DWIDTH-1:0] matrixC21_12; +output [`DWIDTH-1:0] matrixC21_13; +output [`DWIDTH-1:0] matrixC21_14; +output [`DWIDTH-1:0] matrixC21_15; +output [`DWIDTH-1:0] matrixC21_16; +output [`DWIDTH-1:0] matrixC21_17; +output [`DWIDTH-1:0] matrixC21_18; +output [`DWIDTH-1:0] matrixC21_19; +output [`DWIDTH-1:0] matrixC21_20; +output [`DWIDTH-1:0] matrixC21_21; +output [`DWIDTH-1:0] matrixC21_22; +output [`DWIDTH-1:0] matrixC21_23; +output [`DWIDTH-1:0] matrixC21_24; +output [`DWIDTH-1:0] matrixC21_25; +output [`DWIDTH-1:0] matrixC21_26; +output [`DWIDTH-1:0] matrixC21_27; +output [`DWIDTH-1:0] matrixC21_28; +output [`DWIDTH-1:0] matrixC21_29; +output [`DWIDTH-1:0] matrixC21_30; +output [`DWIDTH-1:0] matrixC21_31; +output [`DWIDTH-1:0] matrixC22_0; +output [`DWIDTH-1:0] matrixC22_1; +output [`DWIDTH-1:0] matrixC22_2; +output [`DWIDTH-1:0] matrixC22_3; +output [`DWIDTH-1:0] matrixC22_4; +output [`DWIDTH-1:0] matrixC22_5; +output [`DWIDTH-1:0] matrixC22_6; +output [`DWIDTH-1:0] matrixC22_7; +output [`DWIDTH-1:0] matrixC22_8; +output [`DWIDTH-1:0] matrixC22_9; +output [`DWIDTH-1:0] matrixC22_10; +output [`DWIDTH-1:0] matrixC22_11; +output [`DWIDTH-1:0] matrixC22_12; +output [`DWIDTH-1:0] matrixC22_13; +output [`DWIDTH-1:0] matrixC22_14; +output [`DWIDTH-1:0] matrixC22_15; +output [`DWIDTH-1:0] matrixC22_16; +output [`DWIDTH-1:0] matrixC22_17; +output [`DWIDTH-1:0] matrixC22_18; +output [`DWIDTH-1:0] matrixC22_19; +output [`DWIDTH-1:0] matrixC22_20; +output [`DWIDTH-1:0] matrixC22_21; +output [`DWIDTH-1:0] matrixC22_22; +output [`DWIDTH-1:0] matrixC22_23; +output [`DWIDTH-1:0] matrixC22_24; +output [`DWIDTH-1:0] matrixC22_25; +output [`DWIDTH-1:0] matrixC22_26; +output [`DWIDTH-1:0] matrixC22_27; +output [`DWIDTH-1:0] matrixC22_28; +output [`DWIDTH-1:0] matrixC22_29; +output [`DWIDTH-1:0] matrixC22_30; +output [`DWIDTH-1:0] matrixC22_31; +output [`DWIDTH-1:0] matrixC23_0; +output [`DWIDTH-1:0] matrixC23_1; +output [`DWIDTH-1:0] matrixC23_2; +output [`DWIDTH-1:0] matrixC23_3; +output [`DWIDTH-1:0] matrixC23_4; +output [`DWIDTH-1:0] matrixC23_5; +output [`DWIDTH-1:0] matrixC23_6; +output [`DWIDTH-1:0] matrixC23_7; +output [`DWIDTH-1:0] matrixC23_8; +output [`DWIDTH-1:0] matrixC23_9; +output [`DWIDTH-1:0] matrixC23_10; +output [`DWIDTH-1:0] matrixC23_11; +output [`DWIDTH-1:0] matrixC23_12; +output [`DWIDTH-1:0] matrixC23_13; +output [`DWIDTH-1:0] matrixC23_14; +output [`DWIDTH-1:0] matrixC23_15; +output [`DWIDTH-1:0] matrixC23_16; +output [`DWIDTH-1:0] matrixC23_17; +output [`DWIDTH-1:0] matrixC23_18; +output [`DWIDTH-1:0] matrixC23_19; +output [`DWIDTH-1:0] matrixC23_20; +output [`DWIDTH-1:0] matrixC23_21; +output [`DWIDTH-1:0] matrixC23_22; +output [`DWIDTH-1:0] matrixC23_23; +output [`DWIDTH-1:0] matrixC23_24; +output [`DWIDTH-1:0] matrixC23_25; +output [`DWIDTH-1:0] matrixC23_26; +output [`DWIDTH-1:0] matrixC23_27; +output [`DWIDTH-1:0] matrixC23_28; +output [`DWIDTH-1:0] matrixC23_29; +output [`DWIDTH-1:0] matrixC23_30; +output [`DWIDTH-1:0] matrixC23_31; +output [`DWIDTH-1:0] matrixC24_0; +output [`DWIDTH-1:0] matrixC24_1; +output [`DWIDTH-1:0] matrixC24_2; +output [`DWIDTH-1:0] matrixC24_3; +output [`DWIDTH-1:0] matrixC24_4; +output [`DWIDTH-1:0] matrixC24_5; +output [`DWIDTH-1:0] matrixC24_6; +output [`DWIDTH-1:0] matrixC24_7; +output [`DWIDTH-1:0] matrixC24_8; +output [`DWIDTH-1:0] matrixC24_9; +output [`DWIDTH-1:0] matrixC24_10; +output [`DWIDTH-1:0] matrixC24_11; +output [`DWIDTH-1:0] matrixC24_12; +output [`DWIDTH-1:0] matrixC24_13; +output [`DWIDTH-1:0] matrixC24_14; +output [`DWIDTH-1:0] matrixC24_15; +output [`DWIDTH-1:0] matrixC24_16; +output [`DWIDTH-1:0] matrixC24_17; +output [`DWIDTH-1:0] matrixC24_18; +output [`DWIDTH-1:0] matrixC24_19; +output [`DWIDTH-1:0] matrixC24_20; +output [`DWIDTH-1:0] matrixC24_21; +output [`DWIDTH-1:0] matrixC24_22; +output [`DWIDTH-1:0] matrixC24_23; +output [`DWIDTH-1:0] matrixC24_24; +output [`DWIDTH-1:0] matrixC24_25; +output [`DWIDTH-1:0] matrixC24_26; +output [`DWIDTH-1:0] matrixC24_27; +output [`DWIDTH-1:0] matrixC24_28; +output [`DWIDTH-1:0] matrixC24_29; +output [`DWIDTH-1:0] matrixC24_30; +output [`DWIDTH-1:0] matrixC24_31; +output [`DWIDTH-1:0] matrixC25_0; +output [`DWIDTH-1:0] matrixC25_1; +output [`DWIDTH-1:0] matrixC25_2; +output [`DWIDTH-1:0] matrixC25_3; +output [`DWIDTH-1:0] matrixC25_4; +output [`DWIDTH-1:0] matrixC25_5; +output [`DWIDTH-1:0] matrixC25_6; +output [`DWIDTH-1:0] matrixC25_7; +output [`DWIDTH-1:0] matrixC25_8; +output [`DWIDTH-1:0] matrixC25_9; +output [`DWIDTH-1:0] matrixC25_10; +output [`DWIDTH-1:0] matrixC25_11; +output [`DWIDTH-1:0] matrixC25_12; +output [`DWIDTH-1:0] matrixC25_13; +output [`DWIDTH-1:0] matrixC25_14; +output [`DWIDTH-1:0] matrixC25_15; +output [`DWIDTH-1:0] matrixC25_16; +output [`DWIDTH-1:0] matrixC25_17; +output [`DWIDTH-1:0] matrixC25_18; +output [`DWIDTH-1:0] matrixC25_19; +output [`DWIDTH-1:0] matrixC25_20; +output [`DWIDTH-1:0] matrixC25_21; +output [`DWIDTH-1:0] matrixC25_22; +output [`DWIDTH-1:0] matrixC25_23; +output [`DWIDTH-1:0] matrixC25_24; +output [`DWIDTH-1:0] matrixC25_25; +output [`DWIDTH-1:0] matrixC25_26; +output [`DWIDTH-1:0] matrixC25_27; +output [`DWIDTH-1:0] matrixC25_28; +output [`DWIDTH-1:0] matrixC25_29; +output [`DWIDTH-1:0] matrixC25_30; +output [`DWIDTH-1:0] matrixC25_31; +output [`DWIDTH-1:0] matrixC26_0; +output [`DWIDTH-1:0] matrixC26_1; +output [`DWIDTH-1:0] matrixC26_2; +output [`DWIDTH-1:0] matrixC26_3; +output [`DWIDTH-1:0] matrixC26_4; +output [`DWIDTH-1:0] matrixC26_5; +output [`DWIDTH-1:0] matrixC26_6; +output [`DWIDTH-1:0] matrixC26_7; +output [`DWIDTH-1:0] matrixC26_8; +output [`DWIDTH-1:0] matrixC26_9; +output [`DWIDTH-1:0] matrixC26_10; +output [`DWIDTH-1:0] matrixC26_11; +output [`DWIDTH-1:0] matrixC26_12; +output [`DWIDTH-1:0] matrixC26_13; +output [`DWIDTH-1:0] matrixC26_14; +output [`DWIDTH-1:0] matrixC26_15; +output [`DWIDTH-1:0] matrixC26_16; +output [`DWIDTH-1:0] matrixC26_17; +output [`DWIDTH-1:0] matrixC26_18; +output [`DWIDTH-1:0] matrixC26_19; +output [`DWIDTH-1:0] matrixC26_20; +output [`DWIDTH-1:0] matrixC26_21; +output [`DWIDTH-1:0] matrixC26_22; +output [`DWIDTH-1:0] matrixC26_23; +output [`DWIDTH-1:0] matrixC26_24; +output [`DWIDTH-1:0] matrixC26_25; +output [`DWIDTH-1:0] matrixC26_26; +output [`DWIDTH-1:0] matrixC26_27; +output [`DWIDTH-1:0] matrixC26_28; +output [`DWIDTH-1:0] matrixC26_29; +output [`DWIDTH-1:0] matrixC26_30; +output [`DWIDTH-1:0] matrixC26_31; +output [`DWIDTH-1:0] matrixC27_0; +output [`DWIDTH-1:0] matrixC27_1; +output [`DWIDTH-1:0] matrixC27_2; +output [`DWIDTH-1:0] matrixC27_3; +output [`DWIDTH-1:0] matrixC27_4; +output [`DWIDTH-1:0] matrixC27_5; +output [`DWIDTH-1:0] matrixC27_6; +output [`DWIDTH-1:0] matrixC27_7; +output [`DWIDTH-1:0] matrixC27_8; +output [`DWIDTH-1:0] matrixC27_9; +output [`DWIDTH-1:0] matrixC27_10; +output [`DWIDTH-1:0] matrixC27_11; +output [`DWIDTH-1:0] matrixC27_12; +output [`DWIDTH-1:0] matrixC27_13; +output [`DWIDTH-1:0] matrixC27_14; +output [`DWIDTH-1:0] matrixC27_15; +output [`DWIDTH-1:0] matrixC27_16; +output [`DWIDTH-1:0] matrixC27_17; +output [`DWIDTH-1:0] matrixC27_18; +output [`DWIDTH-1:0] matrixC27_19; +output [`DWIDTH-1:0] matrixC27_20; +output [`DWIDTH-1:0] matrixC27_21; +output [`DWIDTH-1:0] matrixC27_22; +output [`DWIDTH-1:0] matrixC27_23; +output [`DWIDTH-1:0] matrixC27_24; +output [`DWIDTH-1:0] matrixC27_25; +output [`DWIDTH-1:0] matrixC27_26; +output [`DWIDTH-1:0] matrixC27_27; +output [`DWIDTH-1:0] matrixC27_28; +output [`DWIDTH-1:0] matrixC27_29; +output [`DWIDTH-1:0] matrixC27_30; +output [`DWIDTH-1:0] matrixC27_31; +output [`DWIDTH-1:0] matrixC28_0; +output [`DWIDTH-1:0] matrixC28_1; +output [`DWIDTH-1:0] matrixC28_2; +output [`DWIDTH-1:0] matrixC28_3; +output [`DWIDTH-1:0] matrixC28_4; +output [`DWIDTH-1:0] matrixC28_5; +output [`DWIDTH-1:0] matrixC28_6; +output [`DWIDTH-1:0] matrixC28_7; +output [`DWIDTH-1:0] matrixC28_8; +output [`DWIDTH-1:0] matrixC28_9; +output [`DWIDTH-1:0] matrixC28_10; +output [`DWIDTH-1:0] matrixC28_11; +output [`DWIDTH-1:0] matrixC28_12; +output [`DWIDTH-1:0] matrixC28_13; +output [`DWIDTH-1:0] matrixC28_14; +output [`DWIDTH-1:0] matrixC28_15; +output [`DWIDTH-1:0] matrixC28_16; +output [`DWIDTH-1:0] matrixC28_17; +output [`DWIDTH-1:0] matrixC28_18; +output [`DWIDTH-1:0] matrixC28_19; +output [`DWIDTH-1:0] matrixC28_20; +output [`DWIDTH-1:0] matrixC28_21; +output [`DWIDTH-1:0] matrixC28_22; +output [`DWIDTH-1:0] matrixC28_23; +output [`DWIDTH-1:0] matrixC28_24; +output [`DWIDTH-1:0] matrixC28_25; +output [`DWIDTH-1:0] matrixC28_26; +output [`DWIDTH-1:0] matrixC28_27; +output [`DWIDTH-1:0] matrixC28_28; +output [`DWIDTH-1:0] matrixC28_29; +output [`DWIDTH-1:0] matrixC28_30; +output [`DWIDTH-1:0] matrixC28_31; +output [`DWIDTH-1:0] matrixC29_0; +output [`DWIDTH-1:0] matrixC29_1; +output [`DWIDTH-1:0] matrixC29_2; +output [`DWIDTH-1:0] matrixC29_3; +output [`DWIDTH-1:0] matrixC29_4; +output [`DWIDTH-1:0] matrixC29_5; +output [`DWIDTH-1:0] matrixC29_6; +output [`DWIDTH-1:0] matrixC29_7; +output [`DWIDTH-1:0] matrixC29_8; +output [`DWIDTH-1:0] matrixC29_9; +output [`DWIDTH-1:0] matrixC29_10; +output [`DWIDTH-1:0] matrixC29_11; +output [`DWIDTH-1:0] matrixC29_12; +output [`DWIDTH-1:0] matrixC29_13; +output [`DWIDTH-1:0] matrixC29_14; +output [`DWIDTH-1:0] matrixC29_15; +output [`DWIDTH-1:0] matrixC29_16; +output [`DWIDTH-1:0] matrixC29_17; +output [`DWIDTH-1:0] matrixC29_18; +output [`DWIDTH-1:0] matrixC29_19; +output [`DWIDTH-1:0] matrixC29_20; +output [`DWIDTH-1:0] matrixC29_21; +output [`DWIDTH-1:0] matrixC29_22; +output [`DWIDTH-1:0] matrixC29_23; +output [`DWIDTH-1:0] matrixC29_24; +output [`DWIDTH-1:0] matrixC29_25; +output [`DWIDTH-1:0] matrixC29_26; +output [`DWIDTH-1:0] matrixC29_27; +output [`DWIDTH-1:0] matrixC29_28; +output [`DWIDTH-1:0] matrixC29_29; +output [`DWIDTH-1:0] matrixC29_30; +output [`DWIDTH-1:0] matrixC29_31; +output [`DWIDTH-1:0] matrixC30_0; +output [`DWIDTH-1:0] matrixC30_1; +output [`DWIDTH-1:0] matrixC30_2; +output [`DWIDTH-1:0] matrixC30_3; +output [`DWIDTH-1:0] matrixC30_4; +output [`DWIDTH-1:0] matrixC30_5; +output [`DWIDTH-1:0] matrixC30_6; +output [`DWIDTH-1:0] matrixC30_7; +output [`DWIDTH-1:0] matrixC30_8; +output [`DWIDTH-1:0] matrixC30_9; +output [`DWIDTH-1:0] matrixC30_10; +output [`DWIDTH-1:0] matrixC30_11; +output [`DWIDTH-1:0] matrixC30_12; +output [`DWIDTH-1:0] matrixC30_13; +output [`DWIDTH-1:0] matrixC30_14; +output [`DWIDTH-1:0] matrixC30_15; +output [`DWIDTH-1:0] matrixC30_16; +output [`DWIDTH-1:0] matrixC30_17; +output [`DWIDTH-1:0] matrixC30_18; +output [`DWIDTH-1:0] matrixC30_19; +output [`DWIDTH-1:0] matrixC30_20; +output [`DWIDTH-1:0] matrixC30_21; +output [`DWIDTH-1:0] matrixC30_22; +output [`DWIDTH-1:0] matrixC30_23; +output [`DWIDTH-1:0] matrixC30_24; +output [`DWIDTH-1:0] matrixC30_25; +output [`DWIDTH-1:0] matrixC30_26; +output [`DWIDTH-1:0] matrixC30_27; +output [`DWIDTH-1:0] matrixC30_28; +output [`DWIDTH-1:0] matrixC30_29; +output [`DWIDTH-1:0] matrixC30_30; +output [`DWIDTH-1:0] matrixC30_31; +output [`DWIDTH-1:0] matrixC31_0; +output [`DWIDTH-1:0] matrixC31_1; +output [`DWIDTH-1:0] matrixC31_2; +output [`DWIDTH-1:0] matrixC31_3; +output [`DWIDTH-1:0] matrixC31_4; +output [`DWIDTH-1:0] matrixC31_5; +output [`DWIDTH-1:0] matrixC31_6; +output [`DWIDTH-1:0] matrixC31_7; +output [`DWIDTH-1:0] matrixC31_8; +output [`DWIDTH-1:0] matrixC31_9; +output [`DWIDTH-1:0] matrixC31_10; +output [`DWIDTH-1:0] matrixC31_11; +output [`DWIDTH-1:0] matrixC31_12; +output [`DWIDTH-1:0] matrixC31_13; +output [`DWIDTH-1:0] matrixC31_14; +output [`DWIDTH-1:0] matrixC31_15; +output [`DWIDTH-1:0] matrixC31_16; +output [`DWIDTH-1:0] matrixC31_17; +output [`DWIDTH-1:0] matrixC31_18; +output [`DWIDTH-1:0] matrixC31_19; +output [`DWIDTH-1:0] matrixC31_20; +output [`DWIDTH-1:0] matrixC31_21; +output [`DWIDTH-1:0] matrixC31_22; +output [`DWIDTH-1:0] matrixC31_23; +output [`DWIDTH-1:0] matrixC31_24; +output [`DWIDTH-1:0] matrixC31_25; +output [`DWIDTH-1:0] matrixC31_26; +output [`DWIDTH-1:0] matrixC31_27; +output [`DWIDTH-1:0] matrixC31_28; +output [`DWIDTH-1:0] matrixC31_29; +output [`DWIDTH-1:0] matrixC31_30; +output [`DWIDTH-1:0] matrixC31_31; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16, a0_16to0_17, a0_17to0_18, a0_18to0_19, a0_19to0_20, a0_20to0_21, a0_21to0_22, a0_22to0_23, a0_23to0_24, a0_24to0_25, a0_25to0_26, a0_26to0_27, a0_27to0_28, a0_28to0_29, a0_29to0_30, a0_30to0_31, a0_31to0_32; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16, a1_16to1_17, a1_17to1_18, a1_18to1_19, a1_19to1_20, a1_20to1_21, a1_21to1_22, a1_22to1_23, a1_23to1_24, a1_24to1_25, a1_25to1_26, a1_26to1_27, a1_27to1_28, a1_28to1_29, a1_29to1_30, a1_30to1_31, a1_31to1_32; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16, a2_16to2_17, a2_17to2_18, a2_18to2_19, a2_19to2_20, a2_20to2_21, a2_21to2_22, a2_22to2_23, a2_23to2_24, a2_24to2_25, a2_25to2_26, a2_26to2_27, a2_27to2_28, a2_28to2_29, a2_29to2_30, a2_30to2_31, a2_31to2_32; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16, a3_16to3_17, a3_17to3_18, a3_18to3_19, a3_19to3_20, a3_20to3_21, a3_21to3_22, a3_22to3_23, a3_23to3_24, a3_24to3_25, a3_25to3_26, a3_26to3_27, a3_27to3_28, a3_28to3_29, a3_29to3_30, a3_30to3_31, a3_31to3_32; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16, a4_16to4_17, a4_17to4_18, a4_18to4_19, a4_19to4_20, a4_20to4_21, a4_21to4_22, a4_22to4_23, a4_23to4_24, a4_24to4_25, a4_25to4_26, a4_26to4_27, a4_27to4_28, a4_28to4_29, a4_29to4_30, a4_30to4_31, a4_31to4_32; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16, a5_16to5_17, a5_17to5_18, a5_18to5_19, a5_19to5_20, a5_20to5_21, a5_21to5_22, a5_22to5_23, a5_23to5_24, a5_24to5_25, a5_25to5_26, a5_26to5_27, a5_27to5_28, a5_28to5_29, a5_29to5_30, a5_30to5_31, a5_31to5_32; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16, a6_16to6_17, a6_17to6_18, a6_18to6_19, a6_19to6_20, a6_20to6_21, a6_21to6_22, a6_22to6_23, a6_23to6_24, a6_24to6_25, a6_25to6_26, a6_26to6_27, a6_27to6_28, a6_28to6_29, a6_29to6_30, a6_30to6_31, a6_31to6_32; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16, a7_16to7_17, a7_17to7_18, a7_18to7_19, a7_19to7_20, a7_20to7_21, a7_21to7_22, a7_22to7_23, a7_23to7_24, a7_24to7_25, a7_25to7_26, a7_26to7_27, a7_27to7_28, a7_28to7_29, a7_29to7_30, a7_30to7_31, a7_31to7_32; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16, a8_16to8_17, a8_17to8_18, a8_18to8_19, a8_19to8_20, a8_20to8_21, a8_21to8_22, a8_22to8_23, a8_23to8_24, a8_24to8_25, a8_25to8_26, a8_26to8_27, a8_27to8_28, a8_28to8_29, a8_29to8_30, a8_30to8_31, a8_31to8_32; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16, a9_16to9_17, a9_17to9_18, a9_18to9_19, a9_19to9_20, a9_20to9_21, a9_21to9_22, a9_22to9_23, a9_23to9_24, a9_24to9_25, a9_25to9_26, a9_26to9_27, a9_27to9_28, a9_28to9_29, a9_29to9_30, a9_30to9_31, a9_31to9_32; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16, a10_16to10_17, a10_17to10_18, a10_18to10_19, a10_19to10_20, a10_20to10_21, a10_21to10_22, a10_22to10_23, a10_23to10_24, a10_24to10_25, a10_25to10_26, a10_26to10_27, a10_27to10_28, a10_28to10_29, a10_29to10_30, a10_30to10_31, a10_31to10_32; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16, a11_16to11_17, a11_17to11_18, a11_18to11_19, a11_19to11_20, a11_20to11_21, a11_21to11_22, a11_22to11_23, a11_23to11_24, a11_24to11_25, a11_25to11_26, a11_26to11_27, a11_27to11_28, a11_28to11_29, a11_29to11_30, a11_30to11_31, a11_31to11_32; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16, a12_16to12_17, a12_17to12_18, a12_18to12_19, a12_19to12_20, a12_20to12_21, a12_21to12_22, a12_22to12_23, a12_23to12_24, a12_24to12_25, a12_25to12_26, a12_26to12_27, a12_27to12_28, a12_28to12_29, a12_29to12_30, a12_30to12_31, a12_31to12_32; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16, a13_16to13_17, a13_17to13_18, a13_18to13_19, a13_19to13_20, a13_20to13_21, a13_21to13_22, a13_22to13_23, a13_23to13_24, a13_24to13_25, a13_25to13_26, a13_26to13_27, a13_27to13_28, a13_28to13_29, a13_29to13_30, a13_30to13_31, a13_31to13_32; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16, a14_16to14_17, a14_17to14_18, a14_18to14_19, a14_19to14_20, a14_20to14_21, a14_21to14_22, a14_22to14_23, a14_23to14_24, a14_24to14_25, a14_25to14_26, a14_26to14_27, a14_27to14_28, a14_28to14_29, a14_29to14_30, a14_30to14_31, a14_31to14_32; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16, a15_16to15_17, a15_17to15_18, a15_18to15_19, a15_19to15_20, a15_20to15_21, a15_21to15_22, a15_22to15_23, a15_23to15_24, a15_24to15_25, a15_25to15_26, a15_26to15_27, a15_27to15_28, a15_28to15_29, a15_29to15_30, a15_30to15_31, a15_31to15_32; +wire [`DWIDTH-1:0] a16_0to16_1, a16_1to16_2, a16_2to16_3, a16_3to16_4, a16_4to16_5, a16_5to16_6, a16_6to16_7, a16_7to16_8, a16_8to16_9, a16_9to16_10, a16_10to16_11, a16_11to16_12, a16_12to16_13, a16_13to16_14, a16_14to16_15, a16_15to16_16, a16_16to16_17, a16_17to16_18, a16_18to16_19, a16_19to16_20, a16_20to16_21, a16_21to16_22, a16_22to16_23, a16_23to16_24, a16_24to16_25, a16_25to16_26, a16_26to16_27, a16_27to16_28, a16_28to16_29, a16_29to16_30, a16_30to16_31, a16_31to16_32; +wire [`DWIDTH-1:0] a17_0to17_1, a17_1to17_2, a17_2to17_3, a17_3to17_4, a17_4to17_5, a17_5to17_6, a17_6to17_7, a17_7to17_8, a17_8to17_9, a17_9to17_10, a17_10to17_11, a17_11to17_12, a17_12to17_13, a17_13to17_14, a17_14to17_15, a17_15to17_16, a17_16to17_17, a17_17to17_18, a17_18to17_19, a17_19to17_20, a17_20to17_21, a17_21to17_22, a17_22to17_23, a17_23to17_24, a17_24to17_25, a17_25to17_26, a17_26to17_27, a17_27to17_28, a17_28to17_29, a17_29to17_30, a17_30to17_31, a17_31to17_32; +wire [`DWIDTH-1:0] a18_0to18_1, a18_1to18_2, a18_2to18_3, a18_3to18_4, a18_4to18_5, a18_5to18_6, a18_6to18_7, a18_7to18_8, a18_8to18_9, a18_9to18_10, a18_10to18_11, a18_11to18_12, a18_12to18_13, a18_13to18_14, a18_14to18_15, a18_15to18_16, a18_16to18_17, a18_17to18_18, a18_18to18_19, a18_19to18_20, a18_20to18_21, a18_21to18_22, a18_22to18_23, a18_23to18_24, a18_24to18_25, a18_25to18_26, a18_26to18_27, a18_27to18_28, a18_28to18_29, a18_29to18_30, a18_30to18_31, a18_31to18_32; +wire [`DWIDTH-1:0] a19_0to19_1, a19_1to19_2, a19_2to19_3, a19_3to19_4, a19_4to19_5, a19_5to19_6, a19_6to19_7, a19_7to19_8, a19_8to19_9, a19_9to19_10, a19_10to19_11, a19_11to19_12, a19_12to19_13, a19_13to19_14, a19_14to19_15, a19_15to19_16, a19_16to19_17, a19_17to19_18, a19_18to19_19, a19_19to19_20, a19_20to19_21, a19_21to19_22, a19_22to19_23, a19_23to19_24, a19_24to19_25, a19_25to19_26, a19_26to19_27, a19_27to19_28, a19_28to19_29, a19_29to19_30, a19_30to19_31, a19_31to19_32; +wire [`DWIDTH-1:0] a20_0to20_1, a20_1to20_2, a20_2to20_3, a20_3to20_4, a20_4to20_5, a20_5to20_6, a20_6to20_7, a20_7to20_8, a20_8to20_9, a20_9to20_10, a20_10to20_11, a20_11to20_12, a20_12to20_13, a20_13to20_14, a20_14to20_15, a20_15to20_16, a20_16to20_17, a20_17to20_18, a20_18to20_19, a20_19to20_20, a20_20to20_21, a20_21to20_22, a20_22to20_23, a20_23to20_24, a20_24to20_25, a20_25to20_26, a20_26to20_27, a20_27to20_28, a20_28to20_29, a20_29to20_30, a20_30to20_31, a20_31to20_32; +wire [`DWIDTH-1:0] a21_0to21_1, a21_1to21_2, a21_2to21_3, a21_3to21_4, a21_4to21_5, a21_5to21_6, a21_6to21_7, a21_7to21_8, a21_8to21_9, a21_9to21_10, a21_10to21_11, a21_11to21_12, a21_12to21_13, a21_13to21_14, a21_14to21_15, a21_15to21_16, a21_16to21_17, a21_17to21_18, a21_18to21_19, a21_19to21_20, a21_20to21_21, a21_21to21_22, a21_22to21_23, a21_23to21_24, a21_24to21_25, a21_25to21_26, a21_26to21_27, a21_27to21_28, a21_28to21_29, a21_29to21_30, a21_30to21_31, a21_31to21_32; +wire [`DWIDTH-1:0] a22_0to22_1, a22_1to22_2, a22_2to22_3, a22_3to22_4, a22_4to22_5, a22_5to22_6, a22_6to22_7, a22_7to22_8, a22_8to22_9, a22_9to22_10, a22_10to22_11, a22_11to22_12, a22_12to22_13, a22_13to22_14, a22_14to22_15, a22_15to22_16, a22_16to22_17, a22_17to22_18, a22_18to22_19, a22_19to22_20, a22_20to22_21, a22_21to22_22, a22_22to22_23, a22_23to22_24, a22_24to22_25, a22_25to22_26, a22_26to22_27, a22_27to22_28, a22_28to22_29, a22_29to22_30, a22_30to22_31, a22_31to22_32; +wire [`DWIDTH-1:0] a23_0to23_1, a23_1to23_2, a23_2to23_3, a23_3to23_4, a23_4to23_5, a23_5to23_6, a23_6to23_7, a23_7to23_8, a23_8to23_9, a23_9to23_10, a23_10to23_11, a23_11to23_12, a23_12to23_13, a23_13to23_14, a23_14to23_15, a23_15to23_16, a23_16to23_17, a23_17to23_18, a23_18to23_19, a23_19to23_20, a23_20to23_21, a23_21to23_22, a23_22to23_23, a23_23to23_24, a23_24to23_25, a23_25to23_26, a23_26to23_27, a23_27to23_28, a23_28to23_29, a23_29to23_30, a23_30to23_31, a23_31to23_32; +wire [`DWIDTH-1:0] a24_0to24_1, a24_1to24_2, a24_2to24_3, a24_3to24_4, a24_4to24_5, a24_5to24_6, a24_6to24_7, a24_7to24_8, a24_8to24_9, a24_9to24_10, a24_10to24_11, a24_11to24_12, a24_12to24_13, a24_13to24_14, a24_14to24_15, a24_15to24_16, a24_16to24_17, a24_17to24_18, a24_18to24_19, a24_19to24_20, a24_20to24_21, a24_21to24_22, a24_22to24_23, a24_23to24_24, a24_24to24_25, a24_25to24_26, a24_26to24_27, a24_27to24_28, a24_28to24_29, a24_29to24_30, a24_30to24_31, a24_31to24_32; +wire [`DWIDTH-1:0] a25_0to25_1, a25_1to25_2, a25_2to25_3, a25_3to25_4, a25_4to25_5, a25_5to25_6, a25_6to25_7, a25_7to25_8, a25_8to25_9, a25_9to25_10, a25_10to25_11, a25_11to25_12, a25_12to25_13, a25_13to25_14, a25_14to25_15, a25_15to25_16, a25_16to25_17, a25_17to25_18, a25_18to25_19, a25_19to25_20, a25_20to25_21, a25_21to25_22, a25_22to25_23, a25_23to25_24, a25_24to25_25, a25_25to25_26, a25_26to25_27, a25_27to25_28, a25_28to25_29, a25_29to25_30, a25_30to25_31, a25_31to25_32; +wire [`DWIDTH-1:0] a26_0to26_1, a26_1to26_2, a26_2to26_3, a26_3to26_4, a26_4to26_5, a26_5to26_6, a26_6to26_7, a26_7to26_8, a26_8to26_9, a26_9to26_10, a26_10to26_11, a26_11to26_12, a26_12to26_13, a26_13to26_14, a26_14to26_15, a26_15to26_16, a26_16to26_17, a26_17to26_18, a26_18to26_19, a26_19to26_20, a26_20to26_21, a26_21to26_22, a26_22to26_23, a26_23to26_24, a26_24to26_25, a26_25to26_26, a26_26to26_27, a26_27to26_28, a26_28to26_29, a26_29to26_30, a26_30to26_31, a26_31to26_32; +wire [`DWIDTH-1:0] a27_0to27_1, a27_1to27_2, a27_2to27_3, a27_3to27_4, a27_4to27_5, a27_5to27_6, a27_6to27_7, a27_7to27_8, a27_8to27_9, a27_9to27_10, a27_10to27_11, a27_11to27_12, a27_12to27_13, a27_13to27_14, a27_14to27_15, a27_15to27_16, a27_16to27_17, a27_17to27_18, a27_18to27_19, a27_19to27_20, a27_20to27_21, a27_21to27_22, a27_22to27_23, a27_23to27_24, a27_24to27_25, a27_25to27_26, a27_26to27_27, a27_27to27_28, a27_28to27_29, a27_29to27_30, a27_30to27_31, a27_31to27_32; +wire [`DWIDTH-1:0] a28_0to28_1, a28_1to28_2, a28_2to28_3, a28_3to28_4, a28_4to28_5, a28_5to28_6, a28_6to28_7, a28_7to28_8, a28_8to28_9, a28_9to28_10, a28_10to28_11, a28_11to28_12, a28_12to28_13, a28_13to28_14, a28_14to28_15, a28_15to28_16, a28_16to28_17, a28_17to28_18, a28_18to28_19, a28_19to28_20, a28_20to28_21, a28_21to28_22, a28_22to28_23, a28_23to28_24, a28_24to28_25, a28_25to28_26, a28_26to28_27, a28_27to28_28, a28_28to28_29, a28_29to28_30, a28_30to28_31, a28_31to28_32; +wire [`DWIDTH-1:0] a29_0to29_1, a29_1to29_2, a29_2to29_3, a29_3to29_4, a29_4to29_5, a29_5to29_6, a29_6to29_7, a29_7to29_8, a29_8to29_9, a29_9to29_10, a29_10to29_11, a29_11to29_12, a29_12to29_13, a29_13to29_14, a29_14to29_15, a29_15to29_16, a29_16to29_17, a29_17to29_18, a29_18to29_19, a29_19to29_20, a29_20to29_21, a29_21to29_22, a29_22to29_23, a29_23to29_24, a29_24to29_25, a29_25to29_26, a29_26to29_27, a29_27to29_28, a29_28to29_29, a29_29to29_30, a29_30to29_31, a29_31to29_32; +wire [`DWIDTH-1:0] a30_0to30_1, a30_1to30_2, a30_2to30_3, a30_3to30_4, a30_4to30_5, a30_5to30_6, a30_6to30_7, a30_7to30_8, a30_8to30_9, a30_9to30_10, a30_10to30_11, a30_11to30_12, a30_12to30_13, a30_13to30_14, a30_14to30_15, a30_15to30_16, a30_16to30_17, a30_17to30_18, a30_18to30_19, a30_19to30_20, a30_20to30_21, a30_21to30_22, a30_22to30_23, a30_23to30_24, a30_24to30_25, a30_25to30_26, a30_26to30_27, a30_27to30_28, a30_28to30_29, a30_29to30_30, a30_30to30_31, a30_31to30_32; +wire [`DWIDTH-1:0] a31_0to31_1, a31_1to31_2, a31_2to31_3, a31_3to31_4, a31_4to31_5, a31_5to31_6, a31_6to31_7, a31_7to31_8, a31_8to31_9, a31_9to31_10, a31_10to31_11, a31_11to31_12, a31_12to31_13, a31_13to31_14, a31_14to31_15, a31_15to31_16, a31_16to31_17, a31_17to31_18, a31_18to31_19, a31_19to31_20, a31_20to31_21, a31_21to31_22, a31_22to31_23, a31_23to31_24, a31_24to31_25, a31_25to31_26, a31_26to31_27, a31_27to31_28, a31_28to31_29, a31_29to31_30, a31_30to31_31, a31_31to31_32; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0, b16_0to17_0, b17_0to18_0, b18_0to19_0, b19_0to20_0, b20_0to21_0, b21_0to22_0, b22_0to23_0, b23_0to24_0, b24_0to25_0, b25_0to26_0, b26_0to27_0, b27_0to28_0, b28_0to29_0, b29_0to30_0, b30_0to31_0, b31_0to32_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1, b16_1to17_1, b17_1to18_1, b18_1to19_1, b19_1to20_1, b20_1to21_1, b21_1to22_1, b22_1to23_1, b23_1to24_1, b24_1to25_1, b25_1to26_1, b26_1to27_1, b27_1to28_1, b28_1to29_1, b29_1to30_1, b30_1to31_1, b31_1to32_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2, b16_2to17_2, b17_2to18_2, b18_2to19_2, b19_2to20_2, b20_2to21_2, b21_2to22_2, b22_2to23_2, b23_2to24_2, b24_2to25_2, b25_2to26_2, b26_2to27_2, b27_2to28_2, b28_2to29_2, b29_2to30_2, b30_2to31_2, b31_2to32_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3, b16_3to17_3, b17_3to18_3, b18_3to19_3, b19_3to20_3, b20_3to21_3, b21_3to22_3, b22_3to23_3, b23_3to24_3, b24_3to25_3, b25_3to26_3, b26_3to27_3, b27_3to28_3, b28_3to29_3, b29_3to30_3, b30_3to31_3, b31_3to32_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4, b16_4to17_4, b17_4to18_4, b18_4to19_4, b19_4to20_4, b20_4to21_4, b21_4to22_4, b22_4to23_4, b23_4to24_4, b24_4to25_4, b25_4to26_4, b26_4to27_4, b27_4to28_4, b28_4to29_4, b29_4to30_4, b30_4to31_4, b31_4to32_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5, b16_5to17_5, b17_5to18_5, b18_5to19_5, b19_5to20_5, b20_5to21_5, b21_5to22_5, b22_5to23_5, b23_5to24_5, b24_5to25_5, b25_5to26_5, b26_5to27_5, b27_5to28_5, b28_5to29_5, b29_5to30_5, b30_5to31_5, b31_5to32_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6, b16_6to17_6, b17_6to18_6, b18_6to19_6, b19_6to20_6, b20_6to21_6, b21_6to22_6, b22_6to23_6, b23_6to24_6, b24_6to25_6, b25_6to26_6, b26_6to27_6, b27_6to28_6, b28_6to29_6, b29_6to30_6, b30_6to31_6, b31_6to32_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7, b16_7to17_7, b17_7to18_7, b18_7to19_7, b19_7to20_7, b20_7to21_7, b21_7to22_7, b22_7to23_7, b23_7to24_7, b24_7to25_7, b25_7to26_7, b26_7to27_7, b27_7to28_7, b28_7to29_7, b29_7to30_7, b30_7to31_7, b31_7to32_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8, b16_8to17_8, b17_8to18_8, b18_8to19_8, b19_8to20_8, b20_8to21_8, b21_8to22_8, b22_8to23_8, b23_8to24_8, b24_8to25_8, b25_8to26_8, b26_8to27_8, b27_8to28_8, b28_8to29_8, b29_8to30_8, b30_8to31_8, b31_8to32_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9, b16_9to17_9, b17_9to18_9, b18_9to19_9, b19_9to20_9, b20_9to21_9, b21_9to22_9, b22_9to23_9, b23_9to24_9, b24_9to25_9, b25_9to26_9, b26_9to27_9, b27_9to28_9, b28_9to29_9, b29_9to30_9, b30_9to31_9, b31_9to32_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10, b16_10to17_10, b17_10to18_10, b18_10to19_10, b19_10to20_10, b20_10to21_10, b21_10to22_10, b22_10to23_10, b23_10to24_10, b24_10to25_10, b25_10to26_10, b26_10to27_10, b27_10to28_10, b28_10to29_10, b29_10to30_10, b30_10to31_10, b31_10to32_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11, b16_11to17_11, b17_11to18_11, b18_11to19_11, b19_11to20_11, b20_11to21_11, b21_11to22_11, b22_11to23_11, b23_11to24_11, b24_11to25_11, b25_11to26_11, b26_11to27_11, b27_11to28_11, b28_11to29_11, b29_11to30_11, b30_11to31_11, b31_11to32_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12, b16_12to17_12, b17_12to18_12, b18_12to19_12, b19_12to20_12, b20_12to21_12, b21_12to22_12, b22_12to23_12, b23_12to24_12, b24_12to25_12, b25_12to26_12, b26_12to27_12, b27_12to28_12, b28_12to29_12, b29_12to30_12, b30_12to31_12, b31_12to32_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13, b16_13to17_13, b17_13to18_13, b18_13to19_13, b19_13to20_13, b20_13to21_13, b21_13to22_13, b22_13to23_13, b23_13to24_13, b24_13to25_13, b25_13to26_13, b26_13to27_13, b27_13to28_13, b28_13to29_13, b29_13to30_13, b30_13to31_13, b31_13to32_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14, b16_14to17_14, b17_14to18_14, b18_14to19_14, b19_14to20_14, b20_14to21_14, b21_14to22_14, b22_14to23_14, b23_14to24_14, b24_14to25_14, b25_14to26_14, b26_14to27_14, b27_14to28_14, b28_14to29_14, b29_14to30_14, b30_14to31_14, b31_14to32_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15, b16_15to17_15, b17_15to18_15, b18_15to19_15, b19_15to20_15, b20_15to21_15, b21_15to22_15, b22_15to23_15, b23_15to24_15, b24_15to25_15, b25_15to26_15, b26_15to27_15, b27_15to28_15, b28_15to29_15, b29_15to30_15, b30_15to31_15, b31_15to32_15; +wire [`DWIDTH-1:0] b0_16to1_16, b1_16to2_16, b2_16to3_16, b3_16to4_16, b4_16to5_16, b5_16to6_16, b6_16to7_16, b7_16to8_16, b8_16to9_16, b9_16to10_16, b10_16to11_16, b11_16to12_16, b12_16to13_16, b13_16to14_16, b14_16to15_16, b15_16to16_16, b16_16to17_16, b17_16to18_16, b18_16to19_16, b19_16to20_16, b20_16to21_16, b21_16to22_16, b22_16to23_16, b23_16to24_16, b24_16to25_16, b25_16to26_16, b26_16to27_16, b27_16to28_16, b28_16to29_16, b29_16to30_16, b30_16to31_16, b31_16to32_16; +wire [`DWIDTH-1:0] b0_17to1_17, b1_17to2_17, b2_17to3_17, b3_17to4_17, b4_17to5_17, b5_17to6_17, b6_17to7_17, b7_17to8_17, b8_17to9_17, b9_17to10_17, b10_17to11_17, b11_17to12_17, b12_17to13_17, b13_17to14_17, b14_17to15_17, b15_17to16_17, b16_17to17_17, b17_17to18_17, b18_17to19_17, b19_17to20_17, b20_17to21_17, b21_17to22_17, b22_17to23_17, b23_17to24_17, b24_17to25_17, b25_17to26_17, b26_17to27_17, b27_17to28_17, b28_17to29_17, b29_17to30_17, b30_17to31_17, b31_17to32_17; +wire [`DWIDTH-1:0] b0_18to1_18, b1_18to2_18, b2_18to3_18, b3_18to4_18, b4_18to5_18, b5_18to6_18, b6_18to7_18, b7_18to8_18, b8_18to9_18, b9_18to10_18, b10_18to11_18, b11_18to12_18, b12_18to13_18, b13_18to14_18, b14_18to15_18, b15_18to16_18, b16_18to17_18, b17_18to18_18, b18_18to19_18, b19_18to20_18, b20_18to21_18, b21_18to22_18, b22_18to23_18, b23_18to24_18, b24_18to25_18, b25_18to26_18, b26_18to27_18, b27_18to28_18, b28_18to29_18, b29_18to30_18, b30_18to31_18, b31_18to32_18; +wire [`DWIDTH-1:0] b0_19to1_19, b1_19to2_19, b2_19to3_19, b3_19to4_19, b4_19to5_19, b5_19to6_19, b6_19to7_19, b7_19to8_19, b8_19to9_19, b9_19to10_19, b10_19to11_19, b11_19to12_19, b12_19to13_19, b13_19to14_19, b14_19to15_19, b15_19to16_19, b16_19to17_19, b17_19to18_19, b18_19to19_19, b19_19to20_19, b20_19to21_19, b21_19to22_19, b22_19to23_19, b23_19to24_19, b24_19to25_19, b25_19to26_19, b26_19to27_19, b27_19to28_19, b28_19to29_19, b29_19to30_19, b30_19to31_19, b31_19to32_19; +wire [`DWIDTH-1:0] b0_20to1_20, b1_20to2_20, b2_20to3_20, b3_20to4_20, b4_20to5_20, b5_20to6_20, b6_20to7_20, b7_20to8_20, b8_20to9_20, b9_20to10_20, b10_20to11_20, b11_20to12_20, b12_20to13_20, b13_20to14_20, b14_20to15_20, b15_20to16_20, b16_20to17_20, b17_20to18_20, b18_20to19_20, b19_20to20_20, b20_20to21_20, b21_20to22_20, b22_20to23_20, b23_20to24_20, b24_20to25_20, b25_20to26_20, b26_20to27_20, b27_20to28_20, b28_20to29_20, b29_20to30_20, b30_20to31_20, b31_20to32_20; +wire [`DWIDTH-1:0] b0_21to1_21, b1_21to2_21, b2_21to3_21, b3_21to4_21, b4_21to5_21, b5_21to6_21, b6_21to7_21, b7_21to8_21, b8_21to9_21, b9_21to10_21, b10_21to11_21, b11_21to12_21, b12_21to13_21, b13_21to14_21, b14_21to15_21, b15_21to16_21, b16_21to17_21, b17_21to18_21, b18_21to19_21, b19_21to20_21, b20_21to21_21, b21_21to22_21, b22_21to23_21, b23_21to24_21, b24_21to25_21, b25_21to26_21, b26_21to27_21, b27_21to28_21, b28_21to29_21, b29_21to30_21, b30_21to31_21, b31_21to32_21; +wire [`DWIDTH-1:0] b0_22to1_22, b1_22to2_22, b2_22to3_22, b3_22to4_22, b4_22to5_22, b5_22to6_22, b6_22to7_22, b7_22to8_22, b8_22to9_22, b9_22to10_22, b10_22to11_22, b11_22to12_22, b12_22to13_22, b13_22to14_22, b14_22to15_22, b15_22to16_22, b16_22to17_22, b17_22to18_22, b18_22to19_22, b19_22to20_22, b20_22to21_22, b21_22to22_22, b22_22to23_22, b23_22to24_22, b24_22to25_22, b25_22to26_22, b26_22to27_22, b27_22to28_22, b28_22to29_22, b29_22to30_22, b30_22to31_22, b31_22to32_22; +wire [`DWIDTH-1:0] b0_23to1_23, b1_23to2_23, b2_23to3_23, b3_23to4_23, b4_23to5_23, b5_23to6_23, b6_23to7_23, b7_23to8_23, b8_23to9_23, b9_23to10_23, b10_23to11_23, b11_23to12_23, b12_23to13_23, b13_23to14_23, b14_23to15_23, b15_23to16_23, b16_23to17_23, b17_23to18_23, b18_23to19_23, b19_23to20_23, b20_23to21_23, b21_23to22_23, b22_23to23_23, b23_23to24_23, b24_23to25_23, b25_23to26_23, b26_23to27_23, b27_23to28_23, b28_23to29_23, b29_23to30_23, b30_23to31_23, b31_23to32_23; +wire [`DWIDTH-1:0] b0_24to1_24, b1_24to2_24, b2_24to3_24, b3_24to4_24, b4_24to5_24, b5_24to6_24, b6_24to7_24, b7_24to8_24, b8_24to9_24, b9_24to10_24, b10_24to11_24, b11_24to12_24, b12_24to13_24, b13_24to14_24, b14_24to15_24, b15_24to16_24, b16_24to17_24, b17_24to18_24, b18_24to19_24, b19_24to20_24, b20_24to21_24, b21_24to22_24, b22_24to23_24, b23_24to24_24, b24_24to25_24, b25_24to26_24, b26_24to27_24, b27_24to28_24, b28_24to29_24, b29_24to30_24, b30_24to31_24, b31_24to32_24; +wire [`DWIDTH-1:0] b0_25to1_25, b1_25to2_25, b2_25to3_25, b3_25to4_25, b4_25to5_25, b5_25to6_25, b6_25to7_25, b7_25to8_25, b8_25to9_25, b9_25to10_25, b10_25to11_25, b11_25to12_25, b12_25to13_25, b13_25to14_25, b14_25to15_25, b15_25to16_25, b16_25to17_25, b17_25to18_25, b18_25to19_25, b19_25to20_25, b20_25to21_25, b21_25to22_25, b22_25to23_25, b23_25to24_25, b24_25to25_25, b25_25to26_25, b26_25to27_25, b27_25to28_25, b28_25to29_25, b29_25to30_25, b30_25to31_25, b31_25to32_25; +wire [`DWIDTH-1:0] b0_26to1_26, b1_26to2_26, b2_26to3_26, b3_26to4_26, b4_26to5_26, b5_26to6_26, b6_26to7_26, b7_26to8_26, b8_26to9_26, b9_26to10_26, b10_26to11_26, b11_26to12_26, b12_26to13_26, b13_26to14_26, b14_26to15_26, b15_26to16_26, b16_26to17_26, b17_26to18_26, b18_26to19_26, b19_26to20_26, b20_26to21_26, b21_26to22_26, b22_26to23_26, b23_26to24_26, b24_26to25_26, b25_26to26_26, b26_26to27_26, b27_26to28_26, b28_26to29_26, b29_26to30_26, b30_26to31_26, b31_26to32_26; +wire [`DWIDTH-1:0] b0_27to1_27, b1_27to2_27, b2_27to3_27, b3_27to4_27, b4_27to5_27, b5_27to6_27, b6_27to7_27, b7_27to8_27, b8_27to9_27, b9_27to10_27, b10_27to11_27, b11_27to12_27, b12_27to13_27, b13_27to14_27, b14_27to15_27, b15_27to16_27, b16_27to17_27, b17_27to18_27, b18_27to19_27, b19_27to20_27, b20_27to21_27, b21_27to22_27, b22_27to23_27, b23_27to24_27, b24_27to25_27, b25_27to26_27, b26_27to27_27, b27_27to28_27, b28_27to29_27, b29_27to30_27, b30_27to31_27, b31_27to32_27; +wire [`DWIDTH-1:0] b0_28to1_28, b1_28to2_28, b2_28to3_28, b3_28to4_28, b4_28to5_28, b5_28to6_28, b6_28to7_28, b7_28to8_28, b8_28to9_28, b9_28to10_28, b10_28to11_28, b11_28to12_28, b12_28to13_28, b13_28to14_28, b14_28to15_28, b15_28to16_28, b16_28to17_28, b17_28to18_28, b18_28to19_28, b19_28to20_28, b20_28to21_28, b21_28to22_28, b22_28to23_28, b23_28to24_28, b24_28to25_28, b25_28to26_28, b26_28to27_28, b27_28to28_28, b28_28to29_28, b29_28to30_28, b30_28to31_28, b31_28to32_28; +wire [`DWIDTH-1:0] b0_29to1_29, b1_29to2_29, b2_29to3_29, b3_29to4_29, b4_29to5_29, b5_29to6_29, b6_29to7_29, b7_29to8_29, b8_29to9_29, b9_29to10_29, b10_29to11_29, b11_29to12_29, b12_29to13_29, b13_29to14_29, b14_29to15_29, b15_29to16_29, b16_29to17_29, b17_29to18_29, b18_29to19_29, b19_29to20_29, b20_29to21_29, b21_29to22_29, b22_29to23_29, b23_29to24_29, b24_29to25_29, b25_29to26_29, b26_29to27_29, b27_29to28_29, b28_29to29_29, b29_29to30_29, b30_29to31_29, b31_29to32_29; +wire [`DWIDTH-1:0] b0_30to1_30, b1_30to2_30, b2_30to3_30, b3_30to4_30, b4_30to5_30, b5_30to6_30, b6_30to7_30, b7_30to8_30, b8_30to9_30, b9_30to10_30, b10_30to11_30, b11_30to12_30, b12_30to13_30, b13_30to14_30, b14_30to15_30, b15_30to16_30, b16_30to17_30, b17_30to18_30, b18_30to19_30, b19_30to20_30, b20_30to21_30, b21_30to22_30, b22_30to23_30, b23_30to24_30, b24_30to25_30, b25_30to26_30, b26_30to27_30, b27_30to28_30, b28_30to29_30, b29_30to30_30, b30_30to31_30, b31_30to32_30; +wire [`DWIDTH-1:0] b0_31to1_31, b1_31to2_31, b2_31to3_31, b3_31to4_31, b4_31to5_31, b5_31to6_31, b6_31to7_31, b7_31to8_31, b8_31to9_31, b9_31to10_31, b10_31to11_31, b11_31to12_31, b12_31to13_31, b13_31to14_31, b14_31to15_31, b15_31to16_31, b16_31to17_31, b17_31to18_31, b18_31to19_31, b19_31to20_31, b20_31to21_31, b21_31to22_31, b22_31to23_31, b23_31to24_31, b24_31to25_31, b25_31to26_31, b26_31to27_31, b27_31to28_31, b28_31to29_31, b29_31to30_31, b30_31to31_31, b31_31to32_31; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); +processing_element pe0_16(.reset(effective_rst), .clk(clk), .in_a(a0_15to0_16), .in_b(b16), .out_a(a0_16to0_17), .out_b(b0_16to1_16), .out_c(matrixC0_16)); +processing_element pe0_17(.reset(effective_rst), .clk(clk), .in_a(a0_16to0_17), .in_b(b17), .out_a(a0_17to0_18), .out_b(b0_17to1_17), .out_c(matrixC0_17)); +processing_element pe0_18(.reset(effective_rst), .clk(clk), .in_a(a0_17to0_18), .in_b(b18), .out_a(a0_18to0_19), .out_b(b0_18to1_18), .out_c(matrixC0_18)); +processing_element pe0_19(.reset(effective_rst), .clk(clk), .in_a(a0_18to0_19), .in_b(b19), .out_a(a0_19to0_20), .out_b(b0_19to1_19), .out_c(matrixC0_19)); +processing_element pe0_20(.reset(effective_rst), .clk(clk), .in_a(a0_19to0_20), .in_b(b20), .out_a(a0_20to0_21), .out_b(b0_20to1_20), .out_c(matrixC0_20)); +processing_element pe0_21(.reset(effective_rst), .clk(clk), .in_a(a0_20to0_21), .in_b(b21), .out_a(a0_21to0_22), .out_b(b0_21to1_21), .out_c(matrixC0_21)); +processing_element pe0_22(.reset(effective_rst), .clk(clk), .in_a(a0_21to0_22), .in_b(b22), .out_a(a0_22to0_23), .out_b(b0_22to1_22), .out_c(matrixC0_22)); +processing_element pe0_23(.reset(effective_rst), .clk(clk), .in_a(a0_22to0_23), .in_b(b23), .out_a(a0_23to0_24), .out_b(b0_23to1_23), .out_c(matrixC0_23)); +processing_element pe0_24(.reset(effective_rst), .clk(clk), .in_a(a0_23to0_24), .in_b(b24), .out_a(a0_24to0_25), .out_b(b0_24to1_24), .out_c(matrixC0_24)); +processing_element pe0_25(.reset(effective_rst), .clk(clk), .in_a(a0_24to0_25), .in_b(b25), .out_a(a0_25to0_26), .out_b(b0_25to1_25), .out_c(matrixC0_25)); +processing_element pe0_26(.reset(effective_rst), .clk(clk), .in_a(a0_25to0_26), .in_b(b26), .out_a(a0_26to0_27), .out_b(b0_26to1_26), .out_c(matrixC0_26)); +processing_element pe0_27(.reset(effective_rst), .clk(clk), .in_a(a0_26to0_27), .in_b(b27), .out_a(a0_27to0_28), .out_b(b0_27to1_27), .out_c(matrixC0_27)); +processing_element pe0_28(.reset(effective_rst), .clk(clk), .in_a(a0_27to0_28), .in_b(b28), .out_a(a0_28to0_29), .out_b(b0_28to1_28), .out_c(matrixC0_28)); +processing_element pe0_29(.reset(effective_rst), .clk(clk), .in_a(a0_28to0_29), .in_b(b29), .out_a(a0_29to0_30), .out_b(b0_29to1_29), .out_c(matrixC0_29)); +processing_element pe0_30(.reset(effective_rst), .clk(clk), .in_a(a0_29to0_30), .in_b(b30), .out_a(a0_30to0_31), .out_b(b0_30to1_30), .out_c(matrixC0_30)); +processing_element pe0_31(.reset(effective_rst), .clk(clk), .in_a(a0_30to0_31), .in_b(b31), .out_a(a0_31to0_32), .out_b(b0_31to1_31), .out_c(matrixC0_31)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); +processing_element pe16_0(.reset(effective_rst), .clk(clk), .in_a(a16), .in_b(b15_0to16_0), .out_a(a16_0to16_1), .out_b(b16_0to17_0), .out_c(matrixC16_0)); +processing_element pe17_0(.reset(effective_rst), .clk(clk), .in_a(a17), .in_b(b16_0to17_0), .out_a(a17_0to17_1), .out_b(b17_0to18_0), .out_c(matrixC17_0)); +processing_element pe18_0(.reset(effective_rst), .clk(clk), .in_a(a18), .in_b(b17_0to18_0), .out_a(a18_0to18_1), .out_b(b18_0to19_0), .out_c(matrixC18_0)); +processing_element pe19_0(.reset(effective_rst), .clk(clk), .in_a(a19), .in_b(b18_0to19_0), .out_a(a19_0to19_1), .out_b(b19_0to20_0), .out_c(matrixC19_0)); +processing_element pe20_0(.reset(effective_rst), .clk(clk), .in_a(a20), .in_b(b19_0to20_0), .out_a(a20_0to20_1), .out_b(b20_0to21_0), .out_c(matrixC20_0)); +processing_element pe21_0(.reset(effective_rst), .clk(clk), .in_a(a21), .in_b(b20_0to21_0), .out_a(a21_0to21_1), .out_b(b21_0to22_0), .out_c(matrixC21_0)); +processing_element pe22_0(.reset(effective_rst), .clk(clk), .in_a(a22), .in_b(b21_0to22_0), .out_a(a22_0to22_1), .out_b(b22_0to23_0), .out_c(matrixC22_0)); +processing_element pe23_0(.reset(effective_rst), .clk(clk), .in_a(a23), .in_b(b22_0to23_0), .out_a(a23_0to23_1), .out_b(b23_0to24_0), .out_c(matrixC23_0)); +processing_element pe24_0(.reset(effective_rst), .clk(clk), .in_a(a24), .in_b(b23_0to24_0), .out_a(a24_0to24_1), .out_b(b24_0to25_0), .out_c(matrixC24_0)); +processing_element pe25_0(.reset(effective_rst), .clk(clk), .in_a(a25), .in_b(b24_0to25_0), .out_a(a25_0to25_1), .out_b(b25_0to26_0), .out_c(matrixC25_0)); +processing_element pe26_0(.reset(effective_rst), .clk(clk), .in_a(a26), .in_b(b25_0to26_0), .out_a(a26_0to26_1), .out_b(b26_0to27_0), .out_c(matrixC26_0)); +processing_element pe27_0(.reset(effective_rst), .clk(clk), .in_a(a27), .in_b(b26_0to27_0), .out_a(a27_0to27_1), .out_b(b27_0to28_0), .out_c(matrixC27_0)); +processing_element pe28_0(.reset(effective_rst), .clk(clk), .in_a(a28), .in_b(b27_0to28_0), .out_a(a28_0to28_1), .out_b(b28_0to29_0), .out_c(matrixC28_0)); +processing_element pe29_0(.reset(effective_rst), .clk(clk), .in_a(a29), .in_b(b28_0to29_0), .out_a(a29_0to29_1), .out_b(b29_0to30_0), .out_c(matrixC29_0)); +processing_element pe30_0(.reset(effective_rst), .clk(clk), .in_a(a30), .in_b(b29_0to30_0), .out_a(a30_0to30_1), .out_b(b30_0to31_0), .out_c(matrixC30_0)); +processing_element pe31_0(.reset(effective_rst), .clk(clk), .in_a(a31), .in_b(b30_0to31_0), .out_a(a31_0to31_1), .out_b(b31_0to32_0), .out_c(matrixC31_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe1_16(.reset(effective_rst), .clk(clk), .in_a(a1_15to1_16), .in_b(b0_16to1_16), .out_a(a1_16to1_17), .out_b(b1_16to2_16), .out_c(matrixC1_16)); +processing_element pe1_17(.reset(effective_rst), .clk(clk), .in_a(a1_16to1_17), .in_b(b0_17to1_17), .out_a(a1_17to1_18), .out_b(b1_17to2_17), .out_c(matrixC1_17)); +processing_element pe1_18(.reset(effective_rst), .clk(clk), .in_a(a1_17to1_18), .in_b(b0_18to1_18), .out_a(a1_18to1_19), .out_b(b1_18to2_18), .out_c(matrixC1_18)); +processing_element pe1_19(.reset(effective_rst), .clk(clk), .in_a(a1_18to1_19), .in_b(b0_19to1_19), .out_a(a1_19to1_20), .out_b(b1_19to2_19), .out_c(matrixC1_19)); +processing_element pe1_20(.reset(effective_rst), .clk(clk), .in_a(a1_19to1_20), .in_b(b0_20to1_20), .out_a(a1_20to1_21), .out_b(b1_20to2_20), .out_c(matrixC1_20)); +processing_element pe1_21(.reset(effective_rst), .clk(clk), .in_a(a1_20to1_21), .in_b(b0_21to1_21), .out_a(a1_21to1_22), .out_b(b1_21to2_21), .out_c(matrixC1_21)); +processing_element pe1_22(.reset(effective_rst), .clk(clk), .in_a(a1_21to1_22), .in_b(b0_22to1_22), .out_a(a1_22to1_23), .out_b(b1_22to2_22), .out_c(matrixC1_22)); +processing_element pe1_23(.reset(effective_rst), .clk(clk), .in_a(a1_22to1_23), .in_b(b0_23to1_23), .out_a(a1_23to1_24), .out_b(b1_23to2_23), .out_c(matrixC1_23)); +processing_element pe1_24(.reset(effective_rst), .clk(clk), .in_a(a1_23to1_24), .in_b(b0_24to1_24), .out_a(a1_24to1_25), .out_b(b1_24to2_24), .out_c(matrixC1_24)); +processing_element pe1_25(.reset(effective_rst), .clk(clk), .in_a(a1_24to1_25), .in_b(b0_25to1_25), .out_a(a1_25to1_26), .out_b(b1_25to2_25), .out_c(matrixC1_25)); +processing_element pe1_26(.reset(effective_rst), .clk(clk), .in_a(a1_25to1_26), .in_b(b0_26to1_26), .out_a(a1_26to1_27), .out_b(b1_26to2_26), .out_c(matrixC1_26)); +processing_element pe1_27(.reset(effective_rst), .clk(clk), .in_a(a1_26to1_27), .in_b(b0_27to1_27), .out_a(a1_27to1_28), .out_b(b1_27to2_27), .out_c(matrixC1_27)); +processing_element pe1_28(.reset(effective_rst), .clk(clk), .in_a(a1_27to1_28), .in_b(b0_28to1_28), .out_a(a1_28to1_29), .out_b(b1_28to2_28), .out_c(matrixC1_28)); +processing_element pe1_29(.reset(effective_rst), .clk(clk), .in_a(a1_28to1_29), .in_b(b0_29to1_29), .out_a(a1_29to1_30), .out_b(b1_29to2_29), .out_c(matrixC1_29)); +processing_element pe1_30(.reset(effective_rst), .clk(clk), .in_a(a1_29to1_30), .in_b(b0_30to1_30), .out_a(a1_30to1_31), .out_b(b1_30to2_30), .out_c(matrixC1_30)); +processing_element pe1_31(.reset(effective_rst), .clk(clk), .in_a(a1_30to1_31), .in_b(b0_31to1_31), .out_a(a1_31to1_32), .out_b(b1_31to2_31), .out_c(matrixC1_31)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe2_16(.reset(effective_rst), .clk(clk), .in_a(a2_15to2_16), .in_b(b1_16to2_16), .out_a(a2_16to2_17), .out_b(b2_16to3_16), .out_c(matrixC2_16)); +processing_element pe2_17(.reset(effective_rst), .clk(clk), .in_a(a2_16to2_17), .in_b(b1_17to2_17), .out_a(a2_17to2_18), .out_b(b2_17to3_17), .out_c(matrixC2_17)); +processing_element pe2_18(.reset(effective_rst), .clk(clk), .in_a(a2_17to2_18), .in_b(b1_18to2_18), .out_a(a2_18to2_19), .out_b(b2_18to3_18), .out_c(matrixC2_18)); +processing_element pe2_19(.reset(effective_rst), .clk(clk), .in_a(a2_18to2_19), .in_b(b1_19to2_19), .out_a(a2_19to2_20), .out_b(b2_19to3_19), .out_c(matrixC2_19)); +processing_element pe2_20(.reset(effective_rst), .clk(clk), .in_a(a2_19to2_20), .in_b(b1_20to2_20), .out_a(a2_20to2_21), .out_b(b2_20to3_20), .out_c(matrixC2_20)); +processing_element pe2_21(.reset(effective_rst), .clk(clk), .in_a(a2_20to2_21), .in_b(b1_21to2_21), .out_a(a2_21to2_22), .out_b(b2_21to3_21), .out_c(matrixC2_21)); +processing_element pe2_22(.reset(effective_rst), .clk(clk), .in_a(a2_21to2_22), .in_b(b1_22to2_22), .out_a(a2_22to2_23), .out_b(b2_22to3_22), .out_c(matrixC2_22)); +processing_element pe2_23(.reset(effective_rst), .clk(clk), .in_a(a2_22to2_23), .in_b(b1_23to2_23), .out_a(a2_23to2_24), .out_b(b2_23to3_23), .out_c(matrixC2_23)); +processing_element pe2_24(.reset(effective_rst), .clk(clk), .in_a(a2_23to2_24), .in_b(b1_24to2_24), .out_a(a2_24to2_25), .out_b(b2_24to3_24), .out_c(matrixC2_24)); +processing_element pe2_25(.reset(effective_rst), .clk(clk), .in_a(a2_24to2_25), .in_b(b1_25to2_25), .out_a(a2_25to2_26), .out_b(b2_25to3_25), .out_c(matrixC2_25)); +processing_element pe2_26(.reset(effective_rst), .clk(clk), .in_a(a2_25to2_26), .in_b(b1_26to2_26), .out_a(a2_26to2_27), .out_b(b2_26to3_26), .out_c(matrixC2_26)); +processing_element pe2_27(.reset(effective_rst), .clk(clk), .in_a(a2_26to2_27), .in_b(b1_27to2_27), .out_a(a2_27to2_28), .out_b(b2_27to3_27), .out_c(matrixC2_27)); +processing_element pe2_28(.reset(effective_rst), .clk(clk), .in_a(a2_27to2_28), .in_b(b1_28to2_28), .out_a(a2_28to2_29), .out_b(b2_28to3_28), .out_c(matrixC2_28)); +processing_element pe2_29(.reset(effective_rst), .clk(clk), .in_a(a2_28to2_29), .in_b(b1_29to2_29), .out_a(a2_29to2_30), .out_b(b2_29to3_29), .out_c(matrixC2_29)); +processing_element pe2_30(.reset(effective_rst), .clk(clk), .in_a(a2_29to2_30), .in_b(b1_30to2_30), .out_a(a2_30to2_31), .out_b(b2_30to3_30), .out_c(matrixC2_30)); +processing_element pe2_31(.reset(effective_rst), .clk(clk), .in_a(a2_30to2_31), .in_b(b1_31to2_31), .out_a(a2_31to2_32), .out_b(b2_31to3_31), .out_c(matrixC2_31)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe3_16(.reset(effective_rst), .clk(clk), .in_a(a3_15to3_16), .in_b(b2_16to3_16), .out_a(a3_16to3_17), .out_b(b3_16to4_16), .out_c(matrixC3_16)); +processing_element pe3_17(.reset(effective_rst), .clk(clk), .in_a(a3_16to3_17), .in_b(b2_17to3_17), .out_a(a3_17to3_18), .out_b(b3_17to4_17), .out_c(matrixC3_17)); +processing_element pe3_18(.reset(effective_rst), .clk(clk), .in_a(a3_17to3_18), .in_b(b2_18to3_18), .out_a(a3_18to3_19), .out_b(b3_18to4_18), .out_c(matrixC3_18)); +processing_element pe3_19(.reset(effective_rst), .clk(clk), .in_a(a3_18to3_19), .in_b(b2_19to3_19), .out_a(a3_19to3_20), .out_b(b3_19to4_19), .out_c(matrixC3_19)); +processing_element pe3_20(.reset(effective_rst), .clk(clk), .in_a(a3_19to3_20), .in_b(b2_20to3_20), .out_a(a3_20to3_21), .out_b(b3_20to4_20), .out_c(matrixC3_20)); +processing_element pe3_21(.reset(effective_rst), .clk(clk), .in_a(a3_20to3_21), .in_b(b2_21to3_21), .out_a(a3_21to3_22), .out_b(b3_21to4_21), .out_c(matrixC3_21)); +processing_element pe3_22(.reset(effective_rst), .clk(clk), .in_a(a3_21to3_22), .in_b(b2_22to3_22), .out_a(a3_22to3_23), .out_b(b3_22to4_22), .out_c(matrixC3_22)); +processing_element pe3_23(.reset(effective_rst), .clk(clk), .in_a(a3_22to3_23), .in_b(b2_23to3_23), .out_a(a3_23to3_24), .out_b(b3_23to4_23), .out_c(matrixC3_23)); +processing_element pe3_24(.reset(effective_rst), .clk(clk), .in_a(a3_23to3_24), .in_b(b2_24to3_24), .out_a(a3_24to3_25), .out_b(b3_24to4_24), .out_c(matrixC3_24)); +processing_element pe3_25(.reset(effective_rst), .clk(clk), .in_a(a3_24to3_25), .in_b(b2_25to3_25), .out_a(a3_25to3_26), .out_b(b3_25to4_25), .out_c(matrixC3_25)); +processing_element pe3_26(.reset(effective_rst), .clk(clk), .in_a(a3_25to3_26), .in_b(b2_26to3_26), .out_a(a3_26to3_27), .out_b(b3_26to4_26), .out_c(matrixC3_26)); +processing_element pe3_27(.reset(effective_rst), .clk(clk), .in_a(a3_26to3_27), .in_b(b2_27to3_27), .out_a(a3_27to3_28), .out_b(b3_27to4_27), .out_c(matrixC3_27)); +processing_element pe3_28(.reset(effective_rst), .clk(clk), .in_a(a3_27to3_28), .in_b(b2_28to3_28), .out_a(a3_28to3_29), .out_b(b3_28to4_28), .out_c(matrixC3_28)); +processing_element pe3_29(.reset(effective_rst), .clk(clk), .in_a(a3_28to3_29), .in_b(b2_29to3_29), .out_a(a3_29to3_30), .out_b(b3_29to4_29), .out_c(matrixC3_29)); +processing_element pe3_30(.reset(effective_rst), .clk(clk), .in_a(a3_29to3_30), .in_b(b2_30to3_30), .out_a(a3_30to3_31), .out_b(b3_30to4_30), .out_c(matrixC3_30)); +processing_element pe3_31(.reset(effective_rst), .clk(clk), .in_a(a3_30to3_31), .in_b(b2_31to3_31), .out_a(a3_31to3_32), .out_b(b3_31to4_31), .out_c(matrixC3_31)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe4_16(.reset(effective_rst), .clk(clk), .in_a(a4_15to4_16), .in_b(b3_16to4_16), .out_a(a4_16to4_17), .out_b(b4_16to5_16), .out_c(matrixC4_16)); +processing_element pe4_17(.reset(effective_rst), .clk(clk), .in_a(a4_16to4_17), .in_b(b3_17to4_17), .out_a(a4_17to4_18), .out_b(b4_17to5_17), .out_c(matrixC4_17)); +processing_element pe4_18(.reset(effective_rst), .clk(clk), .in_a(a4_17to4_18), .in_b(b3_18to4_18), .out_a(a4_18to4_19), .out_b(b4_18to5_18), .out_c(matrixC4_18)); +processing_element pe4_19(.reset(effective_rst), .clk(clk), .in_a(a4_18to4_19), .in_b(b3_19to4_19), .out_a(a4_19to4_20), .out_b(b4_19to5_19), .out_c(matrixC4_19)); +processing_element pe4_20(.reset(effective_rst), .clk(clk), .in_a(a4_19to4_20), .in_b(b3_20to4_20), .out_a(a4_20to4_21), .out_b(b4_20to5_20), .out_c(matrixC4_20)); +processing_element pe4_21(.reset(effective_rst), .clk(clk), .in_a(a4_20to4_21), .in_b(b3_21to4_21), .out_a(a4_21to4_22), .out_b(b4_21to5_21), .out_c(matrixC4_21)); +processing_element pe4_22(.reset(effective_rst), .clk(clk), .in_a(a4_21to4_22), .in_b(b3_22to4_22), .out_a(a4_22to4_23), .out_b(b4_22to5_22), .out_c(matrixC4_22)); +processing_element pe4_23(.reset(effective_rst), .clk(clk), .in_a(a4_22to4_23), .in_b(b3_23to4_23), .out_a(a4_23to4_24), .out_b(b4_23to5_23), .out_c(matrixC4_23)); +processing_element pe4_24(.reset(effective_rst), .clk(clk), .in_a(a4_23to4_24), .in_b(b3_24to4_24), .out_a(a4_24to4_25), .out_b(b4_24to5_24), .out_c(matrixC4_24)); +processing_element pe4_25(.reset(effective_rst), .clk(clk), .in_a(a4_24to4_25), .in_b(b3_25to4_25), .out_a(a4_25to4_26), .out_b(b4_25to5_25), .out_c(matrixC4_25)); +processing_element pe4_26(.reset(effective_rst), .clk(clk), .in_a(a4_25to4_26), .in_b(b3_26to4_26), .out_a(a4_26to4_27), .out_b(b4_26to5_26), .out_c(matrixC4_26)); +processing_element pe4_27(.reset(effective_rst), .clk(clk), .in_a(a4_26to4_27), .in_b(b3_27to4_27), .out_a(a4_27to4_28), .out_b(b4_27to5_27), .out_c(matrixC4_27)); +processing_element pe4_28(.reset(effective_rst), .clk(clk), .in_a(a4_27to4_28), .in_b(b3_28to4_28), .out_a(a4_28to4_29), .out_b(b4_28to5_28), .out_c(matrixC4_28)); +processing_element pe4_29(.reset(effective_rst), .clk(clk), .in_a(a4_28to4_29), .in_b(b3_29to4_29), .out_a(a4_29to4_30), .out_b(b4_29to5_29), .out_c(matrixC4_29)); +processing_element pe4_30(.reset(effective_rst), .clk(clk), .in_a(a4_29to4_30), .in_b(b3_30to4_30), .out_a(a4_30to4_31), .out_b(b4_30to5_30), .out_c(matrixC4_30)); +processing_element pe4_31(.reset(effective_rst), .clk(clk), .in_a(a4_30to4_31), .in_b(b3_31to4_31), .out_a(a4_31to4_32), .out_b(b4_31to5_31), .out_c(matrixC4_31)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe5_16(.reset(effective_rst), .clk(clk), .in_a(a5_15to5_16), .in_b(b4_16to5_16), .out_a(a5_16to5_17), .out_b(b5_16to6_16), .out_c(matrixC5_16)); +processing_element pe5_17(.reset(effective_rst), .clk(clk), .in_a(a5_16to5_17), .in_b(b4_17to5_17), .out_a(a5_17to5_18), .out_b(b5_17to6_17), .out_c(matrixC5_17)); +processing_element pe5_18(.reset(effective_rst), .clk(clk), .in_a(a5_17to5_18), .in_b(b4_18to5_18), .out_a(a5_18to5_19), .out_b(b5_18to6_18), .out_c(matrixC5_18)); +processing_element pe5_19(.reset(effective_rst), .clk(clk), .in_a(a5_18to5_19), .in_b(b4_19to5_19), .out_a(a5_19to5_20), .out_b(b5_19to6_19), .out_c(matrixC5_19)); +processing_element pe5_20(.reset(effective_rst), .clk(clk), .in_a(a5_19to5_20), .in_b(b4_20to5_20), .out_a(a5_20to5_21), .out_b(b5_20to6_20), .out_c(matrixC5_20)); +processing_element pe5_21(.reset(effective_rst), .clk(clk), .in_a(a5_20to5_21), .in_b(b4_21to5_21), .out_a(a5_21to5_22), .out_b(b5_21to6_21), .out_c(matrixC5_21)); +processing_element pe5_22(.reset(effective_rst), .clk(clk), .in_a(a5_21to5_22), .in_b(b4_22to5_22), .out_a(a5_22to5_23), .out_b(b5_22to6_22), .out_c(matrixC5_22)); +processing_element pe5_23(.reset(effective_rst), .clk(clk), .in_a(a5_22to5_23), .in_b(b4_23to5_23), .out_a(a5_23to5_24), .out_b(b5_23to6_23), .out_c(matrixC5_23)); +processing_element pe5_24(.reset(effective_rst), .clk(clk), .in_a(a5_23to5_24), .in_b(b4_24to5_24), .out_a(a5_24to5_25), .out_b(b5_24to6_24), .out_c(matrixC5_24)); +processing_element pe5_25(.reset(effective_rst), .clk(clk), .in_a(a5_24to5_25), .in_b(b4_25to5_25), .out_a(a5_25to5_26), .out_b(b5_25to6_25), .out_c(matrixC5_25)); +processing_element pe5_26(.reset(effective_rst), .clk(clk), .in_a(a5_25to5_26), .in_b(b4_26to5_26), .out_a(a5_26to5_27), .out_b(b5_26to6_26), .out_c(matrixC5_26)); +processing_element pe5_27(.reset(effective_rst), .clk(clk), .in_a(a5_26to5_27), .in_b(b4_27to5_27), .out_a(a5_27to5_28), .out_b(b5_27to6_27), .out_c(matrixC5_27)); +processing_element pe5_28(.reset(effective_rst), .clk(clk), .in_a(a5_27to5_28), .in_b(b4_28to5_28), .out_a(a5_28to5_29), .out_b(b5_28to6_28), .out_c(matrixC5_28)); +processing_element pe5_29(.reset(effective_rst), .clk(clk), .in_a(a5_28to5_29), .in_b(b4_29to5_29), .out_a(a5_29to5_30), .out_b(b5_29to6_29), .out_c(matrixC5_29)); +processing_element pe5_30(.reset(effective_rst), .clk(clk), .in_a(a5_29to5_30), .in_b(b4_30to5_30), .out_a(a5_30to5_31), .out_b(b5_30to6_30), .out_c(matrixC5_30)); +processing_element pe5_31(.reset(effective_rst), .clk(clk), .in_a(a5_30to5_31), .in_b(b4_31to5_31), .out_a(a5_31to5_32), .out_b(b5_31to6_31), .out_c(matrixC5_31)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe6_16(.reset(effective_rst), .clk(clk), .in_a(a6_15to6_16), .in_b(b5_16to6_16), .out_a(a6_16to6_17), .out_b(b6_16to7_16), .out_c(matrixC6_16)); +processing_element pe6_17(.reset(effective_rst), .clk(clk), .in_a(a6_16to6_17), .in_b(b5_17to6_17), .out_a(a6_17to6_18), .out_b(b6_17to7_17), .out_c(matrixC6_17)); +processing_element pe6_18(.reset(effective_rst), .clk(clk), .in_a(a6_17to6_18), .in_b(b5_18to6_18), .out_a(a6_18to6_19), .out_b(b6_18to7_18), .out_c(matrixC6_18)); +processing_element pe6_19(.reset(effective_rst), .clk(clk), .in_a(a6_18to6_19), .in_b(b5_19to6_19), .out_a(a6_19to6_20), .out_b(b6_19to7_19), .out_c(matrixC6_19)); +processing_element pe6_20(.reset(effective_rst), .clk(clk), .in_a(a6_19to6_20), .in_b(b5_20to6_20), .out_a(a6_20to6_21), .out_b(b6_20to7_20), .out_c(matrixC6_20)); +processing_element pe6_21(.reset(effective_rst), .clk(clk), .in_a(a6_20to6_21), .in_b(b5_21to6_21), .out_a(a6_21to6_22), .out_b(b6_21to7_21), .out_c(matrixC6_21)); +processing_element pe6_22(.reset(effective_rst), .clk(clk), .in_a(a6_21to6_22), .in_b(b5_22to6_22), .out_a(a6_22to6_23), .out_b(b6_22to7_22), .out_c(matrixC6_22)); +processing_element pe6_23(.reset(effective_rst), .clk(clk), .in_a(a6_22to6_23), .in_b(b5_23to6_23), .out_a(a6_23to6_24), .out_b(b6_23to7_23), .out_c(matrixC6_23)); +processing_element pe6_24(.reset(effective_rst), .clk(clk), .in_a(a6_23to6_24), .in_b(b5_24to6_24), .out_a(a6_24to6_25), .out_b(b6_24to7_24), .out_c(matrixC6_24)); +processing_element pe6_25(.reset(effective_rst), .clk(clk), .in_a(a6_24to6_25), .in_b(b5_25to6_25), .out_a(a6_25to6_26), .out_b(b6_25to7_25), .out_c(matrixC6_25)); +processing_element pe6_26(.reset(effective_rst), .clk(clk), .in_a(a6_25to6_26), .in_b(b5_26to6_26), .out_a(a6_26to6_27), .out_b(b6_26to7_26), .out_c(matrixC6_26)); +processing_element pe6_27(.reset(effective_rst), .clk(clk), .in_a(a6_26to6_27), .in_b(b5_27to6_27), .out_a(a6_27to6_28), .out_b(b6_27to7_27), .out_c(matrixC6_27)); +processing_element pe6_28(.reset(effective_rst), .clk(clk), .in_a(a6_27to6_28), .in_b(b5_28to6_28), .out_a(a6_28to6_29), .out_b(b6_28to7_28), .out_c(matrixC6_28)); +processing_element pe6_29(.reset(effective_rst), .clk(clk), .in_a(a6_28to6_29), .in_b(b5_29to6_29), .out_a(a6_29to6_30), .out_b(b6_29to7_29), .out_c(matrixC6_29)); +processing_element pe6_30(.reset(effective_rst), .clk(clk), .in_a(a6_29to6_30), .in_b(b5_30to6_30), .out_a(a6_30to6_31), .out_b(b6_30to7_30), .out_c(matrixC6_30)); +processing_element pe6_31(.reset(effective_rst), .clk(clk), .in_a(a6_30to6_31), .in_b(b5_31to6_31), .out_a(a6_31to6_32), .out_b(b6_31to7_31), .out_c(matrixC6_31)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe7_16(.reset(effective_rst), .clk(clk), .in_a(a7_15to7_16), .in_b(b6_16to7_16), .out_a(a7_16to7_17), .out_b(b7_16to8_16), .out_c(matrixC7_16)); +processing_element pe7_17(.reset(effective_rst), .clk(clk), .in_a(a7_16to7_17), .in_b(b6_17to7_17), .out_a(a7_17to7_18), .out_b(b7_17to8_17), .out_c(matrixC7_17)); +processing_element pe7_18(.reset(effective_rst), .clk(clk), .in_a(a7_17to7_18), .in_b(b6_18to7_18), .out_a(a7_18to7_19), .out_b(b7_18to8_18), .out_c(matrixC7_18)); +processing_element pe7_19(.reset(effective_rst), .clk(clk), .in_a(a7_18to7_19), .in_b(b6_19to7_19), .out_a(a7_19to7_20), .out_b(b7_19to8_19), .out_c(matrixC7_19)); +processing_element pe7_20(.reset(effective_rst), .clk(clk), .in_a(a7_19to7_20), .in_b(b6_20to7_20), .out_a(a7_20to7_21), .out_b(b7_20to8_20), .out_c(matrixC7_20)); +processing_element pe7_21(.reset(effective_rst), .clk(clk), .in_a(a7_20to7_21), .in_b(b6_21to7_21), .out_a(a7_21to7_22), .out_b(b7_21to8_21), .out_c(matrixC7_21)); +processing_element pe7_22(.reset(effective_rst), .clk(clk), .in_a(a7_21to7_22), .in_b(b6_22to7_22), .out_a(a7_22to7_23), .out_b(b7_22to8_22), .out_c(matrixC7_22)); +processing_element pe7_23(.reset(effective_rst), .clk(clk), .in_a(a7_22to7_23), .in_b(b6_23to7_23), .out_a(a7_23to7_24), .out_b(b7_23to8_23), .out_c(matrixC7_23)); +processing_element pe7_24(.reset(effective_rst), .clk(clk), .in_a(a7_23to7_24), .in_b(b6_24to7_24), .out_a(a7_24to7_25), .out_b(b7_24to8_24), .out_c(matrixC7_24)); +processing_element pe7_25(.reset(effective_rst), .clk(clk), .in_a(a7_24to7_25), .in_b(b6_25to7_25), .out_a(a7_25to7_26), .out_b(b7_25to8_25), .out_c(matrixC7_25)); +processing_element pe7_26(.reset(effective_rst), .clk(clk), .in_a(a7_25to7_26), .in_b(b6_26to7_26), .out_a(a7_26to7_27), .out_b(b7_26to8_26), .out_c(matrixC7_26)); +processing_element pe7_27(.reset(effective_rst), .clk(clk), .in_a(a7_26to7_27), .in_b(b6_27to7_27), .out_a(a7_27to7_28), .out_b(b7_27to8_27), .out_c(matrixC7_27)); +processing_element pe7_28(.reset(effective_rst), .clk(clk), .in_a(a7_27to7_28), .in_b(b6_28to7_28), .out_a(a7_28to7_29), .out_b(b7_28to8_28), .out_c(matrixC7_28)); +processing_element pe7_29(.reset(effective_rst), .clk(clk), .in_a(a7_28to7_29), .in_b(b6_29to7_29), .out_a(a7_29to7_30), .out_b(b7_29to8_29), .out_c(matrixC7_29)); +processing_element pe7_30(.reset(effective_rst), .clk(clk), .in_a(a7_29to7_30), .in_b(b6_30to7_30), .out_a(a7_30to7_31), .out_b(b7_30to8_30), .out_c(matrixC7_30)); +processing_element pe7_31(.reset(effective_rst), .clk(clk), .in_a(a7_30to7_31), .in_b(b6_31to7_31), .out_a(a7_31to7_32), .out_b(b7_31to8_31), .out_c(matrixC7_31)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe8_16(.reset(effective_rst), .clk(clk), .in_a(a8_15to8_16), .in_b(b7_16to8_16), .out_a(a8_16to8_17), .out_b(b8_16to9_16), .out_c(matrixC8_16)); +processing_element pe8_17(.reset(effective_rst), .clk(clk), .in_a(a8_16to8_17), .in_b(b7_17to8_17), .out_a(a8_17to8_18), .out_b(b8_17to9_17), .out_c(matrixC8_17)); +processing_element pe8_18(.reset(effective_rst), .clk(clk), .in_a(a8_17to8_18), .in_b(b7_18to8_18), .out_a(a8_18to8_19), .out_b(b8_18to9_18), .out_c(matrixC8_18)); +processing_element pe8_19(.reset(effective_rst), .clk(clk), .in_a(a8_18to8_19), .in_b(b7_19to8_19), .out_a(a8_19to8_20), .out_b(b8_19to9_19), .out_c(matrixC8_19)); +processing_element pe8_20(.reset(effective_rst), .clk(clk), .in_a(a8_19to8_20), .in_b(b7_20to8_20), .out_a(a8_20to8_21), .out_b(b8_20to9_20), .out_c(matrixC8_20)); +processing_element pe8_21(.reset(effective_rst), .clk(clk), .in_a(a8_20to8_21), .in_b(b7_21to8_21), .out_a(a8_21to8_22), .out_b(b8_21to9_21), .out_c(matrixC8_21)); +processing_element pe8_22(.reset(effective_rst), .clk(clk), .in_a(a8_21to8_22), .in_b(b7_22to8_22), .out_a(a8_22to8_23), .out_b(b8_22to9_22), .out_c(matrixC8_22)); +processing_element pe8_23(.reset(effective_rst), .clk(clk), .in_a(a8_22to8_23), .in_b(b7_23to8_23), .out_a(a8_23to8_24), .out_b(b8_23to9_23), .out_c(matrixC8_23)); +processing_element pe8_24(.reset(effective_rst), .clk(clk), .in_a(a8_23to8_24), .in_b(b7_24to8_24), .out_a(a8_24to8_25), .out_b(b8_24to9_24), .out_c(matrixC8_24)); +processing_element pe8_25(.reset(effective_rst), .clk(clk), .in_a(a8_24to8_25), .in_b(b7_25to8_25), .out_a(a8_25to8_26), .out_b(b8_25to9_25), .out_c(matrixC8_25)); +processing_element pe8_26(.reset(effective_rst), .clk(clk), .in_a(a8_25to8_26), .in_b(b7_26to8_26), .out_a(a8_26to8_27), .out_b(b8_26to9_26), .out_c(matrixC8_26)); +processing_element pe8_27(.reset(effective_rst), .clk(clk), .in_a(a8_26to8_27), .in_b(b7_27to8_27), .out_a(a8_27to8_28), .out_b(b8_27to9_27), .out_c(matrixC8_27)); +processing_element pe8_28(.reset(effective_rst), .clk(clk), .in_a(a8_27to8_28), .in_b(b7_28to8_28), .out_a(a8_28to8_29), .out_b(b8_28to9_28), .out_c(matrixC8_28)); +processing_element pe8_29(.reset(effective_rst), .clk(clk), .in_a(a8_28to8_29), .in_b(b7_29to8_29), .out_a(a8_29to8_30), .out_b(b8_29to9_29), .out_c(matrixC8_29)); +processing_element pe8_30(.reset(effective_rst), .clk(clk), .in_a(a8_29to8_30), .in_b(b7_30to8_30), .out_a(a8_30to8_31), .out_b(b8_30to9_30), .out_c(matrixC8_30)); +processing_element pe8_31(.reset(effective_rst), .clk(clk), .in_a(a8_30to8_31), .in_b(b7_31to8_31), .out_a(a8_31to8_32), .out_b(b8_31to9_31), .out_c(matrixC8_31)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe9_16(.reset(effective_rst), .clk(clk), .in_a(a9_15to9_16), .in_b(b8_16to9_16), .out_a(a9_16to9_17), .out_b(b9_16to10_16), .out_c(matrixC9_16)); +processing_element pe9_17(.reset(effective_rst), .clk(clk), .in_a(a9_16to9_17), .in_b(b8_17to9_17), .out_a(a9_17to9_18), .out_b(b9_17to10_17), .out_c(matrixC9_17)); +processing_element pe9_18(.reset(effective_rst), .clk(clk), .in_a(a9_17to9_18), .in_b(b8_18to9_18), .out_a(a9_18to9_19), .out_b(b9_18to10_18), .out_c(matrixC9_18)); +processing_element pe9_19(.reset(effective_rst), .clk(clk), .in_a(a9_18to9_19), .in_b(b8_19to9_19), .out_a(a9_19to9_20), .out_b(b9_19to10_19), .out_c(matrixC9_19)); +processing_element pe9_20(.reset(effective_rst), .clk(clk), .in_a(a9_19to9_20), .in_b(b8_20to9_20), .out_a(a9_20to9_21), .out_b(b9_20to10_20), .out_c(matrixC9_20)); +processing_element pe9_21(.reset(effective_rst), .clk(clk), .in_a(a9_20to9_21), .in_b(b8_21to9_21), .out_a(a9_21to9_22), .out_b(b9_21to10_21), .out_c(matrixC9_21)); +processing_element pe9_22(.reset(effective_rst), .clk(clk), .in_a(a9_21to9_22), .in_b(b8_22to9_22), .out_a(a9_22to9_23), .out_b(b9_22to10_22), .out_c(matrixC9_22)); +processing_element pe9_23(.reset(effective_rst), .clk(clk), .in_a(a9_22to9_23), .in_b(b8_23to9_23), .out_a(a9_23to9_24), .out_b(b9_23to10_23), .out_c(matrixC9_23)); +processing_element pe9_24(.reset(effective_rst), .clk(clk), .in_a(a9_23to9_24), .in_b(b8_24to9_24), .out_a(a9_24to9_25), .out_b(b9_24to10_24), .out_c(matrixC9_24)); +processing_element pe9_25(.reset(effective_rst), .clk(clk), .in_a(a9_24to9_25), .in_b(b8_25to9_25), .out_a(a9_25to9_26), .out_b(b9_25to10_25), .out_c(matrixC9_25)); +processing_element pe9_26(.reset(effective_rst), .clk(clk), .in_a(a9_25to9_26), .in_b(b8_26to9_26), .out_a(a9_26to9_27), .out_b(b9_26to10_26), .out_c(matrixC9_26)); +processing_element pe9_27(.reset(effective_rst), .clk(clk), .in_a(a9_26to9_27), .in_b(b8_27to9_27), .out_a(a9_27to9_28), .out_b(b9_27to10_27), .out_c(matrixC9_27)); +processing_element pe9_28(.reset(effective_rst), .clk(clk), .in_a(a9_27to9_28), .in_b(b8_28to9_28), .out_a(a9_28to9_29), .out_b(b9_28to10_28), .out_c(matrixC9_28)); +processing_element pe9_29(.reset(effective_rst), .clk(clk), .in_a(a9_28to9_29), .in_b(b8_29to9_29), .out_a(a9_29to9_30), .out_b(b9_29to10_29), .out_c(matrixC9_29)); +processing_element pe9_30(.reset(effective_rst), .clk(clk), .in_a(a9_29to9_30), .in_b(b8_30to9_30), .out_a(a9_30to9_31), .out_b(b9_30to10_30), .out_c(matrixC9_30)); +processing_element pe9_31(.reset(effective_rst), .clk(clk), .in_a(a9_30to9_31), .in_b(b8_31to9_31), .out_a(a9_31to9_32), .out_b(b9_31to10_31), .out_c(matrixC9_31)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe10_16(.reset(effective_rst), .clk(clk), .in_a(a10_15to10_16), .in_b(b9_16to10_16), .out_a(a10_16to10_17), .out_b(b10_16to11_16), .out_c(matrixC10_16)); +processing_element pe10_17(.reset(effective_rst), .clk(clk), .in_a(a10_16to10_17), .in_b(b9_17to10_17), .out_a(a10_17to10_18), .out_b(b10_17to11_17), .out_c(matrixC10_17)); +processing_element pe10_18(.reset(effective_rst), .clk(clk), .in_a(a10_17to10_18), .in_b(b9_18to10_18), .out_a(a10_18to10_19), .out_b(b10_18to11_18), .out_c(matrixC10_18)); +processing_element pe10_19(.reset(effective_rst), .clk(clk), .in_a(a10_18to10_19), .in_b(b9_19to10_19), .out_a(a10_19to10_20), .out_b(b10_19to11_19), .out_c(matrixC10_19)); +processing_element pe10_20(.reset(effective_rst), .clk(clk), .in_a(a10_19to10_20), .in_b(b9_20to10_20), .out_a(a10_20to10_21), .out_b(b10_20to11_20), .out_c(matrixC10_20)); +processing_element pe10_21(.reset(effective_rst), .clk(clk), .in_a(a10_20to10_21), .in_b(b9_21to10_21), .out_a(a10_21to10_22), .out_b(b10_21to11_21), .out_c(matrixC10_21)); +processing_element pe10_22(.reset(effective_rst), .clk(clk), .in_a(a10_21to10_22), .in_b(b9_22to10_22), .out_a(a10_22to10_23), .out_b(b10_22to11_22), .out_c(matrixC10_22)); +processing_element pe10_23(.reset(effective_rst), .clk(clk), .in_a(a10_22to10_23), .in_b(b9_23to10_23), .out_a(a10_23to10_24), .out_b(b10_23to11_23), .out_c(matrixC10_23)); +processing_element pe10_24(.reset(effective_rst), .clk(clk), .in_a(a10_23to10_24), .in_b(b9_24to10_24), .out_a(a10_24to10_25), .out_b(b10_24to11_24), .out_c(matrixC10_24)); +processing_element pe10_25(.reset(effective_rst), .clk(clk), .in_a(a10_24to10_25), .in_b(b9_25to10_25), .out_a(a10_25to10_26), .out_b(b10_25to11_25), .out_c(matrixC10_25)); +processing_element pe10_26(.reset(effective_rst), .clk(clk), .in_a(a10_25to10_26), .in_b(b9_26to10_26), .out_a(a10_26to10_27), .out_b(b10_26to11_26), .out_c(matrixC10_26)); +processing_element pe10_27(.reset(effective_rst), .clk(clk), .in_a(a10_26to10_27), .in_b(b9_27to10_27), .out_a(a10_27to10_28), .out_b(b10_27to11_27), .out_c(matrixC10_27)); +processing_element pe10_28(.reset(effective_rst), .clk(clk), .in_a(a10_27to10_28), .in_b(b9_28to10_28), .out_a(a10_28to10_29), .out_b(b10_28to11_28), .out_c(matrixC10_28)); +processing_element pe10_29(.reset(effective_rst), .clk(clk), .in_a(a10_28to10_29), .in_b(b9_29to10_29), .out_a(a10_29to10_30), .out_b(b10_29to11_29), .out_c(matrixC10_29)); +processing_element pe10_30(.reset(effective_rst), .clk(clk), .in_a(a10_29to10_30), .in_b(b9_30to10_30), .out_a(a10_30to10_31), .out_b(b10_30to11_30), .out_c(matrixC10_30)); +processing_element pe10_31(.reset(effective_rst), .clk(clk), .in_a(a10_30to10_31), .in_b(b9_31to10_31), .out_a(a10_31to10_32), .out_b(b10_31to11_31), .out_c(matrixC10_31)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe11_16(.reset(effective_rst), .clk(clk), .in_a(a11_15to11_16), .in_b(b10_16to11_16), .out_a(a11_16to11_17), .out_b(b11_16to12_16), .out_c(matrixC11_16)); +processing_element pe11_17(.reset(effective_rst), .clk(clk), .in_a(a11_16to11_17), .in_b(b10_17to11_17), .out_a(a11_17to11_18), .out_b(b11_17to12_17), .out_c(matrixC11_17)); +processing_element pe11_18(.reset(effective_rst), .clk(clk), .in_a(a11_17to11_18), .in_b(b10_18to11_18), .out_a(a11_18to11_19), .out_b(b11_18to12_18), .out_c(matrixC11_18)); +processing_element pe11_19(.reset(effective_rst), .clk(clk), .in_a(a11_18to11_19), .in_b(b10_19to11_19), .out_a(a11_19to11_20), .out_b(b11_19to12_19), .out_c(matrixC11_19)); +processing_element pe11_20(.reset(effective_rst), .clk(clk), .in_a(a11_19to11_20), .in_b(b10_20to11_20), .out_a(a11_20to11_21), .out_b(b11_20to12_20), .out_c(matrixC11_20)); +processing_element pe11_21(.reset(effective_rst), .clk(clk), .in_a(a11_20to11_21), .in_b(b10_21to11_21), .out_a(a11_21to11_22), .out_b(b11_21to12_21), .out_c(matrixC11_21)); +processing_element pe11_22(.reset(effective_rst), .clk(clk), .in_a(a11_21to11_22), .in_b(b10_22to11_22), .out_a(a11_22to11_23), .out_b(b11_22to12_22), .out_c(matrixC11_22)); +processing_element pe11_23(.reset(effective_rst), .clk(clk), .in_a(a11_22to11_23), .in_b(b10_23to11_23), .out_a(a11_23to11_24), .out_b(b11_23to12_23), .out_c(matrixC11_23)); +processing_element pe11_24(.reset(effective_rst), .clk(clk), .in_a(a11_23to11_24), .in_b(b10_24to11_24), .out_a(a11_24to11_25), .out_b(b11_24to12_24), .out_c(matrixC11_24)); +processing_element pe11_25(.reset(effective_rst), .clk(clk), .in_a(a11_24to11_25), .in_b(b10_25to11_25), .out_a(a11_25to11_26), .out_b(b11_25to12_25), .out_c(matrixC11_25)); +processing_element pe11_26(.reset(effective_rst), .clk(clk), .in_a(a11_25to11_26), .in_b(b10_26to11_26), .out_a(a11_26to11_27), .out_b(b11_26to12_26), .out_c(matrixC11_26)); +processing_element pe11_27(.reset(effective_rst), .clk(clk), .in_a(a11_26to11_27), .in_b(b10_27to11_27), .out_a(a11_27to11_28), .out_b(b11_27to12_27), .out_c(matrixC11_27)); +processing_element pe11_28(.reset(effective_rst), .clk(clk), .in_a(a11_27to11_28), .in_b(b10_28to11_28), .out_a(a11_28to11_29), .out_b(b11_28to12_28), .out_c(matrixC11_28)); +processing_element pe11_29(.reset(effective_rst), .clk(clk), .in_a(a11_28to11_29), .in_b(b10_29to11_29), .out_a(a11_29to11_30), .out_b(b11_29to12_29), .out_c(matrixC11_29)); +processing_element pe11_30(.reset(effective_rst), .clk(clk), .in_a(a11_29to11_30), .in_b(b10_30to11_30), .out_a(a11_30to11_31), .out_b(b11_30to12_30), .out_c(matrixC11_30)); +processing_element pe11_31(.reset(effective_rst), .clk(clk), .in_a(a11_30to11_31), .in_b(b10_31to11_31), .out_a(a11_31to11_32), .out_b(b11_31to12_31), .out_c(matrixC11_31)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe12_16(.reset(effective_rst), .clk(clk), .in_a(a12_15to12_16), .in_b(b11_16to12_16), .out_a(a12_16to12_17), .out_b(b12_16to13_16), .out_c(matrixC12_16)); +processing_element pe12_17(.reset(effective_rst), .clk(clk), .in_a(a12_16to12_17), .in_b(b11_17to12_17), .out_a(a12_17to12_18), .out_b(b12_17to13_17), .out_c(matrixC12_17)); +processing_element pe12_18(.reset(effective_rst), .clk(clk), .in_a(a12_17to12_18), .in_b(b11_18to12_18), .out_a(a12_18to12_19), .out_b(b12_18to13_18), .out_c(matrixC12_18)); +processing_element pe12_19(.reset(effective_rst), .clk(clk), .in_a(a12_18to12_19), .in_b(b11_19to12_19), .out_a(a12_19to12_20), .out_b(b12_19to13_19), .out_c(matrixC12_19)); +processing_element pe12_20(.reset(effective_rst), .clk(clk), .in_a(a12_19to12_20), .in_b(b11_20to12_20), .out_a(a12_20to12_21), .out_b(b12_20to13_20), .out_c(matrixC12_20)); +processing_element pe12_21(.reset(effective_rst), .clk(clk), .in_a(a12_20to12_21), .in_b(b11_21to12_21), .out_a(a12_21to12_22), .out_b(b12_21to13_21), .out_c(matrixC12_21)); +processing_element pe12_22(.reset(effective_rst), .clk(clk), .in_a(a12_21to12_22), .in_b(b11_22to12_22), .out_a(a12_22to12_23), .out_b(b12_22to13_22), .out_c(matrixC12_22)); +processing_element pe12_23(.reset(effective_rst), .clk(clk), .in_a(a12_22to12_23), .in_b(b11_23to12_23), .out_a(a12_23to12_24), .out_b(b12_23to13_23), .out_c(matrixC12_23)); +processing_element pe12_24(.reset(effective_rst), .clk(clk), .in_a(a12_23to12_24), .in_b(b11_24to12_24), .out_a(a12_24to12_25), .out_b(b12_24to13_24), .out_c(matrixC12_24)); +processing_element pe12_25(.reset(effective_rst), .clk(clk), .in_a(a12_24to12_25), .in_b(b11_25to12_25), .out_a(a12_25to12_26), .out_b(b12_25to13_25), .out_c(matrixC12_25)); +processing_element pe12_26(.reset(effective_rst), .clk(clk), .in_a(a12_25to12_26), .in_b(b11_26to12_26), .out_a(a12_26to12_27), .out_b(b12_26to13_26), .out_c(matrixC12_26)); +processing_element pe12_27(.reset(effective_rst), .clk(clk), .in_a(a12_26to12_27), .in_b(b11_27to12_27), .out_a(a12_27to12_28), .out_b(b12_27to13_27), .out_c(matrixC12_27)); +processing_element pe12_28(.reset(effective_rst), .clk(clk), .in_a(a12_27to12_28), .in_b(b11_28to12_28), .out_a(a12_28to12_29), .out_b(b12_28to13_28), .out_c(matrixC12_28)); +processing_element pe12_29(.reset(effective_rst), .clk(clk), .in_a(a12_28to12_29), .in_b(b11_29to12_29), .out_a(a12_29to12_30), .out_b(b12_29to13_29), .out_c(matrixC12_29)); +processing_element pe12_30(.reset(effective_rst), .clk(clk), .in_a(a12_29to12_30), .in_b(b11_30to12_30), .out_a(a12_30to12_31), .out_b(b12_30to13_30), .out_c(matrixC12_30)); +processing_element pe12_31(.reset(effective_rst), .clk(clk), .in_a(a12_30to12_31), .in_b(b11_31to12_31), .out_a(a12_31to12_32), .out_b(b12_31to13_31), .out_c(matrixC12_31)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe13_16(.reset(effective_rst), .clk(clk), .in_a(a13_15to13_16), .in_b(b12_16to13_16), .out_a(a13_16to13_17), .out_b(b13_16to14_16), .out_c(matrixC13_16)); +processing_element pe13_17(.reset(effective_rst), .clk(clk), .in_a(a13_16to13_17), .in_b(b12_17to13_17), .out_a(a13_17to13_18), .out_b(b13_17to14_17), .out_c(matrixC13_17)); +processing_element pe13_18(.reset(effective_rst), .clk(clk), .in_a(a13_17to13_18), .in_b(b12_18to13_18), .out_a(a13_18to13_19), .out_b(b13_18to14_18), .out_c(matrixC13_18)); +processing_element pe13_19(.reset(effective_rst), .clk(clk), .in_a(a13_18to13_19), .in_b(b12_19to13_19), .out_a(a13_19to13_20), .out_b(b13_19to14_19), .out_c(matrixC13_19)); +processing_element pe13_20(.reset(effective_rst), .clk(clk), .in_a(a13_19to13_20), .in_b(b12_20to13_20), .out_a(a13_20to13_21), .out_b(b13_20to14_20), .out_c(matrixC13_20)); +processing_element pe13_21(.reset(effective_rst), .clk(clk), .in_a(a13_20to13_21), .in_b(b12_21to13_21), .out_a(a13_21to13_22), .out_b(b13_21to14_21), .out_c(matrixC13_21)); +processing_element pe13_22(.reset(effective_rst), .clk(clk), .in_a(a13_21to13_22), .in_b(b12_22to13_22), .out_a(a13_22to13_23), .out_b(b13_22to14_22), .out_c(matrixC13_22)); +processing_element pe13_23(.reset(effective_rst), .clk(clk), .in_a(a13_22to13_23), .in_b(b12_23to13_23), .out_a(a13_23to13_24), .out_b(b13_23to14_23), .out_c(matrixC13_23)); +processing_element pe13_24(.reset(effective_rst), .clk(clk), .in_a(a13_23to13_24), .in_b(b12_24to13_24), .out_a(a13_24to13_25), .out_b(b13_24to14_24), .out_c(matrixC13_24)); +processing_element pe13_25(.reset(effective_rst), .clk(clk), .in_a(a13_24to13_25), .in_b(b12_25to13_25), .out_a(a13_25to13_26), .out_b(b13_25to14_25), .out_c(matrixC13_25)); +processing_element pe13_26(.reset(effective_rst), .clk(clk), .in_a(a13_25to13_26), .in_b(b12_26to13_26), .out_a(a13_26to13_27), .out_b(b13_26to14_26), .out_c(matrixC13_26)); +processing_element pe13_27(.reset(effective_rst), .clk(clk), .in_a(a13_26to13_27), .in_b(b12_27to13_27), .out_a(a13_27to13_28), .out_b(b13_27to14_27), .out_c(matrixC13_27)); +processing_element pe13_28(.reset(effective_rst), .clk(clk), .in_a(a13_27to13_28), .in_b(b12_28to13_28), .out_a(a13_28to13_29), .out_b(b13_28to14_28), .out_c(matrixC13_28)); +processing_element pe13_29(.reset(effective_rst), .clk(clk), .in_a(a13_28to13_29), .in_b(b12_29to13_29), .out_a(a13_29to13_30), .out_b(b13_29to14_29), .out_c(matrixC13_29)); +processing_element pe13_30(.reset(effective_rst), .clk(clk), .in_a(a13_29to13_30), .in_b(b12_30to13_30), .out_a(a13_30to13_31), .out_b(b13_30to14_30), .out_c(matrixC13_30)); +processing_element pe13_31(.reset(effective_rst), .clk(clk), .in_a(a13_30to13_31), .in_b(b12_31to13_31), .out_a(a13_31to13_32), .out_b(b13_31to14_31), .out_c(matrixC13_31)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe14_16(.reset(effective_rst), .clk(clk), .in_a(a14_15to14_16), .in_b(b13_16to14_16), .out_a(a14_16to14_17), .out_b(b14_16to15_16), .out_c(matrixC14_16)); +processing_element pe14_17(.reset(effective_rst), .clk(clk), .in_a(a14_16to14_17), .in_b(b13_17to14_17), .out_a(a14_17to14_18), .out_b(b14_17to15_17), .out_c(matrixC14_17)); +processing_element pe14_18(.reset(effective_rst), .clk(clk), .in_a(a14_17to14_18), .in_b(b13_18to14_18), .out_a(a14_18to14_19), .out_b(b14_18to15_18), .out_c(matrixC14_18)); +processing_element pe14_19(.reset(effective_rst), .clk(clk), .in_a(a14_18to14_19), .in_b(b13_19to14_19), .out_a(a14_19to14_20), .out_b(b14_19to15_19), .out_c(matrixC14_19)); +processing_element pe14_20(.reset(effective_rst), .clk(clk), .in_a(a14_19to14_20), .in_b(b13_20to14_20), .out_a(a14_20to14_21), .out_b(b14_20to15_20), .out_c(matrixC14_20)); +processing_element pe14_21(.reset(effective_rst), .clk(clk), .in_a(a14_20to14_21), .in_b(b13_21to14_21), .out_a(a14_21to14_22), .out_b(b14_21to15_21), .out_c(matrixC14_21)); +processing_element pe14_22(.reset(effective_rst), .clk(clk), .in_a(a14_21to14_22), .in_b(b13_22to14_22), .out_a(a14_22to14_23), .out_b(b14_22to15_22), .out_c(matrixC14_22)); +processing_element pe14_23(.reset(effective_rst), .clk(clk), .in_a(a14_22to14_23), .in_b(b13_23to14_23), .out_a(a14_23to14_24), .out_b(b14_23to15_23), .out_c(matrixC14_23)); +processing_element pe14_24(.reset(effective_rst), .clk(clk), .in_a(a14_23to14_24), .in_b(b13_24to14_24), .out_a(a14_24to14_25), .out_b(b14_24to15_24), .out_c(matrixC14_24)); +processing_element pe14_25(.reset(effective_rst), .clk(clk), .in_a(a14_24to14_25), .in_b(b13_25to14_25), .out_a(a14_25to14_26), .out_b(b14_25to15_25), .out_c(matrixC14_25)); +processing_element pe14_26(.reset(effective_rst), .clk(clk), .in_a(a14_25to14_26), .in_b(b13_26to14_26), .out_a(a14_26to14_27), .out_b(b14_26to15_26), .out_c(matrixC14_26)); +processing_element pe14_27(.reset(effective_rst), .clk(clk), .in_a(a14_26to14_27), .in_b(b13_27to14_27), .out_a(a14_27to14_28), .out_b(b14_27to15_27), .out_c(matrixC14_27)); +processing_element pe14_28(.reset(effective_rst), .clk(clk), .in_a(a14_27to14_28), .in_b(b13_28to14_28), .out_a(a14_28to14_29), .out_b(b14_28to15_28), .out_c(matrixC14_28)); +processing_element pe14_29(.reset(effective_rst), .clk(clk), .in_a(a14_28to14_29), .in_b(b13_29to14_29), .out_a(a14_29to14_30), .out_b(b14_29to15_29), .out_c(matrixC14_29)); +processing_element pe14_30(.reset(effective_rst), .clk(clk), .in_a(a14_29to14_30), .in_b(b13_30to14_30), .out_a(a14_30to14_31), .out_b(b14_30to15_30), .out_c(matrixC14_30)); +processing_element pe14_31(.reset(effective_rst), .clk(clk), .in_a(a14_30to14_31), .in_b(b13_31to14_31), .out_a(a14_31to14_32), .out_b(b14_31to15_31), .out_c(matrixC14_31)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +processing_element pe15_16(.reset(effective_rst), .clk(clk), .in_a(a15_15to15_16), .in_b(b14_16to15_16), .out_a(a15_16to15_17), .out_b(b15_16to16_16), .out_c(matrixC15_16)); +processing_element pe15_17(.reset(effective_rst), .clk(clk), .in_a(a15_16to15_17), .in_b(b14_17to15_17), .out_a(a15_17to15_18), .out_b(b15_17to16_17), .out_c(matrixC15_17)); +processing_element pe15_18(.reset(effective_rst), .clk(clk), .in_a(a15_17to15_18), .in_b(b14_18to15_18), .out_a(a15_18to15_19), .out_b(b15_18to16_18), .out_c(matrixC15_18)); +processing_element pe15_19(.reset(effective_rst), .clk(clk), .in_a(a15_18to15_19), .in_b(b14_19to15_19), .out_a(a15_19to15_20), .out_b(b15_19to16_19), .out_c(matrixC15_19)); +processing_element pe15_20(.reset(effective_rst), .clk(clk), .in_a(a15_19to15_20), .in_b(b14_20to15_20), .out_a(a15_20to15_21), .out_b(b15_20to16_20), .out_c(matrixC15_20)); +processing_element pe15_21(.reset(effective_rst), .clk(clk), .in_a(a15_20to15_21), .in_b(b14_21to15_21), .out_a(a15_21to15_22), .out_b(b15_21to16_21), .out_c(matrixC15_21)); +processing_element pe15_22(.reset(effective_rst), .clk(clk), .in_a(a15_21to15_22), .in_b(b14_22to15_22), .out_a(a15_22to15_23), .out_b(b15_22to16_22), .out_c(matrixC15_22)); +processing_element pe15_23(.reset(effective_rst), .clk(clk), .in_a(a15_22to15_23), .in_b(b14_23to15_23), .out_a(a15_23to15_24), .out_b(b15_23to16_23), .out_c(matrixC15_23)); +processing_element pe15_24(.reset(effective_rst), .clk(clk), .in_a(a15_23to15_24), .in_b(b14_24to15_24), .out_a(a15_24to15_25), .out_b(b15_24to16_24), .out_c(matrixC15_24)); +processing_element pe15_25(.reset(effective_rst), .clk(clk), .in_a(a15_24to15_25), .in_b(b14_25to15_25), .out_a(a15_25to15_26), .out_b(b15_25to16_25), .out_c(matrixC15_25)); +processing_element pe15_26(.reset(effective_rst), .clk(clk), .in_a(a15_25to15_26), .in_b(b14_26to15_26), .out_a(a15_26to15_27), .out_b(b15_26to16_26), .out_c(matrixC15_26)); +processing_element pe15_27(.reset(effective_rst), .clk(clk), .in_a(a15_26to15_27), .in_b(b14_27to15_27), .out_a(a15_27to15_28), .out_b(b15_27to16_27), .out_c(matrixC15_27)); +processing_element pe15_28(.reset(effective_rst), .clk(clk), .in_a(a15_27to15_28), .in_b(b14_28to15_28), .out_a(a15_28to15_29), .out_b(b15_28to16_28), .out_c(matrixC15_28)); +processing_element pe15_29(.reset(effective_rst), .clk(clk), .in_a(a15_28to15_29), .in_b(b14_29to15_29), .out_a(a15_29to15_30), .out_b(b15_29to16_29), .out_c(matrixC15_29)); +processing_element pe15_30(.reset(effective_rst), .clk(clk), .in_a(a15_29to15_30), .in_b(b14_30to15_30), .out_a(a15_30to15_31), .out_b(b15_30to16_30), .out_c(matrixC15_30)); +processing_element pe15_31(.reset(effective_rst), .clk(clk), .in_a(a15_30to15_31), .in_b(b14_31to15_31), .out_a(a15_31to15_32), .out_b(b15_31to16_31), .out_c(matrixC15_31)); +processing_element pe16_1(.reset(effective_rst), .clk(clk), .in_a(a16_0to16_1), .in_b(b15_1to16_1), .out_a(a16_1to16_2), .out_b(b16_1to17_1), .out_c(matrixC16_1)); +processing_element pe16_2(.reset(effective_rst), .clk(clk), .in_a(a16_1to16_2), .in_b(b15_2to16_2), .out_a(a16_2to16_3), .out_b(b16_2to17_2), .out_c(matrixC16_2)); +processing_element pe16_3(.reset(effective_rst), .clk(clk), .in_a(a16_2to16_3), .in_b(b15_3to16_3), .out_a(a16_3to16_4), .out_b(b16_3to17_3), .out_c(matrixC16_3)); +processing_element pe16_4(.reset(effective_rst), .clk(clk), .in_a(a16_3to16_4), .in_b(b15_4to16_4), .out_a(a16_4to16_5), .out_b(b16_4to17_4), .out_c(matrixC16_4)); +processing_element pe16_5(.reset(effective_rst), .clk(clk), .in_a(a16_4to16_5), .in_b(b15_5to16_5), .out_a(a16_5to16_6), .out_b(b16_5to17_5), .out_c(matrixC16_5)); +processing_element pe16_6(.reset(effective_rst), .clk(clk), .in_a(a16_5to16_6), .in_b(b15_6to16_6), .out_a(a16_6to16_7), .out_b(b16_6to17_6), .out_c(matrixC16_6)); +processing_element pe16_7(.reset(effective_rst), .clk(clk), .in_a(a16_6to16_7), .in_b(b15_7to16_7), .out_a(a16_7to16_8), .out_b(b16_7to17_7), .out_c(matrixC16_7)); +processing_element pe16_8(.reset(effective_rst), .clk(clk), .in_a(a16_7to16_8), .in_b(b15_8to16_8), .out_a(a16_8to16_9), .out_b(b16_8to17_8), .out_c(matrixC16_8)); +processing_element pe16_9(.reset(effective_rst), .clk(clk), .in_a(a16_8to16_9), .in_b(b15_9to16_9), .out_a(a16_9to16_10), .out_b(b16_9to17_9), .out_c(matrixC16_9)); +processing_element pe16_10(.reset(effective_rst), .clk(clk), .in_a(a16_9to16_10), .in_b(b15_10to16_10), .out_a(a16_10to16_11), .out_b(b16_10to17_10), .out_c(matrixC16_10)); +processing_element pe16_11(.reset(effective_rst), .clk(clk), .in_a(a16_10to16_11), .in_b(b15_11to16_11), .out_a(a16_11to16_12), .out_b(b16_11to17_11), .out_c(matrixC16_11)); +processing_element pe16_12(.reset(effective_rst), .clk(clk), .in_a(a16_11to16_12), .in_b(b15_12to16_12), .out_a(a16_12to16_13), .out_b(b16_12to17_12), .out_c(matrixC16_12)); +processing_element pe16_13(.reset(effective_rst), .clk(clk), .in_a(a16_12to16_13), .in_b(b15_13to16_13), .out_a(a16_13to16_14), .out_b(b16_13to17_13), .out_c(matrixC16_13)); +processing_element pe16_14(.reset(effective_rst), .clk(clk), .in_a(a16_13to16_14), .in_b(b15_14to16_14), .out_a(a16_14to16_15), .out_b(b16_14to17_14), .out_c(matrixC16_14)); +processing_element pe16_15(.reset(effective_rst), .clk(clk), .in_a(a16_14to16_15), .in_b(b15_15to16_15), .out_a(a16_15to16_16), .out_b(b16_15to17_15), .out_c(matrixC16_15)); +processing_element pe16_16(.reset(effective_rst), .clk(clk), .in_a(a16_15to16_16), .in_b(b15_16to16_16), .out_a(a16_16to16_17), .out_b(b16_16to17_16), .out_c(matrixC16_16)); +processing_element pe16_17(.reset(effective_rst), .clk(clk), .in_a(a16_16to16_17), .in_b(b15_17to16_17), .out_a(a16_17to16_18), .out_b(b16_17to17_17), .out_c(matrixC16_17)); +processing_element pe16_18(.reset(effective_rst), .clk(clk), .in_a(a16_17to16_18), .in_b(b15_18to16_18), .out_a(a16_18to16_19), .out_b(b16_18to17_18), .out_c(matrixC16_18)); +processing_element pe16_19(.reset(effective_rst), .clk(clk), .in_a(a16_18to16_19), .in_b(b15_19to16_19), .out_a(a16_19to16_20), .out_b(b16_19to17_19), .out_c(matrixC16_19)); +processing_element pe16_20(.reset(effective_rst), .clk(clk), .in_a(a16_19to16_20), .in_b(b15_20to16_20), .out_a(a16_20to16_21), .out_b(b16_20to17_20), .out_c(matrixC16_20)); +processing_element pe16_21(.reset(effective_rst), .clk(clk), .in_a(a16_20to16_21), .in_b(b15_21to16_21), .out_a(a16_21to16_22), .out_b(b16_21to17_21), .out_c(matrixC16_21)); +processing_element pe16_22(.reset(effective_rst), .clk(clk), .in_a(a16_21to16_22), .in_b(b15_22to16_22), .out_a(a16_22to16_23), .out_b(b16_22to17_22), .out_c(matrixC16_22)); +processing_element pe16_23(.reset(effective_rst), .clk(clk), .in_a(a16_22to16_23), .in_b(b15_23to16_23), .out_a(a16_23to16_24), .out_b(b16_23to17_23), .out_c(matrixC16_23)); +processing_element pe16_24(.reset(effective_rst), .clk(clk), .in_a(a16_23to16_24), .in_b(b15_24to16_24), .out_a(a16_24to16_25), .out_b(b16_24to17_24), .out_c(matrixC16_24)); +processing_element pe16_25(.reset(effective_rst), .clk(clk), .in_a(a16_24to16_25), .in_b(b15_25to16_25), .out_a(a16_25to16_26), .out_b(b16_25to17_25), .out_c(matrixC16_25)); +processing_element pe16_26(.reset(effective_rst), .clk(clk), .in_a(a16_25to16_26), .in_b(b15_26to16_26), .out_a(a16_26to16_27), .out_b(b16_26to17_26), .out_c(matrixC16_26)); +processing_element pe16_27(.reset(effective_rst), .clk(clk), .in_a(a16_26to16_27), .in_b(b15_27to16_27), .out_a(a16_27to16_28), .out_b(b16_27to17_27), .out_c(matrixC16_27)); +processing_element pe16_28(.reset(effective_rst), .clk(clk), .in_a(a16_27to16_28), .in_b(b15_28to16_28), .out_a(a16_28to16_29), .out_b(b16_28to17_28), .out_c(matrixC16_28)); +processing_element pe16_29(.reset(effective_rst), .clk(clk), .in_a(a16_28to16_29), .in_b(b15_29to16_29), .out_a(a16_29to16_30), .out_b(b16_29to17_29), .out_c(matrixC16_29)); +processing_element pe16_30(.reset(effective_rst), .clk(clk), .in_a(a16_29to16_30), .in_b(b15_30to16_30), .out_a(a16_30to16_31), .out_b(b16_30to17_30), .out_c(matrixC16_30)); +processing_element pe16_31(.reset(effective_rst), .clk(clk), .in_a(a16_30to16_31), .in_b(b15_31to16_31), .out_a(a16_31to16_32), .out_b(b16_31to17_31), .out_c(matrixC16_31)); +processing_element pe17_1(.reset(effective_rst), .clk(clk), .in_a(a17_0to17_1), .in_b(b16_1to17_1), .out_a(a17_1to17_2), .out_b(b17_1to18_1), .out_c(matrixC17_1)); +processing_element pe17_2(.reset(effective_rst), .clk(clk), .in_a(a17_1to17_2), .in_b(b16_2to17_2), .out_a(a17_2to17_3), .out_b(b17_2to18_2), .out_c(matrixC17_2)); +processing_element pe17_3(.reset(effective_rst), .clk(clk), .in_a(a17_2to17_3), .in_b(b16_3to17_3), .out_a(a17_3to17_4), .out_b(b17_3to18_3), .out_c(matrixC17_3)); +processing_element pe17_4(.reset(effective_rst), .clk(clk), .in_a(a17_3to17_4), .in_b(b16_4to17_4), .out_a(a17_4to17_5), .out_b(b17_4to18_4), .out_c(matrixC17_4)); +processing_element pe17_5(.reset(effective_rst), .clk(clk), .in_a(a17_4to17_5), .in_b(b16_5to17_5), .out_a(a17_5to17_6), .out_b(b17_5to18_5), .out_c(matrixC17_5)); +processing_element pe17_6(.reset(effective_rst), .clk(clk), .in_a(a17_5to17_6), .in_b(b16_6to17_6), .out_a(a17_6to17_7), .out_b(b17_6to18_6), .out_c(matrixC17_6)); +processing_element pe17_7(.reset(effective_rst), .clk(clk), .in_a(a17_6to17_7), .in_b(b16_7to17_7), .out_a(a17_7to17_8), .out_b(b17_7to18_7), .out_c(matrixC17_7)); +processing_element pe17_8(.reset(effective_rst), .clk(clk), .in_a(a17_7to17_8), .in_b(b16_8to17_8), .out_a(a17_8to17_9), .out_b(b17_8to18_8), .out_c(matrixC17_8)); +processing_element pe17_9(.reset(effective_rst), .clk(clk), .in_a(a17_8to17_9), .in_b(b16_9to17_9), .out_a(a17_9to17_10), .out_b(b17_9to18_9), .out_c(matrixC17_9)); +processing_element pe17_10(.reset(effective_rst), .clk(clk), .in_a(a17_9to17_10), .in_b(b16_10to17_10), .out_a(a17_10to17_11), .out_b(b17_10to18_10), .out_c(matrixC17_10)); +processing_element pe17_11(.reset(effective_rst), .clk(clk), .in_a(a17_10to17_11), .in_b(b16_11to17_11), .out_a(a17_11to17_12), .out_b(b17_11to18_11), .out_c(matrixC17_11)); +processing_element pe17_12(.reset(effective_rst), .clk(clk), .in_a(a17_11to17_12), .in_b(b16_12to17_12), .out_a(a17_12to17_13), .out_b(b17_12to18_12), .out_c(matrixC17_12)); +processing_element pe17_13(.reset(effective_rst), .clk(clk), .in_a(a17_12to17_13), .in_b(b16_13to17_13), .out_a(a17_13to17_14), .out_b(b17_13to18_13), .out_c(matrixC17_13)); +processing_element pe17_14(.reset(effective_rst), .clk(clk), .in_a(a17_13to17_14), .in_b(b16_14to17_14), .out_a(a17_14to17_15), .out_b(b17_14to18_14), .out_c(matrixC17_14)); +processing_element pe17_15(.reset(effective_rst), .clk(clk), .in_a(a17_14to17_15), .in_b(b16_15to17_15), .out_a(a17_15to17_16), .out_b(b17_15to18_15), .out_c(matrixC17_15)); +processing_element pe17_16(.reset(effective_rst), .clk(clk), .in_a(a17_15to17_16), .in_b(b16_16to17_16), .out_a(a17_16to17_17), .out_b(b17_16to18_16), .out_c(matrixC17_16)); +processing_element pe17_17(.reset(effective_rst), .clk(clk), .in_a(a17_16to17_17), .in_b(b16_17to17_17), .out_a(a17_17to17_18), .out_b(b17_17to18_17), .out_c(matrixC17_17)); +processing_element pe17_18(.reset(effective_rst), .clk(clk), .in_a(a17_17to17_18), .in_b(b16_18to17_18), .out_a(a17_18to17_19), .out_b(b17_18to18_18), .out_c(matrixC17_18)); +processing_element pe17_19(.reset(effective_rst), .clk(clk), .in_a(a17_18to17_19), .in_b(b16_19to17_19), .out_a(a17_19to17_20), .out_b(b17_19to18_19), .out_c(matrixC17_19)); +processing_element pe17_20(.reset(effective_rst), .clk(clk), .in_a(a17_19to17_20), .in_b(b16_20to17_20), .out_a(a17_20to17_21), .out_b(b17_20to18_20), .out_c(matrixC17_20)); +processing_element pe17_21(.reset(effective_rst), .clk(clk), .in_a(a17_20to17_21), .in_b(b16_21to17_21), .out_a(a17_21to17_22), .out_b(b17_21to18_21), .out_c(matrixC17_21)); +processing_element pe17_22(.reset(effective_rst), .clk(clk), .in_a(a17_21to17_22), .in_b(b16_22to17_22), .out_a(a17_22to17_23), .out_b(b17_22to18_22), .out_c(matrixC17_22)); +processing_element pe17_23(.reset(effective_rst), .clk(clk), .in_a(a17_22to17_23), .in_b(b16_23to17_23), .out_a(a17_23to17_24), .out_b(b17_23to18_23), .out_c(matrixC17_23)); +processing_element pe17_24(.reset(effective_rst), .clk(clk), .in_a(a17_23to17_24), .in_b(b16_24to17_24), .out_a(a17_24to17_25), .out_b(b17_24to18_24), .out_c(matrixC17_24)); +processing_element pe17_25(.reset(effective_rst), .clk(clk), .in_a(a17_24to17_25), .in_b(b16_25to17_25), .out_a(a17_25to17_26), .out_b(b17_25to18_25), .out_c(matrixC17_25)); +processing_element pe17_26(.reset(effective_rst), .clk(clk), .in_a(a17_25to17_26), .in_b(b16_26to17_26), .out_a(a17_26to17_27), .out_b(b17_26to18_26), .out_c(matrixC17_26)); +processing_element pe17_27(.reset(effective_rst), .clk(clk), .in_a(a17_26to17_27), .in_b(b16_27to17_27), .out_a(a17_27to17_28), .out_b(b17_27to18_27), .out_c(matrixC17_27)); +processing_element pe17_28(.reset(effective_rst), .clk(clk), .in_a(a17_27to17_28), .in_b(b16_28to17_28), .out_a(a17_28to17_29), .out_b(b17_28to18_28), .out_c(matrixC17_28)); +processing_element pe17_29(.reset(effective_rst), .clk(clk), .in_a(a17_28to17_29), .in_b(b16_29to17_29), .out_a(a17_29to17_30), .out_b(b17_29to18_29), .out_c(matrixC17_29)); +processing_element pe17_30(.reset(effective_rst), .clk(clk), .in_a(a17_29to17_30), .in_b(b16_30to17_30), .out_a(a17_30to17_31), .out_b(b17_30to18_30), .out_c(matrixC17_30)); +processing_element pe17_31(.reset(effective_rst), .clk(clk), .in_a(a17_30to17_31), .in_b(b16_31to17_31), .out_a(a17_31to17_32), .out_b(b17_31to18_31), .out_c(matrixC17_31)); +processing_element pe18_1(.reset(effective_rst), .clk(clk), .in_a(a18_0to18_1), .in_b(b17_1to18_1), .out_a(a18_1to18_2), .out_b(b18_1to19_1), .out_c(matrixC18_1)); +processing_element pe18_2(.reset(effective_rst), .clk(clk), .in_a(a18_1to18_2), .in_b(b17_2to18_2), .out_a(a18_2to18_3), .out_b(b18_2to19_2), .out_c(matrixC18_2)); +processing_element pe18_3(.reset(effective_rst), .clk(clk), .in_a(a18_2to18_3), .in_b(b17_3to18_3), .out_a(a18_3to18_4), .out_b(b18_3to19_3), .out_c(matrixC18_3)); +processing_element pe18_4(.reset(effective_rst), .clk(clk), .in_a(a18_3to18_4), .in_b(b17_4to18_4), .out_a(a18_4to18_5), .out_b(b18_4to19_4), .out_c(matrixC18_4)); +processing_element pe18_5(.reset(effective_rst), .clk(clk), .in_a(a18_4to18_5), .in_b(b17_5to18_5), .out_a(a18_5to18_6), .out_b(b18_5to19_5), .out_c(matrixC18_5)); +processing_element pe18_6(.reset(effective_rst), .clk(clk), .in_a(a18_5to18_6), .in_b(b17_6to18_6), .out_a(a18_6to18_7), .out_b(b18_6to19_6), .out_c(matrixC18_6)); +processing_element pe18_7(.reset(effective_rst), .clk(clk), .in_a(a18_6to18_7), .in_b(b17_7to18_7), .out_a(a18_7to18_8), .out_b(b18_7to19_7), .out_c(matrixC18_7)); +processing_element pe18_8(.reset(effective_rst), .clk(clk), .in_a(a18_7to18_8), .in_b(b17_8to18_8), .out_a(a18_8to18_9), .out_b(b18_8to19_8), .out_c(matrixC18_8)); +processing_element pe18_9(.reset(effective_rst), .clk(clk), .in_a(a18_8to18_9), .in_b(b17_9to18_9), .out_a(a18_9to18_10), .out_b(b18_9to19_9), .out_c(matrixC18_9)); +processing_element pe18_10(.reset(effective_rst), .clk(clk), .in_a(a18_9to18_10), .in_b(b17_10to18_10), .out_a(a18_10to18_11), .out_b(b18_10to19_10), .out_c(matrixC18_10)); +processing_element pe18_11(.reset(effective_rst), .clk(clk), .in_a(a18_10to18_11), .in_b(b17_11to18_11), .out_a(a18_11to18_12), .out_b(b18_11to19_11), .out_c(matrixC18_11)); +processing_element pe18_12(.reset(effective_rst), .clk(clk), .in_a(a18_11to18_12), .in_b(b17_12to18_12), .out_a(a18_12to18_13), .out_b(b18_12to19_12), .out_c(matrixC18_12)); +processing_element pe18_13(.reset(effective_rst), .clk(clk), .in_a(a18_12to18_13), .in_b(b17_13to18_13), .out_a(a18_13to18_14), .out_b(b18_13to19_13), .out_c(matrixC18_13)); +processing_element pe18_14(.reset(effective_rst), .clk(clk), .in_a(a18_13to18_14), .in_b(b17_14to18_14), .out_a(a18_14to18_15), .out_b(b18_14to19_14), .out_c(matrixC18_14)); +processing_element pe18_15(.reset(effective_rst), .clk(clk), .in_a(a18_14to18_15), .in_b(b17_15to18_15), .out_a(a18_15to18_16), .out_b(b18_15to19_15), .out_c(matrixC18_15)); +processing_element pe18_16(.reset(effective_rst), .clk(clk), .in_a(a18_15to18_16), .in_b(b17_16to18_16), .out_a(a18_16to18_17), .out_b(b18_16to19_16), .out_c(matrixC18_16)); +processing_element pe18_17(.reset(effective_rst), .clk(clk), .in_a(a18_16to18_17), .in_b(b17_17to18_17), .out_a(a18_17to18_18), .out_b(b18_17to19_17), .out_c(matrixC18_17)); +processing_element pe18_18(.reset(effective_rst), .clk(clk), .in_a(a18_17to18_18), .in_b(b17_18to18_18), .out_a(a18_18to18_19), .out_b(b18_18to19_18), .out_c(matrixC18_18)); +processing_element pe18_19(.reset(effective_rst), .clk(clk), .in_a(a18_18to18_19), .in_b(b17_19to18_19), .out_a(a18_19to18_20), .out_b(b18_19to19_19), .out_c(matrixC18_19)); +processing_element pe18_20(.reset(effective_rst), .clk(clk), .in_a(a18_19to18_20), .in_b(b17_20to18_20), .out_a(a18_20to18_21), .out_b(b18_20to19_20), .out_c(matrixC18_20)); +processing_element pe18_21(.reset(effective_rst), .clk(clk), .in_a(a18_20to18_21), .in_b(b17_21to18_21), .out_a(a18_21to18_22), .out_b(b18_21to19_21), .out_c(matrixC18_21)); +processing_element pe18_22(.reset(effective_rst), .clk(clk), .in_a(a18_21to18_22), .in_b(b17_22to18_22), .out_a(a18_22to18_23), .out_b(b18_22to19_22), .out_c(matrixC18_22)); +processing_element pe18_23(.reset(effective_rst), .clk(clk), .in_a(a18_22to18_23), .in_b(b17_23to18_23), .out_a(a18_23to18_24), .out_b(b18_23to19_23), .out_c(matrixC18_23)); +processing_element pe18_24(.reset(effective_rst), .clk(clk), .in_a(a18_23to18_24), .in_b(b17_24to18_24), .out_a(a18_24to18_25), .out_b(b18_24to19_24), .out_c(matrixC18_24)); +processing_element pe18_25(.reset(effective_rst), .clk(clk), .in_a(a18_24to18_25), .in_b(b17_25to18_25), .out_a(a18_25to18_26), .out_b(b18_25to19_25), .out_c(matrixC18_25)); +processing_element pe18_26(.reset(effective_rst), .clk(clk), .in_a(a18_25to18_26), .in_b(b17_26to18_26), .out_a(a18_26to18_27), .out_b(b18_26to19_26), .out_c(matrixC18_26)); +processing_element pe18_27(.reset(effective_rst), .clk(clk), .in_a(a18_26to18_27), .in_b(b17_27to18_27), .out_a(a18_27to18_28), .out_b(b18_27to19_27), .out_c(matrixC18_27)); +processing_element pe18_28(.reset(effective_rst), .clk(clk), .in_a(a18_27to18_28), .in_b(b17_28to18_28), .out_a(a18_28to18_29), .out_b(b18_28to19_28), .out_c(matrixC18_28)); +processing_element pe18_29(.reset(effective_rst), .clk(clk), .in_a(a18_28to18_29), .in_b(b17_29to18_29), .out_a(a18_29to18_30), .out_b(b18_29to19_29), .out_c(matrixC18_29)); +processing_element pe18_30(.reset(effective_rst), .clk(clk), .in_a(a18_29to18_30), .in_b(b17_30to18_30), .out_a(a18_30to18_31), .out_b(b18_30to19_30), .out_c(matrixC18_30)); +processing_element pe18_31(.reset(effective_rst), .clk(clk), .in_a(a18_30to18_31), .in_b(b17_31to18_31), .out_a(a18_31to18_32), .out_b(b18_31to19_31), .out_c(matrixC18_31)); +processing_element pe19_1(.reset(effective_rst), .clk(clk), .in_a(a19_0to19_1), .in_b(b18_1to19_1), .out_a(a19_1to19_2), .out_b(b19_1to20_1), .out_c(matrixC19_1)); +processing_element pe19_2(.reset(effective_rst), .clk(clk), .in_a(a19_1to19_2), .in_b(b18_2to19_2), .out_a(a19_2to19_3), .out_b(b19_2to20_2), .out_c(matrixC19_2)); +processing_element pe19_3(.reset(effective_rst), .clk(clk), .in_a(a19_2to19_3), .in_b(b18_3to19_3), .out_a(a19_3to19_4), .out_b(b19_3to20_3), .out_c(matrixC19_3)); +processing_element pe19_4(.reset(effective_rst), .clk(clk), .in_a(a19_3to19_4), .in_b(b18_4to19_4), .out_a(a19_4to19_5), .out_b(b19_4to20_4), .out_c(matrixC19_4)); +processing_element pe19_5(.reset(effective_rst), .clk(clk), .in_a(a19_4to19_5), .in_b(b18_5to19_5), .out_a(a19_5to19_6), .out_b(b19_5to20_5), .out_c(matrixC19_5)); +processing_element pe19_6(.reset(effective_rst), .clk(clk), .in_a(a19_5to19_6), .in_b(b18_6to19_6), .out_a(a19_6to19_7), .out_b(b19_6to20_6), .out_c(matrixC19_6)); +processing_element pe19_7(.reset(effective_rst), .clk(clk), .in_a(a19_6to19_7), .in_b(b18_7to19_7), .out_a(a19_7to19_8), .out_b(b19_7to20_7), .out_c(matrixC19_7)); +processing_element pe19_8(.reset(effective_rst), .clk(clk), .in_a(a19_7to19_8), .in_b(b18_8to19_8), .out_a(a19_8to19_9), .out_b(b19_8to20_8), .out_c(matrixC19_8)); +processing_element pe19_9(.reset(effective_rst), .clk(clk), .in_a(a19_8to19_9), .in_b(b18_9to19_9), .out_a(a19_9to19_10), .out_b(b19_9to20_9), .out_c(matrixC19_9)); +processing_element pe19_10(.reset(effective_rst), .clk(clk), .in_a(a19_9to19_10), .in_b(b18_10to19_10), .out_a(a19_10to19_11), .out_b(b19_10to20_10), .out_c(matrixC19_10)); +processing_element pe19_11(.reset(effective_rst), .clk(clk), .in_a(a19_10to19_11), .in_b(b18_11to19_11), .out_a(a19_11to19_12), .out_b(b19_11to20_11), .out_c(matrixC19_11)); +processing_element pe19_12(.reset(effective_rst), .clk(clk), .in_a(a19_11to19_12), .in_b(b18_12to19_12), .out_a(a19_12to19_13), .out_b(b19_12to20_12), .out_c(matrixC19_12)); +processing_element pe19_13(.reset(effective_rst), .clk(clk), .in_a(a19_12to19_13), .in_b(b18_13to19_13), .out_a(a19_13to19_14), .out_b(b19_13to20_13), .out_c(matrixC19_13)); +processing_element pe19_14(.reset(effective_rst), .clk(clk), .in_a(a19_13to19_14), .in_b(b18_14to19_14), .out_a(a19_14to19_15), .out_b(b19_14to20_14), .out_c(matrixC19_14)); +processing_element pe19_15(.reset(effective_rst), .clk(clk), .in_a(a19_14to19_15), .in_b(b18_15to19_15), .out_a(a19_15to19_16), .out_b(b19_15to20_15), .out_c(matrixC19_15)); +processing_element pe19_16(.reset(effective_rst), .clk(clk), .in_a(a19_15to19_16), .in_b(b18_16to19_16), .out_a(a19_16to19_17), .out_b(b19_16to20_16), .out_c(matrixC19_16)); +processing_element pe19_17(.reset(effective_rst), .clk(clk), .in_a(a19_16to19_17), .in_b(b18_17to19_17), .out_a(a19_17to19_18), .out_b(b19_17to20_17), .out_c(matrixC19_17)); +processing_element pe19_18(.reset(effective_rst), .clk(clk), .in_a(a19_17to19_18), .in_b(b18_18to19_18), .out_a(a19_18to19_19), .out_b(b19_18to20_18), .out_c(matrixC19_18)); +processing_element pe19_19(.reset(effective_rst), .clk(clk), .in_a(a19_18to19_19), .in_b(b18_19to19_19), .out_a(a19_19to19_20), .out_b(b19_19to20_19), .out_c(matrixC19_19)); +processing_element pe19_20(.reset(effective_rst), .clk(clk), .in_a(a19_19to19_20), .in_b(b18_20to19_20), .out_a(a19_20to19_21), .out_b(b19_20to20_20), .out_c(matrixC19_20)); +processing_element pe19_21(.reset(effective_rst), .clk(clk), .in_a(a19_20to19_21), .in_b(b18_21to19_21), .out_a(a19_21to19_22), .out_b(b19_21to20_21), .out_c(matrixC19_21)); +processing_element pe19_22(.reset(effective_rst), .clk(clk), .in_a(a19_21to19_22), .in_b(b18_22to19_22), .out_a(a19_22to19_23), .out_b(b19_22to20_22), .out_c(matrixC19_22)); +processing_element pe19_23(.reset(effective_rst), .clk(clk), .in_a(a19_22to19_23), .in_b(b18_23to19_23), .out_a(a19_23to19_24), .out_b(b19_23to20_23), .out_c(matrixC19_23)); +processing_element pe19_24(.reset(effective_rst), .clk(clk), .in_a(a19_23to19_24), .in_b(b18_24to19_24), .out_a(a19_24to19_25), .out_b(b19_24to20_24), .out_c(matrixC19_24)); +processing_element pe19_25(.reset(effective_rst), .clk(clk), .in_a(a19_24to19_25), .in_b(b18_25to19_25), .out_a(a19_25to19_26), .out_b(b19_25to20_25), .out_c(matrixC19_25)); +processing_element pe19_26(.reset(effective_rst), .clk(clk), .in_a(a19_25to19_26), .in_b(b18_26to19_26), .out_a(a19_26to19_27), .out_b(b19_26to20_26), .out_c(matrixC19_26)); +processing_element pe19_27(.reset(effective_rst), .clk(clk), .in_a(a19_26to19_27), .in_b(b18_27to19_27), .out_a(a19_27to19_28), .out_b(b19_27to20_27), .out_c(matrixC19_27)); +processing_element pe19_28(.reset(effective_rst), .clk(clk), .in_a(a19_27to19_28), .in_b(b18_28to19_28), .out_a(a19_28to19_29), .out_b(b19_28to20_28), .out_c(matrixC19_28)); +processing_element pe19_29(.reset(effective_rst), .clk(clk), .in_a(a19_28to19_29), .in_b(b18_29to19_29), .out_a(a19_29to19_30), .out_b(b19_29to20_29), .out_c(matrixC19_29)); +processing_element pe19_30(.reset(effective_rst), .clk(clk), .in_a(a19_29to19_30), .in_b(b18_30to19_30), .out_a(a19_30to19_31), .out_b(b19_30to20_30), .out_c(matrixC19_30)); +processing_element pe19_31(.reset(effective_rst), .clk(clk), .in_a(a19_30to19_31), .in_b(b18_31to19_31), .out_a(a19_31to19_32), .out_b(b19_31to20_31), .out_c(matrixC19_31)); +processing_element pe20_1(.reset(effective_rst), .clk(clk), .in_a(a20_0to20_1), .in_b(b19_1to20_1), .out_a(a20_1to20_2), .out_b(b20_1to21_1), .out_c(matrixC20_1)); +processing_element pe20_2(.reset(effective_rst), .clk(clk), .in_a(a20_1to20_2), .in_b(b19_2to20_2), .out_a(a20_2to20_3), .out_b(b20_2to21_2), .out_c(matrixC20_2)); +processing_element pe20_3(.reset(effective_rst), .clk(clk), .in_a(a20_2to20_3), .in_b(b19_3to20_3), .out_a(a20_3to20_4), .out_b(b20_3to21_3), .out_c(matrixC20_3)); +processing_element pe20_4(.reset(effective_rst), .clk(clk), .in_a(a20_3to20_4), .in_b(b19_4to20_4), .out_a(a20_4to20_5), .out_b(b20_4to21_4), .out_c(matrixC20_4)); +processing_element pe20_5(.reset(effective_rst), .clk(clk), .in_a(a20_4to20_5), .in_b(b19_5to20_5), .out_a(a20_5to20_6), .out_b(b20_5to21_5), .out_c(matrixC20_5)); +processing_element pe20_6(.reset(effective_rst), .clk(clk), .in_a(a20_5to20_6), .in_b(b19_6to20_6), .out_a(a20_6to20_7), .out_b(b20_6to21_6), .out_c(matrixC20_6)); +processing_element pe20_7(.reset(effective_rst), .clk(clk), .in_a(a20_6to20_7), .in_b(b19_7to20_7), .out_a(a20_7to20_8), .out_b(b20_7to21_7), .out_c(matrixC20_7)); +processing_element pe20_8(.reset(effective_rst), .clk(clk), .in_a(a20_7to20_8), .in_b(b19_8to20_8), .out_a(a20_8to20_9), .out_b(b20_8to21_8), .out_c(matrixC20_8)); +processing_element pe20_9(.reset(effective_rst), .clk(clk), .in_a(a20_8to20_9), .in_b(b19_9to20_9), .out_a(a20_9to20_10), .out_b(b20_9to21_9), .out_c(matrixC20_9)); +processing_element pe20_10(.reset(effective_rst), .clk(clk), .in_a(a20_9to20_10), .in_b(b19_10to20_10), .out_a(a20_10to20_11), .out_b(b20_10to21_10), .out_c(matrixC20_10)); +processing_element pe20_11(.reset(effective_rst), .clk(clk), .in_a(a20_10to20_11), .in_b(b19_11to20_11), .out_a(a20_11to20_12), .out_b(b20_11to21_11), .out_c(matrixC20_11)); +processing_element pe20_12(.reset(effective_rst), .clk(clk), .in_a(a20_11to20_12), .in_b(b19_12to20_12), .out_a(a20_12to20_13), .out_b(b20_12to21_12), .out_c(matrixC20_12)); +processing_element pe20_13(.reset(effective_rst), .clk(clk), .in_a(a20_12to20_13), .in_b(b19_13to20_13), .out_a(a20_13to20_14), .out_b(b20_13to21_13), .out_c(matrixC20_13)); +processing_element pe20_14(.reset(effective_rst), .clk(clk), .in_a(a20_13to20_14), .in_b(b19_14to20_14), .out_a(a20_14to20_15), .out_b(b20_14to21_14), .out_c(matrixC20_14)); +processing_element pe20_15(.reset(effective_rst), .clk(clk), .in_a(a20_14to20_15), .in_b(b19_15to20_15), .out_a(a20_15to20_16), .out_b(b20_15to21_15), .out_c(matrixC20_15)); +processing_element pe20_16(.reset(effective_rst), .clk(clk), .in_a(a20_15to20_16), .in_b(b19_16to20_16), .out_a(a20_16to20_17), .out_b(b20_16to21_16), .out_c(matrixC20_16)); +processing_element pe20_17(.reset(effective_rst), .clk(clk), .in_a(a20_16to20_17), .in_b(b19_17to20_17), .out_a(a20_17to20_18), .out_b(b20_17to21_17), .out_c(matrixC20_17)); +processing_element pe20_18(.reset(effective_rst), .clk(clk), .in_a(a20_17to20_18), .in_b(b19_18to20_18), .out_a(a20_18to20_19), .out_b(b20_18to21_18), .out_c(matrixC20_18)); +processing_element pe20_19(.reset(effective_rst), .clk(clk), .in_a(a20_18to20_19), .in_b(b19_19to20_19), .out_a(a20_19to20_20), .out_b(b20_19to21_19), .out_c(matrixC20_19)); +processing_element pe20_20(.reset(effective_rst), .clk(clk), .in_a(a20_19to20_20), .in_b(b19_20to20_20), .out_a(a20_20to20_21), .out_b(b20_20to21_20), .out_c(matrixC20_20)); +processing_element pe20_21(.reset(effective_rst), .clk(clk), .in_a(a20_20to20_21), .in_b(b19_21to20_21), .out_a(a20_21to20_22), .out_b(b20_21to21_21), .out_c(matrixC20_21)); +processing_element pe20_22(.reset(effective_rst), .clk(clk), .in_a(a20_21to20_22), .in_b(b19_22to20_22), .out_a(a20_22to20_23), .out_b(b20_22to21_22), .out_c(matrixC20_22)); +processing_element pe20_23(.reset(effective_rst), .clk(clk), .in_a(a20_22to20_23), .in_b(b19_23to20_23), .out_a(a20_23to20_24), .out_b(b20_23to21_23), .out_c(matrixC20_23)); +processing_element pe20_24(.reset(effective_rst), .clk(clk), .in_a(a20_23to20_24), .in_b(b19_24to20_24), .out_a(a20_24to20_25), .out_b(b20_24to21_24), .out_c(matrixC20_24)); +processing_element pe20_25(.reset(effective_rst), .clk(clk), .in_a(a20_24to20_25), .in_b(b19_25to20_25), .out_a(a20_25to20_26), .out_b(b20_25to21_25), .out_c(matrixC20_25)); +processing_element pe20_26(.reset(effective_rst), .clk(clk), .in_a(a20_25to20_26), .in_b(b19_26to20_26), .out_a(a20_26to20_27), .out_b(b20_26to21_26), .out_c(matrixC20_26)); +processing_element pe20_27(.reset(effective_rst), .clk(clk), .in_a(a20_26to20_27), .in_b(b19_27to20_27), .out_a(a20_27to20_28), .out_b(b20_27to21_27), .out_c(matrixC20_27)); +processing_element pe20_28(.reset(effective_rst), .clk(clk), .in_a(a20_27to20_28), .in_b(b19_28to20_28), .out_a(a20_28to20_29), .out_b(b20_28to21_28), .out_c(matrixC20_28)); +processing_element pe20_29(.reset(effective_rst), .clk(clk), .in_a(a20_28to20_29), .in_b(b19_29to20_29), .out_a(a20_29to20_30), .out_b(b20_29to21_29), .out_c(matrixC20_29)); +processing_element pe20_30(.reset(effective_rst), .clk(clk), .in_a(a20_29to20_30), .in_b(b19_30to20_30), .out_a(a20_30to20_31), .out_b(b20_30to21_30), .out_c(matrixC20_30)); +processing_element pe20_31(.reset(effective_rst), .clk(clk), .in_a(a20_30to20_31), .in_b(b19_31to20_31), .out_a(a20_31to20_32), .out_b(b20_31to21_31), .out_c(matrixC20_31)); +processing_element pe21_1(.reset(effective_rst), .clk(clk), .in_a(a21_0to21_1), .in_b(b20_1to21_1), .out_a(a21_1to21_2), .out_b(b21_1to22_1), .out_c(matrixC21_1)); +processing_element pe21_2(.reset(effective_rst), .clk(clk), .in_a(a21_1to21_2), .in_b(b20_2to21_2), .out_a(a21_2to21_3), .out_b(b21_2to22_2), .out_c(matrixC21_2)); +processing_element pe21_3(.reset(effective_rst), .clk(clk), .in_a(a21_2to21_3), .in_b(b20_3to21_3), .out_a(a21_3to21_4), .out_b(b21_3to22_3), .out_c(matrixC21_3)); +processing_element pe21_4(.reset(effective_rst), .clk(clk), .in_a(a21_3to21_4), .in_b(b20_4to21_4), .out_a(a21_4to21_5), .out_b(b21_4to22_4), .out_c(matrixC21_4)); +processing_element pe21_5(.reset(effective_rst), .clk(clk), .in_a(a21_4to21_5), .in_b(b20_5to21_5), .out_a(a21_5to21_6), .out_b(b21_5to22_5), .out_c(matrixC21_5)); +processing_element pe21_6(.reset(effective_rst), .clk(clk), .in_a(a21_5to21_6), .in_b(b20_6to21_6), .out_a(a21_6to21_7), .out_b(b21_6to22_6), .out_c(matrixC21_6)); +processing_element pe21_7(.reset(effective_rst), .clk(clk), .in_a(a21_6to21_7), .in_b(b20_7to21_7), .out_a(a21_7to21_8), .out_b(b21_7to22_7), .out_c(matrixC21_7)); +processing_element pe21_8(.reset(effective_rst), .clk(clk), .in_a(a21_7to21_8), .in_b(b20_8to21_8), .out_a(a21_8to21_9), .out_b(b21_8to22_8), .out_c(matrixC21_8)); +processing_element pe21_9(.reset(effective_rst), .clk(clk), .in_a(a21_8to21_9), .in_b(b20_9to21_9), .out_a(a21_9to21_10), .out_b(b21_9to22_9), .out_c(matrixC21_9)); +processing_element pe21_10(.reset(effective_rst), .clk(clk), .in_a(a21_9to21_10), .in_b(b20_10to21_10), .out_a(a21_10to21_11), .out_b(b21_10to22_10), .out_c(matrixC21_10)); +processing_element pe21_11(.reset(effective_rst), .clk(clk), .in_a(a21_10to21_11), .in_b(b20_11to21_11), .out_a(a21_11to21_12), .out_b(b21_11to22_11), .out_c(matrixC21_11)); +processing_element pe21_12(.reset(effective_rst), .clk(clk), .in_a(a21_11to21_12), .in_b(b20_12to21_12), .out_a(a21_12to21_13), .out_b(b21_12to22_12), .out_c(matrixC21_12)); +processing_element pe21_13(.reset(effective_rst), .clk(clk), .in_a(a21_12to21_13), .in_b(b20_13to21_13), .out_a(a21_13to21_14), .out_b(b21_13to22_13), .out_c(matrixC21_13)); +processing_element pe21_14(.reset(effective_rst), .clk(clk), .in_a(a21_13to21_14), .in_b(b20_14to21_14), .out_a(a21_14to21_15), .out_b(b21_14to22_14), .out_c(matrixC21_14)); +processing_element pe21_15(.reset(effective_rst), .clk(clk), .in_a(a21_14to21_15), .in_b(b20_15to21_15), .out_a(a21_15to21_16), .out_b(b21_15to22_15), .out_c(matrixC21_15)); +processing_element pe21_16(.reset(effective_rst), .clk(clk), .in_a(a21_15to21_16), .in_b(b20_16to21_16), .out_a(a21_16to21_17), .out_b(b21_16to22_16), .out_c(matrixC21_16)); +processing_element pe21_17(.reset(effective_rst), .clk(clk), .in_a(a21_16to21_17), .in_b(b20_17to21_17), .out_a(a21_17to21_18), .out_b(b21_17to22_17), .out_c(matrixC21_17)); +processing_element pe21_18(.reset(effective_rst), .clk(clk), .in_a(a21_17to21_18), .in_b(b20_18to21_18), .out_a(a21_18to21_19), .out_b(b21_18to22_18), .out_c(matrixC21_18)); +processing_element pe21_19(.reset(effective_rst), .clk(clk), .in_a(a21_18to21_19), .in_b(b20_19to21_19), .out_a(a21_19to21_20), .out_b(b21_19to22_19), .out_c(matrixC21_19)); +processing_element pe21_20(.reset(effective_rst), .clk(clk), .in_a(a21_19to21_20), .in_b(b20_20to21_20), .out_a(a21_20to21_21), .out_b(b21_20to22_20), .out_c(matrixC21_20)); +processing_element pe21_21(.reset(effective_rst), .clk(clk), .in_a(a21_20to21_21), .in_b(b20_21to21_21), .out_a(a21_21to21_22), .out_b(b21_21to22_21), .out_c(matrixC21_21)); +processing_element pe21_22(.reset(effective_rst), .clk(clk), .in_a(a21_21to21_22), .in_b(b20_22to21_22), .out_a(a21_22to21_23), .out_b(b21_22to22_22), .out_c(matrixC21_22)); +processing_element pe21_23(.reset(effective_rst), .clk(clk), .in_a(a21_22to21_23), .in_b(b20_23to21_23), .out_a(a21_23to21_24), .out_b(b21_23to22_23), .out_c(matrixC21_23)); +processing_element pe21_24(.reset(effective_rst), .clk(clk), .in_a(a21_23to21_24), .in_b(b20_24to21_24), .out_a(a21_24to21_25), .out_b(b21_24to22_24), .out_c(matrixC21_24)); +processing_element pe21_25(.reset(effective_rst), .clk(clk), .in_a(a21_24to21_25), .in_b(b20_25to21_25), .out_a(a21_25to21_26), .out_b(b21_25to22_25), .out_c(matrixC21_25)); +processing_element pe21_26(.reset(effective_rst), .clk(clk), .in_a(a21_25to21_26), .in_b(b20_26to21_26), .out_a(a21_26to21_27), .out_b(b21_26to22_26), .out_c(matrixC21_26)); +processing_element pe21_27(.reset(effective_rst), .clk(clk), .in_a(a21_26to21_27), .in_b(b20_27to21_27), .out_a(a21_27to21_28), .out_b(b21_27to22_27), .out_c(matrixC21_27)); +processing_element pe21_28(.reset(effective_rst), .clk(clk), .in_a(a21_27to21_28), .in_b(b20_28to21_28), .out_a(a21_28to21_29), .out_b(b21_28to22_28), .out_c(matrixC21_28)); +processing_element pe21_29(.reset(effective_rst), .clk(clk), .in_a(a21_28to21_29), .in_b(b20_29to21_29), .out_a(a21_29to21_30), .out_b(b21_29to22_29), .out_c(matrixC21_29)); +processing_element pe21_30(.reset(effective_rst), .clk(clk), .in_a(a21_29to21_30), .in_b(b20_30to21_30), .out_a(a21_30to21_31), .out_b(b21_30to22_30), .out_c(matrixC21_30)); +processing_element pe21_31(.reset(effective_rst), .clk(clk), .in_a(a21_30to21_31), .in_b(b20_31to21_31), .out_a(a21_31to21_32), .out_b(b21_31to22_31), .out_c(matrixC21_31)); +processing_element pe22_1(.reset(effective_rst), .clk(clk), .in_a(a22_0to22_1), .in_b(b21_1to22_1), .out_a(a22_1to22_2), .out_b(b22_1to23_1), .out_c(matrixC22_1)); +processing_element pe22_2(.reset(effective_rst), .clk(clk), .in_a(a22_1to22_2), .in_b(b21_2to22_2), .out_a(a22_2to22_3), .out_b(b22_2to23_2), .out_c(matrixC22_2)); +processing_element pe22_3(.reset(effective_rst), .clk(clk), .in_a(a22_2to22_3), .in_b(b21_3to22_3), .out_a(a22_3to22_4), .out_b(b22_3to23_3), .out_c(matrixC22_3)); +processing_element pe22_4(.reset(effective_rst), .clk(clk), .in_a(a22_3to22_4), .in_b(b21_4to22_4), .out_a(a22_4to22_5), .out_b(b22_4to23_4), .out_c(matrixC22_4)); +processing_element pe22_5(.reset(effective_rst), .clk(clk), .in_a(a22_4to22_5), .in_b(b21_5to22_5), .out_a(a22_5to22_6), .out_b(b22_5to23_5), .out_c(matrixC22_5)); +processing_element pe22_6(.reset(effective_rst), .clk(clk), .in_a(a22_5to22_6), .in_b(b21_6to22_6), .out_a(a22_6to22_7), .out_b(b22_6to23_6), .out_c(matrixC22_6)); +processing_element pe22_7(.reset(effective_rst), .clk(clk), .in_a(a22_6to22_7), .in_b(b21_7to22_7), .out_a(a22_7to22_8), .out_b(b22_7to23_7), .out_c(matrixC22_7)); +processing_element pe22_8(.reset(effective_rst), .clk(clk), .in_a(a22_7to22_8), .in_b(b21_8to22_8), .out_a(a22_8to22_9), .out_b(b22_8to23_8), .out_c(matrixC22_8)); +processing_element pe22_9(.reset(effective_rst), .clk(clk), .in_a(a22_8to22_9), .in_b(b21_9to22_9), .out_a(a22_9to22_10), .out_b(b22_9to23_9), .out_c(matrixC22_9)); +processing_element pe22_10(.reset(effective_rst), .clk(clk), .in_a(a22_9to22_10), .in_b(b21_10to22_10), .out_a(a22_10to22_11), .out_b(b22_10to23_10), .out_c(matrixC22_10)); +processing_element pe22_11(.reset(effective_rst), .clk(clk), .in_a(a22_10to22_11), .in_b(b21_11to22_11), .out_a(a22_11to22_12), .out_b(b22_11to23_11), .out_c(matrixC22_11)); +processing_element pe22_12(.reset(effective_rst), .clk(clk), .in_a(a22_11to22_12), .in_b(b21_12to22_12), .out_a(a22_12to22_13), .out_b(b22_12to23_12), .out_c(matrixC22_12)); +processing_element pe22_13(.reset(effective_rst), .clk(clk), .in_a(a22_12to22_13), .in_b(b21_13to22_13), .out_a(a22_13to22_14), .out_b(b22_13to23_13), .out_c(matrixC22_13)); +processing_element pe22_14(.reset(effective_rst), .clk(clk), .in_a(a22_13to22_14), .in_b(b21_14to22_14), .out_a(a22_14to22_15), .out_b(b22_14to23_14), .out_c(matrixC22_14)); +processing_element pe22_15(.reset(effective_rst), .clk(clk), .in_a(a22_14to22_15), .in_b(b21_15to22_15), .out_a(a22_15to22_16), .out_b(b22_15to23_15), .out_c(matrixC22_15)); +processing_element pe22_16(.reset(effective_rst), .clk(clk), .in_a(a22_15to22_16), .in_b(b21_16to22_16), .out_a(a22_16to22_17), .out_b(b22_16to23_16), .out_c(matrixC22_16)); +processing_element pe22_17(.reset(effective_rst), .clk(clk), .in_a(a22_16to22_17), .in_b(b21_17to22_17), .out_a(a22_17to22_18), .out_b(b22_17to23_17), .out_c(matrixC22_17)); +processing_element pe22_18(.reset(effective_rst), .clk(clk), .in_a(a22_17to22_18), .in_b(b21_18to22_18), .out_a(a22_18to22_19), .out_b(b22_18to23_18), .out_c(matrixC22_18)); +processing_element pe22_19(.reset(effective_rst), .clk(clk), .in_a(a22_18to22_19), .in_b(b21_19to22_19), .out_a(a22_19to22_20), .out_b(b22_19to23_19), .out_c(matrixC22_19)); +processing_element pe22_20(.reset(effective_rst), .clk(clk), .in_a(a22_19to22_20), .in_b(b21_20to22_20), .out_a(a22_20to22_21), .out_b(b22_20to23_20), .out_c(matrixC22_20)); +processing_element pe22_21(.reset(effective_rst), .clk(clk), .in_a(a22_20to22_21), .in_b(b21_21to22_21), .out_a(a22_21to22_22), .out_b(b22_21to23_21), .out_c(matrixC22_21)); +processing_element pe22_22(.reset(effective_rst), .clk(clk), .in_a(a22_21to22_22), .in_b(b21_22to22_22), .out_a(a22_22to22_23), .out_b(b22_22to23_22), .out_c(matrixC22_22)); +processing_element pe22_23(.reset(effective_rst), .clk(clk), .in_a(a22_22to22_23), .in_b(b21_23to22_23), .out_a(a22_23to22_24), .out_b(b22_23to23_23), .out_c(matrixC22_23)); +processing_element pe22_24(.reset(effective_rst), .clk(clk), .in_a(a22_23to22_24), .in_b(b21_24to22_24), .out_a(a22_24to22_25), .out_b(b22_24to23_24), .out_c(matrixC22_24)); +processing_element pe22_25(.reset(effective_rst), .clk(clk), .in_a(a22_24to22_25), .in_b(b21_25to22_25), .out_a(a22_25to22_26), .out_b(b22_25to23_25), .out_c(matrixC22_25)); +processing_element pe22_26(.reset(effective_rst), .clk(clk), .in_a(a22_25to22_26), .in_b(b21_26to22_26), .out_a(a22_26to22_27), .out_b(b22_26to23_26), .out_c(matrixC22_26)); +processing_element pe22_27(.reset(effective_rst), .clk(clk), .in_a(a22_26to22_27), .in_b(b21_27to22_27), .out_a(a22_27to22_28), .out_b(b22_27to23_27), .out_c(matrixC22_27)); +processing_element pe22_28(.reset(effective_rst), .clk(clk), .in_a(a22_27to22_28), .in_b(b21_28to22_28), .out_a(a22_28to22_29), .out_b(b22_28to23_28), .out_c(matrixC22_28)); +processing_element pe22_29(.reset(effective_rst), .clk(clk), .in_a(a22_28to22_29), .in_b(b21_29to22_29), .out_a(a22_29to22_30), .out_b(b22_29to23_29), .out_c(matrixC22_29)); +processing_element pe22_30(.reset(effective_rst), .clk(clk), .in_a(a22_29to22_30), .in_b(b21_30to22_30), .out_a(a22_30to22_31), .out_b(b22_30to23_30), .out_c(matrixC22_30)); +processing_element pe22_31(.reset(effective_rst), .clk(clk), .in_a(a22_30to22_31), .in_b(b21_31to22_31), .out_a(a22_31to22_32), .out_b(b22_31to23_31), .out_c(matrixC22_31)); +processing_element pe23_1(.reset(effective_rst), .clk(clk), .in_a(a23_0to23_1), .in_b(b22_1to23_1), .out_a(a23_1to23_2), .out_b(b23_1to24_1), .out_c(matrixC23_1)); +processing_element pe23_2(.reset(effective_rst), .clk(clk), .in_a(a23_1to23_2), .in_b(b22_2to23_2), .out_a(a23_2to23_3), .out_b(b23_2to24_2), .out_c(matrixC23_2)); +processing_element pe23_3(.reset(effective_rst), .clk(clk), .in_a(a23_2to23_3), .in_b(b22_3to23_3), .out_a(a23_3to23_4), .out_b(b23_3to24_3), .out_c(matrixC23_3)); +processing_element pe23_4(.reset(effective_rst), .clk(clk), .in_a(a23_3to23_4), .in_b(b22_4to23_4), .out_a(a23_4to23_5), .out_b(b23_4to24_4), .out_c(matrixC23_4)); +processing_element pe23_5(.reset(effective_rst), .clk(clk), .in_a(a23_4to23_5), .in_b(b22_5to23_5), .out_a(a23_5to23_6), .out_b(b23_5to24_5), .out_c(matrixC23_5)); +processing_element pe23_6(.reset(effective_rst), .clk(clk), .in_a(a23_5to23_6), .in_b(b22_6to23_6), .out_a(a23_6to23_7), .out_b(b23_6to24_6), .out_c(matrixC23_6)); +processing_element pe23_7(.reset(effective_rst), .clk(clk), .in_a(a23_6to23_7), .in_b(b22_7to23_7), .out_a(a23_7to23_8), .out_b(b23_7to24_7), .out_c(matrixC23_7)); +processing_element pe23_8(.reset(effective_rst), .clk(clk), .in_a(a23_7to23_8), .in_b(b22_8to23_8), .out_a(a23_8to23_9), .out_b(b23_8to24_8), .out_c(matrixC23_8)); +processing_element pe23_9(.reset(effective_rst), .clk(clk), .in_a(a23_8to23_9), .in_b(b22_9to23_9), .out_a(a23_9to23_10), .out_b(b23_9to24_9), .out_c(matrixC23_9)); +processing_element pe23_10(.reset(effective_rst), .clk(clk), .in_a(a23_9to23_10), .in_b(b22_10to23_10), .out_a(a23_10to23_11), .out_b(b23_10to24_10), .out_c(matrixC23_10)); +processing_element pe23_11(.reset(effective_rst), .clk(clk), .in_a(a23_10to23_11), .in_b(b22_11to23_11), .out_a(a23_11to23_12), .out_b(b23_11to24_11), .out_c(matrixC23_11)); +processing_element pe23_12(.reset(effective_rst), .clk(clk), .in_a(a23_11to23_12), .in_b(b22_12to23_12), .out_a(a23_12to23_13), .out_b(b23_12to24_12), .out_c(matrixC23_12)); +processing_element pe23_13(.reset(effective_rst), .clk(clk), .in_a(a23_12to23_13), .in_b(b22_13to23_13), .out_a(a23_13to23_14), .out_b(b23_13to24_13), .out_c(matrixC23_13)); +processing_element pe23_14(.reset(effective_rst), .clk(clk), .in_a(a23_13to23_14), .in_b(b22_14to23_14), .out_a(a23_14to23_15), .out_b(b23_14to24_14), .out_c(matrixC23_14)); +processing_element pe23_15(.reset(effective_rst), .clk(clk), .in_a(a23_14to23_15), .in_b(b22_15to23_15), .out_a(a23_15to23_16), .out_b(b23_15to24_15), .out_c(matrixC23_15)); +processing_element pe23_16(.reset(effective_rst), .clk(clk), .in_a(a23_15to23_16), .in_b(b22_16to23_16), .out_a(a23_16to23_17), .out_b(b23_16to24_16), .out_c(matrixC23_16)); +processing_element pe23_17(.reset(effective_rst), .clk(clk), .in_a(a23_16to23_17), .in_b(b22_17to23_17), .out_a(a23_17to23_18), .out_b(b23_17to24_17), .out_c(matrixC23_17)); +processing_element pe23_18(.reset(effective_rst), .clk(clk), .in_a(a23_17to23_18), .in_b(b22_18to23_18), .out_a(a23_18to23_19), .out_b(b23_18to24_18), .out_c(matrixC23_18)); +processing_element pe23_19(.reset(effective_rst), .clk(clk), .in_a(a23_18to23_19), .in_b(b22_19to23_19), .out_a(a23_19to23_20), .out_b(b23_19to24_19), .out_c(matrixC23_19)); +processing_element pe23_20(.reset(effective_rst), .clk(clk), .in_a(a23_19to23_20), .in_b(b22_20to23_20), .out_a(a23_20to23_21), .out_b(b23_20to24_20), .out_c(matrixC23_20)); +processing_element pe23_21(.reset(effective_rst), .clk(clk), .in_a(a23_20to23_21), .in_b(b22_21to23_21), .out_a(a23_21to23_22), .out_b(b23_21to24_21), .out_c(matrixC23_21)); +processing_element pe23_22(.reset(effective_rst), .clk(clk), .in_a(a23_21to23_22), .in_b(b22_22to23_22), .out_a(a23_22to23_23), .out_b(b23_22to24_22), .out_c(matrixC23_22)); +processing_element pe23_23(.reset(effective_rst), .clk(clk), .in_a(a23_22to23_23), .in_b(b22_23to23_23), .out_a(a23_23to23_24), .out_b(b23_23to24_23), .out_c(matrixC23_23)); +processing_element pe23_24(.reset(effective_rst), .clk(clk), .in_a(a23_23to23_24), .in_b(b22_24to23_24), .out_a(a23_24to23_25), .out_b(b23_24to24_24), .out_c(matrixC23_24)); +processing_element pe23_25(.reset(effective_rst), .clk(clk), .in_a(a23_24to23_25), .in_b(b22_25to23_25), .out_a(a23_25to23_26), .out_b(b23_25to24_25), .out_c(matrixC23_25)); +processing_element pe23_26(.reset(effective_rst), .clk(clk), .in_a(a23_25to23_26), .in_b(b22_26to23_26), .out_a(a23_26to23_27), .out_b(b23_26to24_26), .out_c(matrixC23_26)); +processing_element pe23_27(.reset(effective_rst), .clk(clk), .in_a(a23_26to23_27), .in_b(b22_27to23_27), .out_a(a23_27to23_28), .out_b(b23_27to24_27), .out_c(matrixC23_27)); +processing_element pe23_28(.reset(effective_rst), .clk(clk), .in_a(a23_27to23_28), .in_b(b22_28to23_28), .out_a(a23_28to23_29), .out_b(b23_28to24_28), .out_c(matrixC23_28)); +processing_element pe23_29(.reset(effective_rst), .clk(clk), .in_a(a23_28to23_29), .in_b(b22_29to23_29), .out_a(a23_29to23_30), .out_b(b23_29to24_29), .out_c(matrixC23_29)); +processing_element pe23_30(.reset(effective_rst), .clk(clk), .in_a(a23_29to23_30), .in_b(b22_30to23_30), .out_a(a23_30to23_31), .out_b(b23_30to24_30), .out_c(matrixC23_30)); +processing_element pe23_31(.reset(effective_rst), .clk(clk), .in_a(a23_30to23_31), .in_b(b22_31to23_31), .out_a(a23_31to23_32), .out_b(b23_31to24_31), .out_c(matrixC23_31)); +processing_element pe24_1(.reset(effective_rst), .clk(clk), .in_a(a24_0to24_1), .in_b(b23_1to24_1), .out_a(a24_1to24_2), .out_b(b24_1to25_1), .out_c(matrixC24_1)); +processing_element pe24_2(.reset(effective_rst), .clk(clk), .in_a(a24_1to24_2), .in_b(b23_2to24_2), .out_a(a24_2to24_3), .out_b(b24_2to25_2), .out_c(matrixC24_2)); +processing_element pe24_3(.reset(effective_rst), .clk(clk), .in_a(a24_2to24_3), .in_b(b23_3to24_3), .out_a(a24_3to24_4), .out_b(b24_3to25_3), .out_c(matrixC24_3)); +processing_element pe24_4(.reset(effective_rst), .clk(clk), .in_a(a24_3to24_4), .in_b(b23_4to24_4), .out_a(a24_4to24_5), .out_b(b24_4to25_4), .out_c(matrixC24_4)); +processing_element pe24_5(.reset(effective_rst), .clk(clk), .in_a(a24_4to24_5), .in_b(b23_5to24_5), .out_a(a24_5to24_6), .out_b(b24_5to25_5), .out_c(matrixC24_5)); +processing_element pe24_6(.reset(effective_rst), .clk(clk), .in_a(a24_5to24_6), .in_b(b23_6to24_6), .out_a(a24_6to24_7), .out_b(b24_6to25_6), .out_c(matrixC24_6)); +processing_element pe24_7(.reset(effective_rst), .clk(clk), .in_a(a24_6to24_7), .in_b(b23_7to24_7), .out_a(a24_7to24_8), .out_b(b24_7to25_7), .out_c(matrixC24_7)); +processing_element pe24_8(.reset(effective_rst), .clk(clk), .in_a(a24_7to24_8), .in_b(b23_8to24_8), .out_a(a24_8to24_9), .out_b(b24_8to25_8), .out_c(matrixC24_8)); +processing_element pe24_9(.reset(effective_rst), .clk(clk), .in_a(a24_8to24_9), .in_b(b23_9to24_9), .out_a(a24_9to24_10), .out_b(b24_9to25_9), .out_c(matrixC24_9)); +processing_element pe24_10(.reset(effective_rst), .clk(clk), .in_a(a24_9to24_10), .in_b(b23_10to24_10), .out_a(a24_10to24_11), .out_b(b24_10to25_10), .out_c(matrixC24_10)); +processing_element pe24_11(.reset(effective_rst), .clk(clk), .in_a(a24_10to24_11), .in_b(b23_11to24_11), .out_a(a24_11to24_12), .out_b(b24_11to25_11), .out_c(matrixC24_11)); +processing_element pe24_12(.reset(effective_rst), .clk(clk), .in_a(a24_11to24_12), .in_b(b23_12to24_12), .out_a(a24_12to24_13), .out_b(b24_12to25_12), .out_c(matrixC24_12)); +processing_element pe24_13(.reset(effective_rst), .clk(clk), .in_a(a24_12to24_13), .in_b(b23_13to24_13), .out_a(a24_13to24_14), .out_b(b24_13to25_13), .out_c(matrixC24_13)); +processing_element pe24_14(.reset(effective_rst), .clk(clk), .in_a(a24_13to24_14), .in_b(b23_14to24_14), .out_a(a24_14to24_15), .out_b(b24_14to25_14), .out_c(matrixC24_14)); +processing_element pe24_15(.reset(effective_rst), .clk(clk), .in_a(a24_14to24_15), .in_b(b23_15to24_15), .out_a(a24_15to24_16), .out_b(b24_15to25_15), .out_c(matrixC24_15)); +processing_element pe24_16(.reset(effective_rst), .clk(clk), .in_a(a24_15to24_16), .in_b(b23_16to24_16), .out_a(a24_16to24_17), .out_b(b24_16to25_16), .out_c(matrixC24_16)); +processing_element pe24_17(.reset(effective_rst), .clk(clk), .in_a(a24_16to24_17), .in_b(b23_17to24_17), .out_a(a24_17to24_18), .out_b(b24_17to25_17), .out_c(matrixC24_17)); +processing_element pe24_18(.reset(effective_rst), .clk(clk), .in_a(a24_17to24_18), .in_b(b23_18to24_18), .out_a(a24_18to24_19), .out_b(b24_18to25_18), .out_c(matrixC24_18)); +processing_element pe24_19(.reset(effective_rst), .clk(clk), .in_a(a24_18to24_19), .in_b(b23_19to24_19), .out_a(a24_19to24_20), .out_b(b24_19to25_19), .out_c(matrixC24_19)); +processing_element pe24_20(.reset(effective_rst), .clk(clk), .in_a(a24_19to24_20), .in_b(b23_20to24_20), .out_a(a24_20to24_21), .out_b(b24_20to25_20), .out_c(matrixC24_20)); +processing_element pe24_21(.reset(effective_rst), .clk(clk), .in_a(a24_20to24_21), .in_b(b23_21to24_21), .out_a(a24_21to24_22), .out_b(b24_21to25_21), .out_c(matrixC24_21)); +processing_element pe24_22(.reset(effective_rst), .clk(clk), .in_a(a24_21to24_22), .in_b(b23_22to24_22), .out_a(a24_22to24_23), .out_b(b24_22to25_22), .out_c(matrixC24_22)); +processing_element pe24_23(.reset(effective_rst), .clk(clk), .in_a(a24_22to24_23), .in_b(b23_23to24_23), .out_a(a24_23to24_24), .out_b(b24_23to25_23), .out_c(matrixC24_23)); +processing_element pe24_24(.reset(effective_rst), .clk(clk), .in_a(a24_23to24_24), .in_b(b23_24to24_24), .out_a(a24_24to24_25), .out_b(b24_24to25_24), .out_c(matrixC24_24)); +processing_element pe24_25(.reset(effective_rst), .clk(clk), .in_a(a24_24to24_25), .in_b(b23_25to24_25), .out_a(a24_25to24_26), .out_b(b24_25to25_25), .out_c(matrixC24_25)); +processing_element pe24_26(.reset(effective_rst), .clk(clk), .in_a(a24_25to24_26), .in_b(b23_26to24_26), .out_a(a24_26to24_27), .out_b(b24_26to25_26), .out_c(matrixC24_26)); +processing_element pe24_27(.reset(effective_rst), .clk(clk), .in_a(a24_26to24_27), .in_b(b23_27to24_27), .out_a(a24_27to24_28), .out_b(b24_27to25_27), .out_c(matrixC24_27)); +processing_element pe24_28(.reset(effective_rst), .clk(clk), .in_a(a24_27to24_28), .in_b(b23_28to24_28), .out_a(a24_28to24_29), .out_b(b24_28to25_28), .out_c(matrixC24_28)); +processing_element pe24_29(.reset(effective_rst), .clk(clk), .in_a(a24_28to24_29), .in_b(b23_29to24_29), .out_a(a24_29to24_30), .out_b(b24_29to25_29), .out_c(matrixC24_29)); +processing_element pe24_30(.reset(effective_rst), .clk(clk), .in_a(a24_29to24_30), .in_b(b23_30to24_30), .out_a(a24_30to24_31), .out_b(b24_30to25_30), .out_c(matrixC24_30)); +processing_element pe24_31(.reset(effective_rst), .clk(clk), .in_a(a24_30to24_31), .in_b(b23_31to24_31), .out_a(a24_31to24_32), .out_b(b24_31to25_31), .out_c(matrixC24_31)); +processing_element pe25_1(.reset(effective_rst), .clk(clk), .in_a(a25_0to25_1), .in_b(b24_1to25_1), .out_a(a25_1to25_2), .out_b(b25_1to26_1), .out_c(matrixC25_1)); +processing_element pe25_2(.reset(effective_rst), .clk(clk), .in_a(a25_1to25_2), .in_b(b24_2to25_2), .out_a(a25_2to25_3), .out_b(b25_2to26_2), .out_c(matrixC25_2)); +processing_element pe25_3(.reset(effective_rst), .clk(clk), .in_a(a25_2to25_3), .in_b(b24_3to25_3), .out_a(a25_3to25_4), .out_b(b25_3to26_3), .out_c(matrixC25_3)); +processing_element pe25_4(.reset(effective_rst), .clk(clk), .in_a(a25_3to25_4), .in_b(b24_4to25_4), .out_a(a25_4to25_5), .out_b(b25_4to26_4), .out_c(matrixC25_4)); +processing_element pe25_5(.reset(effective_rst), .clk(clk), .in_a(a25_4to25_5), .in_b(b24_5to25_5), .out_a(a25_5to25_6), .out_b(b25_5to26_5), .out_c(matrixC25_5)); +processing_element pe25_6(.reset(effective_rst), .clk(clk), .in_a(a25_5to25_6), .in_b(b24_6to25_6), .out_a(a25_6to25_7), .out_b(b25_6to26_6), .out_c(matrixC25_6)); +processing_element pe25_7(.reset(effective_rst), .clk(clk), .in_a(a25_6to25_7), .in_b(b24_7to25_7), .out_a(a25_7to25_8), .out_b(b25_7to26_7), .out_c(matrixC25_7)); +processing_element pe25_8(.reset(effective_rst), .clk(clk), .in_a(a25_7to25_8), .in_b(b24_8to25_8), .out_a(a25_8to25_9), .out_b(b25_8to26_8), .out_c(matrixC25_8)); +processing_element pe25_9(.reset(effective_rst), .clk(clk), .in_a(a25_8to25_9), .in_b(b24_9to25_9), .out_a(a25_9to25_10), .out_b(b25_9to26_9), .out_c(matrixC25_9)); +processing_element pe25_10(.reset(effective_rst), .clk(clk), .in_a(a25_9to25_10), .in_b(b24_10to25_10), .out_a(a25_10to25_11), .out_b(b25_10to26_10), .out_c(matrixC25_10)); +processing_element pe25_11(.reset(effective_rst), .clk(clk), .in_a(a25_10to25_11), .in_b(b24_11to25_11), .out_a(a25_11to25_12), .out_b(b25_11to26_11), .out_c(matrixC25_11)); +processing_element pe25_12(.reset(effective_rst), .clk(clk), .in_a(a25_11to25_12), .in_b(b24_12to25_12), .out_a(a25_12to25_13), .out_b(b25_12to26_12), .out_c(matrixC25_12)); +processing_element pe25_13(.reset(effective_rst), .clk(clk), .in_a(a25_12to25_13), .in_b(b24_13to25_13), .out_a(a25_13to25_14), .out_b(b25_13to26_13), .out_c(matrixC25_13)); +processing_element pe25_14(.reset(effective_rst), .clk(clk), .in_a(a25_13to25_14), .in_b(b24_14to25_14), .out_a(a25_14to25_15), .out_b(b25_14to26_14), .out_c(matrixC25_14)); +processing_element pe25_15(.reset(effective_rst), .clk(clk), .in_a(a25_14to25_15), .in_b(b24_15to25_15), .out_a(a25_15to25_16), .out_b(b25_15to26_15), .out_c(matrixC25_15)); +processing_element pe25_16(.reset(effective_rst), .clk(clk), .in_a(a25_15to25_16), .in_b(b24_16to25_16), .out_a(a25_16to25_17), .out_b(b25_16to26_16), .out_c(matrixC25_16)); +processing_element pe25_17(.reset(effective_rst), .clk(clk), .in_a(a25_16to25_17), .in_b(b24_17to25_17), .out_a(a25_17to25_18), .out_b(b25_17to26_17), .out_c(matrixC25_17)); +processing_element pe25_18(.reset(effective_rst), .clk(clk), .in_a(a25_17to25_18), .in_b(b24_18to25_18), .out_a(a25_18to25_19), .out_b(b25_18to26_18), .out_c(matrixC25_18)); +processing_element pe25_19(.reset(effective_rst), .clk(clk), .in_a(a25_18to25_19), .in_b(b24_19to25_19), .out_a(a25_19to25_20), .out_b(b25_19to26_19), .out_c(matrixC25_19)); +processing_element pe25_20(.reset(effective_rst), .clk(clk), .in_a(a25_19to25_20), .in_b(b24_20to25_20), .out_a(a25_20to25_21), .out_b(b25_20to26_20), .out_c(matrixC25_20)); +processing_element pe25_21(.reset(effective_rst), .clk(clk), .in_a(a25_20to25_21), .in_b(b24_21to25_21), .out_a(a25_21to25_22), .out_b(b25_21to26_21), .out_c(matrixC25_21)); +processing_element pe25_22(.reset(effective_rst), .clk(clk), .in_a(a25_21to25_22), .in_b(b24_22to25_22), .out_a(a25_22to25_23), .out_b(b25_22to26_22), .out_c(matrixC25_22)); +processing_element pe25_23(.reset(effective_rst), .clk(clk), .in_a(a25_22to25_23), .in_b(b24_23to25_23), .out_a(a25_23to25_24), .out_b(b25_23to26_23), .out_c(matrixC25_23)); +processing_element pe25_24(.reset(effective_rst), .clk(clk), .in_a(a25_23to25_24), .in_b(b24_24to25_24), .out_a(a25_24to25_25), .out_b(b25_24to26_24), .out_c(matrixC25_24)); +processing_element pe25_25(.reset(effective_rst), .clk(clk), .in_a(a25_24to25_25), .in_b(b24_25to25_25), .out_a(a25_25to25_26), .out_b(b25_25to26_25), .out_c(matrixC25_25)); +processing_element pe25_26(.reset(effective_rst), .clk(clk), .in_a(a25_25to25_26), .in_b(b24_26to25_26), .out_a(a25_26to25_27), .out_b(b25_26to26_26), .out_c(matrixC25_26)); +processing_element pe25_27(.reset(effective_rst), .clk(clk), .in_a(a25_26to25_27), .in_b(b24_27to25_27), .out_a(a25_27to25_28), .out_b(b25_27to26_27), .out_c(matrixC25_27)); +processing_element pe25_28(.reset(effective_rst), .clk(clk), .in_a(a25_27to25_28), .in_b(b24_28to25_28), .out_a(a25_28to25_29), .out_b(b25_28to26_28), .out_c(matrixC25_28)); +processing_element pe25_29(.reset(effective_rst), .clk(clk), .in_a(a25_28to25_29), .in_b(b24_29to25_29), .out_a(a25_29to25_30), .out_b(b25_29to26_29), .out_c(matrixC25_29)); +processing_element pe25_30(.reset(effective_rst), .clk(clk), .in_a(a25_29to25_30), .in_b(b24_30to25_30), .out_a(a25_30to25_31), .out_b(b25_30to26_30), .out_c(matrixC25_30)); +processing_element pe25_31(.reset(effective_rst), .clk(clk), .in_a(a25_30to25_31), .in_b(b24_31to25_31), .out_a(a25_31to25_32), .out_b(b25_31to26_31), .out_c(matrixC25_31)); +processing_element pe26_1(.reset(effective_rst), .clk(clk), .in_a(a26_0to26_1), .in_b(b25_1to26_1), .out_a(a26_1to26_2), .out_b(b26_1to27_1), .out_c(matrixC26_1)); +processing_element pe26_2(.reset(effective_rst), .clk(clk), .in_a(a26_1to26_2), .in_b(b25_2to26_2), .out_a(a26_2to26_3), .out_b(b26_2to27_2), .out_c(matrixC26_2)); +processing_element pe26_3(.reset(effective_rst), .clk(clk), .in_a(a26_2to26_3), .in_b(b25_3to26_3), .out_a(a26_3to26_4), .out_b(b26_3to27_3), .out_c(matrixC26_3)); +processing_element pe26_4(.reset(effective_rst), .clk(clk), .in_a(a26_3to26_4), .in_b(b25_4to26_4), .out_a(a26_4to26_5), .out_b(b26_4to27_4), .out_c(matrixC26_4)); +processing_element pe26_5(.reset(effective_rst), .clk(clk), .in_a(a26_4to26_5), .in_b(b25_5to26_5), .out_a(a26_5to26_6), .out_b(b26_5to27_5), .out_c(matrixC26_5)); +processing_element pe26_6(.reset(effective_rst), .clk(clk), .in_a(a26_5to26_6), .in_b(b25_6to26_6), .out_a(a26_6to26_7), .out_b(b26_6to27_6), .out_c(matrixC26_6)); +processing_element pe26_7(.reset(effective_rst), .clk(clk), .in_a(a26_6to26_7), .in_b(b25_7to26_7), .out_a(a26_7to26_8), .out_b(b26_7to27_7), .out_c(matrixC26_7)); +processing_element pe26_8(.reset(effective_rst), .clk(clk), .in_a(a26_7to26_8), .in_b(b25_8to26_8), .out_a(a26_8to26_9), .out_b(b26_8to27_8), .out_c(matrixC26_8)); +processing_element pe26_9(.reset(effective_rst), .clk(clk), .in_a(a26_8to26_9), .in_b(b25_9to26_9), .out_a(a26_9to26_10), .out_b(b26_9to27_9), .out_c(matrixC26_9)); +processing_element pe26_10(.reset(effective_rst), .clk(clk), .in_a(a26_9to26_10), .in_b(b25_10to26_10), .out_a(a26_10to26_11), .out_b(b26_10to27_10), .out_c(matrixC26_10)); +processing_element pe26_11(.reset(effective_rst), .clk(clk), .in_a(a26_10to26_11), .in_b(b25_11to26_11), .out_a(a26_11to26_12), .out_b(b26_11to27_11), .out_c(matrixC26_11)); +processing_element pe26_12(.reset(effective_rst), .clk(clk), .in_a(a26_11to26_12), .in_b(b25_12to26_12), .out_a(a26_12to26_13), .out_b(b26_12to27_12), .out_c(matrixC26_12)); +processing_element pe26_13(.reset(effective_rst), .clk(clk), .in_a(a26_12to26_13), .in_b(b25_13to26_13), .out_a(a26_13to26_14), .out_b(b26_13to27_13), .out_c(matrixC26_13)); +processing_element pe26_14(.reset(effective_rst), .clk(clk), .in_a(a26_13to26_14), .in_b(b25_14to26_14), .out_a(a26_14to26_15), .out_b(b26_14to27_14), .out_c(matrixC26_14)); +processing_element pe26_15(.reset(effective_rst), .clk(clk), .in_a(a26_14to26_15), .in_b(b25_15to26_15), .out_a(a26_15to26_16), .out_b(b26_15to27_15), .out_c(matrixC26_15)); +processing_element pe26_16(.reset(effective_rst), .clk(clk), .in_a(a26_15to26_16), .in_b(b25_16to26_16), .out_a(a26_16to26_17), .out_b(b26_16to27_16), .out_c(matrixC26_16)); +processing_element pe26_17(.reset(effective_rst), .clk(clk), .in_a(a26_16to26_17), .in_b(b25_17to26_17), .out_a(a26_17to26_18), .out_b(b26_17to27_17), .out_c(matrixC26_17)); +processing_element pe26_18(.reset(effective_rst), .clk(clk), .in_a(a26_17to26_18), .in_b(b25_18to26_18), .out_a(a26_18to26_19), .out_b(b26_18to27_18), .out_c(matrixC26_18)); +processing_element pe26_19(.reset(effective_rst), .clk(clk), .in_a(a26_18to26_19), .in_b(b25_19to26_19), .out_a(a26_19to26_20), .out_b(b26_19to27_19), .out_c(matrixC26_19)); +processing_element pe26_20(.reset(effective_rst), .clk(clk), .in_a(a26_19to26_20), .in_b(b25_20to26_20), .out_a(a26_20to26_21), .out_b(b26_20to27_20), .out_c(matrixC26_20)); +processing_element pe26_21(.reset(effective_rst), .clk(clk), .in_a(a26_20to26_21), .in_b(b25_21to26_21), .out_a(a26_21to26_22), .out_b(b26_21to27_21), .out_c(matrixC26_21)); +processing_element pe26_22(.reset(effective_rst), .clk(clk), .in_a(a26_21to26_22), .in_b(b25_22to26_22), .out_a(a26_22to26_23), .out_b(b26_22to27_22), .out_c(matrixC26_22)); +processing_element pe26_23(.reset(effective_rst), .clk(clk), .in_a(a26_22to26_23), .in_b(b25_23to26_23), .out_a(a26_23to26_24), .out_b(b26_23to27_23), .out_c(matrixC26_23)); +processing_element pe26_24(.reset(effective_rst), .clk(clk), .in_a(a26_23to26_24), .in_b(b25_24to26_24), .out_a(a26_24to26_25), .out_b(b26_24to27_24), .out_c(matrixC26_24)); +processing_element pe26_25(.reset(effective_rst), .clk(clk), .in_a(a26_24to26_25), .in_b(b25_25to26_25), .out_a(a26_25to26_26), .out_b(b26_25to27_25), .out_c(matrixC26_25)); +processing_element pe26_26(.reset(effective_rst), .clk(clk), .in_a(a26_25to26_26), .in_b(b25_26to26_26), .out_a(a26_26to26_27), .out_b(b26_26to27_26), .out_c(matrixC26_26)); +processing_element pe26_27(.reset(effective_rst), .clk(clk), .in_a(a26_26to26_27), .in_b(b25_27to26_27), .out_a(a26_27to26_28), .out_b(b26_27to27_27), .out_c(matrixC26_27)); +processing_element pe26_28(.reset(effective_rst), .clk(clk), .in_a(a26_27to26_28), .in_b(b25_28to26_28), .out_a(a26_28to26_29), .out_b(b26_28to27_28), .out_c(matrixC26_28)); +processing_element pe26_29(.reset(effective_rst), .clk(clk), .in_a(a26_28to26_29), .in_b(b25_29to26_29), .out_a(a26_29to26_30), .out_b(b26_29to27_29), .out_c(matrixC26_29)); +processing_element pe26_30(.reset(effective_rst), .clk(clk), .in_a(a26_29to26_30), .in_b(b25_30to26_30), .out_a(a26_30to26_31), .out_b(b26_30to27_30), .out_c(matrixC26_30)); +processing_element pe26_31(.reset(effective_rst), .clk(clk), .in_a(a26_30to26_31), .in_b(b25_31to26_31), .out_a(a26_31to26_32), .out_b(b26_31to27_31), .out_c(matrixC26_31)); +processing_element pe27_1(.reset(effective_rst), .clk(clk), .in_a(a27_0to27_1), .in_b(b26_1to27_1), .out_a(a27_1to27_2), .out_b(b27_1to28_1), .out_c(matrixC27_1)); +processing_element pe27_2(.reset(effective_rst), .clk(clk), .in_a(a27_1to27_2), .in_b(b26_2to27_2), .out_a(a27_2to27_3), .out_b(b27_2to28_2), .out_c(matrixC27_2)); +processing_element pe27_3(.reset(effective_rst), .clk(clk), .in_a(a27_2to27_3), .in_b(b26_3to27_3), .out_a(a27_3to27_4), .out_b(b27_3to28_3), .out_c(matrixC27_3)); +processing_element pe27_4(.reset(effective_rst), .clk(clk), .in_a(a27_3to27_4), .in_b(b26_4to27_4), .out_a(a27_4to27_5), .out_b(b27_4to28_4), .out_c(matrixC27_4)); +processing_element pe27_5(.reset(effective_rst), .clk(clk), .in_a(a27_4to27_5), .in_b(b26_5to27_5), .out_a(a27_5to27_6), .out_b(b27_5to28_5), .out_c(matrixC27_5)); +processing_element pe27_6(.reset(effective_rst), .clk(clk), .in_a(a27_5to27_6), .in_b(b26_6to27_6), .out_a(a27_6to27_7), .out_b(b27_6to28_6), .out_c(matrixC27_6)); +processing_element pe27_7(.reset(effective_rst), .clk(clk), .in_a(a27_6to27_7), .in_b(b26_7to27_7), .out_a(a27_7to27_8), .out_b(b27_7to28_7), .out_c(matrixC27_7)); +processing_element pe27_8(.reset(effective_rst), .clk(clk), .in_a(a27_7to27_8), .in_b(b26_8to27_8), .out_a(a27_8to27_9), .out_b(b27_8to28_8), .out_c(matrixC27_8)); +processing_element pe27_9(.reset(effective_rst), .clk(clk), .in_a(a27_8to27_9), .in_b(b26_9to27_9), .out_a(a27_9to27_10), .out_b(b27_9to28_9), .out_c(matrixC27_9)); +processing_element pe27_10(.reset(effective_rst), .clk(clk), .in_a(a27_9to27_10), .in_b(b26_10to27_10), .out_a(a27_10to27_11), .out_b(b27_10to28_10), .out_c(matrixC27_10)); +processing_element pe27_11(.reset(effective_rst), .clk(clk), .in_a(a27_10to27_11), .in_b(b26_11to27_11), .out_a(a27_11to27_12), .out_b(b27_11to28_11), .out_c(matrixC27_11)); +processing_element pe27_12(.reset(effective_rst), .clk(clk), .in_a(a27_11to27_12), .in_b(b26_12to27_12), .out_a(a27_12to27_13), .out_b(b27_12to28_12), .out_c(matrixC27_12)); +processing_element pe27_13(.reset(effective_rst), .clk(clk), .in_a(a27_12to27_13), .in_b(b26_13to27_13), .out_a(a27_13to27_14), .out_b(b27_13to28_13), .out_c(matrixC27_13)); +processing_element pe27_14(.reset(effective_rst), .clk(clk), .in_a(a27_13to27_14), .in_b(b26_14to27_14), .out_a(a27_14to27_15), .out_b(b27_14to28_14), .out_c(matrixC27_14)); +processing_element pe27_15(.reset(effective_rst), .clk(clk), .in_a(a27_14to27_15), .in_b(b26_15to27_15), .out_a(a27_15to27_16), .out_b(b27_15to28_15), .out_c(matrixC27_15)); +processing_element pe27_16(.reset(effective_rst), .clk(clk), .in_a(a27_15to27_16), .in_b(b26_16to27_16), .out_a(a27_16to27_17), .out_b(b27_16to28_16), .out_c(matrixC27_16)); +processing_element pe27_17(.reset(effective_rst), .clk(clk), .in_a(a27_16to27_17), .in_b(b26_17to27_17), .out_a(a27_17to27_18), .out_b(b27_17to28_17), .out_c(matrixC27_17)); +processing_element pe27_18(.reset(effective_rst), .clk(clk), .in_a(a27_17to27_18), .in_b(b26_18to27_18), .out_a(a27_18to27_19), .out_b(b27_18to28_18), .out_c(matrixC27_18)); +processing_element pe27_19(.reset(effective_rst), .clk(clk), .in_a(a27_18to27_19), .in_b(b26_19to27_19), .out_a(a27_19to27_20), .out_b(b27_19to28_19), .out_c(matrixC27_19)); +processing_element pe27_20(.reset(effective_rst), .clk(clk), .in_a(a27_19to27_20), .in_b(b26_20to27_20), .out_a(a27_20to27_21), .out_b(b27_20to28_20), .out_c(matrixC27_20)); +processing_element pe27_21(.reset(effective_rst), .clk(clk), .in_a(a27_20to27_21), .in_b(b26_21to27_21), .out_a(a27_21to27_22), .out_b(b27_21to28_21), .out_c(matrixC27_21)); +processing_element pe27_22(.reset(effective_rst), .clk(clk), .in_a(a27_21to27_22), .in_b(b26_22to27_22), .out_a(a27_22to27_23), .out_b(b27_22to28_22), .out_c(matrixC27_22)); +processing_element pe27_23(.reset(effective_rst), .clk(clk), .in_a(a27_22to27_23), .in_b(b26_23to27_23), .out_a(a27_23to27_24), .out_b(b27_23to28_23), .out_c(matrixC27_23)); +processing_element pe27_24(.reset(effective_rst), .clk(clk), .in_a(a27_23to27_24), .in_b(b26_24to27_24), .out_a(a27_24to27_25), .out_b(b27_24to28_24), .out_c(matrixC27_24)); +processing_element pe27_25(.reset(effective_rst), .clk(clk), .in_a(a27_24to27_25), .in_b(b26_25to27_25), .out_a(a27_25to27_26), .out_b(b27_25to28_25), .out_c(matrixC27_25)); +processing_element pe27_26(.reset(effective_rst), .clk(clk), .in_a(a27_25to27_26), .in_b(b26_26to27_26), .out_a(a27_26to27_27), .out_b(b27_26to28_26), .out_c(matrixC27_26)); +processing_element pe27_27(.reset(effective_rst), .clk(clk), .in_a(a27_26to27_27), .in_b(b26_27to27_27), .out_a(a27_27to27_28), .out_b(b27_27to28_27), .out_c(matrixC27_27)); +processing_element pe27_28(.reset(effective_rst), .clk(clk), .in_a(a27_27to27_28), .in_b(b26_28to27_28), .out_a(a27_28to27_29), .out_b(b27_28to28_28), .out_c(matrixC27_28)); +processing_element pe27_29(.reset(effective_rst), .clk(clk), .in_a(a27_28to27_29), .in_b(b26_29to27_29), .out_a(a27_29to27_30), .out_b(b27_29to28_29), .out_c(matrixC27_29)); +processing_element pe27_30(.reset(effective_rst), .clk(clk), .in_a(a27_29to27_30), .in_b(b26_30to27_30), .out_a(a27_30to27_31), .out_b(b27_30to28_30), .out_c(matrixC27_30)); +processing_element pe27_31(.reset(effective_rst), .clk(clk), .in_a(a27_30to27_31), .in_b(b26_31to27_31), .out_a(a27_31to27_32), .out_b(b27_31to28_31), .out_c(matrixC27_31)); +processing_element pe28_1(.reset(effective_rst), .clk(clk), .in_a(a28_0to28_1), .in_b(b27_1to28_1), .out_a(a28_1to28_2), .out_b(b28_1to29_1), .out_c(matrixC28_1)); +processing_element pe28_2(.reset(effective_rst), .clk(clk), .in_a(a28_1to28_2), .in_b(b27_2to28_2), .out_a(a28_2to28_3), .out_b(b28_2to29_2), .out_c(matrixC28_2)); +processing_element pe28_3(.reset(effective_rst), .clk(clk), .in_a(a28_2to28_3), .in_b(b27_3to28_3), .out_a(a28_3to28_4), .out_b(b28_3to29_3), .out_c(matrixC28_3)); +processing_element pe28_4(.reset(effective_rst), .clk(clk), .in_a(a28_3to28_4), .in_b(b27_4to28_4), .out_a(a28_4to28_5), .out_b(b28_4to29_4), .out_c(matrixC28_4)); +processing_element pe28_5(.reset(effective_rst), .clk(clk), .in_a(a28_4to28_5), .in_b(b27_5to28_5), .out_a(a28_5to28_6), .out_b(b28_5to29_5), .out_c(matrixC28_5)); +processing_element pe28_6(.reset(effective_rst), .clk(clk), .in_a(a28_5to28_6), .in_b(b27_6to28_6), .out_a(a28_6to28_7), .out_b(b28_6to29_6), .out_c(matrixC28_6)); +processing_element pe28_7(.reset(effective_rst), .clk(clk), .in_a(a28_6to28_7), .in_b(b27_7to28_7), .out_a(a28_7to28_8), .out_b(b28_7to29_7), .out_c(matrixC28_7)); +processing_element pe28_8(.reset(effective_rst), .clk(clk), .in_a(a28_7to28_8), .in_b(b27_8to28_8), .out_a(a28_8to28_9), .out_b(b28_8to29_8), .out_c(matrixC28_8)); +processing_element pe28_9(.reset(effective_rst), .clk(clk), .in_a(a28_8to28_9), .in_b(b27_9to28_9), .out_a(a28_9to28_10), .out_b(b28_9to29_9), .out_c(matrixC28_9)); +processing_element pe28_10(.reset(effective_rst), .clk(clk), .in_a(a28_9to28_10), .in_b(b27_10to28_10), .out_a(a28_10to28_11), .out_b(b28_10to29_10), .out_c(matrixC28_10)); +processing_element pe28_11(.reset(effective_rst), .clk(clk), .in_a(a28_10to28_11), .in_b(b27_11to28_11), .out_a(a28_11to28_12), .out_b(b28_11to29_11), .out_c(matrixC28_11)); +processing_element pe28_12(.reset(effective_rst), .clk(clk), .in_a(a28_11to28_12), .in_b(b27_12to28_12), .out_a(a28_12to28_13), .out_b(b28_12to29_12), .out_c(matrixC28_12)); +processing_element pe28_13(.reset(effective_rst), .clk(clk), .in_a(a28_12to28_13), .in_b(b27_13to28_13), .out_a(a28_13to28_14), .out_b(b28_13to29_13), .out_c(matrixC28_13)); +processing_element pe28_14(.reset(effective_rst), .clk(clk), .in_a(a28_13to28_14), .in_b(b27_14to28_14), .out_a(a28_14to28_15), .out_b(b28_14to29_14), .out_c(matrixC28_14)); +processing_element pe28_15(.reset(effective_rst), .clk(clk), .in_a(a28_14to28_15), .in_b(b27_15to28_15), .out_a(a28_15to28_16), .out_b(b28_15to29_15), .out_c(matrixC28_15)); +processing_element pe28_16(.reset(effective_rst), .clk(clk), .in_a(a28_15to28_16), .in_b(b27_16to28_16), .out_a(a28_16to28_17), .out_b(b28_16to29_16), .out_c(matrixC28_16)); +processing_element pe28_17(.reset(effective_rst), .clk(clk), .in_a(a28_16to28_17), .in_b(b27_17to28_17), .out_a(a28_17to28_18), .out_b(b28_17to29_17), .out_c(matrixC28_17)); +processing_element pe28_18(.reset(effective_rst), .clk(clk), .in_a(a28_17to28_18), .in_b(b27_18to28_18), .out_a(a28_18to28_19), .out_b(b28_18to29_18), .out_c(matrixC28_18)); +processing_element pe28_19(.reset(effective_rst), .clk(clk), .in_a(a28_18to28_19), .in_b(b27_19to28_19), .out_a(a28_19to28_20), .out_b(b28_19to29_19), .out_c(matrixC28_19)); +processing_element pe28_20(.reset(effective_rst), .clk(clk), .in_a(a28_19to28_20), .in_b(b27_20to28_20), .out_a(a28_20to28_21), .out_b(b28_20to29_20), .out_c(matrixC28_20)); +processing_element pe28_21(.reset(effective_rst), .clk(clk), .in_a(a28_20to28_21), .in_b(b27_21to28_21), .out_a(a28_21to28_22), .out_b(b28_21to29_21), .out_c(matrixC28_21)); +processing_element pe28_22(.reset(effective_rst), .clk(clk), .in_a(a28_21to28_22), .in_b(b27_22to28_22), .out_a(a28_22to28_23), .out_b(b28_22to29_22), .out_c(matrixC28_22)); +processing_element pe28_23(.reset(effective_rst), .clk(clk), .in_a(a28_22to28_23), .in_b(b27_23to28_23), .out_a(a28_23to28_24), .out_b(b28_23to29_23), .out_c(matrixC28_23)); +processing_element pe28_24(.reset(effective_rst), .clk(clk), .in_a(a28_23to28_24), .in_b(b27_24to28_24), .out_a(a28_24to28_25), .out_b(b28_24to29_24), .out_c(matrixC28_24)); +processing_element pe28_25(.reset(effective_rst), .clk(clk), .in_a(a28_24to28_25), .in_b(b27_25to28_25), .out_a(a28_25to28_26), .out_b(b28_25to29_25), .out_c(matrixC28_25)); +processing_element pe28_26(.reset(effective_rst), .clk(clk), .in_a(a28_25to28_26), .in_b(b27_26to28_26), .out_a(a28_26to28_27), .out_b(b28_26to29_26), .out_c(matrixC28_26)); +processing_element pe28_27(.reset(effective_rst), .clk(clk), .in_a(a28_26to28_27), .in_b(b27_27to28_27), .out_a(a28_27to28_28), .out_b(b28_27to29_27), .out_c(matrixC28_27)); +processing_element pe28_28(.reset(effective_rst), .clk(clk), .in_a(a28_27to28_28), .in_b(b27_28to28_28), .out_a(a28_28to28_29), .out_b(b28_28to29_28), .out_c(matrixC28_28)); +processing_element pe28_29(.reset(effective_rst), .clk(clk), .in_a(a28_28to28_29), .in_b(b27_29to28_29), .out_a(a28_29to28_30), .out_b(b28_29to29_29), .out_c(matrixC28_29)); +processing_element pe28_30(.reset(effective_rst), .clk(clk), .in_a(a28_29to28_30), .in_b(b27_30to28_30), .out_a(a28_30to28_31), .out_b(b28_30to29_30), .out_c(matrixC28_30)); +processing_element pe28_31(.reset(effective_rst), .clk(clk), .in_a(a28_30to28_31), .in_b(b27_31to28_31), .out_a(a28_31to28_32), .out_b(b28_31to29_31), .out_c(matrixC28_31)); +processing_element pe29_1(.reset(effective_rst), .clk(clk), .in_a(a29_0to29_1), .in_b(b28_1to29_1), .out_a(a29_1to29_2), .out_b(b29_1to30_1), .out_c(matrixC29_1)); +processing_element pe29_2(.reset(effective_rst), .clk(clk), .in_a(a29_1to29_2), .in_b(b28_2to29_2), .out_a(a29_2to29_3), .out_b(b29_2to30_2), .out_c(matrixC29_2)); +processing_element pe29_3(.reset(effective_rst), .clk(clk), .in_a(a29_2to29_3), .in_b(b28_3to29_3), .out_a(a29_3to29_4), .out_b(b29_3to30_3), .out_c(matrixC29_3)); +processing_element pe29_4(.reset(effective_rst), .clk(clk), .in_a(a29_3to29_4), .in_b(b28_4to29_4), .out_a(a29_4to29_5), .out_b(b29_4to30_4), .out_c(matrixC29_4)); +processing_element pe29_5(.reset(effective_rst), .clk(clk), .in_a(a29_4to29_5), .in_b(b28_5to29_5), .out_a(a29_5to29_6), .out_b(b29_5to30_5), .out_c(matrixC29_5)); +processing_element pe29_6(.reset(effective_rst), .clk(clk), .in_a(a29_5to29_6), .in_b(b28_6to29_6), .out_a(a29_6to29_7), .out_b(b29_6to30_6), .out_c(matrixC29_6)); +processing_element pe29_7(.reset(effective_rst), .clk(clk), .in_a(a29_6to29_7), .in_b(b28_7to29_7), .out_a(a29_7to29_8), .out_b(b29_7to30_7), .out_c(matrixC29_7)); +processing_element pe29_8(.reset(effective_rst), .clk(clk), .in_a(a29_7to29_8), .in_b(b28_8to29_8), .out_a(a29_8to29_9), .out_b(b29_8to30_8), .out_c(matrixC29_8)); +processing_element pe29_9(.reset(effective_rst), .clk(clk), .in_a(a29_8to29_9), .in_b(b28_9to29_9), .out_a(a29_9to29_10), .out_b(b29_9to30_9), .out_c(matrixC29_9)); +processing_element pe29_10(.reset(effective_rst), .clk(clk), .in_a(a29_9to29_10), .in_b(b28_10to29_10), .out_a(a29_10to29_11), .out_b(b29_10to30_10), .out_c(matrixC29_10)); +processing_element pe29_11(.reset(effective_rst), .clk(clk), .in_a(a29_10to29_11), .in_b(b28_11to29_11), .out_a(a29_11to29_12), .out_b(b29_11to30_11), .out_c(matrixC29_11)); +processing_element pe29_12(.reset(effective_rst), .clk(clk), .in_a(a29_11to29_12), .in_b(b28_12to29_12), .out_a(a29_12to29_13), .out_b(b29_12to30_12), .out_c(matrixC29_12)); +processing_element pe29_13(.reset(effective_rst), .clk(clk), .in_a(a29_12to29_13), .in_b(b28_13to29_13), .out_a(a29_13to29_14), .out_b(b29_13to30_13), .out_c(matrixC29_13)); +processing_element pe29_14(.reset(effective_rst), .clk(clk), .in_a(a29_13to29_14), .in_b(b28_14to29_14), .out_a(a29_14to29_15), .out_b(b29_14to30_14), .out_c(matrixC29_14)); +processing_element pe29_15(.reset(effective_rst), .clk(clk), .in_a(a29_14to29_15), .in_b(b28_15to29_15), .out_a(a29_15to29_16), .out_b(b29_15to30_15), .out_c(matrixC29_15)); +processing_element pe29_16(.reset(effective_rst), .clk(clk), .in_a(a29_15to29_16), .in_b(b28_16to29_16), .out_a(a29_16to29_17), .out_b(b29_16to30_16), .out_c(matrixC29_16)); +processing_element pe29_17(.reset(effective_rst), .clk(clk), .in_a(a29_16to29_17), .in_b(b28_17to29_17), .out_a(a29_17to29_18), .out_b(b29_17to30_17), .out_c(matrixC29_17)); +processing_element pe29_18(.reset(effective_rst), .clk(clk), .in_a(a29_17to29_18), .in_b(b28_18to29_18), .out_a(a29_18to29_19), .out_b(b29_18to30_18), .out_c(matrixC29_18)); +processing_element pe29_19(.reset(effective_rst), .clk(clk), .in_a(a29_18to29_19), .in_b(b28_19to29_19), .out_a(a29_19to29_20), .out_b(b29_19to30_19), .out_c(matrixC29_19)); +processing_element pe29_20(.reset(effective_rst), .clk(clk), .in_a(a29_19to29_20), .in_b(b28_20to29_20), .out_a(a29_20to29_21), .out_b(b29_20to30_20), .out_c(matrixC29_20)); +processing_element pe29_21(.reset(effective_rst), .clk(clk), .in_a(a29_20to29_21), .in_b(b28_21to29_21), .out_a(a29_21to29_22), .out_b(b29_21to30_21), .out_c(matrixC29_21)); +processing_element pe29_22(.reset(effective_rst), .clk(clk), .in_a(a29_21to29_22), .in_b(b28_22to29_22), .out_a(a29_22to29_23), .out_b(b29_22to30_22), .out_c(matrixC29_22)); +processing_element pe29_23(.reset(effective_rst), .clk(clk), .in_a(a29_22to29_23), .in_b(b28_23to29_23), .out_a(a29_23to29_24), .out_b(b29_23to30_23), .out_c(matrixC29_23)); +processing_element pe29_24(.reset(effective_rst), .clk(clk), .in_a(a29_23to29_24), .in_b(b28_24to29_24), .out_a(a29_24to29_25), .out_b(b29_24to30_24), .out_c(matrixC29_24)); +processing_element pe29_25(.reset(effective_rst), .clk(clk), .in_a(a29_24to29_25), .in_b(b28_25to29_25), .out_a(a29_25to29_26), .out_b(b29_25to30_25), .out_c(matrixC29_25)); +processing_element pe29_26(.reset(effective_rst), .clk(clk), .in_a(a29_25to29_26), .in_b(b28_26to29_26), .out_a(a29_26to29_27), .out_b(b29_26to30_26), .out_c(matrixC29_26)); +processing_element pe29_27(.reset(effective_rst), .clk(clk), .in_a(a29_26to29_27), .in_b(b28_27to29_27), .out_a(a29_27to29_28), .out_b(b29_27to30_27), .out_c(matrixC29_27)); +processing_element pe29_28(.reset(effective_rst), .clk(clk), .in_a(a29_27to29_28), .in_b(b28_28to29_28), .out_a(a29_28to29_29), .out_b(b29_28to30_28), .out_c(matrixC29_28)); +processing_element pe29_29(.reset(effective_rst), .clk(clk), .in_a(a29_28to29_29), .in_b(b28_29to29_29), .out_a(a29_29to29_30), .out_b(b29_29to30_29), .out_c(matrixC29_29)); +processing_element pe29_30(.reset(effective_rst), .clk(clk), .in_a(a29_29to29_30), .in_b(b28_30to29_30), .out_a(a29_30to29_31), .out_b(b29_30to30_30), .out_c(matrixC29_30)); +processing_element pe29_31(.reset(effective_rst), .clk(clk), .in_a(a29_30to29_31), .in_b(b28_31to29_31), .out_a(a29_31to29_32), .out_b(b29_31to30_31), .out_c(matrixC29_31)); +processing_element pe30_1(.reset(effective_rst), .clk(clk), .in_a(a30_0to30_1), .in_b(b29_1to30_1), .out_a(a30_1to30_2), .out_b(b30_1to31_1), .out_c(matrixC30_1)); +processing_element pe30_2(.reset(effective_rst), .clk(clk), .in_a(a30_1to30_2), .in_b(b29_2to30_2), .out_a(a30_2to30_3), .out_b(b30_2to31_2), .out_c(matrixC30_2)); +processing_element pe30_3(.reset(effective_rst), .clk(clk), .in_a(a30_2to30_3), .in_b(b29_3to30_3), .out_a(a30_3to30_4), .out_b(b30_3to31_3), .out_c(matrixC30_3)); +processing_element pe30_4(.reset(effective_rst), .clk(clk), .in_a(a30_3to30_4), .in_b(b29_4to30_4), .out_a(a30_4to30_5), .out_b(b30_4to31_4), .out_c(matrixC30_4)); +processing_element pe30_5(.reset(effective_rst), .clk(clk), .in_a(a30_4to30_5), .in_b(b29_5to30_5), .out_a(a30_5to30_6), .out_b(b30_5to31_5), .out_c(matrixC30_5)); +processing_element pe30_6(.reset(effective_rst), .clk(clk), .in_a(a30_5to30_6), .in_b(b29_6to30_6), .out_a(a30_6to30_7), .out_b(b30_6to31_6), .out_c(matrixC30_6)); +processing_element pe30_7(.reset(effective_rst), .clk(clk), .in_a(a30_6to30_7), .in_b(b29_7to30_7), .out_a(a30_7to30_8), .out_b(b30_7to31_7), .out_c(matrixC30_7)); +processing_element pe30_8(.reset(effective_rst), .clk(clk), .in_a(a30_7to30_8), .in_b(b29_8to30_8), .out_a(a30_8to30_9), .out_b(b30_8to31_8), .out_c(matrixC30_8)); +processing_element pe30_9(.reset(effective_rst), .clk(clk), .in_a(a30_8to30_9), .in_b(b29_9to30_9), .out_a(a30_9to30_10), .out_b(b30_9to31_9), .out_c(matrixC30_9)); +processing_element pe30_10(.reset(effective_rst), .clk(clk), .in_a(a30_9to30_10), .in_b(b29_10to30_10), .out_a(a30_10to30_11), .out_b(b30_10to31_10), .out_c(matrixC30_10)); +processing_element pe30_11(.reset(effective_rst), .clk(clk), .in_a(a30_10to30_11), .in_b(b29_11to30_11), .out_a(a30_11to30_12), .out_b(b30_11to31_11), .out_c(matrixC30_11)); +processing_element pe30_12(.reset(effective_rst), .clk(clk), .in_a(a30_11to30_12), .in_b(b29_12to30_12), .out_a(a30_12to30_13), .out_b(b30_12to31_12), .out_c(matrixC30_12)); +processing_element pe30_13(.reset(effective_rst), .clk(clk), .in_a(a30_12to30_13), .in_b(b29_13to30_13), .out_a(a30_13to30_14), .out_b(b30_13to31_13), .out_c(matrixC30_13)); +processing_element pe30_14(.reset(effective_rst), .clk(clk), .in_a(a30_13to30_14), .in_b(b29_14to30_14), .out_a(a30_14to30_15), .out_b(b30_14to31_14), .out_c(matrixC30_14)); +processing_element pe30_15(.reset(effective_rst), .clk(clk), .in_a(a30_14to30_15), .in_b(b29_15to30_15), .out_a(a30_15to30_16), .out_b(b30_15to31_15), .out_c(matrixC30_15)); +processing_element pe30_16(.reset(effective_rst), .clk(clk), .in_a(a30_15to30_16), .in_b(b29_16to30_16), .out_a(a30_16to30_17), .out_b(b30_16to31_16), .out_c(matrixC30_16)); +processing_element pe30_17(.reset(effective_rst), .clk(clk), .in_a(a30_16to30_17), .in_b(b29_17to30_17), .out_a(a30_17to30_18), .out_b(b30_17to31_17), .out_c(matrixC30_17)); +processing_element pe30_18(.reset(effective_rst), .clk(clk), .in_a(a30_17to30_18), .in_b(b29_18to30_18), .out_a(a30_18to30_19), .out_b(b30_18to31_18), .out_c(matrixC30_18)); +processing_element pe30_19(.reset(effective_rst), .clk(clk), .in_a(a30_18to30_19), .in_b(b29_19to30_19), .out_a(a30_19to30_20), .out_b(b30_19to31_19), .out_c(matrixC30_19)); +processing_element pe30_20(.reset(effective_rst), .clk(clk), .in_a(a30_19to30_20), .in_b(b29_20to30_20), .out_a(a30_20to30_21), .out_b(b30_20to31_20), .out_c(matrixC30_20)); +processing_element pe30_21(.reset(effective_rst), .clk(clk), .in_a(a30_20to30_21), .in_b(b29_21to30_21), .out_a(a30_21to30_22), .out_b(b30_21to31_21), .out_c(matrixC30_21)); +processing_element pe30_22(.reset(effective_rst), .clk(clk), .in_a(a30_21to30_22), .in_b(b29_22to30_22), .out_a(a30_22to30_23), .out_b(b30_22to31_22), .out_c(matrixC30_22)); +processing_element pe30_23(.reset(effective_rst), .clk(clk), .in_a(a30_22to30_23), .in_b(b29_23to30_23), .out_a(a30_23to30_24), .out_b(b30_23to31_23), .out_c(matrixC30_23)); +processing_element pe30_24(.reset(effective_rst), .clk(clk), .in_a(a30_23to30_24), .in_b(b29_24to30_24), .out_a(a30_24to30_25), .out_b(b30_24to31_24), .out_c(matrixC30_24)); +processing_element pe30_25(.reset(effective_rst), .clk(clk), .in_a(a30_24to30_25), .in_b(b29_25to30_25), .out_a(a30_25to30_26), .out_b(b30_25to31_25), .out_c(matrixC30_25)); +processing_element pe30_26(.reset(effective_rst), .clk(clk), .in_a(a30_25to30_26), .in_b(b29_26to30_26), .out_a(a30_26to30_27), .out_b(b30_26to31_26), .out_c(matrixC30_26)); +processing_element pe30_27(.reset(effective_rst), .clk(clk), .in_a(a30_26to30_27), .in_b(b29_27to30_27), .out_a(a30_27to30_28), .out_b(b30_27to31_27), .out_c(matrixC30_27)); +processing_element pe30_28(.reset(effective_rst), .clk(clk), .in_a(a30_27to30_28), .in_b(b29_28to30_28), .out_a(a30_28to30_29), .out_b(b30_28to31_28), .out_c(matrixC30_28)); +processing_element pe30_29(.reset(effective_rst), .clk(clk), .in_a(a30_28to30_29), .in_b(b29_29to30_29), .out_a(a30_29to30_30), .out_b(b30_29to31_29), .out_c(matrixC30_29)); +processing_element pe30_30(.reset(effective_rst), .clk(clk), .in_a(a30_29to30_30), .in_b(b29_30to30_30), .out_a(a30_30to30_31), .out_b(b30_30to31_30), .out_c(matrixC30_30)); +processing_element pe30_31(.reset(effective_rst), .clk(clk), .in_a(a30_30to30_31), .in_b(b29_31to30_31), .out_a(a30_31to30_32), .out_b(b30_31to31_31), .out_c(matrixC30_31)); +processing_element pe31_1(.reset(effective_rst), .clk(clk), .in_a(a31_0to31_1), .in_b(b30_1to31_1), .out_a(a31_1to31_2), .out_b(b31_1to32_1), .out_c(matrixC31_1)); +processing_element pe31_2(.reset(effective_rst), .clk(clk), .in_a(a31_1to31_2), .in_b(b30_2to31_2), .out_a(a31_2to31_3), .out_b(b31_2to32_2), .out_c(matrixC31_2)); +processing_element pe31_3(.reset(effective_rst), .clk(clk), .in_a(a31_2to31_3), .in_b(b30_3to31_3), .out_a(a31_3to31_4), .out_b(b31_3to32_3), .out_c(matrixC31_3)); +processing_element pe31_4(.reset(effective_rst), .clk(clk), .in_a(a31_3to31_4), .in_b(b30_4to31_4), .out_a(a31_4to31_5), .out_b(b31_4to32_4), .out_c(matrixC31_4)); +processing_element pe31_5(.reset(effective_rst), .clk(clk), .in_a(a31_4to31_5), .in_b(b30_5to31_5), .out_a(a31_5to31_6), .out_b(b31_5to32_5), .out_c(matrixC31_5)); +processing_element pe31_6(.reset(effective_rst), .clk(clk), .in_a(a31_5to31_6), .in_b(b30_6to31_6), .out_a(a31_6to31_7), .out_b(b31_6to32_6), .out_c(matrixC31_6)); +processing_element pe31_7(.reset(effective_rst), .clk(clk), .in_a(a31_6to31_7), .in_b(b30_7to31_7), .out_a(a31_7to31_8), .out_b(b31_7to32_7), .out_c(matrixC31_7)); +processing_element pe31_8(.reset(effective_rst), .clk(clk), .in_a(a31_7to31_8), .in_b(b30_8to31_8), .out_a(a31_8to31_9), .out_b(b31_8to32_8), .out_c(matrixC31_8)); +processing_element pe31_9(.reset(effective_rst), .clk(clk), .in_a(a31_8to31_9), .in_b(b30_9to31_9), .out_a(a31_9to31_10), .out_b(b31_9to32_9), .out_c(matrixC31_9)); +processing_element pe31_10(.reset(effective_rst), .clk(clk), .in_a(a31_9to31_10), .in_b(b30_10to31_10), .out_a(a31_10to31_11), .out_b(b31_10to32_10), .out_c(matrixC31_10)); +processing_element pe31_11(.reset(effective_rst), .clk(clk), .in_a(a31_10to31_11), .in_b(b30_11to31_11), .out_a(a31_11to31_12), .out_b(b31_11to32_11), .out_c(matrixC31_11)); +processing_element pe31_12(.reset(effective_rst), .clk(clk), .in_a(a31_11to31_12), .in_b(b30_12to31_12), .out_a(a31_12to31_13), .out_b(b31_12to32_12), .out_c(matrixC31_12)); +processing_element pe31_13(.reset(effective_rst), .clk(clk), .in_a(a31_12to31_13), .in_b(b30_13to31_13), .out_a(a31_13to31_14), .out_b(b31_13to32_13), .out_c(matrixC31_13)); +processing_element pe31_14(.reset(effective_rst), .clk(clk), .in_a(a31_13to31_14), .in_b(b30_14to31_14), .out_a(a31_14to31_15), .out_b(b31_14to32_14), .out_c(matrixC31_14)); +processing_element pe31_15(.reset(effective_rst), .clk(clk), .in_a(a31_14to31_15), .in_b(b30_15to31_15), .out_a(a31_15to31_16), .out_b(b31_15to32_15), .out_c(matrixC31_15)); +processing_element pe31_16(.reset(effective_rst), .clk(clk), .in_a(a31_15to31_16), .in_b(b30_16to31_16), .out_a(a31_16to31_17), .out_b(b31_16to32_16), .out_c(matrixC31_16)); +processing_element pe31_17(.reset(effective_rst), .clk(clk), .in_a(a31_16to31_17), .in_b(b30_17to31_17), .out_a(a31_17to31_18), .out_b(b31_17to32_17), .out_c(matrixC31_17)); +processing_element pe31_18(.reset(effective_rst), .clk(clk), .in_a(a31_17to31_18), .in_b(b30_18to31_18), .out_a(a31_18to31_19), .out_b(b31_18to32_18), .out_c(matrixC31_18)); +processing_element pe31_19(.reset(effective_rst), .clk(clk), .in_a(a31_18to31_19), .in_b(b30_19to31_19), .out_a(a31_19to31_20), .out_b(b31_19to32_19), .out_c(matrixC31_19)); +processing_element pe31_20(.reset(effective_rst), .clk(clk), .in_a(a31_19to31_20), .in_b(b30_20to31_20), .out_a(a31_20to31_21), .out_b(b31_20to32_20), .out_c(matrixC31_20)); +processing_element pe31_21(.reset(effective_rst), .clk(clk), .in_a(a31_20to31_21), .in_b(b30_21to31_21), .out_a(a31_21to31_22), .out_b(b31_21to32_21), .out_c(matrixC31_21)); +processing_element pe31_22(.reset(effective_rst), .clk(clk), .in_a(a31_21to31_22), .in_b(b30_22to31_22), .out_a(a31_22to31_23), .out_b(b31_22to32_22), .out_c(matrixC31_22)); +processing_element pe31_23(.reset(effective_rst), .clk(clk), .in_a(a31_22to31_23), .in_b(b30_23to31_23), .out_a(a31_23to31_24), .out_b(b31_23to32_23), .out_c(matrixC31_23)); +processing_element pe31_24(.reset(effective_rst), .clk(clk), .in_a(a31_23to31_24), .in_b(b30_24to31_24), .out_a(a31_24to31_25), .out_b(b31_24to32_24), .out_c(matrixC31_24)); +processing_element pe31_25(.reset(effective_rst), .clk(clk), .in_a(a31_24to31_25), .in_b(b30_25to31_25), .out_a(a31_25to31_26), .out_b(b31_25to32_25), .out_c(matrixC31_25)); +processing_element pe31_26(.reset(effective_rst), .clk(clk), .in_a(a31_25to31_26), .in_b(b30_26to31_26), .out_a(a31_26to31_27), .out_b(b31_26to32_26), .out_c(matrixC31_26)); +processing_element pe31_27(.reset(effective_rst), .clk(clk), .in_a(a31_26to31_27), .in_b(b30_27to31_27), .out_a(a31_27to31_28), .out_b(b31_27to32_27), .out_c(matrixC31_27)); +processing_element pe31_28(.reset(effective_rst), .clk(clk), .in_a(a31_27to31_28), .in_b(b30_28to31_28), .out_a(a31_28to31_29), .out_b(b31_28to32_28), .out_c(matrixC31_28)); +processing_element pe31_29(.reset(effective_rst), .clk(clk), .in_a(a31_28to31_29), .in_b(b30_29to31_29), .out_a(a31_29to31_30), .out_b(b31_29to32_29), .out_c(matrixC31_29)); +processing_element pe31_30(.reset(effective_rst), .clk(clk), .in_a(a31_29to31_30), .in_b(b30_30to31_30), .out_a(a31_30to31_31), .out_b(b31_30to32_30), .out_c(matrixC31_30)); +processing_element pe31_31(.reset(effective_rst), .clk(clk), .in_a(a31_30to31_31), .in_b(b30_31to31_31), .out_a(a31_31to31_32), .out_b(b31_31to32_31), .out_c(matrixC31_31)); +assign a_data_out = {a31_31to31_32,a30_31to30_32,a29_31to29_32,a28_31to28_32,a27_31to27_32,a26_31to26_32,a25_31to25_32,a24_31to24_32,a23_31to23_32,a22_31to22_32,a21_31to21_32,a20_31to20_32,a19_31to19_32,a18_31to18_32,a17_31to17_32,a16_31to16_32,a15_31to15_32,a14_31to14_32,a13_31to13_32,a12_31to12_32,a11_31to11_32,a10_31to10_32,a9_31to9_32,a8_31to8_32,a7_31to7_32,a6_31to6_32,a5_31to5_32,a4_31to4_32,a3_31to3_32,a2_31to2_32,a1_31to1_32,a0_31to0_32}; +assign b_data_out = {b31_31to32_31,b31_30to32_30,b31_29to32_29,b31_28to32_28,b31_27to32_27,b31_26to32_26,b31_25to32_25,b31_24to32_24,b31_23to32_23,b31_22to32_22,b31_21to32_21,b31_20to32_20,b31_19to32_19,b31_18to32_18,b31_17to32_17,b31_16to32_16,b31_15to32_15,b31_14to32_14,b31_13to32_13,b31_12to32_12,b31_11to32_11,b31_10to32_10,b31_9to32_9,b31_8to32_8,b31_7to32_7,b31_6to32_6,b31_5to32_5,b31_4to32_4,b31_3to32_3,b31_2to32_2,b31_1to32_1,b31_0to32_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + out_temp <= 0; + end else begin + out_temp <= add_out; + end +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count = cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef SIMULATION + +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +reg [31:0] i; + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + + +endmodule + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count = cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count = cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_32x32_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd32), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 99555d626..91108dbac 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -19,10 +19,13 @@ valid_flows = vpr_blif,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , clb_blocks = "Netlist clb blocks: ([0-9]+)", str +io_blocks = "Netlist io blocks: ([0-9]+)", str +mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str +memory_blocks = "Netlist memory blocks: ([0-9]+)", str logic_delay = "Total logic delay: ([0-9.]+)", str total_net_delay = "total net delay: ([0-9.]+)", str -total_routing_area = "Total routing area: ([0-9.]+)", str -total_logic_block_area = "Total used logic block area: ([0-9]+)", str +total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str +total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str total_wire_length = "Total wirelength: ([0-9]+)", str packing_time = "Packing took ([0-9.]+) seconds", str placement_time = "Placement took ([0-9.]+) seconds", str diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index 131bddd3c..587769941 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -2,5 +2,6 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -no_adder -top ${TOP_MODULE} +synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS} +write_verilog -noattr -nohex ${OUTPUT_VERILOG} diff --git a/openfpga_flow/misc/yosys_bram_adder_template.ys b/openfpga_flow/misc/yosys_bram_adder_template.ys deleted file mode 100644 index fe82173f4..000000000 --- a/openfpga_flow/misc/yosys_bram_adder_template.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for alu4 -# read Verilog -read_verilog /full_path/design.v #can be repeated if project has many files -read_verilog -lib /full_path/cells_sim.v # file we provide - -hierarchy -check -top top_module -proc - -flatten -tribuf -logic - -synth -run coarse -opt -fast - -memory -nomap -opt_clean - - -memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt -techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v -opt -fast -mux_undef -undriven -fine -memory_map - -# Technology mapping -#proc -techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v - -# Synthesis -synth -top top_module -flatten -run fine -clean - -# LUT mapping -abc -lut 6 - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_blif design.blif -write_verilog design.v diff --git a/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys b/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys new file mode 100644 index 000000000..b53746aab --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys @@ -0,0 +1,4 @@ +# Rewrite the .blif to Verilog +# so that the pin sequence matches +read_blif rewritten_${OUTPUT_BLIF} +write_verilog ${OUTPUT_VERILOG} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys new file mode 100644 index 000000000..7244532e5 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -0,0 +1,105 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map flip-flops +######################### +techmap -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys new file mode 100644 index 000000000..a81474999 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -0,0 +1,105 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map flip-flops +######################### +techmap -map +/adff2dff.v +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys new file mode 100644 index 000000000..6a8bf372b --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -0,0 +1,89 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################### +# Run coarse synthesis +######################### +# Extract arithmetic functions +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map flip-flops +######################### +techmap -map +/adff2dff.v +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys new file mode 100644 index 000000000..edd21c94c --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys @@ -0,0 +1,27 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG} + +# Synthesis +synth -top ${TOP_MODULE} -flatten +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# FF mapping +techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys new file mode 100644 index 000000000..849ea9811 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys @@ -0,0 +1,96 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map flip-flops +######################### +techmap -map +/adff2dff.v +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} \ No newline at end of file diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys new file mode 100644 index 000000000..edcce4c23 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys @@ -0,0 +1,22 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +${READ_VERILOG_FILE} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +synth -top ${TOP_MODULE} -flatten +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_blif rewritten_${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index 73f412c9c..9ba9073f3 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -6,6 +6,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f * The keyword 'frac' is to specify if fracturable LUT is used or not. * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. +- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs - scan\_chain: If scan chain testing infrastructure is used inside CLBs diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml new file mode 100644 index 000000000..cd12856c5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index d40e7bea2..796f9974d 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -206,9 +206,9 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 000000000..1114d0071 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,289 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 000000000..78978c2c7 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,295 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml new file mode 100644 index 000000000..ed8f0134c --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml @@ -0,0 +1,287 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml new file mode 100644 index 000000000..d1cf24921 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml @@ -0,0 +1,333 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml new file mode 100644 index 000000000..e66611fb0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml @@ -0,0 +1,279 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index a0548c54c..2eb5765c9 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -20,12 +20,7 @@ always @ (posedge CK) begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -46,14 +41,8 @@ always @ (posedge CK) begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -79,12 +68,7 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; -`else - assign Q = 1'bZ; -`endif +assign Q = q_reg; endmodule //End Of Module @@ -111,14 +95,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -144,14 +122,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -178,14 +150,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -211,14 +177,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -249,14 +209,8 @@ end else begin q_reg <= D; end -// Wire q_reg to Q -`ifndef ENABLE_FORMAL_VERIFICATION - assign Q = q_reg; - assign QN = ~q_reg; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = ~q_reg; endmodule //End Of Module @@ -289,6 +243,57 @@ assign Q = q_reg; endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +// - asynchronous set +// which can be switched between active-low and active high +//----------------------------------------------------- +module MULTI_MODE_DFFSRQ ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_set = mode[1] ? ~SET : SET; +wire post_reset = mode[0] ? ~RST : RST; + +DFFSRQ FF_CORE (.SET(post_set), + .RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +//----------------------------------------------------- +module MULTI_MODE_DFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_reset = mode ? ~RST : RST; + +DFFRQ FF_CORE (.RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset @@ -321,14 +326,8 @@ end else begin q_reg <= D; end -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; - assign QN = !Q; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = !Q; endmodule //End Of Module @@ -434,13 +433,7 @@ end assign CFGQ = CFGE ? Q : 1'b0; assign CFGQN = CFGE ? QN : 1'b1; -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q - assign Q = q_reg; - assign QN = !Q; -`else - assign Q = 1'bZ; - assign QN = !Q; -`endif +assign Q = q_reg; +assign QN = !Q; endmodule //End Of Module diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v new file mode 100644 index 000000000..bf5b630be --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v @@ -0,0 +1,61 @@ +//----------------------------------------------------- +// Design Name : dpram_1024x8 +// File Name : dpram8.v +// Function : Wrapper module of dual port RAM 1024 addresses x 8 bit +// Coder : Xifan tang +//----------------------------------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input[0:9] waddr, + input[0:9] raddr, + input[0:7] data_in, + output[0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------------------------------- +// Design Name : dpram_1024x8_core +// File Name : dpram8.v +// Function : Core module of dual port RAM 1024 addresses x 8 bit +// Coder : Xifan tang +//----------------------------------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg[0:7] ram[0:1023]; + reg[0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v b/openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v new file mode 100644 index 000000000..fa56d30cb --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v @@ -0,0 +1,62 @@ +//----------------------------------------------------- +// Design Name : dpram_2048x8 +// File Name : dpram_2048x8.v +// Function : Dual port RAM 2048 x 8bit +// Coder : Xifan Tang +//----------------------------------------------------- + +module dpram_2048x8 ( + input clk, + input wen, + input ren, + input[0:10] waddr, + input[0:10] raddr, + input[0:7] data_in, + output[0:7] data_out ); + + dual_port_sram memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------------------------------- +// Design Name : dpram_2048x8_core +// File Name : dpram_2048x8.v +// Function : Core module of dual port RAM 2048 addresses x 8 bit +// Coder : Xifan tang +//----------------------------------------------------- +module dual_port_sram ( + input wclk, + input wen, + input[0:10] waddr, + input[0:7] data_in, + input rclk, + input ren, + input[0:10] raddr, + output[0:7] data_out ); + + reg[0:7] ram[0:2047]; + reg[0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v index 0b5461615..d5410b5bf 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_lut4_arith.v @@ -63,7 +63,7 @@ wire [0:0] sky130_fd_sc_hd__or2_1_0_X; .A(in[1]), .Y(sky130_fd_sc_hd__inv_1_1_Y[0])); - assign arith_in2 = mode[0] ? in[2] : cin; + assign arith_in2 = mode[0] ? cin : in[2]; sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A(arith_in2), @@ -82,7 +82,7 @@ wire [0:0] sky130_fd_sc_hd__or2_1_0_X; .X(sky130_fd_sc_hd__buf_2_1_X[0])); sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( - .A(in[2]), + .A(arith_in2), .X(sky130_fd_sc_hd__buf_2_2_X[0])); sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v new file mode 100644 index 000000000..d73a1c7e1 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v @@ -0,0 +1,29 @@ +//----------------------------------------------------- +// Design Name : frac_mult_16x16 +// File Name : frac_mult_16x16.v +// Function : A 16-bit multiplier which can operate in fracturable modes: +// 1. two 8-bit multipliers +// 2. one 16-bit multipliers +// Coder : Xifan Tang +//----------------------------------------------------- + +module frac_mult_16x16 ( + input [0:15] a, + input [0:15] b, + output [0:31] out, + input [0:0] mode); + + reg [0:31] out_reg; + + always @(mode, a, b) begin + if (1'b1 == mode) begin + out_reg[0:15] <= a[0:7] * b[0:7]; + out_reg[16:31] <= a[8:15] * b[8:15]; + end else begin + out_reg <= a * b; + end + end + + assign out = out_reg; + +endmodule diff --git a/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v b/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v new file mode 100644 index 000000000..a8649488b --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v @@ -0,0 +1,16 @@ +//----------------------------------------------------- +// Design Name : mult_8x8 +// File Name : mult_8x8.v +// Function : A 8-bit multiplier +// Coder : Xifan Tang +//----------------------------------------------------- + +module mult_8x8 ( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + + assign Y = A * B; + +endmodule diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga index f8b7245b9..be124317b 100644 --- a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga @@ -55,17 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --support_icarus_simulator --explicit_port_mapping - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index a5cbbaf16..d0e0d69e2 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -58,7 +58,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga index 67c1419bd..00944653e 100644 --- a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga @@ -55,7 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga index 3bc847bdf..1e1b46d23 100644 --- a/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,7 @@ write_fabric_verilog --file ./FABRIC_NETLIST --explicit_port_mapping --include_t # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --fabric_netlist_file_path ${OPENFPGA_FABRIC_NETLIST_FILE} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga index 227e1fdda..55c54adb7 100644 --- a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga @@ -55,7 +55,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga index 18b7c97f2..a31f81948 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga new file mode 100644 index 000000000..e614455cf --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga index 0699d4ea6..77af24936 100644 --- a/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping --fast_configuration +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fast_configuration --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga index ef37d9242..594d2e21b 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga new file mode 100644 index 000000000..4a826bffe --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA bitstream settings +read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga index b5fd710b6..1e1db546d 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga @@ -45,7 +45,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -57,7 +57,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index 054f74c0e..7ca431e92 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga new file mode 100644 index 000000000..9f2742315 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga index dccde3d8c..2fc56e4c7 100644 --- a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga index 18b7c97f2..84c107af9 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga new file mode 100644 index 000000000..31717063b --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga index fcbf6e144..467cac0c3 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga @@ -26,7 +26,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga index b7a856dfd..c2107e0cb 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga @@ -46,7 +46,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga index 8d8d07d32..0431c5f75 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga @@ -46,7 +46,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index b88e5370a..0b5cfa232 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -51,7 +51,7 @@ write_fabric_bitstream --file fabric_bitstream --format xml # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./TESTBENCH --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} --bitstream fabric_bitstream.bit # Write the SDC to run timing analysis for a mapped FPGA fabric write_analysis_sdc --file ./SDC_analysis diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index b418685ab..086dc9eb0 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -45,7 +45,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -57,7 +57,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga new file mode 100644 index 000000000..d15fb05e5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index 93af8bdb1..1b1daae4d 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -49,7 +49,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -61,7 +61,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} #--explicit_port_mapping +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index 6c793bc88..31296021f 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga index e161d8e2f..1741f3011 100644 --- a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga @@ -42,6 +42,9 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose @@ -52,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga new file mode 100644 index 000000000..49f1aac73 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -0,0 +1,60 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +# Note: no need to assign activity file when you used a fixed number +# of clock cycles in simulation settings +# Also, ACE2 does not support multiple clocks +# Therefore, activity file is not recommended for multi-clock fabric/implementations +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup #--verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga index 976087ded..1a94138a4 100644 --- a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga @@ -46,7 +46,7 @@ build_architecture_bitstream --verbose \ build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -58,7 +58,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga index 6c753df2f..78daebb4b 100644 --- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga @@ -37,7 +37,7 @@ repack #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose # Build fabric-dependent bitstream build_fabric_bitstream --verbose @@ -46,9 +46,7 @@ build_fabric_bitstream --verbose # - Enable the use of explicit port mapping in Verilog netlist write_fabric_verilog --file ./SRC \ --explicit_port_mapping \ - --include_timing \ - --include_signal_init -# --support_icarus_simulator + --include_timing # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -56,17 +54,8 @@ write_fabric_verilog --file ./SRC \ # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ./${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga new file mode 100644 index 000000000..f07f5e2a5 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga @@ -0,0 +1,57 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream ${OPENFPGA_EMBEDDED_BITSTREAM_HDL_TYPE} --file ./SRC --explicit_port_mapping + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga new file mode 100644 index 000000000..7fd7053f8 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh index 6b568e5d8..c222fa6d5 100644 --- a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh +++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh @@ -1,4 +1,12 @@ foreach i (*.openfpga) - sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i - sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +# sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i +# sed -i 's/simulation_deck\.ini/simulation_deck\.ini --include_signal_init --support_icarus_simulator/g' $i +end + +foreach i (*.openfpga) + sed -i 's/--support_icarus_simulator//g' $i +end + +foreach i (*.openfpga) + sed -i 's/write_preconfigured_fabric_wrapper/write_preconfigured_fabric_wrapper --embed_bitstream iverilog/g' $i end diff --git a/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga new file mode 100644 index 000000000..7fd9666f0 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga @@ -0,0 +1,54 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.txt --format plain_text +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Report bitstream distribution to a file +report_bitstream_distribution ${OPENFPGA_REPORT_BITSTREAM_DISTRIBUTION_OPTIONS} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga index 6887cd8a4..3810aa37b 100644 --- a/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga @@ -42,27 +42,15 @@ build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream. # Build fabric-dependent bitstream build_fabric_bitstream --verbose -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping - # Write the SDC files for PnR backend # - Turn on every options here -write_pnr_sdc --time_unit ps --file ./SDC +write_pnr_sdc --time_unit ${OPENFPGA_SDC_TIME_UNIT} --file ./SDC # Write SDC to disable timing for configure ports write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --time_unit ps --file ./SDC_analysis +write_analysis_sdc --time_unit ${OPENFPGA_SDC_TIME_UNIT} --file ./SDC_analysis # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga index e9195e9e7..7dd793dbe 100644 --- a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga index 6cb86439c..3dc4da3da 100644 --- a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga @@ -43,7 +43,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist @@ -55,7 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE} # Write the SDC files for PnR backend # - Turn on every options here diff --git a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga new file mode 100644 index 000000000..49f1aac73 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga @@ -0,0 +1,60 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +# The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +# Note: no need to assign activity file when you used a fixed number +# of clock cycles in simulation settings +# Also, ACE2 does not support multiple clocks +# Therefore, activity file is not recommended for multi-clock fabric/implementations +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup #--verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga new file mode 100644 index 000000000..612249a15 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION} + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga new file mode 100644 index 000000000..62735f8bd --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga @@ -0,0 +1,38 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Write I/O net mapping information +write_io_mapping --file io_mapping.xml --verbose + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v new file mode 100644 index 000000000..1c9940188 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v @@ -0,0 +1,12 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + +assign Y = A * B; + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v new file mode 100644 index 000000000..e492482f4 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v @@ -0,0 +1,20 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8x8 ( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_8 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v new file mode 100644 index 000000000..d455c79d0 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v @@ -0,0 +1,25 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// 16-bit multiplier +//----------------------------- +module mult_16( + input [0:15] A, + input [0:15] B, + output [0:31] Y +); + +assign Y = A * B; + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v new file mode 100644 index 000000000..035e6f7eb --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v @@ -0,0 +1,41 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8x8 ( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_8 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule + +//----------------------------- +// 16-bit multiplier +//----------------------------- +module mult_16x16 ( + input [0:15] A, + input [0:15] B, + output [0:31] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_16 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt new file mode 100644 index 000000000..00e6a7ce2 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_1024x8 + init 0 + abits 10 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_1024x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v new file mode 100644 index 000000000..804077258 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_1024x8 ( + output [0:7] B1DATA, + input CLK1, + input [0:9] B1ADDR, + input [0:9] A1ADDR, + input [0:7] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_1024x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v new file mode 100644 index 000000000..bc8f1206e --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v @@ -0,0 +1,72 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:1023]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [0:9] waddr, + input [0:9] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 36-bit multiplier +//----------------------------- +module mult_36( + input [0:35] A, + input [0:35] B, + output [0:71] Y +); + +assign Y = A * B; + +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v new file mode 100644 index 000000000..977afdb13 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v @@ -0,0 +1,17 @@ +module mult_36x36 ( + input [0:35] A, + input [0:35] B, + output [0:71] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_36 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v new file mode 100644 index 000000000..cc64801a3 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v @@ -0,0 +1,220 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:1023]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [0:9] waddr, + input [0:9] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 36-bit multiplier +//----------------------------- +module mult_36( + input [0:35] A, + input [0:35] B, + output [0:71] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v new file mode 100644 index 000000000..f8eed8db0 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt new file mode 100644 index 000000000..51617f271 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_128x8 + init 0 + abits 7 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_128x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v new file mode 100644 index 000000000..8cf462c1a --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_128x8 ( + output [0:7] B1DATA, + input CLK1, + input [0:6] B1ADDR, + input [0:6] A1ADDR, + input [0:7] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_128x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v new file mode 100644 index 000000000..9ec66e6ee --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v @@ -0,0 +1,58 @@ +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v new file mode 100644 index 000000000..9d82dc715 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v @@ -0,0 +1,15 @@ +//--------------------------------------- +// 1-bit adder +//--------------------------------------- +module adder( + input cin, + input a, + input b, + output cout, + output sumout ); + + + assign sumout = a ^ b ^ cin; + assign cout = (a & b) | ((a | b) & cin); + +endmodule diff --git a/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams.txt b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams.txt rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams_map.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/cells_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v similarity index 81% rename from openfpga_flow/misc/OpenFPGA_lib/cells_sim.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v index 514aefd85..cd1f2e8f4 100644 --- a/openfpga_flow/misc/OpenFPGA_lib/cells_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v @@ -48,15 +48,4 @@ module dual_port_sram ( endmodule -module adder( - input cin, - input a, - input b, - output cout, - output sumout ); - - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | ((a | b) & cin); - -endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v new file mode 100644 index 000000000..8c6c149c4 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -0,0 +1,75 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async reset, enable +module \$_DFFE_PP0P_ (D, C, E, R, Q); + input D; + input C; + input E; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); +endmodule + +// Latch with Async reset, enable +module \$_DLATCH_PP0_ (input E, R, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + latchre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R)); +endmodule + +// The following techmap operation are not performed right now +// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10 +// but in case we implement clock inversion in the future, the support is ready for it. +module \$_DFF_N_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +module \$_DFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +module \$_DFFE_NP0P_ (D, C, E, R, Q); + input D; + input C; + input E; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v new file mode 100644 index 000000000..12b9e8ec3 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -0,0 +1,127 @@ +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +(* abc9_flop, lib_whitebox *) +module dffre( + output reg Q, + input D, + input R, + input E, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else if(E) + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else if(E) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +(* abc9_flop, lib_whitebox *) +module latchre ( + output reg Q, + input S, + input R, + input D, + input G, + input E +); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @* + begin + if (R) Q <= 1'b0; + if (S) Q <= 1'b1; + else if (E && G) Q <= D; + end +endmodule diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 591883df0..0a11ed4e0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -53,6 +53,10 @@ run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs +echo -e "Testing testbenches without self checking features"; +run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking --debug --show_thread_logs + echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs @@ -84,6 +88,8 @@ run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug - echo -e "Testing K4 series FPGA"; echo -e "Testing K4N4 with facturable LUTs"; run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs +echo -e "Testing K4N4 with asynchronous reset"; +run-task basic_tests/k4_series/k4n4_fracff --debug --show_thread_logs echo -e "Testing K4N4 with hard adders"; run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs echo -e "Testing K4N4 without local routing architecture"; diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index e5b0c2f42..58858e0b9 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -11,7 +11,6 @@ echo -e "FPGA-Bitstream regression tests"; echo -e "Testing bitstream generation for an auto-sized device"; run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs - echo -e "Testing bitstream generation for an 48x48 FPGA device"; run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs @@ -23,3 +22,13 @@ run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thre echo -e "Testing repacker capability in identifying wire LUTs"; run-task fpga_bitstream/repack_wire_lut --debug --show_thread_logs + +echo -e "Testing overloading default paths for programmable interconnect when generating bitstream"; +run-task fpga_bitstream/overload_mux_default_path --debug --show_thread_logs + +echo -e "Testing outputting I/O mapping result to file"; +run-task fpga_bitstream/write_io_mapping --debug --show_thread_logs + +echo -e "Testing report bitstream distribution to file"; +run-task fpga_bitstream/report_bitstream_distribution/default_depth --debug --show_thread_logs +run-task fpga_bitstream/report_bitstream_distribution/custom_depth --debug --show_thread_logs diff --git a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh index c4ff67a09..713c328b9 100755 --- a/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_sdc_reg_test.sh @@ -9,4 +9,12 @@ PYTHON_EXEC=python3.8 echo -e "FPGA-SDC regression tests"; echo -e "Testing SDC generation with time units"; -run-task fpga_sdc/sdc_time_unit --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_as --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_fs --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ps --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ns --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_us --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ms --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_default --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_ks --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit/sdc_time_unit_Ms --debug --show_thread_logs diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 450bc262c..044821b3e 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -38,11 +38,20 @@ run-task fpga_verilog/adder/hard_adder --debug --show_thread_logs echo -e "Testing Verilog generation with soft adder chain in CLBs "; run-task fpga_verilog/adder/soft_adder --debug --show_thread_logs -echo -e "Testing Verilog generation with 16k block RAMs "; -run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs +echo -e "Testing Verilog generation with 1k block RAMs "; +run-task fpga_verilog/bram/dpram1k --debug --show_thread_logs -echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; -run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs +echo -e "Testing Verilog generation with 1k block RAMs spanning two columns "; +run-task fpga_verilog/bram/wide_dpram1k --debug --show_thread_logs + +echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers "; +run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs + +echo -e "Testing Verilog generation with heterogeneous fabric using 16-bit multi-mode multipliers "; +run-task fpga_verilog/dsp/multi_mode_mult_16x16 --debug --show_thread_logs + +echo -e "Testing Verilog generation with heterogeneous fabric using multi-width 16-bit multi-mode multipliers "; +run-task fpga_verilog/dsp/wide_multi_mode_mult_16x16 --debug --show_thread_logs echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs @@ -128,8 +137,6 @@ echo -e "Testing through channels in tileable routing"; run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs -# Verify MCNC big20 benchmark suite with ModelSim -# Please make sure you have ModelSim installed in the environment -# Otherwise, it will fail -#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 -#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators"; +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs diff --git a/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh new file mode 100755 index 000000000..1c00bd150 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/iwls_benchmark_reg_test.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "IWLS'05 benchmark regression tests"; +run-task benchmark_sweep/iwls2005 --debug --show_thread_logs +# Run a quick but relaxed QoR check for heterogeneous blocks +#python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100 +python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv --check_tolerance 0.2,100 diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh new file mode 100755 index 000000000..5f958e261 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "Micro benchmark regression tests"; +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs + +# Verify MCNC big20 benchmark suite with ModelSim +# Please make sure you have ModelSim installed in the environment +# Otherwise, it will fail +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim + +run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh new file mode 100755 index 000000000..4ca761a3e --- /dev/null +++ b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "VTR benchmark regression tests"; +run-task benchmark_sweep/vtr_benchmarks --debug --show_thread_logs +# Run a quick but relaxed QoR check for heterogeneous blocks +python3 openfpga_flow/scripts/check_qor.py --reference_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv --check_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/latest/task_result.csv --metric_checklist_csv_file openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv --check_tolerance 0.2,100 diff --git a/openfpga_flow/scripts/check_qor.py b/openfpga_flow/scripts/check_qor.py new file mode 100644 index 000000000..9b55e64c1 --- /dev/null +++ b/openfpga_flow/scripts/check_qor.py @@ -0,0 +1,129 @@ +##################################################################### +# Python script to check if heterogeneous blocks, e.g., RAM and multipliers +# have been inferred during openfpga flow +# # This script will +# - Check the .csv file generated by openfpga task-run to find out +# the number of each type of heterogeneous blocks +##################################################################### + +import os +from os.path import dirname, abspath, isfile +import shutil +import re +import argparse +import logging +import csv + +##################################################################### +# Contants +##################################################################### +csv_name_tag = "name" +csv_metric_tag = "metric" + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG) + +##################################################################### +# Parse the options +# - [mandatory option] the file path to .csv file +##################################################################### +parser = argparse.ArgumentParser( + description='A checker for hetergeneous block mapping in OpenFPGA flow') +parser.add_argument('--check_csv_file', required=True, + help='Specify the to-be-checked csv file constaining flow-run information') +parser.add_argument('--reference_csv_file', required=True, + help='Specify the reference csv file constaining flow-run information') +parser.add_argument('--metric_checklist_csv_file', required=True, + help='Specify the csv file constaining metrics to be checked') +# By default, allow a 50% tolerance when checking metrics +parser.add_argument('--check_tolerance', default="0.5,1.5", + help='Specify the tolerance when checking metrics. Format ,') +args = parser.parse_args() + +##################################################################### +# Check options: +# - Input csv files must be valid +# Otherwise, error out +##################################################################### +if not isfile(args.check_csv_file): + logging.error("Invalid csv file to check: " + args.check_csv_file + "\nFile does not exist!\n") + exit(1) + +if not isfile(args.reference_csv_file): + logging.error("Invalid reference csv file: " + args.reference_csv_file + "\nFile does not exist!\n") + exit(1) + +if not isfile(args.metric_checklist_csv_file): + logging.error("Invalid metric checklist csv file: " + args.metric_checklist_csv_file + "\nFile does not exist!\n") + exit(1) + +##################################################################### +# Parse a checklist for metrics to be checked +##################################################################### +metric_checklist_csv_file = open(args.metric_checklist_csv_file, "r") +metric_checklist_csv_content = csv.DictReader(filter(lambda row : row[0]!='#', metric_checklist_csv_file), delimiter=',') +# Hash the reference results with the name tag +metric_checklist = [] +for row in metric_checklist_csv_content: + metric_checklist.append(row[csv_metric_tag]); + +##################################################################### +# Parse the reference csv file +# Skip any line start with '#' which is treated as comments +##################################################################### +ref_csv_file = open(args.reference_csv_file, "r") +ref_csv_content = csv.DictReader(filter(lambda row : row[0]!='#', ref_csv_file), delimiter=',') +# Hash the reference results with the name tag +ref_results = {} +for row in ref_csv_content: + ref_results[row[csv_name_tag]] = row; + +##################################################################### +# Parse the tolerance to be applied when checking metrics +##################################################################### +lower_bound_factor = float(args.check_tolerance.split(",")[0]) +upper_bound_factor = float(args.check_tolerance.split(",")[1]) + +##################################################################### +# Parse the csv file to check +##################################################################### +with open(args.check_csv_file, newline='') as check_csv_file: + results_to_check = csv.DictReader(check_csv_file, delimiter=',') + checkpoint_count = 0 + check_error_count = 0 + for row in results_to_check: + # Start from line 1 and check information + for metric_to_check in metric_checklist: + # Check if the metric is in a range + if (lower_bound_factor * float(ref_results[row[csv_name_tag]][metric_to_check]) > float(row[metric_to_check])) or (upper_bound_factor * float(ref_results[row[csv_name_tag]][metric_to_check]) < float(row[metric_to_check])) : + # Check QoR failed, error out + logging.error("Benchmark " + str(row[csv_name_tag]) + " failed in checking '" + str(metric_to_check) +"'\n" + "Found: " + str(row[metric_to_check]) + " but expected: " + str(ref_results[row[csv_name_tag]][metric_to_check]) + " outside range [" + str(lower_bound_factor * 100) + "%, " + str(upper_bound_factor * 100) + "%]") + check_error_count += 1 + # Pass this metric check, increase counter + checkpoint_count += 1 + logging.info("Checked " + str(checkpoint_count) + " metrics") + logging.info("See " + str(check_error_count) + " QoR failures") + + if (0 < check_error_count): + exit(1) + +##################################################################### +# Post checked results on stdout: +# reaching here, it means all the checks have passed +##################################################################### +with open(args.check_csv_file, newline='') as check_csv_file: + results_to_check = csv.DictReader(check_csv_file, delimiter=',') + # Print out keywords: name + metric checklist + print(str(csv_name_tag) + " ", end='') + for metric_to_check in metric_checklist: + print(str(metric_to_check) + " ", end='') + print("") + + for row in results_to_check: + # Start from line 1, print checked metrics + print(row[csv_name_tag] + " ", end='') + for metric_to_check in metric_checklist: + print(row[metric_to_check] + " ", end='') + print("") diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 66472e3c8..93883d330 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -99,6 +99,8 @@ parser.add_argument('--arch_variable_file', type=str, default=None, # help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") +parser.add_argument('--ys_rewrite_tmpl', type=str, default=None, + help="Alternate yosys template, to rewrite verilog netlist") parser.add_argument('--disp', action="store_true", help="Open display while running VPR") parser.add_argument('--debug', action="store_true", @@ -260,7 +262,7 @@ def main(): if args.power: run_ace2() run_pro_blif_3arg() - else: + else: # Make a copy of the blif file to be compatible with vpr flow shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif") @@ -269,7 +271,7 @@ def main(): if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() - logger.info("Runing OpenFPGA Shell Engine ") + logger.info("Running OpenFPGA Shell Engine ") run_openfpga_shell() if args.end_flow_with_test: run_netlists_verification() @@ -302,7 +304,7 @@ def check_required_file(): } for filename, filepath in files_dict.items(): if not os.path.isfile(filepath): - clean_up_and_exit("Not able to locate deafult file " + filename) + clean_up_and_exit("Not able to locate default file " + filename) def read_script_config(): @@ -345,7 +347,7 @@ def validate_command_line_arguments(): - Activity file - Base verilog file ''' - logger.info("Validating commnad line arguments") + logger.info("Validating command line arguments") if args.debug: logger.info("Setting loggger in debug mode") @@ -361,19 +363,19 @@ def validate_command_line_arguments(): dependent = dependent.split(",") for eachdep in dependent: if not any([getattr(args, i, 0) for i in eachdep.split("|")]): - clean_up_and_exit("'%s' argument depends on (%s) argumets" % + clean_up_and_exit("'%s' argument depends on (%s) arguments" % (eacharg, ", ".join(dependent).replace("|", " or "))) # Check if architecrue files exists args.arch_file = os.path.abspath(args.arch_file) if not os.path.isfile(args.arch_file): clean_up_and_exit( - "VPR architecture file not found. -%s", + "VPR architecture file not found. -%s"% args.arch_file) args.openfpga_arch_file = os.path.abspath(args.openfpga_arch_file) if not os.path.isfile(args.openfpga_arch_file): clean_up_and_exit( - "OpenFPGA architecture file not found. -%s", + "OpenFPGA architecture file not found. -%s"% args.openfpga_arch_file) # Filter provided benchmark files @@ -387,14 +389,14 @@ def validate_command_line_arguments(): for everyfile in glob.glob(args.benchmark_files[index]): if not os.path.isfile(everyfile): clean_up_and_exit( - "Failed to copy benchmark file-%s", args.arch_file) + "Failed to copy benchmark file -%s" % args.arch_file) # Filter provided powertech files if args.power_tech: args.power_tech = os.path.abspath(args.power_tech) if not os.path.isfile(args.power_tech): clean_up_and_exit( - "Power Tech file not found. -%s", args.power_tech) + "Power Tech file not found. -%s" % args.power_tech) # Expand run directory to absolute path args.run_dir = os.path.abspath(args.run_dir) @@ -481,14 +483,19 @@ def run_yosys_with_abc(): clean_up_and_exit("") args.K = lut_size # Yosys script parameter mapping - ys_params = { - "READ_VERILOG_FILE": " \n".join([ + ys_params = script_env_vars["PATH"] + ys_params["READ_VERILOG_FILE"] = " \n".join([ "read_verilog -nolatches " + shlex.quote(eachfile) - for eachfile in args.benchmark_files]), - "TOP_MODULE": args.top_module, - "LUT_SIZE": lut_size, - "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", - } + for eachfile in args.benchmark_files]) + ys_params["TOP_MODULE"] = args.top_module + ys_params["LUT_SIZE"] = lut_size + ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif" + ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v" + + for indx in range(0, len(OpenFPGAArgs), 2): + tmpVar = OpenFPGAArgs[indx][2:].upper() + ys_params[tmpVar] = OpenFPGAArgs[indx+1] + yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") tmpl = Template(open(yosys_template, encoding='utf-8').read()) @@ -687,12 +694,41 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"): def run_rewrite_verilog(): # Rewrite the verilog after optimization - script_cmd = [ - "read_blif %s" % args.top_module+".blif", - "write_verilog %s" % args.top_module+"_output_verilog.v" - ] - command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] - run_command("Yosys", "yosys_rewrite.log", command) + # If there is no template script provided, use a default template + # If there is a template script provided, replace parameters from configuration + if not args.ys_rewrite_tmpl: + script_cmd = [ + "read_blif %s" % args.top_module+".blif", + "write_verilog %s" % args.top_module+"_output_verilog.v" + ] + command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] + run_command("Yosys", "yosys_rewrite.log", command) + else: + # Yosys script parameter mapping + ys_rewrite_params = { + "READ_VERILOG_FILE": " \n".join([ + "read_verilog -nolatches " + shlex.quote(eachfile) + for eachfile in args.benchmark_files]), + "TOP_MODULE": args.top_module, + "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", + "INPUT_BLIF": args.top_module+".blif", + "OUTPUT_VERILOG": args.top_module+"_output_verilog.v" + } + + for indx in range(0, len(OpenFPGAArgs), 2): + tmpVar = OpenFPGAArgs[indx][2:].upper() + ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1] + + # Split a series of scripts by delim ';' + # And execute the scripts serially + for iteration_idx, curr_rewrite_tmpl in enumerate(args.ys_rewrite_tmpl.split(";")): + tmpl = Template(open(curr_rewrite_tmpl, encoding='utf-8').read()) + logger.info("Yosys rewrite iteration: " + str(iteration_idx)) + with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile: + archfile.write(tmpl.safe_substitute(ys_rewrite_params)) + run_command("Run yosys", "yosys_rewrite_output.log", + [cad_tools["yosys_path"], "yosys_rewrite_" + str(iteration_idx) + ".ys"]) + def run_netlists_verification(exit_if_fail=True): @@ -705,11 +741,6 @@ def run_netlists_verification(exit_if_fail=True): command = [cad_tools["iverilog_path"]] command += ["-o", compiled_file] - fpga_define_file = "./SRC/define_simulation.v" - fpga_define_file_bk = "./SRC/define_simulation.v.bak" - shutil.copy(fpga_define_file, fpga_define_file_bk) - with open(fpga_define_file, "r") as fp: - fpga_defines = fp.readlines() command += ["./SRC/%s_include_netlists.v" % args.top_module] command += ["-s"] @@ -717,11 +748,6 @@ def run_netlists_verification(exit_if_fail=True): command += [tb_top_formal] else: command += [tb_top_autochecked] - with open(fpga_define_file, "w") as fp: - for eachLine in fpga_defines: - if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or - "FORMAL_SIMULATION" in eachLine): - fp.write(eachLine) run_command("iverilog_verification", "iverilog_output.txt", command) vvp_command = ["vvp", compiled_file] @@ -779,7 +805,8 @@ def filter_openfpga_output(vpr_output): def filter_failed_process_output(vpr_output): for line in vpr_output.split("\n"): - if "error" in line.lower(): + elements_to_log = ["error", "what()"] + if any(match in line.lower() for match in elements_to_log): logger.error("-->>" + line) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index fa297932e..c1ced3ccb 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -168,14 +168,20 @@ def generate_each_task_actions(taskname): # Check if task directory exists and consistent local_tasks = os.path.join(*(taskname)) repo_tasks = os.path.join(gc["task_dir"], *(taskname)) + abs_tasks = os.path.abspath('/' + local_tasks) if os.path.isdir(local_tasks): os.chdir(local_tasks) curr_task_dir = os.path.abspath(os.getcwd()) + elif os.path.isdir(abs_tasks): + curr_task_dir = abs_tasks elif os.path.isdir(repo_tasks): curr_task_dir = repo_tasks else: - clean_up_and_exit("Task directory [%s] not found" % curr_task_dir) - + clean_up_and_exit("Task directory [%s] not found" % taskname + + " locally at [%s]" % local_tasks + + ", absolutely at [%s]" % abs_tasks + + ", or in OpenFPGA task directory [%s]" % repo_tasks) + os.chdir(curr_task_dir) curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf") @@ -254,7 +260,11 @@ def generate_each_task_actions(taskname): # Read provided benchmark configurations # Common configurations + # - All the benchmarks may share the same yosys synthesis template script + # - All the benchmarks may share the same rewrite yosys template script, which converts post-synthesis .v netlist to be compatible with .blif port definition. This is required for correct verification at the end of flows + # - All the benchmarks may share the same routing channel width in VPR runs. This is designed to enable architecture evaluations for a fixed device model ys_for_task_common = SynthSection.get("bench_yosys_common") + ys_rewrite_for_task_common = SynthSection.get("bench_yosys_rewrite_common") chan_width_common = SynthSection.get("bench_chan_width_common") # Individual benchmark configuration @@ -263,8 +273,15 @@ def generate_each_task_actions(taskname): fallback="top") CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys", fallback=ys_for_task_common) + CurrBenchPara["ys_rewrite_script"] = SynthSection.get(bech_name+"_yosys_rewrite", + fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + CurrBenchPara["benchVariable"] = [] + for eachKey, eachValue in SynthSection.items(): + if bech_name in eachKey: + eachKey = eachKey.replace(bech_name+"_", "").upper() + CurrBenchPara["benchVariable"] += [f"--{eachKey}", eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -296,6 +313,13 @@ def generate_each_task_actions(taskname): benchmark_list.append(CurrBenchPara) + # Count the number of duplicated top module name among benchmark + # This is required as flow run directory names for these benchmarks are different than others + # which are uniquified + benchmark_top_module_count = [] + for bench in benchmark_list: + benchmark_top_module_count.append(bench["top_module"]) + # Create OpenFPGA flow run commnad for each combination of # architecture, benchmark and parameters # Create run_job object [arch, bench, run_dir, commnad] @@ -303,7 +327,11 @@ def generate_each_task_actions(taskname): for indx, arch in enumerate(archfile_list): for bench in benchmark_list: for lbl, param in bench["script_params"].items(): - flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) + if (benchmark_top_module_count.count(bench["top_module"]) > 1): + flow_run_dir = get_flow_rundir(arch, "bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"], lbl) + else: + flow_run_dir = get_flow_rundir(arch, bench["top_module"], lbl) + command = create_run_command( curr_job_dir=flow_run_dir, archfile=arch, @@ -315,7 +343,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command, + "commands": command + bench["benchVariable"], "finished": False, "status": False}) @@ -324,6 +352,9 @@ def generate_each_task_actions(taskname): logger.info('Created total %d jobs' % len(flow_run_cmd_list)) return flow_run_cmd_list +# Make the directory name unique by including the benchmark index in the list. +# This is because benchmarks may share the same top module names + def get_flow_rundir(arch, top_module, flow_params=None): path = [ @@ -381,6 +412,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if benchmark_obj.get("ys_script"): command += ["--yosys_tmpl", benchmark_obj["ys_script"]] + if benchmark_obj.get("ys_rewrite_script"): + command += ["--ys_rewrite_tmpl", benchmark_obj["ys_rewrite_script"]] + if task_gc.getboolean("power_analysis"): command += ["--power"] command += ["--power_tech", task_gc.get("power_tech_file")] diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf index 069541110..14110892b 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf @@ -34,4 +34,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf index 787e469d0..474f802dc 100644 --- a/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf @@ -36,4 +36,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf index 3fea70cef..d80ebe9c4 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf @@ -16,11 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_device_layout=--device 2x2 --route_chan_width 40 +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf index 78daaf0c9..cb41e9959 100644 --- a/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -34,4 +36,3 @@ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf index 7ae2d1334..1f818415a 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_config_enable_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_config_enable_scff/config/task.conf index 8fd922fd9..a554331f3 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_config_enable_scff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_config_enable_scff/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf index 9d7ea2d8d..0707f4df2 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf index 4efa817a1..627e7a9ec 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf index 37a1eb75b..e452a2371 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf index 94acf3ed8..da327282e 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf index d3290d175..1706a4e4e 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf index aaee4c7c9..0389fee37 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf index 37d68988c..576a1888b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf index 2a8cded3f..7daaf775c 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf index 40b3c6f9b..27b6005e8 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf index d6f4a1812..3d3c4acdd 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf index 86edcefec..81d1067d9 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf index e91cbd103..0a19f0e50 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf index 63baba79e..1247d8f78 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf index 6f4200ffe..71dbae458 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -27,6 +29,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/blinking/blinking.v [SYNTHESIS_PARAM] bench0_top = and2 @@ -38,5 +41,8 @@ bench1_chan_width = 300 bench2_top = and2_latch bench2_chan_width = 300 +bench3_top = blinking +bench3_chan_width = 300 + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf index 51f2344fe..10d5bfd62 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf index 14425886d..f9b1656f1 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf index 2ee58fbf2..afd572370 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index 5510c7a8c..c8789b46a 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf index 1ceeb3384..03c0b97ed 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf index adaf26a25..f980071c0 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf new file mode 100644 index 000000000..2fe7d3e62 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/full_testbench_without_self_checking/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf index 960cc0358..bd08da556 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf index 88f00dd83..d20ef4ee8 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf index 2db9c982f..502cd68ae 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf index 1b27c683c..33ea7546f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf index 1e15dba22..52e103c6f 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf index 6f166e5fc..1ea736ca9 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf index eff60d97e..dd4bea019 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_chain/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 +openfpga_vpr_device_layout=--device 2x2 +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf index 85771410c..b3c193558 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_configuration_frame/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf index 41c819a8c..004f3701a 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_memory_bank/config/task.conf @@ -16,10 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 +openfpga_vpr_device_layout=--device 2x2 +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf index 4fac7ac49..56f90daef 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf index d4a77cd79..38e2e9556 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf index f7e99fd89..b7368ad66 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf index ed7db9ae5..a5f85fc2b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_chain/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf index 4f9b28e27..13da04cef 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_configuration_frame/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_frame_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf index 66d4da4fb..29fcb228d 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_multi_region_memory_bank/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration=--fast_configuration [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf index db41b7f5a..958c8b9ec 100644 --- a/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf @@ -20,6 +20,10 @@ arch_variable_file=${PATH:TASK_DIR}/design_variables.yml openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +# Use a absolute path for the Verilog netlists to be generated +# This is designed to allow the test case 'basic_tests/generate_testbench' +# to use the Verilog netlists along with testbenches in HDL simulation +openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf index 42d3c5733..db8399fbb 100644 --- a/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf @@ -12,23 +12,27 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 1*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +# Here, we use a fabric netlist generated by another task +# to show case the correctness of testbench generator +# Caution: You MUST run the task 'basic_tests/generate_fabric' +# before this task!!! +openfpga_fabric_verilog_netlist=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/fabric_netlists.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index 275a32b57..feb6dfbaa 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -9,37 +9,30 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 -# Due to the limitation in ACE2 which cannot output .blif files -# with correct multi-clock assignments to .latch lines -# We have to use the vpr_blif flow where the .blif is modified -# based on yosys outputs with correct clock assignment! -# TODO: This limitation should be removed and we should use yosys_vpr flow!!! -fpga_flow=vpr_blif -#fpga_flow=yosys_vpr +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif -#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v [SYNTHESIS_PARAM] -bench0_top = counter4bit_2clock -bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act -bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v -bench0_chan_width = 300 +bench0_top = counter_4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml +bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index abc1be003..ab945d768 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=auto [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index ff0985799..6caa13456 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -12,26 +12,28 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 3*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml new file mode 100644 index 000000000..abcf209f6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..cdef2ad86 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf new file mode 100644 index 000000000..2408323ed --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf new file mode 100644 index 000000000..d511bdbb9 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking/config/task.conf @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 9d5a92747..6fefdb16d 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -9,29 +9,45 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 5*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# # Use a fixed routing channel width to save runtime +vpr_route_chan_width=50 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +#bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + bench0_top = counter -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v -bench0_chan_width = 300 +bench1_top = counter +bench2_top = counter +bench3_top = counter [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +#end_flow_with_test= #vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv new file mode 100644 index 000000000..fe07fa1c1 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/iwls_benchmark_golden_results.csv @@ -0,0 +1,20 @@ +mult_blocks,total_routing_area,total_routing_time,TotalRunTime,packing_time,name,io_blocks,memory_blocks,placement_time,average_net_length,routing_time,clb_blocks,critical_path,total_wire_length,total_logic_block_area +0,8.02931,3.53,143,85.87,00_eth_top_MIN_ROUTE_CHAN_WIDTH,211,4,6.78,15.2037,3.53,292,4.34288e-09,36945,1 +0,7.23279,3.54,108,53.90,00_mc_top_MIN_ROUTE_CHAN_WIDTH,267,0,5.49,17.0883,3.54,254,7.331640000000001e-09,35800,1 +0,620306.,0.17,14,10.78,00_simple_spi_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.33,7.10949,0.17,18,2.56241e-09,974,970092 +0,5.94202,3.04,85,34.23,00_tv80s_MIN_ROUTE_CHAN_WIDTH,46,0,3.71,19.8659,3.04,202,8.90858e-09,32600,1 +0,1.13704,5.56,211,139.55,00_vga_enh_top_MIN_ROUTE_CHAN_WIDTH,196,11,10.12,16.2042,5.56,414,3.8128200000000005e-09,63472,2 +0,7.23279,2.87,338,31.76,00_aes_cipher_top_MIN_ROUTE_CHAN_WIDTH,388,0,6.09,14.2891,2.87,267,4.37135e-09,30993,1 +0,9.51115,4.49,274,51.71,00_aes_inv_cipher_top_MIN_ROUTE_CHAN_WIDTH,389,16,7.55,15.5093,4.49,343,4.749290000000001e-09,40898,2 +1,1.13704,6.18,431,91.44,00_fpu_MIN_ROUTE_CHAN_WIDTH,110,0,8.42,14.6717,6.18,429,1.6591900000000002e-07,58012,2 +0,1.13704,5.7,275,201.24,00_pci_bridge32_MIN_ROUTE_CHAN_WIDTH,367,0,11.01,14.4637,5.70,424,4.54535e-09,64002,2 +0,2.10319,0.84,25,11.70,00_spi_top_MIN_ROUTE_CHAN_WIDTH,90,0,1.25,14.5174,0.84,69,5.46323e-09,7941,3 +0,4.62242,1.97,60,29.06,00_aes_MIN_ROUTE_CHAN_WIDTH,389,0,3.77,15.9033,1.97,151,5.37676e-09,21883,8 +0,8.86284,4.28,199,139.64,00_usbf_top_MIN_ROUTE_CHAN_WIDTH,235,0,6.63,17.6241,4.28,305,5.084290000000001e-09,48290,1 +0,1.21212,86.15,694,97.52,00_wb_conmax_top_MIN_ROUTE_CHAN_WIDTH,2546,0,64.43,42.0125,86.15,831,5.21772e-09,258839,4 +0,789582.,0.3,10,5.62,00_i2c_master_top_MIN_ROUTE_CHAN_WIDTH,33,0,0.41,7.73636,0.30,23,3.07388e-09,1702,1 +0,620306.,0.16,8,4.79,00_sasc_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.24,6.14844,0.16,17,1.77641e-09,787,916198 +0,417802.,0.1,4,2.35,00_pcm_slv_top_MIN_ROUTE_CHAN_WIDTH,28,0,0.14,5.20548,0.10,9,1.68994e-09,380,485046 +0,1.43501,0.49,42,31.70,00_des_MIN_ROUTE_CHAN_WIDTH,189,0,0.84,9.10709,0.49,43,3.6623500000000003e-09,5783,2 +0,620306.,0.15,6,2.75,00_usb_phy_MIN_ROUTE_CHAN_WIDTH,33,0,0.21,6.56044,0.15,13,1.75847e-09,597,700622 +0,3.94926,1.45,78,31.64,00_wb_dma_top_MIN_ROUTE_CHAN_WIDTH,431,0,2.89,13.4492,1.45,85,4.274350000000001e-09,14041,4 diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv new file mode 100644 index 000000000..2adc74073 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/metric_checklist.csv @@ -0,0 +1,6 @@ +########################################################## +# Metrics to check for IWLS benchmark bitstream generation +########################################################## +metric +mult_blocks +memory_blocks diff --git a/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf new file mode 100644 index 000000000..79929256d --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf @@ -0,0 +1,99 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# Use a fixed routing channel width to save runtime +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml + +[BENCHMARKS] +# RTL netlists from IWLS 2005 benchmark release +# Comment out it requires falling edge latches which are not supported yet +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ac97_ctrl/rtl/*.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ethernet/rtl/*.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/mem_ctrl/rtl/*.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.v +# Comment out due to VHDL is not supported by Yosys without Verific +#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/steppermotordrive/rtl/*.vhd +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v +# AES core has two top modules that can be tested: encryption and decryption +# Synthesis is too long; skip it +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v +bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v +## DES has two versions: area-optimized and performance optimized +# The DES has same top-level module name as systemcdes +# Currently openfpga flow has a bug which does not allow same top-level module name +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v +bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v +bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v +bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v +bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcdes/rtl/*.v +bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_phy/rtl/*.v +bench22=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_dma/rtl/*.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +bench0_top = ac97_top +bench1_top = eth_top +bench2_top = mc_top +bench3_top = simple_spi_top +bench4_top = StepperMotorPorts +bench5_top = tv80s +bench6_top = vga_enh_top +bench7_top = aes_cipher_top +bench8_top = aes_inv_cipher_top +bench9_top = fpu +bench10_top = pci_bridge32 +bench11_top = spi_top +bench12_top = aes +bench13_top = usbf_top +bench14_top = wb_conmax_top +# Not sure either des or des3 is the top module. Need further investigation +bench15_top = des +bench16_top = des3 +bench17_top = i2c_master_top +bench18_top = sasc_top +bench19_top = pcm_slv_top +# May conflict with the top module name with other 'des' benchmark; This is a bug of openfpga flow scripts +bench20_top = des +bench21_top = usb_phy +bench22_top = wb_dma_top + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf new file mode 100644 index 000000000..0fddaa91a --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/mac_units/config/task.conf @@ -0,0 +1,67 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# Use a fixed routing channel width to save runtime +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v +bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v +bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v +bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v +bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_32/mac_32.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +bench0_top = mac_2 +bench1_top = mac_4 +bench2_top = mac_6 +bench3_top = mac_8 +bench4_top = mac_8_9 +bench5_top = mac_9 +bench6_top = mac_12 +bench7_top = mac_16 +bench8_top = mac_18 +bench9_top = mac_20 +bench10_top = mac_32 +bench11_top = mac_36 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf new file mode 100644 index 000000000..9ada9e960 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v + +[SYNTHESIS_PARAM] +bench0_top = clock_divider +bench0_chan_width = 300 + +bench1_top = pulse_generator +bench1_chan_width = 300 + +bench2_top = reset_generator +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv new file mode 100644 index 000000000..80ebbc544 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/metric_checklist.csv @@ -0,0 +1,6 @@ +########################################################## +# Metrics to check for VTR benchmark bitstream generation +########################################################## +metric +mult_blocks +memory_blocks diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf new file mode 100644 index 000000000..278b07b8f --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf @@ -0,0 +1,95 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +# VPR parameters +# Use a fixed routing channel width to save runtime +vpr_route_chan_width=300 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml + +[BENCHMARKS] +# Official benchmarks from VTR benchmark release +# Comment out due to high runtime +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/bgm.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v +# Failed due to an unknown error in VPR netlist parser +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v +bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v +bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v +# Comment out due to high runtime +#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v +# Comment out due to high runtime +#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v +# Comment out due to high runtime +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mcml.v +bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v +bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v +bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v +bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v +bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v +bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v +bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v +# Comment out due to high runtime +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v +bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v +# Additional benchmarks after VTR benchmark release +#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v +#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/spree.v +#bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +# Benchmark ch_intrinsics +bench0_top = bgm +bench1_top = RLE_BlobMerging +bench2_top = paj_boundtop_hierarchy_no_mem +bench3_top = memset +bench4_top = diffeq_paj_convert +bench5_top = diffeq_f_systemC +bench6_top = LU8PEEng +bench7_top = LU32PEEng +bench8_top = mcml +bench9_top = mkDelayWorker32B +bench10_top = mkPktMerge +bench11_top = mkSMAdapter4B +bench12_top = or1200_flat +bench13_top = paj_raygentop_hierarchy_no_mem +bench14_top = sha1 +bench15_top = sv_chip0_hierarchy_no_mem +bench16_top = sv_chip1_hierarchy_no_mem +bench17_top = sv_chip2_hierarchy_no_mem +bench18_top = sv_chip3_hierarchy_no_mem +bench19_top = arm_core +bench20_top = system +bench21_top = LU64PEEng + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv new file mode 100644 index 000000000..af8842eed --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv @@ -0,0 +1,28 @@ +##################################################################### +# A database of benchmarks to be checked +# Reference: https://janders.eecg.utoronto.ca/pdfs/p77-rose.pdf +# Name,number of multipliers,number of RAMs +# IMPORTANT: +# - the name is tuned due to the naming convention of openfpga task-run script +# - the limitation should be CHANGED!!! +##################################################################### +name,mult_blocks,memory_blocks +00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0 +00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0 +00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1 +00_memset_MIN_ROUTE_CHAN_WIDTH,0,1 +00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0 +00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0 +00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9 +00_LU32PEEng_MIN_ROUTE_CHAN_WIDTH,32,9 +00_mcml_MIN_ROUTE_CHAN_WIDTH,30,10 +00_mkDelayWorker32B_MIN_ROUTE_CHAN_WIDTH,0,9 +00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3 +00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3 +00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2 +00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1 +00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0 +00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0 +00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0 +00_sv_chip2_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,564,0 +00_sv_chip3_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0 diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/bitstream_annotation.xml new file mode 100644 index 000000000..519a837ef --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/bitstream_annotation.xml @@ -0,0 +1,3 @@ + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/task.conf new file mode 100644 index 000000000..70fe861c2 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/overload_mux_default_path/config/bitstream_annotation.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench0_top = and2_pipelined +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/custom_depth/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/custom_depth/config/task.conf new file mode 100644 index 000000000..ad24a1dd3 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/custom_depth/config/task.conf @@ -0,0 +1,33 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_report_bitstream_distribution_options=--file bitstream_distribution.xml --depth 2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/default_depth/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/default_depth/config/task.conf new file mode 100644 index 000000000..fcbcb6a63 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/report_bitstream_distribution/default_depth/config/task.conf @@ -0,0 +1,33 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_report_bitstream_distribution_options=--file bitstream_distribution.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_bitstream/write_io_mapping/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/write_io_mapping/config/task.conf new file mode 100644 index 000000000..a61ec038b --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/write_io_mapping/config/task.conf @@ -0,0 +1,32 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_Ms/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_Ms/config/task.conf new file mode 100644 index 000000000..d7f988af5 --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_Ms/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=Ms + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_as/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_as/config/task.conf new file mode 100644 index 000000000..ad84fe5ad --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_as/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=as + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_default/config/task.conf similarity index 98% rename from openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf rename to openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_default/config/task.conf index 88e4314d6..db23c45de 100644 --- a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_default/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=vpr_blif openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=s [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_fs/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_fs/config/task.conf new file mode 100644 index 000000000..1bcbd0e88 --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_fs/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=fs + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ks/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ks/config/task.conf new file mode 100644 index 000000000..5d8005eff --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ks/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=ks + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ms/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ms/config/task.conf new file mode 100644 index 000000000..be0a5abef --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ms/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=ms + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ns/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ns/config/task.conf new file mode 100644 index 000000000..1c9166bd6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ns/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=ns + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ps/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ps/config/task.conf new file mode 100644 index 000000000..cd347fb06 --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_ps/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=ps + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_us/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_us/config/task.conf new file mode 100644 index 000000000..a7becff2b --- /dev/null +++ b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/sdc_time_unit_us/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sdc_time_unit=us + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/bram/dpram1k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram1k/config/task.conf new file mode 100644 index 000000000..67ab566f4 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/bram/dpram1k/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v +# VPR parameter +openfpga_vpr_device_layout=3x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys +bench0_top = dual_port_ram_1k + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram1k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram1k/config/task.conf new file mode 100644 index 000000000..234150aa1 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram1k/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v +# VPR parameter +openfpga_vpr_device_layout=4x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/dual_port_ram_1k/dual_port_ram_1k.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys +bench0_top = dual_port_ram_1k + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf new file mode 100644 index 000000000..b9e2c957b --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +# VPR parameter +openfpga_vpr_device_layout=3x4 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mac_4 +bench1_top = mac_8 +bench2_top = mac_12 +bench3_top = mac_16 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf new file mode 100644 index 000000000..a03071351 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +# VPR parameter +openfpga_vpr_device_layout=3x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mac_2 +bench1_top = mac_4 +bench2_top = mac_6 +bench3_top = mac_8 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf new file mode 100644 index 000000000..3923047e8 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +# VPR parameter +openfpga_vpr_device_layout=4x4 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_wide_frac_dsp16_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mac_8 +bench1_top = mac_16 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf index 700f8e3c7..9f7cd13a3 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf index 1e919ff29..9bc003ff1 100644 --- a/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf @@ -16,9 +16,11 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf similarity index 82% rename from openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf index b7d8715ec..9b755a5c7 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim/config/task.conf @@ -12,17 +12,17 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 +timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=3x2 +openfpga_embedded_bitstream_hdl_type=modelsim [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif @@ -31,8 +31,5 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. bench0_top = and2 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf similarity index 82% rename from openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf index d8dc5d26d..c93d2fed8 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/embed_bitstream_none/config/task.conf @@ -12,17 +12,17 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 +timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=4x4 +openfpga_embedded_bitstream_hdl_type=none [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif @@ -31,8 +31,5 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2. bench0_top = and2 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index f7f2a8b06..df4d8b854 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=none arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index 898412cd2..568ded5e4 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=wire arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/synthesizable_verilog/config/task.conf index 22fe003b9..0e60465b0 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/synthesizable_verilog/config/task.conf @@ -16,12 +16,12 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga #openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=auto -openfpga_vpr_route_chan_width=20 +openfpga_vpr_device_layout=--device auto --route_chan_width 20 +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index df236e1cf..d36b504c5 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 71529c23b..e3400e574 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_circuit_format=eblif +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -32,7 +33,8 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/c bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v +#cavlc_top requires async reset/preset +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v # counter120bitx5 requires 5 clocks #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v @@ -40,48 +42,41 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_ bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v +#i2c_master_top requires async reset/preset +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v +#iir requires async reset/preset +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v +#jpeg_qnr requires async reset/preset +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v # sdc_controller requires 4 clocks #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys + bench0_top = io_tc1 -bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench1_top = unsigned_mult_80 -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench2_top = bin2bcd -bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench3_top = counter -bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench5_top = rs_decoder_top -bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench6_top = top_module -bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench7_top = sha256 -bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench8_top = cavlc_top -bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +#bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench9_top = cf_fft_256_8 -bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench10_top = counter120bitx5 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench11_top = top -bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench12_top = dct_mac -bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench13_top = des_perf -bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench14_top = diffeq_f_systemC -bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench15_top = i2c_master_top -bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +#bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench16_top = iir -bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +#bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench17_top = jpeg_qnr -bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +#bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench18_top = multi_enc_decx2x4 # sdc_controller requires 4 clocks #bench19_top = sdc_controller diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml index 735d45c23..b02afba78 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml @@ -1,3 +1,4 @@ + diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 6a5f29063..12f1bebe1 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -21,21 +21,26 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml openfpga_vpr_circuit_format=eblif +yosys_args = -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v [SYNTHESIS_PARAM] -bench1_top = adder_8 -bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = adder_4 +bench1_top = adder_6 +bench2_top = adder_8 +bench3_top = adder_16 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -########################## -# The output verilog of yosys is not synthesizable!!! -# Turn off verification for now -# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow end_flow_with_test= vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index 9ee9dd0ff..f3862b1ee 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -7,6 +7,7 @@ Please reveal the following architecture features in the names to help quickly s - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. - tileable: If the routing architecture is tileable or not. * The keyword 'IO' specifies if the I/O tile is tileable or not +- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs - scan\_chain: If scan chain testing infrastructure is used inside CLBs diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml new file mode 100644 index 000000000..5351486bc --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -0,0 +1,620 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 000000000..187a3e474 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,907 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.reg_out clb.sc_out clb.cout + + + + + + + + + + + + + + + + mult_8.a[0:2] mult_8.b[0:2] mult_8.out[0:5] + mult_8.a[3:5] mult_8.b[3:5] mult_8.out[6:10] + mult_8.a[6:7] mult_8.b[6:7] mult_8.out[11:15] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml @@ -118,14 +118,14 @@ - + - + @@ -135,7 +135,7 @@ - + @@ -180,15 +180,21 @@ - - - + + + - + - + + memory.clk + + memory.wen memory.waddr[0:3] memory.raddr[0:3] memory.data_in[0:2] memory.data_out[0:2] + memory.ren memory.waddr[4:7] memory.raddr[4:7] memory.data_in[3:5] memory.data_out[3:5] + memory.waddr[8:11] memory.raddr[8:11] memory.data_in[6:7] memory.data_out[6:7] + @@ -682,57 +688,57 @@ - - - + + + - + - - - - - - - - - + + + + + + + + - - - - - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml new file mode 100644 index 000000000..a34b29c22 --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml @@ -0,0 +1,828 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml similarity index 93% rename from openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml index 53ad0929f..170e65818 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem1K_40nm.xml @@ -118,14 +118,14 @@ - + - + @@ -135,7 +135,7 @@ - + @@ -164,6 +164,7 @@ + @@ -180,15 +181,23 @@ - - - + + + - + - - + + + + + memory.clk + + memory.wen memory.waddr[0:2] memory.raddr[0:2] memory.data_in[0:2] memory.data_out[0:2] + memory.ren memory.waddr[3:5] memory.raddr[3:5] memory.data_in[3:5] memory.data_out[3:5] + memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:7] memory.data_out[6:7] + @@ -682,57 +691,57 @@ - - - + + + - + - - - - - - - - - + + + + + + + + - - - - - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml similarity index 91% rename from openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml rename to openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml index 476602970..e4119f1cb 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem1K_40nm.xml @@ -118,14 +118,14 @@ - + - + @@ -135,7 +135,7 @@ - + @@ -164,6 +164,7 @@ + @@ -176,19 +177,30 @@ clb.cout clb.O[19:10] clb.I[39:20] - + - - - + + + - + - - + + + + + memory.clk memory.waddr[0:0] memory.raddr[0:0] memory.data_in[0:0] memory.data_out[0:0] + memory.waddr[1:1] memory.raddr[1:1] memory.data_in[1:1] memory.data_out[1:1] + memory.waddr[2:2] memory.raddr[2:2] memory.data_in[2:2] memory.data_out[2:2] + memory.waddr[3:3] memory.raddr[3:3] memory.data_in[3:3] memory.data_out[3:3] + memory.waddr[4:4] memory.raddr[4:4] memory.data_in[4:4] memory.data_out[4:4] + memory.waddr[5:5] memory.raddr[5:5] memory.data_in[5:5] memory.data_out[5:5] + memory.wen memory.waddr[6:6] memory.raddr[6:6] memory.data_in[6:6] memory.data_out[6:6] + memory.ren memory.data_in[7:7] memory.data_out[7:7] + @@ -204,7 +216,7 @@ - + @@ -682,57 +694,57 @@ - - - + + + - + - - - - - - - - - + + + + + + + + - - - - - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml index baada7911..b6dad0a8f 100755 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml @@ -193,7 +193,16 @@ - + + + + + + + + + +