[script] correct paths related to yosys in docker image and ci

.github/workflows/build.yml

@@ -151,8 +151,8 @@ jobs:
             build/openfpga/libopenfpga.a
             build/openfpga/openfpga_shell.so
             build/openfpga/openfpga
-            yosys/install/share
-            yosys/install/bin
+            build/yosys/share
+            build/yosys/bin
             openfpga_flow
             openfpga.sh
 
@@ -446,11 +446,11 @@ jobs:
           chmod +x build/vtr-verilog-to-routing/ace2/ace
           chmod +x build/vtr-verilog-to-routing/vpr/vpr
           chmod +x build/openfpga/openfpga
-          chmod +x yosys/install/bin/yosys
-          chmod +x yosys/install/bin/yosys-abc
-          chmod +x yosys/install/bin/yosys-config
-          chmod +x yosys/install/bin/yosys-filterlib
-          chmod +x yosys/install/bin/yosys-smtbmc
+          chmod +x build/yosys/bin/yosys
+          chmod +x build/yosys/bin/yosys-abc
+          chmod +x build/yosys/bin/yosys-config
+          chmod +x build/yosys/bin/yosys-filterlib
+          chmod +x build/yosys/bin/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04)
         shell: bash
         run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs

docker/Dockerfile.master

@@ -3,8 +3,8 @@ RUN mkdir -p /opt/openfpga
 WORKDIR /opt/openfpga
 COPY . /opt/openfpga
 RUN chmod +x build/vtr-verilog-to-routing/abc/abc build/vtr-verilog-to-routing/ace2/ace build/openfpga/openfpga build/vtr-verilog-to-routing/vpr/vpr
-RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc
-ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/yosys/install/bin:${PATH}"
+RUN chmod +x build/yosys/bin/yosys build/yosys/bin/yosys-abc build/yosys/bin/yosys-config build/yosys/bin/yosys-filterlib build/yosys/bin/yosys-smtbmc
+ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/build/yosys/bin:${PATH}"
 ENV PATH="/opt/openfpga/build/vtr-verilog-to-routing/ace2:/opt/openfpga/build/vtr-verilog-to-routing/abc:/opt/openfpga/build/vtr-verilog-to-routing/vpr:${PATH}"
 ENV OPENFPGA_PATH="/opt/openfpga"