By default yosys works with ys script. For QuickLogic devices, it takes yosys tcl scripts

openfpga_flow/misc/qlf_yosys.tcl

@@ -1,7 +1,7 @@
 # Yosys synthesis script for ${TOP_MODULE}
 yosys -import
 
-if { [info procs ql-qlf] != {} } { plugin -i ql-qlf }
+if { [info procs ql-qlf] == {} } { plugin -i ql-qlf }
 yosys -import  ;# ingest plugin commands
 
 # Read verilog files

openfpga_flow/misc/ys_tmpl_rewrite_flow.ys

@@ -0,0 +1,4 @@
+# Rewrite the .blif to Verilog
+# so that the pin sequence matches
+read_blif rewritten_${OUTPUT_BLIF}
+write_verilog ${OUTPUT_VERILOG}

openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys

@@ -0,0 +1,105 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+
+########################
+# Map multipliers
+# Inspired from synth_xilinx.cc
+#########################
+# Avoid merging any registers into DSP, reserve memory port registers first
+memory_dff
+wreduce t:$mul
+techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
+select a:mul2dsp
+setattr -unset mul2dsp
+opt_expr -fine
+wreduce
+select -clear
+chtype -set $mul t:$__soft_mul# Extract arithmetic functions
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
+alumacc
+share
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
+memory -nomap
+opt_clean
+
+#########################
+# Map logics to BRAMs
+#########################
+memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
+techmap -map ${YOSYS_BRAM_MAP_VERILOG}
+opt -fast -mux_undef -undriven -fine
+memory_map
+opt -undriven -fine
+
+#########################
+# Map flip-flops
+#########################
+techmap -map +/adff2dff.v
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}

openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys

@@ -0,0 +1,87 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+#########################
+# Run coarse synthesis
+#########################
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+# Extract arithmetic functions
+alumacc
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
+memory -nomap
+opt_clean
+
+#########################
+# Map logics to BRAMs
+#########################
+memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
+techmap -map ${YOSYS_BRAM_MAP_VERILOG}
+opt -fast -mux_undef -undriven -fine
+memory_map
+opt -undriven -fine
+
+#########################
+# Map flip-flops
+#########################
+techmap -map +/adff2dff.v
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}

openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys

@@ -0,0 +1,96 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+
+########################
+# Map multipliers
+# Inspired from synth_xilinx.cc
+#########################
+# Avoid merging any registers into DSP, reserve memory port registers first
+memory_dff
+wreduce t:$mul
+techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
+select a:mul2dsp
+setattr -unset mul2dsp
+opt_expr -fine
+wreduce
+select -clear
+chtype -set $mul t:$__soft_mul# Extract arithmetic functions
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
+alumacc
+share
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
+memory -nomap
+opt_clean
+
+#########################
+# Map flip-flops
+#########################
+techmap -map +/adff2dff.v
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys

@@ -0,0 +1,22 @@
+# Yosys synthesis script for ${TOP_MODULE}
+# Read verilog files
+${READ_VERILOG_FILE}
+
+# Technology mapping
+hierarchy -top ${TOP_MODULE}
+proc
+techmap -D NO_LUT -map +/adff2dff.v
+
+# Synthesis
+synth -top ${TOP_MODULE} -flatten
+clean
+
+# LUT mapping
+abc -lut ${LUT_SIZE}
+
+# Check
+synth -run check
+
+# Clean and output blif
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}

openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys

@@ -0,0 +1,22 @@
+# Yosys synthesis script for ${TOP_MODULE}
+# Read verilog files
+${READ_VERILOG_FILE}
+
+# Technology mapping
+hierarchy -top ${TOP_MODULE}
+proc
+techmap -D NO_LUT -map +/adff2dff.v
+
+# Synthesis
+synth -top ${TOP_MODULE} -flatten
+clean
+
+# LUT mapping
+abc -lut ${LUT_SIZE}
+
+# Check
+synth -run check
+
+# Clean and output blif
+opt_clean -purge
+write_blif rewritten_${OUTPUT_BLIF}

openfpga_flow/scripts/run_fpga_flow.py

@@ -496,15 +496,22 @@ def run_yosys_with_abc():
         tmpVar = OpenFPGAArgs[indx][2:].upper()
         ys_params[tmpVar] = OpenFPGAArgs[indx+1]
     
+    def_tmpl_yosys_file = "ys_tmpl_yosys_vpr_flow.ys"
+    yosys_file="yosys.ys"
+    file_extension = os.path.splitext(args.yosys_tmpl)[1]
+    if file_extension is not None:
+        def_tmpl_yosys_file = "ys_tmpl_yosys_vpr_flow"+file_extension
+        yosys_file="yosys"+file_extension
+
     yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
-        cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.tcl")
+        cad_tools["misc_dir"], def_tmpl_yosys_file)
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
-    with open("yosys.tcl", 'w') as archfile:
+    with open(yosys_file, 'w') as archfile:
         archfile.write(tmpl.safe_substitute(ys_params))
     
     yosys_path = get_yosys_path()
     run_command("Run yosys", "yosys_output.log",
-                [yosys_path, 'yosys.tcl'])
+                [yosys_path, yosys_file])
 
 
 def get_yosys_path():
@@ -736,10 +743,10 @@ def run_rewrite_verilog():
         for iteration_idx, curr_rewrite_tmpl in enumerate(args.ys_rewrite_tmpl.split(";")):
             tmpl = Template(open(curr_rewrite_tmpl, encoding='utf-8').read())
             logger.info("Yosys rewrite iteration: " + str(iteration_idx))
-            with open("yosys_rewrite_" + str(iteration_idx) + ".tcl", 'w') as archfile:
+            with open("yosys_rewrite_" + str(iteration_idx) + ".ys", 'w') as archfile:
                 archfile.write(tmpl.safe_substitute(ys_rewrite_params))
             run_command("Run yosys", "yosys_rewrite_output.log",
-                    [yosys_path, "yosys_rewrite_" + str(iteration_idx) + ".tcl"])
+                    [yosys_path, "yosys_rewrite_" + str(iteration_idx) + ".ys"])
 
 
 

openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf

@@ -32,7 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_cha
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.tcl
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
 bench0_top = and2
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf

@@ -65,7 +65,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovisio
 #bench21=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.tcl
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
 # Benchmark ch_intrinsics
 bench0_top = bgm
 bench1_top = RLE_BlobMerging

openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf

@@ -33,8 +33,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_sof
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac_8/mac_8.v
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.tcl
-bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench0_top = mac_8
 

openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf

@@ -31,7 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.tcl
-bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.tcl;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.tcl
 
 bench1_top = adder_8