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remove configuration bus naming dependency on SRAM circuit models

This commit is contained in:
tangxifan 2019-10-11 19:47:36 -06:00
parent 73a5977e0d
commit b3ca0d32a4
6 changed files with 24 additions and 39 deletions
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22
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -459,11 +459,9 @@ std::string generate_local_config_bus_port_name() {
* port list of a module
* The port name is named after the cell name of SRAM in circuit library
*********************************************************************/
std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_sram_orgz& sram_orgz_type,
std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type,
const e_spice_model_port_type& port_type) {
std::string port_name = circuit_lib.model_name(sram_model) + std::string("_");
std::string port_name;
switch (sram_orgz_type) {
case SPICE_SRAM_STANDALONE: {
@ -472,10 +470,10 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
* (2) Inverted output of a SRAM, enabled by port type of OUTPUT
*/
if (SPICE_MODEL_PORT_INPUT == port_type) {
port_name += std::string("out");
port_name = std::string("mem_out");
} else {
VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type );
port_name += std::string("outb");
port_name = std::string("mem_outb");
}
break;
}
@ -488,10 +486,10 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
* +------+ +------+ +------+
*/
if (SPICE_MODEL_PORT_INPUT == port_type) {
port_name += std::string("ccff_head");
port_name = std::string("ccff_head");
} else {
VTR_ASSERT( SPICE_MODEL_PORT_OUTPUT == port_type );
port_name += std::string("ccff_tail");
port_name = std::string("ccff_tail");
}
break;
case SPICE_SRAM_MEMORY_BANK:
@ -510,14 +508,14 @@ std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
* +----------+ +----------+ +----------+
*/
if (SPICE_MODEL_PORT_BL == port_type) {
port_name += std::string("bl");
port_name = std::string("bl");
} else if (SPICE_MODEL_PORT_WL == port_type) {
port_name += std::string("wl");
port_name = std::string("wl");
} else if (SPICE_MODEL_PORT_BLB == port_type) {
port_name += std::string("blb");
port_name = std::string("blb");
} else {
VTR_ASSERT( SPICE_MODEL_PORT_WLB == port_type );
port_name += std::string("wlb");
port_name = std::string("wlb");
}
break;
default:

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
View File

@ -99,9 +99,7 @@ std::string generate_mux_local_decoder_data_inv_port_name();
std::string generate_local_config_bus_port_name();
std::string generate_sram_port_name(const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_sram_orgz& sram_orgz_type,
std::string generate_sram_port_name(const e_sram_orgz& sram_orgz_type,
const e_spice_model_port_type& port_type);
std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,

20
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
View File

@ -207,7 +207,7 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
/* Add ports to the module manager */
for (size_t iport = 0; iport < model_port_types.size(); ++iport) {
/* Create a port */
std::string port_name = generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, model_port_types[iport]);
std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]);
BasicPort module_port(port_name, sram_port_size);
/* Add generated ports to the ModuleManager */
module_manager.add_port(module_id, module_port, module_port_types[iport]);
@ -632,12 +632,9 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitModelId>& memory_models) {
const e_sram_orgz& sram_orgz_type) {
/* Ensure that the size of memory_model vector matches the memory_module vector */
VTR_ASSERT( (memory_modules.size() == memory_instances.size())
&& (memory_modules.size() == memory_models.size()) );
VTR_ASSERT(memory_modules.size() == memory_instances.size());
switch (sram_orgz_type) {
case SPICE_SRAM_STANDALONE:
@ -670,7 +667,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
if (0 == mem_index) {
/* Find the port name of configuration chain head */
std::string src_port_name = generate_sram_port_name(circuit_lib, memory_models[mem_index], sram_orgz_type, SPICE_MODEL_PORT_INPUT);
std::string src_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT);
net_src_module_id = parent_module;
net_src_instance_id = 0;
net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
@ -723,7 +720,7 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name);
/* Find the port name of next memory module */
std::string sink_port_name = generate_sram_port_name(circuit_lib, memory_models.back(), sram_orgz_type, SPICE_MODEL_PORT_OUTPUT);
std::string sink_port_name = generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT);
ModuleId net_sink_module_id = parent_module;
size_t net_sink_instance_id = 0;
ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name);
@ -817,15 +814,12 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitModelId>& memory_models) {
const e_spice_model_design_tech& mem_tech) {
switch (mem_tech) {
case SPICE_MODEL_DESIGN_CMOS:
add_module_nets_cmos_memory_config_bus(module_manager, parent_module,
memory_modules, memory_instances,
sram_orgz_type,
circuit_lib, memory_models);
sram_orgz_type);
break;
case SPICE_MODEL_DESIGN_RRAM:
/* TODO: */

4
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h
View File

@ -70,8 +70,6 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
const std::vector<ModuleId>& memory_modules,
const std::vector<size_t>& memory_instances,
const e_sram_orgz& sram_orgz_type,
const e_spice_model_design_tech& mem_tech,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitModelId>& memory_models);
const e_spice_model_design_tech& mem_tech);
#endif

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
View File

@ -161,7 +161,6 @@ void print_verilog_primitive_block(std::fstream& fp,
*/
std::vector<ModuleId> memory_modules;
std::vector<size_t> memory_instances;
std::vector<CircuitModelId> memory_models;
/* If there is no memory module required, we can skip the assocated net addition */
if (ModuleId::INVALID() != memory_module) {
@ -177,7 +176,6 @@ void print_verilog_primitive_block(std::fstream& fp,
/* Record memory-related information */
memory_modules.push_back(memory_module);
memory_instances.push_back(memory_instance_id);
memory_models.push_back(sram_model);
}
/* Add all the nets to connect configuration ports from memory module to primitive modules
* This is a one-shot addition that covers all the memory modules in this primitive module!
@ -185,8 +183,7 @@ void print_verilog_primitive_block(std::fstream& fp,
if (false == memory_modules.empty()) {
add_module_nets_memory_config_bus(module_manager, primitive_module,
memory_modules, memory_instances,
cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model),
circuit_lib, memory_models);
cur_sram_orgz_info->type, circuit_lib.design_tech_type(sram_model));
}
/* Write the verilog module */

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -814,12 +814,12 @@ void print_verilog_local_sram_wires(std::fstream& fp,
fp << generate_verilog_port(VERILOG_PORT_WIRE, ccff_config_bus_port) << ";" << std::endl;
/* Connect first CCFF to the head */
/* Head is always a 1-bit port */
BasicPort ccff_head_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1);
BasicPort ccff_head_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_INPUT), 1);
BasicPort ccff_head_local_port(ccff_config_bus_port.get_name(), 1);
print_verilog_wire_connection(fp, ccff_head_local_port, ccff_head_port, false);
/* Connect last CCFF to the tail */
/* Tail is always a 1-bit port */
BasicPort ccff_tail_port(generate_sram_port_name(circuit_lib, sram_model, sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1);
BasicPort ccff_tail_port(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_OUTPUT), 1);
BasicPort ccff_tail_local_port(ccff_config_bus_port.get_name(), ccff_config_bus_port.get_msb(), ccff_config_bus_port.get_msb());
print_verilog_wire_connection(fp, ccff_tail_local_port, ccff_tail_port, false);
break;
@ -1027,11 +1027,11 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp,
print_verilog_wire_connection(fp, wl_bus_reserved_bits, reserved_wl_bus, false);
/* Connect SRAM BL/WLs to bus */
BasicPort mux_bl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_BL),
BasicPort mux_bl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_BL),
num_conf_bits);
BasicPort bl_bus_regular_bits(bl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1);
print_verilog_wire_connection(fp, bl_bus_regular_bits, mux_bl_wire, false);
BasicPort mux_wl_wire(generate_sram_port_name(circuit_lib, sram_models[0], sram_orgz_type, SPICE_MODEL_PORT_WL),
BasicPort mux_wl_wire(generate_sram_port_name(sram_orgz_type, SPICE_MODEL_PORT_WL),
num_conf_bits);
BasicPort wl_bus_regular_bits(wl_bus.get_name(), num_reserved_conf_bits, num_reserved_conf_bits + num_conf_bits - 1);
print_verilog_wire_connection(fp, wl_bus_regular_bits, mux_wl_wire, false);