diff --git a/VERSION.md b/VERSION.md index bc34ed21b..1d1bc90a3 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2528 +1.2.2557 diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 3552cdc33..737b78a08 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -54,7 +54,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, chanx_bb.set_xmin(0); chanx_bb.set_xmax(grids.width()); chanx_bb.set_ymin(0); - chanx_bb.set_ymax(grids.height()); + chanx_bb.set_ymax(grids.height() - 1); } /* Check the number of CHANX nodes required */ for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { @@ -74,7 +74,7 @@ static size_t estimate_clock_rr_graph_num_nodes(const DeviceGrid& grids, vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); if (perimeter_cb) { chany_bb.set_xmin(0); - chany_bb.set_xmax(grids.width()); + chany_bb.set_xmax(grids.width() - 1); chany_bb.set_ymin(0); chany_bb.set_ymax(grids.height()); } @@ -179,7 +179,7 @@ static void add_rr_graph_clock_nodes( chanx_bb.set_xmin(0); chanx_bb.set_xmax(grids.width()); chanx_bb.set_ymin(0); - chanx_bb.set_ymax(grids.height()); + chanx_bb.set_ymax(grids.height() - 1); } /* Add X-direction clock nodes */ for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { @@ -201,7 +201,7 @@ static void add_rr_graph_clock_nodes( vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); if (perimeter_cb) { chany_bb.set_xmin(0); - chany_bb.set_xmax(grids.width()); + chany_bb.set_xmax(grids.width() - 1); chany_bb.set_ymin(0); chany_bb.set_ymax(grids.height()); } @@ -418,6 +418,8 @@ static void try_find_and_add_clock_track2ipin_node( const ClockTreePinId& clk_pin, const bool& verbose) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer)); + VTR_LOGV(verbose, "Getting type of grid at (x=%d, y=%d)\n", grid_coord.x(), + grid_coord.y()); for (std::string tap_pin_name : clk_ntwk.tree_flatten_tap_to_ports(clk_tree, clk_pin, grid_coord)) { VTR_LOGV(verbose, "Checking tap pin name: %s\n", tap_pin_name.c_str()); @@ -762,7 +764,7 @@ static void add_rr_graph_clock_edges( chanx_bb.set_xmin(0); chanx_bb.set_xmax(grids.width()); chanx_bb.set_ymin(0); - chanx_bb.set_ymax(grids.height()); + chanx_bb.set_ymax(grids.height() - 1); } /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = chanx_bb.ymin(); iy < chanx_bb.ymax(); ++iy) { @@ -784,7 +786,7 @@ static void add_rr_graph_clock_edges( vtr::Rect chany_bb(0, 1, grids.width() - 1, grids.height() - 1); if (perimeter_cb) { chany_bb.set_xmin(0); - chany_bb.set_xmax(grids.width()); + chany_bb.set_xmax(grids.width() - 1); chany_bb.set_ymin(0); chany_bb.set_ymax(grids.height()); } diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 963d53bc1..78ce8e16b 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -45,19 +45,8 @@ const RRGSB& DeviceRRGSB::get_gsb(const size_t& x, const size_t& y) const { /* Get a rr switch block in the array with a coordinate */ const RRGSB& DeviceRRGSB::get_gsb_by_cb_coordinate( - const t_rr_type& cb_type, const vtr::Point& coordinate) const { + const vtr::Point& coordinate) const { vtr::Point gsb_coord = coordinate; - /* TODO move the coordinate conversion to RRGSB */ - switch (cb_type) { - case CHANX: - break; - case CHANY: - gsb_coord.set_y(gsb_coord.y() - 1); - break; - default: - VTR_LOG("Invalid type of connection block!\n"); - exit(1); - } VTR_ASSERT(validate_coordinate(gsb_coord)); return rr_gsb_[gsb_coord.x()][gsb_coord.y()]; diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 245b1646b..b278985c6 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -40,7 +40,7 @@ class DeviceRRGSB { const; /* Get a rr switch block in the array with a coordinate */ /* Get a gsb using its connection block coordinate */ const RRGSB& get_gsb_by_cb_coordinate( - const t_rr_type& cb_type, const vtr::Point& coordinate) const; + const vtr::Point& coordinate) const; size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ size_t get_num_sb_unique_module() diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 05f1f9b51..9e1f9b225 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1157,8 +1157,9 @@ static void organize_top_module_tile_based_memory_modules( ********************************************************************/ static ModulePinInfo find_tile_module_chan_port( const ModuleManager& module_manager, const ModuleId& tile_module, - const vtr::Point& cb_coord_in_tile, const RRGraphView& rr_graph, - const RRGSB& rr_gsb, const t_rr_type& cb_type, const RRNodeId& chan_rr_node) { + const vtr::Point& cb_coord_in_tile, const size_t& cb_idx_in_tile, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, + const RRNodeId& chan_rr_node, const bool& name_module_using_index) { ModulePinInfo input_port_info; /* Generate the input port object */ switch (rr_graph.node_type(chan_rr_node)) { @@ -1170,9 +1171,15 @@ static ModulePinInfo find_tile_module_chan_port( /* Create a port description for the middle output */ std::string input_port_name = generate_cb_module_track_port_name( cb_type, IN_PORT, 0 == chan_node_track_id % 2); + std::string cb_instance_name_in_tile = + generate_connection_block_module_name(cb_type, cb_coord_in_tile); + if (name_module_using_index) { + cb_instance_name_in_tile = + generate_connection_block_module_name_using_index(cb_type, + cb_idx_in_tile); + } std::string tile_input_port_name = generate_tile_module_port_name( - generate_connection_block_module_name(cb_type, cb_coord_in_tile), - input_port_name); + cb_instance_name_in_tile, input_port_name); /* Must find a valid port id in the Switch Block module */ input_port_info.first = module_manager.find_module_port(tile_module, tile_input_port_name); @@ -1199,7 +1206,8 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const std::string& clk_tree_name, - const RRClockSpatialLookup& rr_clock_lookup) { + const RRClockSpatialLookup& rr_clock_lookup, + const bool& name_module_using_index) { int status = CMD_EXEC_SUCCESS; /* Ensure the clock arch tree name is valid */ @@ -1216,11 +1224,11 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( if (clk_ntwk.tree_width(clk_tree) != module_manager.module_port(top_module, top_module_port).get_width()) { VTR_LOG( - "Clock tree '%s' does not have the same width '%lu' as the port '%'s of " + "Clock tree '%s' does not have the same width '%lu' as the port '%s' of " "FPGA top module", clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), module_manager.module_port(top_module, top_module_port) - .get_name() + .to_verilog_string() .c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -1245,7 +1253,7 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( /* Get the tile module and instance at the entry point */ const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( - entry_track_type, vtr::Point(entry_point.x(), entry_point.y())); + vtr::Point(entry_point.x(), entry_point.y())); vtr::Point cb_coord_in_tile = rr_gsb.get_sb_coordinate(); FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_cb_coordinate( entry_track_type, cb_coord_in_tile); @@ -1268,8 +1276,9 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( fabric_tile.cb_coordinates( unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile]; ModulePinInfo des_pin_info = find_tile_module_chan_port( - module_manager, tile_module, cb_coord_in_unique_fabric_tile, rr_graph, - rr_gsb, entry_track_type, entry_rr_node); + module_manager, tile_module, cb_coord_in_unique_fabric_tile, + cb_idx_in_curr_fabric_tile, rr_graph, rr_gsb, entry_track_type, + entry_rr_node, name_module_using_index); /* Configure the net sink */ BasicPort sink_port = @@ -1601,7 +1610,7 @@ static int add_top_module_global_ports_from_tile_modules( const DeviceRRGSB& device_rr_gsb, const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, - const bool& perimeter_cb) { + const bool& perimeter_cb, const bool& name_module_using_index) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1618,12 +1627,20 @@ static int add_top_module_global_ports_from_tile_modules( BasicPort global_port_to_add; global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); - size_t max_port_size = 0; - for (const BasicPort& tile_port : - tile_annotation.global_port_tile_ports(tile_global_port)) { - max_port_size = std::max(tile_port.get_width(), max_port_size); + if (tile_annotation.global_port_thru_dedicated_network( + tile_global_port)) { + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); + global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); + } else { + size_t max_port_size = 0; + for (const BasicPort& tile_port : + tile_annotation.global_port_tile_ports(tile_global_port)) { + max_port_size = std::max(tile_port.get_width(), max_port_size); + } + global_port_to_add.set_width(max_port_size); } - global_port_to_add.set_width(max_port_size); global_ports_to_add.push_back(global_port_to_add); } } @@ -1653,7 +1670,7 @@ static int add_top_module_global_ports_from_tile_modules( module_manager, top_module, top_module_port, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, tile_annotation.global_port_clock_arch_tree_name(tile_global_port), - rr_clock_lookup); + rr_clock_lookup, name_module_using_index); } else { status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, @@ -1943,7 +1960,7 @@ int build_top_module_tile_child_instances( status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, tile_annotation, vpr_device_annotation, grids, layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, - rr_clock_lookup, perimeter_cb); + rr_clock_lookup, perimeter_cb, name_module_using_index); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 508516a8d..16b0823df 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1287,12 +1287,15 @@ static int build_top_module_global_net_from_clock_arch_tree( clk_ntwk.spine_level(spine), pin, entry_dir); /* Get the connection block module and instance at the entry point */ - const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( - entry_track_type, vtr::Point(entry_point.x(), entry_point.y())); - ModuleId cb_module = - module_manager.find_module(generate_connection_block_module_name( - entry_track_type, - vtr::Point(entry_point.x(), entry_point.y()))); + vtr::Point entry_cb_coord(entry_point.x(), entry_point.y()); + const RRGSB& rr_gsb = + device_rr_gsb.get_gsb_by_cb_coordinate(entry_cb_coord); + vtr::Point entry_unique_cb_coord = + device_rr_gsb.get_cb_unique_module(entry_track_type, entry_cb_coord) + .get_cb_coordinate(entry_track_type); + std::string cb_module_name = generate_connection_block_module_name( + entry_track_type, entry_unique_cb_coord); + ModuleId cb_module = module_manager.find_module(cb_module_name); size_t cb_instance = cb_instance_ids.at(entry_track_type)[entry_point.x()][entry_point.y()]; ModulePinInfo des_pin_info = find_connection_block_module_chan_port( diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga index e7a07d61d..0ea39c4ea 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga @@ -73,7 +73,7 @@ write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REF write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis +#write_analysis_sdc --file ./SDC_analysis # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 85e0d9bfd..813e9f181 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -220,6 +220,7 @@ run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_glob echo -e "Module naming"; run-task basic_tests/module_naming/using_index $@ +run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ run-task basic_tests/module_naming/renaming_rules $@ run-task basic_tests/module_naming/renaming_rules_strong $@ run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ @@ -234,12 +235,14 @@ run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${ run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ echo -e "Testing programmable clock architecture"; +run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ run-task basic_tests/clock_network/homo_1clock_2layer $@ run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ run-task basic_tests/clock_network/homo_2clock_2layer $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..60f1bfb36 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf new file mode 100644 index 000000000..554a53d64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_1layer_2entry/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..cfdb727a1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml new file mode 100644 index 000000000..3788a1411 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_reset.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml new file mode 100644 index 000000000..1311926f5 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/pin_constraints_resetb.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf new file mode 100644 index 000000000..9237ad156 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_verilog_testbench_port_mapping= + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml +bench1_openfpga_verilog_testbench_port_mapping= + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml new file mode 100644 index 000000000..2b85f88cd --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/clk_arch_1clk_2layer.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf new file mode 100644 index 000000000..245ac9b9f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=2x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml --name_module_using_index +openfpga_verilog_testbench_options=--explicit_port_mapping +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2_pipelined + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml new file mode 100644 index 000000000..0d07fa612 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_TileOrgzTr_fracff_40nm.xml @@ -0,0 +1,642 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + clb.O[0:3] clb.I[0:5] + clb.reset clb.clk clb.O[4:7] clb.I[6:11] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index ddc3ac408..9eef18c4f 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit ddc3ac408aa123dc8d4da1685c6dec7e65038646 +Subproject commit 9eef18c4facb5dad0604682e6e5d3d904b97f6d8 diff --git a/yosys b/yosys index 960bca019..c78848467 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 960bca019639402df3211ad0687b01522a01ba22 +Subproject commit c788484679a5d551bf554f8789f86d05338cb0bc