diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 5ddc5af76..c593994d8 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -61,7 +61,6 @@ run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread
 run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs
 run-task basic_tests/full_testbench/ql_memory_bank_shift_register --debug --show_thread_logs
 run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr --debug --show_thread_logs
-run-task basic_tests/full_testbench/multi_region_ql_memory_bank_shift_register --debug --show_thread_logs
 
 echo -e "Testing testbenches without self checking features";
 run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
@@ -96,6 +95,7 @@ run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_
 run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
 run-task basic_tests/fabric_key/load_external_key_qlbank_fpga --debug --show_thread_logs
 run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga --debug --show_thread_logs
+run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga --debug --show_thread_logs
 
 echo -e "Testing K4 series FPGA";
 echo -e "Testing K4N4 with facturable LUTs";
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank_shift_register/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga/config/task.conf
similarity index 72%
rename from openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank_shift_register/config/task.conf
rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga/config/task.conf
index 4683a6e19..53330396b 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/multi_region_ql_memory_bank_shift_register/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga/config/task.conf
@@ -13,24 +13,27 @@ power_analysis = true
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
-fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbanksr_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
-openfpga_vpr_device_layout=--device 2x2
-openfpga_fast_configuration=
+external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbanksr_sample_key.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=