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hotfix on removing dangling inputs from GSB, which are CLB direct output

This commit is contained in:
tangxifan 2020-03-08 13:54:49 -06:00
parent 0fbf3fca41
commit b219b096ee
4 changed files with 34 additions and 5 deletions
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5
openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
View File

@ -499,6 +499,11 @@
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<directlist>
<direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<!--switch_segment_patterns>
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
<unbuf_mux name="1"/>

4
openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
View File

@ -499,6 +499,10 @@
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<directlist>
<direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
</directlist>
<!--switch_segment_patterns>
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
<unbuf_mux name="1"/>

8
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1032,10 +1032,18 @@ RRGSB build_rr_gsb(DeviceCoordinator& device_range,
/* Fill opin_rr_nodes */
/* Copy from temp_opin_rr_node to opin_rr_node */
for (int inode = 0; inode < temp_num_opin_rr_nodes[0]; ++inode) {
/* Skip Fc = 0 pins, they should NOT appear in the GSB connection */
if (0. == grid[temp_opin_rr_node[0][inode]->xlow][temp_opin_rr_node[0][inode]->ylow].type->Fc[temp_opin_rr_node[0][inode]->ptc_num]) {
continue;
}
/* Grid[x+1][y+1] Bottom side outputs pins */
rr_gsb.add_opin_node(temp_opin_rr_node[0][inode], side_manager.get_side(), opin_grid_side[0]);
}
for (int inode = 0; inode < temp_num_opin_rr_nodes[1]; ++inode) {
/* Skip Fc = 0 pins, they should NOT appear in the GSB connection */
if (0. == grid[temp_opin_rr_node[1][inode]->xlow][temp_opin_rr_node[1][inode]->ylow].type->Fc[temp_opin_rr_node[1][inode]->ptc_num]) {
continue;
}
/* Grid[x+1][y] TOP side outputs pins */
rr_gsb.add_opin_node(temp_opin_rr_node[1][inode], side_manager.get_side(), opin_grid_side[1]);
}

22
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_module_writer.cpp
View File

@ -20,9 +20,21 @@
*******************************************************************/
static
std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager,
const ModuleId& module,
const ModulePortId& module_port_id) {
return module_manager.module_port(module, module_port_id).get_name();
const ModuleId& parent,
const ModuleId& child,
const size_t& instance_id,
const ModulePortId& child_port_id) {
std::string wire_name;
if (!module_manager.instance_name(parent, child, instance_id).empty()) {
wire_name = module_manager.instance_name(parent, child, instance_id);
} else {
wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id);
wire_name += std::string("_");
}
wire_name += module_manager.module_port(child, child_port_id).get_name();
return wire_name;
}
/********************************************************************
@ -164,7 +176,7 @@ std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(co
}
/* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
BasicPort instance_port;
instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, module_id, child, instance, child_port_id));
/* We give the same port name as child module, this case happens to global ports */
instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
*std::max_element(undriven_pins.begin(), undriven_pins.end()));
@ -401,7 +413,7 @@ void write_verilog_instance_to_file(std::fstream& fp,
BasicPort instance_port;
if (ModuleNetId::INVALID() == net) {
/* We give the same port name as child module, this case happens to global ports */
instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
instance_port.set_width(child_pin, child_pin);
} else {
/* Find the name for this child port */