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[HDL] Bug fix in HDL netlist due to port name mismatching

This commit is contained in:
tangxifan 2021-02-01 11:35:25 -07:00
parent e4abe263c3
commit b215b868c1
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/openfpga_cell_library/verilog/mux2.v
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@ -63,13 +63,13 @@ endmodule
//----------------------------------------------------- //-----------------------------------------------------
module CARRY_MUX2( module CARRY_MUX2(
input [0:0] A, // Data input 0 input [0:0] A0, // Data input 0
input [0:0] B, // Data input 1 input [0:0] A1, // Data input 1
input [0:0] S0, // Select port input [0:0] S, // Select port
output [0:0] Y // Data output output [0:0] Y // Data output
); );
assign Y = S0 ? B : A; assign Y = S ? A1 : A0;
// Note: // Note:
// MUX2 appears in the datapath logic driven by carry-in and LUT outputs // MUX2 appears in the datapath logic driven by carry-in and LUT outputs