From b215b868c10c35b60b06ae6526a263631862304c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 1 Feb 2021 11:35:25 -0700 Subject: [PATCH] [HDL] Bug fix in HDL netlist due to port name mismatching --- openfpga_flow/openfpga_cell_library/verilog/mux2.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v index bfa527959..fed7858ba 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v +++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v @@ -63,13 +63,13 @@ endmodule //----------------------------------------------------- module CARRY_MUX2( - input [0:0] A, // Data input 0 - input [0:0] B, // Data input 1 - input [0:0] S0, // Select port + input [0:0] A0, // Data input 0 + input [0:0] A1, // Data input 1 + input [0:0] S, // Select port output [0:0] Y // Data output ); - assign Y = S0 ? B : A; + assign Y = S ? A1 : A0; // Note: // MUX2 appears in the datapath logic driven by carry-in and LUT outputs