From b185a17359e51f2ea60bd7ba231323f307d12a66 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 20 May 2019 22:33:17 -0600 Subject: [PATCH] add routing_channel unique module generation --- .../SRC/fpga_spice_include/spice_types.h | 4 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c | 3 +- .../vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h | 9 + .../fpga_x2p/base/fpga_x2p_identify_routing.c | 94 ++++++++++ .../fpga_x2p/base/fpga_x2p_identify_routing.h | 4 + .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 4 + vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp | 55 ++++-- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h | 7 +- .../verilog/verilog_compact_netlist.c | 161 ++++++++++++++++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 171 ++++++++++++++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 24 ++- vpr7_x2p/vpr/SRC/tags | 49 ++++- 12 files changed, 545 insertions(+), 40 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index b9b88683a..e99869c93 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -1,3 +1,5 @@ +#ifndef SPICE_TYPES_H +#define SPICE_TYPES_H #include "util.h" #include "linkedlist.h" @@ -574,3 +576,5 @@ struct s_sram_orgz_info { }; /* SPICE support end*/ + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c index 25049237d..b078609c0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.c @@ -45,5 +45,4 @@ char* fpga_spice_bitstream_logic_block_log_file_postfix = "_lb_bitstream.log"; char* fpga_spice_bitstream_routing_log_file_postfix = "_routing_bitstream.log"; char* default_sdc_folder = "SDC/"; - - +DeviceRRChan device_rr_chan; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h index 8e8a4ef1d..12270b785 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_globals.h @@ -1,3 +1,8 @@ +#ifndef FPGA_X2P_GLOBALS_H +#define FPGA_X2P_GLOBALS_H + +#include "rr_chan.h" + /* global parameters for FPGA-SPICE tool suites */ extern t_spice_model* fpga_spice_sram_model; @@ -34,3 +39,7 @@ extern char* renaming_report_postfix; extern char* fpga_spice_bitstream_output_file_postfix; extern char* fpga_spice_bitstream_logic_block_log_file_postfix; extern char* fpga_spice_bitstream_routing_log_file_postfix; + +extern DeviceRRChan device_rr_chan; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c index 17d2986af..12764dd61 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.c @@ -27,6 +27,7 @@ /* Include spice support headers*/ #include "read_xml_spice_util.h" #include "linkedlist.h" +#include "rr_chan.h" #include "fpga_x2p_types.h" #include "fpga_x2p_globals.h" #include "fpga_x2p_utils.h" @@ -72,6 +73,12 @@ void print_mirror_switch_block_stats(); void print_mirror_connection_block_stats(); +RRChan build_one_rr_chan(t_rr_type chan_type, size_t chan_x, size_t chan_y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data); + +void print_device_rr_chan_stats(DeviceRRChan& device_rr_chan); /***** subroutines *****/ void assign_switch_block_mirror(t_sb* src, t_sb* des) { @@ -702,6 +709,93 @@ void identify_mirror_connection_blocks() { return; } +/* Build a RRChan Object with the given channel type and coorindators */ +RRChan build_one_rr_chan(t_rr_type chan_type, size_t chan_x, size_t chan_y, + int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data) { + int chan_width = 0; + t_rr_node** chan_rr_nodes = NULL; + + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan; + /* Fill the information */ + rr_chan.set_type(chan_type); + + /* Collect rr_nodes for this channel */ + chan_rr_nodes = get_chan_rr_nodes(&chan_width, chan_type, chan_x, chan_y, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + + /* Reserve */ + /* rr_chan.reserve_node(size_t(chan_width)); */ + + /* Fill the rr_chan */ + for (size_t itrack = 0; itrack < size_t(chan_width); ++itrack) { + int cost_index = chan_rr_nodes[itrack]->cost_index; + int iseg = LL_rr_indexed_data[cost_index].seg_index; + /* Check */ + assert((!(iseg < 0))&&(iseg < num_segments)); + + rr_chan.add_node(chan_rr_nodes[itrack], size_t(iseg)); + } + + /* Free rr_nodes */ + my_free(chan_rr_nodes); + + return rr_chan; +} + +void print_device_rr_chan_stats(DeviceRRChan& device_rr_chan) { + /* Print stats */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d independent routing channel from %d X-direction routing channels.\n", + device_rr_chan.get_num_modules(CHANX), (nx + 0) * (ny + 1) ); + + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d independent routing channel from %d Y-direction routing channels.\n", + device_rr_chan.get_num_modules(CHANY), (nx + 1) * (ny + 0) ); + +} + +/* Build the list of unique routing channels */ +DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data) { + /* Create an object of DeviceRRChan */ + DeviceRRChan device_rr_chan; + + /* Initialize array of rr_chan inside the device */ + device_rr_chan.init_module_ids(nx + 1, ny + 1); + + /* For X-direction routing channel */ + for (size_t iy = 0; iy < (ny + 1); iy++) { + for (size_t ix = 1; ix < (nx + 1); ix++) { + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan = build_one_rr_chan(CHANX, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + num_segments, LL_rr_indexed_data); + /* check and add this rr_chan to the mirror list */ + device_rr_chan.add_one_chan_module(CHANX, ix, iy, rr_chan); + } + } + + /* For X-direction routing channel */ + for (size_t ix = 0; ix < (nx + 1); ix++) { + for (size_t iy = 1; iy < (ny + 1); iy++) { + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan = build_one_rr_chan(CHANY, ix, iy, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, + num_segments, LL_rr_indexed_data); + /* check and add this rr_chan to the mirror list */ + device_rr_chan.add_one_chan_module(CHANY, ix, iy, rr_chan); + } + } + + print_device_rr_chan_stats(device_rr_chan); + + return device_rr_chan; +} + /* Rotatable will be done in the next step void identify_rotatable_switch_blocks(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h index bb3649850..bb50cd25e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_identify_routing.h @@ -5,6 +5,10 @@ void identify_mirror_switch_blocks(); void identify_mirror_connection_blocks(); +DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, + t_ivec*** LL_rr_node_indices, int num_segments, + t_rr_indexed_data* LL_rr_indexed_data); + /* Rotatable will be done in the next step identify_rotatable_switch_blocks(); identify_rotatable_connection_blocks(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index e1f2d39d8..5373e8f79 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -1397,6 +1397,10 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, /* Idenify mirror and rotatable Switch blocks and Connection blocks */ identify_mirror_switch_blocks(); identify_mirror_connection_blocks(); + + /* Assign Gobal variable: build the Routing Resource Channels */ + device_rr_chan = build_device_rr_chan(num_rr_nodes, rr_node, rr_node_indices, Arch->num_segments, rr_indexed_data); + /* Rotatable will be done in the next step identify_rotatable_switch_blocks(); identify_rotatable_connection_blocks(); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp index dee691da1..f88428237 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.cpp @@ -92,10 +92,16 @@ void RRChan::set_type(t_rr_type type) { return; } +/* Reserve node list */ +void RRChan::reserve_node(size_t node_size) { + nodes_.reserve(node_size); /* reserve to the maximum */ + node_segments_.reserve(node_size); /* reserve to the maximum */ +} + /* add a node to the array */ void RRChan::add_node(t_rr_node* node, size_t node_segment) { /* resize the array if needed, node is placed in the sequence of node->ptc_num */ - if (size_t(node->ptc_num) > (nodes_.size() + 1)) { + if (node->ptc_num + 1 > nodes_.size()) { nodes_.resize(node->ptc_num + 1); /* resize to the maximum */ node_segments_.resize(node->ptc_num + 1); /* resize to the maximum */ } @@ -118,7 +124,7 @@ void RRChan::clear() { /* for type, only valid type is CHANX and CHANY */ bool RRChan::valid_type(t_rr_type type) const { - if ((CHANX == type) && (CHANY == type)) { + if ((CHANX == type) || (CHANY == type)) { return true; } return false; @@ -126,7 +132,7 @@ bool RRChan::valid_type(t_rr_type type) const { /* check if the node id is valid */ bool RRChan::valid_node_id(size_t node_id) const { - if ( (size_t(-1) < node_id) && (node_id < nodes_.size()) ) { + if (node_id < nodes_.size()) { return true; } @@ -145,6 +151,33 @@ RRChan DeviceRRChan::get_module(t_rr_type chan_type, size_t module_id) const { } } +RRChan DeviceRRChan::get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const { + assert(valid_coordinator(chan_type, x, y)); + assert(valid_module_id(chan_type, get_module_id(chan_type, x, y))); + return get_module(chan_type, get_module_id(chan_type, x, y)); +} + +/* Get the number of RRChan modules in either X-channel or Y-channel */ +size_t DeviceRRChan::get_num_modules(t_rr_type chan_type) const { + assert(valid_chan_type(chan_type)); + + if (CHANX == chan_type) { + return chanx_modules_.size(); + } else if (CHANY == chan_type) { + return chany_modules_.size(); + } +} + +size_t DeviceRRChan::get_module_id(t_rr_type chan_type, size_t x, size_t y) const { + assert(valid_coordinator(chan_type, x, y)); + + if (CHANX == chan_type) { + return chanx_module_ids_[x][y]; + } else if (CHANY == chan_type) { + return chany_module_ids_[x][y]; + } +} + void DeviceRRChan::init_module_ids(size_t device_width, size_t device_height) { init_chan_module_ids(CHANX, device_width, device_height); init_chan_module_ids(CHANY, device_width, device_height); @@ -169,7 +202,7 @@ void DeviceRRChan::init_chan_module_ids(t_rr_type chan_type, size_t device_width return; } -void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan rr_chan) { +void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan) { assert(valid_coordinator(chan_type, x, y)); if (CHANX == chan_type) { @@ -222,7 +255,7 @@ void DeviceRRChan::clear_chan(t_rr_type chan_type) { /* for type, only valid type is CHANX and CHANY */ bool DeviceRRChan::valid_chan_type(t_rr_type chan_type) const { - if ((CHANX == chan_type) && (CHANY == chan_type)) { + if ((CHANX == chan_type) || (CHANY == chan_type)) { return true; } return false; @@ -233,17 +266,17 @@ bool DeviceRRChan::valid_coordinator(t_rr_type chan_type, size_t x, size_t y) co assert(valid_chan_type(chan_type)); if (CHANX == chan_type) { - if (!( (size_t(-1) < x) && (x < chanx_module_ids_.size()) )) { + if ( (0 > x) || (x > chanx_module_ids_.size() - 1 )) { return false; } - if (!( (size_t(-1) < y) && (y < chanx_module_ids_[x].size()) )) { + if ( (0 > y) || (y > chanx_module_ids_[x].size() - 1) ) { return false; } } else if (CHANY == chan_type) { - if (!( (size_t(-1) < x) && (x < chany_module_ids_.size()) )) { + if ( (0 > x) && (x > chany_module_ids_.size() - 1) ) { return false; } - if (!( (size_t(-1) < y) && (y < chany_module_ids_[x].size()) )) { + if ( (0 > y) && (y > chany_module_ids_[x].size() - 1) ) { return false; } } @@ -256,11 +289,11 @@ bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const assert(valid_chan_type(chan_type)); if (CHANX == chan_type) { - if ( (size_t(-1) < module_id) && (module_id < chanx_modules_.size()) ) { + if (module_id < chanx_modules_.size()) { return true; } } else if (CHANY == chan_type) { - if ( (size_t(-1) < module_id) && (module_id < chany_modules_.size()) ) { + if (module_id < chany_modules_.size()) { return true; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h index 7df3fd16c..9b1c20f1e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_chan.h @@ -30,6 +30,7 @@ class RRChan { bool is_mirror(RRChan& cand) const; /* evaluate if two RR_chan is mirror to each other */ public: /* Mutators */ void set_type(t_rr_type type); /* modify type */ + void reserve_node(size_t node_size); /* reseve a number of nodes to the array */ void add_node(t_rr_node* node, size_t node_segment); /* add a node to the array */ void clear(); /* clear the content */ private: /* internal functions */ @@ -51,11 +52,15 @@ class RRChan { * and link each RR channel to */ class DeviceRRChan { + public: /* contructor */ public: /* Accessors */ RRChan get_module(t_rr_type chan_type, size_t module_id) const; + RRChan get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const; + size_t get_num_modules(t_rr_type chan_type) const; + size_t get_module_id(t_rr_type chan_type, size_t x, size_t y) const; public: /* Mutators */ void init_module_ids(size_t device_height, size_t device_width); - void add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan rr_chan); /* Add a new unique module of RRChan*/ + void add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan); /* Add a new unique module of RRChan*/ void clear(); private: /* internal functions */ void clear_chan(t_rr_type chan_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 00aaa61f2..08f4c7d7b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1043,6 +1043,161 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or return; } +/* Call defined channels. + * Ensure the port name here is co-herent to other sub-circuits(SB,CB,grid)!!! + */ +static +void dump_compact_verilog_defined_one_channel(FILE* fp, + int x, int y, + const RRChan& rr_chan, size_t subckt_id) { + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* check x*/ + assert((!(0 > x))&&(x < (nx + 1))); + /* check y*/ + assert((!(0 > y))&&(y < (ny + 1))); + + /* Comment lines */ + switch (rr_chan.get_type()) { + case CHANX: + fprintf(fp, "//----- BEGIN Call Channel-X [%d][%d] module -----\n", x, y); + break; + case CHANY: + fprintf(fp, "//----- BEGIN call Channel-Y [%d][%d] module -----\n\n", x, y); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel Type!\n", + __FILE__, __LINE__); + exit(1); + } + + /* Call the define sub-circuit */ + fprintf(fp, "%s ", + gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), subckt_id, -1)); + fprintf(fp, "%s ", + gen_verilog_one_routing_channel_instance_name(rr_chan.get_type(), x, y)); + fprintf(fp, "("); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + fprintf(fp, ",\n"); + } + + /* LEFT/BOTTOM side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the LEFT/BOTTOM port would be an output of a switch block + * When a track is in DEC_DIRECTION, the LEFT/BOTTOM port would be an input of a switch block + */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), + x, y, itrack, OUT_PORT)); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), + x, y, itrack, IN_PORT)); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + x, y, itrack); + exit(1); + } + } + /* RIGHT/TOP side port of CHANX/CHANY */ + /* We apply an opposite port naming rule than function: fprint_routing_chan_subckt + * In top-level netlists, we follow the same port name as switch blocks and connection blocks + * When a track is in INC_DIRECTION, the RIGHT/TOP port would be an input of a switch block + * When a track is in DEC_DIRECTION, the RIGHT/TOP port would be an output of a switch block + */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), + x, y, itrack, IN_PORT)); + fprintf(fp, "\n"); + break; + case DEC_DIRECTION: + fprintf(fp, "%s, ", + gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), + x, y, itrack, OUT_PORT)); + fprintf(fp, "\n"); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + x, y, itrack); + exit(1); + } + } + + /* output at middle point */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + fprintf(fp, "%s_%d__%d__midout_%u_ ", + convert_chan_type_to_string(rr_chan.get_type()), + x, y, itrack); + if (itrack < rr_chan.get_chan_width() - 1) { + fprintf(fp, ","); + } + fprintf(fp, "\n"); + } + fprintf(fp, ");\n"); + + /* Comment lines */ + fprintf(fp, + "//----- END Call Verilog Module of %s [%u] -----\n\n", + convert_chan_type_to_string(rr_chan.get_type()), + subckt_id); + + /* Free */ + + return; +} + + +/* Call the sub-circuits for channels : Channel X and Channel Y*/ +void dump_compact_verilog_defined_channels(FILE* fp) { + int ix, iy; + + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); + exit(1); + } + + /* Channel X */ + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + dump_compact_verilog_defined_one_channel(fp, ix, iy, + device_rr_chan.get_module_with_coordinator(CHANX, ix, iy), + device_rr_chan.get_module_id(CHANX, ix, iy)); + } + } + + /* Channel Y */ + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + dump_compact_verilog_defined_one_channel(fp, ix, iy, + device_rr_chan.get_module_with_coordinator(CHANY, ix, iy), + device_rr_chan.get_module_id(CHANY, ix, iy)); + } + } + + return; +} + /** Print Top-level SPICE netlist in a compact way @@ -1113,7 +1268,11 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_top_netlist_internal_wires(cur_sram_orgz_info, fp); /* Quote Routing structures: Channels */ - dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + if (TRUE == compact_routing_hierarchy ) { + dump_compact_verilog_defined_channels(fp); + } else { + dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + } /* Quote Routing structures: Switch Boxes */ if (TRUE == compact_routing_hierarchy ) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 7e021bc6f..2846bdd3f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -37,6 +37,129 @@ #include "verilog_utils.h" #include "verilog_routing.h" +void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, + char* verilog_dir, + char* subckt_dir, + size_t rr_chan_subckt_id, const RRChan& rr_chan, + t_syn_verilog_opts fpga_verilog_opts) { + FILE* fp = NULL; + char* fname = NULL; + + /* Initial chan_prefix*/ + switch (rr_chan.get_type()) { + case CHANX: + /* Create file handler */ + fp = verilog_create_one_subckt_file(subckt_dir, "Routing Channel - X direction ", chanx_verilog_file_name_prefix, rr_chan_subckt_id, 0, &fname); + /* Print preprocessing flags */ + verilog_include_defines_preproc_file(fp, verilog_dir); + /* Comment lines */ + fprintf(fp, "//----- Verilog Module of Channel X [%u] -----\n", rr_chan_subckt_id); + break; + case CHANY: + /* Create file handler */ + fp = verilog_create_one_subckt_file(subckt_dir, "Routing Channel - Y direction ", chany_verilog_file_name_prefix, rr_chan_subckt_id, 0, &fname); + /* Print preprocessing flags */ + verilog_include_defines_preproc_file(fp, verilog_dir); + /* Comment lines */ + fprintf(fp, "//----- Verilog Module Channel Y [%u] -----\n", rr_chan_subckt_id); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File:%s, [LINE%d])Invalid Channel type! Should be CHANX or CHANY.\n", + __FILE__, __LINE__); + exit(1); + } + + /* Chan subckt definition */ + fprintf(fp, "module %s ( \n", + gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); + fprintf(fp, "\n"); + /* dump global ports */ + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + fprintf(fp, ",\n"); + } + /* Inputs and outputs, + * Rules for CHANX: + * print left-hand ports(in) first, then right-hand ports(out) + * Rules for CHANX: + * print bottom ports(in) first, then top ports(out) + */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: + fprintf(fp, " input in%u, //--- track %u input \n", itrack, itrack); + break; + case DEC_DIRECTION: + fprintf(fp, " output out%u, //--- track %u output \n", itrack, itrack); + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%u]_in/out[%u]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + switch (rr_chan.get_node(itrack)->direction) { + case INC_DIRECTION: + fprintf(fp, " output out%u, //--- track %u output\n", itrack, itrack); + break; + case DEC_DIRECTION: + fprintf(fp, " input in%u, //--- track %u input \n", itrack, itrack); + break; + case BI_DIRECTION: + default: + vpr_printf(TIO_MESSAGE_ERROR, + "(File: %s [LINE%d]) Invalid direction of rr_node %s[%u]_in/out[%u]!\n", + __FILE__, __LINE__, + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id, itrack); + exit(1); + } + } + /* Middle point output for connection box inputs */ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + fprintf(fp, " output mid_out%u", itrack); + if (itrack < (rr_chan.get_chan_width() - 1)) { + fprintf(fp, ","); + } + fprintf(fp, " // Middle output %u to logic blocks \n", itrack); + } + fprintf(fp, " );\n"); + + /* Print segments models*/ + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* short connecting inputs and outputs: + * length of metal wire and parasitics are handled by semi-custom flow + */ + fprintf(fp, "assign out%u = in%u; \n", itrack, itrack); + fprintf(fp, "assign mid_out%u = in%u; \n", itrack, itrack); + } + + fprintf(fp, "endmodule\n"); + + /* Comment lines */ + fprintf(fp, + "//----- END Verilog Module of %s [%u] -----\n\n", + convert_chan_type_to_string(rr_chan.get_type()), + rr_chan_subckt_id); + + /* Close file handler */ + fclose(fp); + + /* Add fname to the linked list */ + routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, fname); + + /* Free */ + my_free(fname); + + return; +} + + void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, @@ -2011,22 +2134,40 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, * For INC_DIRECTION chany, the inputs are at the bottom of channels, the outputs are at the top of channels * For DEC_DIRECTION chany, the inputs are at the top of channels, the outputs are at the bottom of channels */ - /* X - channels [1...nx][0..ny]*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); - for (iy = 0; iy < (ny + 1); iy++) { - for (ix = 1; ix < (nx + 1); ix++) { - dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, ix, iy, CHANX, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, arch.Segments, fpga_verilog_opts); + if (TRUE == compact_routing_hierarchy) { + /* Call all the unique mirrors in a DeviceRRChan */ + vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); + /* X - channels [1...nx][0..ny]*/ + for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { + dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, + ichan, device_rr_chan.get_module(CHANX, ichan), + fpga_verilog_opts); } - } - /* Y - channels [1...ny][0..nx]*/ - vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); - for (ix = 0; ix < (nx + 1); ix++) { - for (iy = 1; iy < (ny + 1); iy++) { - dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, ix, iy, CHANY, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments, arch.Segments, fpga_verilog_opts); + /* Y - channels [1...ny][0..nx]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); + for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { + dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, + ichan, device_rr_chan.get_module(CHANY, ichan), + fpga_verilog_opts); + } + } else { + /* Output the full array of routing channels */ + vpr_printf(TIO_MESSAGE_INFO, "Writing X-direction Channels...\n"); + for (iy = 0; iy < (ny + 1); iy++) { + for (ix = 1; ix < (nx + 1); ix++) { + dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, ix, iy, CHANX, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, + arch.num_segments, arch.Segments, fpga_verilog_opts); + } + } + /* Y - channels [1...ny][0..nx]*/ + vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); + for (ix = 0; ix < (nx + 1); ix++) { + for (iy = 1; iy < (ny + 1); iy++) { + dump_verilog_routing_chan_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, ix, iy, CHANY, + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, + arch.num_segments, arch.Segments, fpga_verilog_opts); + } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index dbfb5fafb..4bbda5ae4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -3218,14 +3218,22 @@ char* gen_verilog_one_routing_channel_module_name(t_rr_type chan_type, int x, int y) { char* ret = NULL; - ret = (char*)my_malloc(strlen(convert_chan_type_to_string(chan_type)) - + 1 + strlen(my_itoa(x)) - + 2 + strlen(my_itoa(y)) - + 1 + 1); - - sprintf(ret, "%s_%d__%d_", - convert_chan_type_to_string(chan_type), - x, y); + if (-1 == y) { + ret = (char*)my_malloc(strlen(convert_chan_type_to_string(chan_type)) + + 1 + strlen(my_itoa(x)) + + 1 + 1); + sprintf(ret, "%s_%d_", + convert_chan_type_to_string(chan_type), + x); + } else { + ret = (char*)my_malloc(strlen(convert_chan_type_to_string(chan_type)) + + 1 + strlen(my_itoa(x)) + + 2 + strlen(my_itoa(y)) + + 1 + 1); + sprintf(ret, "%s_%d__%d_", + convert_chan_type_to_string(chan_type), + x, y); + } return ret; } diff --git a/vpr7_x2p/vpr/SRC/tags b/vpr7_x2p/vpr/SRC/tags index 285dc6e8a..3a97f03ea 100644 --- a/vpr7_x2p/vpr/SRC/tags +++ b/vpr7_x2p/vpr/SRC/tags @@ -127,6 +127,7 @@ DRAW_NO_RR ./base/draw.c /^ DRAW_NO_RR = 0,$/;" e enum:e_draw_rr_toggle file: DRAW_RR_TOGGLE_MAX ./base/draw.c /^ DRAW_RR_TOGGLE_MAX$/;" e enum:e_draw_rr_toggle file: DRAW_XOR ./base/graphics.h /^enum e_draw_mode {DRAW_NORMAL = 0, DRAW_XOR};$/;" e enum:e_draw_mode DUMPFILE ./place/timing_place_lookup.c 63;" d file: +DeviceRRChan ./fpga_x2p/base/rr_chan.h /^class DeviceRRChan {$/;" c EASYGL_CONSTANTS_H ./base/easygl_constants.h 2;" d EMPTY ./base/vpr_types.h 90;" d EMPTY_TYPE ./base/globals.c /^t_type_ptr EMPTY_TYPE = NULL;$/;" v @@ -198,6 +199,7 @@ FINAL_DISCOUNT_FUNCTION_BASE ./timing/path_delay.h 28;" d FIRST_ITER_WIRELENTH_LIMIT ./base/vpr_types.h 88;" d FONTMAG ./base/graphics.c 229;" d file: FPGA_SPICE_Opts ./base/vpr_types.h /^ t_fpga_spice_opts FPGA_SPICE_Opts; \/* Xifan TANG: FPGA-SPICE support *\/$/;" m struct:s_vpr_setup +FPGA_X2P_GLOBALS_H ./fpga_x2p/base/fpga_x2p_globals.h 2;" d FPGA_X2P_IDENTIFY_ROUTING ./fpga_x2p/base/fpga_x2p_identify_routing.h 3;" d FPGA_X2P_UTILS_H ./fpga_x2p/base/fpga_x2p_utils.h 2;" d FREE ./base/vpr_types.h /^ FREE, RANDOM, USER$/;" e enum:e_pad_loc_type @@ -606,6 +608,8 @@ ROUTE_CMD ./fpga_x2p/shell/shell_types.h /^ ROUTE_CMD,$/;" e enum:e_cmd_categor ROUTE_FILE_POSTFIX ./fpga_x2p/shell/shell_file_postfix.h 4;" d ROUTE_PATH_WEIGHT ./timing/path_delay.h 37;" d ROUTING ./base/vpr_types.h /^ NO_PICTURE, PLACEMENT, ROUTING$/;" e enum:pic_type +RRChan ./fpga_x2p/base/rr_chan.h /^class RRChan {$/;" c +RR_CHAN_H ./fpga_x2p/base/rr_chan.h 6;" d RR_GRAPH2_H ./route/rr_graph2.h 2;" d RR_GRAPH_H ./route/rr_graph.h 2;" d RR_GRAPH_NO_WARN ./route/rr_graph.h /^ RR_GRAPH_NO_WARN = 0x00,$/;" e enum:__anon17 @@ -820,8 +824,6 @@ add_activity_to_net ./base/read_blif.c /^bool add_activity_to_net(char * net_nam add_conf_bit_info_to_llist ./fpga_x2p/base/fpga_x2p_utils.c /^add_conf_bit_info_to_llist(t_llist* head, int index, $/;" f add_data_point ./power/PowerSpicedComponent.c /^void PowerSpicedComponent::add_data_point(int num_inputs, float transistor_size,$/;" f class:PowerSpicedComponent add_delay_to_array ./mrfpga/buffer_insertion.c /^static void add_delay_to_array( float* sink_delay, t_linked_int* index, float delay_addition )$/;" f file: -add_delay_to_buffer_list ./mrfpga/buffer_insertion.c /^static void add_delay_to_buffer_list( t_buffer_plan_list list, float Tdel , boolean skip_first )$/;" f file: -add_delay_to_buffer_plan ./mrfpga/buffer_insertion.c /^static t_buffer_plan add_delay_to_buffer_plan( t_buffer_plan plan, float Tdel )$/;" f file: add_entry ./power/PowerSpicedComponent.c /^PowerCallibInputs * PowerSpicedComponent::add_entry(int num_inputs) {$/;" f class:PowerSpicedComponent add_heap_node_to_rr_graph_heap ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void add_heap_node_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f add_latch ./base/read_blif.c /^static void add_latch(int doall, INP t_model *latch_model) {$/;" f file: @@ -833,7 +835,9 @@ add_mux_membank_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^ add_mux_scff_conf_bits_to_llist ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^add_mux_scff_conf_bits_to_llist(int mux_size,$/;" f add_net_rr_terminal_cluster ./pack/cluster_legality.c /^static void add_net_rr_terminal_cluster(int iblk_net,$/;" f file: add_net_to_hash ./base/read_netlist.c /^static int add_net_to_hash(INOUTP struct s_hash **nhash, INP char *net_name,$/;" f file: +add_node ./fpga_x2p/base/rr_chan.cpp /^void RRChan::add_node(t_rr_node* node, size_t node_segment) {$/;" f class:RRChan add_node_to_rr_graph_heap ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void add_node_to_rr_graph_heap(t_rr_graph* local_rr_graph,$/;" f +add_one_chan_module ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::add_one_chan_module(t_rr_type chan_type, size_t x, size_t y, RRChan& rr_chan) {$/;" f class:DeviceRRChan add_one_conf_bit_to_sram_orgz_info ./fpga_x2p/base/fpga_x2p_bitstream_utils.c /^void add_one_conf_bit_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info) {$/;" f add_one_spice_tb_info_to_llist ./fpga_x2p/spice/spice_utils.c /^t_llist* add_one_spice_tb_info_to_llist(t_llist* cur_head, $/;" f add_one_subckt_file_name_to_llist ./fpga_x2p/base/fpga_x2p_utils.c /^t_llist* add_one_subckt_file_name_to_llist(t_llist* cur_head, $/;" f @@ -1123,8 +1127,10 @@ buffer_size_inf ./power/power.h /^ t_power_buffer_size_inf * buffer_size_inf;$/; buffered ./base/vpr_types.h /^ int buffered;$/;" m struct:s_rr_node build_bidir_rr_opins ./route/rr_graph.c /^static void build_bidir_rr_opins(INP int i, INP int j,$/;" f file: build_default_menu ./base/graphics.c /^build_default_menu (void) $/;" f file: +build_device_rr_chan ./fpga_x2p/base/fpga_x2p_identify_routing.c /^DeviceRRChan build_device_rr_chan(int LL_num_rr_nodes, t_rr_node* LL_rr_node, $/;" f build_ending_rr_node_for_one_sb_wire ./fpga_x2p/verilog/verilog_report_timing.c /^void build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_node, $/;" f build_one_connection_block_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void build_one_connection_block_info(t_cb* cur_cb, int cb_x, int cb_y, t_rr_type cb_type,$/;" f +build_one_rr_chan ./fpga_x2p/base/fpga_x2p_identify_routing.c /^RRChan build_one_rr_chan(t_rr_type chan_type, size_t chan_x, size_t chan_y,$/;" f build_one_switch_block_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void build_one_switch_block_info(t_sb* cur_sb, int sb_x, int sb_y, $/;" f build_prev_node_list_rr_nodes ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void build_prev_node_list_rr_nodes(int LL_num_rr_nodes,$/;" f build_rr_graph ./route/rr_graph.c /^void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types,$/;" f @@ -1172,9 +1178,13 @@ change_button_text ./base/graphics.c /^void change_button_text(const char *butto change_button_text ./base/graphics.c /^void change_button_text(const char *button_text, const char *new_button_text) { }$/;" f channel_width ./power/power.h /^ int channel_width;$/;" m struct:s_solution_inf chanx_chany_adjacent ./route/check_route.c /^static int chanx_chany_adjacent(int chanx_node, int chany_node) {$/;" f file: +chanx_module_ids_ ./fpga_x2p/base/rr_chan.h /^ std::vector< std::vector > chanx_module_ids_; \/* Module id in modules_ for each X-direction rr_channel *\/ $/;" m class:DeviceRRChan +chanx_modules_ ./fpga_x2p/base/rr_chan.h /^ std::vector chanx_modules_; \/* Detailed internal structure of each unique module *\/$/;" m class:DeviceRRChan chanx_place_cost_fac ./place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: chanx_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* chanx_spice_file_name_prefix = "chanx_";$/;" v chanx_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* chanx_verilog_file_name_prefix = "chanx_";$/;" v +chany_module_ids_ ./fpga_x2p/base/rr_chan.h /^ std::vector< std::vector > chany_module_ids_; \/* Module id in modules_ for each Y-direction rr_channel *\/ $/;" m class:DeviceRRChan +chany_modules_ ./fpga_x2p/base/rr_chan.h /^ std::vector chany_modules_; \/* Detailed internal structure of each unique module *\/$/;" m class:DeviceRRChan chany_place_cost_fac ./place/place.c /^static float **chanx_place_cost_fac, **chany_place_cost_fac;$/;" v file: chany_spice_file_name_prefix ./fpga_x2p/spice/spice_globals.c /^char* chany_spice_file_name_prefix = "chany_";$/;" v chany_verilog_file_name_prefix ./fpga_x2p/verilog/verilog_global.c /^char* chany_verilog_file_name_prefix = "chany_";$/;" v @@ -1252,7 +1262,10 @@ clb_net_density ./power/power_util.c /^float clb_net_density(int net_idx) {$/;" clb_net_prob ./power/power_util.c /^float clb_net_prob(int net_idx) {$/;" f clb_opins_used_locally ./place/timing_place_lookup.c /^static t_ivec **clb_opins_used_locally;$/;" v file: clb_to_vpack_net_mapping ./base/globals.c /^int *clb_to_vpack_net_mapping = NULL; \/* [0..num_clb_nets - 1] *\/$/;" v +clear ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::clear() {$/;" f class:DeviceRRChan +clear ./fpga_x2p/base/rr_chan.cpp /^void RRChan::clear() {$/;" f class:RRChan clear_buffer ./mrfpga/buffer_insertion.c /^void clear_buffer( )$/;" f +clear_chan ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::clear_chan(t_rr_type chan_type) {$/;" f class:DeviceRRChan clearscreen ./base/graphics.c /^clearscreen (void) $/;" f clearscreen ./base/graphics.c /^void clearscreen (void) { }$/;" f clock_delay ./base/vpr_types.h /^ float clock_delay; \/* The time taken for a clock signal to get to the flip-flop or I\/O (assumed 0 for I\/Os). *\/$/;" m struct:s_tnode @@ -1493,6 +1506,7 @@ determine_rr_node_default_prev_node ./fpga_x2p/base/fpga_x2p_backannotate_utils. determine_sb_port_coordinator ./fpga_x2p/base/fpga_x2p_utils.c /^void determine_sb_port_coordinator(t_sb cur_sb_info, int side, $/;" f determine_tree_mux_level ./fpga_x2p/base/fpga_x2p_mux_utils.c /^int determine_tree_mux_level(int mux_size) {$/;" f determine_verilog_generic_port_split_sign ./fpga_x2p/verilog/verilog_utils.c /^char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type) {$/;" f +device_rr_chan ./fpga_x2p/base/fpga_x2p_globals.c /^DeviceRRChan device_rr_chan;$/;" v diff_sram_orgz_info ./fpga_x2p/base/fpga_x2p_utils.c /^t_sram_orgz_info* diff_sram_orgz_info(t_sram_orgz_info* des_sram_orgz_info, $/;" f direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_rr_node typeref:enum:s_rr_node::e_direction direction ./base/vpr_types.h /^ enum e_direction direction; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_direction @@ -1576,8 +1590,14 @@ drivers ./base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m s drivers ./base/vpr_types.h /^ enum e_drivers drivers; \/* UDSD by AY *\/$/;" m struct:s_seg_details typeref:enum:s_seg_details::e_drivers dum_parse ./base/read_blif.c /^void dum_parse(char *buf) {$/;" f dummy_type_descriptors ./place/timing_place_lookup.c /^static t_type_descriptor dummy_type_descriptors[NUM_TYPES_USED];$/;" v file: +dump_compact_verilog_defined_channels ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_channels(FILE* fp) {$/;" f +dump_compact_verilog_defined_connection_boxes ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info,$/;" f dump_compact_verilog_defined_grids ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info,$/;" f +dump_compact_verilog_defined_one_channel ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_channel(FILE* fp,$/;" f file: +dump_compact_verilog_defined_one_connection_box ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: dump_compact_verilog_defined_one_grid ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info,$/;" f file: +dump_compact_verilog_defined_one_switch_box ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, $/;" f file: +dump_compact_verilog_defined_switch_boxes ./fpga_x2p/verilog/verilog_compact_netlist.c /^void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, $/;" f dump_compact_verilog_grid_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_grid_pins(FILE* fp,$/;" f dump_compact_verilog_io_grid_block_subckt_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp,$/;" f dump_compact_verilog_io_grid_pins ./fpga_x2p/verilog/verilog_top_netlist_utils.c /^void dump_compact_verilog_io_grid_pins(FILE* fp,$/;" f @@ -1840,6 +1860,8 @@ encode_decoder_addr ./fpga_x2p/bitstream/fpga_bitstream.c /^void encode_decoder_ endlines ./base/read_blif.c /^static int ilines, olines, model_lines, endlines;$/;" v file: entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerSpicedComponent entries ./power/PowerSpicedComponent.h /^ std::vector entries;$/;" m class:PowerCallibInputs +error_counter ./fpga_x2p/verilog/verilog_autocheck_top_testbench.c /^static char* error_counter = "nb_error";$/;" v file: +error_counter ./fpga_x2p/verilog/verilog_formal_random_top_testbench.c /^static char* error_counter = "nb_error";$/;" v file: error_no_match ./timing/slre.c /^static const char *error_no_match = "No match";$/;" v file: error_string ./timing/slre.c /^ const char *error_string; \/\/ Error string$/;" m struct:slre file: essentials_verilog_file_name ./fpga_x2p/verilog/verilog_global.c /^char* essentials_verilog_file_name = "inv_buf_passgate.v";$/;" v @@ -2412,6 +2434,7 @@ get_chan_rr_node_ending_cb ./fpga_x2p/verilog/verilog_tcl_utils.c /^t_cb* get_ch get_chan_rr_node_ending_sb ./fpga_x2p/verilog/verilog_tcl_utils.c /^t_sb* get_chan_rr_node_ending_sb(t_rr_node* src_rr_node, $/;" f get_chan_rr_node_start_coordinate ./fpga_x2p/base/fpga_x2p_rr_graph_utils.c /^void get_chan_rr_node_start_coordinate(t_rr_node* chan_rr_node,$/;" f get_chan_rr_nodes ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^t_rr_node** get_chan_rr_nodes(int* num_chan_rr_nodes,$/;" f +get_chan_width ./fpga_x2p/base/rr_chan.cpp /^size_t RRChan::get_chan_width() const { $/;" f class:RRChan get_channel_occupancy_stats ./base/stats.c /^static void get_channel_occupancy_stats(void) {$/;" f file: get_child_pb_for_phy_pb_graph_node ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^t_pb* get_child_pb_for_phy_pb_graph_node(t_pb* cur_pb, int ipb, int jpb) {$/;" f get_class_range_for_block ./util/vpr_utils.c /^void get_class_range_for_block(INP int iblk, OUTP int *class_low,$/;" f @@ -2468,6 +2491,9 @@ get_max_nets_in_pb_type ./util/vpr_utils.c /^int get_max_nets_in_pb_type(const t get_max_pins_per_net ./route/route_timing.c /^static int get_max_pins_per_net(void) {$/;" f file: get_max_primitives_in_pb_type ./util/vpr_utils.c /^int get_max_primitives_in_pb_type(t_pb_type *pb_type) {$/;" f get_mem_bank_info_reserved_blwl ./fpga_x2p/base/fpga_x2p_utils.c /^void get_mem_bank_info_reserved_blwl(t_mem_bank_info* cur_mem_bank_info,$/;" f +get_module ./fpga_x2p/base/rr_chan.cpp /^RRChan DeviceRRChan::get_module(t_rr_type chan_type, size_t module_id) const {$/;" f class:DeviceRRChan +get_module_id ./fpga_x2p/base/rr_chan.cpp /^size_t DeviceRRChan::get_module_id(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan +get_module_with_coordinator ./fpga_x2p/base/rr_chan.cpp /^RRChan DeviceRRChan::get_module_with_coordinator(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan get_molecule_by_num_ext_inputs ./pack/cluster.c /^static t_pack_molecule *get_molecule_by_num_ext_inputs($/;" f file: get_molecule_for_cluster ./pack/cluster.c /^static t_pack_molecule *get_molecule_for_cluster($/;" f file: get_molecule_gain ./pack/cluster.c /^static float get_molecule_gain(t_pack_molecule *molecule, std::map &blk_gain) {$/;" f file: @@ -2481,9 +2507,14 @@ get_net_cost ./place/place.c /^static float get_net_cost(int inet, struct s_bb * get_net_wirelength_estimate ./place/place.c /^static double get_net_wirelength_estimate(int inet, struct s_bb *bbptr) {$/;" f file: get_next_hash ./util/hash.c /^get_next_hash(struct s_hash **hash_table, struct s_hash_iterator *hash_iterator) {$/;" f get_next_primitive_list ./pack/cluster_placement.c /^boolean get_next_primitive_list($/;" f +get_node ./fpga_x2p/base/rr_chan.cpp /^t_rr_node* RRChan::get_node(size_t track_num) const {$/;" f class:RRChan +get_node_segment ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_segment(size_t track_num) const {$/;" f class:RRChan +get_node_segment ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_segment(t_rr_node* node) const {$/;" f class:RRChan +get_node_track_id ./fpga_x2p/base/rr_chan.cpp /^int RRChan::get_node_track_id(t_rr_node* node) const {$/;" f class:RRChan get_non_updateable_bb ./place/place.c /^static void get_non_updateable_bb(int inet, struct s_bb *bb_coord_new) {$/;" f file: get_num_bends_and_length ./base/stats.c /^void get_num_bends_and_length(int inet, int *bends_ptr, int *len_ptr,$/;" f get_num_conn ./base/check_netlist.c /^static int get_num_conn(int bnum) {$/;" f file: +get_num_modules ./fpga_x2p/base/rr_chan.cpp /^size_t DeviceRRChan::get_num_modules(t_rr_type chan_type) const {$/;" f class:DeviceRRChan get_opin_direct_connecions ./route/rr_graph.c /^static int get_opin_direct_connecions(int x, int y, int opin, INOUTP t_linked_edge ** edge_list_ptr, INP t_ivec *** L_rr_node_indices, $/;" f file: get_opposite_side ./fpga_x2p/base/fpga_x2p_utils.c /^int get_opposite_side(int side){$/;" f get_opt_float_val ./fpga_x2p/shell/read_opt.c /^float get_opt_float_val(t_opt_info* opts, char* opt_name, float default_val) {$/;" f @@ -2546,6 +2577,7 @@ get_top_of_heap_index ./util/heapsort.c /^static int get_top_of_heap_index(int * get_track_num ./base/draw.c /^static int get_track_num(int inode, int **chanx_track, int **chany_track) {$/;" f file: get_track_to_ipins ./route/rr_graph2.c /^int get_track_to_ipins(int seg, int chan, int track,$/;" f get_track_to_tracks ./route/rr_graph2.c /^int get_track_to_tracks(INP int from_chan, INP int from_seg, INP int from_track,$/;" f +get_type ./fpga_x2p/base/rr_chan.cpp /^t_rr_type RRChan::get_type() const {$/;" f class:RRChan get_unidir_opin_connections ./route/rr_graph2.c /^int get_unidir_opin_connections(INP int chan, INP int seg, INP int Fc,$/;" f get_unidir_track_to_chan_seg ./route/rr_graph2.c /^static int get_unidir_track_to_chan_seg(INP boolean is_end_sb,$/;" f file: get_unused_spice_model_port_tedge ./fpga_x2p/base/fpga_x2p_timing_utils.c /^t_spice_model_tedge* get_unused_spice_model_port_tedge(t_spice_model_port* cur_port,$/;" f @@ -2640,6 +2672,7 @@ index ./util/hash.h /^ int index;$/;" m struct:s_hash init_and_check_one_sram_inf_orgz ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz,$/;" f file: init_and_check_sram_inf ./fpga_x2p/base/fpga_x2p_setup.c /^void init_and_check_sram_inf(t_arch* arch,$/;" f file: init_chan ./base/place_and_route.c /^void init_chan(int cfactor, t_chan_width_dist chan_width_dist) {$/;" f +init_chan_module_ids ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::init_chan_module_ids(t_rr_type chan_type, size_t device_width, size_t device_height) {$/;" f class:DeviceRRChan init_chan_seg_detail_params ./route/rr_graph_swseg.c /^static int init_chan_seg_detail_params(INP char* chan_type,$/;" f file: init_check_arch_pb_type_idle_and_phy_mode ./fpga_x2p/base/fpga_x2p_setup.c /^void init_check_arch_pb_type_idle_and_phy_mode(t_arch* Arch) {$/;" f file: init_check_arch_spice_models ./fpga_x2p/base/fpga_x2p_setup.c /^void init_check_arch_spice_models(t_arch* arch,$/;" f @@ -2658,6 +2691,7 @@ init_llist_verilog_and_spice_syntax_char ./fpga_x2p/base/fpga_x2p_setup.c /^t_ll init_logical_block_spice_model_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_temp_used(t_spice_model* spice_model) {$/;" f init_logical_block_spice_model_type_temp_used ./fpga_x2p/spice/spice_utils.c /^void init_logical_block_spice_model_type_temp_used(int num_spice_models, t_spice_model* spice_model,$/;" f init_mem_bank_info ./fpga_x2p/base/fpga_x2p_utils.c /^void init_mem_bank_info(t_mem_bank_info* cur_mem_bank_info,$/;" f +init_module_ids ./fpga_x2p/base/rr_chan.cpp /^void DeviceRRChan::init_module_ids(size_t device_width, size_t device_height) {$/;" f class:DeviceRRChan init_mux_arch_default ./power/power_util.c /^static void init_mux_arch_default(t_mux_arch * mux_arch, int levels,$/;" f file: init_one_cb_info ./fpga_x2p/base/fpga_x2p_backannotate_utils.c /^void init_one_cb_info(t_cb* cur_cb) { $/;" f init_one_grid_num_conf_bits ./fpga_x2p/base/fpga_x2p_pbtypes_utils.c /^void init_one_grid_num_conf_bits(int ix, int iy, $/;" f @@ -2769,6 +2803,7 @@ is_in_heap ./base/vpr_types.h /^ boolean is_in_heap;$/;" m struct:s_rr_node is_isolation ./mrfpga/mrfpga_globals.c /^boolean is_isolation = FALSE;$/;" v is_junction ./mrfpga/mrfpga_globals.c /^boolean is_junction = FALSE;$/;" v is_logical_blk_in_pb ./pack/cluster.c /^static boolean is_logical_blk_in_pb(int iblk, t_pb *pb) {$/;" f file: +is_mirror ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::is_mirror(RRChan& cand) const {$/;" f class:RRChan is_mrFPGA ./mrfpga/mrfpga_globals.c /^boolean is_mrFPGA = FALSE;$/;" v is_net_in_cluster ./pack/cluster_legality.c /^static boolean is_net_in_cluster(INP int inet) {$/;" f file: is_net_pi ./fpga_x2p/base/fpga_x2p_utils.c /^boolean is_net_pi(t_net* cur_net) {$/;" f @@ -3021,6 +3056,7 @@ my_realloc ./base/graphics.c /^static void *my_realloc(void *memblk, int ibytes) my_remove_file ./fpga_x2p/base/fpga_x2p_utils.c /^void my_remove_file(char* file_path) {$/;" f my_strcat ./fpga_x2p/base/fpga_x2p_utils.c /^char* my_strcat(char* str1,$/;" f my_strcmp ./fpga_x2p/shell/shell_utils.c /^int my_strcmp(char* str1, char* str2) {$/;" f +my_strlen_int ./fpga_x2p/base/fpga_x2p_utils.c /^int my_strlen_int(int input_int) {$/;" f name ./base/vpr_types.h /^ char * name; \/* I\/O port name with an SDC constraint *\/$/;" m struct:s_io name ./base/vpr_types.h /^ char * name;$/;" m struct:s_clock name ./base/vpr_types.h /^ char *name; \/* Name of this physical block *\/$/;" m struct:s_pb @@ -3090,7 +3126,9 @@ nmos_subckt_name ./fpga_x2p/spice/spice_globals.c /^char* nmos_subckt_name = "vp node_block ./base/vpr_types.h /^ int *node_block;$/;" m struct:s_net node_block_pin ./base/vpr_types.h /^ int *node_block_pin;$/;" m struct:s_net node_block_port ./base/vpr_types.h /^ int *node_block_port;$/;" m struct:s_net +node_segments_ ./fpga_x2p/base/rr_chan.h /^ std::vector node_segments_; \/* segment of each track *\/$/;" m class:RRChan node_to_heap ./route/route_common.c /^void node_to_heap(int inode, float cost, int prev_node, int prev_edge,$/;" f +nodes_ ./fpga_x2p/base/rr_chan.h /^ std::vector nodes_; \/* rr nodes of each track in the channel *\/$/;" m class:RRChan normalized_T_arr ./base/vpr_types.h /^ float normalized_T_arr; \/* arrival time (normalized with respect to max time) *\/$/;" m struct:s_prepacked_tnode_data normalized_slack ./base/vpr_types.h /^ float normalized_slack; \/* slack (normalized with respect to max slack) *\/$/;" m struct:s_prepacked_tnode_data normalized_total_critical_paths ./base/vpr_types.h /^ float normalized_total_critical_paths; \/* critical path count (normalized with respect to max count) *\/$/;" m struct:s_prepacked_tnode_data @@ -3921,6 +3959,7 @@ set_src_bottom_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_ set_src_left_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_left_side_net_one_sink_prefer_side(int* prefer_side, $/;" f set_src_right_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_right_side_net_one_sink_prefer_side(int* prefer_side, $/;" f set_src_top_side_net_one_sink_prefer_side ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^void set_src_top_side_net_one_sink_prefer_side(int* prefer_side, $/;" f +set_type ./fpga_x2p/base/rr_chan.cpp /^void RRChan::set_type(t_rr_type type) {$/;" f class:RRChan set_unroute_blk_pins_prefer_sides ./fpga_x2p/clb_pin_remap/place_clb_pin_remap.c /^int set_unroute_blk_pins_prefer_sides(int n_blk, t_block* blk) {$/;" f setcolor ./base/graphics.c /^void setcolor (int cindex) $/;" f setcolor ./base/graphics.c /^void setcolor (int cindex) { }$/;" f @@ -4378,6 +4417,7 @@ type ./base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_block type ./base/vpr_types.h /^ t_type_ptr type;$/;" m struct:s_grid_tile type ./base/vpr_types.h /^ t_rr_type type;$/;" m struct:s_cb type ./util/token.h /^ enum e_token_type type;$/;" m struct:s_token typeref:enum:s_token::e_token_type +type_ ./fpga_x2p/base/rr_chan.h /^ t_rr_type type_; \/* channel type: CHANX or CHANY *\/$/;" m class:RRChan type_descriptors ./base/globals.c /^struct s_type_descriptor *type_descriptors = NULL;$/;" v typeref:struct:s_type_descriptor type_descriptors_backup ./place/timing_place_lookup.c /^static t_type_descriptor *type_descriptors_backup;$/;" v file: u ./route/route_common.h /^ } u;$/;" m struct:s_heap typeref:union:s_heap::__anon14 @@ -4460,7 +4500,12 @@ v_out_min ./power/power.h /^ float v_out_min;$/;" m struct:s_power_mux_volt_pair val ./fpga_x2p/shell/read_opt_types.h /^ char* val; \/*The value*\/$/;" m struct:s_opt_info val_type ./fpga_x2p/shell/read_opt_types.h /^ enum opt_val_type val_type; $/;" m struct:s_opt_info typeref:enum:s_opt_info::opt_val_type valid ./base/vpr_types.h /^ boolean valid; \/* Whether or not this molecule is still valid *\/$/;" m struct:s_pack_molecule +valid_chan_type ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_chan_type(t_rr_type chan_type) const {$/;" f class:DeviceRRChan +valid_coordinator ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_coordinator(t_rr_type chan_type, size_t x, size_t y) const {$/;" f class:DeviceRRChan +valid_module_id ./fpga_x2p/base/rr_chan.cpp /^bool DeviceRRChan::valid_module_id(t_rr_type chan_type, size_t module_id) const {$/;" f class:DeviceRRChan +valid_node_id ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::valid_node_id(size_t node_id) const {$/;" f class:RRChan valid_primitives ./base/vpr_types.h /^ t_cluster_placement_primitive **valid_primitives; \/* [0..num_pb_types-1] ptrs to linked list of valid primitives, for convenience, each linked list head is empty *\/$/;" m struct:s_cluster_placement_stats +valid_type ./fpga_x2p/base/rr_chan.cpp /^bool RRChan::valid_type(t_rr_type type) const {$/;" f class:RRChan validate_mirror_connection_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_connection_blocks() {$/;" f validate_mirror_switch_blocks ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_mirror_switch_blocks() {$/;" f validate_one_connection_block_mirror ./fpga_x2p/base/fpga_x2p_identify_routing.c /^boolean validate_one_connection_block_mirror(t_cb* cur_cb) {$/;" f