[doc] add ack page. move related files to appendix subdirectory

2022-12-06 16:03:34 -08:00 · 2022-12-06 16:03:34 -08:00 · b179f4bd7f
parent 19c99d6f0d
commit b179f4bd7f
15 changed files with 38 additions and 3 deletions
--- a/docs/source/appendix/acknowledge.rst
+++ b/docs/source/appendix/acknowledge.rst
@ -0,0 +1,21 @@
+.. _acknowledgement:
+
+Acknowledgement
+===============
+
+We are thankful to the organizations which support the OpenFPGA project and build the growing community.
+
+.. figure:: ./figures/uofu_logo.png
+      :width: 30%
+.. figure:: ./figures/lnis_logo.png
+      :width: 30%
+.. figure:: ./figures/darpa_logo.png
+      :width: 30%
+.. figure:: ./figures/google_logo.png
+      :width: 30%
+.. figure:: ./figures/quicklogic_logo.png
+      :width: 30%
+.. figure:: ./figures/rapidsilicon_logo.png
+      :width: 30%
+.. figure:: ./figures/rapidflex_logo.png
+      :width: 30%
--- a/docs/source/appendix/contact.rst
+++ b/docs/source/appendix/contact.rst
@ -9,7 +9,7 @@ Prof. Pierre-Emmanuel Gaillardon

 pierre-emmanuel.gaillardon@utah.edu

-Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
+Technical Details about EDA and Software:

 Dr. Xifan Tang

--- a/docs/source/appendix/figures/darpa_logo.png
+++ b/docs/source/appendix/figures/darpa_logo.png
--- a/docs/source/appendix/figures/google_logo.png
+++ b/docs/source/appendix/figures/google_logo.png
--- a/docs/source/appendix/figures/lnis_logo.png
+++ b/docs/source/appendix/figures/lnis_logo.png
--- a/docs/source/appendix/figures/quicklogic_logo.png
+++ b/docs/source/appendix/figures/quicklogic_logo.png
--- a/docs/source/appendix/figures/rapidflex_logo.png
+++ b/docs/source/appendix/figures/rapidflex_logo.png
--- a/docs/source/appendix/figures/rapidflex_logo.png:Zone.Identifier
+++ b/docs/source/appendix/figures/rapidflex_logo.png:Zone.Identifier
@ -0,0 +1,3 @@
+[ZoneTransfer]
+ZoneId=3
+HostUrl=https://rapidflex.cn/wp-content/uploads/2022/04/Untitled-design-49.png
--- a/docs/source/appendix/figures/rapidsilicon_logo.png
+++ b/docs/source/appendix/figures/rapidsilicon_logo.png
--- a/docs/source/appendix/figures/uofu_logo.png
+++ b/docs/source/appendix/figures/uofu_logo.png
--- a/docs/source/appendix/index.rst
+++ b/docs/source/appendix/index.rst
@ -0,0 +1,9 @@
+
+.. toctree::
+   :maxdepth: 1
+
+   contact
+
+   acknowledge
+
+   reference
--- a/docs/source/appendix/reference.rst
+++ b/docs/source/appendix/reference.rst
--- a/docs/source/appendix/z_reference.bib
+++ b/docs/source/appendix/z_reference.bib
--- a/docs/source/dev_manual/index.rst
+++ b/docs/source/dev_manual/index.rst
@ -6,6 +6,9 @@

   back_compatible

+   contributor_guidelines
+
   cicd_setup

   regression_tests
+
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@ -34,8 +34,7 @@ Welcome to OpenFPGA's documentation!
   :maxdepth: 2
   :caption: Appendix

-   contact
-   reference
+   appendix/index

 For more information on the VTR see vtr_doc_ or vtr_github_