[doc] add ack page. move related files to appendix subdirectory

docs/source/appendix/acknowledge.rst

@@ -0,0 +1,21 @@
+.. _acknowledgement:
+
+Acknowledgement
+===============
+
+We are thankful to the organizations which support the OpenFPGA project and build the growing community.
+
+.. figure:: ./figures/uofu_logo.png
+      :width: 30%
+.. figure:: ./figures/lnis_logo.png
+      :width: 30%
+.. figure:: ./figures/darpa_logo.png
+      :width: 30%
+.. figure:: ./figures/google_logo.png
+      :width: 30%
+.. figure:: ./figures/quicklogic_logo.png
+      :width: 30%
+.. figure:: ./figures/rapidsilicon_logo.png
+      :width: 30%
+.. figure:: ./figures/rapidflex_logo.png
+      :width: 30%

docs/source/appendix/contact.rst

@@ -9,7 +9,7 @@ Prof. Pierre-Emmanuel Gaillardon
 
 pierre-emmanuel.gaillardon@utah.edu
 
-Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
+Technical Details about EDA and Software:
 
 Dr. Xifan Tang
 

docs/source/appendix/figures/rapidflex_logo.png:Zone.Identifier

@@ -0,0 +1,3 @@
+[ZoneTransfer]
+ZoneId=3
+HostUrl=https://rapidflex.cn/wp-content/uploads/2022/04/Untitled-design-49.png

docs/source/appendix/index.rst

@@ -0,0 +1,9 @@
+
+.. toctree::
+   :maxdepth: 1
+
+   contact
+
+   acknowledge
+
+   reference

docs/source/dev_manual/index.rst

@@ -6,6 +6,9 @@
 
    back_compatible
 
+   contributor_guidelines
+
    cicd_setup
 
    regression_tests
+

docs/source/index.rst

@@ -34,8 +34,7 @@ Welcome to OpenFPGA's documentation!
    :maxdepth: 2
    :caption: Appendix
 
-   contact
+   appendix/index
-   reference
 
 For more information on the VTR see vtr_doc_ or vtr_github_