diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
index ff4eca8d2..197bef1c8 100644
--- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
@@ -34,3 +34,27 @@ bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
+
+[SCRIPT_PARAM_Fixed_Routing_30]
+fix_route_chan_width=30
+
+[SCRIPT_PARAM_Fixed_Routing_40]
+fix_route_chan_width=40
+
+[SCRIPT_PARAM_Fixed_Routing_50]
+fix_route_chan_width=50
+
+[SCRIPT_PARAM_Fixed_Routing_60]
+fix_route_chan_width=60
+
+[SCRIPT_PARAM_Fixed_Routing_70]
+fix_route_chan_width=70
+
+[SCRIPT_PARAM_Fixed_Routing_80]
+fix_route_chan_width=80
+
+[SCRIPT_PARAM_Fixed_Routing_90]
+fix_route_chan_width=90
+
+[SCRIPT_PARAM_Fixed_Routing_100]
+fix_route_chan_width=100