From b0a97a7052f0c85e66d541f8ca465071c158f0d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 27 Sep 2021 10:24:04 -0700 Subject: [PATCH] [Doc] Update doc about WLR usage for QL memory bank --- docs/source/manual/arch_lang/config_protocol.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index 560dc77fa..04b47d638 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -177,6 +177,7 @@ The BL and WL protocols can be customized through the XML syntax ``bl`` and ``wl - two outputs (one regular and another inverted) - a Bit-Line input to load the data - a Word-Line input to enable data write + - (optional) a Word-Line read input to enabe data readback .. warning:: Please do NOT add inverted Bit-Line and Word-Line inputs. It is not supported yet!