From b09b051249090a090d890d934ae96f1c99b71880 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 27 Mar 2020 13:58:35 -0600 Subject: [PATCH] add all the test cases considering tileable, carry chain, direct connection and memory blocks --- .../test_script/and_k6_frac_tileable.openfpga | 59 + .../and_k6_frac_tileable_adder_chain.openfpga | 62 + ..._frac_tileable_adder_chain_mem16K.openfpga | 62 + ...e_thru_channel_adder_chain_mem16K.openfpga | 62 + .../and_latch_k6_frac_tileable.openfpga | 59 + ...atch_k6_frac_tileable_adder_chain.openfpga | 62 + ..._frac_tileable_adder_chain_mem16K.openfpga | 62 + openfpga/test_vpr_arch/k6_N10_40nm.xml | 2 +- .../test_vpr_arch/k6_N10_tileable_40nm.xml | 299 ++++ openfpga/test_vpr_arch/k6_frac_N10_40nm.xml | 2 +- .../k6_frac_N10_adder_chain_40nm.xml | 2 +- .../k6_frac_N10_adder_chain_mem16K_40nm.xml | 2 +- ...rac_N10_frac_chain_depop50_mem32K_40nm.xml | 1429 ----------------- .../k6_frac_N10_tileable_40nm.xml | 441 +++++ .../k6_frac_N10_tileable_adder_chain_40nm.xml | 639 ++++++++ ...c_N10_tileable_adder_chain_mem16K_40nm.xml | 734 +++++++++ ..._thru_channel_adder_chain_mem16K_40nm.xml} | 0 17 files changed, 2545 insertions(+), 1433 deletions(-) create mode 100644 openfpga/test_script/and_k6_frac_tileable.openfpga create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga create mode 100644 openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga create mode 100644 openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable.openfpga create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga create mode 100644 openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga create mode 100644 openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml delete mode 100644 openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml create mode 100644 openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml rename openfpga/test_vpr_arch/{k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml => k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml} (100%) diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga new file mode 100644 index 000000000..0731e6543 --- /dev/null +++ b/openfpga/test_script/and_k6_frac_tileable.openfpga @@ -0,0 +1,59 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga new file mode 100644 index 000000000..77fa29aa1 --- /dev/null +++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga @@ -0,0 +1,62 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose + +# Write GSB to XML for debugging +write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga new file mode 100644 index 000000000..ed0d8cc5a --- /dev/null +++ b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga @@ -0,0 +1,62 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose + +# Write GSB to XML for debugging +write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga new file mode 100644 index 000000000..5b1177586 --- /dev/null +++ b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga @@ -0,0 +1,62 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose + +# Write GSB to XML for debugging +write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga new file mode 100644 index 000000000..c89174d2d --- /dev/null +++ b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga @@ -0,0 +1,59 @@ +# Run VPR for the 'and_latch' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin #--verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack --verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga new file mode 100644 index 000000000..ef49426d0 --- /dev/null +++ b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga @@ -0,0 +1,62 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose + +# Write GSB to XML for debugging +write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga new file mode 100644 index 000000000..87c69c880 --- /dev/null +++ b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga @@ -0,0 +1,62 @@ +# Run VPR for the 'and' design +vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml + +# Write out the architecture XML as a proof +#write_openfpga_arch -f ./arch_echo.xml + +# Annotate the OpenFPGA architecture to VPR data base +link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose + +# Write GSB to XML for debugging +write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup #--verbose + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --duplicate_grid_pin --verbose + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis + +# Finish and exit OpenFPGA +exit diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml index bbd694a79..630011e84 100644 --- a/openfpga/test_vpr_arch/k6_N10_40nm.xml +++ b/openfpga/test_vpr_arch/k6_N10_40nm.xml @@ -63,7 +63,7 @@ - + diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml new file mode 100644 index 000000000..d86d7aa62 --- /dev/null +++ b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml @@ -0,0 +1,299 @@ + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml index 2c528c13c..ef9268810 100644 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml @@ -76,7 +76,7 @@ - + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml index eea76837f..bbe041562 100644 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml +++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml @@ -159,7 +159,7 @@ - + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml index 9422c3a09..850eb5450 100644 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml @@ -193,7 +193,7 @@ - + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml deleted file mode 100644 index af4612b61..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml +++ /dev/null @@ -1,1429 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml new file mode 100644 index 000000000..2c528c13c --- /dev/null +++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml new file mode 100644 index 000000000..eea76837f --- /dev/null +++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml @@ -0,0 +1,639 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml new file mode 100644 index 000000000..9422c3a09 --- /dev/null +++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml @@ -0,0 +1,734 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml similarity index 100% rename from openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_thru_channel_40nm.xml rename to openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml