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add warning to force formal_verification_top_netlist enabled

This commit is contained in:
tangxifan 2020-02-27 13:28:21 -07:00
parent 078f72320f
commit b010fc1983
1 changed files with 5 additions and 1 deletions
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4
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
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@ -2,6 +2,7 @@
* Memember functions for data structure VerilogTestbenchOption * Memember functions for data structure VerilogTestbenchOption
******************************************************************************/ ******************************************************************************/
#include "vtr_assert.h" #include "vtr_assert.h"
#include "vtr_log.h"
#include "verilog_testbench_options.h" #include "verilog_testbench_options.h"
@ -81,8 +82,11 @@ void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabl
&& (!reference_benchmark_file_path_.empty()); && (!reference_benchmark_file_path_.empty());
/* Enable print formal verification top_netlist if this is enabled */ /* Enable print formal verification top_netlist if this is enabled */
if (true == print_preconfig_top_testbench_) { if (true == print_preconfig_top_testbench_) {
if (false == print_formal_verification_top_netlist_) {
VTR_LOG_WARN("Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled\n");
print_formal_verification_top_netlist_ = true; print_formal_verification_top_netlist_ = true;
} }
}
} }
void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) { void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {