diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys
new file mode 100644
index 000000000..5697352c8
--- /dev/null
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys
@@ -0,0 +1,96 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+
+########################
+# Map multipliers
+# Inspired from synth_xilinx.cc
+#########################
+# Avoid merging any registers into DSP, reserve memory port registers first
+memory_dff
+wreduce t:$mul
+techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
+select a:mul2dsp
+setattr -unset mul2dsp
+opt_expr -fine
+wreduce
+select -clear
+chtype -set $mul t:$__soft_mul# Extract arithmetic functions
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
+alumacc
+share
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
+memory -nomap
+opt_clean
+
+#########################
+# Map flip-flops
+#########################
+techmap -map ${YOSYS_DFF_MAP_VERILOG}
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml
new file mode 100644
index 000000000..97fdacb1a
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml
@@ -0,0 +1,317 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml
new file mode 100644
index 000000000..e2ec2a3a2
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml
@@ -0,0 +1,300 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
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+
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+
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+
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+
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+
+
+
diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
new file mode 100644
index 000000000..ab976c6bb
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
@@ -0,0 +1,26 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT3_DELAY: 0.92e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.21e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+REGIN_TO_FF0_DELAY: 1.12e-9
+FF0_TO_FF1_DELAY: 0.56e-9
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v
similarity index 97%
rename from openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v
rename to openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v
index 6491d7870..9a5dfd26e 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v
@@ -60,15 +60,15 @@ endmodule
//-----------------------------
// 18-bit multiplier
//-----------------------------
-// module mult_18(
-// input [0:17] A,
-// input [0:17] B,
-// output [0:35] Y
-// );
+module mult_18(
+ input [0:17] A,
+ input [0:17] B,
+ output [0:35] Y
+);
-// assign Y = A * B;
+assign Y = A * B;
-// endmodule
+endmodule
//-----------------------------
// Native D-type flip-flop
diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v b/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v
deleted file mode 100644
index e44a98334..000000000
--- a/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module mult_18x18 (
- input [0:17] A,
- input [0:17] B,
- output [0:35] Y
-);
- parameter A_SIGNED = 0;
- parameter B_SIGNED = 0;
- parameter A_WIDTH = 0;
- parameter B_WIDTH = 0;
- parameter Y_WIDTH = 0;
-
- mult_18 #() _TECHMAP_REPLACE_ (
- .A (A),
- .B (B),
- .Y (Y) );
-
-endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/dsp_map.v
new file mode 100644
index 000000000..2ec30fccc
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/dsp_map.v
@@ -0,0 +1,41 @@
+//-----------------------------
+// 9-bit multiplier
+//-----------------------------
+module mult_9x9 (
+ input [0:8] A,
+ input [0:8] B,
+ output [0:17] Y
+);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 0;
+ parameter B_WIDTH = 0;
+ parameter Y_WIDTH = 0;
+
+ mult_9 #() _TECHMAP_REPLACE_ (
+ .A (A),
+ .B (B),
+ .Y (Y) );
+
+endmodule
+
+//-----------------------------
+// 18-bit multiplier
+//-----------------------------
+module mult_18x18 (
+ input [0:17] A,
+ input [0:17] B,
+ output [0:35] Y
+);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 0;
+ parameter B_WIDTH = 0;
+ parameter Y_WIDTH = 0;
+
+ mult_18 #() _TECHMAP_REPLACE_ (
+ .A (A),
+ .B (B),
+ .Y (Y) );
+
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v
similarity index 100%
rename from openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v
rename to openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v
similarity index 100%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v
rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt
similarity index 100%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt
rename to openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v
similarity index 100%
rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v
rename to openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml
new file mode 100644
index 000000000..8f70260b0
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml
@@ -0,0 +1,1123 @@
+
+
+
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
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+
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+
+
+ clb.clk clb.reset clb.set
+ clb.cin
+ clb.O[9:0] clb.I[19:0]
+ clb.cout clb.O[19:10] clb.I[39:20]
+
+
+
+
+
+
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+
+
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+
+
+ mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35]
+
+ mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17]
+
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+ 1 1 1 1 1
+ 1 1 1 1
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+ 235e-12
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+ 235e-12
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+ 261e-12
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diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml
new file mode 100644
index 000000000..0009de0c3
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml
@@ -0,0 +1,975 @@
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
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+ clb.clk clb.reset clb.set
+ clb.O[9:0] clb.I[19:0]
+ clb.O[19:10] clb.I[39:20]
+
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+ memory.clk
+
+ memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]
+ memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]
+
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+ mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35]
+
+ mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17]
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+ 1 1 1 1 1
+ 1 1 1 1
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