Merge branch 'dev' into documentation: resolved conflicts and add logo files
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Xifan Tang
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README.md
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README.md
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@ -1,39 +1,31 @@
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# Getting Started with OpenFPGA
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[](https://travis-ci.org/LNIS-Projects/OpenFPGA)
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[](https://openfpga.readthedocs.io/en/master/?badge=master)
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## Introduction
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The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.<br />
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## Compilation
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<<<<<<< HEAD
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Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
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=======
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Dependencies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
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>>>>>>> dev
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**Compilation steps:**
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1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it*
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2. mkdir build && cd build # *Create a folder named build in OpenPFGA repository*
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3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create Makefile in this folder using cmake*
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**Compilation Steps:**
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1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go inside it*
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2. mkdir build && cd build # *Create a folder named build in the OpenPFGA repository*
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3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create a Makefile in this folder using cmake*
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4. make # *Compile the tool and its dependencies*
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*We currently implemented OpenFPGA for:*<br />
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*1. Ubuntu 16.04*<br />
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*2. Red Hat 7.5*<br />
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*3. MacOS Mojave 10.13.4*<br /><br />
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*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.*
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*3. MacOS Mojave 10.14.4*<br /><br />
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*Please note that those were the versions for which the tool was tested. It might work with earlier versions and other distributions.*
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## Documentation
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OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
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## Tutorial
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You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them.
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Through this tutorial users can learn how to use the flow and set the dependancies.<br />
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The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords.
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## Tutorials
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You can find some tutorials in the [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.
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Through those tutorials, users can learn how to use the flow and install the different dependencies.<br />
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The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords.
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@ -215,6 +215,24 @@ SRAMs
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.. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
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Logic gates
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-----
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.. code-block:: xml
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<circuit_model type="gate" name="string" prefix="string" netlist="string" dump_explicit_port_map="true|false"/>
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<design_technology type="cmos" topology="string"/>
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<input_buffer exist="string" circuit_model_name="string"/>
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<output_buffer exist="string" circuit_model_name="string"/>
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<port type="input" prefix="string" lib_name="string" size="int"/>
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<port type="output" prefix="string" lib_name="string" size="int"/>
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</circuit_model>
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.. note:: The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users.
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.. note:: The logic functionality of a gate can be defined through the XML keyword topology. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
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.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword dump_explicit_port_map to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword lib_name.
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Multiplexers
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------------
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@ -319,14 +337,16 @@ Look-Up Tables
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.. code-block:: xml
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<circuit_model type="lut" name="string" prefix="string" is_default="int" netlist="string"/>
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<design_technology type="cmos"/>
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<lut_input_buffer exist="string" circuit_model_name="string"/>
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<design_technology type="cmos" fracturable_lut="true|false"/>
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<input_buffer exist="string" circuit_model_name="string"/>
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<output_buffer exist="string" circuit_model_name="string"/>
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<lut_input_buffer exist="string" circuit_model_name="string"/>
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<lut_intermediate_buffer exist="string" circuit_model_name="string" location_map="string"/>
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<lut_input_inverter exist="string" circuit_model_name="string"/>
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<pass_gate_logic type="string" circuit_model_name="string"/>
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<port type="input" prefix="string" size="int"/>
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<port type="output" prefix="string" size="int"/>
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<port type="sram" prefix="string" size="int"/>
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<port type="input" prefix="string" size="int" tri_state_map="----11" circuit_model_name="string"/>
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<port type="output" prefix="string" size="int" lut_frac_level="int" lut_output_mask="int"/>
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<port type="sram" prefix="string" size="int" mode_select="true|false" circuit_model_name="string" default_val="0|1"/>
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</circuit_model>
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.. note:: The SPICE netlists of LUT can be auto-generated or customized.
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@ -335,7 +355,13 @@ Look-Up Tables
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Additional design parameters for LUTs:
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* **lut_input_buffer:** Specify the buffer for the inputs of a LUT (gates of the internal multiplexer).
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* **lut_input_buffer:** Define transistor-level description for the buffer for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit.
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* **lut_input_inverter:** Define transistor-level description for the inverter for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit.
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* **lut_intermediate_buffer:** Define transistor-level description for the buffer locating at intermediate stages of internal multiplexer of a LUT. Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. To customize the location, users can define an integer array in the XML keyword location_map. For example, "-1-1-" indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT.
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Instructions of defining design parameters:
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@ -343,7 +369,9 @@ Instructions of defining design parameters:
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* **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers.
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* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
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* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask.
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* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map.
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**LUT example**
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After Width: | Height: | Size: 20 KiB |
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@ -269,6 +269,7 @@
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="on" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="on" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6"/>
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# How to build?
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## Dependancies
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## Dependencies
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OpenFPGA requires all the dependancies listed below:
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OpenFPGA requires all the following dependencies:
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- autoconf
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- automake
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- bash
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@ -40,18 +40,18 @@ OpenFPGA requires all the dependancies listed below:
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## Docker
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If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command:
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If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command:
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- docker run lnis/open_fpga:release <br />
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*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".*
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Or a container where you can build OpenFPGA yourself can be created with the following commands:
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Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands:
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- docker build . -t open_fpga
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- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash<br />
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[*docker download link*](https://www.docker.com/products/docker-desktop)
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## Building
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To build the tool you have to be in OpenFPGA folder and do:
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To build the tool you have to go in OpenFPGA folder and do:
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- mkdir build && cd build
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- cmake .. -DCMAKE_BUILD_TYPE=debug
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- make (*WARNING using docker you cannot use "make -j", errors will happen*)
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@ -1,36 +1,31 @@
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# FPGA flow
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This tutorial will help the user to understand how to use OpenFPGA flow.<br />
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During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
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# FPGA Flow
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This tutorial will help the user to understand how to use the OpenFPGA flow.<br />
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During this tutorial, we consider that the user starts in the OpenFPGA folder and we will use tips and information provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
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## Running fpga_flow.pl
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A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
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### Experiment
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cd fpga_flow<br />
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./tuto_fpga_flow.sh<br />
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### Explanation
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The *fpga_flow.pl* script takes an architecture description file (.xml), generates its netlists and generates a bitstream to implement a benchmark on the FPGA fabric and verifis its correct implementation.<br />
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When you open the perl script, you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allows us to make this tutorial generic by generating full path to the dependencies.<br />
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The second one is **fpga_flow.pl**. This script launches the OpenFPGA flow and can be used with many different [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).<br />
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There are 3 important things to observe here:
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- All the FPGA-Verilog options have been activated
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- fpga_flow.pl calls a configuration file through the "config_file" variable
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- fpga_flow.pl calls a list of benchmark to be implemented and tested through the "bench_txt" variable
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By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
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When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
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The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).<br />
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There is 3 important things to see:
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- All FPGA-Verilog options have been activated
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- fpga_flow.pl calls a configuration file through "config_file" variable
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- fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable
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### Configuration file
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In this file paths have to be full path. Relative path could lead to errors.<br />
|
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### Configuration File
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In this file, paths have to be defined as **absolute** paths as relative paths could lead to errors.<br />
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The file is organized in 3 parts:
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* **dir_path**: provides all the tools and repository path
|
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* **flow_conf**: provides information on how the flow run
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* **csv_tags**: *to complete*
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* **dir_path**: provides all the tool and repository paths
|
||||
* **flow_conf**: provides information on how the flow runs
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* **csv_tags**: *to be completed*
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While empty the file is as follow:
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When empty, the file is as follow:
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[dir_path]<br />
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script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts<br />
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|
|
@ -64,33 +59,30 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
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*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
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### Benchmark list
|
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|
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### Benchmark List
|
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The benchmark folder contains 3 sub-folders:
|
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* **Blif**: contains .blif and .act of benchmarks
|
||||
* **List**: contains all benchmark list files
|
||||
* **Verilog**: contains Verilog designs
|
||||
|
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Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**<br />
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The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:<br />
|
||||
Blif and Verilog folders are organized by folders using the name of the projects. **The folder, top module and top module file must share the same name.**<br />
|
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The benchmark list file can contain as many benchmarks as available in the same folder targetted by the "benchmark_dir" variable from the configuration file. It's written as:<br />
|
||||
top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
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|
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*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
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## Modifying flow
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Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width.
|
||||
## Modifying the Flow
|
||||
Once the dependencies are understood, the flow can be modified by changing the architecture file and the route channel width.
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|
||||
### Experiment
|
||||
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
|
||||
* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
|
||||
* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
|
||||
* replace "200" with "300" in tuto_benchmark.txt
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow
|
||||
* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
|
||||
* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
|
||||
* ./tuto_fpga_flow.sh
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||||
|
||||
### Explanation
|
||||
|
||||
With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.
|
||||
### Explanations
|
||||
With this last experiment, the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) was replaced by a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means that an 8-input fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs) is used. This architecture provides more modes for the CLB and the crossbar which is changed from a half-connected to a fully connected, implying bigger multiplexors between the CLB and LUT inputs. These requirements in term of interconnection will lead an increase in the routing channel width. Indeed, if the routing channel is too low, it could be impossible to route a benchmark or the FPGA output could be delayed.
|
||||
|
|
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|||
|
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@ -1,26 +1,20 @@
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# Tutorial introduction
|
||||
|
||||
OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.<br />
|
||||
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.<br /><br />
|
||||
These tutorials are organized as follow:
|
||||
* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
|
||||
# Tutorial Introduction
|
||||
OpenFPGA is an IP Verilog Generator allowing reliable and fast testing of homogeneous FPGA architectures.<br />
|
||||
Its main goal is to easily and efficiently generated a complete customizable FPGA and uses a semi-custom design flow.<br /><br />
|
||||
In order to help you get in touch with the software, we provide few tutorials which are organized as follow:
|
||||
* [Building the tool and his dependencies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
|
||||
* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
|
||||
* Architecture modification
|
||||
|
||||
## Folder organization
|
||||
|
||||
## Folder Organization
|
||||
OpenFPGA repository is organized as follow:
|
||||
* **abc**: open source synthesys tool
|
||||
* **ace2**: abc extension generating .act files
|
||||
* **ace2**: abc extension generating activity files (.act)
|
||||
* **vpr7_x2p**: sources of modified vpr
|
||||
* **yosys**: opensource synthesys tool
|
||||
* **fpga_flow**: scripts and dependencies to run the complete flow
|
||||
|
||||
## Tips and informations
|
||||
|
||||
Some keywords will be used during this tutorial:
|
||||
## Tips and Information
|
||||
Some keywords will be used during in the tutorials:
|
||||
* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,8 @@ enum e_spice_model_pass_gate_logic_type {
|
|||
|
||||
enum e_spice_model_gate_type {
|
||||
SPICE_MODEL_GATE_AND,
|
||||
SPICE_MODEL_GATE_OR
|
||||
SPICE_MODEL_GATE_OR,
|
||||
SPICE_MODEL_GATE_MUX2
|
||||
};
|
||||
|
||||
/* Transistor-level basic informations*/
|
||||
|
|
|
|||
|
|
@ -616,8 +616,10 @@ static void ProcessSpiceModelGate(ezxml_t Node,
|
|||
gate_info->type = SPICE_MODEL_GATE_AND;
|
||||
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"OR")) {
|
||||
gate_info->type = SPICE_MODEL_GATE_OR;
|
||||
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"MUX2")) {
|
||||
gate_info->type = SPICE_MODEL_GATE_MUX2;
|
||||
} else {
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR].\n",
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR|MUX2].\n",
|
||||
Node->line);
|
||||
exit(1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -440,7 +440,15 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
|
|||
exit(1);
|
||||
}
|
||||
/* Copy the information from found spice model to current spice model*/
|
||||
memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic));
|
||||
/* copy gate info if this is a standard cell */
|
||||
if (SPICE_MODEL_GATE == pgl_spice_model->type) {
|
||||
assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type);
|
||||
spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate));
|
||||
memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate));
|
||||
} else {
|
||||
assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type);
|
||||
memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic));
|
||||
}
|
||||
/* Recover the spice_model_name */
|
||||
spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name);
|
||||
spice_model[i].pass_gate_logic->spice_model = pgl_spice_model;
|
||||
|
|
|
|||
|
|
@ -3213,7 +3213,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
cur_num_sram,
|
||||
cur_num_sram + num_mux_conf_bits - 1);
|
||||
|
||||
fprintf(fp, "is_explicit_mappingf\n");
|
||||
fprintf(fp, "`endif\n");
|
||||
|
||||
|
||||
/* Call the MUX SPICE model */
|
||||
|
|
|
|||
|
|
@ -1104,6 +1104,19 @@ void dump_verilog_mux_basis_module(FILE* fp,
|
|||
spice_mux_model->spice_mux_arch,
|
||||
spice_mux_model->size);
|
||||
|
||||
/* Exception: if tgate is a standard cell, we skip the basis circuit generation */
|
||||
t_spice_model* tgate_spice_model = spice_mux_model->spice_model->pass_gate_logic->spice_model;
|
||||
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
|
||||
assert (SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
|
||||
/* Double check the mux structure, which should be tree-like */
|
||||
if ( SPICE_MODEL_STRUCTURE_TREE != spice_mux_model->spice_mux_arch->structure ) {
|
||||
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of Circuit model (%s) should be tree-like because it is linked to a 2:1 MUX!\n",
|
||||
__FILE__, __LINE__, spice_mux_model->spice_model->name);
|
||||
exit(1);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */
|
||||
/*
|
||||
if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) {
|
||||
|
|
@ -1115,9 +1128,9 @@ void dump_verilog_mux_basis_module(FILE* fp,
|
|||
|
||||
/* Prepare the basis subckt name:
|
||||
*/
|
||||
mux_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix);
|
||||
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix);
|
||||
|
||||
special_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix);
|
||||
special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix);
|
||||
|
||||
/* deteremine the number of inputs of basis subckt */
|
||||
num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis;
|
||||
|
|
@ -1228,41 +1241,107 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
|
|||
out_idx = j/2;
|
||||
/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
|
||||
fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
|
||||
/* Dump global ports */
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, ".in(");
|
||||
}
|
||||
/* For intermediate buffers */
|
||||
if (TRUE == inter_buf_loc[level]) {
|
||||
fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */
|
||||
/* For MUX2 standard cell */
|
||||
t_spice_model* tgate_spice_model = spice_model.pass_gate_logic->spice_model;
|
||||
/* For non-standard cells */
|
||||
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
|
||||
assert(SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
|
||||
int num_input_port = 0;
|
||||
int num_output_port = 0;
|
||||
t_spice_model_port** input_port = NULL;
|
||||
t_spice_model_port** output_port = NULL;
|
||||
|
||||
input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
|
||||
output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
|
||||
/* Quick check on the number of ports */
|
||||
assert(3 == num_input_port); /* A, B and SEL */
|
||||
assert(1 == num_output_port); /* OUT */
|
||||
|
||||
bool use_explicit_port_map;
|
||||
if ( (true == is_explicit_mapping)
|
||||
|| (TRUE == tgate_spice_model->dump_explicit_port_map) ) {
|
||||
use_explicit_port_map = true;
|
||||
}
|
||||
|
||||
/* Dump global ports */
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) {
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
if (true == use_explicit_port_map) {
|
||||
fprintf(fp, ".%s(", input_port[0]->lib_name);
|
||||
}
|
||||
/* For intermediate buffers */
|
||||
if (TRUE == inter_buf_loc[level]) {
|
||||
fprintf(fp, "mux2_l%d_in_buf[%d]", level, j); /* input0 */
|
||||
} else {
|
||||
fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */
|
||||
}
|
||||
if (true == use_explicit_port_map) {
|
||||
fprintf(fp, "), .%s(", input_port[1]->lib_name);
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
/* For intermediate buffers */
|
||||
if (TRUE == inter_buf_loc[level]) {
|
||||
fprintf(fp, "mux2_l%d_in_buf[%d]", level, nextj); /* input1 */
|
||||
} else {
|
||||
fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */
|
||||
}
|
||||
if (true == use_explicit_port_map) {
|
||||
fprintf(fp, "), .%s(", output_port[0]->lib_name);
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
|
||||
if (true == use_explicit_port_map) {
|
||||
fprintf(fp, "), .%s(", input_port[2]->lib_name);
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
|
||||
if (true == use_explicit_port_map) {
|
||||
fprintf(fp, "));\n");
|
||||
} else {
|
||||
fprintf(fp, ");\n");
|
||||
}
|
||||
} else {
|
||||
fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */
|
||||
}
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .out(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .mem(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .mem_inv(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "));\n");
|
||||
} else {
|
||||
fprintf(fp, ");\n");
|
||||
assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type);
|
||||
/* Dump global ports */
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, ".in(");
|
||||
}
|
||||
/* For intermediate buffers */
|
||||
if (TRUE == inter_buf_loc[level]) {
|
||||
fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */
|
||||
} else {
|
||||
fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */
|
||||
}
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .out(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .mem(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "), .mem_inv(");
|
||||
} else {
|
||||
fprintf(fp, ", ");
|
||||
}
|
||||
fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */
|
||||
if (true == is_explicit_mapping) {
|
||||
fprintf(fp, "));\n");
|
||||
} else {
|
||||
fprintf(fp, ");\n");
|
||||
}
|
||||
}
|
||||
/* For intermediate buffers */
|
||||
if (TRUE == inter_buf_loc[nextlevel]) {
|
||||
|
|
@ -1568,9 +1647,9 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
|
|||
char* mux_basis_subckt_name = NULL;
|
||||
char* mux_special_basis_subckt_name = NULL;
|
||||
|
||||
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
|
||||
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
|
||||
|
||||
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
|
||||
mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
|
||||
|
||||
/* Make sure we have a valid file handler*/
|
||||
if (NULL == fp) {
|
||||
|
|
@ -2077,9 +2156,9 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
|
|||
char* mux_basis_subckt_name = NULL;
|
||||
char* mux_special_basis_subckt_name = NULL;
|
||||
|
||||
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
|
||||
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
|
||||
|
||||
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
|
||||
mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
|
||||
|
||||
/* Make sure we have a valid file handler*/
|
||||
if (NULL == fp) {
|
||||
|
|
|
|||
|
|
@ -2915,6 +2915,24 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
|
|||
return subckt_name;
|
||||
}
|
||||
|
||||
/* Generate the subckt name for a MUX module/submodule */
|
||||
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
|
||||
int mux_size, char* postfix) {
|
||||
char* mux_subckt_name = NULL;
|
||||
|
||||
/* If the tgate spice model of this MUX is a MUX2 standard cell,
|
||||
* the mux_subckt name will be the name of the standard cell
|
||||
*/
|
||||
if ( SPICE_MODEL_GATE == spice_model->pass_gate_logic->spice_model->type) {
|
||||
assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type);
|
||||
mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name);
|
||||
} else {
|
||||
mux_subckt_name = generate_verilog_mux_subckt_name(spice_model, mux_size, postfix);
|
||||
}
|
||||
|
||||
return mux_subckt_name;
|
||||
}
|
||||
|
||||
|
||||
/* Generate the subckt name for a MUX module/submodule */
|
||||
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
|
||||
|
|
|
|||
|
|
@ -221,6 +221,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
|
|||
t_spice_model* mem_model,
|
||||
char* postfix);
|
||||
|
||||
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
|
||||
int mux_size, char* postfix);
|
||||
|
||||
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
|
||||
int mux_size, char* postfix);
|
||||
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
|
|||
cd -
|
||||
|
||||
# Run VPR
|
||||
#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
|
||||
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
|
||||
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
|
||||
|
||||
cd $fpga_flow_scripts
|
||||
|
|
|
|||
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Reference in New Issue