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use bus port for primitives in Verilog generator

This commit is contained in:
tangxifan 2019-06-13 16:26:58 -06:00
parent dddbbac85c
commit af1628abfe
1 changed files with 1 additions and 1 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
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@ -235,7 +235,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* assert */ /* assert */
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
/* print ports --> input ports */ /* print ports --> input ports */
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, FALSE, FALSE, TRUE); dump_verilog_pb_type_bus_ports(fp, port_prefix, 0, prim_pb_type, FALSE, TRUE);
/* IOPADs requires a specical port to output */ /* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) { if (SPICE_MODEL_IOPAD == verilog_model->type) {