diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 2154a8513..4e2d129c5 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -74,6 +74,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, fp << std::endl; print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation, + clock_port_names, std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), @@ -209,7 +210,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME))); /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist); + std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Start of testbench */ print_verilog_top_random_testbench_ports(fp, circuit_name, clock_port_names, atom_ctx, netlist_annotation); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 000879230..695d9275f 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -423,7 +423,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME)); /* Find clock ports in benchmark */ - std::vector benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist); + std::vector benchmark_clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Connect FPGA top module global ports to constant or benchmark global signals! */ print_verilog_preconfig_top_module_connect_global_ports(fp, module_manager, top_module, diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 395d80493..8d3e856c7 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -534,6 +534,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, @@ -556,6 +557,9 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, } /* TODO: Skip clocks because they are handled in another function */ + if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) { + continue; + } /* Each logical block assumes a single-width port */ BasicPort input_port(block_name, 1); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index e9a481380..61d5929c8 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -82,6 +82,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 76bc1ea49..f64558dda 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -399,6 +399,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, } print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation, + clock_port_names, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), @@ -798,7 +799,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, VTR_ASSERT(true == module_manager.valid_module_id(top_module)); /* Preparation: find all the clock ports */ - std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist); + std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.cpp b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp index d2786e88d..8d1876f90 100644 --- a/openfpga/src/utils/openfpga_atom_netlist_utils.cpp +++ b/openfpga/src/utils/openfpga_atom_netlist_utils.cpp @@ -18,14 +18,21 @@ namespace openfpga { /*************************************************************************************** * Find the names of all the atom blocks that drive clock nets + * This function will find if the block has been renamed due to contain sensitive characters + * that violates the Verilog syntax ***************************************************************************************/ -std::vector find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist) { +std::vector find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist, + const VprNetlistAnnotation& netlist_annotation) { std::vector clock_names; std::set clock_pins = find_netlist_logical_clock_drivers(atom_nlist); for (const AtomPinId& clock_pin : clock_pins) { const AtomBlockId& atom_blk = atom_nlist.port_block(atom_nlist.pin_port(clock_pin)); - clock_names.push_back(atom_nlist.block_name(atom_blk)); + std::string block_name = atom_nlist.block_name(atom_blk); + if (true == netlist_annotation.is_block_renamed(atom_blk)) { + block_name = netlist_annotation.block_name(atom_blk); + } + clock_names.push_back(block_name); } return clock_names; diff --git a/openfpga/src/utils/openfpga_atom_netlist_utils.h b/openfpga/src/utils/openfpga_atom_netlist_utils.h index 180181687..dfa5743a2 100644 --- a/openfpga/src/utils/openfpga_atom_netlist_utils.h +++ b/openfpga/src/utils/openfpga_atom_netlist_utils.h @@ -7,6 +7,7 @@ #include #include #include "atom_netlist.h" +#include "vpr_netlist_annotation.h" /******************************************************************** * Function declaration @@ -15,7 +16,8 @@ /* begin namespace openfpga */ namespace openfpga { -std::vector find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist); +std::vector find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist, + const VprNetlistAnnotation& netlist_annotation); } /* end namespace openfpga */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp index ee2a80ea6..9293c7cf6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_testbench_utils.cpp @@ -479,7 +479,6 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, /* Validate the file stream */ check_file_handler(fp); - /* Instantiate register for inputs stimulis */ print_verilog_comment(fp, std::string("----- Shared inputs -------")); for (const t_logical_block& lb : L_logical_blocks) {