From ae05871b1fbcf7b67466ad36171b4df426fc116d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 28 Feb 2021 12:19:14 -0700 Subject: [PATCH] [Script] Remove default net type from an example script; Limit it to some test cases --- openfpga_flow/openfpga_shell_scripts/example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga index 8254c3f24..18b7c97f2 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --default_net_type ${OPENFPGA_VERILOG_NET_TYPE} --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists