diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index a82b88fae..a1d3e2407 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -296,7 +296,7 @@ endmodule //End Of Module
 //           - asynchronous set which can be switched 
 //             which can be switched between active-low and active hight
 //-----------------------------------------------------
-module MULTIMODE_DFFSRQ (
+module MULTI_MODE_DFFSRQ (
   input SET, // Set input
   input RST, // Reset input
   input CK, // Clock Input