From ade8f43a368158546792d0aeaee6242e39f55325 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 10:16:55 -0700 Subject: [PATCH] [engine] Updating RRGraph Annotation and VTr --- openfpga/src/annotation/annotate_rr_graph.cpp | 6 +++--- vtr-verilog-to-routing | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 5d9dcf639..7ef690a95 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -491,8 +491,8 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx, const bool& verbose_output) { size_t count = 0; - for (const RRSwitchId& rr_switch_id : vpr_device_ctx.rr_graph.rr_switch()) { - std::string switch_name(vpr_device_ctx.rr_graph.rr_switch()[rr_switch_id].name); + for (size_t rr_switch_id = 0; rr_switch_id < vpr_device_ctx.rr_graph.rr_switch().size(); rr_switch_id++) { + std::string switch_name(vpr_device_ctx.rr_graph.rr_switch()[RRSwitchId(rr_switch_id)].name); /* Skip the delayless switch, which is only used by the edges between * - SOURCE and OPIN * - IPIN and SINK @@ -534,7 +534,7 @@ void annotate_rr_switch_circuit_models(const DeviceContext& vpr_device_ctx, } /* Now update the device annotation */ - vpr_device_annotation.add_rr_switch_circuit_model(rr_switch_id, circuit_model); + vpr_device_annotation.add_rr_switch_circuit_model(RRSwitchId(rr_switch_id), circuit_model); VTR_LOGV(verbose_output, "Binded a routing resource graph switch '%s' to circuit model '%s'\n", switch_name.c_str(), diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index bcc0fd9db..b54d4ad4f 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit bcc0fd9dbefc8649647b99525421274a538d07f4 +Subproject commit b54d4ad4f3e6bbd0e54a567be3921fdd30efed4d