diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index c87073c67..13cfb52af 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -1953,7 +1953,6 @@ void print_verilog_full_testbench_configuration_chain_bitstream(std::fstream& fp
                                                                 const bool& bit_value_to_skip,
                                                                 const ModuleManager& module_manager,
                                                                 const ModuleId& top_module,
-                                                                const BitstreamManager& bitstream_manager,
                                                                 const FabricBitstream& fabric_bitstream) {
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -2078,7 +2077,7 @@ void print_verilog_full_testbench_bitstream(std::fstream& fp,
                                                                fast_configuration, 
                                                                bit_value_to_skip,
                                                                module_manager, top_module,
-                                                               bitstream_manager, fabric_bitstream);
+                                                               fabric_bitstream);
     break;
   case CONFIG_MEM_MEMORY_BANK:
     break;