From ad881ea4dc1a43404187ba4c6159ae35d8ea324b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 18:59:25 -0600 Subject: [PATCH] [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank --- .../src/fpga_verilog/verilog_top_testbench.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 27f714957..8a5ec3721 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -136,15 +136,15 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); } @@ -173,15 +173,16 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } /********************************************************************