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[test] now bypass clock routing in default example

This commit is contained in:
tangxifan 2023-06-08 13:44:22 -07:00
parent 2934938989
commit ac31a20376
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}