From ac22ba28e451ea7ffe7b3be277f7ede6e98edcd3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 2 Jul 2020 12:26:59 -0600
Subject: [PATCH] add config protocol type information to simulation ini file

---
 openfpga/src/fpga_verilog/simulation_info_writer.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.cpp b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
index de9f5f6af..134b34f0a 100644
--- a/openfpga/src/fpga_verilog/simulation_info_writer.cpp
+++ b/openfpga/src/fpga_verilog/simulation_info_writer.cpp
@@ -78,6 +78,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
   ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
   ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
   ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
+  ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);
 
   /* Information required by UVM */
   if (CONFIG_MEM_FRAME_BASED == config_protocol_type) {