From 2ea08a0f46d9867ecaacaedcbb90fa57dca60257 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 13:59:16 -0800 Subject: [PATCH 01/20] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 254d38faa..5d41e33cc 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 254d38faa02884c9b48d6a82e18fd54d9b567d44 +Subproject commit 5d41e33cc89a34d0481550728f855252a63ac704 From 0b83ca3902200e485cf578ab07a23f96af384b03 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:00:42 -0800 Subject: [PATCH 02/20] [script] now use submodule checkout for github --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e3d23b82a..23c2cdab6 100644 --- a/Makefile +++ b/Makefile @@ -58,7 +58,7 @@ help: checkout: # Update all the submodules git submodule init - git submodule update --init --depth 1 + git submodule update --init --recursive prebuild: # Run cmake to generate Makefile under the build directory, before compilation From d78f18d235e8d0671d7529ef766bef4e5c055e18 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:11:34 -0800 Subject: [PATCH 03/20] [test] add new testcase --- .../fpga_verilog_reg_test.sh | 3 + .../rr_concat_wire/config/bus_group_gen.py | 173 +++ .../config/counter8_bus_group_task.yaml | 5 + .../config/pin_constraints_reset.xml | 7 + .../rr_concat_wire/config/task.conf | 48 + openfpga_flow/vpr_arch/README.md | 3 +- ..._adder_chain_dpram8K_dsp36_fracff_40nm.xml | 1239 +++++++++++++++++ 7 files changed, 1477 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/bus_group_gen.py create mode 100644 openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/counter8_bus_group_task.yaml create mode 100644 openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 3cad92b31..46bf5cba9 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -140,6 +140,9 @@ echo -e "Testing through channels in tileable routing"; run-task fpga_verilog/thru_channel/thru_narrow_tile $@ run-task fpga_verilog/thru_channel/thru_wide_tile $@ +echo -e "Testing wire concatation in tileable routing"; +run-task fpga_verilog/rr_concat_wire $@ + echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators"; run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none $@ run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim $@ diff --git a/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/bus_group_gen.py b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/bus_group_gen.py new file mode 100644 index 000000000..3303aaf0a --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/bus_group_gen.py @@ -0,0 +1,173 @@ +##################################################################### +# A script to create a bus group file based on an input verilog file +# The bug group file is an input required by OpenFPGA +##################################################################### +import os +from os.path import dirname, abspath +import argparse +import logging +import subprocess +import hashlib +import yaml +import pyverilog +from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer +from xml.dom import minidom + +##################################################################### +# Error codes +##################################################################### +error_codes = { + "SUCCESS": 0, + "MD5_ERROR": 1, + "OPTION_ERROR": 2, + "FILE_ERROR": 3 +} + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO); + +##################################################################### +# Generate the string for a Verilog port +##################################################################### +def gen_verilog_port_str(port_name, msb, lsb): + port_str = str(port_name) + "[" + str(msb) + ":" + str(lsb) + "]" + return port_str + +##################################################################### +# Generate the string for a flatten Verilog port +##################################################################### +def gen_flatten_verilog_port_str(port_name, pin_id): + port_str = str(port_name) + "_" + str(pin_id) + "_" + return port_str + +##################################################################### +# Parse a verilog file and collect bus port information +##################################################################### +def parse_verilog_file_bus_ports(verilog_files, top_module): + # Check if verilog file exists + verilog_file_list = [] + for verilog_f in verilog_files: + print(verilog_f) + verilog_f_abspath = os.path.abspath(verilog_f["name"]) + if not os.path.exists(verilog_f_abspath): + raise IOError("file not found: " + verilog_f_abspath) + + verilog_file_list.append(verilog_f_abspath) + + # Parse verilog file + analyzer = VerilogDataflowAnalyzer(verilog_file_list, top_module) + analyzer.generate() + # Get port information + terms = analyzer.getTerms() + # Create XML tree + xml = minidom.Document() + bus_group = xml.createElement("bus_group") + xml.appendChild(bus_group) + for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])): + logging.debug(tv.name) + logging.debug(tv.termtype) + logging.debug("[" + str(tv.lsb) + ":" + str(tv.msb) + "]") + for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])): + # Skip ports that do not belong to top module + if (top_module != str(tv.name).split(".")[-2]): + continue + port_name = str(tv.name).split(".")[-1] + + # Skip minus lsb or msb, which are in don't care set + if (("Minus" == str(tv.lsb)) or ("Minus" == str(tv.msb))): + continue + port_lsb = int(str(tv.lsb)) + port_msb = int(str(tv.msb)) + # Only care input and outports + if ((not ("Input" in tv.termtype)) and (not ("Output" in tv.termtype))): + continue + # Only care bus (msb - lsb > 0) + if (abs(port_lsb - port_msb) == 0): + continue + # Reaching here, this is a bus port we need + # Get the second part of the name, which is the port name + cur_bus = xml.createElement("bus") + cur_bus.setAttribute("name", gen_verilog_port_str(port_name, port_msb, port_lsb)) + # Get if this is little endian or not + cur_bus.setAttribute("big_endian", "false") + if (port_lsb > port_msb): + cur_bus.setAttribute("big_endian", "true") + bus_group.appendChild(cur_bus) + # Add all the pins + for ipin in range(min([port_msb, port_lsb]), max([port_msb, port_lsb]) + 1): + cur_pin = xml.createElement("pin") + cur_pin.setAttribute('id', str(ipin)) + cur_pin.setAttribute('name', gen_flatten_verilog_port_str(port_name, ipin)) + cur_bus.appendChild(cur_pin) + + return xml, bus_group + +##################################################################### +# Generate bus group files with a given task list +##################################################################### +def generate_bus_group_files(task_db): + # Iterate over all the tasks + for verilog_fname in task_db.keys(): + space_limit = 120 + log_str = "Parsing verilog file: " + top_module_name = task_db[verilog_fname]["top_module"] + logging_space = "." * (space_limit - len(log_str) - len(top_module_name)) + logging.info(log_str + top_module_name) + xml, bus_group_data = parse_verilog_file_bus_ports(task_db[verilog_fname]["source"], top_module_name) + logging.info(log_str + top_module_name + logging_space + "Done") + # Write bus ports to an XML file + bus_group_frelname = task_db[verilog_fname]["bus_group_file"] + bus_group_fname = os.path.abspath(bus_group_frelname) + log_str = "Writing bus group file:" + logging_space = "." * (space_limit - len(log_str) - len(bus_group_frelname)) + logging.info(log_str + bus_group_frelname) + xml_str = xml.toprettyxml(indent="\t") + with open(bus_group_fname, "w") as bus_group_f: + bus_group_f.write(xml_str) + logging.info(log_str + bus_group_frelname + logging_space + "Done") + +##################################################################### +# Read task list from a yaml file +##################################################################### +def read_yaml_to_task_database(yaml_filename): + task_db = {} + with open(yaml_filename, 'r') as stream: + try: + task_db = yaml.load(stream, Loader=yaml.FullLoader) + logging.info("Found " + str(len(task_db)) + " tasks to create symbolic links") + except yaml.YAMLError as exc: + logging.error(exc) + exit(error_codes["FILE_ERROR"]); + + return task_db + +##################################################################### +# Write result database to a yaml file +##################################################################### +def write_result_database_to_yaml(result_db, yaml_filename): + with open(yaml_filename, 'w') as yaml_file: + yaml.dump(result_db, yaml_file, default_flow_style=False) + +##################################################################### +# Main function +##################################################################### +if __name__ == '__main__': + # Execute when the module is not initialized from an import statement + + # Parse the options and apply sanity checks + parser = argparse.ArgumentParser(description='Create bus group files for Verilog inputs') + parser.add_argument('--task_list', + required=True, + help='Configuration file in YAML format which contains a list of input Verilog and output bus group files') + args = parser.parse_args() + + # Create a database for tasks + task_db = {} + task_db = read_yaml_to_task_database(args.task_list) + + # Generate links based on the task list in database + generate_bus_group_files(task_db) + logging.info("Created " + str(len(task_db)) + " bus group files") + exit(error_codes["SUCCESS"]) diff --git a/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/counter8_bus_group_task.yaml b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/counter8_bus_group_task.yaml new file mode 100644 index 000000000..2c0a81258 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/counter8_bus_group_task.yaml @@ -0,0 +1,5 @@ +counter8: + source: + - name: counter_output_verilog.v + top_module: counter + bus_group_file: bus_group.xml diff --git a/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/pin_constraints_reset.xml b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/pin_constraints_reset.xml new file mode 100644 index 000000000..abcf209f6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/task.conf new file mode 100644 index 000000000..39335966e --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/rr_concat_wire/config/task.conf @@ -0,0 +1,48 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/auto_bus_group_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_verilog_port_mapping=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v +bench_yosys_bram_map_rules_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt +bench_yosys_bram_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v +bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36 +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys + +bench0_top = counter +bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml +bench0_openfpga_bus_group_file=bus_group.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md index cbec4f286..65f3c3d55 100644 --- a/openfpga_flow/vpr_arch/README.md +++ b/openfpga_flow/vpr_arch/README.md @@ -5,8 +5,9 @@ Please reveal the following architecture features in the names to help quickly s * The keyword 'frac' is to specify if fracturable LUT is used or not. * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). - N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. -- tileable: If the routing architecture is tileable or not. +- tileable: If the routing architecture is tileable or not. * The keyword 'IO' specifies if the I/O tile is tileable or not + * The keyword 'ConcatWire' specifies if the routing wires can be continued in the same direction or not. For example, L4 -> L1 - fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered - adder\_chain: If hard adder/carry chain is used inside CLBs - register\_chain: If shift register chain is used inside CLBs diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml new file mode 100644 index 000000000..c9dc5e65e --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml @@ -0,0 +1,1239 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset clb.set + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + + + mult_36.b[0:9] mult_36.b[10:35] mult_36.out[36:71] + + mult_36.a[0:9] mult_36.a[10:35] mult_36.out[0:35] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 1b8748abb491750037375e187c3c26ea419481d8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 14:21:34 -0800 Subject: [PATCH 04/20] [core] update vtr --- ...tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml | 2 +- vtr-verilog-to-routing | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml index c9dc5e65e..370341554 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml @@ -302,7 +302,7 @@ - + diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 5d41e33cc..229e43e30 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 5d41e33cc89a34d0481550728f855252a63ac704 +Subproject commit 229e43e30bd7a99bf34239179ad957ca6e00f8da From 59a5db5f26b6b195bb73506d3e1fe4168b326f77 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:02:04 -0800 Subject: [PATCH 05/20] [lib] update vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 229e43e30..a668e3938 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 229e43e30bd7a99bf34239179ad957ca6e00f8da +Subproject commit a668e393859ecbc85a113d54800f0ffd2272bbca From 2006a33a4960f069cfdfc93841a7ce7f5539a7bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:11:52 -0800 Subject: [PATCH 06/20] [lib] upgrade vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index a668e3938..320ab25a5 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit a668e393859ecbc85a113d54800f0ffd2272bbca +Subproject commit 320ab25a5a8f8f7559f27cb87f8feafa8dca0903 From a014a99e75a8137e26030ee61fb37e77174a4656 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:31:38 -0800 Subject: [PATCH 07/20] [lib] upgrade vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 320ab25a5..7b5d47bd1 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 320ab25a5a8f8f7559f27cb87f8feafa8dca0903 +Subproject commit 7b5d47bd1ddbb3843c6638f89f2faa531bd31dad From 70d502d09486f3c843c2c367ff430d824fcb6c0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:34:20 -0800 Subject: [PATCH 08/20] [lib] upgrade vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 7b5d47bd1..d65c0546a 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 7b5d47bd1ddbb3843c6638f89f2faa531bd31dad +Subproject commit d65c0546ac34f53f0713d841004a003aa1131e9f From f2f66028e30f75eb997324e60dedbb4f91261e4f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:37:35 -0800 Subject: [PATCH 09/20] [lib] upgrade vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index d65c0546a..2818f1b0c 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit d65c0546ac34f53f0713d841004a003aa1131e9f +Subproject commit 2818f1b0c64d206826d57a6b32d234a81d0c6fdd From 5a80250aa36277cd9e7c5aa4c9b7e6c719bf460a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 15:38:39 -0800 Subject: [PATCH 10/20] [lib] upgrade vtr --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 2818f1b0c..eb9722851 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 2818f1b0c64d206826d57a6b32d234a81d0c6fdd +Subproject commit eb9722851bd3de03df7fb9ace5bdfb9cb078ca83 From 32772d1bd980fa6ce1a11d0264f9772bcb66de25 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 16:13:09 -0800 Subject: [PATCH 11/20] [ci] remove gcc-7 support --- .github/workflows/build.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e0cd7bc71..360870213 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -76,9 +76,6 @@ jobs: fail-fast: false matrix: config: - - name: "Build Compatibility: GCC-7 (Ubuntu 20.04)" - cc: gcc-7 - cxx: g++-7 - name: "Build Compatibility: GCC-8 (Ubuntu 20.04)" cc: gcc-8 cxx: g++-8 From e94e7c7c75a4294a21ff601bbb95d2eacb706826 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 21:13:42 -0800 Subject: [PATCH 12/20] [ci] now change to use gcc-11 build image --- .github/workflows/build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 360870213..01d945a01 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -134,7 +134,7 @@ jobs: run: ccache -s - name: Upload artifact uses: actions/upload-artifact@v2 - if: ${{ matrix.config.cc == 'gcc-8'}} + if: ${{ matrix.config.cc == 'gcc-11'}} with: name: openfpga path: | @@ -438,7 +438,7 @@ jobs: chmod +x build/yosys/bin/yosys-config chmod +x build/yosys/bin/yosys-filterlib chmod +x build/yosys/bin/yosys-smtbmc - - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 20.04) shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact @@ -482,7 +482,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v3 - - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 20.04) shell: bash run: | bash .github/workflows/install_dependencies_run.sh From 5cbe698dd1f19bd71fc27afa9bf1223df8ed26e8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 13 Nov 2023 22:59:27 -0800 Subject: [PATCH 13/20] [ci] switch to use gcc-9 when running reg tests --- .github/workflows/build.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 01d945a01..2e8a8246c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -134,7 +134,7 @@ jobs: run: ccache -s - name: Upload artifact uses: actions/upload-artifact@v2 - if: ${{ matrix.config.cc == 'gcc-11'}} + if: ${{ matrix.config.cc == 'gcc-9'}} with: name: openfpga path: | @@ -438,7 +438,7 @@ jobs: chmod +x build/yosys/bin/yosys-config chmod +x build/yosys/bin/yosys-filterlib chmod +x build/yosys/bin/yosys-smtbmc - - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) shell: bash run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs - name: Upload artifact @@ -482,7 +482,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v3 - - name: ${{matrix.config.name}}_GCC-11_(Ubuntu 20.04) + - name: ${{matrix.config.name}}_GCC-9_(Ubuntu 20.04) shell: bash run: | bash .github/workflows/install_dependencies_run.sh From 59d086a27ff904d3be8cf8348a949de2d5e45538 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:25:45 -0800 Subject: [PATCH 14/20] [test] try to keep the golden inputs --- openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml index 3c32dbc99..7a354232c 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -67,7 +67,7 @@ - + From 913434b70d91e6d2d74b07f74f8209d5681271d3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:28:57 -0800 Subject: [PATCH 15/20] [test] fixed the bug that golden netlists are modified --- openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml index 7a354232c..33a4f4e56 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -67,7 +67,7 @@ - + From d1082841053154fd73e1c03a6115ee1535ff6e4c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:31:07 -0800 Subject: [PATCH 16/20] [test] update arch to keep golden outputs --- openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml index b3b4110a3..2946ce80a 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml @@ -103,7 +103,7 @@ - + From 0b473e345452e655c26b4275c12cb7a6f31b440c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:35:26 -0800 Subject: [PATCH 17/20] [test] fixed the bug in single-mode lut testcase --- .../tasks/fpga_verilog/lut_design/single_mode/config/task.conf | 2 +- openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf index 989f8e09a..ae5896549 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=vpr_blif openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 +openfpga_vpr_device_layout=auto [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml index 4706bb30f..634dacd64 100644 --- a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml @@ -67,7 +67,7 @@ - + From dff03e7993f1f70aa1ec4c8b4e5eac4cd0d53aae Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:45:02 -0800 Subject: [PATCH 18/20] [test] enable missing options in the arch used by benchmark sweeping tests --- .../k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml | 2 +- ..._frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml | 2 +- ...frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml index b2eea07af..d0750f9ac 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml @@ -234,7 +234,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml index 0ae64adda..428a0e617 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml @@ -302,7 +302,7 @@ - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml index 1190e3624..1b6f2760b 100755 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml @@ -146,7 +146,7 @@ - + From e9673916b2ae875efc5412cdcdf58afca28c94e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 09:56:57 -0800 Subject: [PATCH 19/20] [doc] add figures for new options in tileable rr graph --- .../arch_lang/figures/concat_pass_wire.svg | 574 +++++++++++++++++ .../manual/arch_lang/figures/concat_wire.svg | 580 +++++++++++++++++ .../arch_lang/figures/opin2all_sides.svg | 592 ++++++++++++++++++ 3 files changed, 1746 insertions(+) create mode 100644 docs/source/manual/arch_lang/figures/concat_pass_wire.svg create mode 100644 docs/source/manual/arch_lang/figures/concat_wire.svg create mode 100644 docs/source/manual/arch_lang/figures/opin2all_sides.svg diff --git a/docs/source/manual/arch_lang/figures/concat_pass_wire.svg b/docs/source/manual/arch_lang/figures/concat_pass_wire.svg new file mode 100644 index 000000000..ccebac06b --- /dev/null +++ b/docs/source/manual/arch_lang/figures/concat_pass_wire.svg @@ -0,0 +1,574 @@ + + + + + + + + + + + + + + + + + concat_pass_wire + + base + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + wires + + + + + + + + + + + + + + + legend + + + (a) + + + + + + + + + + + + + Starting routing tracks + + + + + + + + + Ending routing tracks + + + + + + + + + Passing routing tracks + + + + + + + + + Output pin of blocks + + + + + (b) + + + + + diff --git a/docs/source/manual/arch_lang/figures/concat_wire.svg b/docs/source/manual/arch_lang/figures/concat_wire.svg new file mode 100644 index 000000000..bb01dd6d5 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/concat_wire.svg @@ -0,0 +1,580 @@ + + + + + + + + + + + + + + + + + concat_wire + + base + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + wires + + + + + + + + + + + + + + + + + + + + + legend + + + (a) + + + + + + + + + + + + + Starting routing tracks + + + + + + + + + Ending routing tracks + + + + + + + + + Passing routing tracks + + + + + + + + + Output pin of blocks + + + + + (b) + + + + + diff --git a/docs/source/manual/arch_lang/figures/opin2all_sides.svg b/docs/source/manual/arch_lang/figures/opin2all_sides.svg new file mode 100644 index 000000000..dff4b1222 --- /dev/null +++ b/docs/source/manual/arch_lang/figures/opin2all_sides.svg @@ -0,0 +1,592 @@ + + + + + + + + + + + + + + + + + opin2all_sides + + base + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + wires + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + legend + + + (a) + + + + + + + + + + + + + Starting routing tracks + + + + + + + + + Ending routing tracks + + + + + + + + + Passing routing tracks + + + + + + + + + Output pin of blocks + + + + + (b) + + + + + From b79703fc8bdb6d7fed5d6599eb4817cfde8c1148 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Nov 2023 10:10:41 -0800 Subject: [PATCH 20/20] [doc] comment on new options --- .../manual/arch_lang/addon_vpr_syntax.rst | 49 ++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst index ef93be938..b2c88992c 100644 --- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst +++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst @@ -88,11 +88,58 @@ Layout .. warning:: Do NOT enable ``shrink_boundary`` if you are not using the tileable routing resource graph generator! +.. option:: opin2all_sides="" + + Allow each output pin of a programmable block to drive the routing tracks on all the sides of its adjacent switch block (see an illustrative example in :numref:`fig_opin2all_sides`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. + By default, it is ``false``. + + .. _fig_opin2all_sides: + + .. figure:: ./figures/opin2all_sides.svg + :width: 100% + :alt: Impact of opin2all_sides + + Impact on routing architecture when the opin-to-all-sides: (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``opin2all_sides`` if you are not using the tileable routing resource graph generator! + +.. option:: concat_wire="" + + In each switch block, allow each routing track which ends to drive another routing track on the opposite side, as such a wire can be continued in the same direction (see an illustrative example in :numref:`fig_concat_wire`). In other words, routing wires can be concatenated in the same direction across an FPGA fabric. This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. + By default, it is ``false``. + + .. _fig_concat_wire: + + .. figure:: ./figures/concat_wire.svg + :width: 100% + :alt: Impact of concat_wire + + Impact on routing architecture when the wire concatenation: (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``concat_wire`` if you are not using the tileable routing resource graph generator! + +.. option:: concat_pass_wire="" + + In each switch block, allow each routing track which passes to drive another routing track on the opposite side, as such a pass wire can be continued in the same direction (see an illustrative example in :numref:`fig_concat_pass_wire`). This can improve the routability of an FPGA fabric with an increase in the sizes of routing multiplexers in each switch block. + By default, it is ``false``. + + .. warning:: Please enable this option if you are looking for device support which is created by any release which is before v1.1.541!!! + + .. _fig_concat_wire: + + .. figure:: ./figures/concat_pass_wire.svg + :width: 100% + :alt: Impact of concat_pass_wire + + Impact on routing architecture when the pass wire concatenation: (a) disabled; (b) enabled. + + .. warning:: Do NOT enable ``concat_pass_wire`` if you are not using the tileable routing resource graph generator! + A quick example to show tileable routing is enabled, other options, e.g., through channels are disabled: .. code-block:: xml - + Switch Block