fix critical bugs in routing submodules
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01e075377d
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aaf8d23971
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@ -2223,7 +2223,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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int side_num_reserved_conf_bits = count_verilog_switch_box_side_reserved_conf_bits(cur_sram_orgz_info, rr_sb, side_manager.get_side(), seg_ids[iseg]);
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/* Cache the sram counter */
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cur_sram_msb += side_num_conf_bits - 1;
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cur_sram_msb = cur_sram_lsb + side_num_conf_bits - 1;
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/* Instanciate the subckt*/
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fprintf(fp,
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@ -2248,13 +2248,13 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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fprintf(fp, ",\n");
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}
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/* Normal sram ports */
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dump_verilog_sram_ports(fp, cur_sram_orgz_info,
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cur_sram_lsb,
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cur_sram_msb,
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VERILOG_PORT_CONKT);
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dump_verilog_sram_local_ports(fp, cur_sram_orgz_info,
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cur_sram_lsb,
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cur_sram_msb,
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VERILOG_PORT_CONKT);
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/* Dump ports only visible during formal verification*/
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if (0 < num_conf_bits) {
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if (0 < side_num_conf_bits) {
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fprintf(fp, "\n");
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fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag);
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fprintf(fp, ",\n");
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@ -2271,6 +2271,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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cur_sram_lsb = cur_sram_msb + 1;
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}
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}
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/* checker */
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assert(cur_sram_msb == cur_num_sram + num_conf_bits - 1);
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fprintf(fp, "endmodule\n");
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