From aac74d91632ee9210ae46cb7e642d56ecf324fb0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 9 Oct 2021 18:46:20 -0700 Subject: [PATCH] [Engine] Bug fix --- .../fabric/build_top_module_memory_bank.cpp | 54 ++++++++------- .../memory_bank_shift_register_banks.cpp | 68 ++++++++++--------- .../fabric/memory_bank_shift_register_banks.h | 42 +++++++----- 3 files changed, 90 insertions(+), 74 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp index 88062d5b2..5ed22c70c 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.cpp +++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp @@ -1284,14 +1284,6 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_bank_bls(ModuleMa BasicPort sr_module_blwl_port_info = module_manager.module_port(sr_bank_module, sr_module_blwl_port); for (const BasicPort& src_port : sr_banks.bl_shift_register_bank_source_ports(config_region, bank)) { - size_t child_id = sr_banks.bl_shift_register_bank_sink_child_id(config_region, bank, src_port); - ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; - size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; - - /* Find the BL port */ - ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); - BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); - VTR_ASSERT(1 == src_port.get_width()); /* Create net */ ModuleNetId net = create_module_source_pin_net(module_manager, top_module, @@ -1300,10 +1292,20 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_bank_bls(ModuleMa src_port.pins()[0]); VTR_ASSERT(ModuleNetId::INVALID() != net); - /* Add net sink */ - size_t sink_child_pin_id = sr_banks.bl_shift_register_bank_sink_child_pin_id(config_region, bank, src_port); - module_manager.add_module_net_sink(top_module, net, - child_module, child_instance, child_blwl_port, sink_child_pin_id); + for (size_t ichild = 0; ichild < sr_banks.bl_shift_register_bank_sink_child_ids(config_region, bank, src_port).size(); ++ichild) { + size_t child_id = sr_banks.bl_shift_register_bank_sink_child_ids(config_region, bank, src_port)[ichild]; + ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; + + /* Find the BL port */ + ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); + BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); + + /* Add net sink */ + size_t sink_child_pin_id = sr_banks.bl_shift_register_bank_sink_child_pin_ids(config_region, bank, src_port)[ichild]; + module_manager.add_module_net_sink(top_module, net, + child_module, child_instance, child_blwl_port, sink_child_pin_id); + } } } } @@ -1359,14 +1361,6 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_bank_wls(ModuleMa BasicPort sr_module_blwl_port_info = module_manager.module_port(sr_bank_module, sr_module_blwl_port); for (const BasicPort& src_port : sr_banks.wl_shift_register_bank_source_ports(config_region, bank)) { - size_t child_id = sr_banks.wl_shift_register_bank_sink_child_id(config_region, bank, src_port); - ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; - size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; - - /* Find the BL port */ - ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); - BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); - VTR_ASSERT(1 == src_port.get_width()); /* Create net */ ModuleNetId net = create_module_source_pin_net(module_manager, top_module, @@ -1375,10 +1369,20 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_bank_wls(ModuleMa src_port.pins()[0]); VTR_ASSERT(ModuleNetId::INVALID() != net); - /* Add net sink */ - size_t sink_child_pin_id = sr_banks.wl_shift_register_bank_sink_child_pin_id(config_region, bank, src_port); - module_manager.add_module_net_sink(top_module, net, - child_module, child_instance, child_blwl_port, sink_child_pin_id); + for (size_t ichild = 0; ichild < sr_banks.wl_shift_register_bank_sink_child_ids(config_region, bank, src_port).size(); ++ichild) { + size_t child_id = sr_banks.wl_shift_register_bank_sink_child_ids(config_region, bank, src_port)[ichild]; + ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id]; + size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id]; + + /* Find the BL port */ + ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); + BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); + + /* Add net sink */ + size_t sink_child_pin_id = sr_banks.wl_shift_register_bank_sink_child_pin_ids(config_region, bank, src_port)[ichild]; + module_manager.add_module_net_sink(top_module, net, + child_module, child_instance, child_blwl_port, sink_child_pin_id); + } } } } @@ -1501,6 +1505,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module BasicPort src_bl_port(std::string(MEMORY_BL_PORT_NAME), bl_pin_id, bl_pin_id); FabricBitLineBankId sr_bank = sr_banks.find_bl_shift_register_bank_id(config_region, src_bl_port); BasicPort sr_bank_port = sr_banks.find_bl_shift_register_bank_data_port(config_region, src_bl_port); + VTR_ASSERT(sr_bank_port.is_valid()); sr_banks.add_bl_shift_register_bank_sink_node(config_region, sr_bank, sr_bank_port, child_id, sink_bl_pin); @@ -1594,6 +1599,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module FabricWordLineBankId sr_bank = sr_banks.find_wl_shift_register_bank_id(config_region, src_wl_port); BasicPort sr_bank_port = sr_banks.find_wl_shift_register_bank_data_port(config_region, src_wl_port); + VTR_ASSERT(sr_bank_port.is_valid()); sr_banks.add_wl_shift_register_bank_sink_node(config_region, sr_bank, sr_bank_port, child_id, sink_wl_pin); diff --git a/openfpga/src/fabric/memory_bank_shift_register_banks.cpp b/openfpga/src/fabric/memory_bank_shift_register_banks.cpp index a593f2831..0a506b9ae 100644 --- a/openfpga/src/fabric/memory_bank_shift_register_banks.cpp +++ b/openfpga/src/fabric/memory_bank_shift_register_banks.cpp @@ -124,24 +124,24 @@ BasicPort MemoryBankShiftRegisterBanks::find_bl_shift_register_bank_data_port(co return result->second; } -size_t MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_child_id(const ConfigRegionId& region_id, - const FabricBitLineBankId& bank_id, - const BasicPort& src_port) const { +std::vector MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_child_ids(const ConfigRegionId& region_id, + const FabricBitLineBankId& bank_id, + const BasicPort& src_port) const { VTR_ASSERT(valid_bl_bank_id(region_id, bank_id)); auto result = bl_bank_sink_child_ids_[region_id][bank_id].find(src_port); if (result == bl_bank_sink_child_ids_[region_id][bank_id].end()) { - return -1; /* Not found, return an invalid value */ + return std::vector(); /* Not found, return an empty list */ } return result->second; } -size_t MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_child_pin_id(const ConfigRegionId& region_id, - const FabricBitLineBankId& bank_id, - const BasicPort& src_port) const { +std::vector MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_child_pin_ids(const ConfigRegionId& region_id, + const FabricBitLineBankId& bank_id, + const BasicPort& src_port) const { VTR_ASSERT(valid_bl_bank_id(region_id, bank_id)); auto result = bl_bank_sink_child_pin_ids_[region_id][bank_id].find(src_port); if (result == bl_bank_sink_child_pin_ids_[region_id][bank_id].end()) { - return -1; /* Not found, return an invalid value */ + return std::vector(); /* Not found, return an empty list */ } return result->second; } @@ -151,9 +151,11 @@ std::vector MemoryBankShiftRegisterBanks::bl_shift_register_bank_sour VTR_ASSERT(valid_bl_bank_id(region_id, bank_id)); std::vector src_ports; + size_t cur_pin =0; for (const BasicPort& wide_port : bl_bank_data_ports(region_id, bank_id)) { - for (const size_t& pin : wide_port.pins()) { - src_ports.push_back(BasicPort(wide_port.get_name(), pin, pin)); + for (size_t ipin = 0; ipin < wide_port.pins().size(); ++ipin) { + src_ports.push_back(BasicPort(std::string(MEMORY_BL_PORT_NAME), cur_pin, cur_pin)); + cur_pin++; } } @@ -250,8 +252,8 @@ void MemoryBankShiftRegisterBanks::add_bl_shift_register_bank_sink_node(const Co const size_t& sink_child_id, const size_t& sink_child_pin_id) { VTR_ASSERT(valid_bl_bank_id(region, bank)); - bl_bank_sink_child_ids_[region][bank][src_port] = sink_child_id; - bl_bank_sink_child_pin_ids_[region][bank][src_port] = sink_child_pin_id; + bl_bank_sink_child_ids_[region][bank][src_port].push_back(sink_child_id); + bl_bank_sink_child_pin_ids_[region][bank][src_port].push_back(sink_child_pin_id); } void MemoryBankShiftRegisterBanks::add_wl_shift_register_bank_sink_node(const ConfigRegionId& region, @@ -260,8 +262,8 @@ void MemoryBankShiftRegisterBanks::add_wl_shift_register_bank_sink_node(const Co const size_t& sink_child_id, const size_t& sink_child_pin_id) { VTR_ASSERT(valid_wl_bank_id(region, bank)); - wl_bank_sink_child_ids_[region][bank][src_port] = sink_child_id; - wl_bank_sink_child_pin_ids_[region][bank][src_port] = sink_child_pin_id; + wl_bank_sink_child_ids_[region][bank][src_port].push_back(sink_child_id); + wl_bank_sink_child_pin_ids_[region][bank][src_port].push_back(sink_child_pin_id); } void MemoryBankShiftRegisterBanks::reserve_bl_shift_register_banks(const ConfigRegionId& region_id, const size_t& num_banks) { @@ -364,13 +366,13 @@ void MemoryBankShiftRegisterBanks::add_data_port_to_wl_shift_register_bank(const is_wl_bank_dirty_ = true; } -size_t MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_child_id(const ConfigRegionId& region_id, - const FabricWordLineBankId& bank_id, - const BasicPort& src_port) const { +std::vector MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_child_ids(const ConfigRegionId& region_id, + const FabricWordLineBankId& bank_id, + const BasicPort& src_port) const { VTR_ASSERT(valid_wl_bank_id(region_id, bank_id)); auto result = wl_bank_sink_child_ids_[region_id][bank_id].find(src_port); if (result == wl_bank_sink_child_ids_[region_id][bank_id].end()) { - return -1; /* Not found, return an invalid value */ + return std::vector(); /* Not found, return an empty list */ } return result->second; } @@ -387,13 +389,13 @@ size_t MemoryBankShiftRegisterBanks::wl_shift_register_bank_instance(const Confi return wl_bank_instances_[region_id][bank_id]; } -size_t MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_child_pin_id(const ConfigRegionId& region_id, - const FabricWordLineBankId& bank_id, - const BasicPort& src_port) const { +std::vector MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_child_pin_ids(const ConfigRegionId& region_id, + const FabricWordLineBankId& bank_id, + const BasicPort& src_port) const { VTR_ASSERT(valid_wl_bank_id(region_id, bank_id)); auto result = wl_bank_sink_child_pin_ids_[region_id][bank_id].find(src_port); if (result == wl_bank_sink_child_pin_ids_[region_id][bank_id].end()) { - return -1; /* Not found, return an invalid value */ + return std::vector(); /* Not found, return an empty list */ } return result->second; } @@ -403,9 +405,11 @@ std::vector MemoryBankShiftRegisterBanks::wl_shift_register_bank_sour VTR_ASSERT(valid_wl_bank_id(region_id, bank_id)); std::vector src_ports; + size_t cur_pin = 0; for (const BasicPort& wide_port : wl_bank_data_ports(region_id, bank_id)) { - for (const size_t& pin : wide_port.pins()) { - src_ports.push_back(BasicPort(wide_port.get_name(), pin, pin)); + for (size_t ipin = 0; ipin < wide_port.pins().size(); ++ipin) { + src_ports.push_back(BasicPort(std::string(MEMORY_WL_PORT_NAME), cur_pin, cur_pin)); + cur_pin++; } } @@ -438,17 +442,17 @@ void MemoryBankShiftRegisterBanks::build_bl_port_fast_lookup() const { bl_ports_to_sr_bank_ids_.resize(bl_bank_data_ports_.size()); bl_ports_to_sr_bank_ports_.resize(bl_bank_data_ports_.size()); for (const auto& region : bl_bank_data_ports_) { - size_t bl_index = 0; for (const auto& bank : region) { + size_t cur_pin = 0; for (const auto& port : bank) { - for (const auto& pin : port.pins()) { + for (const size_t& bl_index : port.pins()) { BasicPort bl_port(std::string(MEMORY_BL_PORT_NAME), bl_index, bl_index); - BasicPort sr_bl_port(std::string(MEMORY_BL_PORT_NAME), pin, pin); + BasicPort sr_bl_port(std::string(MEMORY_BL_PORT_NAME), cur_pin, cur_pin); ConfigRegionId region_id = ConfigRegionId(®ion - &bl_bank_data_ports_[ConfigRegionId(0)]); FabricBitLineBankId bank_id = FabricBitLineBankId(&bank - ®ion[FabricBitLineBankId(0)]); bl_ports_to_sr_bank_ids_[region_id][bl_port] = bank_id; bl_ports_to_sr_bank_ports_[region_id][bl_port] = sr_bl_port; - bl_index++; + cur_pin++; } } } @@ -461,17 +465,17 @@ void MemoryBankShiftRegisterBanks::build_wl_port_fast_lookup() const { wl_ports_to_sr_bank_ids_.resize(wl_bank_data_ports_.size()); wl_ports_to_sr_bank_ports_.resize(wl_bank_data_ports_.size()); for (const auto& region : wl_bank_data_ports_) { - size_t wl_index = 0; for (const auto& bank : region) { + size_t cur_pin = 0; for (const auto& port : bank) { - for (const auto& pin : port.pins()) { + for (const size_t& wl_index : port.pins()) { BasicPort wl_port(std::string(MEMORY_WL_PORT_NAME), wl_index, wl_index); - BasicPort sr_wl_port(std::string(MEMORY_WL_PORT_NAME), pin, pin); + BasicPort sr_wl_port(std::string(MEMORY_WL_PORT_NAME), cur_pin, cur_pin); ConfigRegionId region_id = ConfigRegionId(®ion - &wl_bank_data_ports_[ConfigRegionId(0)]); FabricWordLineBankId bank_id = FabricWordLineBankId(&bank - ®ion[FabricWordLineBankId(0)]); wl_ports_to_sr_bank_ids_[region_id][wl_port] = bank_id; wl_ports_to_sr_bank_ports_[region_id][wl_port] = sr_wl_port; - wl_index++; + cur_pin++; } } } diff --git a/openfpga/src/fabric/memory_bank_shift_register_banks.h b/openfpga/src/fabric/memory_bank_shift_register_banks.h index 9de627b58..fd226ded0 100644 --- a/openfpga/src/fabric/memory_bank_shift_register_banks.h +++ b/openfpga/src/fabric/memory_bank_shift_register_banks.h @@ -52,17 +52,20 @@ class MemoryBankShiftRegisterBanks { size_t bl_shift_register_bank_instance(const ConfigRegionId& region_id, const FabricBitLineBankId& bank_id) const; - /** @brief return the child id at top-level module to which a data port (1-bit) of a BL shift register bank is connected to */ - size_t bl_shift_register_bank_sink_child_id(const ConfigRegionId& region_id, - const FabricBitLineBankId& bank_id, - const BasicPort& src_port) const; + /** @brief return the child ids at top-level module to which a data port (1-bit) of a BL shift register bank is connected to + * @note a BL may drive multiple children (children on the same column share the same BLs) + */ + std::vector bl_shift_register_bank_sink_child_ids(const ConfigRegionId& region_id, + const FabricBitLineBankId& bank_id, + const BasicPort& src_port) const; /** @brief return the child pin id of the child module at top-level module * to which a data port (1-bit) of a BL shift register bank is connected to + * @note a BL may drive multiple children (children on the same column share the same BLs) */ - size_t bl_shift_register_bank_sink_child_pin_id(const ConfigRegionId& region_id, - const FabricBitLineBankId& bank_id, - const BasicPort& src_port) const; + std::vector bl_shift_register_bank_sink_child_pin_ids(const ConfigRegionId& region_id, + const FabricBitLineBankId& bank_id, + const BasicPort& src_port) const; /** @brief Return a list of single-bit ports which are the data ports of a BL shift register bank */ std::vector bl_shift_register_bank_source_ports(const ConfigRegionId& region_id, @@ -94,17 +97,20 @@ class MemoryBankShiftRegisterBanks { size_t wl_shift_register_bank_instance(const ConfigRegionId& region_id, const FabricWordLineBankId& bank_id) const; - /** @brief return the child id at top-level module to which a data port (1-bit) of a WL shift register bank is connected to */ - size_t wl_shift_register_bank_sink_child_id(const ConfigRegionId& region, - const FabricWordLineBankId& bank_id, - const BasicPort& src_port) const; + /** @brief return the child id at top-level module to which a data port (1-bit) of a WL shift register bank is connected to + * @note a WL may drive multiple children (children on the same row share the same WLs) + */ + std::vector wl_shift_register_bank_sink_child_ids(const ConfigRegionId& region, + const FabricWordLineBankId& bank_id, + const BasicPort& src_port) const; /** @brief return the child pin id of the child module at top-level module * to which a data port (1-bit) of a WL shift register bank is connected to + * @note a WL may drive multiple children (children on the same row share the same WLs) */ - size_t wl_shift_register_bank_sink_child_pin_id(const ConfigRegionId& region, - const FabricWordLineBankId& bank_id, - const BasicPort& src_port) const; + std::vector wl_shift_register_bank_sink_child_pin_ids(const ConfigRegionId& region, + const FabricWordLineBankId& bank_id, + const BasicPort& src_port) const; /** @brief Return a list of single-bit ports which are the data ports of a WL shift register bank */ std::vector wl_shift_register_bank_source_ports(const ConfigRegionId& region_id, @@ -199,16 +205,16 @@ class MemoryBankShiftRegisterBanks { vtr::vector>> bl_bank_data_ports_; vtr::vector> bl_bank_modules_; vtr::vector> bl_bank_instances_; - vtr::vector>> bl_bank_sink_child_ids_; - vtr::vector>> bl_bank_sink_child_pin_ids_; + vtr::vector>>> bl_bank_sink_child_ids_; + vtr::vector>>> bl_bank_sink_child_pin_ids_; /* General information about the WL shift register bank */ vtr::vector> wl_bank_ids_; vtr::vector>> wl_bank_data_ports_; vtr::vector> wl_bank_modules_; vtr::vector> wl_bank_instances_; - vtr::vector>> wl_bank_sink_child_ids_; - vtr::vector>> wl_bank_sink_child_pin_ids_; + vtr::vector>>> wl_bank_sink_child_ids_; + vtr::vector>>> wl_bank_sink_child_pin_ids_; /* Fast look-up: given a BL/Wl port, e.g., bl[i], find out * - the shift register bank id