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fixed bugs in configure pb_rr_graph and dependence on testbenches

This commit is contained in:
tangxifan 2019-08-16 18:20:30 -06:00
parent e456b6f905
commit aa7f3bef7f
2 changed files with 14 additions and 5 deletions
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14
vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_pb_rr_graph.c
View File

@ -231,16 +231,22 @@ void connect_one_rr_node_for_phy_pb_graph_node(INP t_pb_graph_pin* cur_pb_graph_
assert(rr_node_type == local_rr_graph->rr_node[cur_rr_node_index].type); assert(rr_node_type == local_rr_graph->rr_node[cur_rr_node_index].type);
switch (rr_node_type) { switch (rr_node_type) {
case INTRA_CLUSTER_EDGE: case INTRA_CLUSTER_EDGE: {
/* Check out all the output_edges belonging to the same physical mode */ /* Check out all the output_edges belonging to the same physical mode */
int cur_edge = 0;
for (iedge = 0; iedge < cur_pb_graph_pin->num_output_edges; iedge++) { for (iedge = 0; iedge < cur_pb_graph_pin->num_output_edges; iedge++) {
check_pb_graph_edge(*(cur_pb_graph_pin->output_edges[iedge])); check_pb_graph_edge(*(cur_pb_graph_pin->output_edges[iedge]));
if (phy_mode_index == cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) { /* Bypass fan-outs that are not in the physical mode */
local_rr_graph->rr_node[cur_rr_node_index].edges[iedge] = cur_pb_graph_pin->output_edges[iedge]->output_pins[0]->rr_node_index_physical_pb; if (phy_mode_index != cur_pb_graph_pin->output_edges[iedge]->interconnect->parent_mode_index) {
local_rr_graph->rr_node[cur_rr_node_index].switches[iedge] = local_rr_graph->delayless_switch_index; continue;
} }
assert ( cur_edge < local_rr_graph->rr_node[cur_rr_node_index].num_edges);
local_rr_graph->rr_node[cur_rr_node_index].edges[cur_edge] = cur_pb_graph_pin->output_edges[iedge]->output_pins[0]->rr_node_index_physical_pb;
local_rr_graph->rr_node[cur_rr_node_index].switches[cur_edge] = local_rr_graph->delayless_switch_index;
cur_edge++;
} }
break; break;
}
case SOURCE: case SOURCE:
/* Connect the SOURCE nodes to the rr_node of cur_pb_graph_pin */ /* Connect the SOURCE nodes to the rr_node of cur_pb_graph_pin */
assert (0 == local_rr_graph->rr_node[cur_rr_node_index].fan_in); assert (0 == local_rr_graph->rr_node[cur_rr_node_index].fan_in);

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -310,7 +310,10 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
sram_verilog_orgz_info->type); sram_verilog_orgz_info->type);
/* Force enable bitstream generator when we need to output Verilog top testbench*/ /* Force enable bitstream generator when we need to output Verilog top testbench*/
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench) { if ((TRUE == vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream)
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_top_testbench)
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_autocheck_top_testbench)
|| (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_formal_verification_top_netlist)) {
vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream = TRUE; vpr_setup.FPGA_SPICE_Opts.BitstreamGenOpts.gen_bitstream = TRUE;
} }